Add KEY_HOLDER implementation for TYPE2
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src/Tests/Type2_key_holder.vhd
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783
src/Tests/Type2_key_holder.vhd
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.rtps_package.all;
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use work.rtps_config_package.all;
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use work.Type2_package.all;
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architecture TYPE2 of key_holder is
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--*****COMPONENT DECLARATION*****
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component md5_calculator is
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port (
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clk : in std_logic;
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reset : in std_logic;
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start : in std_logic;
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ack : out std_logic;
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data_in : in std_logic_vector(7 downto 0);
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valid_in : in std_logic;
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ready_in : out std_logic;
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last_word_in : in std_logic;
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hash_out : out std_logic_vector(127 downto 0);
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done : out std_logic
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);
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end component;
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--*****TYPE DECLARATION*****
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-- FSM states. Explained below in detail
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type STAGE_TYPE is (IDLE,START_MD5_CALCULATION,GET_PAYLOAD_HEADER,FETCH,ALIGN_IN_STREAM,SKIP_PAYLOAD,DECODE_PAYLOAD,PUSH,ALIGN_OUT_STREAM,SERIALIZE_KEY,GET_KEY_HASH,PUSH_KEY_HASH);
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-- ###GENERATED START###
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type DECODE_STAGE_TYPE is (GET_ID,GET_TESTSEQUENCE_LENGTH,GET_TESTSEQUENCE_TESTARRAY,GET_TESTSEQUENCE_TESTCHAR,GET_TESTSEQUENCE_TESTWCHAR,GET_TESTSEQUENCE_TESTLONGLONG,GET_TESTSEQUENCE_TESTLONGDOUBLE,TESTSEQUENCE_MEMBER_END,GET_OPTIONAL_HEADER);
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type ENCODE_STAGE_TYPE is (WRITE_ID,WRITE_TESTSEQUENCE_LENGTH,WRITE_TESTSEQUENCE_TESTARRAY,TESTSEQUENCE_MEMBER_END);
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type TESTSEQUENCE_TESTARRAY_ADDR_TYPE is array (0 to TESTSEQUENCE_MAX_DEPTH-1) of std_logic_vector(TESTSEQUENCE_TESTARRAY_ADDR_WIDTH-1 downto 0);
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type TESTSEQUENCE_TESTARRAY_DATA_TYPE is array (0 to TESTSEQUENCE_MAX_DEPTH-1) of std_logic_vector(CDR_OCTET_WIDTH-1 downto 0);
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-- ###GENERATED END###
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-- *MAIN PROCESS*
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signal stage, stage_next : STAGE_TYPE := IDLE;
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signal cnt, cnt_next : natural range 0 to 5 := 0;
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signal endian_flag, endian_flag_next : std_logic := '0';
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signal last_word_in_latch, last_word_in_latch_next : std_logic := '0';
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signal decode_error_latch, decode_error_latch_next : std_logic := '0';
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signal align_offset, align_offset_next : unsigned(MAX_ALIGN_OFFSET_WIDTH-1 downto 0) := (others => '0');
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signal target_align, target_align_next : ALIGN_TYPE := ALIGN_1;
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signal data_in_latch, data_in_latch_next : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
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signal data_out_latch, data_out_latch_next : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
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signal optional, optional_next : std_logic := '0';
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signal abort_mem : std_logic := '0';
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signal opcode_latch, opcode_latch_next : KEY_HOLDER_OPCODE_TYPE := NOP;
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signal cnt_2, cnt_2_next : natural range 0 to (WORD_WIDTH/BYTE_WIDTH)-1 := 0;
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signal align_op, align_op_next : std_logic := '0';
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signal finalize_payload, finalize_payload_next : std_logic := '0';
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signal ready_in_sig : std_logic := '0';
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-- ###GENERATED START###
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signal start_md5, ack_md5, done_md5 : std_logic := '0';
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signal data_in_md5 : std_logic_vector(BYTE_WIDTH-1 downto 0) := (others => '0');
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signal valid_in_md5, ready_in_md5, last_word_in_md5 : std_logic := '0';
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signal hash_out_md5 : std_logic_vector(KEY_HASH_WIDTH-1 downto 0) := (others => '0');
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signal key_hash, key_hash_next : KEY_HASH_TYPE := HANDLE_NIL;
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signal decode_stage, decode_stage_next : DECODE_STAGE_TYPE := GET_ID;
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signal encode_stage, encode_stage_next : ENCODE_STAGE_TYPE := WRITE_ID;
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signal return_stage, return_stage_next : DECODE_STAGE_TYPE := GET_ID;
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signal id_latch, id_latch_next : std_logic_vector(CDR_LONG_WIDTH-1 downto 0) := (others => '0');
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signal TestSequence_cnt, TestSequence_cnt_next : natural range 0 to TESTSEQUENCE_MAX_DEPTH-1 := 0;
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signal TestSequence_len_latch, TestSequence_len_latch_next : unsigned(TESTSEQUENCE_ADDR_WIDTH-1 downto 0) := (others => '0');
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signal TestSequence_addr_latch, TestSequence_addr_latch_next : std_logic_vector(TESTSEQUENCE_ADDR_WIDTH-1 downto 0) := (others => '0');
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signal TestSequence_TestArray_cnt, TestSequence_TestArray_cnt_next : natural range 0 to TESTSEQUENCE_TESTARRAY_MAX_DEPTH-1 := 0;
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-- TestSequence_TestArray_mem SIGNALS
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signal TestSequence_TestArray_mem_addr : TESTSEQUENCE_TESTARRAY_ADDR_TYPE := (others => (others => '0'));
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signal TestSequence_TestArray_mem_read, TestSequence_TestArray_mem_ready_in, TestSequence_TestArray_mem_ready_out, TestSequence_TestArray_mem_valid_in, TestSequence_TestArray_mem_valid_out : std_logic_vector(0 to TESTSEQUENCE_TESTARRAY_MAX_DEPTH-1) := (others => '0');
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signal TestSequence_TestArray_mem_data_in, TestSequence_TestArray_mem_data_out : TESTSEQUENCE_TESTARRAY_DATA_TYPE := (others => (others => '0'));
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-- ###GENERATED END###
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--*****ALIAS DECLARATION*****
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alias representation_id : std_logic_vector(PAYLOAD_REPRESENTATION_ID_WIDTH-1 downto 0) is data_in(WORD_WIDTH-1 downto WORD_WIDTH-PAYLOAD_REPRESENTATION_ID_WIDTH);
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alias representation_options : std_logic_vector(PAYLOAD_REPRESENTATION_ID_WIDTH-1 downto 0) is data_in(PAYLOAD_REPRESENTATION_OPTIONS_WIDTH-1 downto 0);
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alias parameter_id : std_logic_vector(PARAMETER_ID_WIDTH-1 downto 0) is data_in_latch(WORD_WIDTH-1 downto WORD_WIDTH-PARAMETER_ID_WIDTH);
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alias parameter_length : std_logic_vector(PARAMETER_LENGTH_WIDTH-1 downto 0) is data_in_latch(PARAMETER_LENGTH_WIDTH-1 downto 0);
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begin
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-- ###GENERATED START###
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TestSequence_TestArray_gen : for i in 0 to TESTSEQUENCE_MAX_DEPTH-1 generate
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begin
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TestSequence_TestArray_mem : entity work.mem_ctrl(arch)
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generic map (
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ADDR_WIDTH => TESTSEQUENCE_TESTARRAY_ADDR_WIDTH,
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DATA_WIDTH => CDR_OCTET_WIDTH,
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MEMORY_DEPTH => TESTSEQUENCE_TESTARRAY_MAX_DEPTH,
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MAX_BURST_LENGTH => 1
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)
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port map (
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clk => clk,
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reset => reset or abort_mem,
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addr => TestSequence_TestArray_mem_addr(i),
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read => TestSequence_TestArray_mem_read(i),
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ready_in => TestSequence_TestArray_mem_ready_in(i),
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valid_in => TestSequence_TestArray_mem_valid_in(i),
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data_in => TestSequence_TestArray_mem_data_in(i),
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ready_out => TestSequence_TestArray_mem_ready_out(i),
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valid_out => TestSequence_TestArray_mem_valid_out(i),
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data_out => TestSequence_TestArray_mem_data_out(i)
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);
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end generate;
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md5_calculator_inst : md5_calculator
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port map (
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clk => clk,
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reset => reset,
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start => start_md5,
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ack => ack_md5,
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data_in => data_in_md5,
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valid_in => valid_in_md5,
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ready_in => ready_in_md5,
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last_word_in => last_word_in_md5,
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hash_out => hash_out_md5,
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done => done_md5
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);
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-- ###GENERATED END###
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decode_error <= decode_error_latch;
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ready_in <= ready_in_sig;
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main_prc : process (all)
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variable tmp_length : unsigned(WORD_WIDTH-1 downto 0) := (others => '0');
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begin
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-- DEFAULT
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stage_next <= stage;
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decode_stage_next <= decode_stage;
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encode_stage_next <= encode_stage;
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return_stage_next <= return_stage;
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cnt_next <= cnt;
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cnt_2_next <= cnt_2;
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endian_flag_next <= endian_flag;
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last_word_in_latch_next <= last_word_in_latch;
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decode_error_latch_next <= decode_error_latch;
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align_offset_next <= align_offset;
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target_align_next <= target_align;
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optional_next <= optional;
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data_in_latch_next <= data_in_latch;
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opcode_latch_next <= opcode_latch;
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key_hash_next <= key_hash;
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align_op_next <= align_op;
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finalize_payload_next <= finalize_payload;
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abort_mem <= '0';
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ack <= '0';
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ready_in_sig <= '0';
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last_word_out <= '0';
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valid_out <= '0';
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data_out <= (others => '0');
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-- ###GENERATED START###
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id_latch_next <= id_latch;
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TestSequence_len_latch_next <= TestSequence_len_latch;
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TestSequence_cnt_next <= TestSequence_cnt;
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TestSequence_TestArray_cnt_next <= TestSequence_TestArray_cnt;
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TestSequence_addr_latch_next <= TestSequence_addr_latch;
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TestSequence_TestArray_mem_addr <= (others => (others => '0'));
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TestSequence_TestArray_mem_read <= (others => '0');
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TestSequence_TestArray_mem_valid_in <= (others => '0');
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TestSequence_TestArray_mem_ready_out <= (others => '0');
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TestSequence_TestArray_mem_data_in <= (others => (others => '0'));
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-- ###GENERATED END###
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-- Last Word Latch Setter
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if (last_word_in = '1') then
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last_word_in_latch_next <= '1';
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end if;
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case (stage) is
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when IDLE =>
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-- Latch Opcode
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opcode_latch_next <= opcode;
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if (start = '1') then
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case (opcode) is
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when PUSH_DATA =>
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ack <= '1';
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stage_next <= GET_PAYLOAD_HEADER;
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-- Reset
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key_hash_next <= HANDLE_NIL;
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when PUSH_SERIALIZED_KEY =>
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ack <= '1';
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-- Serialized Key is in PLAIN_CDR2 Big Endian encoding
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endian_flag_next <= '0';
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stage_next <= FETCH;
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decode_stage_next <= GET_ID;
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when READ_KEY_HASH =>
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ack <= '1';
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-- Key Hash not calculated
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if (key_hash = HANDLE_NIL) then
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-- DES: If MAX_TYPE2_KEY_HOLDER_SIZE is <= 16 we don't have to calculate the md5 (or even instantiate the md5_calculator at all)
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stage_next <= START_MD5_CALCULATION;
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else
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stage_next <= PUSH_KEY_HASH;
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cnt_next <= 0;
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end if;
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when READ_SERIALIZED_KEY =>
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ack <= '1';
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stage_next <= SERIALIZE_KEY;
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encode_stage_next <= WRITE_ID;
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when others =>
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null;
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end case;
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end if;
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when START_MD5_CALCULATION =>
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start_md5 <= '1';
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if (ack_md5 = '1') then
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stage_next <= SERIALIZE_KEY;
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encode_stage_next <= WRITE_ID;
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end if;
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when GET_PAYLOAD_HEADER =>
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-- TODO: Latch Offset from Options Field?
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ready_in_sig <= '1';
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-- Input Guard
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if (valid_in = '1') then
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case (representation_id) is
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when CDR_BE =>
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endian_flag_next <= '0';
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stage_next <= FETCH;
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decode_stage_next <= GET_ID;
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-- Alignment Reset
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align_offset_next <= (others => '0');
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-- Initial Fetch
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when CDR_LE =>
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endian_flag_next <= '1';
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stage_next <= FETCH;
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decode_stage_next <= GET_ID;
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-- Alignment Reset
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align_offset_next <= (others => '0');
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when others =>
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-- Unknown Payload Encoding
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stage_next <= SKIP_PAYLOAD;
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decode_error_latch_next <= '1';
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end case;
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end if;
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when FETCH =>
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ready_in_sig <= '1';
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-- Input Guard
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if (valid_in = '1') then
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data_in_latch_next <= data_in;
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-- Alignment Operation in progress
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if (align_op = '1') then
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stage_next <= ALIGN_IN_STREAM;
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-- Reset
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align_op_next <= '0';
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else
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stage_next <= DECODE_PAYLOAD;
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end if;
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end if;
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when ALIGN_IN_STREAM =>
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-- Target Stream Alignment reached
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if (check_align(align_offset, target_align)) then
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-- DONE
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stage_next <= DECODE_PAYLOAD;
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else
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align_offset_next <= align_offset + 1;
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-- Need to fetch new Input Word
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if (align_offset(1 downto 0) = "11") then
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align_op_next <= '1';
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stage_next <= FETCH;
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end if;
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end if;
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when SKIP_PAYLOAD =>
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if (last_word_in_latch = '0' and last_word_in = '0') then
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-- Skip Read
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ready_in_sig <= '1';
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else
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stage_next <= IDLE;
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-- Reset
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last_word_in_latch_next <= '0';
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end if;
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when DECODE_PAYLOAD =>
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-- ###GENERATED START###
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case (decode_stage) is
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when GET_ID =>
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-- ALIGN GUARD
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-- DES: If ALIGN_8 is used, we have to to check the latched opcode and use ALIGN_4 if PUSH_SERIALIZED_KEY (since it uses PLAIN_CDR2 encoding)
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if (not check_align(align_offset, ALIGN_4)) then
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target_align_next <= ALIGN_4;
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stage_next <= ALIGN_IN_STREAM;
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else
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id_latch_next <= endian_swap(endian_flag, data_in_latch);
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align_offset_next <= align_offset + 4;
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stage_next <= FETCH;
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-- Next Member
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decode_stage_next <= GET_TESTSEQUENCE_LENGTH;
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end if;
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when GET_TESTSEQUENCE_LENGTH =>
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-- ALIGN GUARD
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if (not check_align(align_offset, ALIGN_4)) then
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target_align_next <= ALIGN_4;
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stage_next <= ALIGN_IN_STREAM;
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else
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tmp_length := unsigned(endian_swap(endian_flag, data_in_latch));
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align_offset_next <= align_offset + 4;
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stage_next <= FETCH;
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-- Empty Sequence
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if (tmp_length = 0) then
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-- Next Member
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stage_next <= SKIP_PAYLOAD;
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else
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decode_stage_next <= GET_TESTSEQUENCE_TESTARRAY;
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TestSequence_len_latch_next <= resize(tmp_length, TestSequence_len_latch_next'length);
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TestSequence_cnt_next <= 0;
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-- DES: For array types the _cnt has to be initialized in the previous member stage
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TestSequence_TestArray_cnt_next <= 0;
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end if;
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end if;
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when GET_TESTSEQUENCE_TESTARRAY =>
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-- ALIGN GUARD
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if (not check_align(align_offset, ALIGN_1)) then
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target_align_next <= ALIGN_1;
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stage_next <= ALIGN_IN_STREAM;
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else
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TestSequence_TestArray_mem_addr(TestSequence_cnt) <= std_logic_vector(to_unsigned(TestSequence_TestArray_cnt,TestSequence_TestArray_mem_addr'length));
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TestSequence_TestArray_mem_data_in(TestSequence_cnt) <= endian_swap(endian_flag, get_sub_vector(data_in_latch, to_integer(align_offset(1 downto 0)), CDR_OCTET_WIDTH, TRUE));
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TestSequence_TestArray_mem_valid_in(TestSequence_cnt) <= '1';
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-- Memory Operation Guard
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if (TestSequence_TestArray_mem_ready_in(TestSequence_cnt) = '1') then
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align_offset_next <= align_offset + 1;
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-- All Elements processed
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if (TestSequence_TestArray_cnt = TESTSEQUENCE_TESTARRAY_MAX_DEPTH-1) then
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-- DES: The decoding stages are used for both PUSH_DATA and PUSH_SERIALIZED_KEY.
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-- We us the latched opcode to differentiate between them.
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if (opcode_latch = READ_SERIALIZED_KEY) then
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decode_stage_next <= TESTSEQUENCE_MEMBER_END;
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else
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decode_stage_next <= GET_TESTSEQUENCE_TESTCHAR;
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end if;
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else
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TestSequence_TestArray_cnt_next <= TestSequence_TestArray_cnt + 1;
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end if;
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-- DES: Needed for ALIGN_1
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-- Need to fetch next Word
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if(align_offset(1 downto 0) = "11") then
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stage_next <= FETCH;
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end if;
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end if;
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end if;
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when GET_TESTSEQUENCE_TESTCHAR =>
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-- ALIGN GUARD
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if (not check_align(align_offset, ALIGN_1)) then
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target_align_next <= ALIGN_1;
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stage_next <= ALIGN_IN_STREAM;
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else
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align_offset_next <= align_offset + 1;
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decode_stage_next <= GET_TESTSEQUENCE_TESTWCHAR;
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-- Need to fetch next Word
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if(align_offset(1 downto 0) = "11") then
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stage_next <= FETCH;
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end if;
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end if;
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when GET_TESTSEQUENCE_TESTWCHAR =>
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-- ALIGN GUARD
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if (not check_align(align_offset, ALIGN_2)) then
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target_align_next <= ALIGN_2;
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stage_next <= ALIGN_IN_STREAM;
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else
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align_offset_next <= align_offset + 2;
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decode_stage_next <= GET_TESTSEQUENCE_TESTLONGLONG;
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cnt_next <= 0;
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-- DES: Needed for ALIGN_2
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-- Need to fetch next Word
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if(align_offset(1) = '1') then
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stage_next <= FETCH;
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end if;
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end if;
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when GET_TESTSEQUENCE_TESTLONGLONG =>
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-- ALIGN GUARD
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if (not check_align(align_offset, ALIGN_8)) then
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target_align_next <= ALIGN_8;
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stage_next <= ALIGN_IN_STREAM;
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else
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case (cnt) is
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-- Double Word 1/2
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when 0 =>
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stage_next <= FETCH;
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cnt_next <= cnt + 1;
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-- Double Word 2/2
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when 1 =>
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stage_next <= FETCH;
|
||||
cnt_next <= cnt + 1;
|
||||
-- Push Double Word
|
||||
when 2 =>
|
||||
align_offset_next <= align_offset + 8;
|
||||
decode_stage_next <= GET_OPTIONAL_HEADER;
|
||||
return_stage_next <= GET_TESTSEQUENCE_TESTLONGDOUBLE;
|
||||
cnt_next <= 0;
|
||||
when others =>
|
||||
null;
|
||||
end case;
|
||||
end if;
|
||||
when GET_TESTSEQUENCE_TESTLONGDOUBLE =>
|
||||
-- Optional Omitted
|
||||
if (optional = '0') then
|
||||
decode_stage_next <= TESTSEQUENCE_MEMBER_END;
|
||||
-- ALIGN GUARD
|
||||
elsif (not check_align(align_offset, ALIGN_8)) then
|
||||
target_align_next <= ALIGN_8;
|
||||
stage_next <= ALIGN_IN_STREAM;
|
||||
else
|
||||
case (cnt) is
|
||||
-- Quad Word 1/4
|
||||
when 0 =>
|
||||
stage_next <= FETCH;
|
||||
cnt_next <= cnt + 1;
|
||||
-- Quad Word 2/4
|
||||
when 1 =>
|
||||
stage_next <= FETCH;
|
||||
cnt_next <= cnt + 1;
|
||||
-- Quad Word 3/4
|
||||
when 2 =>
|
||||
stage_next <= FETCH;
|
||||
cnt_next <= cnt + 1;
|
||||
-- Quad Word 4/4
|
||||
when 3 =>
|
||||
stage_next <= FETCH;
|
||||
cnt_next <= cnt + 1;
|
||||
-- Push Quad Word
|
||||
when 4 =>
|
||||
align_offset_next <= align_offset + 16;
|
||||
decode_stage_next <= TESTSEQUENCE_MEMBER_END;
|
||||
when others =>
|
||||
null;
|
||||
end case;
|
||||
end if;
|
||||
-- DES: If the elements of an array/sequence are of a complex/nested type, the array/sequence iteration check is done in a seperate *_MEMBER_END stage.
|
||||
when TESTSEQUENCE_MEMBER_END =>
|
||||
-- All Elements processed
|
||||
if (TestSequence_cnt = TestSequence_len_latch-1) then
|
||||
-- Next Member
|
||||
stage_next <= SKIP_PAYLOAD;
|
||||
else
|
||||
TestSequence_cnt_next <= TestSequence_cnt + 1;
|
||||
decode_stage_next <= GET_TESTSEQUENCE_TESTARRAY;
|
||||
TestSequence_TestArray_cnt_next <= 0;
|
||||
end if;
|
||||
when GET_OPTIONAL_HEADER =>
|
||||
-- ALIGN GUARD
|
||||
if (not check_align(align_offset, ALIGN_4)) then
|
||||
target_align_next <= ALIGN_4;
|
||||
stage_next <= ALIGN_IN_STREAM;
|
||||
else
|
||||
case (cnt) is
|
||||
-- Optional Member Header
|
||||
when 0 =>
|
||||
-- Extended Parameter Header
|
||||
if (endian_swap(endian_flag,parameter_id) = PID_EXTENDED) then
|
||||
cnt_next <= cnt + 1;
|
||||
stage_next <= FETCH;
|
||||
else
|
||||
stage_next <= FETCH;
|
||||
decode_stage_next <= return_stage;
|
||||
cnt_next <= 0;
|
||||
-- Alignment Reset
|
||||
align_offset_next <= (others => '0');
|
||||
|
||||
-- Optional omitted
|
||||
if(endian_swap(endian_flag,parameter_length) = (parameter_length'reverse_range => '0')) then
|
||||
optional_next <= '0';
|
||||
else
|
||||
optional_next <= '1';
|
||||
end if;
|
||||
end if;
|
||||
-- eMemberHeader
|
||||
when 1 =>
|
||||
-- Ignore Parameter ID
|
||||
cnt_next <= cnt + 1;
|
||||
stage_next <= FETCH;
|
||||
-- Llength
|
||||
when 2 =>
|
||||
stage_next <= FETCH;
|
||||
decode_stage_next <= return_stage;
|
||||
cnt_next <= 0;
|
||||
-- Alignment Reset
|
||||
align_offset_next <= (others => '0');
|
||||
|
||||
-- Optional omitted
|
||||
if(endian_swap(endian_flag, data_in) = (data_in'reverse_range => '0')) then
|
||||
optional_next <= '0';
|
||||
else
|
||||
optional_next <= '1';
|
||||
end if;
|
||||
when others =>
|
||||
null;
|
||||
end case;
|
||||
end if;
|
||||
when others =>
|
||||
null;
|
||||
end case;
|
||||
-- ###GENERATED END###
|
||||
when PUSH =>
|
||||
-- Push to MD5 Calculator
|
||||
if (opcode_latch = READ_KEY_HASH) then
|
||||
-- Mark Last Word
|
||||
if (finalize_payload = '1' and cnt_2 = to_integer(unsigned(align_offset(1 downto 0)))) then
|
||||
last_word_out <= '1';
|
||||
end if;
|
||||
|
||||
valid_in_md5 <= '1';
|
||||
data_in_md5 <= get_sub_vector(data_out_latch, cnt_2, BYTE_WIDTH, TRUE);
|
||||
-- Output Guard
|
||||
if (ready_in_md5 = '1') then
|
||||
-- Last Byte
|
||||
if ((finalize_payload = '1' and cnt_2 = to_integer(unsigned(align_offset(1 downto 0)))) or cnt_2 = (WORD_WIDTH/BYTE_WIDTH)-1) then
|
||||
-- Reset
|
||||
cnt_2_next <= 0;
|
||||
-- Alignment Operation in process
|
||||
if (align_op = '1') then
|
||||
stage_next <= ALIGN_OUT_STREAM;
|
||||
-- Reset
|
||||
align_op_next <= '0';
|
||||
-- DONE
|
||||
elsif (finalize_payload = '1') then
|
||||
stage_next <= GET_KEY_HASH;
|
||||
-- Reset
|
||||
finalize_payload_next <= '0';
|
||||
else
|
||||
stage_next <= SERIALIZE_KEY;
|
||||
end if;
|
||||
else
|
||||
cnt_2_next <= cnt_2 + 1;
|
||||
end if;
|
||||
end if;
|
||||
else
|
||||
-- Mark Last Word
|
||||
if (finalize_payload = '1') then
|
||||
last_word_out <= '1';
|
||||
end if;
|
||||
|
||||
valid_out <= '1';
|
||||
data_out <= data_out_latch;
|
||||
-- Output Guard
|
||||
if (ready_out = '1') then
|
||||
-- NOTE: Ensures all padding is zero.
|
||||
data_out_latch_next <= (others => '0');
|
||||
-- Alignment Operation in process
|
||||
if (align_op = '1') then
|
||||
stage_next <= ALIGN_OUT_STREAM;
|
||||
-- Reset
|
||||
align_op_next <= '0';
|
||||
-- DONE
|
||||
elsif (finalize_payload = '1') then
|
||||
finalize_payload_next <= '0';
|
||||
stage_next <= IDLE;
|
||||
else
|
||||
stage_next <= SERIALIZE_KEY;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
when ALIGN_OUT_STREAM =>
|
||||
-- Target Stream Alignment reached
|
||||
if (check_align(align_offset, target_align)) then
|
||||
-- DONE
|
||||
stage_next <= SERIALIZE_KEY;
|
||||
else
|
||||
align_offset_next <= align_offset + 1;
|
||||
-- Need to push Word
|
||||
if (align_offset(1 downto 0) = "11") then
|
||||
align_op_next <= '1';
|
||||
stage_next <= PUSH;
|
||||
end if;
|
||||
end if;
|
||||
when SERIALIZE_KEY =>
|
||||
-- ###GENERATED START###
|
||||
case (encode_stage) is
|
||||
when WRITE_ID =>
|
||||
-- ALIGN GUARD
|
||||
if (not check_align(align_offset, ALIGN_4)) then
|
||||
target_align_next <= ALIGN_4;
|
||||
stage_next <= ALIGN_OUT_STREAM;
|
||||
else
|
||||
data_out_latch_next <= id_latch;
|
||||
align_offset_next <= align_offset + 4;
|
||||
stage_next <= PUSH;
|
||||
-- Next Member
|
||||
encode_stage_next <= WRITE_TESTSEQUENCE_LENGTH;
|
||||
end if;
|
||||
when WRITE_TESTSEQUENCE_LENGTH =>
|
||||
-- ALIGN GUARD
|
||||
if (not check_align(align_offset, ALIGN_4)) then
|
||||
target_align_next <= ALIGN_4;
|
||||
stage_next <= ALIGN_OUT_STREAM;
|
||||
else
|
||||
data_out_latch_next <= std_logic_vector(resize(TestSequence_len_latch,WORD_WIDTH));
|
||||
align_offset_next <= align_offset + 4;
|
||||
stage_next <= PUSH;
|
||||
|
||||
-- Empty Sequence
|
||||
if (unsigned(TestSequence_len_latch) = 0) then
|
||||
-- DONE
|
||||
stage_next <= PUSH;
|
||||
finalize_payload_next <= '1';
|
||||
else
|
||||
encode_stage_next <= WRITE_TESTSEQUENCE_TESTARRAY;
|
||||
cnt_next <= 0;
|
||||
TestSequence_cnt_next <= 0;
|
||||
-- DES: For array types the _cnt has to be initialized in the previous member stage
|
||||
TestSequence_TestArray_cnt_next <= 0;
|
||||
end if;
|
||||
end if;
|
||||
when WRITE_TESTSEQUENCE_TESTARRAY =>
|
||||
-- ALIGN GUARD
|
||||
if (not check_align(align_offset, ALIGN_1)) then
|
||||
target_align_next <= ALIGN_1;
|
||||
stage_next <= ALIGN_OUT_STREAM;
|
||||
else
|
||||
case (cnt) is
|
||||
-- GET
|
||||
when 0 =>
|
||||
TestSequence_TestArray_mem_addr(TestSequence_cnt) <= std_logic_vector(to_unsigned(TestSequence_TestArray_cnt,TestSequence_TestArray_mem_addr'length));
|
||||
TestSequence_TestArray_mem_valid_in(TestSequence_cnt) <= '1';
|
||||
TestSequence_TestArray_mem_read(TestSequence_cnt) <= '1';
|
||||
-- Memory Operation Guard
|
||||
if (TestSequence_TestArray_mem_ready_in(TestSequence_cnt) = '1') then
|
||||
cnt_next <= cnt + 1;
|
||||
end if;
|
||||
-- WRITE
|
||||
when 1 =>
|
||||
TestSequence_TestArray_mem_ready_out(TestSequence_cnt) <= '1';
|
||||
-- Memory Operation Guard
|
||||
if (TestSequence_TestArray_mem_valid_out(TestSequence_cnt) = '1') then
|
||||
data_out_latch_next <= write_sub_vector(data_out_latch, TestSequence_TestArray_mem_data_out(TestSequence_cnt), to_integer(align_offset(1 downto 0)), TRUE);
|
||||
align_offset_next <= align_offset + 1;
|
||||
cnt_next <= 0;
|
||||
|
||||
-- All Elements processed
|
||||
if (TestSequence_TestArray_cnt = TESTSEQUENCE_TESTARRAY_MAX_DEPTH-1) then
|
||||
-- DONE
|
||||
stage_next <= PUSH;
|
||||
finalize_payload_next <= '1';
|
||||
else
|
||||
TestSequence_TestArray_cnt_next <= TestSequence_TestArray_cnt + 1;
|
||||
end if;
|
||||
|
||||
-- DES: Needed for ALIGN_1
|
||||
-- Need to fetch next Word
|
||||
if(align_offset(1 downto 0) = "11") then
|
||||
stage_next <= PUSH;
|
||||
end if;
|
||||
end if;
|
||||
when others =>
|
||||
end case;
|
||||
end if;
|
||||
when TESTSEQUENCE_MEMBER_END =>
|
||||
-- All Elements processed
|
||||
if (TestSequence_cnt = unsigned(TestSequence_len_latch)-1) then
|
||||
-- DONE
|
||||
stage_next <= PUSH;
|
||||
finalize_payload_next <= '1';
|
||||
else
|
||||
TestSequence_cnt_next <= TestSequence_cnt + 1;
|
||||
encode_stage_next <= WRITE_TESTSEQUENCE_TESTARRAY;
|
||||
TestSequence_TestArray_cnt_next <= 0;
|
||||
cnt_next <= 0;
|
||||
end if;
|
||||
end case;
|
||||
-- ###GENERATED END###
|
||||
when GET_KEY_HASH =>
|
||||
if (done_md5 = '1') then
|
||||
key_hash_next <= to_key_hash(hash_out_md5);
|
||||
stage_next <= PUSH_KEY_HASH;
|
||||
cnt_next <= 0;
|
||||
end if;
|
||||
when PUSH_KEY_HASH =>
|
||||
case (cnt) is
|
||||
-- Key Hash 1/4
|
||||
when 0 =>
|
||||
data_out <= key_hash(0);
|
||||
valid_out <= '1';
|
||||
-- Output Guard
|
||||
if (ready_out = '1') then
|
||||
cnt_next <= cnt + 1;
|
||||
end if;
|
||||
-- Key Hash 2/4
|
||||
when 1 =>
|
||||
data_out <= key_hash(1);
|
||||
valid_out <= '1';
|
||||
-- Output Guard
|
||||
if (ready_out = '1') then
|
||||
cnt_next <= cnt + 1;
|
||||
end if;
|
||||
-- Key Hash 3/4
|
||||
when 2 =>
|
||||
data_out <= key_hash(2);
|
||||
valid_out <= '1';
|
||||
-- Output Guard
|
||||
if (ready_out = '1') then
|
||||
cnt_next <= cnt + 1;
|
||||
end if;
|
||||
-- Key Hash 4/4
|
||||
when 3 =>
|
||||
data_out <= key_hash(3);
|
||||
valid_out <= '1';
|
||||
last_word_out <= '1';
|
||||
-- Output Guard
|
||||
if (ready_out = '1') then
|
||||
-- DONE
|
||||
stage_next <= IDLE;
|
||||
end if;
|
||||
when others =>
|
||||
null;
|
||||
end case;
|
||||
when others =>
|
||||
null;
|
||||
end case;
|
||||
|
||||
-- OVERREAD GUARD
|
||||
-- Attempted read on empty input
|
||||
if (last_word_in_latch = '1' and ready_in_sig = '1') then
|
||||
stage_next <= SKIP_PAYLOAD;
|
||||
decode_error_latch_next <= '1';
|
||||
end if;
|
||||
|
||||
end process;
|
||||
|
||||
sync_prc : process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if (reset = '1') then
|
||||
stage <= IDLE;
|
||||
decode_stage <= GET_ID;
|
||||
encode_stage <= WRITE_ID;
|
||||
return_stage <= GET_ID;
|
||||
target_align <= ALIGN_1;
|
||||
opcode_latch <= NOP;
|
||||
cnt <= 0;
|
||||
cnt_2 <= 0;
|
||||
endian_flag <= '0';
|
||||
last_word_in_latch <= '0';
|
||||
decode_error <= '0';
|
||||
optional <= '0';
|
||||
align_op <= '0';
|
||||
finalize_payload <= '0';
|
||||
align_offset <= (others => '0');
|
||||
data_in_latch <= (others => '0');
|
||||
key_hash <= HANDLE_NIL;
|
||||
-- ###GENERATED START###
|
||||
id_latch <= (others => '0');
|
||||
TestSequence_len_latch <= (others => '0');
|
||||
TestSequence_cnt <= 0;
|
||||
TestSequence_TestArray_cnt <= 0;
|
||||
-- ###GENERATED END###
|
||||
else
|
||||
stage <= stage_next;
|
||||
decode_stage <= decode_stage_next;
|
||||
encode_stage <= encode_stage_next;
|
||||
return_stage <= return_stage_next;
|
||||
target_align <= target_align_next;
|
||||
opcode_latch <= opcode_latch_next;
|
||||
cnt <= cnt_next;
|
||||
cnt_2 <= cnt_2_next;
|
||||
endian_flag <= endian_flag_next;
|
||||
last_word_in_latch <= last_word_in_latch_next;
|
||||
decode_error <= decode_error_latch_next;
|
||||
optional <= optional_next;
|
||||
align_op <= align_op_next;
|
||||
finalize_payload <= finalize_payload_next;
|
||||
align_offset <= align_offset_next;
|
||||
data_in_latch <= data_in_latch_next;
|
||||
key_hash <= key_hash_next;
|
||||
-- ###GENERATED START###
|
||||
id_latch <= id_latch_next;
|
||||
TestSequence_len_latch <= TestSequence_len_latch_next;
|
||||
TestSequence_cnt <= TestSequence_cnt_next;
|
||||
TestSequence_TestArray_cnt <= TestSequence_TestArray_cnt_next;
|
||||
-- ###GENERATED END###
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end architecture;
|
||||
@ -1,24 +0,0 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity key_generator is
|
||||
port (
|
||||
clk : in std_logic;
|
||||
reset : in std_logic;
|
||||
|
||||
start : in std_logic;
|
||||
opcode : in KEY_GENERATOR_OPCODE_TYPE;
|
||||
busy : out std_logic;
|
||||
|
||||
data_in : in std_logic_vector(WORD_WIDTH-1 downto 0);
|
||||
valid_in : in std_logic;
|
||||
ready_in : out std_logic;
|
||||
last_word_in : in std_logic;
|
||||
|
||||
data_out : out std_logic_vector(WORD_WIDTH-1 downto 0);
|
||||
valid_out : out std_logic;
|
||||
ready_out : in std_logic;
|
||||
last_word_out : out std_logic
|
||||
);
|
||||
end entity;
|
||||
@ -1,148 +0,0 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity key_hash_generator is
|
||||
port (
|
||||
clk : in std_logic;
|
||||
reset : in std_logic;
|
||||
|
||||
data_in : in std_logic_vector(WORD_WIDTH-1 downto 0);
|
||||
valid_in : in std_logic;
|
||||
ready_in : out std_logic;
|
||||
last_word_in : in std_logic;
|
||||
|
||||
data_out : out std_logic_vector(WORD_WIDTH-1 downto 0);
|
||||
valid_out : out std_logic;
|
||||
ready_out : in std_logic;
|
||||
last_word_out : out std_logic
|
||||
);
|
||||
end entity;
|
||||
|
||||
architecture arch of key_hash_generator is
|
||||
|
||||
--*****CONSTANT DECLARATION*****
|
||||
constant KEY_SIZE : natural := TODO;
|
||||
|
||||
--*****TYPE DECLARATION*****
|
||||
type STAGE_TYPE is (IDLE, TODO);
|
||||
|
||||
--*****SIGNAL DECLARATION*****
|
||||
signal key_gen_start, key_gen_busy, key_gen_valid_in, key_gen_ready_in, key_gen_last_word_in, key_gen_valid_out, key_gen_ready_out, key_gen_last_word_out : std_logic := '0';
|
||||
signal key_gen_opcode : KEY_GENERATOR_OPCODE_TYPE := NOP;
|
||||
signal key_gen_data_in, key_gen_data_out : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
|
||||
|
||||
signal stage, stage_next : STAGE_TYPE := IDLE;
|
||||
signal key_hash, key_hash_next : KEY_HASH_TYPE := (others => (others => '0'));
|
||||
signal cnt, cnt_next : natural range 0 to KEY_HASH_TYPE'length-1 := 0;
|
||||
|
||||
begin
|
||||
|
||||
key_generator_inst : entity work.key_generator(arch)
|
||||
port map(
|
||||
clk => clk,
|
||||
reset => reset,
|
||||
start => key_gen_start,
|
||||
opcode => key_gen_opcode,
|
||||
busy => key_gen_busy,
|
||||
data_in => key_gen_data_in,
|
||||
valid_in => key_gen_valid_in,
|
||||
ready_in => key_gen_ready_in,
|
||||
last_word_in => key_gen_last_word_in,
|
||||
data_out => key_gen_data_out,
|
||||
valid_out => key_gen_valid_out,
|
||||
ready_out => key_gen_ready_out,
|
||||
last_word_out => key_gen_last_word_out
|
||||
);
|
||||
|
||||
|
||||
main_prc : process (all)
|
||||
begin
|
||||
-- DEFAULT
|
||||
stage_next <= stage;
|
||||
key_hash_next <= key_hash;
|
||||
cnt_next <= cnt;
|
||||
ready_in <= '0';
|
||||
key_gen_start <= '0';
|
||||
key_gen_valid_in <= '0';
|
||||
key_gen_last_word_in <= '0';
|
||||
key_gen_data_in <= (others => '0');
|
||||
key_gen_ready_out <= '0';
|
||||
valid_out <= '0';
|
||||
last_word_out <= '0';
|
||||
data_out <= (others => '0');
|
||||
|
||||
case (stage) is
|
||||
when IDLE =>
|
||||
if (valid_in = '1' and key_gen_busy = '0') then
|
||||
key_gen_start <= '1';
|
||||
key_gen_opcode <= WRITE_PAYLOAD;
|
||||
stage_next <= PASSTHROUGH_PAYLOAD;
|
||||
end if;
|
||||
when PASSTHROUGH_PAYLOAD =>
|
||||
-- TODO: Connect directly to key_generator?
|
||||
ready_in <= key_gen_ready_in;
|
||||
key_gen_valid_in <= valid_in;
|
||||
key_gen_data_in <= data_in;
|
||||
key_gen_last_word_in <= last_word_in;
|
||||
|
||||
-- Exit Condition
|
||||
if (last_word_in = '1') then
|
||||
stage_next <= GET_SIZE;
|
||||
end if;
|
||||
when GET_SIZE =>
|
||||
if (key_gen_busy = '0') then
|
||||
key_gen_start <= '1';
|
||||
key_gen_opcode <= READ_SIZE;
|
||||
stage_next <= READ_SIZE;
|
||||
end if;
|
||||
when READ_SIZE =>
|
||||
key_gen_ready_out <= '1';
|
||||
if (key_gen_valid_out = '1') then
|
||||
if (unsigned(key_gen_data_out)) > (KEY_HASH_WIDTH/BYTE_WIDTH)) then
|
||||
-- TODO: MD5 Calculation
|
||||
assert FALSE report "MD5 Key hash generation not yet implemented." severity FAILURE;
|
||||
else
|
||||
stage_next <= GET_KEY_HASH;
|
||||
end if;
|
||||
end if;
|
||||
when GET_KEY_HASH =>
|
||||
if (key_gen_busy = '0') then
|
||||
key_gen_start <= '1';
|
||||
key_gen_opcode <= READ_KEY;
|
||||
|
||||
stage_next <= WRITE_KEY_HASH;
|
||||
cnt_next <= 0;
|
||||
key_hash_next <= (others => (others => '0'));
|
||||
end if;
|
||||
when WRITE_KEY_HASH =>
|
||||
key_gen_ready_out <= '1';
|
||||
if (key_gen_valid_out) then
|
||||
cnt_next <= cnt + 1;
|
||||
|
||||
key_hash_next(cnt) <= key_gen_data_out;
|
||||
|
||||
if (key_gen_last_word_out = '1') then
|
||||
stage_next <= FINISHED_KEY_HASH;
|
||||
cnt_next <= 0;
|
||||
end if;
|
||||
end if;
|
||||
when FINISHED_KEY_HASH =>
|
||||
valid_out <= '1';
|
||||
if (ready_out = '1') then
|
||||
cnt_next <= cnt + 1;
|
||||
|
||||
data_out <= key_hash(cnt);
|
||||
|
||||
if (cnt = key_hash'length-1) then
|
||||
last_word_out <= '1';
|
||||
-- DONE
|
||||
stage_next <= IDLE;
|
||||
end if;
|
||||
end if;
|
||||
when others =>
|
||||
null;
|
||||
end case;
|
||||
end process;
|
||||
|
||||
end architecture;
|
||||
@ -8,8 +8,9 @@ entity key_holder is
|
||||
reset : in std_logic;
|
||||
|
||||
start : in std_logic;
|
||||
opcode : in KEY_HOLDER_TYPE;
|
||||
ack : in std_logic;
|
||||
opcode : in KEY_HOLDER_OPCODE_TYPE;
|
||||
ack : out std_logic;
|
||||
decode_error : out std_logic;
|
||||
|
||||
data_in : in std_logic_vector(WORD_WIDTH-1 downto 0);
|
||||
valid_in : in std_logic;
|
||||
|
||||
21
src/md5_calculator.vhd
Normal file
21
src/md5_calculator.vhd
Normal file
@ -0,0 +1,21 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity md5_calculator is
|
||||
port (
|
||||
clk : in std_logic;
|
||||
reset : in std_logic;
|
||||
|
||||
start : in std_logic;
|
||||
ack : out std_logic;
|
||||
|
||||
data_in : in std_logic_vector(7 downto 0);
|
||||
valid_in : in std_logic;
|
||||
ready_in : out std_logic;
|
||||
last_word_in : in std_logic;
|
||||
|
||||
hash_out : out std_logic_vector(127 downto 0);
|
||||
done : out std_logic;
|
||||
);
|
||||
end entity;
|
||||
@ -463,6 +463,7 @@ package rtps_package is
|
||||
|
||||
function to_guid(A : GUIDPREFIX_TYPE; B : std_logic_vector(ENTITYID_WIDTH-1 downto 0)) return GUID_TYPE;
|
||||
function to_key_hash(A : GUID_TYPE) return KEY_HASH_TYPE;
|
||||
function to_key_hash(A : std_logic_vector) return KEY_HASH_TYPE;
|
||||
|
||||
-- *OVERLOAD FUNCTIONS*
|
||||
function to_unsigned (input: DOUBLE_WORD_ARRAY) return unsigned;
|
||||
@ -709,6 +710,16 @@ package body rtps_package is
|
||||
return ret;
|
||||
end function;
|
||||
|
||||
function to_key_hash (A : std_logic_vector) return KEY_HASH_TYPE is
|
||||
variable ret : KEY_HASH_TYPE := HANDLE_NIL;
|
||||
begin
|
||||
assert (A'length = KEY_HASH_WIDTH) severity FAILURE;
|
||||
for i in 0 to KEY_HASH_TYPE'length-1 loop
|
||||
ret(i) := A(((i+1)*WORD_WIDTH)-1 downto i*WORD_WIDTH);
|
||||
end loop;
|
||||
return ret;
|
||||
end function;
|
||||
|
||||
function to_unsigned(input : KEY_HASH_TYPE) return unsigned is
|
||||
variable ret : unsigned(KEY_HASH_WIDTH-1 downto 0) := (others => '0');
|
||||
begin
|
||||
|
||||
@ -1,24 +0,0 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity serialized_key_generator is
|
||||
port (
|
||||
clk : in std_logic;
|
||||
reset : in std_logic;
|
||||
|
||||
start : in std_logic;
|
||||
opcode : in KEY_GENERATOR_OPCODE_TYPE;
|
||||
busy : out std_logic;
|
||||
|
||||
data_in : in std_logic_vector(WORD_WIDTH-1 downto 0);
|
||||
valid_in : in std_logic;
|
||||
ready_in : out std_logic;
|
||||
last_word_in : in std_logic;
|
||||
|
||||
data_out : out std_logic_vector(WORD_WIDTH-1 downto 0);
|
||||
valid_out : out std_logic;
|
||||
ready_out : in std_logic;
|
||||
last_word_out : out std_logic
|
||||
);
|
||||
end entity;
|
||||
Loading…
Reference in New Issue
Block a user