diff --git a/src/Avalon_MM_wrapper.vhd b/src/Avalon_MM_wrapper.vhd
index 37ef7f5..e36af53 100644
--- a/src/Avalon_MM_wrapper.vhd
+++ b/src/Avalon_MM_wrapper.vhd
@@ -1,3 +1,6 @@
+-- altera vhdl_input_version vhdl_2008
+-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
@@ -84,4 +87,4 @@ begin
         end if;
     end process;
     
-end architecture;
\ No newline at end of file
+end architecture;
diff --git a/src/FWFT_FIFO.vhd b/src/FWFT_FIFO.vhd
index 2120fa6..3bc1b2b 100644
--- a/src/FWFT_FIFO.vhd
+++ b/src/FWFT_FIFO.vhd
@@ -1,3 +1,6 @@
+-- altera vhdl_input_version vhdl_2008
+-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
@@ -66,4 +69,4 @@ begin
         end if;
     end process;
     
-end architecture;
\ No newline at end of file
+end architecture;
diff --git a/src/FWFT_FIFO_Altera.vhd b/src/FWFT_FIFO_Altera.vhd
index 54cd4bd..dfaf9cb 100644
--- a/src/FWFT_FIFO_Altera.vhd
+++ b/src/FWFT_FIFO_Altera.vhd
@@ -1,3 +1,6 @@
+-- altera vhdl_input_version vhdl_2008
+-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
@@ -40,4 +43,4 @@ begin
 		usedw   => used_sig
 	);
     
-end architecture;
\ No newline at end of file
+end architecture;
diff --git a/src/FWFT_FIFO_cfg.vhd b/src/FWFT_FIFO_cfg.vhd
index 8583299..e665265 100644
--- a/src/FWFT_FIFO_cfg.vhd
+++ b/src/FWFT_FIFO_cfg.vhd
@@ -1,4 +1,7 @@
+-- altera vhdl_input_version vhdl_2008
+-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
+
 configuration FWFT_FIFO_cfg of FWFT_FIFO is
     for altera
     end for;
-end configuration;
\ No newline at end of file
+end configuration;
diff --git a/src/TEMPLATE_key_holder.vhd b/src/TEMPLATE_key_holder.vhd
index ab3c6ed..2f7bbfa 100644
--- a/src/TEMPLATE_key_holder.vhd
+++ b/src/TEMPLATE_key_holder.vhd
@@ -1,3 +1,6 @@
+-- altera vhdl_input_version vhdl_2008
+-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
@@ -508,4 +511,4 @@ begin
         end if;
     end process;
     
-end architecture;
\ No newline at end of file
+end architecture;
diff --git a/src/TEMPLATE_reader_wrapper.vhd b/src/TEMPLATE_reader_wrapper.vhd
index 88abdea..8c34722 100644
--- a/src/TEMPLATE_reader_wrapper.vhd
+++ b/src/TEMPLATE_reader_wrapper.vhd
@@ -1,3 +1,6 @@
+-- altera vhdl_input_version vhdl_2008
+-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
@@ -391,4 +394,4 @@ begin
         end if;
     end process;
     
-end architecture;
\ No newline at end of file
+end architecture;
diff --git a/src/TEMPLATE_writer_wrapper.vhd b/src/TEMPLATE_writer_wrapper.vhd
index 6aebeb2..1142d9a 100644
--- a/src/TEMPLATE_writer_wrapper.vhd
+++ b/src/TEMPLATE_writer_wrapper.vhd
@@ -1,3 +1,6 @@
+-- altera vhdl_input_version vhdl_2008
+-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
@@ -253,4 +256,4 @@ begin
         end if;
     end process;
     
-end architecture;
\ No newline at end of file
+end architecture;
diff --git a/src/addsub.vhd b/src/addsub.vhd
index 43967c1..b11531e 100644
--- a/src/addsub.vhd
+++ b/src/addsub.vhd
@@ -1,3 +1,6 @@
+-- altera vhdl_input_version vhdl_2008
+-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
@@ -73,4 +76,4 @@ begin
         end if;
     end process;
     
-end architecture;
\ No newline at end of file
+end architecture;
diff --git a/src/checksum.vhd b/src/checksum.vhd
index 59ad562..98c76b1 100644
--- a/src/checksum.vhd
+++ b/src/checksum.vhd
@@ -1,8 +1,10 @@
+-- altera vhdl_input_version vhdl_2008
+-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 
-
 entity addsub is
     generic (
         INPUT_WIDTH     : integer := 32;
@@ -44,4 +46,4 @@ architecture arch of addsub is
 begin
 
     
-end architecture;
\ No newline at end of file
+end architecture;
diff --git a/src/dds_reader.vhd b/src/dds_reader.vhd
index 8bfb031..24a4f80 100644
--- a/src/dds_reader.vhd
+++ b/src/dds_reader.vhd
@@ -1,3 +1,6 @@
+-- altera vhdl_input_version vhdl_2008
+-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
@@ -6825,4 +6828,4 @@ begin
             end if;
         end if;
     end process;
-end architecture;
\ No newline at end of file
+end architecture;
diff --git a/src/dds_writer.vhd b/src/dds_writer.vhd
index 39938ff..286f60c 100644
--- a/src/dds_writer.vhd
+++ b/src/dds_writer.vhd
@@ -1,3 +1,6 @@
+-- altera vhdl_input_version vhdl_2008
+-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
@@ -4685,4 +4688,4 @@ begin
         end if;
     end process;
     
-end architecture;
\ No newline at end of file
+end architecture;
diff --git a/src/history_cache.vhd b/src/history_cache.vhd
index 8f19dc4..dd8a9c5 100644
--- a/src/history_cache.vhd
+++ b/src/history_cache.vhd
@@ -1,3 +1,6 @@
+-- altera vhdl_input_version vhdl_2008
+-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
@@ -1677,4 +1680,4 @@ begin
         end case;
     end process;
     
-end architecture;
\ No newline at end of file
+end architecture;
diff --git a/src/ip_package.vhd b/src/ip_package.vhd
index b5274b2..9aa1459 100644
--- a/src/ip_package.vhd
+++ b/src/ip_package.vhd
@@ -1,3 +1,6 @@
+-- altera vhdl_input_version vhdl_2008
+-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
@@ -15,4 +18,4 @@ package ip_package is
 end package;
 
 package body ip_package is
-end package body;
\ No newline at end of file
+end package body;
diff --git a/src/ipv4_in_handler.vhd b/src/ipv4_in_handler.vhd
index a562a3a..d6bd355 100644
--- a/src/ipv4_in_handler.vhd
+++ b/src/ipv4_in_handler.vhd
@@ -1,3 +1,6 @@
+-- altera vhdl_input_version vhdl_2008
+-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
@@ -1033,4 +1036,4 @@ begin
         end if;
     end process;
     
-end architecture;
\ No newline at end of file
+end architecture;
diff --git a/src/key_hash_generator.vhd b/src/key_hash_generator.vhd
index a5d4b51..3e0c41f 100644
--- a/src/key_hash_generator.vhd
+++ b/src/key_hash_generator.vhd
@@ -1,3 +1,6 @@
+-- altera vhdl_input_version vhdl_2008
+-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
@@ -19,4 +22,4 @@ entity key_hash_generator is
         key_hash        : out std_logic_vector(127 downto 0);
         done            : out std_logic
     );
-end entity;
\ No newline at end of file
+end entity;
diff --git a/src/key_holder.vhd b/src/key_holder.vhd
index 8596eba..b1f0555 100644
--- a/src/key_holder.vhd
+++ b/src/key_holder.vhd
@@ -1,3 +1,6 @@
+-- altera vhdl_input_version vhdl_2008
+-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
@@ -27,4 +30,4 @@ entity key_holder is
         data_out        : out std_logic_vector(WORD_WIDTH-1 downto 0);
         last_word_out   : out std_logic
     );
-end entity;
\ No newline at end of file
+end entity;
diff --git a/src/math_pkg.vhd b/src/math_pkg.vhd
index 3e58354..e79c33d 100644
--- a/src/math_pkg.vhd
+++ b/src/math_pkg.vhd
@@ -1,3 +1,6 @@
+-- altera vhdl_input_version vhdl_2008
+-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
+
 package math_pkg is
     -- calculates the logarithm dualis of the operand and rounds up
     -- the result to the next integer value.
diff --git a/src/mem_ctrl.vhd b/src/mem_ctrl.vhd
index a5bc100..5a066ac 100644
--- a/src/mem_ctrl.vhd
+++ b/src/mem_ctrl.vhd
@@ -1,3 +1,6 @@
+-- altera vhdl_input_version vhdl_2008
+-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
@@ -110,4 +113,4 @@ begin
             full        => open,
             free        => fifo_cnt
         );
-end architecture;
\ No newline at end of file
+end architecture;
diff --git a/src/rtps_builtin_endpoint.vhd b/src/rtps_builtin_endpoint.vhd
index eb13710..8a239e1 100644
--- a/src/rtps_builtin_endpoint.vhd
+++ b/src/rtps_builtin_endpoint.vhd
@@ -1,3 +1,6 @@
+-- altera vhdl_input_version vhdl_2008
+-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
diff --git a/src/rtps_config_package.vhd b/src/rtps_config_package.vhd
index d4fa111..4171807 100644
--- a/src/rtps_config_package.vhd
+++ b/src/rtps_config_package.vhd
@@ -1,3 +1,6 @@
+-- altera vhdl_input_version vhdl_2008
+-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
diff --git a/src/rtps_handler.vhd b/src/rtps_handler.vhd
index d38928b..7ff0481 100644
--- a/src/rtps_handler.vhd
+++ b/src/rtps_handler.vhd
@@ -1,3 +1,6 @@
+-- altera vhdl_input_version vhdl_2008
+-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
diff --git a/src/rtps_out.vhd b/src/rtps_out.vhd
index b615297..34774fb 100644
--- a/src/rtps_out.vhd
+++ b/src/rtps_out.vhd
@@ -1,3 +1,6 @@
+-- altera vhdl_input_version vhdl_2008
+-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
@@ -312,4 +315,4 @@ begin
         end if;
     end process;
     
-end architecture;
\ No newline at end of file
+end architecture;
diff --git a/src/rtps_package.vhd b/src/rtps_package.vhd
index ffbb94b..03c8763 100644
--- a/src/rtps_package.vhd
+++ b/src/rtps_package.vhd
@@ -1,3 +1,6 @@
+-- altera vhdl_input_version vhdl_2008
+-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
diff --git a/src/rtps_reader.vhd b/src/rtps_reader.vhd
index 00cb175..453377d 100644
--- a/src/rtps_reader.vhd
+++ b/src/rtps_reader.vhd
@@ -1,3 +1,6 @@
+-- altera vhdl_input_version vhdl_2008
+-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
@@ -3068,4 +3071,4 @@ begin
             end if;
         end if;
     end process;
-end architecture;
\ No newline at end of file
+end architecture;
diff --git a/src/rtps_test_package.vhd b/src/rtps_test_package.vhd
index 78d0eaa..ae98097 100644
--- a/src/rtps_test_package.vhd
+++ b/src/rtps_test_package.vhd
@@ -1,3 +1,6 @@
+-- altera vhdl_input_version vhdl_2008
+-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
@@ -3367,4 +3370,4 @@ package body rtps_test_package is
         end loop;
     end procedure;
     
-end package body;
\ No newline at end of file
+end package body;
diff --git a/src/rtps_writer.vhd b/src/rtps_writer.vhd
index e771b32..181c371 100644
--- a/src/rtps_writer.vhd
+++ b/src/rtps_writer.vhd
@@ -1,3 +1,6 @@
+-- altera vhdl_input_version vhdl_2008
+-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
@@ -3757,4 +3760,4 @@ begin
         end if;
     end process;
     
-end architecture;
\ No newline at end of file
+end architecture;
diff --git a/src/single_port_ram.vhd b/src/single_port_ram.vhd
index 6f8f97b..533e967 100644
--- a/src/single_port_ram.vhd
+++ b/src/single_port_ram.vhd
@@ -1,3 +1,6 @@
+-- altera vhdl_input_version vhdl_2008
+-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
diff --git a/src/single_port_ram_Altera.vhd b/src/single_port_ram_Altera.vhd
index 3a5b652..56ec88a 100644
--- a/src/single_port_ram_Altera.vhd
+++ b/src/single_port_ram_Altera.vhd
@@ -1,3 +1,6 @@
+-- altera vhdl_input_version vhdl_2008
+-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
diff --git a/src/single_port_ram_cfg.vhd b/src/single_port_ram_cfg.vhd
index 3c417d0..2fc13c6 100644
--- a/src/single_port_ram_cfg.vhd
+++ b/src/single_port_ram_cfg.vhd
@@ -1,4 +1,7 @@
+-- altera vhdl_input_version vhdl_2008
+-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
+
 configuration single_port_ram_cfg of single_port_ram is
     for altera
     end for;
-end configuration;
\ No newline at end of file
+end configuration;
diff --git a/src/true_dual_port_ram.vhd b/src/true_dual_port_ram.vhd
index 102ba30..d645e06 100644
--- a/src/true_dual_port_ram.vhd
+++ b/src/true_dual_port_ram.vhd
@@ -1,3 +1,6 @@
+-- altera vhdl_input_version vhdl_2008
+-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
diff --git a/src/user_config.vhd b/src/user_config.vhd
index f71d94d..5cc4cab 100644
--- a/src/user_config.vhd
+++ b/src/user_config.vhd
@@ -1,3 +1,6 @@
+-- altera vhdl_input_version vhdl_2008
+-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
@@ -123,4 +126,4 @@ package user_config is
     
     -- Set to TRUE for Simulation Testing (Extra Code generated)
     constant SIMULATION_FLAG : boolean := FALSE;
-end package;
\ No newline at end of file
+end package;
diff --git a/syn/dds_reader_syn.vhd b/syn/dds_reader_syn.vhd
index 81f4f76..784433f 100644
--- a/syn/dds_reader_syn.vhd
+++ b/syn/dds_reader_syn.vhd
@@ -1,3 +1,6 @@
+-- altera vhdl_input_version vhdl_2008
+-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
diff --git a/syn/dds_writer_syn.vhd b/syn/dds_writer_syn.vhd
index f5dd295..0e08910 100644
--- a/syn/dds_writer_syn.vhd
+++ b/syn/dds_writer_syn.vhd
@@ -1,3 +1,6 @@
+-- altera vhdl_input_version vhdl_2008
+-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
diff --git a/syn/rtps_reader_syn.vhd b/syn/rtps_reader_syn.vhd
index 9f1d9d4..ebc8fa2 100644
--- a/syn/rtps_reader_syn.vhd
+++ b/syn/rtps_reader_syn.vhd
@@ -1,3 +1,6 @@
+-- altera vhdl_input_version vhdl_2008
+-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
diff --git a/syn/rtps_writer_syn.vhd b/syn/rtps_writer_syn.vhd
index 80ee2c1..0959098 100644
--- a/syn/rtps_writer_syn.vhd
+++ b/syn/rtps_writer_syn.vhd
@@ -1,3 +1,6 @@
+-- altera vhdl_input_version vhdl_2008
+-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
diff --git a/syn/syn_config.vhd b/syn/syn_config.vhd
index 34f5730..0ecb7b9 100644
--- a/syn/syn_config.vhd
+++ b/syn/syn_config.vhd
@@ -1,3 +1,6 @@
+-- altera vhdl_input_version vhdl_2008
+-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
@@ -125,4 +128,4 @@ package user_config is
     
     -- Set to TRUE for Simulation Testing (Extra Code generated)
     constant SIMULATION_FLAG : boolean := FALSE;
-end package;
\ No newline at end of file
+end package;
diff --git a/syn/test.vhd b/syn/test.vhd
index e974e91..d58e0ac 100644
--- a/syn/test.vhd
+++ b/syn/test.vhd
@@ -1,3 +1,6 @@
+-- altera vhdl_input_version vhdl_2008
+-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
diff --git a/syn/test2.vhd b/syn/test2.vhd
index 78b64a5..d1cb089 100644
--- a/syn/test2.vhd
+++ b/syn/test2.vhd
@@ -1,3 +1,6 @@
+-- altera vhdl_input_version vhdl_2008
+-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
diff --git a/syn/test3.vhd b/syn/test3.vhd
index 2e4e8b8..8dc4894 100644
--- a/syn/test3.vhd
+++ b/syn/test3.vhd
@@ -1,3 +1,6 @@
+-- altera vhdl_input_version vhdl_2008
+-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
diff --git a/syn/test4.vhd b/syn/test4.vhd
index 0fe7880..8836fd8 100644
--- a/syn/test4.vhd
+++ b/syn/test4.vhd
@@ -1,3 +1,6 @@
+-- altera vhdl_input_version vhdl_2008
+-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
diff --git a/syn/test5.vhd b/syn/test5.vhd
index a8a1cdb..a11dbda 100644
--- a/syn/test5.vhd
+++ b/syn/test5.vhd
@@ -1,3 +1,6 @@
+-- altera vhdl_input_version vhdl_2008
+-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
diff --git a/syn/test_fpga.vhd b/syn/test_fpga.vhd
index caefe8b..881d109 100644
--- a/syn/test_fpga.vhd
+++ b/syn/test_fpga.vhd
@@ -1,3 +1,6 @@
+-- altera vhdl_input_version vhdl_2008
+-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
diff --git a/syn/test_package.vhd b/syn/test_package.vhd
index 4cedf01..a1dd2ea 100644
--- a/syn/test_package.vhd
+++ b/syn/test_package.vhd
@@ -1,3 +1,6 @@
+-- altera vhdl_input_version vhdl_2008
+-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
diff --git a/syn/test_top.vhd b/syn/test_top.vhd
index bff25ec..b8456fc 100644
--- a/syn/test_top.vhd
+++ b/syn/test_top.vhd
@@ -1,3 +1,6 @@
+-- altera vhdl_input_version vhdl_2008
+-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;