diff --git a/ros_action_Fibonacci_with_feedback.txt b/ros_action_Fibonacci_with_feedback.txt index 75ffe29..8bf760e 100644 --- a/ros_action_Fibonacci_with_feedback.txt +++ b/ros_action_Fibonacci_with_feedback.txt @@ -59,4 +59,18 @@ ; |dds_writer:\dds_endpoint_gen:7:dds_endpoint_if:dds_writer_inst| ; 1496 (1357) ; 527 (453) ; 292096 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_gen:7:dds_endpoint_if:dds_writer_inst ; dds_writer ; work ; ; |rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst| ; 5427 (5295) ; 2360 (2279) ; 84672 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst ; rtps_reader ; work ; ; |rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst| ; 7010 (6750) ; 3150 (2988) ; 169344 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst ; rtps_writer ; work ; ++------------------------------------------------------------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------+--------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Resource Utilization by Entity ; ++------------------------------------------------------------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------+--------------+ +; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ; ++------------------------------------------------------------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------+--------------+ +; |test_top ; 42256 (64) ; 19765 (63) ; 2408283 ; 4 ; 71 ; 0 ; |test_top ; test_top ; work ; +; |dds_reader:\dds_endpoint_gen:0:dds_reader_inst| ; 2371 (2263) ; 606 (551) ; 20160 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:0:dds_reader_inst ; dds_reader ; work ; +; |dds_reader:\dds_endpoint_gen:1:dds_reader_inst| ; 2363 (2258) ; 605 (551) ; 18752 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:1:dds_reader_inst ; dds_reader ; work ; +; |dds_reader:\dds_endpoint_gen:2:dds_reader_inst| ; 2372 (2266) ; 605 (551) ; 21568 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:2:dds_reader_inst ; dds_reader ; work ; +; |dds_writer:\dds_endpoint_w_if:dds_writer_inst| ; 6798 (4926) ; 4149 (1812) ; 428928 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst ; dds_writer ; work ; +; |rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst| ; 5381 (5249) ; 2360 (2279) ; 84672 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst ; rtps_reader ; work ; +; |rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst| ; 6872 (6612) ; 3150 (2988) ; 169344 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst ; rtps_writer ; work ; +------------------------------------------------------------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------+--------------+ \ No newline at end of file diff --git a/ros_action_Fibonacci_with_feedback5.rpt b/ros_action_Fibonacci_with_feedback5.rpt new file mode 100644 index 0000000..08d0cb5 --- /dev/null +++ b/ros_action_Fibonacci_with_feedback5.rpt @@ -0,0 +1,686 @@ +Resource Utilization by Entity report for top +Sat Apr 2 19:16:42 2022 +Quartus Prime Version 21.1.0 Build 842 10/21/2021 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Analysis & Synthesis Resource Utilization by Entity + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2021 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. + + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Resource Utilization by Entity ; ++------------------------------------------------------------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------+--------------+ +; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ; ++------------------------------------------------------------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------+--------------+ +; |test_top ; 42256 (64) ; 19765 (63) ; 2408283 ; 4 ; 71 ; 0 ; |test_top ; test_top ; work ; +; |Avalon_MM_wrapper:Avalon_MM_wrapper_inst| ; 69 (69) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |test_top|Avalon_MM_wrapper:Avalon_MM_wrapper_inst ; Avalon_MM_wrapper ; work ; +; |FWFT_FIFO:FIFO_IN_inst| ; 121 (0) ; 62 (0) ; 524288 ; 0 ; 0 ; 0 ; |test_top|FWFT_FIFO:FIFO_IN_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 121 (0) ; 62 (0) ; 524288 ; 0 ; 0 ; 0 ; |test_top|FWFT_FIFO:FIFO_IN_inst|scfifo:scfifo_component ; scfifo ; work ; +; |scfifo_ink1:auto_generated| ; 121 (0) ; 62 (0) ; 524288 ; 0 ; 0 ; 0 ; |test_top|FWFT_FIFO:FIFO_IN_inst|scfifo:scfifo_component|scfifo_ink1:auto_generated ; scfifo_ink1 ; work ; +; |a_dpfifo_ojb1:dpfifo| ; 121 (43) ; 62 (20) ; 524288 ; 0 ; 0 ; 0 ; |test_top|FWFT_FIFO:FIFO_IN_inst|scfifo:scfifo_component|scfifo_ink1:auto_generated|a_dpfifo_ojb1:dpfifo ; a_dpfifo_ojb1 ; work ; +; |altsyncram_eek1:FIFOram| ; 34 (0) ; 1 (1) ; 524288 ; 0 ; 0 ; 0 ; |test_top|FWFT_FIFO:FIFO_IN_inst|scfifo:scfifo_component|scfifo_ink1:auto_generated|a_dpfifo_ojb1:dpfifo|altsyncram_eek1:FIFOram ; altsyncram_eek1 ; work ; +; |decode_s07:decode2| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |test_top|FWFT_FIFO:FIFO_IN_inst|scfifo:scfifo_component|scfifo_ink1:auto_generated|a_dpfifo_ojb1:dpfifo|altsyncram_eek1:FIFOram|decode_s07:decode2 ; decode_s07 ; work ; +; |decode_s07:wren_decode_a| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |test_top|FWFT_FIFO:FIFO_IN_inst|scfifo:scfifo_component|scfifo_ink1:auto_generated|a_dpfifo_ojb1:dpfifo|altsyncram_eek1:FIFOram|decode_s07:wren_decode_a ; decode_s07 ; work ; +; |mux_ps7:mux3| ; 32 (32) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |test_top|FWFT_FIFO:FIFO_IN_inst|scfifo:scfifo_component|scfifo_ink1:auto_generated|a_dpfifo_ojb1:dpfifo|altsyncram_eek1:FIFOram|mux_ps7:mux3 ; mux_ps7 ; work ; +; |cntr_04b:wr_ptr| ; 15 (15) ; 14 (14) ; 0 ; 0 ; 0 ; 0 ; |test_top|FWFT_FIFO:FIFO_IN_inst|scfifo:scfifo_component|scfifo_ink1:auto_generated|a_dpfifo_ojb1:dpfifo|cntr_04b:wr_ptr ; cntr_04b ; work ; +; |cntr_c47:usedw_counter| ; 15 (15) ; 14 (14) ; 0 ; 0 ; 0 ; 0 ; |test_top|FWFT_FIFO:FIFO_IN_inst|scfifo:scfifo_component|scfifo_ink1:auto_generated|a_dpfifo_ojb1:dpfifo|cntr_c47:usedw_counter ; cntr_c47 ; work ; +; |cntr_v3b:rd_ptr_msb| ; 14 (14) ; 13 (13) ; 0 ; 0 ; 0 ; 0 ; |test_top|FWFT_FIFO:FIFO_IN_inst|scfifo:scfifo_component|scfifo_ink1:auto_generated|a_dpfifo_ojb1:dpfifo|cntr_v3b:rd_ptr_msb ; cntr_v3b ; work ; +; |FWFT_FIFO:FIFO_OUT_inst| ; 91 (0) ; 62 (0) ; 524288 ; 0 ; 0 ; 0 ; |test_top|FWFT_FIFO:FIFO_OUT_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 91 (0) ; 62 (0) ; 524288 ; 0 ; 0 ; 0 ; |test_top|FWFT_FIFO:FIFO_OUT_inst|scfifo:scfifo_component ; scfifo ; work ; +; |scfifo_ink1:auto_generated| ; 91 (0) ; 62 (0) ; 524288 ; 0 ; 0 ; 0 ; |test_top|FWFT_FIFO:FIFO_OUT_inst|scfifo:scfifo_component|scfifo_ink1:auto_generated ; scfifo_ink1 ; work ; +; |a_dpfifo_ojb1:dpfifo| ; 91 (45) ; 62 (20) ; 524288 ; 0 ; 0 ; 0 ; |test_top|FWFT_FIFO:FIFO_OUT_inst|scfifo:scfifo_component|scfifo_ink1:auto_generated|a_dpfifo_ojb1:dpfifo ; a_dpfifo_ojb1 ; work ; +; |altsyncram_eek1:FIFOram| ; 2 (0) ; 1 (1) ; 524288 ; 0 ; 0 ; 0 ; |test_top|FWFT_FIFO:FIFO_OUT_inst|scfifo:scfifo_component|scfifo_ink1:auto_generated|a_dpfifo_ojb1:dpfifo|altsyncram_eek1:FIFOram ; altsyncram_eek1 ; work ; +; |decode_s07:decode2| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |test_top|FWFT_FIFO:FIFO_OUT_inst|scfifo:scfifo_component|scfifo_ink1:auto_generated|a_dpfifo_ojb1:dpfifo|altsyncram_eek1:FIFOram|decode_s07:decode2 ; decode_s07 ; work ; +; |cntr_04b:wr_ptr| ; 15 (15) ; 14 (14) ; 0 ; 0 ; 0 ; 0 ; |test_top|FWFT_FIFO:FIFO_OUT_inst|scfifo:scfifo_component|scfifo_ink1:auto_generated|a_dpfifo_ojb1:dpfifo|cntr_04b:wr_ptr ; cntr_04b ; work ; +; |cntr_c47:usedw_counter| ; 15 (15) ; 14 (14) ; 0 ; 0 ; 0 ; 0 ; |test_top|FWFT_FIFO:FIFO_OUT_inst|scfifo:scfifo_component|scfifo_ink1:auto_generated|a_dpfifo_ojb1:dpfifo|cntr_c47:usedw_counter ; cntr_c47 ; work ; +; |cntr_v3b:rd_ptr_msb| ; 14 (14) ; 13 (13) ; 0 ; 0 ; 0 ; 0 ; |test_top|FWFT_FIFO:FIFO_OUT_inst|scfifo:scfifo_component|scfifo_ink1:auto_generated|a_dpfifo_ojb1:dpfifo|cntr_v3b:rd_ptr_msb ; cntr_v3b ; work ; +; |L2_Testbench_ROS_Lib4:ros_action_inst| ; 41911 (0) ; 19578 (0) ; 1359707 ; 4 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst ; L2_Testbench_ROS_Lib4 ; work ; +; |FWFT_FIFO:\fifo_in_ro_gen:0:fifo_in_ro_if:fifo_in_ro_inst| ; 17 (0) ; 9 (0) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|FWFT_FIFO:\fifo_in_ro_gen:0:fifo_in_ro_if:fifo_in_ro_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 17 (0) ; 9 (0) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|FWFT_FIFO:\fifo_in_ro_gen:0:fifo_in_ro_if:fifo_in_ro_inst|scfifo:scfifo_component ; scfifo ; work ; +; |scfifo_bfk1:auto_generated| ; 17 (0) ; 9 (0) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|FWFT_FIFO:\fifo_in_ro_gen:0:fifo_in_ro_if:fifo_in_ro_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated ; scfifo_bfk1 ; work ; +; |a_dpfifo_hbb1:dpfifo| ; 17 (13) ; 9 (7) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|FWFT_FIFO:\fifo_in_ro_gen:0:fifo_in_ro_if:fifo_in_ro_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated|a_dpfifo_hbb1:dpfifo ; a_dpfifo_hbb1 ; work ; +; |altsyncram_0uj1:FIFOram| ; 0 (0) ; 0 (0) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|FWFT_FIFO:\fifo_in_ro_gen:0:fifo_in_ro_if:fifo_in_ro_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated|a_dpfifo_hbb1:dpfifo|altsyncram_0uj1:FIFOram ; altsyncram_0uj1 ; work ; +; |cntr_c2b:wr_ptr| ; 2 (2) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|FWFT_FIFO:\fifo_in_ro_gen:0:fifo_in_ro_if:fifo_in_ro_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated|a_dpfifo_hbb1:dpfifo|cntr_c2b:wr_ptr ; cntr_c2b ; work ; +; |cntr_o27:usedw_counter| ; 2 (2) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|FWFT_FIFO:\fifo_in_ro_gen:0:fifo_in_ro_if:fifo_in_ro_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated|a_dpfifo_hbb1:dpfifo|cntr_o27:usedw_counter ; cntr_o27 ; work ; +; |FWFT_FIFO:\fifo_in_ro_gen:1:fifo_in_ro_if:fifo_in_ro_inst| ; 17 (0) ; 9 (0) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|FWFT_FIFO:\fifo_in_ro_gen:1:fifo_in_ro_if:fifo_in_ro_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 17 (0) ; 9 (0) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|FWFT_FIFO:\fifo_in_ro_gen:1:fifo_in_ro_if:fifo_in_ro_inst|scfifo:scfifo_component ; scfifo ; work ; +; |scfifo_bfk1:auto_generated| ; 17 (0) ; 9 (0) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|FWFT_FIFO:\fifo_in_ro_gen:1:fifo_in_ro_if:fifo_in_ro_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated ; scfifo_bfk1 ; work ; +; |a_dpfifo_hbb1:dpfifo| ; 17 (13) ; 9 (7) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|FWFT_FIFO:\fifo_in_ro_gen:1:fifo_in_ro_if:fifo_in_ro_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated|a_dpfifo_hbb1:dpfifo ; a_dpfifo_hbb1 ; work ; +; |altsyncram_0uj1:FIFOram| ; 0 (0) ; 0 (0) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|FWFT_FIFO:\fifo_in_ro_gen:1:fifo_in_ro_if:fifo_in_ro_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated|a_dpfifo_hbb1:dpfifo|altsyncram_0uj1:FIFOram ; altsyncram_0uj1 ; work ; +; |cntr_c2b:wr_ptr| ; 2 (2) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|FWFT_FIFO:\fifo_in_ro_gen:1:fifo_in_ro_if:fifo_in_ro_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated|a_dpfifo_hbb1:dpfifo|cntr_c2b:wr_ptr ; cntr_c2b ; work ; +; |cntr_o27:usedw_counter| ; 2 (2) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|FWFT_FIFO:\fifo_in_ro_gen:1:fifo_in_ro_if:fifo_in_ro_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated|a_dpfifo_hbb1:dpfifo|cntr_o27:usedw_counter ; cntr_o27 ; work ; +; |FWFT_FIFO:\fifo_in_ro_gen:2:fifo_in_ro_if:fifo_in_ro_inst| ; 16 (0) ; 9 (0) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|FWFT_FIFO:\fifo_in_ro_gen:2:fifo_in_ro_if:fifo_in_ro_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 16 (0) ; 9 (0) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|FWFT_FIFO:\fifo_in_ro_gen:2:fifo_in_ro_if:fifo_in_ro_inst|scfifo:scfifo_component ; scfifo ; work ; +; |scfifo_bfk1:auto_generated| ; 16 (0) ; 9 (0) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|FWFT_FIFO:\fifo_in_ro_gen:2:fifo_in_ro_if:fifo_in_ro_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated ; scfifo_bfk1 ; work ; +; |a_dpfifo_hbb1:dpfifo| ; 16 (12) ; 9 (7) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|FWFT_FIFO:\fifo_in_ro_gen:2:fifo_in_ro_if:fifo_in_ro_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated|a_dpfifo_hbb1:dpfifo ; a_dpfifo_hbb1 ; work ; +; |altsyncram_0uj1:FIFOram| ; 0 (0) ; 0 (0) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|FWFT_FIFO:\fifo_in_ro_gen:2:fifo_in_ro_if:fifo_in_ro_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated|a_dpfifo_hbb1:dpfifo|altsyncram_0uj1:FIFOram ; altsyncram_0uj1 ; work ; +; |cntr_c2b:wr_ptr| ; 2 (2) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|FWFT_FIFO:\fifo_in_ro_gen:2:fifo_in_ro_if:fifo_in_ro_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated|a_dpfifo_hbb1:dpfifo|cntr_c2b:wr_ptr ; cntr_c2b ; work ; +; |cntr_o27:usedw_counter| ; 2 (2) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|FWFT_FIFO:\fifo_in_ro_gen:2:fifo_in_ro_if:fifo_in_ro_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated|a_dpfifo_hbb1:dpfifo|cntr_o27:usedw_counter ; cntr_o27 ; work ; +; |FWFT_FIFO:fifo_in_rb_inst| ; 16 (0) ; 9 (0) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|FWFT_FIFO:fifo_in_rb_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 16 (0) ; 9 (0) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|FWFT_FIFO:fifo_in_rb_inst|scfifo:scfifo_component ; scfifo ; work ; +; |scfifo_bfk1:auto_generated| ; 16 (0) ; 9 (0) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|FWFT_FIFO:fifo_in_rb_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated ; scfifo_bfk1 ; work ; +; |a_dpfifo_hbb1:dpfifo| ; 16 (12) ; 9 (7) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|FWFT_FIFO:fifo_in_rb_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated|a_dpfifo_hbb1:dpfifo ; a_dpfifo_hbb1 ; work ; +; |altsyncram_0uj1:FIFOram| ; 0 (0) ; 0 (0) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|FWFT_FIFO:fifo_in_rb_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated|a_dpfifo_hbb1:dpfifo|altsyncram_0uj1:FIFOram ; altsyncram_0uj1 ; work ; +; |cntr_c2b:wr_ptr| ; 2 (2) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|FWFT_FIFO:fifo_in_rb_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated|a_dpfifo_hbb1:dpfifo|cntr_c2b:wr_ptr ; cntr_c2b ; work ; +; |cntr_o27:usedw_counter| ; 2 (2) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|FWFT_FIFO:fifo_in_rb_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated|a_dpfifo_hbb1:dpfifo|cntr_o27:usedw_counter ; cntr_o27 ; work ; +; |Fibonacci:Fibonacci_inst| ; 295 (295) ; 183 (183) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci:Fibonacci_inst ; Fibonacci ; work ; +; |Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst| ; 4277 (128) ; 3171 (13) ; 50439 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst ; Fibonacci_ros_action_server ; work ; +; |CancelGoal_ros_srv_server:cancel_srv_server_inst| ; 598 (584) ; 699 (501) ; 19200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|CancelGoal_ros_srv_server:cancel_srv_server_inst ; CancelGoal_ros_srv_server ; work ; +; |mem_ctrl:goals_canceling_goal_id_mem| ; 8 (5) ; 131 (2) ; 12800 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|CancelGoal_ros_srv_server:cancel_srv_server_inst|mem_ctrl:goals_canceling_goal_id_mem ; mem_ctrl ; work ; +; |FWFT_FIFO:burst_fifo_inst| ; 3 (0) ; 129 (0) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|CancelGoal_ros_srv_server:cancel_srv_server_inst|mem_ctrl:goals_canceling_goal_id_mem|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 3 (0) ; 129 (0) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|CancelGoal_ros_srv_server:cancel_srv_server_inst|mem_ctrl:goals_canceling_goal_id_mem|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ; +; |a_regfifo:subfifo| ; 3 (3) ; 129 (129) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|CancelGoal_ros_srv_server:cancel_srv_server_inst|mem_ctrl:goals_canceling_goal_id_mem|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|a_regfifo:subfifo ; a_regfifo ; work ; +; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 12800 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|CancelGoal_ros_srv_server:cancel_srv_server_inst|mem_ctrl:goals_canceling_goal_id_mem|single_port_ram:ram_inst ; single_port_ram ; work ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 12800 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|CancelGoal_ros_srv_server:cancel_srv_server_inst|mem_ctrl:goals_canceling_goal_id_mem|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ; +; |altsyncram_hpv3:auto_generated| ; 0 (0) ; 0 (0) ; 12800 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|CancelGoal_ros_srv_server:cancel_srv_server_inst|mem_ctrl:goals_canceling_goal_id_mem|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_hpv3:auto_generated ; altsyncram_hpv3 ; work ; +; |mem_ctrl:goals_canceling_stamp_mem| ; 6 (4) ; 67 (2) ; 6400 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|CancelGoal_ros_srv_server:cancel_srv_server_inst|mem_ctrl:goals_canceling_stamp_mem ; mem_ctrl ; work ; +; |FWFT_FIFO:burst_fifo_inst| ; 2 (0) ; 65 (0) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|CancelGoal_ros_srv_server:cancel_srv_server_inst|mem_ctrl:goals_canceling_stamp_mem|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 2 (0) ; 65 (0) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|CancelGoal_ros_srv_server:cancel_srv_server_inst|mem_ctrl:goals_canceling_stamp_mem|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ; +; |a_regfifo:subfifo| ; 2 (2) ; 65 (65) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|CancelGoal_ros_srv_server:cancel_srv_server_inst|mem_ctrl:goals_canceling_stamp_mem|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|a_regfifo:subfifo ; a_regfifo ; work ; +; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 6400 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|CancelGoal_ros_srv_server:cancel_srv_server_inst|mem_ctrl:goals_canceling_stamp_mem|single_port_ram:ram_inst ; single_port_ram ; work ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 6400 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|CancelGoal_ros_srv_server:cancel_srv_server_inst|mem_ctrl:goals_canceling_stamp_mem|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ; +; |altsyncram_vnv3:auto_generated| ; 0 (0) ; 0 (0) ; 6400 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|CancelGoal_ros_srv_server:cancel_srv_server_inst|mem_ctrl:goals_canceling_stamp_mem|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_vnv3:auto_generated ; altsyncram_vnv3 ; work ; +; |Fibonacci_ros_action_feedback_pub:\feedback_gen:feedback_pub_inst| ; 194 (155) ; 95 (60) ; 3200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|Fibonacci_ros_action_feedback_pub:\feedback_gen:feedback_pub_inst ; Fibonacci_ros_action_feedback_pub ; work ; +; |mem_ctrl:seq_mem| ; 39 (4) ; 35 (2) ; 3200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|Fibonacci_ros_action_feedback_pub:\feedback_gen:feedback_pub_inst|mem_ctrl:seq_mem ; mem_ctrl ; work ; +; |FWFT_FIFO:burst_fifo_inst| ; 35 (0) ; 33 (0) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|Fibonacci_ros_action_feedback_pub:\feedback_gen:feedback_pub_inst|mem_ctrl:seq_mem|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 35 (0) ; 33 (0) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|Fibonacci_ros_action_feedback_pub:\feedback_gen:feedback_pub_inst|mem_ctrl:seq_mem|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ; +; |a_regfifo:subfifo| ; 35 (35) ; 33 (33) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|Fibonacci_ros_action_feedback_pub:\feedback_gen:feedback_pub_inst|mem_ctrl:seq_mem|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|a_regfifo:subfifo ; a_regfifo ; work ; +; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 3200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|Fibonacci_ros_action_feedback_pub:\feedback_gen:feedback_pub_inst|mem_ctrl:seq_mem|single_port_ram:ram_inst ; single_port_ram ; work ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 3200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|Fibonacci_ros_action_feedback_pub:\feedback_gen:feedback_pub_inst|mem_ctrl:seq_mem|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ; +; |altsyncram_qnv3:auto_generated| ; 0 (0) ; 0 (0) ; 3200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|Fibonacci_ros_action_feedback_pub:\feedback_gen:feedback_pub_inst|mem_ctrl:seq_mem|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_qnv3:auto_generated ; altsyncram_qnv3 ; work ; +; |Fibonacci_ros_action_goal_srv_server:goal_srv_server_inst| ; 368 (368) ; 460 (460) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|Fibonacci_ros_action_goal_srv_server:goal_srv_server_inst ; Fibonacci_ros_action_goal_srv_server ; work ; +; |Fibonacci_ros_action_result_srv_server:result_srv_server_inst| ; 458 (419) ; 470 (435) ; 3200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|Fibonacci_ros_action_result_srv_server:result_srv_server_inst ; Fibonacci_ros_action_result_srv_server ; work ; +; |mem_ctrl:seq_mem| ; 39 (5) ; 35 (2) ; 3200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|Fibonacci_ros_action_result_srv_server:result_srv_server_inst|mem_ctrl:seq_mem ; mem_ctrl ; work ; +; |FWFT_FIFO:burst_fifo_inst| ; 34 (0) ; 33 (0) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|Fibonacci_ros_action_result_srv_server:result_srv_server_inst|mem_ctrl:seq_mem|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 34 (0) ; 33 (0) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|Fibonacci_ros_action_result_srv_server:result_srv_server_inst|mem_ctrl:seq_mem|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ; +; |a_regfifo:subfifo| ; 34 (34) ; 33 (33) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|Fibonacci_ros_action_result_srv_server:result_srv_server_inst|mem_ctrl:seq_mem|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|a_regfifo:subfifo ; a_regfifo ; work ; +; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 3200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|Fibonacci_ros_action_result_srv_server:result_srv_server_inst|mem_ctrl:seq_mem|single_port_ram:ram_inst ; single_port_ram ; work ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 3200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|Fibonacci_ros_action_result_srv_server:result_srv_server_inst|mem_ctrl:seq_mem|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ; +; |altsyncram_qnv3:auto_generated| ; 0 (0) ; 0 (0) ; 3200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|Fibonacci_ros_action_result_srv_server:result_srv_server_inst|mem_ctrl:seq_mem|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_qnv3:auto_generated ; altsyncram_qnv3 ; work ; +; |GoalStatusArray_ros_pub:status_pub_inst| ; 254 (226) ; 271 (62) ; 20000 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|GoalStatusArray_ros_pub:status_pub_inst ; GoalStatusArray_ros_pub ; work ; +; |mem_ctrl:status_list_goal_info_goal_id_mem| ; 7 (4) ; 131 (2) ; 12800 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|GoalStatusArray_ros_pub:status_pub_inst|mem_ctrl:status_list_goal_info_goal_id_mem ; mem_ctrl ; work ; +; |FWFT_FIFO:burst_fifo_inst| ; 3 (0) ; 129 (0) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|GoalStatusArray_ros_pub:status_pub_inst|mem_ctrl:status_list_goal_info_goal_id_mem|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 3 (0) ; 129 (0) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|GoalStatusArray_ros_pub:status_pub_inst|mem_ctrl:status_list_goal_info_goal_id_mem|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ; +; |a_regfifo:subfifo| ; 3 (3) ; 129 (129) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|GoalStatusArray_ros_pub:status_pub_inst|mem_ctrl:status_list_goal_info_goal_id_mem|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|a_regfifo:subfifo ; a_regfifo ; work ; +; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 12800 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|GoalStatusArray_ros_pub:status_pub_inst|mem_ctrl:status_list_goal_info_goal_id_mem|single_port_ram:ram_inst ; single_port_ram ; work ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 12800 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|GoalStatusArray_ros_pub:status_pub_inst|mem_ctrl:status_list_goal_info_goal_id_mem|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ; +; |altsyncram_hpv3:auto_generated| ; 0 (0) ; 0 (0) ; 12800 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|GoalStatusArray_ros_pub:status_pub_inst|mem_ctrl:status_list_goal_info_goal_id_mem|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_hpv3:auto_generated ; altsyncram_hpv3 ; work ; +; |mem_ctrl:status_list_goal_info_stamp_mem| ; 6 (4) ; 67 (2) ; 6400 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|GoalStatusArray_ros_pub:status_pub_inst|mem_ctrl:status_list_goal_info_stamp_mem ; mem_ctrl ; work ; +; |FWFT_FIFO:burst_fifo_inst| ; 2 (0) ; 65 (0) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|GoalStatusArray_ros_pub:status_pub_inst|mem_ctrl:status_list_goal_info_stamp_mem|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 2 (0) ; 65 (0) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|GoalStatusArray_ros_pub:status_pub_inst|mem_ctrl:status_list_goal_info_stamp_mem|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ; +; |a_regfifo:subfifo| ; 2 (2) ; 65 (65) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|GoalStatusArray_ros_pub:status_pub_inst|mem_ctrl:status_list_goal_info_stamp_mem|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|a_regfifo:subfifo ; a_regfifo ; work ; +; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 6400 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|GoalStatusArray_ros_pub:status_pub_inst|mem_ctrl:status_list_goal_info_stamp_mem|single_port_ram:ram_inst ; single_port_ram ; work ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 6400 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|GoalStatusArray_ros_pub:status_pub_inst|mem_ctrl:status_list_goal_info_stamp_mem|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ; +; |altsyncram_vnv3:auto_generated| ; 0 (0) ; 0 (0) ; 6400 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|GoalStatusArray_ros_pub:status_pub_inst|mem_ctrl:status_list_goal_info_stamp_mem|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_vnv3:auto_generated ; altsyncram_vnv3 ; work ; +; |mem_ctrl:status_list_status_mem| ; 15 (4) ; 11 (2) ; 800 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|GoalStatusArray_ros_pub:status_pub_inst|mem_ctrl:status_list_status_mem ; mem_ctrl ; work ; +; |FWFT_FIFO:burst_fifo_inst| ; 11 (0) ; 9 (0) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|GoalStatusArray_ros_pub:status_pub_inst|mem_ctrl:status_list_status_mem|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 11 (0) ; 9 (0) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|GoalStatusArray_ros_pub:status_pub_inst|mem_ctrl:status_list_status_mem|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ; +; |a_regfifo:subfifo| ; 11 (11) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|GoalStatusArray_ros_pub:status_pub_inst|mem_ctrl:status_list_status_mem|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|a_regfifo:subfifo ; a_regfifo ; work ; +; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 800 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|GoalStatusArray_ros_pub:status_pub_inst|mem_ctrl:status_list_status_mem|single_port_ram:ram_inst ; single_port_ram ; work ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 800 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|GoalStatusArray_ros_pub:status_pub_inst|mem_ctrl:status_list_status_mem|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ; +; |altsyncram_emv3:auto_generated| ; 0 (0) ; 0 (0) ; 800 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|GoalStatusArray_ros_pub:status_pub_inst|mem_ctrl:status_list_status_mem|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_emv3:auto_generated ; altsyncram_emv3 ; work ; +; |mem_ctrl:\r_seq_gen:0:r_seq_mem| ; 38 (4) ; 35 (2) ; 3200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|mem_ctrl:\r_seq_gen:0:r_seq_mem ; mem_ctrl ; work ; +; |FWFT_FIFO:burst_fifo_inst| ; 34 (0) ; 33 (0) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|mem_ctrl:\r_seq_gen:0:r_seq_mem|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 34 (0) ; 33 (0) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|mem_ctrl:\r_seq_gen:0:r_seq_mem|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ; +; |a_regfifo:subfifo| ; 34 (34) ; 33 (33) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|mem_ctrl:\r_seq_gen:0:r_seq_mem|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|a_regfifo:subfifo ; a_regfifo ; work ; +; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 3200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|mem_ctrl:\r_seq_gen:0:r_seq_mem|single_port_ram:ram_inst ; single_port_ram ; work ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 3200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|mem_ctrl:\r_seq_gen:0:r_seq_mem|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ; +; |altsyncram_qnv3:auto_generated| ; 0 (0) ; 0 (0) ; 3200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|mem_ctrl:\r_seq_gen:0:r_seq_mem|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_qnv3:auto_generated ; altsyncram_qnv3 ; work ; +; |mem_ctrl:r_seq_len_mem| ; 14 (5) ; 10 (2) ; 7 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|mem_ctrl:r_seq_len_mem ; mem_ctrl ; work ; +; |FWFT_FIFO:burst_fifo_inst| ; 9 (0) ; 8 (0) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|mem_ctrl:r_seq_len_mem|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 9 (0) ; 8 (0) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|mem_ctrl:r_seq_len_mem|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ; +; |a_regfifo:subfifo| ; 9 (9) ; 8 (8) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|mem_ctrl:r_seq_len_mem|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|a_regfifo:subfifo ; a_regfifo ; work ; +; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 7 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|mem_ctrl:r_seq_len_mem|single_port_ram:ram_inst ; single_port_ram ; work ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 7 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|mem_ctrl:r_seq_len_mem|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ; +; |altsyncram_6jv3:auto_generated| ; 0 (0) ; 0 (0) ; 7 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|mem_ctrl:r_seq_len_mem|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_6jv3:auto_generated ; altsyncram_6jv3 ; work ; +; |ros_action_server:action_server_inst| ; 2225 (2142) ; 1118 (1072) ; 1632 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|ros_action_server:action_server_inst ; ros_action_server ; work ; +; |mem_ctrl:goal_mem_ctrl_inst| ; 42 (6) ; 23 (2) ; 832 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|ros_action_server:action_server_inst|mem_ctrl:goal_mem_ctrl_inst ; mem_ctrl ; work ; +; |FWFT_FIFO:burst_fifo_inst| ; 36 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|ros_action_server:action_server_inst|mem_ctrl:goal_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 36 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|ros_action_server:action_server_inst|mem_ctrl:goal_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ; +; |scfifo_sgk1:auto_generated| ; 36 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|ros_action_server:action_server_inst|mem_ctrl:goal_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_sgk1:auto_generated ; scfifo_sgk1 ; work ; +; |a_dpfifo_2db1:dpfifo| ; 36 (22) ; 21 (10) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|ros_action_server:action_server_inst|mem_ctrl:goal_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_sgk1:auto_generated|a_dpfifo_2db1:dpfifo ; a_dpfifo_2db1 ; work ; +; |altsyncram_e1k1:FIFOram| ; 0 (0) ; 0 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|ros_action_server:action_server_inst|mem_ctrl:goal_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_sgk1:auto_generated|a_dpfifo_2db1:dpfifo|altsyncram_e1k1:FIFOram ; altsyncram_e1k1 ; work ; +; |cntr_e2b:rd_ptr_msb| ; 4 (4) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|ros_action_server:action_server_inst|mem_ctrl:goal_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_sgk1:auto_generated|a_dpfifo_2db1:dpfifo|cntr_e2b:rd_ptr_msb ; cntr_e2b ; work ; +; |cntr_f2b:wr_ptr| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|ros_action_server:action_server_inst|mem_ctrl:goal_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_sgk1:auto_generated|a_dpfifo_2db1:dpfifo|cntr_f2b:wr_ptr ; cntr_f2b ; work ; +; |cntr_r27:usedw_counter| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|ros_action_server:action_server_inst|mem_ctrl:goal_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_sgk1:auto_generated|a_dpfifo_2db1:dpfifo|cntr_r27:usedw_counter ; cntr_r27 ; work ; +; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 320 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|ros_action_server:action_server_inst|mem_ctrl:goal_mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 320 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|ros_action_server:action_server_inst|mem_ctrl:goal_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ; +; |altsyncram_7mv3:auto_generated| ; 0 (0) ; 0 (0) ; 320 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|ros_action_server:action_server_inst|mem_ctrl:goal_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_7mv3:auto_generated ; altsyncram_7mv3 ; work ; +; |mem_ctrl:rrq_mem_ctrl_inst| ; 41 (6) ; 23 (2) ; 800 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|ros_action_server:action_server_inst|mem_ctrl:rrq_mem_ctrl_inst ; mem_ctrl ; work ; +; |FWFT_FIFO:burst_fifo_inst| ; 35 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|ros_action_server:action_server_inst|mem_ctrl:rrq_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 35 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|ros_action_server:action_server_inst|mem_ctrl:rrq_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ; +; |scfifo_kfk1:auto_generated| ; 35 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|ros_action_server:action_server_inst|mem_ctrl:rrq_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated ; scfifo_kfk1 ; work ; +; |a_dpfifo_qbb1:dpfifo| ; 35 (21) ; 21 (10) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|ros_action_server:action_server_inst|mem_ctrl:rrq_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo ; a_dpfifo_qbb1 ; work ; +; |altsyncram_e1k1:FIFOram| ; 0 (0) ; 0 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|ros_action_server:action_server_inst|mem_ctrl:rrq_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo|altsyncram_e1k1:FIFOram ; altsyncram_e1k1 ; work ; +; |cntr_e2b:rd_ptr_msb| ; 4 (4) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|ros_action_server:action_server_inst|mem_ctrl:rrq_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo|cntr_e2b:rd_ptr_msb ; cntr_e2b ; work ; +; |cntr_f2b:wr_ptr| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|ros_action_server:action_server_inst|mem_ctrl:rrq_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo|cntr_f2b:wr_ptr ; cntr_f2b ; work ; +; |cntr_r27:usedw_counter| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|ros_action_server:action_server_inst|mem_ctrl:rrq_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo|cntr_r27:usedw_counter ; cntr_r27 ; work ; +; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 288 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|ros_action_server:action_server_inst|mem_ctrl:rrq_mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 288 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|ros_action_server:action_server_inst|mem_ctrl:rrq_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ; +; |altsyncram_vkv3:auto_generated| ; 0 (0) ; 0 (0) ; 288 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|ros_action_server:action_server_inst|mem_ctrl:rrq_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_vkv3:auto_generated ; altsyncram_vkv3 ; work ; +; |dds_reader:\dds_endpoint_gen:0:dds_reader_inst| ; 2371 (2263) ; 606 (551) ; 20160 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:0:dds_reader_inst ; dds_reader ; work ; +; |key_holder:key_holder_inst| ; 0 (0) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:0:dds_reader_inst|key_holder:key_holder_inst ; key_holder ; work ; +; |mem_ctrl:payload_mem_ctrl_inst| ; 61 (14) ; 31 (2) ; 16128 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:0:dds_reader_inst|mem_ctrl:payload_mem_ctrl_inst ; mem_ctrl ; work ; +; |FWFT_FIFO:burst_fifo_inst| ; 47 (2) ; 29 (0) ; 2048 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:0:dds_reader_inst|mem_ctrl:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 45 (0) ; 29 (0) ; 2048 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:0:dds_reader_inst|mem_ctrl:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ; +; |scfifo_1hk1:auto_generated| ; 45 (0) ; 29 (0) ; 2048 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:0:dds_reader_inst|mem_ctrl:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_1hk1:auto_generated ; scfifo_1hk1 ; work ; +; |a_dpfifo_7db1:dpfifo| ; 45 (25) ; 29 (12) ; 2048 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:0:dds_reader_inst|mem_ctrl:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_1hk1:auto_generated|a_dpfifo_7db1:dpfifo ; a_dpfifo_7db1 ; work ; +; |altsyncram_o1k1:FIFOram| ; 0 (0) ; 0 (0) ; 2048 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:0:dds_reader_inst|mem_ctrl:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_1hk1:auto_generated|a_dpfifo_7db1:dpfifo|altsyncram_o1k1:FIFOram ; altsyncram_o1k1 ; work ; +; |cntr_g2b:rd_ptr_msb| ; 6 (6) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:0:dds_reader_inst|mem_ctrl:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_1hk1:auto_generated|a_dpfifo_7db1:dpfifo|cntr_g2b:rd_ptr_msb ; cntr_g2b ; work ; +; |cntr_h2b:wr_ptr| ; 7 (7) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:0:dds_reader_inst|mem_ctrl:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_1hk1:auto_generated|a_dpfifo_7db1:dpfifo|cntr_h2b:wr_ptr ; cntr_h2b ; work ; +; |cntr_t27:usedw_counter| ; 7 (7) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:0:dds_reader_inst|mem_ctrl:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_1hk1:auto_generated|a_dpfifo_7db1:dpfifo|cntr_t27:usedw_counter ; cntr_t27 ; work ; +; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 14080 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:0:dds_reader_inst|mem_ctrl:payload_mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 14080 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:0:dds_reader_inst|mem_ctrl:payload_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ; +; |altsyncram_3ov3:auto_generated| ; 0 (0) ; 0 (0) ; 14080 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:0:dds_reader_inst|mem_ctrl:payload_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_3ov3:auto_generated ; altsyncram_3ov3 ; work ; +; |mem_ctrl:sample_mem_ctrl_inst| ; 47 (7) ; 23 (2) ; 4032 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:0:dds_reader_inst|mem_ctrl:sample_mem_ctrl_inst ; mem_ctrl ; work ; +; |FWFT_FIFO:burst_fifo_inst| ; 40 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:0:dds_reader_inst|mem_ctrl:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 40 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:0:dds_reader_inst|mem_ctrl:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ; +; |scfifo_sgk1:auto_generated| ; 40 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:0:dds_reader_inst|mem_ctrl:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_sgk1:auto_generated ; scfifo_sgk1 ; work ; +; |a_dpfifo_2db1:dpfifo| ; 40 (26) ; 21 (10) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:0:dds_reader_inst|mem_ctrl:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_sgk1:auto_generated|a_dpfifo_2db1:dpfifo ; a_dpfifo_2db1 ; work ; +; |altsyncram_e1k1:FIFOram| ; 0 (0) ; 0 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:0:dds_reader_inst|mem_ctrl:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_sgk1:auto_generated|a_dpfifo_2db1:dpfifo|altsyncram_e1k1:FIFOram ; altsyncram_e1k1 ; work ; +; |cntr_e2b:rd_ptr_msb| ; 4 (4) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:0:dds_reader_inst|mem_ctrl:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_sgk1:auto_generated|a_dpfifo_2db1:dpfifo|cntr_e2b:rd_ptr_msb ; cntr_e2b ; work ; +; |cntr_f2b:wr_ptr| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:0:dds_reader_inst|mem_ctrl:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_sgk1:auto_generated|a_dpfifo_2db1:dpfifo|cntr_f2b:wr_ptr ; cntr_f2b ; work ; +; |cntr_r27:usedw_counter| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:0:dds_reader_inst|mem_ctrl:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_sgk1:auto_generated|a_dpfifo_2db1:dpfifo|cntr_r27:usedw_counter ; cntr_r27 ; work ; +; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 3520 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:0:dds_reader_inst|mem_ctrl:sample_mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 3520 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:0:dds_reader_inst|mem_ctrl:sample_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ; +; |altsyncram_rnv3:auto_generated| ; 0 (0) ; 0 (0) ; 3520 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:0:dds_reader_inst|mem_ctrl:sample_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_rnv3:auto_generated ; altsyncram_rnv3 ; work ; +; |dds_reader:\dds_endpoint_gen:1:dds_reader_inst| ; 2363 (2258) ; 605 (551) ; 18752 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:1:dds_reader_inst ; dds_reader ; work ; +; |mem_ctrl:payload_mem_ctrl_inst| ; 60 (15) ; 31 (2) ; 14720 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:1:dds_reader_inst|mem_ctrl:payload_mem_ctrl_inst ; mem_ctrl ; work ; +; |FWFT_FIFO:burst_fifo_inst| ; 45 (1) ; 29 (0) ; 2048 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:1:dds_reader_inst|mem_ctrl:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 44 (0) ; 29 (0) ; 2048 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:1:dds_reader_inst|mem_ctrl:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ; +; |scfifo_6hk1:auto_generated| ; 44 (0) ; 29 (0) ; 2048 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:1:dds_reader_inst|mem_ctrl:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_6hk1:auto_generated ; scfifo_6hk1 ; work ; +; |a_dpfifo_cdb1:dpfifo| ; 44 (24) ; 29 (12) ; 2048 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:1:dds_reader_inst|mem_ctrl:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_6hk1:auto_generated|a_dpfifo_cdb1:dpfifo ; a_dpfifo_cdb1 ; work ; +; |altsyncram_o1k1:FIFOram| ; 0 (0) ; 0 (0) ; 2048 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:1:dds_reader_inst|mem_ctrl:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_6hk1:auto_generated|a_dpfifo_cdb1:dpfifo|altsyncram_o1k1:FIFOram ; altsyncram_o1k1 ; work ; +; |cntr_g2b:rd_ptr_msb| ; 6 (6) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:1:dds_reader_inst|mem_ctrl:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_6hk1:auto_generated|a_dpfifo_cdb1:dpfifo|cntr_g2b:rd_ptr_msb ; cntr_g2b ; work ; +; |cntr_h2b:wr_ptr| ; 7 (7) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:1:dds_reader_inst|mem_ctrl:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_6hk1:auto_generated|a_dpfifo_cdb1:dpfifo|cntr_h2b:wr_ptr ; cntr_h2b ; work ; +; |cntr_t27:usedw_counter| ; 7 (7) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:1:dds_reader_inst|mem_ctrl:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_6hk1:auto_generated|a_dpfifo_cdb1:dpfifo|cntr_t27:usedw_counter ; cntr_t27 ; work ; +; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 12672 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:1:dds_reader_inst|mem_ctrl:payload_mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 12672 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:1:dds_reader_inst|mem_ctrl:payload_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ; +; |altsyncram_dov3:auto_generated| ; 0 (0) ; 0 (0) ; 12672 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:1:dds_reader_inst|mem_ctrl:payload_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_dov3:auto_generated ; altsyncram_dov3 ; work ; +; |mem_ctrl:sample_mem_ctrl_inst| ; 45 (7) ; 23 (2) ; 4032 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:1:dds_reader_inst|mem_ctrl:sample_mem_ctrl_inst ; mem_ctrl ; work ; +; |FWFT_FIFO:burst_fifo_inst| ; 38 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:1:dds_reader_inst|mem_ctrl:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 38 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:1:dds_reader_inst|mem_ctrl:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ; +; |scfifo_sgk1:auto_generated| ; 38 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:1:dds_reader_inst|mem_ctrl:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_sgk1:auto_generated ; scfifo_sgk1 ; work ; +; |a_dpfifo_2db1:dpfifo| ; 38 (24) ; 21 (10) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:1:dds_reader_inst|mem_ctrl:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_sgk1:auto_generated|a_dpfifo_2db1:dpfifo ; a_dpfifo_2db1 ; work ; +; |altsyncram_e1k1:FIFOram| ; 0 (0) ; 0 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:1:dds_reader_inst|mem_ctrl:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_sgk1:auto_generated|a_dpfifo_2db1:dpfifo|altsyncram_e1k1:FIFOram ; altsyncram_e1k1 ; work ; +; |cntr_e2b:rd_ptr_msb| ; 4 (4) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:1:dds_reader_inst|mem_ctrl:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_sgk1:auto_generated|a_dpfifo_2db1:dpfifo|cntr_e2b:rd_ptr_msb ; cntr_e2b ; work ; +; |cntr_f2b:wr_ptr| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:1:dds_reader_inst|mem_ctrl:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_sgk1:auto_generated|a_dpfifo_2db1:dpfifo|cntr_f2b:wr_ptr ; cntr_f2b ; work ; +; |cntr_r27:usedw_counter| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:1:dds_reader_inst|mem_ctrl:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_sgk1:auto_generated|a_dpfifo_2db1:dpfifo|cntr_r27:usedw_counter ; cntr_r27 ; work ; +; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 3520 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:1:dds_reader_inst|mem_ctrl:sample_mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 3520 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:1:dds_reader_inst|mem_ctrl:sample_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ; +; |altsyncram_rnv3:auto_generated| ; 0 (0) ; 0 (0) ; 3520 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:1:dds_reader_inst|mem_ctrl:sample_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_rnv3:auto_generated ; altsyncram_rnv3 ; work ; +; |dds_reader:\dds_endpoint_gen:2:dds_reader_inst| ; 2372 (2266) ; 605 (551) ; 21568 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:2:dds_reader_inst ; dds_reader ; work ; +; |mem_ctrl:payload_mem_ctrl_inst| ; 61 (15) ; 31 (2) ; 17536 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:2:dds_reader_inst|mem_ctrl:payload_mem_ctrl_inst ; mem_ctrl ; work ; +; |FWFT_FIFO:burst_fifo_inst| ; 46 (2) ; 29 (0) ; 2048 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:2:dds_reader_inst|mem_ctrl:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 44 (0) ; 29 (0) ; 2048 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:2:dds_reader_inst|mem_ctrl:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ; +; |scfifo_7hk1:auto_generated| ; 44 (0) ; 29 (0) ; 2048 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:2:dds_reader_inst|mem_ctrl:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_7hk1:auto_generated ; scfifo_7hk1 ; work ; +; |a_dpfifo_ddb1:dpfifo| ; 44 (24) ; 29 (12) ; 2048 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:2:dds_reader_inst|mem_ctrl:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_7hk1:auto_generated|a_dpfifo_ddb1:dpfifo ; a_dpfifo_ddb1 ; work ; +; |altsyncram_o1k1:FIFOram| ; 0 (0) ; 0 (0) ; 2048 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:2:dds_reader_inst|mem_ctrl:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_7hk1:auto_generated|a_dpfifo_ddb1:dpfifo|altsyncram_o1k1:FIFOram ; altsyncram_o1k1 ; work ; +; |cntr_g2b:rd_ptr_msb| ; 6 (6) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:2:dds_reader_inst|mem_ctrl:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_7hk1:auto_generated|a_dpfifo_ddb1:dpfifo|cntr_g2b:rd_ptr_msb ; cntr_g2b ; work ; +; |cntr_h2b:wr_ptr| ; 7 (7) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:2:dds_reader_inst|mem_ctrl:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_7hk1:auto_generated|a_dpfifo_ddb1:dpfifo|cntr_h2b:wr_ptr ; cntr_h2b ; work ; +; |cntr_t27:usedw_counter| ; 7 (7) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:2:dds_reader_inst|mem_ctrl:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_7hk1:auto_generated|a_dpfifo_ddb1:dpfifo|cntr_t27:usedw_counter ; cntr_t27 ; work ; +; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 15488 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:2:dds_reader_inst|mem_ctrl:payload_mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 15488 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:2:dds_reader_inst|mem_ctrl:payload_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ; +; |altsyncram_bov3:auto_generated| ; 0 (0) ; 0 (0) ; 15488 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:2:dds_reader_inst|mem_ctrl:payload_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_bov3:auto_generated ; altsyncram_bov3 ; work ; +; |mem_ctrl:sample_mem_ctrl_inst| ; 45 (7) ; 23 (2) ; 4032 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:2:dds_reader_inst|mem_ctrl:sample_mem_ctrl_inst ; mem_ctrl ; work ; +; |FWFT_FIFO:burst_fifo_inst| ; 38 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:2:dds_reader_inst|mem_ctrl:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 38 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:2:dds_reader_inst|mem_ctrl:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ; +; |scfifo_sgk1:auto_generated| ; 38 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:2:dds_reader_inst|mem_ctrl:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_sgk1:auto_generated ; scfifo_sgk1 ; work ; +; |a_dpfifo_2db1:dpfifo| ; 38 (24) ; 21 (10) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:2:dds_reader_inst|mem_ctrl:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_sgk1:auto_generated|a_dpfifo_2db1:dpfifo ; a_dpfifo_2db1 ; work ; +; |altsyncram_e1k1:FIFOram| ; 0 (0) ; 0 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:2:dds_reader_inst|mem_ctrl:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_sgk1:auto_generated|a_dpfifo_2db1:dpfifo|altsyncram_e1k1:FIFOram ; altsyncram_e1k1 ; work ; +; |cntr_e2b:rd_ptr_msb| ; 4 (4) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:2:dds_reader_inst|mem_ctrl:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_sgk1:auto_generated|a_dpfifo_2db1:dpfifo|cntr_e2b:rd_ptr_msb ; cntr_e2b ; work ; +; |cntr_f2b:wr_ptr| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:2:dds_reader_inst|mem_ctrl:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_sgk1:auto_generated|a_dpfifo_2db1:dpfifo|cntr_f2b:wr_ptr ; cntr_f2b ; work ; +; |cntr_r27:usedw_counter| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:2:dds_reader_inst|mem_ctrl:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_sgk1:auto_generated|a_dpfifo_2db1:dpfifo|cntr_r27:usedw_counter ; cntr_r27 ; work ; +; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 3520 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:2:dds_reader_inst|mem_ctrl:sample_mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 3520 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:2:dds_reader_inst|mem_ctrl:sample_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ; +; |altsyncram_rnv3:auto_generated| ; 0 (0) ; 0 (0) ; 3520 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:2:dds_reader_inst|mem_ctrl:sample_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_rnv3:auto_generated ; altsyncram_rnv3 ; work ; +; |dds_writer:\dds_endpoint_w_if:dds_writer_inst| ; 6798 (4926) ; 4149 (1812) ; 428928 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst ; dds_writer ; work ; +; |key_holder:\key_holder_gen:0:key_holder_inst| ; 217 (184) ; 384 (249) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|key_holder:\key_holder_gen:0:key_holder_inst ; key_holder ; work ; +; |key_hash_generator:key_hash_generator_inst| ; 33 (33) ; 135 (135) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|key_holder:\key_holder_gen:0:key_holder_inst|key_hash_generator:key_hash_generator_inst ; key_hash_generator ; work ; +; |key_holder:\key_holder_gen:1:key_holder_inst| ; 215 (183) ; 384 (249) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|key_holder:\key_holder_gen:1:key_holder_inst ; key_holder ; work ; +; |key_hash_generator:key_hash_generator_inst| ; 32 (32) ; 135 (135) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|key_holder:\key_holder_gen:1:key_holder_inst|key_hash_generator:key_hash_generator_inst ; key_hash_generator ; work ; +; |key_holder:\key_holder_gen:2:key_holder_inst| ; 217 (182) ; 384 (249) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|key_holder:\key_holder_gen:2:key_holder_inst ; key_holder ; work ; +; |key_hash_generator:key_hash_generator_inst| ; 35 (35) ; 135 (135) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|key_holder:\key_holder_gen:2:key_holder_inst|key_hash_generator:key_hash_generator_inst ; key_hash_generator ; work ; +; |key_holder:\key_holder_gen:3:key_holder_inst| ; 215 (183) ; 384 (249) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|key_holder:\key_holder_gen:3:key_holder_inst ; key_holder ; work ; +; |key_hash_generator:key_hash_generator_inst| ; 32 (32) ; 135 (135) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|key_holder:\key_holder_gen:3:key_holder_inst|key_hash_generator:key_hash_generator_inst ; key_hash_generator ; work ; +; |key_holder:\key_holder_gen:4:key_holder_inst| ; 214 (181) ; 384 (249) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|key_holder:\key_holder_gen:4:key_holder_inst ; key_holder ; work ; +; |key_hash_generator:key_hash_generator_inst| ; 33 (33) ; 135 (135) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|key_holder:\key_holder_gen:4:key_holder_inst|key_hash_generator:key_hash_generator_inst ; key_hash_generator ; work ; +; |mem_ctrl:\instance_mem_ctrl_gen:0:instance_mem_ctrl_inst| ; 40 (7) ; 23 (2) ; 800 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:0:instance_mem_ctrl_inst ; mem_ctrl ; work ; +; |FWFT_FIFO:burst_fifo_inst| ; 33 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:0:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 33 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:0:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ; +; |scfifo_kfk1:auto_generated| ; 33 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:0:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated ; scfifo_kfk1 ; work ; +; |a_dpfifo_qbb1:dpfifo| ; 33 (19) ; 21 (10) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:0:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo ; a_dpfifo_qbb1 ; work ; +; |altsyncram_e1k1:FIFOram| ; 0 (0) ; 0 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:0:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo|altsyncram_e1k1:FIFOram ; altsyncram_e1k1 ; work ; +; |cntr_e2b:rd_ptr_msb| ; 4 (4) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:0:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo|cntr_e2b:rd_ptr_msb ; cntr_e2b ; work ; +; |cntr_f2b:wr_ptr| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:0:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo|cntr_f2b:wr_ptr ; cntr_f2b ; work ; +; |cntr_r27:usedw_counter| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:0:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo|cntr_r27:usedw_counter ; cntr_r27 ; work ; +; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 288 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:0:instance_mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 288 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:0:instance_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ; +; |altsyncram_vkv3:auto_generated| ; 0 (0) ; 0 (0) ; 288 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:0:instance_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_vkv3:auto_generated ; altsyncram_vkv3 ; work ; +; |mem_ctrl:\instance_mem_ctrl_gen:1:instance_mem_ctrl_inst| ; 38 (5) ; 23 (2) ; 800 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:1:instance_mem_ctrl_inst ; mem_ctrl ; work ; +; |FWFT_FIFO:burst_fifo_inst| ; 33 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:1:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 33 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:1:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ; +; |scfifo_kfk1:auto_generated| ; 33 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:1:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated ; scfifo_kfk1 ; work ; +; |a_dpfifo_qbb1:dpfifo| ; 33 (19) ; 21 (10) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:1:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo ; a_dpfifo_qbb1 ; work ; +; |altsyncram_e1k1:FIFOram| ; 0 (0) ; 0 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:1:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo|altsyncram_e1k1:FIFOram ; altsyncram_e1k1 ; work ; +; |cntr_e2b:rd_ptr_msb| ; 4 (4) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:1:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo|cntr_e2b:rd_ptr_msb ; cntr_e2b ; work ; +; |cntr_f2b:wr_ptr| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:1:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo|cntr_f2b:wr_ptr ; cntr_f2b ; work ; +; |cntr_r27:usedw_counter| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:1:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo|cntr_r27:usedw_counter ; cntr_r27 ; work ; +; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 288 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:1:instance_mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 288 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:1:instance_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ; +; |altsyncram_vkv3:auto_generated| ; 0 (0) ; 0 (0) ; 288 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:1:instance_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_vkv3:auto_generated ; altsyncram_vkv3 ; work ; +; |mem_ctrl:\instance_mem_ctrl_gen:2:instance_mem_ctrl_inst| ; 38 (5) ; 23 (2) ; 800 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:2:instance_mem_ctrl_inst ; mem_ctrl ; work ; +; |FWFT_FIFO:burst_fifo_inst| ; 33 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:2:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 33 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:2:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ; +; |scfifo_kfk1:auto_generated| ; 33 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:2:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated ; scfifo_kfk1 ; work ; +; |a_dpfifo_qbb1:dpfifo| ; 33 (19) ; 21 (10) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:2:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo ; a_dpfifo_qbb1 ; work ; +; |altsyncram_e1k1:FIFOram| ; 0 (0) ; 0 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:2:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo|altsyncram_e1k1:FIFOram ; altsyncram_e1k1 ; work ; +; |cntr_e2b:rd_ptr_msb| ; 4 (4) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:2:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo|cntr_e2b:rd_ptr_msb ; cntr_e2b ; work ; +; |cntr_f2b:wr_ptr| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:2:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo|cntr_f2b:wr_ptr ; cntr_f2b ; work ; +; |cntr_r27:usedw_counter| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:2:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo|cntr_r27:usedw_counter ; cntr_r27 ; work ; +; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 288 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:2:instance_mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 288 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:2:instance_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ; +; |altsyncram_vkv3:auto_generated| ; 0 (0) ; 0 (0) ; 288 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:2:instance_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_vkv3:auto_generated ; altsyncram_vkv3 ; work ; +; |mem_ctrl:\instance_mem_ctrl_gen:3:instance_mem_ctrl_inst| ; 38 (5) ; 23 (2) ; 800 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:3:instance_mem_ctrl_inst ; mem_ctrl ; work ; +; |FWFT_FIFO:burst_fifo_inst| ; 33 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:3:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 33 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:3:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ; +; |scfifo_kfk1:auto_generated| ; 33 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:3:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated ; scfifo_kfk1 ; work ; +; |a_dpfifo_qbb1:dpfifo| ; 33 (19) ; 21 (10) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:3:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo ; a_dpfifo_qbb1 ; work ; +; |altsyncram_e1k1:FIFOram| ; 0 (0) ; 0 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:3:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo|altsyncram_e1k1:FIFOram ; altsyncram_e1k1 ; work ; +; |cntr_e2b:rd_ptr_msb| ; 4 (4) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:3:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo|cntr_e2b:rd_ptr_msb ; cntr_e2b ; work ; +; |cntr_f2b:wr_ptr| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:3:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo|cntr_f2b:wr_ptr ; cntr_f2b ; work ; +; |cntr_r27:usedw_counter| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:3:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo|cntr_r27:usedw_counter ; cntr_r27 ; work ; +; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 288 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:3:instance_mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 288 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:3:instance_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ; +; |altsyncram_vkv3:auto_generated| ; 0 (0) ; 0 (0) ; 288 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:3:instance_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_vkv3:auto_generated ; altsyncram_vkv3 ; work ; +; |mem_ctrl:\instance_mem_ctrl_gen:4:instance_mem_ctrl_inst| ; 38 (5) ; 23 (2) ; 800 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:4:instance_mem_ctrl_inst ; mem_ctrl ; work ; +; |FWFT_FIFO:burst_fifo_inst| ; 33 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:4:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 33 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:4:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ; +; |scfifo_kfk1:auto_generated| ; 33 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:4:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated ; scfifo_kfk1 ; work ; +; |a_dpfifo_qbb1:dpfifo| ; 33 (19) ; 21 (10) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:4:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo ; a_dpfifo_qbb1 ; work ; +; |altsyncram_e1k1:FIFOram| ; 0 (0) ; 0 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:4:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo|altsyncram_e1k1:FIFOram ; altsyncram_e1k1 ; work ; +; |cntr_e2b:rd_ptr_msb| ; 4 (4) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:4:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo|cntr_e2b:rd_ptr_msb ; cntr_e2b ; work ; +; |cntr_f2b:wr_ptr| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:4:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo|cntr_f2b:wr_ptr ; cntr_f2b ; work ; +; |cntr_r27:usedw_counter| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:4:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo|cntr_r27:usedw_counter ; cntr_r27 ; work ; +; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 288 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:4:instance_mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 288 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:4:instance_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ; +; |altsyncram_vkv3:auto_generated| ; 0 (0) ; 0 (0) ; 288 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:4:instance_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_vkv3:auto_generated ; altsyncram_vkv3 ; work ; +; |mem_ctrl:\payload_mem_ctrl_gen:0:payload_mem_ctrl_inst| ; 40 (6) ; 23 (2) ; 3680 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:0:payload_mem_ctrl_inst ; mem_ctrl ; work ; +; |FWFT_FIFO:burst_fifo_inst| ; 34 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:0:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 34 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:0:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ; +; |scfifo_kfk1:auto_generated| ; 34 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:0:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated ; scfifo_kfk1 ; work ; +; |a_dpfifo_qbb1:dpfifo| ; 34 (20) ; 21 (10) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:0:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo ; a_dpfifo_qbb1 ; work ; +; |altsyncram_e1k1:FIFOram| ; 0 (0) ; 0 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:0:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo|altsyncram_e1k1:FIFOram ; altsyncram_e1k1 ; work ; +; |cntr_e2b:rd_ptr_msb| ; 4 (4) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:0:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo|cntr_e2b:rd_ptr_msb ; cntr_e2b ; work ; +; |cntr_f2b:wr_ptr| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:0:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo|cntr_f2b:wr_ptr ; cntr_f2b ; work ; +; |cntr_r27:usedw_counter| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:0:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo|cntr_r27:usedw_counter ; cntr_r27 ; work ; +; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 3168 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:0:payload_mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 3168 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:0:payload_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ; +; |altsyncram_aov3:auto_generated| ; 0 (0) ; 0 (0) ; 3168 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:0:payload_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_aov3:auto_generated ; altsyncram_aov3 ; work ; +; |mem_ctrl:\payload_mem_ctrl_gen:1:payload_mem_ctrl_inst| ; 69 (14) ; 35 (2) ; 41760 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:1:payload_mem_ctrl_inst ; mem_ctrl ; work ; +; |FWFT_FIFO:burst_fifo_inst| ; 55 (5) ; 33 (0) ; 4096 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:1:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 50 (0) ; 33 (0) ; 4096 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:1:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ; +; |scfifo_oik1:auto_generated| ; 50 (0) ; 33 (0) ; 4096 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:1:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_oik1:auto_generated ; scfifo_oik1 ; work ; +; |a_dpfifo_ueb1:dpfifo| ; 50 (27) ; 33 (13) ; 4096 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:1:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_oik1:auto_generated|a_dpfifo_ueb1:dpfifo ; a_dpfifo_ueb1 ; work ; +; |altsyncram_s4k1:FIFOram| ; 0 (0) ; 0 (0) ; 4096 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:1:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_oik1:auto_generated|a_dpfifo_ueb1:dpfifo|altsyncram_s4k1:FIFOram ; altsyncram_s4k1 ; work ; +; |cntr_h2b:rd_ptr_msb| ; 7 (7) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:1:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_oik1:auto_generated|a_dpfifo_ueb1:dpfifo|cntr_h2b:rd_ptr_msb ; cntr_h2b ; work ; +; |cntr_i2b:wr_ptr| ; 8 (8) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:1:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_oik1:auto_generated|a_dpfifo_ueb1:dpfifo|cntr_i2b:wr_ptr ; cntr_i2b ; work ; +; |cntr_u27:usedw_counter| ; 8 (8) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:1:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_oik1:auto_generated|a_dpfifo_ueb1:dpfifo|cntr_u27:usedw_counter ; cntr_u27 ; work ; +; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 37664 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:1:payload_mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 37664 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:1:payload_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ; +; |altsyncram_6rv3:auto_generated| ; 0 (0) ; 0 (0) ; 37664 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:1:payload_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_6rv3:auto_generated ; altsyncram_6rv3 ; work ; +; |mem_ctrl:\payload_mem_ctrl_gen:2:payload_mem_ctrl_inst| ; 90 (19) ; 47 (2) ; 246432 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:2:payload_mem_ctrl_inst ; mem_ctrl ; work ; +; |FWFT_FIFO:burst_fifo_inst| ; 71 (5) ; 45 (0) ; 32768 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:2:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 66 (0) ; 45 (0) ; 32768 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:2:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ; +; |scfifo_5kk1:auto_generated| ; 66 (0) ; 45 (0) ; 32768 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:2:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_5kk1:auto_generated ; scfifo_5kk1 ; work ; +; |a_dpfifo_bgb1:dpfifo| ; 66 (34) ; 45 (16) ; 32768 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:2:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_5kk1:auto_generated|a_dpfifo_bgb1:dpfifo ; a_dpfifo_bgb1 ; work ; +; |altsyncram_8ak1:FIFOram| ; 0 (0) ; 0 (0) ; 32768 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:2:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_5kk1:auto_generated|a_dpfifo_bgb1:dpfifo|altsyncram_8ak1:FIFOram ; altsyncram_8ak1 ; work ; +; |cntr_847:usedw_counter| ; 11 (11) ; 10 (10) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:2:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_5kk1:auto_generated|a_dpfifo_bgb1:dpfifo|cntr_847:usedw_counter ; cntr_847 ; work ; +; |cntr_k2b:rd_ptr_msb| ; 10 (10) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:2:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_5kk1:auto_generated|a_dpfifo_bgb1:dpfifo|cntr_k2b:rd_ptr_msb ; cntr_k2b ; work ; +; |cntr_s3b:wr_ptr| ; 11 (11) ; 10 (10) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:2:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_5kk1:auto_generated|a_dpfifo_bgb1:dpfifo|cntr_s3b:wr_ptr ; cntr_s3b ; work ; +; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 213664 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:2:payload_mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 213664 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:2:payload_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ; +; |altsyncram_grv3:auto_generated| ; 0 (0) ; 0 (0) ; 213664 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:2:payload_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_grv3:auto_generated ; altsyncram_grv3 ; work ; +; |mem_ctrl:\payload_mem_ctrl_gen:3:payload_mem_ctrl_inst| ; 72 (15) ; 35 (2) ; 41408 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:3:payload_mem_ctrl_inst ; mem_ctrl ; work ; +; |FWFT_FIFO:burst_fifo_inst| ; 57 (7) ; 33 (0) ; 4096 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:3:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 50 (0) ; 33 (0) ; 4096 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:3:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ; +; |scfifo_pik1:auto_generated| ; 50 (0) ; 33 (0) ; 4096 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:3:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_pik1:auto_generated ; scfifo_pik1 ; work ; +; |a_dpfifo_veb1:dpfifo| ; 50 (27) ; 33 (13) ; 4096 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:3:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_pik1:auto_generated|a_dpfifo_veb1:dpfifo ; a_dpfifo_veb1 ; work ; +; |altsyncram_s4k1:FIFOram| ; 0 (0) ; 0 (0) ; 4096 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:3:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_pik1:auto_generated|a_dpfifo_veb1:dpfifo|altsyncram_s4k1:FIFOram ; altsyncram_s4k1 ; work ; +; |cntr_h2b:rd_ptr_msb| ; 7 (7) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:3:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_pik1:auto_generated|a_dpfifo_veb1:dpfifo|cntr_h2b:rd_ptr_msb ; cntr_h2b ; work ; +; |cntr_i2b:wr_ptr| ; 8 (8) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:3:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_pik1:auto_generated|a_dpfifo_veb1:dpfifo|cntr_i2b:wr_ptr ; cntr_i2b ; work ; +; |cntr_u27:usedw_counter| ; 8 (8) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:3:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_pik1:auto_generated|a_dpfifo_veb1:dpfifo|cntr_u27:usedw_counter ; cntr_u27 ; work ; +; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 37312 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:3:payload_mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 37312 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:3:payload_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ; +; |altsyncram_5rv3:auto_generated| ; 0 (0) ; 0 (0) ; 37312 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:3:payload_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_5rv3:auto_generated ; altsyncram_5rv3 ; work ; +; |mem_ctrl:\payload_mem_ctrl_gen:4:payload_mem_ctrl_inst| ; 90 (17) ; 47 (2) ; 72896 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:4:payload_mem_ctrl_inst ; mem_ctrl ; work ; +; |FWFT_FIFO:burst_fifo_inst| ; 73 (8) ; 45 (0) ; 32768 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:4:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 65 (0) ; 45 (0) ; 32768 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:4:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ; +; |scfifo_7kk1:auto_generated| ; 65 (0) ; 45 (0) ; 32768 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:4:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_7kk1:auto_generated ; scfifo_7kk1 ; work ; +; |a_dpfifo_dgb1:dpfifo| ; 65 (33) ; 45 (16) ; 32768 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:4:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_7kk1:auto_generated|a_dpfifo_dgb1:dpfifo ; a_dpfifo_dgb1 ; work ; +; |altsyncram_8ak1:FIFOram| ; 0 (0) ; 0 (0) ; 32768 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:4:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_7kk1:auto_generated|a_dpfifo_dgb1:dpfifo|altsyncram_8ak1:FIFOram ; altsyncram_8ak1 ; work ; +; |cntr_847:usedw_counter| ; 11 (11) ; 10 (10) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:4:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_7kk1:auto_generated|a_dpfifo_dgb1:dpfifo|cntr_847:usedw_counter ; cntr_847 ; work ; +; |cntr_k2b:rd_ptr_msb| ; 10 (10) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:4:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_7kk1:auto_generated|a_dpfifo_dgb1:dpfifo|cntr_k2b:rd_ptr_msb ; cntr_k2b ; work ; +; |cntr_s3b:wr_ptr| ; 11 (11) ; 10 (10) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:4:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_7kk1:auto_generated|a_dpfifo_dgb1:dpfifo|cntr_s3b:wr_ptr ; cntr_s3b ; work ; +; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 40128 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:4:payload_mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 40128 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:4:payload_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ; +; |altsyncram_7rv3:auto_generated| ; 0 (0) ; 0 (0) ; 40128 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:4:payload_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_7rv3:auto_generated ; altsyncram_7rv3 ; work ; +; |mem_ctrl:\sample_mem_ctrl_gen:0:sample_mem_ctrl_inst| ; 50 (9) ; 23 (2) ; 4384 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:0:sample_mem_ctrl_inst ; mem_ctrl ; work ; +; |FWFT_FIFO:burst_fifo_inst| ; 41 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:0:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 41 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:0:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ; +; |scfifo_tgk1:auto_generated| ; 41 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:0:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated ; scfifo_tgk1 ; work ; +; |a_dpfifo_3db1:dpfifo| ; 41 (25) ; 21 (10) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:0:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated|a_dpfifo_3db1:dpfifo ; a_dpfifo_3db1 ; work ; +; |altsyncram_e1k1:FIFOram| ; 0 (0) ; 0 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:0:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated|a_dpfifo_3db1:dpfifo|altsyncram_e1k1:FIFOram ; altsyncram_e1k1 ; work ; +; |cntr_e2b:rd_ptr_msb| ; 4 (4) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:0:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated|a_dpfifo_3db1:dpfifo|cntr_e2b:rd_ptr_msb ; cntr_e2b ; work ; +; |cntr_f2b:wr_ptr| ; 6 (6) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:0:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated|a_dpfifo_3db1:dpfifo|cntr_f2b:wr_ptr ; cntr_f2b ; work ; +; |cntr_r27:usedw_counter| ; 6 (6) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:0:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated|a_dpfifo_3db1:dpfifo|cntr_r27:usedw_counter ; cntr_r27 ; work ; +; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 3872 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:0:sample_mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 3872 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:0:sample_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ; +; |altsyncram_tnv3:auto_generated| ; 0 (0) ; 0 (0) ; 3872 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:0:sample_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_tnv3:auto_generated ; altsyncram_tnv3 ; work ; +; |mem_ctrl:\sample_mem_ctrl_gen:1:sample_mem_ctrl_inst| ; 48 (7) ; 23 (2) ; 4384 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:1:sample_mem_ctrl_inst ; mem_ctrl ; work ; +; |FWFT_FIFO:burst_fifo_inst| ; 41 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:1:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 41 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:1:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ; +; |scfifo_tgk1:auto_generated| ; 41 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:1:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated ; scfifo_tgk1 ; work ; +; |a_dpfifo_3db1:dpfifo| ; 41 (25) ; 21 (10) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:1:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated|a_dpfifo_3db1:dpfifo ; a_dpfifo_3db1 ; work ; +; |altsyncram_e1k1:FIFOram| ; 0 (0) ; 0 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:1:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated|a_dpfifo_3db1:dpfifo|altsyncram_e1k1:FIFOram ; altsyncram_e1k1 ; work ; +; |cntr_e2b:rd_ptr_msb| ; 4 (4) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:1:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated|a_dpfifo_3db1:dpfifo|cntr_e2b:rd_ptr_msb ; cntr_e2b ; work ; +; |cntr_f2b:wr_ptr| ; 6 (6) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:1:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated|a_dpfifo_3db1:dpfifo|cntr_f2b:wr_ptr ; cntr_f2b ; work ; +; |cntr_r27:usedw_counter| ; 6 (6) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:1:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated|a_dpfifo_3db1:dpfifo|cntr_r27:usedw_counter ; cntr_r27 ; work ; +; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 3872 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:1:sample_mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 3872 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:1:sample_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ; +; |altsyncram_tnv3:auto_generated| ; 0 (0) ; 0 (0) ; 3872 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:1:sample_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_tnv3:auto_generated ; altsyncram_tnv3 ; work ; +; |mem_ctrl:\sample_mem_ctrl_gen:2:sample_mem_ctrl_inst| ; 48 (7) ; 23 (2) ; 4384 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:2:sample_mem_ctrl_inst ; mem_ctrl ; work ; +; |FWFT_FIFO:burst_fifo_inst| ; 41 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:2:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 41 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:2:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ; +; |scfifo_tgk1:auto_generated| ; 41 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:2:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated ; scfifo_tgk1 ; work ; +; |a_dpfifo_3db1:dpfifo| ; 41 (25) ; 21 (10) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:2:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated|a_dpfifo_3db1:dpfifo ; a_dpfifo_3db1 ; work ; +; |altsyncram_e1k1:FIFOram| ; 0 (0) ; 0 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:2:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated|a_dpfifo_3db1:dpfifo|altsyncram_e1k1:FIFOram ; altsyncram_e1k1 ; work ; +; |cntr_e2b:rd_ptr_msb| ; 4 (4) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:2:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated|a_dpfifo_3db1:dpfifo|cntr_e2b:rd_ptr_msb ; cntr_e2b ; work ; +; |cntr_f2b:wr_ptr| ; 6 (6) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:2:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated|a_dpfifo_3db1:dpfifo|cntr_f2b:wr_ptr ; cntr_f2b ; work ; +; |cntr_r27:usedw_counter| ; 6 (6) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:2:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated|a_dpfifo_3db1:dpfifo|cntr_r27:usedw_counter ; cntr_r27 ; work ; +; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 3872 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:2:sample_mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 3872 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:2:sample_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ; +; |altsyncram_tnv3:auto_generated| ; 0 (0) ; 0 (0) ; 3872 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:2:sample_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_tnv3:auto_generated ; altsyncram_tnv3 ; work ; +; |mem_ctrl:\sample_mem_ctrl_gen:3:sample_mem_ctrl_inst| ; 48 (7) ; 23 (2) ; 4384 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:3:sample_mem_ctrl_inst ; mem_ctrl ; work ; +; |FWFT_FIFO:burst_fifo_inst| ; 41 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:3:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 41 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:3:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ; +; |scfifo_tgk1:auto_generated| ; 41 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:3:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated ; scfifo_tgk1 ; work ; +; |a_dpfifo_3db1:dpfifo| ; 41 (25) ; 21 (10) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:3:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated|a_dpfifo_3db1:dpfifo ; a_dpfifo_3db1 ; work ; +; |altsyncram_e1k1:FIFOram| ; 0 (0) ; 0 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:3:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated|a_dpfifo_3db1:dpfifo|altsyncram_e1k1:FIFOram ; altsyncram_e1k1 ; work ; +; |cntr_e2b:rd_ptr_msb| ; 4 (4) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:3:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated|a_dpfifo_3db1:dpfifo|cntr_e2b:rd_ptr_msb ; cntr_e2b ; work ; +; |cntr_f2b:wr_ptr| ; 6 (6) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:3:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated|a_dpfifo_3db1:dpfifo|cntr_f2b:wr_ptr ; cntr_f2b ; work ; +; |cntr_r27:usedw_counter| ; 6 (6) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:3:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated|a_dpfifo_3db1:dpfifo|cntr_r27:usedw_counter ; cntr_r27 ; work ; +; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 3872 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:3:sample_mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 3872 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:3:sample_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ; +; |altsyncram_tnv3:auto_generated| ; 0 (0) ; 0 (0) ; 3872 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:3:sample_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_tnv3:auto_generated ; altsyncram_tnv3 ; work ; +; |mem_ctrl:\sample_mem_ctrl_gen:4:sample_mem_ctrl_inst| ; 47 (7) ; 23 (2) ; 1216 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:4:sample_mem_ctrl_inst ; mem_ctrl ; work ; +; |FWFT_FIFO:burst_fifo_inst| ; 40 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:4:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 40 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:4:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ; +; |scfifo_tgk1:auto_generated| ; 40 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:4:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated ; scfifo_tgk1 ; work ; +; |a_dpfifo_3db1:dpfifo| ; 40 (24) ; 21 (10) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:4:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated|a_dpfifo_3db1:dpfifo ; a_dpfifo_3db1 ; work ; +; |altsyncram_e1k1:FIFOram| ; 0 (0) ; 0 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:4:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated|a_dpfifo_3db1:dpfifo|altsyncram_e1k1:FIFOram ; altsyncram_e1k1 ; work ; +; |cntr_e2b:rd_ptr_msb| ; 4 (4) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:4:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated|a_dpfifo_3db1:dpfifo|cntr_e2b:rd_ptr_msb ; cntr_e2b ; work ; +; |cntr_f2b:wr_ptr| ; 6 (6) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:4:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated|a_dpfifo_3db1:dpfifo|cntr_f2b:wr_ptr ; cntr_f2b ; work ; +; |cntr_r27:usedw_counter| ; 6 (6) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:4:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated|a_dpfifo_3db1:dpfifo|cntr_r27:usedw_counter ; cntr_r27 ; work ; +; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 704 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:4:sample_mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 704 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:4:sample_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ; +; |altsyncram_fmv3:auto_generated| ; 0 (0) ; 0 (0) ; 704 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:4:sample_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_fmv3:auto_generated ; altsyncram_fmv3 ; work ; +; |ros_static_discovery_writer:ros_discovery_writer_inst| ; 51 (51) ; 12 (12) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|ros_static_discovery_writer:ros_discovery_writer_inst ; ros_static_discovery_writer ; work ; +; |ros_time_converter:ros_time_converter_inst| ; 122 (63) ; 240 (95) ; 0 ; 4 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|ros_time_converter:ros_time_converter_inst ; ros_time_converter ; work ; +; |mult:mult_inst| ; 59 (0) ; 145 (0) ; 0 ; 4 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|ros_time_converter:ros_time_converter_inst|mult:mult_inst ; mult ; work ; +; |lpm_mult:lpm_mult_component| ; 59 (0) ; 145 (0) ; 0 ; 4 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|ros_time_converter:ros_time_converter_inst|mult:mult_inst|lpm_mult:lpm_mult_component ; lpm_mult ; work ; +; |mult_ilr:auto_generated| ; 59 (59) ; 145 (145) ; 0 ; 4 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|ros_time_converter:ros_time_converter_inst|mult:mult_inst|lpm_mult:lpm_mult_component|mult_ilr:auto_generated ; mult_ilr ; work ; +; |rtps_discovery_module:rtps_discovery_module_inst| ; 8804 (8757) ; 3240 (3213) ; 41024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_discovery_module:rtps_discovery_module_inst ; rtps_discovery_module ; work ; +; |mem_ctrl:mem_ctrl_inst| ; 47 (6) ; 27 (2) ; 41024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_discovery_module:rtps_discovery_module_inst|mem_ctrl:mem_ctrl_inst ; mem_ctrl ; work ; +; |FWFT_FIFO:burst_fifo_inst| ; 41 (0) ; 25 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_discovery_module:rtps_discovery_module_inst|mem_ctrl:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 41 (0) ; 25 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_discovery_module:rtps_discovery_module_inst|mem_ctrl:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ; +; |scfifo_3hk1:auto_generated| ; 41 (0) ; 25 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_discovery_module:rtps_discovery_module_inst|mem_ctrl:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_3hk1:auto_generated ; scfifo_3hk1 ; work ; +; |a_dpfifo_9db1:dpfifo| ; 41 (24) ; 25 (11) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_discovery_module:rtps_discovery_module_inst|mem_ctrl:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_3hk1:auto_generated|a_dpfifo_9db1:dpfifo ; a_dpfifo_9db1 ; work ; +; |altsyncram_c1k1:FIFOram| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_discovery_module:rtps_discovery_module_inst|mem_ctrl:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_3hk1:auto_generated|a_dpfifo_9db1:dpfifo|altsyncram_c1k1:FIFOram ; altsyncram_c1k1 ; work ; +; |cntr_f2b:rd_ptr_msb| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_discovery_module:rtps_discovery_module_inst|mem_ctrl:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_3hk1:auto_generated|a_dpfifo_9db1:dpfifo|cntr_f2b:rd_ptr_msb ; cntr_f2b ; work ; +; |cntr_g2b:wr_ptr| ; 6 (6) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_discovery_module:rtps_discovery_module_inst|mem_ctrl:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_3hk1:auto_generated|a_dpfifo_9db1:dpfifo|cntr_g2b:wr_ptr ; cntr_g2b ; work ; +; |cntr_s27:usedw_counter| ; 6 (6) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_discovery_module:rtps_discovery_module_inst|mem_ctrl:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_3hk1:auto_generated|a_dpfifo_9db1:dpfifo|cntr_s27:usedw_counter ; cntr_s27 ; work ; +; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 40000 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_discovery_module:rtps_discovery_module_inst|mem_ctrl:mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 40000 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_discovery_module:rtps_discovery_module_inst|mem_ctrl:mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ; +; |altsyncram_sqv3:auto_generated| ; 0 (0) ; 0 (0) ; 40000 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_discovery_module:rtps_discovery_module_inst|mem_ctrl:mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_sqv3:auto_generated ; altsyncram_sqv3 ; work ; +; |rtps_handler:rtps_handler_inst| ; 1633 (1633) ; 964 (964) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_handler:rtps_handler_inst ; rtps_handler ; work ; +; |rtps_out:rtps_out_inst| ; 370 (316) ; 185 (173) ; 524256 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_out:rtps_out_inst ; rtps_out ; work ; +; |dp_mem_ctrl:buffer_inst| ; 54 (3) ; 12 (2) ; 524256 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_out:rtps_out_inst|dp_mem_ctrl:buffer_inst ; dp_mem_ctrl ; work ; +; |FWFT_FIFO:burst_fifo_inst| ; 15 (0) ; 9 (0) ; 64 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_out:rtps_out_inst|dp_mem_ctrl:buffer_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 15 (0) ; 9 (0) ; 64 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_out:rtps_out_inst|dp_mem_ctrl:buffer_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ; +; |scfifo_afk1:auto_generated| ; 15 (0) ; 9 (0) ; 64 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_out:rtps_out_inst|dp_mem_ctrl:buffer_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_afk1:auto_generated ; scfifo_afk1 ; work ; +; |a_dpfifo_gbb1:dpfifo| ; 15 (11) ; 9 (7) ; 64 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_out:rtps_out_inst|dp_mem_ctrl:buffer_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_afk1:auto_generated|a_dpfifo_gbb1:dpfifo ; a_dpfifo_gbb1 ; work ; +; |altsyncram_utj1:FIFOram| ; 0 (0) ; 0 (0) ; 64 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_out:rtps_out_inst|dp_mem_ctrl:buffer_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_afk1:auto_generated|a_dpfifo_gbb1:dpfifo|altsyncram_utj1:FIFOram ; altsyncram_utj1 ; work ; +; |cntr_c2b:wr_ptr| ; 2 (2) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_out:rtps_out_inst|dp_mem_ctrl:buffer_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_afk1:auto_generated|a_dpfifo_gbb1:dpfifo|cntr_c2b:wr_ptr ; cntr_c2b ; work ; +; |cntr_o27:usedw_counter| ; 2 (2) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_out:rtps_out_inst|dp_mem_ctrl:buffer_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_afk1:auto_generated|a_dpfifo_gbb1:dpfifo|cntr_o27:usedw_counter ; cntr_o27 ; work ; +; |dual_port_ram:ram_inst| ; 36 (0) ; 1 (0) ; 524192 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_out:rtps_out_inst|dp_mem_ctrl:buffer_inst|dual_port_ram:ram_inst ; dual_port_ram ; work ; +; |altsyncram:altsyncram_component| ; 36 (0) ; 1 (0) ; 524192 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_out:rtps_out_inst|dp_mem_ctrl:buffer_inst|dual_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ; +; |altsyncram_1qv3:auto_generated| ; 36 (0) ; 1 (1) ; 524192 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_out:rtps_out_inst|dp_mem_ctrl:buffer_inst|dual_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_1qv3:auto_generated ; altsyncram_1qv3 ; work ; +; |decode_5la:rden_decode_b| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_out:rtps_out_inst|dp_mem_ctrl:buffer_inst|dual_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_1qv3:auto_generated|decode_5la:rden_decode_b ; decode_5la ; work ; +; |decode_5la:wren_decode_a| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_out:rtps_out_inst|dp_mem_ctrl:buffer_inst|dual_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_1qv3:auto_generated|decode_5la:wren_decode_a ; decode_5la ; work ; +; |mux_2hb:mux3| ; 32 (32) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_out:rtps_out_inst|dp_mem_ctrl:buffer_inst|dual_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_1qv3:auto_generated|mux_2hb:mux3 ; mux_2hb ; work ; +; |rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst| ; 5381 (5249) ; 2360 (2279) ; 84672 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst ; rtps_reader ; work ; +; |mem_ctrl:\mem_ctrl_gen:0:mem_ctrl_inst| ; 44 (6) ; 27 (2) ; 28224 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:0:mem_ctrl_inst ; mem_ctrl ; work ; +; |FWFT_FIFO:burst_fifo_inst| ; 38 (0) ; 25 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:0:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 38 (0) ; 25 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:0:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ; +; |scfifo_4hk1:auto_generated| ; 38 (0) ; 25 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:0:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated ; scfifo_4hk1 ; work ; +; |a_dpfifo_adb1:dpfifo| ; 38 (21) ; 25 (11) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:0:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo ; a_dpfifo_adb1 ; work ; +; |altsyncram_c1k1:FIFOram| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:0:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|altsyncram_c1k1:FIFOram ; altsyncram_c1k1 ; work ; +; |cntr_f2b:rd_ptr_msb| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:0:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|cntr_f2b:rd_ptr_msb ; cntr_f2b ; work ; +; |cntr_g2b:wr_ptr| ; 6 (6) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:0:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|cntr_g2b:wr_ptr ; cntr_g2b ; work ; +; |cntr_s27:usedw_counter| ; 6 (6) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:0:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|cntr_s27:usedw_counter ; cntr_s27 ; work ; +; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 27200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:0:mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 27200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:0:mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ; +; |altsyncram_gpv3:auto_generated| ; 0 (0) ; 0 (0) ; 27200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:0:mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_gpv3:auto_generated ; altsyncram_gpv3 ; work ; +; |mem_ctrl:\mem_ctrl_gen:1:mem_ctrl_inst| ; 44 (6) ; 27 (2) ; 28224 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:1:mem_ctrl_inst ; mem_ctrl ; work ; +; |FWFT_FIFO:burst_fifo_inst| ; 38 (0) ; 25 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:1:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 38 (0) ; 25 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:1:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ; +; |scfifo_4hk1:auto_generated| ; 38 (0) ; 25 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:1:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated ; scfifo_4hk1 ; work ; +; |a_dpfifo_adb1:dpfifo| ; 38 (21) ; 25 (11) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:1:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo ; a_dpfifo_adb1 ; work ; +; |altsyncram_c1k1:FIFOram| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:1:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|altsyncram_c1k1:FIFOram ; altsyncram_c1k1 ; work ; +; |cntr_f2b:rd_ptr_msb| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:1:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|cntr_f2b:rd_ptr_msb ; cntr_f2b ; work ; +; |cntr_g2b:wr_ptr| ; 6 (6) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:1:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|cntr_g2b:wr_ptr ; cntr_g2b ; work ; +; |cntr_s27:usedw_counter| ; 6 (6) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:1:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|cntr_s27:usedw_counter ; cntr_s27 ; work ; +; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 27200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:1:mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 27200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:1:mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ; +; |altsyncram_gpv3:auto_generated| ; 0 (0) ; 0 (0) ; 27200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:1:mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_gpv3:auto_generated ; altsyncram_gpv3 ; work ; +; |mem_ctrl:\mem_ctrl_gen:2:mem_ctrl_inst| ; 44 (6) ; 27 (2) ; 28224 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:2:mem_ctrl_inst ; mem_ctrl ; work ; +; |FWFT_FIFO:burst_fifo_inst| ; 38 (0) ; 25 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:2:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 38 (0) ; 25 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:2:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ; +; |scfifo_4hk1:auto_generated| ; 38 (0) ; 25 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:2:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated ; scfifo_4hk1 ; work ; +; |a_dpfifo_adb1:dpfifo| ; 38 (21) ; 25 (11) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:2:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo ; a_dpfifo_adb1 ; work ; +; |altsyncram_c1k1:FIFOram| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:2:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|altsyncram_c1k1:FIFOram ; altsyncram_c1k1 ; work ; +; |cntr_f2b:rd_ptr_msb| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:2:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|cntr_f2b:rd_ptr_msb ; cntr_f2b ; work ; +; |cntr_g2b:wr_ptr| ; 6 (6) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:2:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|cntr_g2b:wr_ptr ; cntr_g2b ; work ; +; |cntr_s27:usedw_counter| ; 6 (6) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:2:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|cntr_s27:usedw_counter ; cntr_s27 ; work ; +; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 27200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:2:mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 27200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:2:mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ; +; |altsyncram_gpv3:auto_generated| ; 0 (0) ; 0 (0) ; 27200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:2:mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_gpv3:auto_generated ; altsyncram_gpv3 ; work ; +; |rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst| ; 6872 (6612) ; 3150 (2988) ; 169344 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst ; rtps_writer ; work ; +; |mem_ctrl:\mem_ctrl_gen:0:mem_ctrl_inst| ; 45 (7) ; 27 (2) ; 28224 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:0:mem_ctrl_inst ; mem_ctrl ; work ; +; |FWFT_FIFO:burst_fifo_inst| ; 38 (0) ; 25 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:0:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 38 (0) ; 25 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:0:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ; +; |scfifo_4hk1:auto_generated| ; 38 (0) ; 25 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:0:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated ; scfifo_4hk1 ; work ; +; |a_dpfifo_adb1:dpfifo| ; 38 (21) ; 25 (11) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:0:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo ; a_dpfifo_adb1 ; work ; +; |altsyncram_c1k1:FIFOram| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:0:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|altsyncram_c1k1:FIFOram ; altsyncram_c1k1 ; work ; +; |cntr_f2b:rd_ptr_msb| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:0:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|cntr_f2b:rd_ptr_msb ; cntr_f2b ; work ; +; |cntr_g2b:wr_ptr| ; 6 (6) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:0:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|cntr_g2b:wr_ptr ; cntr_g2b ; work ; +; |cntr_s27:usedw_counter| ; 6 (6) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:0:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|cntr_s27:usedw_counter ; cntr_s27 ; work ; +; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 27200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:0:mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 27200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:0:mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ; +; |altsyncram_gpv3:auto_generated| ; 0 (0) ; 0 (0) ; 27200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:0:mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_gpv3:auto_generated ; altsyncram_gpv3 ; work ; +; |mem_ctrl:\mem_ctrl_gen:1:mem_ctrl_inst| ; 43 (5) ; 27 (2) ; 28224 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:1:mem_ctrl_inst ; mem_ctrl ; work ; +; |FWFT_FIFO:burst_fifo_inst| ; 38 (0) ; 25 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:1:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 38 (0) ; 25 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:1:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ; +; |scfifo_4hk1:auto_generated| ; 38 (0) ; 25 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:1:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated ; scfifo_4hk1 ; work ; +; |a_dpfifo_adb1:dpfifo| ; 38 (21) ; 25 (11) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:1:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo ; a_dpfifo_adb1 ; work ; +; |altsyncram_c1k1:FIFOram| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:1:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|altsyncram_c1k1:FIFOram ; altsyncram_c1k1 ; work ; +; |cntr_f2b:rd_ptr_msb| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:1:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|cntr_f2b:rd_ptr_msb ; cntr_f2b ; work ; +; |cntr_g2b:wr_ptr| ; 6 (6) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:1:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|cntr_g2b:wr_ptr ; cntr_g2b ; work ; +; |cntr_s27:usedw_counter| ; 6 (6) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:1:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|cntr_s27:usedw_counter ; cntr_s27 ; work ; +; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 27200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:1:mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 27200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:1:mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ; +; |altsyncram_gpv3:auto_generated| ; 0 (0) ; 0 (0) ; 27200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:1:mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_gpv3:auto_generated ; altsyncram_gpv3 ; work ; +; |mem_ctrl:\mem_ctrl_gen:2:mem_ctrl_inst| ; 43 (5) ; 27 (2) ; 28224 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:2:mem_ctrl_inst ; mem_ctrl ; work ; +; |FWFT_FIFO:burst_fifo_inst| ; 38 (0) ; 25 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:2:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 38 (0) ; 25 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:2:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ; +; |scfifo_4hk1:auto_generated| ; 38 (0) ; 25 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:2:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated ; scfifo_4hk1 ; work ; +; |a_dpfifo_adb1:dpfifo| ; 38 (21) ; 25 (11) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:2:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo ; a_dpfifo_adb1 ; work ; +; |altsyncram_c1k1:FIFOram| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:2:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|altsyncram_c1k1:FIFOram ; altsyncram_c1k1 ; work ; +; |cntr_f2b:rd_ptr_msb| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:2:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|cntr_f2b:rd_ptr_msb ; cntr_f2b ; work ; +; |cntr_g2b:wr_ptr| ; 6 (6) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:2:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|cntr_g2b:wr_ptr ; cntr_g2b ; work ; +; |cntr_s27:usedw_counter| ; 6 (6) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:2:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|cntr_s27:usedw_counter ; cntr_s27 ; work ; +; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 27200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:2:mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 27200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:2:mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ; +; |altsyncram_gpv3:auto_generated| ; 0 (0) ; 0 (0) ; 27200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:2:mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_gpv3:auto_generated ; altsyncram_gpv3 ; work ; +; |mem_ctrl:\mem_ctrl_gen:3:mem_ctrl_inst| ; 43 (5) ; 27 (2) ; 28224 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:3:mem_ctrl_inst ; mem_ctrl ; work ; +; |FWFT_FIFO:burst_fifo_inst| ; 38 (0) ; 25 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:3:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 38 (0) ; 25 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:3:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ; +; |scfifo_4hk1:auto_generated| ; 38 (0) ; 25 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:3:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated ; scfifo_4hk1 ; work ; +; |a_dpfifo_adb1:dpfifo| ; 38 (21) ; 25 (11) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:3:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo ; a_dpfifo_adb1 ; work ; +; |altsyncram_c1k1:FIFOram| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:3:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|altsyncram_c1k1:FIFOram ; altsyncram_c1k1 ; work ; +; |cntr_f2b:rd_ptr_msb| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:3:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|cntr_f2b:rd_ptr_msb ; cntr_f2b ; work ; +; |cntr_g2b:wr_ptr| ; 6 (6) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:3:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|cntr_g2b:wr_ptr ; cntr_g2b ; work ; +; |cntr_s27:usedw_counter| ; 6 (6) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:3:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|cntr_s27:usedw_counter ; cntr_s27 ; work ; +; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 27200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:3:mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 27200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:3:mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ; +; |altsyncram_gpv3:auto_generated| ; 0 (0) ; 0 (0) ; 27200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:3:mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_gpv3:auto_generated ; altsyncram_gpv3 ; work ; +; |mem_ctrl:\mem_ctrl_gen:4:mem_ctrl_inst| ; 43 (5) ; 27 (2) ; 28224 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:4:mem_ctrl_inst ; mem_ctrl ; work ; +; |FWFT_FIFO:burst_fifo_inst| ; 38 (0) ; 25 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:4:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 38 (0) ; 25 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:4:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ; +; |scfifo_4hk1:auto_generated| ; 38 (0) ; 25 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:4:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated ; scfifo_4hk1 ; work ; +; |a_dpfifo_adb1:dpfifo| ; 38 (21) ; 25 (11) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:4:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo ; a_dpfifo_adb1 ; work ; +; |altsyncram_c1k1:FIFOram| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:4:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|altsyncram_c1k1:FIFOram ; altsyncram_c1k1 ; work ; +; |cntr_f2b:rd_ptr_msb| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:4:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|cntr_f2b:rd_ptr_msb ; cntr_f2b ; work ; +; |cntr_g2b:wr_ptr| ; 6 (6) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:4:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|cntr_g2b:wr_ptr ; cntr_g2b ; work ; +; |cntr_s27:usedw_counter| ; 6 (6) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:4:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|cntr_s27:usedw_counter ; cntr_s27 ; work ; +; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 27200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:4:mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 27200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:4:mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ; +; |altsyncram_gpv3:auto_generated| ; 0 (0) ; 0 (0) ; 27200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:4:mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_gpv3:auto_generated ; altsyncram_gpv3 ; work ; +; |mem_ctrl:\mem_ctrl_gen:5:mem_ctrl_inst| ; 43 (5) ; 27 (2) ; 28224 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:5:mem_ctrl_inst ; mem_ctrl ; work ; +; |FWFT_FIFO:burst_fifo_inst| ; 38 (0) ; 25 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:5:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 38 (0) ; 25 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:5:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ; +; |scfifo_4hk1:auto_generated| ; 38 (0) ; 25 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:5:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated ; scfifo_4hk1 ; work ; +; |a_dpfifo_adb1:dpfifo| ; 38 (21) ; 25 (11) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:5:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo ; a_dpfifo_adb1 ; work ; +; |altsyncram_c1k1:FIFOram| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:5:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|altsyncram_c1k1:FIFOram ; altsyncram_c1k1 ; work ; +; |cntr_f2b:rd_ptr_msb| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:5:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|cntr_f2b:rd_ptr_msb ; cntr_f2b ; work ; +; |cntr_g2b:wr_ptr| ; 6 (6) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:5:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|cntr_g2b:wr_ptr ; cntr_g2b ; work ; +; |cntr_s27:usedw_counter| ; 6 (6) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:5:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|cntr_s27:usedw_counter ; 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15 (11) ; 9 (7) ; 6 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_rb_re_r_if:fifo_rb_re_inst|FWFT_FIFO:fifo_sup_inst|scfifo:scfifo_component|scfifo_odk1:auto_generated|a_dpfifo_u9b1:dpfifo ; a_dpfifo_u9b1 ; work ; +; |altsyncram_qqj1:FIFOram| ; 0 (0) ; 0 (0) ; 6 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_rb_re_r_if:fifo_rb_re_inst|FWFT_FIFO:fifo_sup_inst|scfifo:scfifo_component|scfifo_odk1:auto_generated|a_dpfifo_u9b1:dpfifo|altsyncram_qqj1:FIFOram ; altsyncram_qqj1 ; work ; +; |cntr_c2b:wr_ptr| ; 2 (2) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_rb_re_r_if:fifo_rb_re_inst|FWFT_FIFO:fifo_sup_inst|scfifo:scfifo_component|scfifo_odk1:auto_generated|a_dpfifo_u9b1:dpfifo|cntr_c2b:wr_ptr ; cntr_c2b ; work ; +; |cntr_o27:usedw_counter| ; 2 (2) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_rb_re_r_if:fifo_rb_re_inst|FWFT_FIFO:fifo_sup_inst|scfifo:scfifo_component|scfifo_odk1:auto_generated|a_dpfifo_u9b1:dpfifo|cntr_o27:usedw_counter ; cntr_o27 ; work ; +; |vector_FIFO:\fifo_rb_re_w_if:fifo_rb_re_inst| ; 37 (7) ; 18 (0) ; 78 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_rb_re_w_if:fifo_rb_re_inst ; vector_FIFO ; work ; +; |FWFT_FIFO:fifo_main_inst| ; 15 (0) ; 9 (0) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_rb_re_w_if:fifo_rb_re_inst|FWFT_FIFO:fifo_main_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 15 (0) ; 9 (0) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_rb_re_w_if:fifo_rb_re_inst|FWFT_FIFO:fifo_main_inst|scfifo:scfifo_component ; scfifo ; work ; +; |scfifo_bfk1:auto_generated| ; 15 (0) ; 9 (0) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_rb_re_w_if:fifo_rb_re_inst|FWFT_FIFO:fifo_main_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated ; scfifo_bfk1 ; work ; +; |a_dpfifo_hbb1:dpfifo| ; 15 (11) ; 9 (7) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_rb_re_w_if:fifo_rb_re_inst|FWFT_FIFO:fifo_main_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated|a_dpfifo_hbb1:dpfifo ; a_dpfifo_hbb1 ; work ; +; |altsyncram_0uj1:FIFOram| ; 0 (0) ; 0 (0) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_rb_re_w_if:fifo_rb_re_inst|FWFT_FIFO:fifo_main_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated|a_dpfifo_hbb1:dpfifo|altsyncram_0uj1:FIFOram ; altsyncram_0uj1 ; work ; +; |cntr_c2b:wr_ptr| ; 2 (2) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_rb_re_w_if:fifo_rb_re_inst|FWFT_FIFO:fifo_main_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated|a_dpfifo_hbb1:dpfifo|cntr_c2b:wr_ptr ; cntr_c2b ; work ; +; |cntr_o27:usedw_counter| ; 2 (2) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_rb_re_w_if:fifo_rb_re_inst|FWFT_FIFO:fifo_main_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated|a_dpfifo_hbb1:dpfifo|cntr_o27:usedw_counter ; cntr_o27 ; work ; +; |FWFT_FIFO:fifo_sup_inst| ; 15 (0) ; 9 (0) ; 12 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_rb_re_w_if:fifo_rb_re_inst|FWFT_FIFO:fifo_sup_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 15 (0) ; 9 (0) ; 12 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_rb_re_w_if:fifo_rb_re_inst|FWFT_FIFO:fifo_sup_inst|scfifo:scfifo_component ; scfifo ; work ; +; |scfifo_rdk1:auto_generated| ; 15 (0) ; 9 (0) ; 12 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_rb_re_w_if:fifo_rb_re_inst|FWFT_FIFO:fifo_sup_inst|scfifo:scfifo_component|scfifo_rdk1:auto_generated ; scfifo_rdk1 ; work ; +; |a_dpfifo_1ab1:dpfifo| ; 15 (11) ; 9 (7) ; 12 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_rb_re_w_if:fifo_rb_re_inst|FWFT_FIFO:fifo_sup_inst|scfifo:scfifo_component|scfifo_rdk1:auto_generated|a_dpfifo_1ab1:dpfifo ; a_dpfifo_1ab1 ; work ; +; |altsyncram_0rj1:FIFOram| ; 0 (0) ; 0 (0) ; 12 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_rb_re_w_if:fifo_rb_re_inst|FWFT_FIFO:fifo_sup_inst|scfifo:scfifo_component|scfifo_rdk1:auto_generated|a_dpfifo_1ab1:dpfifo|altsyncram_0rj1:FIFOram ; altsyncram_0rj1 ; work ; +; |cntr_c2b:wr_ptr| ; 2 (2) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_rb_re_w_if:fifo_rb_re_inst|FWFT_FIFO:fifo_sup_inst|scfifo:scfifo_component|scfifo_rdk1:auto_generated|a_dpfifo_1ab1:dpfifo|cntr_c2b:wr_ptr ; cntr_c2b ; work ; +; |cntr_o27:usedw_counter| ; 2 (2) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_rb_re_w_if:fifo_rb_re_inst|FWFT_FIFO:fifo_sup_inst|scfifo:scfifo_component|scfifo_rdk1:auto_generated|a_dpfifo_1ab1:dpfifo|cntr_o27:usedw_counter ; cntr_o27 ; work ; ++------------------------------------------------------------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++---------------------------------------------------------+ +; Analysis & Synthesis Resource Usage Summary ; ++---------------------------------------------+-----------+ +; Resource ; Usage ; ++---------------------------------------------+-----------+ +; Estimate of Logic utilization (ALMs needed) ; 27731 ; +; ; ; +; Combinational ALUT usage for logic ; 42256 ; +; -- 7 input functions ; 700 ; +; -- 6 input functions ; 8987 ; +; -- 5 input functions ; 9513 ; +; -- 4 input functions ; 9502 ; +; -- <=3 input functions ; 13554 ; +; ; ; +; Dedicated logic registers ; 19765 ; +; ; ; +; I/O pins ; 71 ; +; Total MLAB memory bits ; 0 ; +; Total block memory bits ; 2408283 ; +; ; ; +; Total DSP Blocks ; 4 ; +; ; ; +; Maximum fan-out node ; clk~input ; +; Maximum fan-out ; 22878 ; +; Total fan-out ; 293222 ; +; Average fan-out ; 4.49 ; ++---------------------------------------------+-----------+ \ No newline at end of file diff --git a/sim/L0_dds_writer_test1.do b/sim/L0_dds_writer_test1.do new file mode 100644 index 0000000..1b056f3 --- /dev/null +++ b/sim/L0_dds_writer_test1.do @@ -0,0 +1,154 @@ +onerror {resume} +radix define DDS_RETCODE { + "10#0#" "RETCODE_OK", + "10#1#" "RETCODE_ERROR", + "10#2#" "RETCODE_UNSUPPORTED", + "10#3#" "RETCODE_BAD_PARAMETER", + "10#4#" "RETCODE_PRECONDITION_NOT_MET", + "10#5#" "RETCODE_OUT_OF_RESOURCES", + "10#6#" "RETCODE_NOT_ENABLED", + "10#7#" "RETCODE_IMMUTABLE_POLICY", + "10#8#" "RETCODE_INCONSISTENT_POLICY", + "10#9#" "RETCODE_ALREADY_DELETED", + "10#10#" "RETCODE_TIMEOUT", + "10#11#" "RETCODE_NO_DATA", + "10#12#" "RETCODE_ILLEGAL_OPERATION", + -default unsigned +} +quietly WaveActivateNextPane {} 0 +add wave -noupdate -divider SYSTEM +add wave -noupdate /l0_dds_writer_test1/uut/clk +add wave -noupdate /l0_dds_writer_test1/uut/reset +add wave -noupdate -radix unsigned /l0_dds_writer_test1/uut/time +add wave -noupdate -divider {RTPS IN} +add wave -noupdate -group {RTPS IN} /l0_dds_writer_test1/uut/start_rtps +add wave -noupdate -group {RTPS IN} -radix unsigned /l0_dds_writer_test1/uut/seq_nr_rtps +add wave -noupdate -group {RTPS IN} /l0_dds_writer_test1/uut/opcode_rtps +add wave -noupdate -group {RTPS IN} /l0_dds_writer_test1/uut/ack_rtps +add wave -noupdate -group {RTPS IN} /l0_dds_writer_test1/uut/done_rtps +add wave -noupdate -group {RTPS IN} /l0_dds_writer_test1/uut/ret_rtps +add wave -noupdate -divider {RTPS OUT} +add wave -noupdate -group {RTPS OUT} -radix hexadecimal /l0_dds_writer_test1/uut/cc_instance_handle +add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test1/uut/cc_kind +add wave -noupdate -group {RTPS OUT} -radix unsigned /l0_dds_writer_test1/uut/cc_source_timestamp +add wave -noupdate -group {RTPS OUT} -radix unsigned -childformat {{/l0_dds_writer_test1/uut/cc_seq_nr(0) -radix unsigned -childformat {{/l0_dds_writer_test1/uut/cc_seq_nr(0)(0) -radix unsigned} {/l0_dds_writer_test1/uut/cc_seq_nr(0)(1) -radix unsigned}}} {/l0_dds_writer_test1/uut/cc_seq_nr(1) -radix unsigned} {/l0_dds_writer_test1/uut/cc_seq_nr(2) -radix unsigned} {/l0_dds_writer_test1/uut/cc_seq_nr(3) -radix unsigned}} -subitemconfig {/l0_dds_writer_test1/uut/cc_seq_nr(0) {-height 15 -radix unsigned -childformat {{/l0_dds_writer_test1/uut/cc_seq_nr(0)(0) -radix unsigned} {/l0_dds_writer_test1/uut/cc_seq_nr(0)(1) -radix unsigned}}} /l0_dds_writer_test1/uut/cc_seq_nr(0)(0) {-height 15 -radix unsigned} /l0_dds_writer_test1/uut/cc_seq_nr(0)(1) {-height 15 -radix unsigned} /l0_dds_writer_test1/uut/cc_seq_nr(1) {-height 15 -radix unsigned} /l0_dds_writer_test1/uut/cc_seq_nr(2) {-height 15 -radix unsigned} /l0_dds_writer_test1/uut/cc_seq_nr(3) {-height 15 -radix unsigned}} /l0_dds_writer_test1/uut/cc_seq_nr +add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test1/uut/get_data_rtps +add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test1/uut/ready_out_rtps +add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test1/uut/valid_out_rtps +add wave -noupdate -group {RTPS OUT} -radix hexadecimal /l0_dds_writer_test1/uut/data_out_rtps +add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test1/uut/last_word_out_rtps +add wave -noupdate -divider {DDS IN} +add wave -noupdate -expand -group DDS /l0_dds_writer_test1/uut/start_dds +add wave -noupdate -expand -group DDS -radix unsigned /l0_dds_writer_test1/uut/source_ts_dds +add wave -noupdate -expand -group DDS /l0_dds_writer_test1/uut/opcode_dds +add wave -noupdate -expand -group DDS /l0_dds_writer_test1/uut/ack_dds +add wave -noupdate -expand -group DDS /l0_dds_writer_test1/uut/done_dds +add wave -noupdate -expand -group DDS -radix unsigned -childformat {{/l0_dds_writer_test1/uut/return_code_dds(0) -radix DDS_RETCODE} {/l0_dds_writer_test1/uut/return_code_dds(1) -radix DDS_RETCODE} {/l0_dds_writer_test1/uut/return_code_dds(2) -radix DDS_RETCODE} {/l0_dds_writer_test1/uut/return_code_dds(3) -radix DDS_RETCODE}} -subitemconfig {/l0_dds_writer_test1/uut/return_code_dds(0) {-height 15 -radix DDS_RETCODE} /l0_dds_writer_test1/uut/return_code_dds(1) {-height 15 -radix DDS_RETCODE} /l0_dds_writer_test1/uut/return_code_dds(2) {-height 15 -radix DDS_RETCODE} /l0_dds_writer_test1/uut/return_code_dds(3) {-height 15 -radix DDS_RETCODE}} /l0_dds_writer_test1/uut/return_code_dds +add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_writer_test1/uut/instance_handle_in_dds +add wave -noupdate -expand -group DDS /l0_dds_writer_test1/uut/ready_in_dds +add wave -noupdate -expand -group DDS /l0_dds_writer_test1/uut/valid_in_dds +add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_writer_test1/uut/data_in_dds +add wave -noupdate -expand -group DDS /l0_dds_writer_test1/uut/last_word_in_dds +add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_writer_test1/uut/instance_handle_out_dds +add wave -noupdate -expand -group DDS /l0_dds_writer_test1/uut/ready_out_dds +add wave -noupdate -expand -group DDS /l0_dds_writer_test1/uut/valid_out_dds +add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_writer_test1/uut/data_out_dds +add wave -noupdate -expand -group DDS /l0_dds_writer_test1/uut/last_word_out_dds +add wave -noupdate -divider {MAIN FSM} +add wave -noupdate /l0_dds_writer_test1/uut/stage +add wave -noupdate /l0_dds_writer_test1/uut/cnt +add wave -noupdate /l0_dds_writer_test1/uut/ind +add wave -noupdate -radix unsigned /l0_dds_writer_test1/uut/global_seq_nr +add wave -noupdate -radix unsigned /l0_dds_writer_test1/uut/global_sample_cnt +add wave -noupdate -radix unsigned /l0_dds_writer_test1/uut/global_ack_cnt +add wave -noupdate -radix unsigned /l0_dds_writer_test1/uut/stale_inst_cnt +add wave -noupdate /l0_dds_writer_test1/uut/remove_oldest_inst_sample +add wave -noupdate /l0_dds_writer_test1/uut/remove_oldest_sample +add wave -noupdate /l0_dds_writer_test1/uut/remove_ack_sample +add wave -noupdate -divider MEMORY +add wave -noupdate -group {SAMPLE MEM} -radix unsigned /l0_dds_writer_test1/uut/sample_addr +add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test1/uut/sample_read +add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test1/uut/sample_ready_in +add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test1/uut/sample_valid_in +add wave -noupdate -group {SAMPLE MEM} -radix hexadecimal /l0_dds_writer_test1/uut/sample_write_data +add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test1/uut/sample_ready_out +add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test1/uut/sample_valid_out +add wave -noupdate -group {SAMPLE MEM} -radix hexadecimal /l0_dds_writer_test1/uut/sample_read_data +add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test1/uut/sample_abort_read +add wave -noupdate -group {PAYLOAD MEM} -radix unsigned /l0_dds_writer_test1/uut/payload_addr +add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test1/uut/payload_read +add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test1/uut/payload_ready_in +add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test1/uut/payload_valid_in +add wave -noupdate -group {PAYLOAD MEM} -radix hexadecimal /l0_dds_writer_test1/uut/payload_write_data +add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test1/uut/payload_ready_out +add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test1/uut/payload_valid_out +add wave -noupdate -group {PAYLOAD MEM} -radix hexadecimal /l0_dds_writer_test1/uut/payload_read_data +add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test1/uut/payload_abort_read +add wave -noupdate /l0_dds_writer_test1/uut/inst_op_start +add wave -noupdate /l0_dds_writer_test1/uut/inst_opcode +add wave -noupdate /l0_dds_writer_test1/uut/inst_op_done +add wave -noupdate /l0_dds_writer_test1/uut/inst_stage +add wave -noupdate /l0_dds_writer_test1/uut/inst_cnt +add wave -noupdate -radix unsigned /l0_dds_writer_test1/uut/inst_addr_base +add wave -noupdate -group {INSTANCE MEM} -radix unsigned /l0_dds_writer_test1/uut/inst_addr +add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test1/uut/inst_read +add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test1/uut/inst_ready_in +add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test1/uut/inst_valid_in +add wave -noupdate -group {INSTANCE MEM} -radix hexadecimal /l0_dds_writer_test1/uut/inst_write_data +add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test1/uut/inst_ready_out +add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test1/uut/inst_valid_out +add wave -noupdate -group {INSTANCE MEM} -radix hexadecimal /l0_dds_writer_test1/uut/inst_read_data +add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test1/uut/inst_abort_read +add wave -noupdate -radix hexadecimal -childformat {{/l0_dds_writer_test1/uut/inst_data.i -radix hexadecimal} {/l0_dds_writer_test1/uut/inst_data.addr -radix unsigned} {/l0_dds_writer_test1/uut/inst_data.key_hash -radix hexadecimal} {/l0_dds_writer_test1/uut/inst_data.status_info -radix binary} {/l0_dds_writer_test1/uut/inst_data.sample_cnt -radix unsigned} {/l0_dds_writer_test1/uut/inst_data.ack_cnt -radix unsigned}} -subitemconfig {/l0_dds_writer_test1/uut/inst_data.i {-height 15 -radix hexadecimal} /l0_dds_writer_test1/uut/inst_data.addr {-height 15 -radix unsigned} /l0_dds_writer_test1/uut/inst_data.key_hash {-height 15 -radix hexadecimal} /l0_dds_writer_test1/uut/inst_data.status_info {-height 15 -radix binary} /l0_dds_writer_test1/uut/inst_data.sample_cnt {-height 15 -radix unsigned} /l0_dds_writer_test1/uut/inst_data.ack_cnt {-height 15 -radix unsigned} /l0_dds_writer_test1/uut/inst_data.field_flags {-height 15}} /l0_dds_writer_test1/uut/inst_data +add wave -noupdate -divider {KEY HOLDER} +add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test1/uut/start_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test1/uut/opcode_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test1/uut/ack_kh +add wave -noupdate -group {KEY HOLDER} -radix hexadecimal /l0_dds_writer_test1/uut/data_in_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test1/uut/valid_in_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test1/uut/ready_in_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test1/uut/last_word_in_kh +add wave -noupdate -group {KEY HOLDER} -radix hexadecimal /l0_dds_writer_test1/uut/data_out_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test1/uut/valid_out_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test1/uut/ready_out_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test1/uut/last_word_out_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test1/uut/abort_kh +add wave -noupdate -divider POINTERS +add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test1/uut/empty_sample_list_head +add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test1/uut/empty_sample_list_tail +add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test1/uut/empty_payload_list_head +add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test1/uut/oldest_sample +add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test1/uut/newest_sample +add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test1/uut/inst_empty_head +add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test1/uut/inst_occupied_head +add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test1/uut/cur_sample +add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test1/uut/prev_sample +add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test1/uut/next_sample +add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test1/uut/cur_payload +add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test1/uut/next_payload +add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test1/uut/cur_inst +add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test1/uut/next_inst +add wave -noupdate -divider TESTBENCH +add wave -noupdate -divider MISC +add wave -noupdate /l0_dds_writer_test1/uut/cnt2 +add wave -noupdate /l0_dds_writer_test1/uut/cnt3 +add wave -noupdate -radix unsigned /l0_dds_writer_test1/uut/long_latch +add wave -noupdate /l0_dds_writer_test1/uut/sample_status_info +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {158543351 ps} 0} +quietly wave cursor active 1 +configure wave -namecolwidth 187 +configure wave -valuecolwidth 100 +configure wave -justifyvalue left +configure wave -signalnamewidth 1 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ns +update +WaveRestoreZoom {157882360 ps} {158883001 ps} diff --git a/sim/L0_dds_writer_test1_aik.do b/sim/L0_dds_writer_test1_aik.do deleted file mode 100644 index fbe93d3..0000000 --- a/sim/L0_dds_writer_test1_aik.do +++ /dev/null @@ -1,135 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -divider SYSTEM -add wave -noupdate /l0_dds_writer_test1_aik/uut/clk -add wave -noupdate /l0_dds_writer_test1_aik/uut/reset -add wave -noupdate -radix unsigned /l0_dds_writer_test1_aik/uut/time -add wave -noupdate -divider {RTPS IN} -add wave -noupdate -group {RTPS IN} /l0_dds_writer_test1_aik/uut/start_rtps -add wave -noupdate -group {RTPS IN} -radix unsigned /l0_dds_writer_test1_aik/uut/seq_nr_rtps -add wave -noupdate -group {RTPS IN} /l0_dds_writer_test1_aik/uut/opcode_rtps -add wave -noupdate -group {RTPS IN} /l0_dds_writer_test1_aik/uut/ack_rtps -add wave -noupdate -group {RTPS IN} /l0_dds_writer_test1_aik/uut/done_rtps -add wave -noupdate -group {RTPS IN} /l0_dds_writer_test1_aik/uut/ret_rtps -add wave -noupdate -divider {RTPS OUT} -add wave -noupdate -group {RTPS OUT} -radix hexadecimal /l0_dds_writer_test1_aik/uut/cc_instance_handle -add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test1_aik/uut/cc_kind -add wave -noupdate -group {RTPS OUT} -radix unsigned /l0_dds_writer_test1_aik/uut/cc_source_timestamp -add wave -noupdate -group {RTPS OUT} -radix unsigned -childformat {{/l0_dds_writer_test1_aik/uut/cc_seq_nr(0) -radix unsigned -childformat {{/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(31) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(30) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(29) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(28) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(27) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(26) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(25) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(24) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(23) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(22) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(21) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(20) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(19) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(18) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(17) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(16) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(15) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(14) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(13) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(12) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(11) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(10) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(9) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(8) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(7) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(6) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(5) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(4) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(3) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(2) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(1) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(0) -radix unsigned}}} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(1) -radix unsigned}} -subitemconfig {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0) {-height 15 -radix unsigned -childformat {{/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(31) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(30) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(29) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(28) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(27) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(26) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(25) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(24) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(23) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(22) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(21) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(20) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(19) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(18) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(17) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(16) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(15) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(14) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(13) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(12) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(11) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(10) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(9) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(8) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(7) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(6) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(5) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(4) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(3) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(2) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(1) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(0) -radix unsigned}}} /l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(31) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(30) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(29) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(28) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(27) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(26) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(25) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(24) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(23) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(22) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(21) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(20) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(19) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(18) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(17) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(16) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(15) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(14) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(13) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(12) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(11) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(10) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(9) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(8) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(7) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(6) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(5) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(4) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(3) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(2) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(1) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(0) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/cc_seq_nr(1) {-height 15 -radix unsigned}} /l0_dds_writer_test1_aik/uut/cc_seq_nr -add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test1_aik/uut/get_data_rtps -add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test1_aik/uut/ready_out_rtps -add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test1_aik/uut/valid_out_rtps -add wave -noupdate -group {RTPS OUT} -radix hexadecimal /l0_dds_writer_test1_aik/uut/data_out_rtps -add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test1_aik/uut/last_word_out_rtps -add wave -noupdate -divider {DDS IN} -add wave -noupdate -expand -group DDS /l0_dds_writer_test1_aik/uut/start_dds -add wave -noupdate -expand -group DDS -radix unsigned /l0_dds_writer_test1_aik/uut/source_ts_dds -add wave -noupdate -expand -group DDS /l0_dds_writer_test1_aik/uut/opcode_dds -add wave -noupdate -expand -group DDS /l0_dds_writer_test1_aik/uut/ack_dds -add wave -noupdate -expand -group DDS /l0_dds_writer_test1_aik/uut/done_dds -add wave -noupdate -expand -group DDS -radix unsigned /l0_dds_writer_test1_aik/uut/return_code_dds -add wave -noupdate -expand -group DDS /l0_dds_writer_test1_aik/uut/ready_in_dds -add wave -noupdate -expand -group DDS /l0_dds_writer_test1_aik/uut/valid_in_dds -add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_writer_test1_aik/uut/data_in_dds -add wave -noupdate -expand -group DDS /l0_dds_writer_test1_aik/uut/last_word_in_dds -add wave -noupdate -expand -group DDS /l0_dds_writer_test1_aik/uut/ready_out_dds -add wave -noupdate -expand -group DDS /l0_dds_writer_test1_aik/uut/valid_out_dds -add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_writer_test1_aik/uut/data_out_dds -add wave -noupdate -expand -group DDS /l0_dds_writer_test1_aik/uut/last_word_out_dds -add wave -noupdate -divider {MAIN FSM} -add wave -noupdate /l0_dds_writer_test1_aik/uut/stage -add wave -noupdate /l0_dds_writer_test1_aik/uut/cnt -add wave -noupdate -radix unsigned /l0_dds_writer_test1_aik/uut/global_seq_nr -add wave -noupdate -radix unsigned /l0_dds_writer_test1_aik/uut/global_sample_cnt -add wave -noupdate -radix unsigned /l0_dds_writer_test1_aik/uut/global_ack_cnt -add wave -noupdate -radix unsigned /l0_dds_writer_test1_aik/uut/stale_inst_cnt -add wave -noupdate /l0_dds_writer_test1_aik/uut/remove_oldest_inst_sample -add wave -noupdate /l0_dds_writer_test1_aik/uut/remove_oldest_sample -add wave -noupdate /l0_dds_writer_test1_aik/uut/remove_ack_sample -add wave -noupdate -divider MEMORY -add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test1_aik/uut/sample_abort_read -add wave -noupdate -group {SAMPLE MEM} -radix unsigned -childformat {{/l0_dds_writer_test1_aik/uut/sample_mem_ctrl_inst/addr(5) -radix unsigned} {/l0_dds_writer_test1_aik/uut/sample_mem_ctrl_inst/addr(4) -radix unsigned} {/l0_dds_writer_test1_aik/uut/sample_mem_ctrl_inst/addr(3) -radix unsigned} {/l0_dds_writer_test1_aik/uut/sample_mem_ctrl_inst/addr(2) -radix unsigned} {/l0_dds_writer_test1_aik/uut/sample_mem_ctrl_inst/addr(1) -radix unsigned} {/l0_dds_writer_test1_aik/uut/sample_mem_ctrl_inst/addr(0) -radix unsigned}} -subitemconfig {/l0_dds_writer_test1_aik/uut/sample_mem_ctrl_inst/addr(5) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/sample_mem_ctrl_inst/addr(4) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/sample_mem_ctrl_inst/addr(3) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/sample_mem_ctrl_inst/addr(2) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/sample_mem_ctrl_inst/addr(1) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/sample_mem_ctrl_inst/addr(0) {-height 15 -radix unsigned}} /l0_dds_writer_test1_aik/uut/sample_mem_ctrl_inst/addr -add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test1_aik/uut/sample_mem_ctrl_inst/read -add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test1_aik/uut/sample_mem_ctrl_inst/ready_in -add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test1_aik/uut/sample_mem_ctrl_inst/valid_in -add wave -noupdate -group {SAMPLE MEM} -radix hexadecimal /l0_dds_writer_test1_aik/uut/sample_mem_ctrl_inst/data_in -add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test1_aik/uut/sample_mem_ctrl_inst/ready_out -add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test1_aik/uut/sample_mem_ctrl_inst/valid_out -add wave -noupdate -group {SAMPLE MEM} -radix hexadecimal /l0_dds_writer_test1_aik/uut/sample_mem_ctrl_inst/data_out -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test1_aik/uut/payload_abort_read -add wave -noupdate -group {PAYLOAD MEM} -radix unsigned /l0_dds_writer_test1_aik/uut/payload_mem_ctrl_inst/addr -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test1_aik/uut/payload_mem_ctrl_inst/read -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test1_aik/uut/payload_mem_ctrl_inst/ready_in -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test1_aik/uut/payload_mem_ctrl_inst/valid_in -add wave -noupdate -group {PAYLOAD MEM} -radix hexadecimal /l0_dds_writer_test1_aik/uut/payload_mem_ctrl_inst/data_in -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test1_aik/uut/payload_mem_ctrl_inst/ready_out -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test1_aik/uut/payload_mem_ctrl_inst/valid_out -add wave -noupdate -group {PAYLOAD MEM} -radix hexadecimal /l0_dds_writer_test1_aik/uut/payload_mem_ctrl_inst/data_out -add wave -noupdate /l0_dds_writer_test1_aik/uut/inst_op_start -add wave -noupdate /l0_dds_writer_test1_aik/uut/inst_opcode -add wave -noupdate /l0_dds_writer_test1_aik/uut/inst_op_done -add wave -noupdate /l0_dds_writer_test1_aik/uut/inst_stage -add wave -noupdate /l0_dds_writer_test1_aik/uut/inst_cnt -add wave -noupdate -radix unsigned /l0_dds_writer_test1_aik/uut/inst_addr_base -add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test1_aik/uut/inst_abort_read -add wave -noupdate -group {INSTANCE MEM} -radix unsigned /l0_dds_writer_test1_aik/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/addr -add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test1_aik/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/read -add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test1_aik/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/ready_in -add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test1_aik/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/valid_in -add wave -noupdate -group {INSTANCE MEM} -radix hexadecimal /l0_dds_writer_test1_aik/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/data_in -add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test1_aik/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/ready_out -add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test1_aik/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/valid_out -add wave -noupdate -group {INSTANCE MEM} -radix hexadecimal /l0_dds_writer_test1_aik/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/data_out -add wave -noupdate -childformat {{/l0_dds_writer_test1_aik/uut/inst_data.addr -radix unsigned} {/l0_dds_writer_test1_aik/uut/inst_data.key_hash -radix hexadecimal} {/l0_dds_writer_test1_aik/uut/inst_data.status_info -radix binary} {/l0_dds_writer_test1_aik/uut/inst_data.sample_cnt -radix unsigned} {/l0_dds_writer_test1_aik/uut/inst_data.ack_cnt -radix unsigned}} -subitemconfig {/l0_dds_writer_test1_aik/uut/inst_data.addr {-radix unsigned} /l0_dds_writer_test1_aik/uut/inst_data.key_hash {-height 15 -radix hexadecimal} /l0_dds_writer_test1_aik/uut/inst_data.status_info {-height 15 -radix binary} /l0_dds_writer_test1_aik/uut/inst_data.sample_cnt {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/inst_data.ack_cnt {-height 15 -radix unsigned}} /l0_dds_writer_test1_aik/uut/inst_data -add wave -noupdate -divider {KEY HOLDER} -add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test1_aik/uut/start_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test1_aik/uut/opcode_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test1_aik/uut/ack_kh -add wave -noupdate -group {KEY HOLDER} -radix hexadecimal /l0_dds_writer_test1_aik/uut/data_in_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test1_aik/uut/valid_in_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test1_aik/uut/ready_in_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test1_aik/uut/last_word_in_kh -add wave -noupdate -group {KEY HOLDER} -radix hexadecimal /l0_dds_writer_test1_aik/uut/data_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test1_aik/uut/valid_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test1_aik/uut/ready_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test1_aik/uut/last_word_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test1_aik/uut/abort_kh -add wave -noupdate -divider POINTERS -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test1_aik/uut/empty_sample_list_head -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test1_aik/uut/empty_sample_list_tail -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test1_aik/uut/empty_payload_list_head -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test1_aik/uut/oldest_sample -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test1_aik/uut/newest_sample -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test1_aik/uut/inst_empty_head -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test1_aik/uut/inst_occupied_head -add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test1_aik/uut/cur_sample -add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test1_aik/uut/prev_sample -add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test1_aik/uut/next_sample -add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test1_aik/uut/cur_payload -add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test1_aik/uut/next_payload -add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test1_aik/uut/cur_inst -add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test1_aik/uut/next_inst -add wave -noupdate -divider TESTBENCH -add wave -noupdate -divider MISC -add wave -noupdate /l0_dds_writer_test1_aik/uut/cnt2 -add wave -noupdate /l0_dds_writer_test1_aik/uut/cnt3 -add wave -noupdate -radix unsigned /l0_dds_writer_test1_aik/uut/long_latch -add wave -noupdate /l0_dds_writer_test1_aik/uut/sample_status_info -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {34725000 ps} 0} -quietly wave cursor active 1 -configure wave -namecolwidth 187 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -configure wave -timelineunits ns -update -WaveRestoreZoom {34274712 ps} {35275353 ps} diff --git a/sim/L0_dds_writer_test1_ain.do b/sim/L0_dds_writer_test1_ain.do deleted file mode 100644 index 2a05b49..0000000 --- a/sim/L0_dds_writer_test1_ain.do +++ /dev/null @@ -1,128 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -divider SYSTEM -add wave -noupdate /l0_dds_writer_test1_ain/uut/clk -add wave -noupdate /l0_dds_writer_test1_ain/uut/reset -add wave -noupdate -radix unsigned /l0_dds_writer_test1_ain/uut/time -add wave -noupdate -divider {RTPS IN} -add wave -noupdate -group {RTPS IN} /l0_dds_writer_test1_ain/uut/start_rtps -add wave -noupdate -group {RTPS IN} -radix unsigned /l0_dds_writer_test1_ain/uut/seq_nr_rtps -add wave -noupdate -group {RTPS IN} /l0_dds_writer_test1_ain/uut/opcode_rtps -add wave -noupdate -group {RTPS IN} /l0_dds_writer_test1_ain/uut/ack_rtps -add wave -noupdate -group {RTPS IN} /l0_dds_writer_test1_ain/uut/done_rtps -add wave -noupdate -group {RTPS IN} /l0_dds_writer_test1_ain/uut/ret_rtps -add wave -noupdate -divider {RTPS OUT} -add wave -noupdate -group {RTPS OUT} -radix hexadecimal /l0_dds_writer_test1_ain/uut/cc_instance_handle -add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test1_ain/uut/cc_kind -add wave -noupdate -group {RTPS OUT} -radix unsigned /l0_dds_writer_test1_ain/uut/cc_source_timestamp -add wave -noupdate -group {RTPS OUT} -radix unsigned -childformat {{/l0_dds_writer_test1_ain/uut/cc_seq_nr(0) -radix unsigned -childformat {{/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(31) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(30) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(29) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(28) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(27) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(26) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(25) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(24) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(23) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(22) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(21) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(20) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(19) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(18) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(17) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(16) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(15) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(14) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(13) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(12) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(11) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(10) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(9) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(8) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(7) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(6) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(5) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(4) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(3) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(2) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(1) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(0) -radix unsigned}}} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(1) -radix unsigned}} -subitemconfig {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0) {-height 15 -radix unsigned -childformat {{/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(31) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(30) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(29) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(28) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(27) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(26) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(25) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(24) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(23) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(22) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(21) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(20) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(19) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(18) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(17) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(16) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(15) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(14) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(13) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(12) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(11) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(10) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(9) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(8) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(7) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(6) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(5) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(4) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(3) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(2) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(1) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(0) -radix unsigned}}} /l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(31) {-height 15 -radix unsigned} /l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(30) {-height 15 -radix unsigned} /l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(29) {-height 15 -radix unsigned} /l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(28) {-height 15 -radix unsigned} /l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(27) {-height 15 -radix unsigned} /l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(26) {-height 15 -radix unsigned} /l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(25) {-height 15 -radix unsigned} /l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(24) {-height 15 -radix unsigned} /l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(23) {-height 15 -radix unsigned} /l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(22) {-height 15 -radix unsigned} /l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(21) {-height 15 -radix unsigned} /l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(20) {-height 15 -radix unsigned} /l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(19) {-height 15 -radix unsigned} /l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(18) {-height 15 -radix unsigned} /l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(17) {-height 15 -radix unsigned} /l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(16) {-height 15 -radix unsigned} /l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(15) {-height 15 -radix unsigned} /l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(14) {-height 15 -radix unsigned} /l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(13) {-height 15 -radix unsigned} /l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(12) {-height 15 -radix unsigned} /l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(11) {-height 15 -radix unsigned} /l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(10) {-height 15 -radix unsigned} /l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(9) {-height 15 -radix unsigned} /l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(8) {-height 15 -radix unsigned} /l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(7) {-height 15 -radix unsigned} /l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(6) {-height 15 -radix unsigned} /l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(5) {-height 15 -radix unsigned} /l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(4) {-height 15 -radix unsigned} /l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(3) {-height 15 -radix unsigned} /l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(2) {-height 15 -radix unsigned} /l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(1) {-height 15 -radix unsigned} /l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(0) {-height 15 -radix unsigned} /l0_dds_writer_test1_ain/uut/cc_seq_nr(1) {-height 15 -radix unsigned}} /l0_dds_writer_test1_ain/uut/cc_seq_nr -add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test1_ain/uut/get_data_rtps -add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test1_ain/uut/ready_out_rtps -add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test1_ain/uut/valid_out_rtps -add wave -noupdate -group {RTPS OUT} -radix hexadecimal /l0_dds_writer_test1_ain/uut/data_out_rtps -add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test1_ain/uut/last_word_out_rtps -add wave -noupdate -divider {DDS IN} -add wave -noupdate -expand -group DDS /l0_dds_writer_test1_ain/uut/start_dds -add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_writer_test1_ain/uut/instance_handle_dds -add wave -noupdate -expand -group DDS -radix unsigned /l0_dds_writer_test1_ain/uut/source_ts_dds -add wave -noupdate -expand -group DDS /l0_dds_writer_test1_ain/uut/opcode_dds -add wave -noupdate -expand -group DDS /l0_dds_writer_test1_ain/uut/ack_dds -add wave -noupdate -expand -group DDS /l0_dds_writer_test1_ain/uut/done_dds -add wave -noupdate -expand -group DDS -radix unsigned /l0_dds_writer_test1_ain/uut/return_code_dds -add wave -noupdate -expand -group DDS /l0_dds_writer_test1_ain/uut/ready_in_dds -add wave -noupdate -expand -group DDS /l0_dds_writer_test1_ain/uut/valid_in_dds -add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_writer_test1_ain/uut/data_in_dds -add wave -noupdate -expand -group DDS /l0_dds_writer_test1_ain/uut/last_word_in_dds -add wave -noupdate -expand -group DDS /l0_dds_writer_test1_ain/uut/ready_out_dds -add wave -noupdate -expand -group DDS /l0_dds_writer_test1_ain/uut/valid_out_dds -add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_writer_test1_ain/uut/data_out_dds -add wave -noupdate -expand -group DDS /l0_dds_writer_test1_ain/uut/last_word_out_dds -add wave -noupdate -divider {MAIN FSM} -add wave -noupdate /l0_dds_writer_test1_ain/uut/stage -add wave -noupdate /l0_dds_writer_test1_ain/uut/stage_next -add wave -noupdate /l0_dds_writer_test1_ain/uut/cnt -add wave -noupdate -radix unsigned /l0_dds_writer_test1_ain/uut/global_seq_nr -add wave -noupdate -radix unsigned /l0_dds_writer_test1_ain/uut/global_sample_cnt -add wave -noupdate -radix unsigned /l0_dds_writer_test1_ain/uut/global_ack_cnt -add wave -noupdate -radix unsigned /l0_dds_writer_test1_ain/uut/stale_inst_cnt -add wave -noupdate /l0_dds_writer_test1_ain/uut/remove_oldest_inst_sample -add wave -noupdate /l0_dds_writer_test1_ain/uut/remove_oldest_sample -add wave -noupdate /l0_dds_writer_test1_ain/uut/remove_ack_sample -add wave -noupdate -divider MEMORY -add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test1_ain/uut/sample_abort_read -add wave -noupdate -group {SAMPLE MEM} -radix unsigned -childformat {{/l0_dds_writer_test1_ain/uut/sample_mem_ctrl_inst/addr(5) -radix unsigned} {/l0_dds_writer_test1_ain/uut/sample_mem_ctrl_inst/addr(4) -radix unsigned} {/l0_dds_writer_test1_ain/uut/sample_mem_ctrl_inst/addr(3) -radix unsigned} {/l0_dds_writer_test1_ain/uut/sample_mem_ctrl_inst/addr(2) -radix unsigned} {/l0_dds_writer_test1_ain/uut/sample_mem_ctrl_inst/addr(1) -radix unsigned} {/l0_dds_writer_test1_ain/uut/sample_mem_ctrl_inst/addr(0) -radix unsigned}} -subitemconfig {/l0_dds_writer_test1_ain/uut/sample_mem_ctrl_inst/addr(5) {-height 15 -radix unsigned} /l0_dds_writer_test1_ain/uut/sample_mem_ctrl_inst/addr(4) {-height 15 -radix unsigned} /l0_dds_writer_test1_ain/uut/sample_mem_ctrl_inst/addr(3) {-height 15 -radix unsigned} /l0_dds_writer_test1_ain/uut/sample_mem_ctrl_inst/addr(2) {-height 15 -radix unsigned} /l0_dds_writer_test1_ain/uut/sample_mem_ctrl_inst/addr(1) {-height 15 -radix unsigned} /l0_dds_writer_test1_ain/uut/sample_mem_ctrl_inst/addr(0) {-height 15 -radix unsigned}} /l0_dds_writer_test1_ain/uut/sample_mem_ctrl_inst/addr -add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test1_ain/uut/sample_mem_ctrl_inst/read -add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test1_ain/uut/sample_mem_ctrl_inst/ready_in -add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test1_ain/uut/sample_mem_ctrl_inst/valid_in -add wave -noupdate -group {SAMPLE MEM} -radix hexadecimal /l0_dds_writer_test1_ain/uut/sample_mem_ctrl_inst/data_in -add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test1_ain/uut/sample_mem_ctrl_inst/ready_out -add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test1_ain/uut/sample_mem_ctrl_inst/valid_out -add wave -noupdate -group {SAMPLE MEM} -radix hexadecimal /l0_dds_writer_test1_ain/uut/sample_mem_ctrl_inst/data_out -add wave -noupdate -expand -group {PAYLOAD MEM} /l0_dds_writer_test1_ain/uut/payload_abort_read -add wave -noupdate -expand -group {PAYLOAD MEM} -radix unsigned /l0_dds_writer_test1_ain/uut/payload_mem_ctrl_inst/addr -add wave -noupdate -expand -group {PAYLOAD MEM} /l0_dds_writer_test1_ain/uut/payload_mem_ctrl_inst/read -add wave -noupdate -expand -group {PAYLOAD MEM} /l0_dds_writer_test1_ain/uut/payload_mem_ctrl_inst/ready_in -add wave -noupdate -expand -group {PAYLOAD MEM} /l0_dds_writer_test1_ain/uut/payload_mem_ctrl_inst/valid_in -add wave -noupdate -expand -group {PAYLOAD MEM} -radix hexadecimal /l0_dds_writer_test1_ain/uut/payload_mem_ctrl_inst/data_in -add wave -noupdate -expand -group {PAYLOAD MEM} /l0_dds_writer_test1_ain/uut/payload_mem_ctrl_inst/ready_out -add wave -noupdate -expand -group {PAYLOAD MEM} /l0_dds_writer_test1_ain/uut/payload_mem_ctrl_inst/valid_out -add wave -noupdate -expand -group {PAYLOAD MEM} -radix hexadecimal /l0_dds_writer_test1_ain/uut/payload_mem_ctrl_inst/data_out -add wave -noupdate -childformat {{/l0_dds_writer_test1_ain/uut/inst_data.key_hash -radix hexadecimal} {/l0_dds_writer_test1_ain/uut/inst_data.status_info -radix binary} {/l0_dds_writer_test1_ain/uut/inst_data.sample_cnt -radix unsigned} {/l0_dds_writer_test1_ain/uut/inst_data.ack_cnt -radix unsigned}} -expand -subitemconfig {/l0_dds_writer_test1_ain/uut/inst_data.key_hash {-height 15 -radix hexadecimal} /l0_dds_writer_test1_ain/uut/inst_data.status_info {-height 15 -radix binary} /l0_dds_writer_test1_ain/uut/inst_data.sample_cnt {-height 15 -radix unsigned} /l0_dds_writer_test1_ain/uut/inst_data.ack_cnt {-height 15 -radix unsigned}} /l0_dds_writer_test1_ain/uut/inst_data -add wave -noupdate -divider {KEY HOLDER} -add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test1_ain/uut/start_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test1_ain/uut/opcode_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test1_ain/uut/ack_kh -add wave -noupdate -group {KEY HOLDER} -radix hexadecimal /l0_dds_writer_test1_ain/uut/data_in_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test1_ain/uut/valid_in_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test1_ain/uut/ready_in_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test1_ain/uut/last_word_in_kh -add wave -noupdate -group {KEY HOLDER} -radix hexadecimal /l0_dds_writer_test1_ain/uut/data_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test1_ain/uut/valid_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test1_ain/uut/ready_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test1_ain/uut/last_word_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test1_ain/uut/abort_kh -add wave -noupdate -divider POINTERS -add wave -noupdate -expand -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test1_ain/uut/empty_sample_list_head -add wave -noupdate -expand -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test1_ain/uut/empty_sample_list_tail -add wave -noupdate -expand -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test1_ain/uut/empty_payload_list_head -add wave -noupdate -expand -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test1_ain/uut/oldest_sample -add wave -noupdate -expand -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test1_ain/uut/newest_sample -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test1_ain/uut/cur_sample -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test1_ain/uut/prev_sample -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test1_ain/uut/next_sample -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test1_ain/uut/cur_payload -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test1_ain/uut/next_payload -add wave -noupdate -divider TESTBENCH -add wave -noupdate -expand -group TESTBENCH /l0_dds_writer_test1_ain/stim_start -add wave -noupdate -expand -group TESTBENCH /l0_dds_writer_test1_ain/stim_stage -add wave -noupdate -expand -group TESTBENCH /l0_dds_writer_test1_ain/stim_cnt -add wave -noupdate -expand -group TESTBENCH /l0_dds_writer_test1_ain/stim_done -add wave -noupdate -expand -group TESTBENCH /l0_dds_writer_test1_ain/ref_start -add wave -noupdate -expand -group TESTBENCH /l0_dds_writer_test1_ain/ref_stage -add wave -noupdate -expand -group TESTBENCH /l0_dds_writer_test1_ain/ref_cnt -add wave -noupdate -expand -group TESTBENCH /l0_dds_writer_test1_ain/ref_done -add wave -noupdate -expand -group TESTBENCH /l0_dds_writer_test1_ain/kh_cnt -add wave -noupdate -expand -group TESTBENCH /l0_dds_writer_test1_ain/kh_stage -add wave -noupdate -divider MISC -add wave -noupdate /l0_dds_writer_test1_ain/uut/cnt2 -add wave -noupdate /l0_dds_writer_test1_ain/uut/cnt3 -add wave -noupdate -radix unsigned /l0_dds_writer_test1_ain/uut/long_latch -add wave -noupdate /l0_dds_writer_test1_ain/uut/sample_status_info -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {642360 ps} 0} -quietly wave cursor active 1 -configure wave -namecolwidth 187 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -configure wave -timelineunits ns -update -WaveRestoreZoom {300185 ps} {1300826 ps} diff --git a/sim/L0_dds_writer_test1_lik.do b/sim/L0_dds_writer_test1_lik.do deleted file mode 100644 index 41021ad..0000000 --- a/sim/L0_dds_writer_test1_lik.do +++ /dev/null @@ -1,150 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -divider SYSTEM -add wave -noupdate /l0_dds_writer_test1_lik/uut/clk -add wave -noupdate /l0_dds_writer_test1_lik/uut/reset -add wave -noupdate -radix unsigned /l0_dds_writer_test1_lik/uut/time -add wave -noupdate -divider {RTPS IN} -add wave -noupdate -group {RTPS IN} /l0_dds_writer_test1_lik/uut/start_rtps -add wave -noupdate -group {RTPS IN} -radix unsigned /l0_dds_writer_test1_lik/uut/seq_nr_rtps -add wave -noupdate -group {RTPS IN} /l0_dds_writer_test1_lik/uut/opcode_rtps -add wave -noupdate -group {RTPS IN} /l0_dds_writer_test1_lik/uut/ack_rtps -add wave -noupdate -group {RTPS IN} /l0_dds_writer_test1_lik/uut/done_rtps -add wave -noupdate -group {RTPS IN} /l0_dds_writer_test1_lik/uut/ret_rtps -add wave -noupdate -divider {RTPS OUT} -add wave -noupdate -group {RTPS OUT} -radix hexadecimal /l0_dds_writer_test1_lik/uut/cc_instance_handle -add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test1_lik/uut/cc_kind -add wave -noupdate -group {RTPS OUT} -radix unsigned /l0_dds_writer_test1_lik/uut/cc_source_timestamp -add wave -noupdate -group {RTPS OUT} -radix unsigned -childformat {{/l0_dds_writer_test1_lik/uut/cc_seq_nr(0) -radix unsigned -childformat {{/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(31) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(30) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(29) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(28) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(27) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(26) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(25) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(24) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(23) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(22) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(21) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(20) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(19) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(18) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(17) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(16) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(15) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(14) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(13) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(12) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(11) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(10) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(9) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(8) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(7) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(6) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(5) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(4) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(3) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(2) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(1) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(0) -radix unsigned}}} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(1) -radix unsigned}} -subitemconfig {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0) {-height 15 -radix unsigned -childformat {{/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(31) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(30) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(29) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(28) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(27) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(26) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(25) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(24) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(23) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(22) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(21) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(20) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(19) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(18) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(17) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(16) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(15) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(14) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(13) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(12) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(11) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(10) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(9) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(8) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(7) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(6) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(5) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(4) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(3) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(2) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(1) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(0) -radix unsigned}}} /l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(31) {-height 15 -radix unsigned} /l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(30) {-height 15 -radix unsigned} /l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(29) {-height 15 -radix unsigned} /l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(28) {-height 15 -radix unsigned} /l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(27) {-height 15 -radix unsigned} /l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(26) {-height 15 -radix unsigned} /l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(25) {-height 15 -radix unsigned} /l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(24) {-height 15 -radix unsigned} /l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(23) {-height 15 -radix unsigned} /l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(22) {-height 15 -radix unsigned} /l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(21) {-height 15 -radix unsigned} /l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(20) {-height 15 -radix unsigned} /l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(19) {-height 15 -radix unsigned} /l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(18) {-height 15 -radix unsigned} /l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(17) {-height 15 -radix unsigned} /l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(16) {-height 15 -radix unsigned} /l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(15) {-height 15 -radix unsigned} /l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(14) {-height 15 -radix unsigned} /l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(13) {-height 15 -radix unsigned} /l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(12) {-height 15 -radix unsigned} /l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(11) {-height 15 -radix unsigned} /l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(10) {-height 15 -radix unsigned} /l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(9) {-height 15 -radix unsigned} /l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(8) {-height 15 -radix unsigned} /l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(7) {-height 15 -radix unsigned} /l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(6) {-height 15 -radix unsigned} /l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(5) {-height 15 -radix unsigned} /l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(4) {-height 15 -radix unsigned} /l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(3) {-height 15 -radix unsigned} /l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(2) {-height 15 -radix unsigned} /l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(1) {-height 15 -radix unsigned} /l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(0) {-height 15 -radix unsigned} /l0_dds_writer_test1_lik/uut/cc_seq_nr(1) {-height 15 -radix unsigned}} /l0_dds_writer_test1_lik/uut/cc_seq_nr -add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test1_lik/uut/get_data_rtps -add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test1_lik/uut/ready_out_rtps -add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test1_lik/uut/valid_out_rtps -add wave -noupdate -group {RTPS OUT} -radix hexadecimal /l0_dds_writer_test1_lik/uut/data_out_rtps -add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test1_lik/uut/last_word_out_rtps -add wave -noupdate -divider {DDS IN} -add wave -noupdate -expand -group DDS /l0_dds_writer_test1_lik/uut/start_dds -add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_writer_test1_lik/uut/instance_handle_dds -add wave -noupdate -expand -group DDS -radix unsigned /l0_dds_writer_test1_lik/uut/source_ts_dds -add wave -noupdate -expand -group DDS /l0_dds_writer_test1_lik/uut/opcode_dds -add wave -noupdate -expand -group DDS /l0_dds_writer_test1_lik/uut/ack_dds -add wave -noupdate -expand -group DDS /l0_dds_writer_test1_lik/uut/done_dds -add wave -noupdate -expand -group DDS -radix unsigned /l0_dds_writer_test1_lik/uut/return_code_dds -add wave -noupdate -expand -group DDS /l0_dds_writer_test1_lik/uut/ready_in_dds -add wave -noupdate -expand -group DDS /l0_dds_writer_test1_lik/uut/valid_in_dds -add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_writer_test1_lik/uut/data_in_dds -add wave -noupdate -expand -group DDS /l0_dds_writer_test1_lik/uut/last_word_in_dds -add wave -noupdate -expand -group DDS /l0_dds_writer_test1_lik/uut/ready_out_dds -add wave -noupdate -expand -group DDS /l0_dds_writer_test1_lik/uut/valid_out_dds -add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_writer_test1_lik/uut/data_out_dds -add wave -noupdate -expand -group DDS /l0_dds_writer_test1_lik/uut/last_word_out_dds -add wave -noupdate -divider {MAIN FSM} -add wave -noupdate /l0_dds_writer_test1_lik/uut/stage -add wave -noupdate /l0_dds_writer_test1_lik/uut/stage_next -add wave -noupdate /l0_dds_writer_test1_lik/uut/cnt -add wave -noupdate -radix unsigned /l0_dds_writer_test1_lik/uut/global_seq_nr -add wave -noupdate -radix unsigned /l0_dds_writer_test1_lik/uut/global_sample_cnt -add wave -noupdate -radix unsigned /l0_dds_writer_test1_lik/uut/global_ack_cnt -add wave -noupdate -radix unsigned /l0_dds_writer_test1_lik/uut/stale_inst_cnt -add wave -noupdate /l0_dds_writer_test1_lik/uut/remove_oldest_inst_sample -add wave -noupdate /l0_dds_writer_test1_lik/uut/remove_oldest_sample -add wave -noupdate /l0_dds_writer_test1_lik/uut/remove_ack_sample -add wave -noupdate -divider MEMORY -add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test1_lik/uut/sample_abort_read -add wave -noupdate -group {SAMPLE MEM} -radix unsigned -childformat {{/l0_dds_writer_test1_lik/uut/sample_mem_ctrl_inst/addr(5) -radix unsigned} {/l0_dds_writer_test1_lik/uut/sample_mem_ctrl_inst/addr(4) -radix unsigned} {/l0_dds_writer_test1_lik/uut/sample_mem_ctrl_inst/addr(3) -radix unsigned} {/l0_dds_writer_test1_lik/uut/sample_mem_ctrl_inst/addr(2) -radix unsigned} {/l0_dds_writer_test1_lik/uut/sample_mem_ctrl_inst/addr(1) -radix unsigned} {/l0_dds_writer_test1_lik/uut/sample_mem_ctrl_inst/addr(0) -radix unsigned}} -subitemconfig {/l0_dds_writer_test1_lik/uut/sample_mem_ctrl_inst/addr(5) {-height 15 -radix unsigned} /l0_dds_writer_test1_lik/uut/sample_mem_ctrl_inst/addr(4) {-height 15 -radix unsigned} /l0_dds_writer_test1_lik/uut/sample_mem_ctrl_inst/addr(3) {-height 15 -radix unsigned} /l0_dds_writer_test1_lik/uut/sample_mem_ctrl_inst/addr(2) {-height 15 -radix unsigned} /l0_dds_writer_test1_lik/uut/sample_mem_ctrl_inst/addr(1) {-height 15 -radix unsigned} /l0_dds_writer_test1_lik/uut/sample_mem_ctrl_inst/addr(0) {-height 15 -radix unsigned}} /l0_dds_writer_test1_lik/uut/sample_mem_ctrl_inst/addr -add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test1_lik/uut/sample_mem_ctrl_inst/read -add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test1_lik/uut/sample_mem_ctrl_inst/ready_in -add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test1_lik/uut/sample_mem_ctrl_inst/valid_in -add wave -noupdate -group {SAMPLE MEM} -radix hexadecimal /l0_dds_writer_test1_lik/uut/sample_mem_ctrl_inst/data_in -add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test1_lik/uut/sample_mem_ctrl_inst/ready_out -add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test1_lik/uut/sample_mem_ctrl_inst/valid_out -add wave -noupdate -group {SAMPLE MEM} -radix hexadecimal /l0_dds_writer_test1_lik/uut/sample_mem_ctrl_inst/data_out -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test1_lik/uut/payload_abort_read -add wave -noupdate -group {PAYLOAD MEM} -radix unsigned /l0_dds_writer_test1_lik/uut/payload_mem_ctrl_inst/addr -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test1_lik/uut/payload_mem_ctrl_inst/read -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test1_lik/uut/payload_mem_ctrl_inst/ready_in -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test1_lik/uut/payload_mem_ctrl_inst/valid_in -add wave -noupdate -group {PAYLOAD MEM} -radix hexadecimal /l0_dds_writer_test1_lik/uut/payload_mem_ctrl_inst/data_in -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test1_lik/uut/payload_mem_ctrl_inst/ready_out -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test1_lik/uut/payload_mem_ctrl_inst/valid_out -add wave -noupdate -group {PAYLOAD MEM} -radix hexadecimal /l0_dds_writer_test1_lik/uut/payload_mem_ctrl_inst/data_out -add wave -noupdate /l0_dds_writer_test1_lik/uut/inst_op_start -add wave -noupdate /l0_dds_writer_test1_lik/uut/inst_opcode -add wave -noupdate /l0_dds_writer_test1_lik/uut/inst_op_done -add wave -noupdate /l0_dds_writer_test1_lik/uut/inst_stage -add wave -noupdate /l0_dds_writer_test1_lik/uut/inst_stage_next -add wave -noupdate /l0_dds_writer_test1_lik/uut/inst_cnt -add wave -noupdate -radix unsigned /l0_dds_writer_test1_lik/uut/inst_addr_base -add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test1_lik/uut/inst_abort_read -add wave -noupdate -group {INSTANCE MEM} -radix unsigned /l0_dds_writer_test1_lik/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/addr -add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test1_lik/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/read -add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test1_lik/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/ready_in -add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test1_lik/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/valid_in -add wave -noupdate -group {INSTANCE MEM} -radix hexadecimal /l0_dds_writer_test1_lik/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/data_in -add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test1_lik/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/ready_out -add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test1_lik/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/valid_out -add wave -noupdate -group {INSTANCE MEM} -radix hexadecimal /l0_dds_writer_test1_lik/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/data_out -add wave -noupdate -childformat {{/l0_dds_writer_test1_lik/uut/inst_data.key_hash -radix hexadecimal} {/l0_dds_writer_test1_lik/uut/inst_data.status_info -radix binary} {/l0_dds_writer_test1_lik/uut/inst_data.sample_cnt -radix unsigned} {/l0_dds_writer_test1_lik/uut/inst_data.ack_cnt -radix unsigned}} -expand -subitemconfig {/l0_dds_writer_test1_lik/uut/inst_data.key_hash {-height 15 -radix hexadecimal} /l0_dds_writer_test1_lik/uut/inst_data.status_info {-height 15 -radix binary} /l0_dds_writer_test1_lik/uut/inst_data.sample_cnt {-height 15 -radix unsigned} /l0_dds_writer_test1_lik/uut/inst_data.ack_cnt {-height 15 -radix unsigned}} /l0_dds_writer_test1_lik/uut/inst_data -add wave -noupdate -radix unsigned /l0_dds_writer_test1_lik/uut/inst_next_addr_base -add wave -noupdate -radix unsigned /l0_dds_writer_test1_lik/uut/inst_prev_addr_base -add wave -noupdate -divider {KEY HOLDER} -add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test1_lik/uut/start_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test1_lik/uut/opcode_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test1_lik/uut/ack_kh -add wave -noupdate -group {KEY HOLDER} -radix hexadecimal /l0_dds_writer_test1_lik/uut/data_in_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test1_lik/uut/valid_in_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test1_lik/uut/ready_in_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test1_lik/uut/last_word_in_kh -add wave -noupdate -group {KEY HOLDER} -radix hexadecimal /l0_dds_writer_test1_lik/uut/data_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test1_lik/uut/valid_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test1_lik/uut/ready_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test1_lik/uut/last_word_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test1_lik/uut/abort_kh -add wave -noupdate -divider POINTERS -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test1_lik/uut/empty_sample_list_head -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test1_lik/uut/empty_sample_list_tail -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test1_lik/uut/empty_payload_list_head -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test1_lik/uut/oldest_sample -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test1_lik/uut/newest_sample -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test1_lik/uut/inst_empty_head -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test1_lik/uut/inst_occupied_head -add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test1_lik/uut/cur_sample -add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test1_lik/uut/prev_sample -add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test1_lik/uut/next_sample -add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test1_lik/uut/cur_payload -add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test1_lik/uut/next_payload -add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test1_lik/uut/cur_inst -add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test1_lik/uut/next_inst -add wave -noupdate -divider TESTBENCH -add wave -noupdate -group TESTBENCH /l0_dds_writer_test1_lik/stim_start -add wave -noupdate -group TESTBENCH /l0_dds_writer_test1_lik/stim_stage -add wave -noupdate -group TESTBENCH /l0_dds_writer_test1_lik/stim_cnt -add wave -noupdate -group TESTBENCH /l0_dds_writer_test1_lik/stim_done -add wave -noupdate -group TESTBENCH /l0_dds_writer_test1_lik/ref_start -add wave -noupdate -group TESTBENCH /l0_dds_writer_test1_lik/ref_stage -add wave -noupdate -group TESTBENCH /l0_dds_writer_test1_lik/ref_cnt -add wave -noupdate -group TESTBENCH /l0_dds_writer_test1_lik/ref_done -add wave -noupdate -group TESTBENCH /l0_dds_writer_test1_lik/kh_cnt -add wave -noupdate -group TESTBENCH /l0_dds_writer_test1_lik/kh_stage -add wave -noupdate -divider MISC -add wave -noupdate /l0_dds_writer_test1_lik/uut/cnt2 -add wave -noupdate /l0_dds_writer_test1_lik/uut/cnt3 -add wave -noupdate -radix unsigned /l0_dds_writer_test1_lik/uut/long_latch -add wave -noupdate /l0_dds_writer_test1_lik/uut/sample_status_info -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {106575000 ps} 0} -quietly wave cursor active 1 -configure wave -namecolwidth 187 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -configure wave -timelineunits ns -update -WaveRestoreZoom {106074680 ps} {107075321 ps} diff --git a/sim/L0_dds_writer_test2.do b/sim/L0_dds_writer_test2.do new file mode 100644 index 0000000..8c3af7f --- /dev/null +++ b/sim/L0_dds_writer_test2.do @@ -0,0 +1,154 @@ +onerror {resume} +radix define DDS_RETCODE { + "10#0#" "RETCODE_OK", + "10#1#" "RETCODE_ERROR", + "10#2#" "RETCODE_UNSUPPORTED", + "10#3#" "RETCODE_BAD_PARAMETER", + "10#4#" "RETCODE_PRECONDITION_NOT_MET", + "10#5#" "RETCODE_OUT_OF_RESOURCES", + "10#6#" "RETCODE_NOT_ENABLED", + "10#7#" "RETCODE_IMMUTABLE_POLICY", + "10#8#" "RETCODE_INCONSISTENT_POLICY", + "10#9#" "RETCODE_ALREADY_DELETED", + "10#10#" "RETCODE_TIMEOUT", + "10#11#" "RETCODE_NO_DATA", + "10#12#" "RETCODE_ILLEGAL_OPERATION", + -default unsigned +} +quietly WaveActivateNextPane {} 0 +add wave -noupdate -divider SYSTEM +add wave -noupdate /l0_dds_writer_test2/uut/clk +add wave -noupdate /l0_dds_writer_test2/uut/reset +add wave -noupdate -radix unsigned /l0_dds_writer_test2/uut/time +add wave -noupdate -radix unsigned /l0_dds_writer_test2/uut/timeout_check_time +add wave -noupdate -divider {RTPS IN} +add wave -noupdate -group {RTPS IN} /l0_dds_writer_test2/uut/start_rtps +add wave -noupdate -group {RTPS IN} -radix unsigned /l0_dds_writer_test2/uut/seq_nr_rtps +add wave -noupdate -group {RTPS IN} /l0_dds_writer_test2/uut/opcode_rtps +add wave -noupdate -group {RTPS IN} /l0_dds_writer_test2/uut/ack_rtps +add wave -noupdate -group {RTPS IN} /l0_dds_writer_test2/uut/done_rtps +add wave -noupdate -group {RTPS IN} /l0_dds_writer_test2/uut/ret_rtps +add wave -noupdate -divider {RTPS OUT} +add wave -noupdate -group {RTPS OUT} -radix hexadecimal /l0_dds_writer_test2/uut/cc_instance_handle +add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test2/uut/cc_kind +add wave -noupdate -group {RTPS OUT} -radix unsigned /l0_dds_writer_test2/uut/cc_source_timestamp +add wave -noupdate -group {RTPS OUT} -radix unsigned -childformat {{/l0_dds_writer_test2/uut/cc_seq_nr(0) -radix unsigned -childformat {{/l0_dds_writer_test2/uut/cc_seq_nr(0)(0) -radix unsigned} {/l0_dds_writer_test2/uut/cc_seq_nr(0)(1) -radix unsigned}}} {/l0_dds_writer_test2/uut/cc_seq_nr(1) -radix unsigned}} -subitemconfig {/l0_dds_writer_test2/uut/cc_seq_nr(0) {-height 15 -radix unsigned -childformat {{/l0_dds_writer_test2/uut/cc_seq_nr(0)(0) -radix unsigned} {/l0_dds_writer_test2/uut/cc_seq_nr(0)(1) -radix unsigned}}} /l0_dds_writer_test2/uut/cc_seq_nr(0)(0) {-height 15 -radix unsigned} /l0_dds_writer_test2/uut/cc_seq_nr(0)(1) {-height 15 -radix unsigned} /l0_dds_writer_test2/uut/cc_seq_nr(1) {-height 15 -radix unsigned}} /l0_dds_writer_test2/uut/cc_seq_nr +add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test2/uut/get_data_rtps +add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test2/uut/ready_out_rtps +add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test2/uut/valid_out_rtps +add wave -noupdate -group {RTPS OUT} -radix hexadecimal /l0_dds_writer_test2/uut/data_out_rtps +add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test2/uut/last_word_out_rtps +add wave -noupdate -divider {DDS IN} +add wave -noupdate -expand -group DDS /l0_dds_writer_test2/uut/start_dds +add wave -noupdate -expand -group DDS -radix unsigned /l0_dds_writer_test2/uut/source_ts_dds +add wave -noupdate -expand -group DDS /l0_dds_writer_test2/uut/opcode_dds +add wave -noupdate -expand -group DDS -radix unsigned /l0_dds_writer_test2/uut/max_wait_dds +add wave -noupdate -expand -group DDS /l0_dds_writer_test2/uut/ack_dds +add wave -noupdate -expand -group DDS /l0_dds_writer_test2/uut/done_dds +add wave -noupdate -expand -group DDS -radix unsigned -childformat {{/l0_dds_writer_test2/uut/return_code_dds(0) -radix DDS_RETCODE} {/l0_dds_writer_test2/uut/return_code_dds(1) -radix DDS_RETCODE}} -subitemconfig {/l0_dds_writer_test2/uut/return_code_dds(0) {-height 15 -radix DDS_RETCODE} /l0_dds_writer_test2/uut/return_code_dds(1) {-height 15 -radix DDS_RETCODE}} /l0_dds_writer_test2/uut/return_code_dds +add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_writer_test2/uut/instance_handle_in_dds +add wave -noupdate -expand -group DDS /l0_dds_writer_test2/uut/ready_in_dds +add wave -noupdate -expand -group DDS /l0_dds_writer_test2/uut/valid_in_dds +add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_writer_test2/uut/data_in_dds +add wave -noupdate -expand -group DDS /l0_dds_writer_test2/uut/last_word_in_dds +add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_writer_test2/uut/instance_handle_out_dds +add wave -noupdate -expand -group DDS /l0_dds_writer_test2/uut/ready_out_dds +add wave -noupdate -expand -group DDS /l0_dds_writer_test2/uut/valid_out_dds +add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_writer_test2/uut/data_out_dds +add wave -noupdate -expand -group DDS /l0_dds_writer_test2/uut/last_word_out_dds +add wave -noupdate -divider {MAIN FSM} +add wave -noupdate /l0_dds_writer_test2/uut/stage +add wave -noupdate /l0_dds_writer_test2/uut/cnt +add wave -noupdate /l0_dds_writer_test2/uut/ind +add wave -noupdate -radix unsigned /l0_dds_writer_test2/uut/global_seq_nr +add wave -noupdate -radix unsigned /l0_dds_writer_test2/uut/global_sample_cnt +add wave -noupdate -radix unsigned /l0_dds_writer_test2/uut/global_ack_cnt +add wave -noupdate -radix unsigned /l0_dds_writer_test2/uut/stale_inst_cnt +add wave -noupdate /l0_dds_writer_test2/uut/remove_oldest_inst_sample +add wave -noupdate /l0_dds_writer_test2/uut/remove_oldest_sample +add wave -noupdate /l0_dds_writer_test2/uut/remove_ack_sample +add wave -noupdate -divider MEMORY +add wave -noupdate -group {SAMPLE MEM} -radix unsigned /l0_dds_writer_test2/uut/sample_addr +add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test2/uut/sample_read +add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test2/uut/sample_ready_in +add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test2/uut/sample_valid_in +add wave -noupdate -group {SAMPLE MEM} -radix hexadecimal /l0_dds_writer_test2/uut/sample_write_data +add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test2/uut/sample_ready_out +add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test2/uut/sample_valid_out +add wave -noupdate -group {SAMPLE MEM} -radix hexadecimal /l0_dds_writer_test2/uut/sample_read_data +add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test2/uut/sample_abort_read +add wave -noupdate -group {PAYLOAD MEM} -radix unsigned /l0_dds_writer_test2/uut/payload_addr +add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test2/uut/payload_read +add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test2/uut/payload_ready_in +add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test2/uut/payload_valid_in +add wave -noupdate -group {PAYLOAD MEM} -radix hexadecimal /l0_dds_writer_test2/uut/payload_write_data +add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test2/uut/payload_ready_out +add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test2/uut/payload_valid_out +add wave -noupdate -group {PAYLOAD MEM} -radix hexadecimal /l0_dds_writer_test2/uut/payload_read_data +add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test2/uut/payload_abort_read +add wave -noupdate /l0_dds_writer_test2/uut/inst_op_start +add wave -noupdate /l0_dds_writer_test2/uut/inst_opcode +add wave -noupdate /l0_dds_writer_test2/uut/inst_op_done +add wave -noupdate /l0_dds_writer_test2/uut/inst_stage +add wave -noupdate /l0_dds_writer_test2/uut/inst_cnt +add wave -noupdate -radix unsigned /l0_dds_writer_test2/uut/inst_addr_base +add wave -noupdate -group {INSTANCE MEM} -radix unsigned /l0_dds_writer_test2/uut/inst_addr +add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test2/uut/inst_read +add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test2/uut/inst_ready_in +add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test2/uut/inst_valid_in +add wave -noupdate -group {INSTANCE MEM} -radix hexadecimal /l0_dds_writer_test2/uut/inst_write_data +add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test2/uut/inst_ready_out +add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test2/uut/inst_valid_out +add wave -noupdate -group {INSTANCE MEM} -radix hexadecimal /l0_dds_writer_test2/uut/inst_read_data +add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test2/uut/inst_abort_read +add wave -noupdate -radix hexadecimal -childformat {{/l0_dds_writer_test2/uut/inst_data.i -radix hexadecimal} {/l0_dds_writer_test2/uut/inst_data.addr -radix unsigned} {/l0_dds_writer_test2/uut/inst_data.key_hash -radix hexadecimal} {/l0_dds_writer_test2/uut/inst_data.status_info -radix binary} {/l0_dds_writer_test2/uut/inst_data.sample_cnt -radix unsigned} {/l0_dds_writer_test2/uut/inst_data.ack_cnt -radix unsigned}} -subitemconfig {/l0_dds_writer_test2/uut/inst_data.i {-height 15 -radix hexadecimal} /l0_dds_writer_test2/uut/inst_data.addr {-height 15 -radix unsigned} /l0_dds_writer_test2/uut/inst_data.key_hash {-height 15 -radix hexadecimal} /l0_dds_writer_test2/uut/inst_data.status_info {-height 15 -radix binary} /l0_dds_writer_test2/uut/inst_data.sample_cnt {-height 15 -radix unsigned} /l0_dds_writer_test2/uut/inst_data.ack_cnt {-height 15 -radix unsigned} /l0_dds_writer_test2/uut/inst_data.field_flags {-height 15}} /l0_dds_writer_test2/uut/inst_data +add wave -noupdate -divider {KEY HOLDER} +add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test2/uut/start_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test2/uut/opcode_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test2/uut/ack_kh +add wave -noupdate -group {KEY HOLDER} -radix hexadecimal /l0_dds_writer_test2/uut/data_in_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test2/uut/valid_in_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test2/uut/ready_in_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test2/uut/last_word_in_kh +add wave -noupdate -group {KEY HOLDER} -radix hexadecimal /l0_dds_writer_test2/uut/data_out_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test2/uut/valid_out_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test2/uut/ready_out_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test2/uut/last_word_out_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test2/uut/abort_kh +add wave -noupdate -divider POINTERS +add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test2/uut/empty_sample_list_head +add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test2/uut/empty_sample_list_tail +add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test2/uut/empty_payload_list_head +add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test2/uut/oldest_sample +add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test2/uut/newest_sample +add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test2/uut/inst_empty_head +add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test2/uut/inst_occupied_head +add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test2/uut/cur_sample +add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test2/uut/prev_sample +add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test2/uut/next_sample +add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test2/uut/cur_payload +add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test2/uut/next_payload +add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test2/uut/cur_inst +add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test2/uut/next_inst +add wave -noupdate -divider MISC +add wave -noupdate /l0_dds_writer_test2/uut/ack_wait +add wave -noupdate /l0_dds_writer_test2/uut/ack_wait_check +add wave -noupdate -radix unsigned /l0_dds_writer_test2/uut/timeout_time +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {158543351 ps} 0} +quietly wave cursor active 1 +configure wave -namecolwidth 187 +configure wave -valuecolwidth 100 +configure wave -justifyvalue left +configure wave -signalnamewidth 1 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ns +update +WaveRestoreZoom {157882360 ps} {158883001 ps} diff --git a/sim/L0_dds_writer_test2_aik.do b/sim/L0_dds_writer_test2_aik.do deleted file mode 100644 index 7e22aa0..0000000 --- a/sim/L0_dds_writer_test2_aik.do +++ /dev/null @@ -1,151 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -divider SYSTEM -add wave -noupdate /l0_dds_writer_test2_aik/uut/clk -add wave -noupdate /l0_dds_writer_test2_aik/uut/reset -add wave -noupdate -radix unsigned /l0_dds_writer_test2_aik/uut/time -add wave -noupdate -radix unsigned /l0_dds_writer_test2_aik/uut/max_wait_dds -add wave -noupdate -divider {RTPS IN} -add wave -noupdate -group {RTPS IN} /l0_dds_writer_test2_aik/uut/start_rtps -add wave -noupdate -group {RTPS IN} -radix unsigned /l0_dds_writer_test2_aik/uut/seq_nr_rtps -add wave -noupdate -group {RTPS IN} /l0_dds_writer_test2_aik/uut/opcode_rtps -add wave -noupdate -group {RTPS IN} /l0_dds_writer_test2_aik/uut/ack_rtps -add wave -noupdate -group {RTPS IN} /l0_dds_writer_test2_aik/uut/done_rtps -add wave -noupdate -group {RTPS IN} /l0_dds_writer_test2_aik/uut/ret_rtps -add wave -noupdate -divider {RTPS OUT} -add wave -noupdate -group {RTPS OUT} -radix hexadecimal /l0_dds_writer_test2_aik/uut/cc_instance_handle -add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test2_aik/uut/cc_kind -add wave -noupdate -group {RTPS OUT} -radix unsigned /l0_dds_writer_test2_aik/uut/cc_source_timestamp -add wave -noupdate -group {RTPS OUT} -radix unsigned -childformat {{/l0_dds_writer_test2_aik/uut/cc_seq_nr(0) -radix unsigned -childformat {{/l0_dds_writer_test2_aik/uut/cc_seq_nr(0)(31) -radix unsigned} {/l0_dds_writer_test2_aik/uut/cc_seq_nr(0)(30) -radix unsigned} {/l0_dds_writer_test2_aik/uut/cc_seq_nr(0)(29) -radix unsigned} {/l0_dds_writer_test2_aik/uut/cc_seq_nr(0)(28) -radix unsigned} {/l0_dds_writer_test2_aik/uut/cc_seq_nr(0)(27) -radix unsigned} {/l0_dds_writer_test2_aik/uut/cc_seq_nr(0)(26) -radix unsigned} {/l0_dds_writer_test2_aik/uut/cc_seq_nr(0)(25) -radix unsigned} {/l0_dds_writer_test2_aik/uut/cc_seq_nr(0)(24) -radix unsigned} {/l0_dds_writer_test2_aik/uut/cc_seq_nr(0)(23) -radix unsigned} {/l0_dds_writer_test2_aik/uut/cc_seq_nr(0)(22) -radix unsigned} {/l0_dds_writer_test2_aik/uut/cc_seq_nr(0)(21) -radix unsigned} {/l0_dds_writer_test2_aik/uut/cc_seq_nr(0)(20) -radix unsigned} {/l0_dds_writer_test2_aik/uut/cc_seq_nr(0)(19) -radix unsigned} {/l0_dds_writer_test2_aik/uut/cc_seq_nr(0)(18) -radix unsigned} {/l0_dds_writer_test2_aik/uut/cc_seq_nr(0)(17) -radix unsigned} {/l0_dds_writer_test2_aik/uut/cc_seq_nr(0)(16) -radix unsigned} {/l0_dds_writer_test2_aik/uut/cc_seq_nr(0)(15) -radix unsigned} {/l0_dds_writer_test2_aik/uut/cc_seq_nr(0)(14) -radix unsigned} {/l0_dds_writer_test2_aik/uut/cc_seq_nr(0)(13) -radix unsigned} {/l0_dds_writer_test2_aik/uut/cc_seq_nr(0)(12) -radix unsigned} {/l0_dds_writer_test2_aik/uut/cc_seq_nr(0)(11) -radix unsigned} {/l0_dds_writer_test2_aik/uut/cc_seq_nr(0)(10) -radix unsigned} {/l0_dds_writer_test2_aik/uut/cc_seq_nr(0)(9) -radix unsigned} {/l0_dds_writer_test2_aik/uut/cc_seq_nr(0)(8) -radix unsigned} {/l0_dds_writer_test2_aik/uut/cc_seq_nr(0)(7) -radix unsigned} {/l0_dds_writer_test2_aik/uut/cc_seq_nr(0)(6) -radix unsigned} {/l0_dds_writer_test2_aik/uut/cc_seq_nr(0)(5) -radix unsigned} {/l0_dds_writer_test2_aik/uut/cc_seq_nr(0)(4) -radix unsigned} {/l0_dds_writer_test2_aik/uut/cc_seq_nr(0)(3) -radix unsigned} {/l0_dds_writer_test2_aik/uut/cc_seq_nr(0)(2) -radix unsigned} {/l0_dds_writer_test2_aik/uut/cc_seq_nr(0)(1) -radix unsigned} {/l0_dds_writer_test2_aik/uut/cc_seq_nr(0)(0) -radix unsigned}}} {/l0_dds_writer_test2_aik/uut/cc_seq_nr(1) -radix unsigned}} -subitemconfig {/l0_dds_writer_test2_aik/uut/cc_seq_nr(0) {-height 15 -radix unsigned -childformat {{/l0_dds_writer_test2_aik/uut/cc_seq_nr(0)(31) -radix unsigned} {/l0_dds_writer_test2_aik/uut/cc_seq_nr(0)(30) -radix unsigned} {/l0_dds_writer_test2_aik/uut/cc_seq_nr(0)(29) -radix unsigned} {/l0_dds_writer_test2_aik/uut/cc_seq_nr(0)(28) -radix unsigned} {/l0_dds_writer_test2_aik/uut/cc_seq_nr(0)(27) -radix unsigned} {/l0_dds_writer_test2_aik/uut/cc_seq_nr(0)(26) -radix unsigned} {/l0_dds_writer_test2_aik/uut/cc_seq_nr(0)(25) -radix unsigned} {/l0_dds_writer_test2_aik/uut/cc_seq_nr(0)(24) -radix unsigned} {/l0_dds_writer_test2_aik/uut/cc_seq_nr(0)(23) -radix unsigned} {/l0_dds_writer_test2_aik/uut/cc_seq_nr(0)(22) -radix unsigned} {/l0_dds_writer_test2_aik/uut/cc_seq_nr(0)(21) -radix unsigned} {/l0_dds_writer_test2_aik/uut/cc_seq_nr(0)(20) -radix unsigned} {/l0_dds_writer_test2_aik/uut/cc_seq_nr(0)(19) -radix unsigned} {/l0_dds_writer_test2_aik/uut/cc_seq_nr(0)(18) -radix unsigned} {/l0_dds_writer_test2_aik/uut/cc_seq_nr(0)(17) -radix unsigned} {/l0_dds_writer_test2_aik/uut/cc_seq_nr(0)(16) -radix unsigned} {/l0_dds_writer_test2_aik/uut/cc_seq_nr(0)(15) -radix unsigned} {/l0_dds_writer_test2_aik/uut/cc_seq_nr(0)(14) -radix unsigned} {/l0_dds_writer_test2_aik/uut/cc_seq_nr(0)(13) -radix unsigned} {/l0_dds_writer_test2_aik/uut/cc_seq_nr(0)(12) -radix unsigned} {/l0_dds_writer_test2_aik/uut/cc_seq_nr(0)(11) -radix unsigned} {/l0_dds_writer_test2_aik/uut/cc_seq_nr(0)(10) -radix unsigned} {/l0_dds_writer_test2_aik/uut/cc_seq_nr(0)(9) -radix unsigned} {/l0_dds_writer_test2_aik/uut/cc_seq_nr(0)(8) -radix unsigned} {/l0_dds_writer_test2_aik/uut/cc_seq_nr(0)(7) -radix unsigned} {/l0_dds_writer_test2_aik/uut/cc_seq_nr(0)(6) -radix unsigned} {/l0_dds_writer_test2_aik/uut/cc_seq_nr(0)(5) -radix unsigned} {/l0_dds_writer_test2_aik/uut/cc_seq_nr(0)(4) -radix unsigned} {/l0_dds_writer_test2_aik/uut/cc_seq_nr(0)(3) -radix unsigned} {/l0_dds_writer_test2_aik/uut/cc_seq_nr(0)(2) -radix unsigned} {/l0_dds_writer_test2_aik/uut/cc_seq_nr(0)(1) -radix unsigned} {/l0_dds_writer_test2_aik/uut/cc_seq_nr(0)(0) -radix unsigned}}} /l0_dds_writer_test2_aik/uut/cc_seq_nr(0)(31) {-height 15 -radix unsigned} /l0_dds_writer_test2_aik/uut/cc_seq_nr(0)(30) {-height 15 -radix unsigned} /l0_dds_writer_test2_aik/uut/cc_seq_nr(0)(29) {-height 15 -radix unsigned} /l0_dds_writer_test2_aik/uut/cc_seq_nr(0)(28) {-height 15 -radix unsigned} /l0_dds_writer_test2_aik/uut/cc_seq_nr(0)(27) {-height 15 -radix unsigned} /l0_dds_writer_test2_aik/uut/cc_seq_nr(0)(26) {-height 15 -radix unsigned} /l0_dds_writer_test2_aik/uut/cc_seq_nr(0)(25) {-height 15 -radix unsigned} /l0_dds_writer_test2_aik/uut/cc_seq_nr(0)(24) {-height 15 -radix unsigned} /l0_dds_writer_test2_aik/uut/cc_seq_nr(0)(23) {-height 15 -radix unsigned} /l0_dds_writer_test2_aik/uut/cc_seq_nr(0)(22) {-height 15 -radix unsigned} /l0_dds_writer_test2_aik/uut/cc_seq_nr(0)(21) {-height 15 -radix unsigned} /l0_dds_writer_test2_aik/uut/cc_seq_nr(0)(20) {-height 15 -radix unsigned} /l0_dds_writer_test2_aik/uut/cc_seq_nr(0)(19) {-height 15 -radix unsigned} /l0_dds_writer_test2_aik/uut/cc_seq_nr(0)(18) {-height 15 -radix unsigned} /l0_dds_writer_test2_aik/uut/cc_seq_nr(0)(17) {-height 15 -radix unsigned} /l0_dds_writer_test2_aik/uut/cc_seq_nr(0)(16) {-height 15 -radix unsigned} /l0_dds_writer_test2_aik/uut/cc_seq_nr(0)(15) {-height 15 -radix unsigned} /l0_dds_writer_test2_aik/uut/cc_seq_nr(0)(14) {-height 15 -radix unsigned} /l0_dds_writer_test2_aik/uut/cc_seq_nr(0)(13) {-height 15 -radix unsigned} /l0_dds_writer_test2_aik/uut/cc_seq_nr(0)(12) {-height 15 -radix unsigned} /l0_dds_writer_test2_aik/uut/cc_seq_nr(0)(11) {-height 15 -radix unsigned} /l0_dds_writer_test2_aik/uut/cc_seq_nr(0)(10) {-height 15 -radix unsigned} /l0_dds_writer_test2_aik/uut/cc_seq_nr(0)(9) {-height 15 -radix unsigned} /l0_dds_writer_test2_aik/uut/cc_seq_nr(0)(8) {-height 15 -radix unsigned} /l0_dds_writer_test2_aik/uut/cc_seq_nr(0)(7) {-height 15 -radix unsigned} /l0_dds_writer_test2_aik/uut/cc_seq_nr(0)(6) {-height 15 -radix unsigned} /l0_dds_writer_test2_aik/uut/cc_seq_nr(0)(5) {-height 15 -radix unsigned} /l0_dds_writer_test2_aik/uut/cc_seq_nr(0)(4) {-height 15 -radix unsigned} /l0_dds_writer_test2_aik/uut/cc_seq_nr(0)(3) {-height 15 -radix unsigned} /l0_dds_writer_test2_aik/uut/cc_seq_nr(0)(2) {-height 15 -radix unsigned} /l0_dds_writer_test2_aik/uut/cc_seq_nr(0)(1) {-height 15 -radix unsigned} /l0_dds_writer_test2_aik/uut/cc_seq_nr(0)(0) {-height 15 -radix unsigned} /l0_dds_writer_test2_aik/uut/cc_seq_nr(1) {-height 15 -radix unsigned}} /l0_dds_writer_test2_aik/uut/cc_seq_nr -add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test2_aik/uut/get_data_rtps -add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test2_aik/uut/ready_out_rtps -add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test2_aik/uut/valid_out_rtps -add wave -noupdate -group {RTPS OUT} -radix hexadecimal /l0_dds_writer_test2_aik/uut/data_out_rtps -add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test2_aik/uut/last_word_out_rtps -add wave -noupdate -divider {DDS IN} -add wave -noupdate -expand -group DDS /l0_dds_writer_test2_aik/uut/start_dds -add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_writer_test2_aik/uut/instance_handle_dds -add wave -noupdate -expand -group DDS -radix unsigned /l0_dds_writer_test2_aik/uut/source_ts_dds -add wave -noupdate -expand -group DDS /l0_dds_writer_test2_aik/uut/opcode_dds -add wave -noupdate -expand -group DDS /l0_dds_writer_test2_aik/uut/ack_dds -add wave -noupdate -expand -group DDS /l0_dds_writer_test2_aik/uut/done_dds -add wave -noupdate -expand -group DDS -radix unsigned /l0_dds_writer_test2_aik/uut/return_code_dds -add wave -noupdate -expand -group DDS /l0_dds_writer_test2_aik/uut/ready_in_dds -add wave -noupdate -expand -group DDS /l0_dds_writer_test2_aik/uut/valid_in_dds -add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_writer_test2_aik/uut/data_in_dds -add wave -noupdate -expand -group DDS /l0_dds_writer_test2_aik/uut/last_word_in_dds -add wave -noupdate -expand -group DDS /l0_dds_writer_test2_aik/uut/ready_out_dds -add wave -noupdate -expand -group DDS /l0_dds_writer_test2_aik/uut/valid_out_dds -add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_writer_test2_aik/uut/data_out_dds -add wave -noupdate -expand -group DDS /l0_dds_writer_test2_aik/uut/last_word_out_dds -add wave -noupdate -divider {MAIN FSM} -add wave -noupdate /l0_dds_writer_test2_aik/uut/stage -add wave -noupdate /l0_dds_writer_test2_aik/uut/stage_next -add wave -noupdate /l0_dds_writer_test2_aik/uut/cnt -add wave -noupdate -radix unsigned /l0_dds_writer_test2_aik/uut/global_seq_nr -add wave -noupdate -radix unsigned /l0_dds_writer_test2_aik/uut/global_sample_cnt -add wave -noupdate -radix unsigned /l0_dds_writer_test2_aik/uut/global_ack_cnt -add wave -noupdate -radix unsigned /l0_dds_writer_test2_aik/uut/stale_inst_cnt -add wave -noupdate /l0_dds_writer_test2_aik/uut/remove_oldest_inst_sample -add wave -noupdate /l0_dds_writer_test2_aik/uut/remove_oldest_sample -add wave -noupdate /l0_dds_writer_test2_aik/uut/remove_ack_sample -add wave -noupdate -divider MEMORY -add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test2_aik/uut/sample_abort_read -add wave -noupdate -group {SAMPLE MEM} -radix unsigned -childformat {{/l0_dds_writer_test2_aik/uut/sample_mem_ctrl_inst/addr(5) -radix unsigned} {/l0_dds_writer_test2_aik/uut/sample_mem_ctrl_inst/addr(4) -radix unsigned} {/l0_dds_writer_test2_aik/uut/sample_mem_ctrl_inst/addr(3) -radix unsigned} {/l0_dds_writer_test2_aik/uut/sample_mem_ctrl_inst/addr(2) -radix unsigned} {/l0_dds_writer_test2_aik/uut/sample_mem_ctrl_inst/addr(1) -radix unsigned} {/l0_dds_writer_test2_aik/uut/sample_mem_ctrl_inst/addr(0) -radix unsigned}} -subitemconfig {/l0_dds_writer_test2_aik/uut/sample_mem_ctrl_inst/addr(5) {-height 15 -radix unsigned} /l0_dds_writer_test2_aik/uut/sample_mem_ctrl_inst/addr(4) {-height 15 -radix unsigned} /l0_dds_writer_test2_aik/uut/sample_mem_ctrl_inst/addr(3) {-height 15 -radix unsigned} /l0_dds_writer_test2_aik/uut/sample_mem_ctrl_inst/addr(2) {-height 15 -radix unsigned} /l0_dds_writer_test2_aik/uut/sample_mem_ctrl_inst/addr(1) {-height 15 -radix unsigned} /l0_dds_writer_test2_aik/uut/sample_mem_ctrl_inst/addr(0) {-height 15 -radix unsigned}} /l0_dds_writer_test2_aik/uut/sample_mem_ctrl_inst/addr -add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test2_aik/uut/sample_mem_ctrl_inst/read -add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test2_aik/uut/sample_mem_ctrl_inst/ready_in -add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test2_aik/uut/sample_mem_ctrl_inst/valid_in -add wave -noupdate -group {SAMPLE MEM} -radix hexadecimal /l0_dds_writer_test2_aik/uut/sample_mem_ctrl_inst/data_in -add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test2_aik/uut/sample_mem_ctrl_inst/ready_out -add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test2_aik/uut/sample_mem_ctrl_inst/valid_out -add wave -noupdate -group {SAMPLE MEM} -radix hexadecimal /l0_dds_writer_test2_aik/uut/sample_mem_ctrl_inst/data_out -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test2_aik/uut/payload_abort_read -add wave -noupdate -group {PAYLOAD MEM} -radix unsigned /l0_dds_writer_test2_aik/uut/payload_mem_ctrl_inst/addr -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test2_aik/uut/payload_mem_ctrl_inst/read -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test2_aik/uut/payload_mem_ctrl_inst/ready_in -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test2_aik/uut/payload_mem_ctrl_inst/valid_in -add wave -noupdate -group {PAYLOAD MEM} -radix hexadecimal /l0_dds_writer_test2_aik/uut/payload_mem_ctrl_inst/data_in -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test2_aik/uut/payload_mem_ctrl_inst/ready_out -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test2_aik/uut/payload_mem_ctrl_inst/valid_out -add wave -noupdate -group {PAYLOAD MEM} -radix hexadecimal /l0_dds_writer_test2_aik/uut/payload_mem_ctrl_inst/data_out -add wave -noupdate /l0_dds_writer_test2_aik/uut/inst_op_start -add wave -noupdate /l0_dds_writer_test2_aik/uut/inst_opcode -add wave -noupdate /l0_dds_writer_test2_aik/uut/inst_op_done -add wave -noupdate /l0_dds_writer_test2_aik/uut/inst_stage -add wave -noupdate /l0_dds_writer_test2_aik/uut/inst_stage_next -add wave -noupdate /l0_dds_writer_test2_aik/uut/inst_cnt -add wave -noupdate -radix unsigned /l0_dds_writer_test2_aik/uut/inst_addr_base -add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test2_aik/uut/inst_abort_read -add wave -noupdate -group {INSTANCE MEM} -radix unsigned /l0_dds_writer_test2_aik/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/addr -add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test2_aik/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/read -add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test2_aik/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/ready_in -add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test2_aik/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/valid_in -add wave -noupdate -group {INSTANCE MEM} -radix hexadecimal /l0_dds_writer_test2_aik/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/data_in -add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test2_aik/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/ready_out -add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test2_aik/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/valid_out -add wave -noupdate -group {INSTANCE MEM} -radix hexadecimal /l0_dds_writer_test2_aik/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/data_out -add wave -noupdate -childformat {{/l0_dds_writer_test2_aik/uut/inst_data.key_hash -radix hexadecimal} {/l0_dds_writer_test2_aik/uut/inst_data.status_info -radix binary} {/l0_dds_writer_test2_aik/uut/inst_data.sample_cnt -radix unsigned} {/l0_dds_writer_test2_aik/uut/inst_data.ack_cnt -radix unsigned}} -expand -subitemconfig {/l0_dds_writer_test2_aik/uut/inst_data.key_hash {-height 15 -radix hexadecimal} /l0_dds_writer_test2_aik/uut/inst_data.status_info {-height 15 -radix binary} /l0_dds_writer_test2_aik/uut/inst_data.sample_cnt {-height 15 -radix unsigned} /l0_dds_writer_test2_aik/uut/inst_data.ack_cnt {-height 15 -radix unsigned}} /l0_dds_writer_test2_aik/uut/inst_data -add wave -noupdate -radix unsigned /l0_dds_writer_test2_aik/uut/inst_next_addr_base -add wave -noupdate -radix unsigned /l0_dds_writer_test2_aik/uut/inst_prev_addr_base -add wave -noupdate -divider {KEY HOLDER} -add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test2_aik/uut/start_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test2_aik/uut/opcode_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test2_aik/uut/ack_kh -add wave -noupdate -group {KEY HOLDER} -radix hexadecimal /l0_dds_writer_test2_aik/uut/data_in_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test2_aik/uut/valid_in_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test2_aik/uut/ready_in_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test2_aik/uut/last_word_in_kh -add wave -noupdate -group {KEY HOLDER} -radix hexadecimal /l0_dds_writer_test2_aik/uut/data_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test2_aik/uut/valid_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test2_aik/uut/ready_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test2_aik/uut/last_word_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test2_aik/uut/abort_kh -add wave -noupdate -divider POINTERS -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test2_aik/uut/empty_sample_list_head -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test2_aik/uut/empty_sample_list_tail -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test2_aik/uut/empty_payload_list_head -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test2_aik/uut/oldest_sample -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test2_aik/uut/newest_sample -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test2_aik/uut/inst_empty_head -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test2_aik/uut/inst_occupied_head -add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test2_aik/uut/cur_sample -add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test2_aik/uut/prev_sample -add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test2_aik/uut/next_sample -add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test2_aik/uut/cur_payload -add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test2_aik/uut/next_payload -add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test2_aik/uut/cur_inst -add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test2_aik/uut/next_inst -add wave -noupdate -divider TESTBENCH -add wave -noupdate -group TESTBENCH /l0_dds_writer_test2_aik/stim_start -add wave -noupdate -group TESTBENCH /l0_dds_writer_test2_aik/stim_stage -add wave -noupdate -group TESTBENCH /l0_dds_writer_test2_aik/stim_cnt -add wave -noupdate -group TESTBENCH /l0_dds_writer_test2_aik/stim_done -add wave -noupdate -group TESTBENCH /l0_dds_writer_test2_aik/ref_start -add wave -noupdate -group TESTBENCH /l0_dds_writer_test2_aik/ref_stage -add wave -noupdate -group TESTBENCH /l0_dds_writer_test2_aik/ref_cnt -add wave -noupdate -group TESTBENCH /l0_dds_writer_test2_aik/ref_done -add wave -noupdate -group TESTBENCH /l0_dds_writer_test2_aik/kh_cnt -add wave -noupdate -group TESTBENCH /l0_dds_writer_test2_aik/kh_stage -add wave -noupdate -divider MISC -add wave -noupdate /l0_dds_writer_test2_aik/uut/cnt2 -add wave -noupdate /l0_dds_writer_test2_aik/uut/cnt3 -add wave -noupdate -radix unsigned /l0_dds_writer_test2_aik/uut/long_latch -add wave -noupdate /l0_dds_writer_test2_aik/uut/sample_status_info -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {106575000 ps} 0} -quietly wave cursor active 1 -configure wave -namecolwidth 187 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -configure wave -timelineunits ns -update -WaveRestoreZoom {8424391 ps} {9425032 ps} diff --git a/sim/L0_dds_writer_test3.do b/sim/L0_dds_writer_test3.do new file mode 100644 index 0000000..4183abe --- /dev/null +++ b/sim/L0_dds_writer_test3.do @@ -0,0 +1,154 @@ +onerror {resume} +radix define DDS_RETCODE { + "10#0#" "RETCODE_OK", + "10#1#" "RETCODE_ERROR", + "10#2#" "RETCODE_UNSUPPORTED", + "10#3#" "RETCODE_BAD_PARAMETER", + "10#4#" "RETCODE_PRECONDITION_NOT_MET", + "10#5#" "RETCODE_OUT_OF_RESOURCES", + "10#6#" "RETCODE_NOT_ENABLED", + "10#7#" "RETCODE_IMMUTABLE_POLICY", + "10#8#" "RETCODE_INCONSISTENT_POLICY", + "10#9#" "RETCODE_ALREADY_DELETED", + "10#10#" "RETCODE_TIMEOUT", + "10#11#" "RETCODE_NO_DATA", + "10#12#" "RETCODE_ILLEGAL_OPERATION", + -default unsigned +} +quietly WaveActivateNextPane {} 0 +add wave -noupdate -divider SYSTEM +add wave -noupdate /l0_dds_writer_test3/uut/clk +add wave -noupdate /l0_dds_writer_test3/uut/reset +add wave -noupdate -radix unsigned /l0_dds_writer_test3/uut/time +add wave -noupdate -divider {RTPS IN} +add wave -noupdate -group {RTPS IN} /l0_dds_writer_test3/uut/start_rtps +add wave -noupdate -group {RTPS IN} -radix unsigned /l0_dds_writer_test3/uut/seq_nr_rtps +add wave -noupdate -group {RTPS IN} /l0_dds_writer_test3/uut/opcode_rtps +add wave -noupdate -group {RTPS IN} /l0_dds_writer_test3/uut/ack_rtps +add wave -noupdate -group {RTPS IN} /l0_dds_writer_test3/uut/done_rtps +add wave -noupdate -group {RTPS IN} /l0_dds_writer_test3/uut/ret_rtps +add wave -noupdate -divider {RTPS OUT} +add wave -noupdate -group {RTPS OUT} -radix hexadecimal /l0_dds_writer_test3/uut/cc_instance_handle +add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test3/uut/cc_kind +add wave -noupdate -group {RTPS OUT} -radix unsigned /l0_dds_writer_test3/uut/cc_source_timestamp +add wave -noupdate -group {RTPS OUT} -radix unsigned -childformat {{/l0_dds_writer_test3/uut/cc_seq_nr(0) -radix unsigned -childformat {{/l0_dds_writer_test3/uut/cc_seq_nr(0)(0) -radix unsigned} {/l0_dds_writer_test3/uut/cc_seq_nr(0)(1) -radix unsigned}}} {/l0_dds_writer_test3/uut/cc_seq_nr(1) -radix unsigned} {/l0_dds_writer_test3/uut/cc_seq_nr(2) -radix unsigned} {/l0_dds_writer_test3/uut/cc_seq_nr(3) -radix unsigned}} -subitemconfig {/l0_dds_writer_test3/uut/cc_seq_nr(0) {-height 15 -radix unsigned -childformat {{/l0_dds_writer_test3/uut/cc_seq_nr(0)(0) -radix unsigned} {/l0_dds_writer_test3/uut/cc_seq_nr(0)(1) -radix unsigned}}} /l0_dds_writer_test3/uut/cc_seq_nr(0)(0) {-height 15 -radix unsigned} /l0_dds_writer_test3/uut/cc_seq_nr(0)(1) {-height 15 -radix unsigned} /l0_dds_writer_test3/uut/cc_seq_nr(1) {-height 15 -radix unsigned} /l0_dds_writer_test3/uut/cc_seq_nr(2) {-height 15 -radix unsigned} /l0_dds_writer_test3/uut/cc_seq_nr(3) {-height 15 -radix unsigned}} /l0_dds_writer_test3/uut/cc_seq_nr +add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test3/uut/get_data_rtps +add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test3/uut/ready_out_rtps +add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test3/uut/valid_out_rtps +add wave -noupdate -group {RTPS OUT} -radix hexadecimal /l0_dds_writer_test3/uut/data_out_rtps +add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test3/uut/last_word_out_rtps +add wave -noupdate -divider {DDS IN} +add wave -noupdate -expand -group DDS /l0_dds_writer_test3/uut/start_dds +add wave -noupdate -expand -group DDS -radix unsigned /l0_dds_writer_test3/uut/source_ts_dds +add wave -noupdate -expand -group DDS /l0_dds_writer_test3/uut/opcode_dds +add wave -noupdate -expand -group DDS /l0_dds_writer_test3/uut/ack_dds +add wave -noupdate -expand -group DDS /l0_dds_writer_test3/uut/done_dds +add wave -noupdate -expand -group DDS -radix unsigned -childformat {{/l0_dds_writer_test3/uut/return_code_dds(0) -radix DDS_RETCODE} {/l0_dds_writer_test3/uut/return_code_dds(1) -radix DDS_RETCODE} {/l0_dds_writer_test3/uut/return_code_dds(2) -radix DDS_RETCODE} {/l0_dds_writer_test3/uut/return_code_dds(3) -radix DDS_RETCODE}} -subitemconfig {/l0_dds_writer_test3/uut/return_code_dds(0) {-height 15 -radix DDS_RETCODE} /l0_dds_writer_test3/uut/return_code_dds(1) {-height 15 -radix DDS_RETCODE} /l0_dds_writer_test3/uut/return_code_dds(2) {-height 15 -radix DDS_RETCODE} /l0_dds_writer_test3/uut/return_code_dds(3) {-height 15 -radix DDS_RETCODE}} /l0_dds_writer_test3/uut/return_code_dds +add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_writer_test3/uut/instance_handle_in_dds +add wave -noupdate -expand -group DDS /l0_dds_writer_test3/uut/ready_in_dds +add wave -noupdate -expand -group DDS /l0_dds_writer_test3/uut/valid_in_dds +add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_writer_test3/uut/data_in_dds +add wave -noupdate -expand -group DDS /l0_dds_writer_test3/uut/last_word_in_dds +add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_writer_test3/uut/instance_handle_out_dds +add wave -noupdate -expand -group DDS /l0_dds_writer_test3/uut/ready_out_dds +add wave -noupdate -expand -group DDS /l0_dds_writer_test3/uut/valid_out_dds +add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_writer_test3/uut/data_out_dds +add wave -noupdate -expand -group DDS /l0_dds_writer_test3/uut/last_word_out_dds +add wave -noupdate -divider {MAIN FSM} +add wave -noupdate /l0_dds_writer_test3/uut/stage +add wave -noupdate /l0_dds_writer_test3/uut/cnt +add wave -noupdate /l0_dds_writer_test3/uut/ind +add wave -noupdate -radix unsigned /l0_dds_writer_test3/uut/global_seq_nr +add wave -noupdate -radix unsigned /l0_dds_writer_test3/uut/global_sample_cnt +add wave -noupdate -radix unsigned /l0_dds_writer_test3/uut/global_ack_cnt +add wave -noupdate -radix unsigned /l0_dds_writer_test3/uut/stale_inst_cnt +add wave -noupdate /l0_dds_writer_test3/uut/remove_oldest_inst_sample +add wave -noupdate /l0_dds_writer_test3/uut/remove_oldest_sample +add wave -noupdate /l0_dds_writer_test3/uut/remove_ack_sample +add wave -noupdate -divider MEMORY +add wave -noupdate -group {SAMPLE MEM} -radix unsigned /l0_dds_writer_test3/uut/sample_addr +add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test3/uut/sample_read +add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test3/uut/sample_ready_in +add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test3/uut/sample_valid_in +add wave -noupdate -group {SAMPLE MEM} -radix hexadecimal /l0_dds_writer_test3/uut/sample_write_data +add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test3/uut/sample_ready_out +add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test3/uut/sample_valid_out +add wave -noupdate -group {SAMPLE MEM} -radix hexadecimal /l0_dds_writer_test3/uut/sample_read_data +add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test3/uut/sample_abort_read +add wave -noupdate -group {PAYLOAD MEM} -radix unsigned /l0_dds_writer_test3/uut/payload_addr +add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test3/uut/payload_read +add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test3/uut/payload_ready_in +add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test3/uut/payload_valid_in +add wave -noupdate -group {PAYLOAD MEM} -radix hexadecimal /l0_dds_writer_test3/uut/payload_write_data +add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test3/uut/payload_ready_out +add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test3/uut/payload_valid_out +add wave -noupdate -group {PAYLOAD MEM} -radix hexadecimal /l0_dds_writer_test3/uut/payload_read_data +add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test3/uut/payload_abort_read +add wave -noupdate /l0_dds_writer_test3/uut/inst_op_start +add wave -noupdate /l0_dds_writer_test3/uut/inst_opcode +add wave -noupdate /l0_dds_writer_test3/uut/inst_op_done +add wave -noupdate /l0_dds_writer_test3/uut/inst_stage +add wave -noupdate /l0_dds_writer_test3/uut/inst_cnt +add wave -noupdate -radix unsigned /l0_dds_writer_test3/uut/inst_addr_base +add wave -noupdate -group {INSTANCE MEM} -radix unsigned /l0_dds_writer_test3/uut/inst_addr +add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test3/uut/inst_read +add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test3/uut/inst_ready_in +add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test3/uut/inst_valid_in +add wave -noupdate -group {INSTANCE MEM} -radix hexadecimal /l0_dds_writer_test3/uut/inst_write_data +add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test3/uut/inst_ready_out +add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test3/uut/inst_valid_out +add wave -noupdate -group {INSTANCE MEM} -radix hexadecimal /l0_dds_writer_test3/uut/inst_read_data +add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test3/uut/inst_abort_read +add wave -noupdate -radix hexadecimal -childformat {{/l0_dds_writer_test3/uut/inst_data.i -radix hexadecimal} {/l0_dds_writer_test3/uut/inst_data.addr -radix unsigned} {/l0_dds_writer_test3/uut/inst_data.key_hash -radix hexadecimal} {/l0_dds_writer_test3/uut/inst_data.status_info -radix binary} {/l0_dds_writer_test3/uut/inst_data.sample_cnt -radix unsigned} {/l0_dds_writer_test3/uut/inst_data.ack_cnt -radix unsigned}} -subitemconfig {/l0_dds_writer_test3/uut/inst_data.i {-height 15 -radix hexadecimal} /l0_dds_writer_test3/uut/inst_data.addr {-height 15 -radix unsigned} /l0_dds_writer_test3/uut/inst_data.key_hash {-height 15 -radix hexadecimal} /l0_dds_writer_test3/uut/inst_data.status_info {-height 15 -radix binary} /l0_dds_writer_test3/uut/inst_data.sample_cnt {-height 15 -radix unsigned} /l0_dds_writer_test3/uut/inst_data.ack_cnt {-height 15 -radix unsigned} /l0_dds_writer_test3/uut/inst_data.field_flags {-height 15}} /l0_dds_writer_test3/uut/inst_data +add wave -noupdate -divider {KEY HOLDER} +add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test3/uut/start_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test3/uut/opcode_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test3/uut/ack_kh +add wave -noupdate -group {KEY HOLDER} -radix hexadecimal /l0_dds_writer_test3/uut/data_in_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test3/uut/valid_in_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test3/uut/ready_in_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test3/uut/last_word_in_kh +add wave -noupdate -group {KEY HOLDER} -radix hexadecimal /l0_dds_writer_test3/uut/data_out_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test3/uut/valid_out_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test3/uut/ready_out_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test3/uut/last_word_out_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test3/uut/abort_kh +add wave -noupdate -divider POINTERS +add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test3/uut/empty_sample_list_head +add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test3/uut/empty_sample_list_tail +add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test3/uut/empty_payload_list_head +add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test3/uut/oldest_sample +add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test3/uut/newest_sample +add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test3/uut/inst_empty_head +add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test3/uut/inst_occupied_head +add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test3/uut/cur_sample +add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test3/uut/prev_sample +add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test3/uut/next_sample +add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test3/uut/cur_payload +add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test3/uut/next_payload +add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test3/uut/cur_inst +add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test3/uut/next_inst +add wave -noupdate -divider TESTBENCH +add wave -noupdate -divider MISC +add wave -noupdate /l0_dds_writer_test3/uut/cnt2 +add wave -noupdate /l0_dds_writer_test3/uut/cnt3 +add wave -noupdate -radix unsigned /l0_dds_writer_test3/uut/long_latch +add wave -noupdate /l0_dds_writer_test3/uut/sample_status_info +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {158543351 ps} 0} +quietly wave cursor active 1 +configure wave -namecolwidth 187 +configure wave -valuecolwidth 100 +configure wave -justifyvalue left +configure wave -signalnamewidth 1 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ns +update +WaveRestoreZoom {157882360 ps} {158883001 ps} diff --git a/sim/L0_dds_writer_test3_aik.do b/sim/L0_dds_writer_test3_aik.do deleted file mode 100644 index 069aab9..0000000 --- a/sim/L0_dds_writer_test3_aik.do +++ /dev/null @@ -1,153 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -divider SYSTEM -add wave -noupdate /l0_dds_writer_test3_aik/uut/clk -add wave -noupdate /l0_dds_writer_test3_aik/uut/reset -add wave -noupdate -radix unsigned /l0_dds_writer_test3_aik/uut/time -add wave -noupdate -radix unsigned /l0_dds_writer_test3_aik/uut/deadline_time -add wave -noupdate -divider {RTPS IN} -add wave -noupdate -group {RTPS IN} /l0_dds_writer_test3_aik/uut/start_rtps -add wave -noupdate -group {RTPS IN} -radix unsigned /l0_dds_writer_test3_aik/uut/seq_nr_rtps -add wave -noupdate -group {RTPS IN} /l0_dds_writer_test3_aik/uut/opcode_rtps -add wave -noupdate -group {RTPS IN} /l0_dds_writer_test3_aik/uut/ack_rtps -add wave -noupdate -group {RTPS IN} /l0_dds_writer_test3_aik/uut/done_rtps -add wave -noupdate -group {RTPS IN} /l0_dds_writer_test3_aik/uut/ret_rtps -add wave -noupdate -divider {RTPS OUT} -add wave -noupdate -group {RTPS OUT} -radix hexadecimal /l0_dds_writer_test3_aik/uut/cc_instance_handle -add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test3_aik/uut/cc_kind -add wave -noupdate -group {RTPS OUT} -radix unsigned /l0_dds_writer_test3_aik/uut/cc_source_timestamp -add wave -noupdate -group {RTPS OUT} -radix unsigned -childformat {{/l0_dds_writer_test3_aik/uut/cc_seq_nr(0) -radix unsigned -childformat {{/l0_dds_writer_test3_aik/uut/cc_seq_nr(0)(31) -radix unsigned} {/l0_dds_writer_test3_aik/uut/cc_seq_nr(0)(30) -radix unsigned} {/l0_dds_writer_test3_aik/uut/cc_seq_nr(0)(29) -radix unsigned} {/l0_dds_writer_test3_aik/uut/cc_seq_nr(0)(28) -radix unsigned} {/l0_dds_writer_test3_aik/uut/cc_seq_nr(0)(27) -radix unsigned} {/l0_dds_writer_test3_aik/uut/cc_seq_nr(0)(26) -radix unsigned} {/l0_dds_writer_test3_aik/uut/cc_seq_nr(0)(25) -radix unsigned} {/l0_dds_writer_test3_aik/uut/cc_seq_nr(0)(24) -radix unsigned} {/l0_dds_writer_test3_aik/uut/cc_seq_nr(0)(23) -radix unsigned} {/l0_dds_writer_test3_aik/uut/cc_seq_nr(0)(22) -radix unsigned} {/l0_dds_writer_test3_aik/uut/cc_seq_nr(0)(21) -radix unsigned} {/l0_dds_writer_test3_aik/uut/cc_seq_nr(0)(20) -radix unsigned} {/l0_dds_writer_test3_aik/uut/cc_seq_nr(0)(19) -radix unsigned} {/l0_dds_writer_test3_aik/uut/cc_seq_nr(0)(18) -radix unsigned} {/l0_dds_writer_test3_aik/uut/cc_seq_nr(0)(17) -radix unsigned} {/l0_dds_writer_test3_aik/uut/cc_seq_nr(0)(16) -radix unsigned} {/l0_dds_writer_test3_aik/uut/cc_seq_nr(0)(15) -radix unsigned} {/l0_dds_writer_test3_aik/uut/cc_seq_nr(0)(14) -radix unsigned} {/l0_dds_writer_test3_aik/uut/cc_seq_nr(0)(13) -radix unsigned} {/l0_dds_writer_test3_aik/uut/cc_seq_nr(0)(12) -radix unsigned} {/l0_dds_writer_test3_aik/uut/cc_seq_nr(0)(11) -radix unsigned} {/l0_dds_writer_test3_aik/uut/cc_seq_nr(0)(10) -radix unsigned} {/l0_dds_writer_test3_aik/uut/cc_seq_nr(0)(9) -radix unsigned} {/l0_dds_writer_test3_aik/uut/cc_seq_nr(0)(8) -radix unsigned} {/l0_dds_writer_test3_aik/uut/cc_seq_nr(0)(7) -radix unsigned} {/l0_dds_writer_test3_aik/uut/cc_seq_nr(0)(6) -radix unsigned} {/l0_dds_writer_test3_aik/uut/cc_seq_nr(0)(5) -radix unsigned} {/l0_dds_writer_test3_aik/uut/cc_seq_nr(0)(4) -radix unsigned} {/l0_dds_writer_test3_aik/uut/cc_seq_nr(0)(3) -radix unsigned} {/l0_dds_writer_test3_aik/uut/cc_seq_nr(0)(2) -radix unsigned} {/l0_dds_writer_test3_aik/uut/cc_seq_nr(0)(1) -radix unsigned} {/l0_dds_writer_test3_aik/uut/cc_seq_nr(0)(0) -radix unsigned}}} {/l0_dds_writer_test3_aik/uut/cc_seq_nr(1) -radix unsigned}} -subitemconfig {/l0_dds_writer_test3_aik/uut/cc_seq_nr(0) {-height 15 -radix unsigned -childformat {{/l0_dds_writer_test3_aik/uut/cc_seq_nr(0)(31) -radix unsigned} {/l0_dds_writer_test3_aik/uut/cc_seq_nr(0)(30) -radix unsigned} {/l0_dds_writer_test3_aik/uut/cc_seq_nr(0)(29) -radix unsigned} {/l0_dds_writer_test3_aik/uut/cc_seq_nr(0)(28) -radix unsigned} {/l0_dds_writer_test3_aik/uut/cc_seq_nr(0)(27) -radix unsigned} {/l0_dds_writer_test3_aik/uut/cc_seq_nr(0)(26) -radix unsigned} {/l0_dds_writer_test3_aik/uut/cc_seq_nr(0)(25) -radix unsigned} {/l0_dds_writer_test3_aik/uut/cc_seq_nr(0)(24) -radix unsigned} {/l0_dds_writer_test3_aik/uut/cc_seq_nr(0)(23) -radix unsigned} {/l0_dds_writer_test3_aik/uut/cc_seq_nr(0)(22) -radix unsigned} {/l0_dds_writer_test3_aik/uut/cc_seq_nr(0)(21) -radix unsigned} {/l0_dds_writer_test3_aik/uut/cc_seq_nr(0)(20) -radix unsigned} {/l0_dds_writer_test3_aik/uut/cc_seq_nr(0)(19) -radix unsigned} {/l0_dds_writer_test3_aik/uut/cc_seq_nr(0)(18) -radix unsigned} {/l0_dds_writer_test3_aik/uut/cc_seq_nr(0)(17) -radix unsigned} {/l0_dds_writer_test3_aik/uut/cc_seq_nr(0)(16) -radix unsigned} {/l0_dds_writer_test3_aik/uut/cc_seq_nr(0)(15) -radix unsigned} {/l0_dds_writer_test3_aik/uut/cc_seq_nr(0)(14) -radix unsigned} {/l0_dds_writer_test3_aik/uut/cc_seq_nr(0)(13) -radix unsigned} {/l0_dds_writer_test3_aik/uut/cc_seq_nr(0)(12) -radix unsigned} {/l0_dds_writer_test3_aik/uut/cc_seq_nr(0)(11) -radix unsigned} {/l0_dds_writer_test3_aik/uut/cc_seq_nr(0)(10) -radix unsigned} {/l0_dds_writer_test3_aik/uut/cc_seq_nr(0)(9) -radix unsigned} {/l0_dds_writer_test3_aik/uut/cc_seq_nr(0)(8) -radix unsigned} {/l0_dds_writer_test3_aik/uut/cc_seq_nr(0)(7) -radix unsigned} {/l0_dds_writer_test3_aik/uut/cc_seq_nr(0)(6) -radix unsigned} {/l0_dds_writer_test3_aik/uut/cc_seq_nr(0)(5) -radix unsigned} {/l0_dds_writer_test3_aik/uut/cc_seq_nr(0)(4) -radix unsigned} {/l0_dds_writer_test3_aik/uut/cc_seq_nr(0)(3) -radix unsigned} {/l0_dds_writer_test3_aik/uut/cc_seq_nr(0)(2) -radix unsigned} {/l0_dds_writer_test3_aik/uut/cc_seq_nr(0)(1) -radix unsigned} {/l0_dds_writer_test3_aik/uut/cc_seq_nr(0)(0) -radix unsigned}}} /l0_dds_writer_test3_aik/uut/cc_seq_nr(0)(31) {-height 15 -radix unsigned} /l0_dds_writer_test3_aik/uut/cc_seq_nr(0)(30) {-height 15 -radix unsigned} /l0_dds_writer_test3_aik/uut/cc_seq_nr(0)(29) {-height 15 -radix unsigned} /l0_dds_writer_test3_aik/uut/cc_seq_nr(0)(28) {-height 15 -radix unsigned} /l0_dds_writer_test3_aik/uut/cc_seq_nr(0)(27) {-height 15 -radix unsigned} /l0_dds_writer_test3_aik/uut/cc_seq_nr(0)(26) {-height 15 -radix unsigned} /l0_dds_writer_test3_aik/uut/cc_seq_nr(0)(25) {-height 15 -radix unsigned} /l0_dds_writer_test3_aik/uut/cc_seq_nr(0)(24) {-height 15 -radix unsigned} /l0_dds_writer_test3_aik/uut/cc_seq_nr(0)(23) {-height 15 -radix unsigned} /l0_dds_writer_test3_aik/uut/cc_seq_nr(0)(22) {-height 15 -radix unsigned} /l0_dds_writer_test3_aik/uut/cc_seq_nr(0)(21) {-height 15 -radix unsigned} /l0_dds_writer_test3_aik/uut/cc_seq_nr(0)(20) {-height 15 -radix unsigned} /l0_dds_writer_test3_aik/uut/cc_seq_nr(0)(19) {-height 15 -radix unsigned} /l0_dds_writer_test3_aik/uut/cc_seq_nr(0)(18) {-height 15 -radix unsigned} /l0_dds_writer_test3_aik/uut/cc_seq_nr(0)(17) {-height 15 -radix unsigned} /l0_dds_writer_test3_aik/uut/cc_seq_nr(0)(16) {-height 15 -radix unsigned} /l0_dds_writer_test3_aik/uut/cc_seq_nr(0)(15) {-height 15 -radix unsigned} /l0_dds_writer_test3_aik/uut/cc_seq_nr(0)(14) {-height 15 -radix unsigned} /l0_dds_writer_test3_aik/uut/cc_seq_nr(0)(13) {-height 15 -radix unsigned} /l0_dds_writer_test3_aik/uut/cc_seq_nr(0)(12) {-height 15 -radix unsigned} /l0_dds_writer_test3_aik/uut/cc_seq_nr(0)(11) {-height 15 -radix unsigned} /l0_dds_writer_test3_aik/uut/cc_seq_nr(0)(10) {-height 15 -radix unsigned} /l0_dds_writer_test3_aik/uut/cc_seq_nr(0)(9) {-height 15 -radix unsigned} /l0_dds_writer_test3_aik/uut/cc_seq_nr(0)(8) {-height 15 -radix unsigned} /l0_dds_writer_test3_aik/uut/cc_seq_nr(0)(7) {-height 15 -radix unsigned} /l0_dds_writer_test3_aik/uut/cc_seq_nr(0)(6) {-height 15 -radix unsigned} /l0_dds_writer_test3_aik/uut/cc_seq_nr(0)(5) {-height 15 -radix unsigned} /l0_dds_writer_test3_aik/uut/cc_seq_nr(0)(4) {-height 15 -radix unsigned} /l0_dds_writer_test3_aik/uut/cc_seq_nr(0)(3) {-height 15 -radix unsigned} /l0_dds_writer_test3_aik/uut/cc_seq_nr(0)(2) {-height 15 -radix unsigned} /l0_dds_writer_test3_aik/uut/cc_seq_nr(0)(1) {-height 15 -radix unsigned} /l0_dds_writer_test3_aik/uut/cc_seq_nr(0)(0) {-height 15 -radix unsigned} /l0_dds_writer_test3_aik/uut/cc_seq_nr(1) {-height 15 -radix unsigned}} /l0_dds_writer_test3_aik/uut/cc_seq_nr -add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test3_aik/uut/get_data_rtps -add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test3_aik/uut/ready_out_rtps -add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test3_aik/uut/valid_out_rtps -add wave -noupdate -group {RTPS OUT} -radix hexadecimal /l0_dds_writer_test3_aik/uut/data_out_rtps -add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test3_aik/uut/last_word_out_rtps -add wave -noupdate -divider DDS -add wave -noupdate /l0_dds_writer_test3_aik/uut/status -add wave -noupdate -expand -group DDS /l0_dds_writer_test3_aik/uut/start_dds -add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_writer_test3_aik/uut/instance_handle_dds -add wave -noupdate -expand -group DDS -radix unsigned /l0_dds_writer_test3_aik/uut/source_ts_dds -add wave -noupdate -expand -group DDS /l0_dds_writer_test3_aik/uut/opcode_dds -add wave -noupdate -expand -group DDS /l0_dds_writer_test3_aik/uut/ack_dds -add wave -noupdate -expand -group DDS /l0_dds_writer_test3_aik/uut/done_dds -add wave -noupdate -expand -group DDS -radix unsigned /l0_dds_writer_test3_aik/uut/return_code_dds -add wave -noupdate -expand -group DDS /l0_dds_writer_test3_aik/uut/ready_in_dds -add wave -noupdate -expand -group DDS /l0_dds_writer_test3_aik/uut/valid_in_dds -add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_writer_test3_aik/uut/data_in_dds -add wave -noupdate -expand -group DDS /l0_dds_writer_test3_aik/uut/last_word_in_dds -add wave -noupdate -expand -group DDS /l0_dds_writer_test3_aik/uut/ready_out_dds -add wave -noupdate -expand -group DDS /l0_dds_writer_test3_aik/uut/valid_out_dds -add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_writer_test3_aik/uut/data_out_dds -add wave -noupdate -expand -group DDS /l0_dds_writer_test3_aik/uut/last_word_out_dds -add wave -noupdate -divider {MAIN FSM} -add wave -noupdate /l0_dds_writer_test3_aik/uut/idle_sig -add wave -noupdate /l0_dds_writer_test3_aik/uut/stage -add wave -noupdate /l0_dds_writer_test3_aik/uut/stage_next -add wave -noupdate /l0_dds_writer_test3_aik/uut/cnt -add wave -noupdate -radix unsigned /l0_dds_writer_test3_aik/uut/global_seq_nr -add wave -noupdate -radix unsigned /l0_dds_writer_test3_aik/uut/global_sample_cnt -add wave -noupdate -radix unsigned /l0_dds_writer_test3_aik/uut/global_ack_cnt -add wave -noupdate -radix unsigned /l0_dds_writer_test3_aik/uut/stale_inst_cnt -add wave -noupdate /l0_dds_writer_test3_aik/uut/remove_oldest_inst_sample -add wave -noupdate /l0_dds_writer_test3_aik/uut/remove_oldest_sample -add wave -noupdate /l0_dds_writer_test3_aik/uut/remove_ack_sample -add wave -noupdate -divider MEMORY -add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test3_aik/uut/sample_abort_read -add wave -noupdate -group {SAMPLE MEM} -radix unsigned -childformat {{/l0_dds_writer_test3_aik/uut/sample_mem_ctrl_inst/addr(5) -radix unsigned} {/l0_dds_writer_test3_aik/uut/sample_mem_ctrl_inst/addr(4) -radix unsigned} {/l0_dds_writer_test3_aik/uut/sample_mem_ctrl_inst/addr(3) -radix unsigned} {/l0_dds_writer_test3_aik/uut/sample_mem_ctrl_inst/addr(2) -radix unsigned} {/l0_dds_writer_test3_aik/uut/sample_mem_ctrl_inst/addr(1) -radix unsigned} {/l0_dds_writer_test3_aik/uut/sample_mem_ctrl_inst/addr(0) -radix unsigned}} -subitemconfig {/l0_dds_writer_test3_aik/uut/sample_mem_ctrl_inst/addr(5) {-height 15 -radix unsigned} /l0_dds_writer_test3_aik/uut/sample_mem_ctrl_inst/addr(4) {-height 15 -radix unsigned} /l0_dds_writer_test3_aik/uut/sample_mem_ctrl_inst/addr(3) {-height 15 -radix unsigned} /l0_dds_writer_test3_aik/uut/sample_mem_ctrl_inst/addr(2) {-height 15 -radix unsigned} /l0_dds_writer_test3_aik/uut/sample_mem_ctrl_inst/addr(1) {-height 15 -radix unsigned} /l0_dds_writer_test3_aik/uut/sample_mem_ctrl_inst/addr(0) {-height 15 -radix unsigned}} /l0_dds_writer_test3_aik/uut/sample_mem_ctrl_inst/addr -add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test3_aik/uut/sample_mem_ctrl_inst/read -add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test3_aik/uut/sample_mem_ctrl_inst/ready_in -add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test3_aik/uut/sample_mem_ctrl_inst/valid_in -add wave -noupdate -group {SAMPLE MEM} -radix hexadecimal /l0_dds_writer_test3_aik/uut/sample_mem_ctrl_inst/data_in -add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test3_aik/uut/sample_mem_ctrl_inst/ready_out -add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test3_aik/uut/sample_mem_ctrl_inst/valid_out -add wave -noupdate -group {SAMPLE MEM} -radix hexadecimal /l0_dds_writer_test3_aik/uut/sample_mem_ctrl_inst/data_out -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test3_aik/uut/payload_abort_read -add wave -noupdate -group {PAYLOAD MEM} -radix unsigned /l0_dds_writer_test3_aik/uut/payload_mem_ctrl_inst/addr -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test3_aik/uut/payload_mem_ctrl_inst/read -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test3_aik/uut/payload_mem_ctrl_inst/ready_in -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test3_aik/uut/payload_mem_ctrl_inst/valid_in -add wave -noupdate -group {PAYLOAD MEM} -radix hexadecimal /l0_dds_writer_test3_aik/uut/payload_mem_ctrl_inst/data_in -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test3_aik/uut/payload_mem_ctrl_inst/ready_out -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test3_aik/uut/payload_mem_ctrl_inst/valid_out -add wave -noupdate -group {PAYLOAD MEM} -radix hexadecimal /l0_dds_writer_test3_aik/uut/payload_mem_ctrl_inst/data_out -add wave -noupdate /l0_dds_writer_test3_aik/uut/inst_op_start -add wave -noupdate /l0_dds_writer_test3_aik/uut/inst_opcode -add wave -noupdate /l0_dds_writer_test3_aik/uut/inst_op_done -add wave -noupdate /l0_dds_writer_test3_aik/uut/inst_stage -add wave -noupdate /l0_dds_writer_test3_aik/uut/inst_stage_next -add wave -noupdate /l0_dds_writer_test3_aik/uut/inst_cnt -add wave -noupdate -radix unsigned /l0_dds_writer_test3_aik/uut/inst_addr_base -add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test3_aik/uut/inst_abort_read -add wave -noupdate -group {INSTANCE MEM} -radix unsigned /l0_dds_writer_test3_aik/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/addr -add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test3_aik/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/read -add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test3_aik/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/ready_in -add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test3_aik/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/valid_in -add wave -noupdate -group {INSTANCE MEM} -radix hexadecimal /l0_dds_writer_test3_aik/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/data_in -add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test3_aik/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/ready_out -add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test3_aik/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/valid_out -add wave -noupdate -group {INSTANCE MEM} -radix hexadecimal /l0_dds_writer_test3_aik/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/data_out -add wave -noupdate -childformat {{/l0_dds_writer_test3_aik/uut/inst_data.key_hash -radix hexadecimal} {/l0_dds_writer_test3_aik/uut/inst_data.status_info -radix binary} {/l0_dds_writer_test3_aik/uut/inst_data.sample_cnt -radix unsigned} {/l0_dds_writer_test3_aik/uut/inst_data.ack_cnt -radix unsigned}} -expand -subitemconfig {/l0_dds_writer_test3_aik/uut/inst_data.key_hash {-height 15 -radix hexadecimal} /l0_dds_writer_test3_aik/uut/inst_data.status_info {-height 15 -radix binary} /l0_dds_writer_test3_aik/uut/inst_data.sample_cnt {-height 15 -radix unsigned} /l0_dds_writer_test3_aik/uut/inst_data.ack_cnt {-height 15 -radix unsigned}} /l0_dds_writer_test3_aik/uut/inst_data -add wave -noupdate -radix unsigned /l0_dds_writer_test3_aik/uut/inst_next_addr_base -add wave -noupdate -radix unsigned /l0_dds_writer_test3_aik/uut/inst_prev_addr_base -add wave -noupdate -divider {KEY HOLDER} -add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test3_aik/uut/start_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test3_aik/uut/opcode_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test3_aik/uut/ack_kh -add wave -noupdate -group {KEY HOLDER} -radix hexadecimal /l0_dds_writer_test3_aik/uut/data_in_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test3_aik/uut/valid_in_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test3_aik/uut/ready_in_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test3_aik/uut/last_word_in_kh -add wave -noupdate -group {KEY HOLDER} -radix hexadecimal /l0_dds_writer_test3_aik/uut/data_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test3_aik/uut/valid_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test3_aik/uut/ready_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test3_aik/uut/last_word_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test3_aik/uut/abort_kh -add wave -noupdate -divider POINTERS -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test3_aik/uut/empty_sample_list_head -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test3_aik/uut/empty_sample_list_tail -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test3_aik/uut/empty_payload_list_head -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test3_aik/uut/oldest_sample -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test3_aik/uut/newest_sample -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test3_aik/uut/inst_empty_head -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test3_aik/uut/inst_occupied_head -add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test3_aik/uut/cur_sample -add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test3_aik/uut/prev_sample -add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test3_aik/uut/next_sample -add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test3_aik/uut/cur_payload -add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test3_aik/uut/next_payload -add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test3_aik/uut/cur_inst -add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test3_aik/uut/next_inst -add wave -noupdate -divider TESTBENCH -add wave -noupdate -group TESTBENCH /l0_dds_writer_test3_aik/stim_start -add wave -noupdate -group TESTBENCH /l0_dds_writer_test3_aik/stim_stage -add wave -noupdate -group TESTBENCH /l0_dds_writer_test3_aik/stim_cnt -add wave -noupdate -group TESTBENCH /l0_dds_writer_test3_aik/stim_done -add wave -noupdate -group TESTBENCH /l0_dds_writer_test3_aik/ref_start -add wave -noupdate -group TESTBENCH /l0_dds_writer_test3_aik/ref_stage -add wave -noupdate -group TESTBENCH /l0_dds_writer_test3_aik/ref_cnt -add wave -noupdate -group TESTBENCH /l0_dds_writer_test3_aik/ref_done -add wave -noupdate -group TESTBENCH /l0_dds_writer_test3_aik/kh_cnt -add wave -noupdate -group TESTBENCH /l0_dds_writer_test3_aik/kh_stage -add wave -noupdate -divider MISC -add wave -noupdate /l0_dds_writer_test3_aik/uut/cnt2 -add wave -noupdate /l0_dds_writer_test3_aik/uut/cnt3 -add wave -noupdate -radix unsigned /l0_dds_writer_test3_aik/uut/long_latch -add wave -noupdate /l0_dds_writer_test3_aik/uut/sample_status_info -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {5825000 ps} 0} -quietly wave cursor active 1 -configure wave -namecolwidth 187 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -configure wave -timelineunits ns -update -WaveRestoreZoom {5019227 ps} {6019868 ps} diff --git a/sim/L0_dds_writer_test3_ain.do b/sim/L0_dds_writer_test3_ain.do deleted file mode 100644 index 8d949d8..0000000 --- a/sim/L0_dds_writer_test3_ain.do +++ /dev/null @@ -1,144 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -divider SYSTEM -add wave -noupdate /l0_dds_writer_test3_ain/uut/clk -add wave -noupdate /l0_dds_writer_test3_ain/uut/reset -add wave -noupdate -radix unsigned /l0_dds_writer_test3_ain/uut/time -add wave -noupdate -radix unsigned /l0_dds_writer_test3_ain/uut/deadline_time -add wave -noupdate -divider {RTPS IN} -add wave -noupdate -group {RTPS IN} /l0_dds_writer_test3_ain/uut/start_rtps -add wave -noupdate -group {RTPS IN} -radix unsigned /l0_dds_writer_test3_ain/uut/seq_nr_rtps -add wave -noupdate -group {RTPS IN} /l0_dds_writer_test3_ain/uut/opcode_rtps -add wave -noupdate -group {RTPS IN} /l0_dds_writer_test3_ain/uut/ack_rtps -add wave -noupdate -group {RTPS IN} /l0_dds_writer_test3_ain/uut/done_rtps -add wave -noupdate -group {RTPS IN} /l0_dds_writer_test3_ain/uut/ret_rtps -add wave -noupdate -divider {RTPS OUT} -add wave -noupdate -group {RTPS OUT} -radix hexadecimal /l0_dds_writer_test3_ain/uut/cc_instance_handle -add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test3_ain/uut/cc_kind -add wave -noupdate -group {RTPS OUT} -radix unsigned /l0_dds_writer_test3_ain/uut/cc_source_timestamp -add wave -noupdate -group {RTPS OUT} -radix unsigned -childformat {{/l0_dds_writer_test3_ain/uut/cc_seq_nr(0) -radix unsigned -childformat {{/l0_dds_writer_test3_ain/uut/cc_seq_nr(0)(31) -radix unsigned} {/l0_dds_writer_test3_ain/uut/cc_seq_nr(0)(30) -radix unsigned} {/l0_dds_writer_test3_ain/uut/cc_seq_nr(0)(29) -radix unsigned} {/l0_dds_writer_test3_ain/uut/cc_seq_nr(0)(28) -radix unsigned} {/l0_dds_writer_test3_ain/uut/cc_seq_nr(0)(27) -radix unsigned} {/l0_dds_writer_test3_ain/uut/cc_seq_nr(0)(26) -radix unsigned} {/l0_dds_writer_test3_ain/uut/cc_seq_nr(0)(25) -radix unsigned} {/l0_dds_writer_test3_ain/uut/cc_seq_nr(0)(24) -radix unsigned} {/l0_dds_writer_test3_ain/uut/cc_seq_nr(0)(23) -radix unsigned} {/l0_dds_writer_test3_ain/uut/cc_seq_nr(0)(22) -radix unsigned} {/l0_dds_writer_test3_ain/uut/cc_seq_nr(0)(21) -radix unsigned} {/l0_dds_writer_test3_ain/uut/cc_seq_nr(0)(20) -radix unsigned} {/l0_dds_writer_test3_ain/uut/cc_seq_nr(0)(19) -radix unsigned} {/l0_dds_writer_test3_ain/uut/cc_seq_nr(0)(18) -radix unsigned} {/l0_dds_writer_test3_ain/uut/cc_seq_nr(0)(17) -radix unsigned} {/l0_dds_writer_test3_ain/uut/cc_seq_nr(0)(16) -radix unsigned} {/l0_dds_writer_test3_ain/uut/cc_seq_nr(0)(15) -radix unsigned} {/l0_dds_writer_test3_ain/uut/cc_seq_nr(0)(14) -radix unsigned} {/l0_dds_writer_test3_ain/uut/cc_seq_nr(0)(13) -radix unsigned} {/l0_dds_writer_test3_ain/uut/cc_seq_nr(0)(12) -radix unsigned} {/l0_dds_writer_test3_ain/uut/cc_seq_nr(0)(11) -radix unsigned} {/l0_dds_writer_test3_ain/uut/cc_seq_nr(0)(10) -radix unsigned} {/l0_dds_writer_test3_ain/uut/cc_seq_nr(0)(9) -radix unsigned} {/l0_dds_writer_test3_ain/uut/cc_seq_nr(0)(8) -radix unsigned} {/l0_dds_writer_test3_ain/uut/cc_seq_nr(0)(7) -radix unsigned} {/l0_dds_writer_test3_ain/uut/cc_seq_nr(0)(6) -radix unsigned} {/l0_dds_writer_test3_ain/uut/cc_seq_nr(0)(5) -radix unsigned} {/l0_dds_writer_test3_ain/uut/cc_seq_nr(0)(4) -radix unsigned} {/l0_dds_writer_test3_ain/uut/cc_seq_nr(0)(3) -radix unsigned} {/l0_dds_writer_test3_ain/uut/cc_seq_nr(0)(2) -radix unsigned} {/l0_dds_writer_test3_ain/uut/cc_seq_nr(0)(1) -radix unsigned} {/l0_dds_writer_test3_ain/uut/cc_seq_nr(0)(0) -radix unsigned}}} {/l0_dds_writer_test3_ain/uut/cc_seq_nr(1) -radix unsigned}} -subitemconfig {/l0_dds_writer_test3_ain/uut/cc_seq_nr(0) {-height 15 -radix unsigned -childformat {{/l0_dds_writer_test3_ain/uut/cc_seq_nr(0)(31) -radix unsigned} {/l0_dds_writer_test3_ain/uut/cc_seq_nr(0)(30) -radix unsigned} {/l0_dds_writer_test3_ain/uut/cc_seq_nr(0)(29) -radix unsigned} {/l0_dds_writer_test3_ain/uut/cc_seq_nr(0)(28) -radix unsigned} {/l0_dds_writer_test3_ain/uut/cc_seq_nr(0)(27) -radix unsigned} {/l0_dds_writer_test3_ain/uut/cc_seq_nr(0)(26) -radix unsigned} {/l0_dds_writer_test3_ain/uut/cc_seq_nr(0)(25) -radix unsigned} {/l0_dds_writer_test3_ain/uut/cc_seq_nr(0)(24) -radix unsigned} {/l0_dds_writer_test3_ain/uut/cc_seq_nr(0)(23) -radix unsigned} {/l0_dds_writer_test3_ain/uut/cc_seq_nr(0)(22) -radix unsigned} {/l0_dds_writer_test3_ain/uut/cc_seq_nr(0)(21) -radix unsigned} {/l0_dds_writer_test3_ain/uut/cc_seq_nr(0)(20) -radix unsigned} {/l0_dds_writer_test3_ain/uut/cc_seq_nr(0)(19) -radix unsigned} {/l0_dds_writer_test3_ain/uut/cc_seq_nr(0)(18) -radix unsigned} {/l0_dds_writer_test3_ain/uut/cc_seq_nr(0)(17) -radix unsigned} {/l0_dds_writer_test3_ain/uut/cc_seq_nr(0)(16) -radix unsigned} {/l0_dds_writer_test3_ain/uut/cc_seq_nr(0)(15) -radix unsigned} {/l0_dds_writer_test3_ain/uut/cc_seq_nr(0)(14) -radix unsigned} {/l0_dds_writer_test3_ain/uut/cc_seq_nr(0)(13) -radix unsigned} {/l0_dds_writer_test3_ain/uut/cc_seq_nr(0)(12) -radix unsigned} {/l0_dds_writer_test3_ain/uut/cc_seq_nr(0)(11) -radix unsigned} {/l0_dds_writer_test3_ain/uut/cc_seq_nr(0)(10) -radix unsigned} {/l0_dds_writer_test3_ain/uut/cc_seq_nr(0)(9) -radix unsigned} {/l0_dds_writer_test3_ain/uut/cc_seq_nr(0)(8) -radix unsigned} {/l0_dds_writer_test3_ain/uut/cc_seq_nr(0)(7) -radix unsigned} {/l0_dds_writer_test3_ain/uut/cc_seq_nr(0)(6) -radix unsigned} {/l0_dds_writer_test3_ain/uut/cc_seq_nr(0)(5) -radix unsigned} {/l0_dds_writer_test3_ain/uut/cc_seq_nr(0)(4) -radix unsigned} {/l0_dds_writer_test3_ain/uut/cc_seq_nr(0)(3) -radix unsigned} {/l0_dds_writer_test3_ain/uut/cc_seq_nr(0)(2) -radix unsigned} {/l0_dds_writer_test3_ain/uut/cc_seq_nr(0)(1) -radix unsigned} {/l0_dds_writer_test3_ain/uut/cc_seq_nr(0)(0) -radix unsigned}}} /l0_dds_writer_test3_ain/uut/cc_seq_nr(0)(31) {-height 15 -radix unsigned} /l0_dds_writer_test3_ain/uut/cc_seq_nr(0)(30) {-height 15 -radix unsigned} /l0_dds_writer_test3_ain/uut/cc_seq_nr(0)(29) {-height 15 -radix unsigned} /l0_dds_writer_test3_ain/uut/cc_seq_nr(0)(28) {-height 15 -radix unsigned} /l0_dds_writer_test3_ain/uut/cc_seq_nr(0)(27) {-height 15 -radix unsigned} /l0_dds_writer_test3_ain/uut/cc_seq_nr(0)(26) {-height 15 -radix unsigned} /l0_dds_writer_test3_ain/uut/cc_seq_nr(0)(25) {-height 15 -radix unsigned} /l0_dds_writer_test3_ain/uut/cc_seq_nr(0)(24) {-height 15 -radix unsigned} /l0_dds_writer_test3_ain/uut/cc_seq_nr(0)(23) {-height 15 -radix unsigned} /l0_dds_writer_test3_ain/uut/cc_seq_nr(0)(22) {-height 15 -radix unsigned} /l0_dds_writer_test3_ain/uut/cc_seq_nr(0)(21) {-height 15 -radix unsigned} /l0_dds_writer_test3_ain/uut/cc_seq_nr(0)(20) {-height 15 -radix unsigned} /l0_dds_writer_test3_ain/uut/cc_seq_nr(0)(19) {-height 15 -radix unsigned} /l0_dds_writer_test3_ain/uut/cc_seq_nr(0)(18) {-height 15 -radix unsigned} /l0_dds_writer_test3_ain/uut/cc_seq_nr(0)(17) {-height 15 -radix unsigned} /l0_dds_writer_test3_ain/uut/cc_seq_nr(0)(16) {-height 15 -radix unsigned} /l0_dds_writer_test3_ain/uut/cc_seq_nr(0)(15) {-height 15 -radix unsigned} /l0_dds_writer_test3_ain/uut/cc_seq_nr(0)(14) {-height 15 -radix unsigned} /l0_dds_writer_test3_ain/uut/cc_seq_nr(0)(13) {-height 15 -radix unsigned} /l0_dds_writer_test3_ain/uut/cc_seq_nr(0)(12) {-height 15 -radix unsigned} /l0_dds_writer_test3_ain/uut/cc_seq_nr(0)(11) {-height 15 -radix unsigned} /l0_dds_writer_test3_ain/uut/cc_seq_nr(0)(10) {-height 15 -radix unsigned} /l0_dds_writer_test3_ain/uut/cc_seq_nr(0)(9) {-height 15 -radix unsigned} /l0_dds_writer_test3_ain/uut/cc_seq_nr(0)(8) {-height 15 -radix unsigned} /l0_dds_writer_test3_ain/uut/cc_seq_nr(0)(7) {-height 15 -radix unsigned} /l0_dds_writer_test3_ain/uut/cc_seq_nr(0)(6) {-height 15 -radix unsigned} /l0_dds_writer_test3_ain/uut/cc_seq_nr(0)(5) {-height 15 -radix unsigned} /l0_dds_writer_test3_ain/uut/cc_seq_nr(0)(4) {-height 15 -radix unsigned} /l0_dds_writer_test3_ain/uut/cc_seq_nr(0)(3) {-height 15 -radix unsigned} /l0_dds_writer_test3_ain/uut/cc_seq_nr(0)(2) {-height 15 -radix unsigned} /l0_dds_writer_test3_ain/uut/cc_seq_nr(0)(1) {-height 15 -radix unsigned} /l0_dds_writer_test3_ain/uut/cc_seq_nr(0)(0) {-height 15 -radix unsigned} /l0_dds_writer_test3_ain/uut/cc_seq_nr(1) {-height 15 -radix unsigned}} /l0_dds_writer_test3_ain/uut/cc_seq_nr -add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test3_ain/uut/get_data_rtps -add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test3_ain/uut/ready_out_rtps -add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test3_ain/uut/valid_out_rtps -add wave -noupdate -group {RTPS OUT} -radix hexadecimal /l0_dds_writer_test3_ain/uut/data_out_rtps -add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test3_ain/uut/last_word_out_rtps -add wave -noupdate -divider DDS -add wave -noupdate /l0_dds_writer_test3_ain/uut/status -add wave -noupdate -expand -group DDS /l0_dds_writer_test3_ain/uut/start_dds -add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_writer_test3_ain/uut/instance_handle_dds -add wave -noupdate -expand -group DDS -radix unsigned /l0_dds_writer_test3_ain/uut/source_ts_dds -add wave -noupdate -expand -group DDS /l0_dds_writer_test3_ain/uut/opcode_dds -add wave -noupdate -expand -group DDS /l0_dds_writer_test3_ain/uut/ack_dds -add wave -noupdate -expand -group DDS /l0_dds_writer_test3_ain/uut/done_dds -add wave -noupdate -expand -group DDS -radix unsigned /l0_dds_writer_test3_ain/uut/return_code_dds -add wave -noupdate -expand -group DDS /l0_dds_writer_test3_ain/uut/ready_in_dds -add wave -noupdate -expand -group DDS /l0_dds_writer_test3_ain/uut/valid_in_dds -add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_writer_test3_ain/uut/data_in_dds -add wave -noupdate -expand -group DDS /l0_dds_writer_test3_ain/uut/last_word_in_dds -add wave -noupdate -expand -group DDS /l0_dds_writer_test3_ain/uut/ready_out_dds -add wave -noupdate -expand -group DDS /l0_dds_writer_test3_ain/uut/valid_out_dds -add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_writer_test3_ain/uut/data_out_dds -add wave -noupdate -expand -group DDS /l0_dds_writer_test3_ain/uut/last_word_out_dds -add wave -noupdate -divider {MAIN FSM} -add wave -noupdate /l0_dds_writer_test3_ain/uut/idle_sig -add wave -noupdate /l0_dds_writer_test3_ain/uut/stage -add wave -noupdate /l0_dds_writer_test3_ain/uut/stage_next -add wave -noupdate /l0_dds_writer_test3_ain/uut/cnt -add wave -noupdate -radix unsigned /l0_dds_writer_test3_ain/uut/global_seq_nr -add wave -noupdate -radix unsigned /l0_dds_writer_test3_ain/uut/global_sample_cnt -add wave -noupdate -radix unsigned /l0_dds_writer_test3_ain/uut/global_ack_cnt -add wave -noupdate -radix unsigned /l0_dds_writer_test3_ain/uut/stale_inst_cnt -add wave -noupdate /l0_dds_writer_test3_ain/uut/remove_oldest_inst_sample -add wave -noupdate /l0_dds_writer_test3_ain/uut/remove_oldest_sample -add wave -noupdate /l0_dds_writer_test3_ain/uut/remove_ack_sample -add wave -noupdate -divider MEMORY -add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test3_ain/uut/sample_abort_read -add wave -noupdate -group {SAMPLE MEM} -radix unsigned -childformat {{/l0_dds_writer_test3_ain/uut/sample_mem_ctrl_inst/addr(5) -radix unsigned} {/l0_dds_writer_test3_ain/uut/sample_mem_ctrl_inst/addr(4) -radix unsigned} {/l0_dds_writer_test3_ain/uut/sample_mem_ctrl_inst/addr(3) -radix unsigned} {/l0_dds_writer_test3_ain/uut/sample_mem_ctrl_inst/addr(2) -radix unsigned} {/l0_dds_writer_test3_ain/uut/sample_mem_ctrl_inst/addr(1) -radix unsigned} {/l0_dds_writer_test3_ain/uut/sample_mem_ctrl_inst/addr(0) -radix unsigned}} -subitemconfig {/l0_dds_writer_test3_ain/uut/sample_mem_ctrl_inst/addr(5) {-height 15 -radix unsigned} /l0_dds_writer_test3_ain/uut/sample_mem_ctrl_inst/addr(4) {-height 15 -radix unsigned} /l0_dds_writer_test3_ain/uut/sample_mem_ctrl_inst/addr(3) {-height 15 -radix unsigned} /l0_dds_writer_test3_ain/uut/sample_mem_ctrl_inst/addr(2) {-height 15 -radix unsigned} /l0_dds_writer_test3_ain/uut/sample_mem_ctrl_inst/addr(1) {-height 15 -radix unsigned} /l0_dds_writer_test3_ain/uut/sample_mem_ctrl_inst/addr(0) {-height 15 -radix unsigned}} /l0_dds_writer_test3_ain/uut/sample_mem_ctrl_inst/addr -add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test3_ain/uut/sample_mem_ctrl_inst/read -add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test3_ain/uut/sample_mem_ctrl_inst/ready_in -add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test3_ain/uut/sample_mem_ctrl_inst/valid_in -add wave -noupdate -group {SAMPLE MEM} -radix hexadecimal /l0_dds_writer_test3_ain/uut/sample_mem_ctrl_inst/data_in -add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test3_ain/uut/sample_mem_ctrl_inst/ready_out -add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test3_ain/uut/sample_mem_ctrl_inst/valid_out -add wave -noupdate -group {SAMPLE MEM} -radix hexadecimal /l0_dds_writer_test3_ain/uut/sample_mem_ctrl_inst/data_out -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test3_ain/uut/payload_abort_read -add wave -noupdate -group {PAYLOAD MEM} -radix unsigned /l0_dds_writer_test3_ain/uut/payload_mem_ctrl_inst/addr -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test3_ain/uut/payload_mem_ctrl_inst/read -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test3_ain/uut/payload_mem_ctrl_inst/ready_in -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test3_ain/uut/payload_mem_ctrl_inst/valid_in -add wave -noupdate -group {PAYLOAD MEM} -radix hexadecimal /l0_dds_writer_test3_ain/uut/payload_mem_ctrl_inst/data_in -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test3_ain/uut/payload_mem_ctrl_inst/ready_out -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test3_ain/uut/payload_mem_ctrl_inst/valid_out -add wave -noupdate -group {PAYLOAD MEM} -radix hexadecimal /l0_dds_writer_test3_ain/uut/payload_mem_ctrl_inst/data_out -add wave -noupdate /l0_dds_writer_test3_ain/uut/inst_op_start -add wave -noupdate /l0_dds_writer_test3_ain/uut/inst_opcode -add wave -noupdate /l0_dds_writer_test3_ain/uut/inst_op_done -add wave -noupdate /l0_dds_writer_test3_ain/uut/inst_stage -add wave -noupdate /l0_dds_writer_test3_ain/uut/inst_stage_next -add wave -noupdate /l0_dds_writer_test3_ain/uut/inst_cnt -add wave -noupdate -radix unsigned /l0_dds_writer_test3_ain/uut/inst_addr_base -add wave -noupdate -childformat {{/l0_dds_writer_test3_ain/uut/inst_data.key_hash -radix hexadecimal} {/l0_dds_writer_test3_ain/uut/inst_data.status_info -radix binary} {/l0_dds_writer_test3_ain/uut/inst_data.sample_cnt -radix unsigned} {/l0_dds_writer_test3_ain/uut/inst_data.ack_cnt -radix unsigned}} -expand -subitemconfig {/l0_dds_writer_test3_ain/uut/inst_data.key_hash {-height 15 -radix hexadecimal} /l0_dds_writer_test3_ain/uut/inst_data.status_info {-height 15 -radix binary} /l0_dds_writer_test3_ain/uut/inst_data.sample_cnt {-height 15 -radix unsigned} /l0_dds_writer_test3_ain/uut/inst_data.ack_cnt {-height 15 -radix unsigned}} /l0_dds_writer_test3_ain/uut/inst_data -add wave -noupdate -radix unsigned /l0_dds_writer_test3_ain/uut/inst_next_addr_base -add wave -noupdate -radix unsigned /l0_dds_writer_test3_ain/uut/inst_prev_addr_base -add wave -noupdate -divider {KEY HOLDER} -add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test3_ain/uut/start_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test3_ain/uut/opcode_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test3_ain/uut/ack_kh -add wave -noupdate -group {KEY HOLDER} -radix hexadecimal /l0_dds_writer_test3_ain/uut/data_in_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test3_ain/uut/valid_in_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test3_ain/uut/ready_in_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test3_ain/uut/last_word_in_kh -add wave -noupdate -group {KEY HOLDER} -radix hexadecimal /l0_dds_writer_test3_ain/uut/data_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test3_ain/uut/valid_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test3_ain/uut/ready_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test3_ain/uut/last_word_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test3_ain/uut/abort_kh -add wave -noupdate -divider POINTERS -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test3_ain/uut/empty_sample_list_head -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test3_ain/uut/empty_sample_list_tail -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test3_ain/uut/empty_payload_list_head -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test3_ain/uut/oldest_sample -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test3_ain/uut/newest_sample -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test3_ain/uut/inst_empty_head -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test3_ain/uut/inst_occupied_head -add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test3_ain/uut/cur_sample -add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test3_ain/uut/prev_sample -add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test3_ain/uut/next_sample -add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test3_ain/uut/cur_payload -add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test3_ain/uut/next_payload -add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test3_ain/uut/cur_inst -add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test3_ain/uut/next_inst -add wave -noupdate -divider TESTBENCH -add wave -noupdate -group TESTBENCH /l0_dds_writer_test3_ain/stim_start -add wave -noupdate -group TESTBENCH /l0_dds_writer_test3_ain/stim_stage -add wave -noupdate -group TESTBENCH /l0_dds_writer_test3_ain/stim_cnt -add wave -noupdate -group TESTBENCH /l0_dds_writer_test3_ain/stim_done -add wave -noupdate -group TESTBENCH /l0_dds_writer_test3_ain/ref_start -add wave -noupdate -group TESTBENCH /l0_dds_writer_test3_ain/ref_stage -add wave -noupdate -group TESTBENCH /l0_dds_writer_test3_ain/ref_cnt -add wave -noupdate -group TESTBENCH /l0_dds_writer_test3_ain/ref_done -add wave -noupdate -group TESTBENCH /l0_dds_writer_test3_ain/kh_cnt -add wave -noupdate -group TESTBENCH /l0_dds_writer_test3_ain/kh_stage -add wave -noupdate -divider MISC -add wave -noupdate /l0_dds_writer_test3_ain/uut/cnt2 -add wave -noupdate /l0_dds_writer_test3_ain/uut/cnt3 -add wave -noupdate -radix unsigned /l0_dds_writer_test3_ain/uut/long_latch -add wave -noupdate /l0_dds_writer_test3_ain/uut/sample_status_info -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {1025000 ps} 0} -quietly wave cursor active 1 -configure wave -namecolwidth 187 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -configure wave -timelineunits ns -update -WaveRestoreZoom {590827 ps} {1591468 ps} diff --git a/sim/L0_dds_writer_test4.do b/sim/L0_dds_writer_test4.do new file mode 100644 index 0000000..dcaffbf --- /dev/null +++ b/sim/L0_dds_writer_test4.do @@ -0,0 +1,154 @@ +onerror {resume} +radix define DDS_RETCODE { + "10#0#" "RETCODE_OK", + "10#1#" "RETCODE_ERROR", + "10#2#" "RETCODE_UNSUPPORTED", + "10#3#" "RETCODE_BAD_PARAMETER", + "10#4#" "RETCODE_PRECONDITION_NOT_MET", + "10#5#" "RETCODE_OUT_OF_RESOURCES", + "10#6#" "RETCODE_NOT_ENABLED", + "10#7#" "RETCODE_IMMUTABLE_POLICY", + "10#8#" "RETCODE_INCONSISTENT_POLICY", + "10#9#" "RETCODE_ALREADY_DELETED", + "10#10#" "RETCODE_TIMEOUT", + "10#11#" "RETCODE_NO_DATA", + "10#12#" "RETCODE_ILLEGAL_OPERATION", + -default unsigned +} +quietly WaveActivateNextPane {} 0 +add wave -noupdate -divider SYSTEM +add wave -noupdate /l0_dds_writer_test4/uut/clk +add wave -noupdate /l0_dds_writer_test4/uut/reset +add wave -noupdate -radix unsigned /l0_dds_writer_test4/uut/time +add wave -noupdate -divider {RTPS IN} +add wave -noupdate -group {RTPS IN} /l0_dds_writer_test4/uut/start_rtps +add wave -noupdate -group {RTPS IN} -radix unsigned /l0_dds_writer_test4/uut/seq_nr_rtps +add wave -noupdate -group {RTPS IN} /l0_dds_writer_test4/uut/opcode_rtps +add wave -noupdate -group {RTPS IN} /l0_dds_writer_test4/uut/ack_rtps +add wave -noupdate -group {RTPS IN} /l0_dds_writer_test4/uut/done_rtps +add wave -noupdate -group {RTPS IN} /l0_dds_writer_test4/uut/ret_rtps +add wave -noupdate -divider {RTPS OUT} +add wave -noupdate -group {RTPS OUT} -radix hexadecimal /l0_dds_writer_test4/uut/cc_instance_handle +add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test4/uut/cc_kind +add wave -noupdate -group {RTPS OUT} -radix unsigned /l0_dds_writer_test4/uut/cc_source_timestamp +add wave -noupdate -group {RTPS OUT} -radix unsigned -childformat {{/l0_dds_writer_test4/uut/cc_seq_nr(0) -radix unsigned -childformat {{/l0_dds_writer_test4/uut/cc_seq_nr(0)(0) -radix unsigned} {/l0_dds_writer_test4/uut/cc_seq_nr(0)(1) -radix unsigned}}} {/l0_dds_writer_test4/uut/cc_seq_nr(1) -radix unsigned} {/l0_dds_writer_test4/uut/cc_seq_nr(2) -radix unsigned} {/l0_dds_writer_test4/uut/cc_seq_nr(3) -radix unsigned}} -subitemconfig {/l0_dds_writer_test4/uut/cc_seq_nr(0) {-height 15 -radix unsigned -childformat {{/l0_dds_writer_test4/uut/cc_seq_nr(0)(0) -radix unsigned} {/l0_dds_writer_test4/uut/cc_seq_nr(0)(1) -radix unsigned}}} /l0_dds_writer_test4/uut/cc_seq_nr(0)(0) {-height 15 -radix unsigned} /l0_dds_writer_test4/uut/cc_seq_nr(0)(1) {-height 15 -radix unsigned} /l0_dds_writer_test4/uut/cc_seq_nr(1) {-height 15 -radix unsigned} /l0_dds_writer_test4/uut/cc_seq_nr(2) {-height 15 -radix unsigned} /l0_dds_writer_test4/uut/cc_seq_nr(3) {-height 15 -radix unsigned}} /l0_dds_writer_test4/uut/cc_seq_nr +add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test4/uut/get_data_rtps +add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test4/uut/ready_out_rtps +add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test4/uut/valid_out_rtps +add wave -noupdate -group {RTPS OUT} -radix hexadecimal /l0_dds_writer_test4/uut/data_out_rtps +add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test4/uut/last_word_out_rtps +add wave -noupdate -divider {DDS IN} +add wave -noupdate -expand -group DDS /l0_dds_writer_test4/uut/start_dds +add wave -noupdate -expand -group DDS -radix unsigned /l0_dds_writer_test4/uut/source_ts_dds +add wave -noupdate -expand -group DDS /l0_dds_writer_test4/uut/opcode_dds +add wave -noupdate -expand -group DDS /l0_dds_writer_test4/uut/ack_dds +add wave -noupdate -expand -group DDS /l0_dds_writer_test4/uut/done_dds +add wave -noupdate -expand -group DDS -radix unsigned -childformat {{/l0_dds_writer_test4/uut/return_code_dds(0) -radix DDS_RETCODE} {/l0_dds_writer_test4/uut/return_code_dds(1) -radix DDS_RETCODE} {/l0_dds_writer_test4/uut/return_code_dds(2) -radix DDS_RETCODE} {/l0_dds_writer_test4/uut/return_code_dds(3) -radix DDS_RETCODE}} -subitemconfig {/l0_dds_writer_test4/uut/return_code_dds(0) {-height 15 -radix DDS_RETCODE} /l0_dds_writer_test4/uut/return_code_dds(1) {-height 15 -radix DDS_RETCODE} /l0_dds_writer_test4/uut/return_code_dds(2) {-height 15 -radix DDS_RETCODE} /l0_dds_writer_test4/uut/return_code_dds(3) {-height 15 -radix DDS_RETCODE}} /l0_dds_writer_test4/uut/return_code_dds +add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_writer_test4/uut/instance_handle_in_dds +add wave -noupdate -expand -group DDS /l0_dds_writer_test4/uut/ready_in_dds +add wave -noupdate -expand -group DDS /l0_dds_writer_test4/uut/valid_in_dds +add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_writer_test4/uut/data_in_dds +add wave -noupdate -expand -group DDS /l0_dds_writer_test4/uut/last_word_in_dds +add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_writer_test4/uut/instance_handle_out_dds +add wave -noupdate -expand -group DDS /l0_dds_writer_test4/uut/ready_out_dds +add wave -noupdate -expand -group DDS /l0_dds_writer_test4/uut/valid_out_dds +add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_writer_test4/uut/data_out_dds +add wave -noupdate -expand -group DDS /l0_dds_writer_test4/uut/last_word_out_dds +add wave -noupdate -divider {MAIN FSM} +add wave -noupdate /l0_dds_writer_test4/uut/stage +add wave -noupdate /l0_dds_writer_test4/uut/cnt +add wave -noupdate /l0_dds_writer_test4/uut/ind +add wave -noupdate -radix unsigned /l0_dds_writer_test4/uut/global_seq_nr +add wave -noupdate -radix unsigned /l0_dds_writer_test4/uut/global_sample_cnt +add wave -noupdate -radix unsigned /l0_dds_writer_test4/uut/global_ack_cnt +add wave -noupdate -radix unsigned /l0_dds_writer_test4/uut/stale_inst_cnt +add wave -noupdate /l0_dds_writer_test4/uut/remove_oldest_inst_sample +add wave -noupdate /l0_dds_writer_test4/uut/remove_oldest_sample +add wave -noupdate /l0_dds_writer_test4/uut/remove_ack_sample +add wave -noupdate -divider MEMORY +add wave -noupdate -group {SAMPLE MEM} -radix unsigned /l0_dds_writer_test4/uut/sample_addr +add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test4/uut/sample_read +add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test4/uut/sample_ready_in +add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test4/uut/sample_valid_in +add wave -noupdate -group {SAMPLE MEM} -radix hexadecimal /l0_dds_writer_test4/uut/sample_write_data +add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test4/uut/sample_ready_out +add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test4/uut/sample_valid_out +add wave -noupdate -group {SAMPLE MEM} -radix hexadecimal /l0_dds_writer_test4/uut/sample_read_data +add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test4/uut/sample_abort_read +add wave -noupdate -group {PAYLOAD MEM} -radix unsigned /l0_dds_writer_test4/uut/payload_addr +add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test4/uut/payload_read +add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test4/uut/payload_ready_in +add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test4/uut/payload_valid_in +add wave -noupdate -group {PAYLOAD MEM} -radix hexadecimal /l0_dds_writer_test4/uut/payload_write_data +add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test4/uut/payload_ready_out +add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test4/uut/payload_valid_out +add wave -noupdate -group {PAYLOAD MEM} -radix hexadecimal /l0_dds_writer_test4/uut/payload_read_data +add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test4/uut/payload_abort_read +add wave -noupdate /l0_dds_writer_test4/uut/inst_op_start +add wave -noupdate /l0_dds_writer_test4/uut/inst_opcode +add wave -noupdate /l0_dds_writer_test4/uut/inst_op_done +add wave -noupdate /l0_dds_writer_test4/uut/inst_stage +add wave -noupdate /l0_dds_writer_test4/uut/inst_cnt +add wave -noupdate -radix unsigned /l0_dds_writer_test4/uut/inst_addr_base +add wave -noupdate -group {INSTANCE MEM} -radix unsigned /l0_dds_writer_test4/uut/inst_addr +add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test4/uut/inst_read +add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test4/uut/inst_ready_in +add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test4/uut/inst_valid_in +add wave -noupdate -group {INSTANCE MEM} -radix hexadecimal /l0_dds_writer_test4/uut/inst_write_data +add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test4/uut/inst_ready_out +add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test4/uut/inst_valid_out +add wave -noupdate -group {INSTANCE MEM} -radix hexadecimal /l0_dds_writer_test4/uut/inst_read_data +add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test4/uut/inst_abort_read +add wave -noupdate -radix hexadecimal -childformat {{/l0_dds_writer_test4/uut/inst_data.i -radix hexadecimal} {/l0_dds_writer_test4/uut/inst_data.addr -radix unsigned} {/l0_dds_writer_test4/uut/inst_data.key_hash -radix hexadecimal} {/l0_dds_writer_test4/uut/inst_data.status_info -radix binary} {/l0_dds_writer_test4/uut/inst_data.sample_cnt -radix unsigned} {/l0_dds_writer_test4/uut/inst_data.ack_cnt -radix unsigned}} -subitemconfig {/l0_dds_writer_test4/uut/inst_data.i {-height 15 -radix hexadecimal} /l0_dds_writer_test4/uut/inst_data.addr {-height 15 -radix unsigned} /l0_dds_writer_test4/uut/inst_data.key_hash {-height 15 -radix hexadecimal} /l0_dds_writer_test4/uut/inst_data.status_info {-height 15 -radix binary} /l0_dds_writer_test4/uut/inst_data.sample_cnt {-height 15 -radix unsigned} /l0_dds_writer_test4/uut/inst_data.ack_cnt {-height 15 -radix unsigned} /l0_dds_writer_test4/uut/inst_data.field_flags {-height 15}} /l0_dds_writer_test4/uut/inst_data +add wave -noupdate -divider {KEY HOLDER} +add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test4/uut/start_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test4/uut/opcode_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test4/uut/ack_kh +add wave -noupdate -group {KEY HOLDER} -radix hexadecimal /l0_dds_writer_test4/uut/data_in_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test4/uut/valid_in_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test4/uut/ready_in_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test4/uut/last_word_in_kh +add wave -noupdate -group {KEY HOLDER} -radix hexadecimal /l0_dds_writer_test4/uut/data_out_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test4/uut/valid_out_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test4/uut/ready_out_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test4/uut/last_word_out_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test4/uut/abort_kh +add wave -noupdate -divider POINTERS +add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test4/uut/empty_sample_list_head +add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test4/uut/empty_sample_list_tail +add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test4/uut/empty_payload_list_head +add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test4/uut/oldest_sample +add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test4/uut/newest_sample +add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test4/uut/inst_empty_head +add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test4/uut/inst_occupied_head +add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test4/uut/cur_sample +add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test4/uut/prev_sample +add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test4/uut/next_sample +add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test4/uut/cur_payload +add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test4/uut/next_payload +add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test4/uut/cur_inst +add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test4/uut/next_inst +add wave -noupdate -divider TESTBENCH +add wave -noupdate -divider MISC +add wave -noupdate /l0_dds_writer_test4/uut/cnt2 +add wave -noupdate /l0_dds_writer_test4/uut/cnt3 +add wave -noupdate -radix unsigned /l0_dds_writer_test4/uut/long_latch +add wave -noupdate /l0_dds_writer_test4/uut/sample_status_info +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {158543351 ps} 0} +quietly wave cursor active 1 +configure wave -namecolwidth 187 +configure wave -valuecolwidth 100 +configure wave -justifyvalue left +configure wave -signalnamewidth 1 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ns +update +WaveRestoreZoom {157882360 ps} {158883001 ps} diff --git a/sim/L0_dds_writer_test4_aik.do b/sim/L0_dds_writer_test4_aik.do deleted file mode 100644 index f268185..0000000 --- a/sim/L0_dds_writer_test4_aik.do +++ /dev/null @@ -1,154 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -divider SYSTEM -add wave -noupdate /l0_dds_writer_test4_aik/uut/clk -add wave -noupdate /l0_dds_writer_test4_aik/uut/reset -add wave -noupdate -radix unsigned /l0_dds_writer_test4_aik/uut/time -add wave -noupdate -radix unsigned /l0_dds_writer_test4_aik/uut/lease_deadline -add wave -noupdate -divider {RTPS IN} -add wave -noupdate -group {RTPS IN} /l0_dds_writer_test4_aik/uut/start_rtps -add wave -noupdate -group {RTPS IN} -radix unsigned /l0_dds_writer_test4_aik/uut/seq_nr_rtps -add wave -noupdate -group {RTPS IN} /l0_dds_writer_test4_aik/uut/opcode_rtps -add wave -noupdate -group {RTPS IN} /l0_dds_writer_test4_aik/uut/ack_rtps -add wave -noupdate -group {RTPS IN} /l0_dds_writer_test4_aik/uut/done_rtps -add wave -noupdate -group {RTPS IN} /l0_dds_writer_test4_aik/uut/ret_rtps -add wave -noupdate -divider {RTPS OUT} -add wave -noupdate -group {RTPS OUT} -radix hexadecimal /l0_dds_writer_test4_aik/uut/cc_instance_handle -add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test4_aik/uut/cc_kind -add wave -noupdate -group {RTPS OUT} -radix unsigned /l0_dds_writer_test4_aik/uut/cc_source_timestamp -add wave -noupdate -group {RTPS OUT} -radix unsigned -childformat {{/l0_dds_writer_test4_aik/uut/cc_seq_nr(0) -radix unsigned -childformat {{/l0_dds_writer_test4_aik/uut/cc_seq_nr(0)(31) -radix unsigned} {/l0_dds_writer_test4_aik/uut/cc_seq_nr(0)(30) -radix unsigned} {/l0_dds_writer_test4_aik/uut/cc_seq_nr(0)(29) -radix unsigned} {/l0_dds_writer_test4_aik/uut/cc_seq_nr(0)(28) -radix unsigned} {/l0_dds_writer_test4_aik/uut/cc_seq_nr(0)(27) -radix unsigned} {/l0_dds_writer_test4_aik/uut/cc_seq_nr(0)(26) -radix unsigned} {/l0_dds_writer_test4_aik/uut/cc_seq_nr(0)(25) -radix unsigned} {/l0_dds_writer_test4_aik/uut/cc_seq_nr(0)(24) -radix unsigned} {/l0_dds_writer_test4_aik/uut/cc_seq_nr(0)(23) -radix unsigned} {/l0_dds_writer_test4_aik/uut/cc_seq_nr(0)(22) -radix unsigned} {/l0_dds_writer_test4_aik/uut/cc_seq_nr(0)(21) -radix unsigned} {/l0_dds_writer_test4_aik/uut/cc_seq_nr(0)(20) -radix unsigned} {/l0_dds_writer_test4_aik/uut/cc_seq_nr(0)(19) -radix unsigned} {/l0_dds_writer_test4_aik/uut/cc_seq_nr(0)(18) -radix unsigned} {/l0_dds_writer_test4_aik/uut/cc_seq_nr(0)(17) -radix unsigned} {/l0_dds_writer_test4_aik/uut/cc_seq_nr(0)(16) -radix unsigned} {/l0_dds_writer_test4_aik/uut/cc_seq_nr(0)(15) -radix unsigned} {/l0_dds_writer_test4_aik/uut/cc_seq_nr(0)(14) -radix unsigned} {/l0_dds_writer_test4_aik/uut/cc_seq_nr(0)(13) -radix unsigned} {/l0_dds_writer_test4_aik/uut/cc_seq_nr(0)(12) -radix unsigned} {/l0_dds_writer_test4_aik/uut/cc_seq_nr(0)(11) -radix unsigned} {/l0_dds_writer_test4_aik/uut/cc_seq_nr(0)(10) -radix unsigned} {/l0_dds_writer_test4_aik/uut/cc_seq_nr(0)(9) -radix unsigned} {/l0_dds_writer_test4_aik/uut/cc_seq_nr(0)(8) -radix unsigned} {/l0_dds_writer_test4_aik/uut/cc_seq_nr(0)(7) -radix unsigned} {/l0_dds_writer_test4_aik/uut/cc_seq_nr(0)(6) -radix unsigned} {/l0_dds_writer_test4_aik/uut/cc_seq_nr(0)(5) -radix unsigned} {/l0_dds_writer_test4_aik/uut/cc_seq_nr(0)(4) -radix unsigned} {/l0_dds_writer_test4_aik/uut/cc_seq_nr(0)(3) -radix unsigned} {/l0_dds_writer_test4_aik/uut/cc_seq_nr(0)(2) -radix unsigned} {/l0_dds_writer_test4_aik/uut/cc_seq_nr(0)(1) -radix unsigned} {/l0_dds_writer_test4_aik/uut/cc_seq_nr(0)(0) -radix unsigned}}} {/l0_dds_writer_test4_aik/uut/cc_seq_nr(1) -radix unsigned}} -subitemconfig {/l0_dds_writer_test4_aik/uut/cc_seq_nr(0) {-height 15 -radix unsigned -childformat {{/l0_dds_writer_test4_aik/uut/cc_seq_nr(0)(31) -radix unsigned} {/l0_dds_writer_test4_aik/uut/cc_seq_nr(0)(30) -radix unsigned} {/l0_dds_writer_test4_aik/uut/cc_seq_nr(0)(29) -radix unsigned} {/l0_dds_writer_test4_aik/uut/cc_seq_nr(0)(28) -radix unsigned} {/l0_dds_writer_test4_aik/uut/cc_seq_nr(0)(27) -radix unsigned} {/l0_dds_writer_test4_aik/uut/cc_seq_nr(0)(26) -radix unsigned} {/l0_dds_writer_test4_aik/uut/cc_seq_nr(0)(25) -radix unsigned} {/l0_dds_writer_test4_aik/uut/cc_seq_nr(0)(24) -radix unsigned} {/l0_dds_writer_test4_aik/uut/cc_seq_nr(0)(23) -radix unsigned} {/l0_dds_writer_test4_aik/uut/cc_seq_nr(0)(22) -radix unsigned} {/l0_dds_writer_test4_aik/uut/cc_seq_nr(0)(21) -radix unsigned} {/l0_dds_writer_test4_aik/uut/cc_seq_nr(0)(20) -radix unsigned} {/l0_dds_writer_test4_aik/uut/cc_seq_nr(0)(19) -radix unsigned} {/l0_dds_writer_test4_aik/uut/cc_seq_nr(0)(18) -radix unsigned} {/l0_dds_writer_test4_aik/uut/cc_seq_nr(0)(17) -radix unsigned} {/l0_dds_writer_test4_aik/uut/cc_seq_nr(0)(16) -radix unsigned} {/l0_dds_writer_test4_aik/uut/cc_seq_nr(0)(15) -radix unsigned} {/l0_dds_writer_test4_aik/uut/cc_seq_nr(0)(14) -radix unsigned} {/l0_dds_writer_test4_aik/uut/cc_seq_nr(0)(13) -radix unsigned} {/l0_dds_writer_test4_aik/uut/cc_seq_nr(0)(12) -radix unsigned} {/l0_dds_writer_test4_aik/uut/cc_seq_nr(0)(11) -radix unsigned} {/l0_dds_writer_test4_aik/uut/cc_seq_nr(0)(10) -radix unsigned} {/l0_dds_writer_test4_aik/uut/cc_seq_nr(0)(9) -radix unsigned} {/l0_dds_writer_test4_aik/uut/cc_seq_nr(0)(8) -radix unsigned} {/l0_dds_writer_test4_aik/uut/cc_seq_nr(0)(7) -radix unsigned} {/l0_dds_writer_test4_aik/uut/cc_seq_nr(0)(6) -radix unsigned} {/l0_dds_writer_test4_aik/uut/cc_seq_nr(0)(5) -radix unsigned} {/l0_dds_writer_test4_aik/uut/cc_seq_nr(0)(4) -radix unsigned} {/l0_dds_writer_test4_aik/uut/cc_seq_nr(0)(3) -radix unsigned} {/l0_dds_writer_test4_aik/uut/cc_seq_nr(0)(2) -radix unsigned} {/l0_dds_writer_test4_aik/uut/cc_seq_nr(0)(1) -radix unsigned} {/l0_dds_writer_test4_aik/uut/cc_seq_nr(0)(0) -radix unsigned}}} /l0_dds_writer_test4_aik/uut/cc_seq_nr(0)(31) {-height 15 -radix unsigned} /l0_dds_writer_test4_aik/uut/cc_seq_nr(0)(30) {-height 15 -radix unsigned} /l0_dds_writer_test4_aik/uut/cc_seq_nr(0)(29) {-height 15 -radix unsigned} /l0_dds_writer_test4_aik/uut/cc_seq_nr(0)(28) {-height 15 -radix unsigned} /l0_dds_writer_test4_aik/uut/cc_seq_nr(0)(27) {-height 15 -radix unsigned} /l0_dds_writer_test4_aik/uut/cc_seq_nr(0)(26) {-height 15 -radix unsigned} /l0_dds_writer_test4_aik/uut/cc_seq_nr(0)(25) {-height 15 -radix unsigned} /l0_dds_writer_test4_aik/uut/cc_seq_nr(0)(24) {-height 15 -radix unsigned} /l0_dds_writer_test4_aik/uut/cc_seq_nr(0)(23) {-height 15 -radix unsigned} /l0_dds_writer_test4_aik/uut/cc_seq_nr(0)(22) {-height 15 -radix unsigned} /l0_dds_writer_test4_aik/uut/cc_seq_nr(0)(21) {-height 15 -radix unsigned} /l0_dds_writer_test4_aik/uut/cc_seq_nr(0)(20) {-height 15 -radix unsigned} /l0_dds_writer_test4_aik/uut/cc_seq_nr(0)(19) {-height 15 -radix unsigned} /l0_dds_writer_test4_aik/uut/cc_seq_nr(0)(18) {-height 15 -radix unsigned} /l0_dds_writer_test4_aik/uut/cc_seq_nr(0)(17) {-height 15 -radix unsigned} /l0_dds_writer_test4_aik/uut/cc_seq_nr(0)(16) {-height 15 -radix unsigned} /l0_dds_writer_test4_aik/uut/cc_seq_nr(0)(15) {-height 15 -radix unsigned} /l0_dds_writer_test4_aik/uut/cc_seq_nr(0)(14) {-height 15 -radix unsigned} /l0_dds_writer_test4_aik/uut/cc_seq_nr(0)(13) {-height 15 -radix unsigned} /l0_dds_writer_test4_aik/uut/cc_seq_nr(0)(12) {-height 15 -radix unsigned} /l0_dds_writer_test4_aik/uut/cc_seq_nr(0)(11) {-height 15 -radix unsigned} /l0_dds_writer_test4_aik/uut/cc_seq_nr(0)(10) {-height 15 -radix unsigned} /l0_dds_writer_test4_aik/uut/cc_seq_nr(0)(9) {-height 15 -radix unsigned} /l0_dds_writer_test4_aik/uut/cc_seq_nr(0)(8) {-height 15 -radix unsigned} /l0_dds_writer_test4_aik/uut/cc_seq_nr(0)(7) {-height 15 -radix unsigned} /l0_dds_writer_test4_aik/uut/cc_seq_nr(0)(6) {-height 15 -radix unsigned} /l0_dds_writer_test4_aik/uut/cc_seq_nr(0)(5) {-height 15 -radix unsigned} /l0_dds_writer_test4_aik/uut/cc_seq_nr(0)(4) {-height 15 -radix unsigned} /l0_dds_writer_test4_aik/uut/cc_seq_nr(0)(3) {-height 15 -radix unsigned} /l0_dds_writer_test4_aik/uut/cc_seq_nr(0)(2) {-height 15 -radix unsigned} /l0_dds_writer_test4_aik/uut/cc_seq_nr(0)(1) {-height 15 -radix unsigned} /l0_dds_writer_test4_aik/uut/cc_seq_nr(0)(0) {-height 15 -radix unsigned} /l0_dds_writer_test4_aik/uut/cc_seq_nr(1) {-height 15 -radix unsigned}} /l0_dds_writer_test4_aik/uut/cc_seq_nr -add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test4_aik/uut/get_data_rtps -add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test4_aik/uut/ready_out_rtps -add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test4_aik/uut/valid_out_rtps -add wave -noupdate -group {RTPS OUT} -radix hexadecimal /l0_dds_writer_test4_aik/uut/data_out_rtps -add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test4_aik/uut/last_word_out_rtps -add wave -noupdate -divider DDS -add wave -noupdate /l0_dds_writer_test4_aik/uut/status -add wave -noupdate /l0_dds_writer_test4_aik/uut/liveliness_assertion -add wave -noupdate -expand -group DDS /l0_dds_writer_test4_aik/uut/start_dds -add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_writer_test4_aik/uut/instance_handle_dds -add wave -noupdate -expand -group DDS -radix unsigned /l0_dds_writer_test4_aik/uut/source_ts_dds -add wave -noupdate -expand -group DDS /l0_dds_writer_test4_aik/uut/opcode_dds -add wave -noupdate -expand -group DDS /l0_dds_writer_test4_aik/uut/ack_dds -add wave -noupdate -expand -group DDS /l0_dds_writer_test4_aik/uut/done_dds -add wave -noupdate -expand -group DDS -radix unsigned /l0_dds_writer_test4_aik/uut/return_code_dds -add wave -noupdate -expand -group DDS /l0_dds_writer_test4_aik/uut/ready_in_dds -add wave -noupdate -expand -group DDS /l0_dds_writer_test4_aik/uut/valid_in_dds -add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_writer_test4_aik/uut/data_in_dds -add wave -noupdate -expand -group DDS /l0_dds_writer_test4_aik/uut/last_word_in_dds -add wave -noupdate -expand -group DDS /l0_dds_writer_test4_aik/uut/ready_out_dds -add wave -noupdate -expand -group DDS /l0_dds_writer_test4_aik/uut/valid_out_dds -add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_writer_test4_aik/uut/data_out_dds -add wave -noupdate -expand -group DDS /l0_dds_writer_test4_aik/uut/last_word_out_dds -add wave -noupdate -divider {MAIN FSM} -add wave -noupdate /l0_dds_writer_test4_aik/uut/idle_sig -add wave -noupdate /l0_dds_writer_test4_aik/uut/stage -add wave -noupdate /l0_dds_writer_test4_aik/uut/stage_next -add wave -noupdate /l0_dds_writer_test4_aik/uut/cnt -add wave -noupdate -radix unsigned /l0_dds_writer_test4_aik/uut/global_seq_nr -add wave -noupdate -radix unsigned /l0_dds_writer_test4_aik/uut/global_sample_cnt -add wave -noupdate -radix unsigned /l0_dds_writer_test4_aik/uut/global_ack_cnt -add wave -noupdate -radix unsigned /l0_dds_writer_test4_aik/uut/stale_inst_cnt -add wave -noupdate /l0_dds_writer_test4_aik/uut/remove_oldest_inst_sample -add wave -noupdate /l0_dds_writer_test4_aik/uut/remove_oldest_sample -add wave -noupdate /l0_dds_writer_test4_aik/uut/remove_ack_sample -add wave -noupdate -divider MEMORY -add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test4_aik/uut/sample_abort_read -add wave -noupdate -group {SAMPLE MEM} -radix unsigned -childformat {{/l0_dds_writer_test4_aik/uut/sample_mem_ctrl_inst/addr(5) -radix unsigned} {/l0_dds_writer_test4_aik/uut/sample_mem_ctrl_inst/addr(4) -radix unsigned} {/l0_dds_writer_test4_aik/uut/sample_mem_ctrl_inst/addr(3) -radix unsigned} {/l0_dds_writer_test4_aik/uut/sample_mem_ctrl_inst/addr(2) -radix unsigned} {/l0_dds_writer_test4_aik/uut/sample_mem_ctrl_inst/addr(1) -radix unsigned} {/l0_dds_writer_test4_aik/uut/sample_mem_ctrl_inst/addr(0) -radix unsigned}} -subitemconfig {/l0_dds_writer_test4_aik/uut/sample_mem_ctrl_inst/addr(5) {-height 15 -radix unsigned} /l0_dds_writer_test4_aik/uut/sample_mem_ctrl_inst/addr(4) {-height 15 -radix unsigned} /l0_dds_writer_test4_aik/uut/sample_mem_ctrl_inst/addr(3) {-height 15 -radix unsigned} /l0_dds_writer_test4_aik/uut/sample_mem_ctrl_inst/addr(2) {-height 15 -radix unsigned} /l0_dds_writer_test4_aik/uut/sample_mem_ctrl_inst/addr(1) {-height 15 -radix unsigned} /l0_dds_writer_test4_aik/uut/sample_mem_ctrl_inst/addr(0) {-height 15 -radix unsigned}} /l0_dds_writer_test4_aik/uut/sample_mem_ctrl_inst/addr -add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test4_aik/uut/sample_mem_ctrl_inst/read -add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test4_aik/uut/sample_mem_ctrl_inst/ready_in -add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test4_aik/uut/sample_mem_ctrl_inst/valid_in -add wave -noupdate -group {SAMPLE MEM} -radix hexadecimal /l0_dds_writer_test4_aik/uut/sample_mem_ctrl_inst/data_in -add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test4_aik/uut/sample_mem_ctrl_inst/ready_out -add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test4_aik/uut/sample_mem_ctrl_inst/valid_out -add wave -noupdate -group {SAMPLE MEM} -radix hexadecimal /l0_dds_writer_test4_aik/uut/sample_mem_ctrl_inst/data_out -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test4_aik/uut/payload_abort_read -add wave -noupdate -group {PAYLOAD MEM} -radix unsigned /l0_dds_writer_test4_aik/uut/payload_mem_ctrl_inst/addr -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test4_aik/uut/payload_mem_ctrl_inst/read -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test4_aik/uut/payload_mem_ctrl_inst/ready_in -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test4_aik/uut/payload_mem_ctrl_inst/valid_in -add wave -noupdate -group {PAYLOAD MEM} -radix hexadecimal /l0_dds_writer_test4_aik/uut/payload_mem_ctrl_inst/data_in -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test4_aik/uut/payload_mem_ctrl_inst/ready_out -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test4_aik/uut/payload_mem_ctrl_inst/valid_out -add wave -noupdate -group {PAYLOAD MEM} -radix hexadecimal /l0_dds_writer_test4_aik/uut/payload_mem_ctrl_inst/data_out -add wave -noupdate /l0_dds_writer_test4_aik/uut/inst_op_start -add wave -noupdate /l0_dds_writer_test4_aik/uut/inst_opcode -add wave -noupdate /l0_dds_writer_test4_aik/uut/inst_op_done -add wave -noupdate /l0_dds_writer_test4_aik/uut/inst_stage -add wave -noupdate /l0_dds_writer_test4_aik/uut/inst_stage_next -add wave -noupdate /l0_dds_writer_test4_aik/uut/inst_cnt -add wave -noupdate -radix unsigned /l0_dds_writer_test4_aik/uut/inst_addr_base -add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test4_aik/uut/inst_abort_read -add wave -noupdate -group {INSTANCE MEM} -radix unsigned /l0_dds_writer_test4_aik/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/addr -add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test4_aik/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/read -add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test4_aik/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/ready_in -add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test4_aik/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/valid_in -add wave -noupdate -group {INSTANCE MEM} -radix hexadecimal /l0_dds_writer_test4_aik/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/data_in -add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test4_aik/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/ready_out -add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test4_aik/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/valid_out -add wave -noupdate -group {INSTANCE MEM} -radix hexadecimal /l0_dds_writer_test4_aik/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/data_out -add wave -noupdate -childformat {{/l0_dds_writer_test4_aik/uut/inst_data.key_hash -radix hexadecimal} {/l0_dds_writer_test4_aik/uut/inst_data.status_info -radix binary} {/l0_dds_writer_test4_aik/uut/inst_data.sample_cnt -radix unsigned} {/l0_dds_writer_test4_aik/uut/inst_data.ack_cnt -radix unsigned}} -expand -subitemconfig {/l0_dds_writer_test4_aik/uut/inst_data.key_hash {-height 15 -radix hexadecimal} /l0_dds_writer_test4_aik/uut/inst_data.status_info {-height 15 -radix binary} /l0_dds_writer_test4_aik/uut/inst_data.sample_cnt {-height 15 -radix unsigned} /l0_dds_writer_test4_aik/uut/inst_data.ack_cnt {-height 15 -radix unsigned}} /l0_dds_writer_test4_aik/uut/inst_data -add wave -noupdate -radix unsigned /l0_dds_writer_test4_aik/uut/inst_next_addr_base -add wave -noupdate -radix unsigned /l0_dds_writer_test4_aik/uut/inst_prev_addr_base -add wave -noupdate -divider {KEY HOLDER} -add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test4_aik/uut/start_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test4_aik/uut/opcode_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test4_aik/uut/ack_kh -add wave -noupdate -group {KEY HOLDER} -radix hexadecimal /l0_dds_writer_test4_aik/uut/data_in_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test4_aik/uut/valid_in_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test4_aik/uut/ready_in_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test4_aik/uut/last_word_in_kh -add wave -noupdate -group {KEY HOLDER} -radix hexadecimal /l0_dds_writer_test4_aik/uut/data_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test4_aik/uut/valid_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test4_aik/uut/ready_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test4_aik/uut/last_word_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test4_aik/uut/abort_kh -add wave -noupdate -divider POINTERS -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test4_aik/uut/empty_sample_list_head -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test4_aik/uut/empty_sample_list_tail -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test4_aik/uut/empty_payload_list_head -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test4_aik/uut/oldest_sample -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test4_aik/uut/newest_sample -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test4_aik/uut/inst_empty_head -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test4_aik/uut/inst_occupied_head -add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test4_aik/uut/cur_sample -add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test4_aik/uut/prev_sample -add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test4_aik/uut/next_sample -add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test4_aik/uut/cur_payload -add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test4_aik/uut/next_payload -add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test4_aik/uut/cur_inst -add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test4_aik/uut/next_inst -add wave -noupdate -divider TESTBENCH -add wave -noupdate -group TESTBENCH /l0_dds_writer_test4_aik/stim_start -add wave -noupdate -group TESTBENCH /l0_dds_writer_test4_aik/stim_stage -add wave -noupdate -group TESTBENCH /l0_dds_writer_test4_aik/stim_cnt -add wave -noupdate -group TESTBENCH /l0_dds_writer_test4_aik/stim_done -add wave -noupdate -group TESTBENCH /l0_dds_writer_test4_aik/ref_start -add wave -noupdate -group TESTBENCH /l0_dds_writer_test4_aik/ref_stage -add wave -noupdate -group TESTBENCH /l0_dds_writer_test4_aik/ref_cnt -add wave -noupdate -group TESTBENCH /l0_dds_writer_test4_aik/ref_done -add wave -noupdate -group TESTBENCH /l0_dds_writer_test4_aik/kh_cnt -add wave -noupdate -group TESTBENCH /l0_dds_writer_test4_aik/kh_stage -add wave -noupdate -divider MISC -add wave -noupdate /l0_dds_writer_test4_aik/uut/cnt2 -add wave -noupdate /l0_dds_writer_test4_aik/uut/cnt3 -add wave -noupdate -radix unsigned /l0_dds_writer_test4_aik/uut/long_latch -add wave -noupdate /l0_dds_writer_test4_aik/uut/sample_status_info -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {7825000 ps} 0} -quietly wave cursor active 1 -configure wave -namecolwidth 187 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -configure wave -timelineunits ns -update -WaveRestoreZoom {7324680 ps} {8325321 ps} diff --git a/sim/L0_dds_writer_test5.do b/sim/L0_dds_writer_test5.do new file mode 100644 index 0000000..5996a3b --- /dev/null +++ b/sim/L0_dds_writer_test5.do @@ -0,0 +1,155 @@ +onerror {resume} +radix define DDS_RETCODE { + "10#0#" "RETCODE_OK", + "10#1#" "RETCODE_ERROR", + "10#2#" "RETCODE_UNSUPPORTED", + "10#3#" "RETCODE_BAD_PARAMETER", + "10#4#" "RETCODE_PRECONDITION_NOT_MET", + "10#5#" "RETCODE_OUT_OF_RESOURCES", + "10#6#" "RETCODE_NOT_ENABLED", + "10#7#" "RETCODE_IMMUTABLE_POLICY", + "10#8#" "RETCODE_INCONSISTENT_POLICY", + "10#9#" "RETCODE_ALREADY_DELETED", + "10#10#" "RETCODE_TIMEOUT", + "10#11#" "RETCODE_NO_DATA", + "10#12#" "RETCODE_ILLEGAL_OPERATION", + -default unsigned +} +quietly WaveActivateNextPane {} 0 +add wave -noupdate -divider SYSTEM +add wave -noupdate /l0_dds_writer_test5/uut/clk +add wave -noupdate /l0_dds_writer_test5/uut/reset +add wave -noupdate -radix unsigned /l0_dds_writer_test5/uut/time +add wave -noupdate -radix unsigned /l0_dds_writer_test5/uut/lifespan_time +add wave -noupdate -divider {RTPS IN} +add wave -noupdate -group {RTPS IN} /l0_dds_writer_test5/uut/start_rtps +add wave -noupdate -group {RTPS IN} -radix unsigned /l0_dds_writer_test5/uut/seq_nr_rtps +add wave -noupdate -group {RTPS IN} /l0_dds_writer_test5/uut/opcode_rtps +add wave -noupdate -group {RTPS IN} /l0_dds_writer_test5/uut/ack_rtps +add wave -noupdate -group {RTPS IN} /l0_dds_writer_test5/uut/done_rtps +add wave -noupdate -group {RTPS IN} /l0_dds_writer_test5/uut/ret_rtps +add wave -noupdate -divider {RTPS OUT} +add wave -noupdate -group {RTPS OUT} -radix hexadecimal /l0_dds_writer_test5/uut/cc_instance_handle +add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test5/uut/cc_kind +add wave -noupdate -group {RTPS OUT} -radix unsigned /l0_dds_writer_test5/uut/cc_source_timestamp +add wave -noupdate -group {RTPS OUT} -radix unsigned -childformat {{/l0_dds_writer_test5/uut/cc_seq_nr(0) -radix unsigned -childformat {{/l0_dds_writer_test5/uut/cc_seq_nr(0)(0) -radix unsigned} {/l0_dds_writer_test5/uut/cc_seq_nr(0)(1) -radix unsigned}}} {/l0_dds_writer_test5/uut/cc_seq_nr(1) -radix unsigned}} -subitemconfig {/l0_dds_writer_test5/uut/cc_seq_nr(0) {-height 15 -radix unsigned -childformat {{/l0_dds_writer_test5/uut/cc_seq_nr(0)(0) -radix unsigned} {/l0_dds_writer_test5/uut/cc_seq_nr(0)(1) -radix unsigned}}} /l0_dds_writer_test5/uut/cc_seq_nr(0)(0) {-height 15 -radix unsigned} /l0_dds_writer_test5/uut/cc_seq_nr(0)(1) {-height 15 -radix unsigned} /l0_dds_writer_test5/uut/cc_seq_nr(1) {-height 15 -radix unsigned}} /l0_dds_writer_test5/uut/cc_seq_nr +add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test5/uut/get_data_rtps +add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test5/uut/ready_out_rtps +add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test5/uut/valid_out_rtps +add wave -noupdate -group {RTPS OUT} -radix hexadecimal /l0_dds_writer_test5/uut/data_out_rtps +add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test5/uut/last_word_out_rtps +add wave -noupdate -divider {DDS IN} +add wave -noupdate -expand -group DDS /l0_dds_writer_test5/uut/start_dds +add wave -noupdate -expand -group DDS -radix unsigned /l0_dds_writer_test5/uut/source_ts_dds +add wave -noupdate -expand -group DDS /l0_dds_writer_test5/uut/opcode_dds +add wave -noupdate -expand -group DDS /l0_dds_writer_test5/uut/ack_dds +add wave -noupdate -expand -group DDS /l0_dds_writer_test5/uut/done_dds +add wave -noupdate -expand -group DDS -radix unsigned -childformat {{/l0_dds_writer_test5/uut/return_code_dds(0) -radix DDS_RETCODE} {/l0_dds_writer_test5/uut/return_code_dds(1) -radix DDS_RETCODE}} -subitemconfig {/l0_dds_writer_test5/uut/return_code_dds(0) {-height 15 -radix DDS_RETCODE} /l0_dds_writer_test5/uut/return_code_dds(1) {-height 15 -radix DDS_RETCODE}} /l0_dds_writer_test5/uut/return_code_dds +add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_writer_test5/uut/instance_handle_in_dds +add wave -noupdate -expand -group DDS /l0_dds_writer_test5/uut/ready_in_dds +add wave -noupdate -expand -group DDS /l0_dds_writer_test5/uut/valid_in_dds +add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_writer_test5/uut/data_in_dds +add wave -noupdate -expand -group DDS /l0_dds_writer_test5/uut/last_word_in_dds +add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_writer_test5/uut/instance_handle_out_dds +add wave -noupdate -expand -group DDS /l0_dds_writer_test5/uut/ready_out_dds +add wave -noupdate -expand -group DDS /l0_dds_writer_test5/uut/valid_out_dds +add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_writer_test5/uut/data_out_dds +add wave -noupdate -expand -group DDS /l0_dds_writer_test5/uut/last_word_out_dds +add wave -noupdate -divider {MAIN FSM} +add wave -noupdate /l0_dds_writer_test5/uut/stage +add wave -noupdate /l0_dds_writer_test5/uut/cnt +add wave -noupdate /l0_dds_writer_test5/uut/ind +add wave -noupdate -radix unsigned /l0_dds_writer_test5/uut/global_seq_nr +add wave -noupdate -radix unsigned /l0_dds_writer_test5/uut/global_sample_cnt +add wave -noupdate -radix unsigned /l0_dds_writer_test5/uut/global_ack_cnt +add wave -noupdate -radix unsigned /l0_dds_writer_test5/uut/stale_inst_cnt +add wave -noupdate /l0_dds_writer_test5/uut/remove_oldest_inst_sample +add wave -noupdate /l0_dds_writer_test5/uut/remove_oldest_sample +add wave -noupdate /l0_dds_writer_test5/uut/remove_ack_sample +add wave -noupdate -divider MEMORY +add wave -noupdate -group {SAMPLE MEM} -radix unsigned /l0_dds_writer_test5/uut/sample_addr +add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test5/uut/sample_read +add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test5/uut/sample_ready_in +add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test5/uut/sample_valid_in +add wave -noupdate -group {SAMPLE MEM} -radix hexadecimal /l0_dds_writer_test5/uut/sample_write_data +add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test5/uut/sample_ready_out +add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test5/uut/sample_valid_out +add wave -noupdate -group {SAMPLE MEM} -radix hexadecimal /l0_dds_writer_test5/uut/sample_read_data +add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test5/uut/sample_abort_read +add wave -noupdate -group {PAYLOAD MEM} -radix unsigned /l0_dds_writer_test5/uut/payload_addr +add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test5/uut/payload_read +add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test5/uut/payload_ready_in +add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test5/uut/payload_valid_in +add wave -noupdate -group {PAYLOAD MEM} -radix hexadecimal /l0_dds_writer_test5/uut/payload_write_data +add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test5/uut/payload_ready_out +add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test5/uut/payload_valid_out +add wave -noupdate -group {PAYLOAD MEM} -radix hexadecimal /l0_dds_writer_test5/uut/payload_read_data +add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test5/uut/payload_abort_read +add wave -noupdate /l0_dds_writer_test5/uut/inst_op_start +add wave -noupdate /l0_dds_writer_test5/uut/inst_opcode +add wave -noupdate /l0_dds_writer_test5/uut/inst_op_done +add wave -noupdate /l0_dds_writer_test5/uut/inst_stage +add wave -noupdate /l0_dds_writer_test5/uut/inst_cnt +add wave -noupdate -radix unsigned /l0_dds_writer_test5/uut/inst_addr_base +add wave -noupdate -group {INSTANCE MEM} -radix unsigned /l0_dds_writer_test5/uut/inst_addr +add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test5/uut/inst_read +add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test5/uut/inst_ready_in +add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test5/uut/inst_valid_in +add wave -noupdate -group {INSTANCE MEM} -radix hexadecimal /l0_dds_writer_test5/uut/inst_write_data +add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test5/uut/inst_ready_out +add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test5/uut/inst_valid_out +add wave -noupdate -group {INSTANCE MEM} -radix hexadecimal /l0_dds_writer_test5/uut/inst_read_data +add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test5/uut/inst_abort_read +add wave -noupdate -radix hexadecimal -childformat {{/l0_dds_writer_test5/uut/inst_data.i -radix hexadecimal} {/l0_dds_writer_test5/uut/inst_data.addr -radix unsigned} {/l0_dds_writer_test5/uut/inst_data.key_hash -radix hexadecimal} {/l0_dds_writer_test5/uut/inst_data.status_info -radix binary} {/l0_dds_writer_test5/uut/inst_data.sample_cnt -radix unsigned} {/l0_dds_writer_test5/uut/inst_data.ack_cnt -radix unsigned}} -subitemconfig {/l0_dds_writer_test5/uut/inst_data.i {-height 15 -radix hexadecimal} /l0_dds_writer_test5/uut/inst_data.addr {-height 15 -radix unsigned} /l0_dds_writer_test5/uut/inst_data.key_hash {-height 15 -radix hexadecimal} /l0_dds_writer_test5/uut/inst_data.status_info {-height 15 -radix binary} /l0_dds_writer_test5/uut/inst_data.sample_cnt {-height 15 -radix unsigned} /l0_dds_writer_test5/uut/inst_data.ack_cnt {-height 15 -radix unsigned} /l0_dds_writer_test5/uut/inst_data.field_flags {-height 15}} /l0_dds_writer_test5/uut/inst_data +add wave -noupdate -divider {KEY HOLDER} +add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test5/uut/start_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test5/uut/opcode_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test5/uut/ack_kh +add wave -noupdate -group {KEY HOLDER} -radix hexadecimal /l0_dds_writer_test5/uut/data_in_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test5/uut/valid_in_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test5/uut/ready_in_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test5/uut/last_word_in_kh +add wave -noupdate -group {KEY HOLDER} -radix hexadecimal /l0_dds_writer_test5/uut/data_out_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test5/uut/valid_out_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test5/uut/ready_out_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test5/uut/last_word_out_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test5/uut/abort_kh +add wave -noupdate -divider POINTERS +add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test5/uut/empty_sample_list_head +add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test5/uut/empty_sample_list_tail +add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test5/uut/empty_payload_list_head +add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test5/uut/oldest_sample +add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test5/uut/newest_sample +add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test5/uut/inst_empty_head +add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test5/uut/inst_occupied_head +add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test5/uut/cur_sample +add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test5/uut/prev_sample +add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test5/uut/next_sample +add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test5/uut/cur_payload +add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test5/uut/next_payload +add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test5/uut/cur_inst +add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test5/uut/next_inst +add wave -noupdate -divider TESTBENCH +add wave -noupdate -divider MISC +add wave -noupdate /l0_dds_writer_test5/uut/cnt2 +add wave -noupdate /l0_dds_writer_test5/uut/cnt3 +add wave -noupdate -radix unsigned /l0_dds_writer_test5/uut/long_latch +add wave -noupdate /l0_dds_writer_test5/uut/sample_status_info +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {27047657 ps} 0} +quietly wave cursor active 1 +configure wave -namecolwidth 187 +configure wave -valuecolwidth 100 +configure wave -justifyvalue left +configure wave -signalnamewidth 1 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ns +update +WaveRestoreZoom {26890438 ps} {27891079 ps} diff --git a/sim/L0_dds_writer_test5_afk.do b/sim/L0_dds_writer_test5_afk.do deleted file mode 100644 index e843c64..0000000 --- a/sim/L0_dds_writer_test5_afk.do +++ /dev/null @@ -1,151 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -divider SYSTEM -add wave -noupdate /l0_dds_writer_test5_afk/uut/clk -add wave -noupdate /l0_dds_writer_test5_afk/uut/reset -add wave -noupdate -radix unsigned /l0_dds_writer_test5_afk/uut/time -add wave -noupdate -radix unsigned /l0_dds_writer_test5_afk/uut/lifespan_time -add wave -noupdate -divider {RTPS IN} -add wave -noupdate -group {RTPS IN} /l0_dds_writer_test5_afk/uut/start_rtps -add wave -noupdate -group {RTPS IN} -radix unsigned /l0_dds_writer_test5_afk/uut/seq_nr_rtps -add wave -noupdate -group {RTPS IN} /l0_dds_writer_test5_afk/uut/opcode_rtps -add wave -noupdate -group {RTPS IN} /l0_dds_writer_test5_afk/uut/ack_rtps -add wave -noupdate -group {RTPS IN} /l0_dds_writer_test5_afk/uut/done_rtps -add wave -noupdate -group {RTPS IN} /l0_dds_writer_test5_afk/uut/ret_rtps -add wave -noupdate -divider {RTPS OUT} -add wave -noupdate -group {RTPS OUT} -radix hexadecimal /l0_dds_writer_test5_afk/uut/cc_instance_handle -add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test5_afk/uut/cc_kind -add wave -noupdate -group {RTPS OUT} -radix unsigned /l0_dds_writer_test5_afk/uut/cc_source_timestamp -add wave -noupdate -group {RTPS OUT} -radix unsigned -childformat {{/l0_dds_writer_test5_afk/uut/cc_seq_nr(0) -radix unsigned -childformat {{/l0_dds_writer_test5_afk/uut/cc_seq_nr(0)(31) -radix unsigned} {/l0_dds_writer_test5_afk/uut/cc_seq_nr(0)(30) -radix unsigned} {/l0_dds_writer_test5_afk/uut/cc_seq_nr(0)(29) -radix unsigned} {/l0_dds_writer_test5_afk/uut/cc_seq_nr(0)(28) -radix unsigned} {/l0_dds_writer_test5_afk/uut/cc_seq_nr(0)(27) -radix unsigned} {/l0_dds_writer_test5_afk/uut/cc_seq_nr(0)(26) -radix unsigned} {/l0_dds_writer_test5_afk/uut/cc_seq_nr(0)(25) -radix unsigned} {/l0_dds_writer_test5_afk/uut/cc_seq_nr(0)(24) -radix unsigned} {/l0_dds_writer_test5_afk/uut/cc_seq_nr(0)(23) -radix unsigned} {/l0_dds_writer_test5_afk/uut/cc_seq_nr(0)(22) -radix unsigned} {/l0_dds_writer_test5_afk/uut/cc_seq_nr(0)(21) -radix unsigned} {/l0_dds_writer_test5_afk/uut/cc_seq_nr(0)(20) -radix unsigned} {/l0_dds_writer_test5_afk/uut/cc_seq_nr(0)(19) -radix unsigned} {/l0_dds_writer_test5_afk/uut/cc_seq_nr(0)(18) -radix unsigned} {/l0_dds_writer_test5_afk/uut/cc_seq_nr(0)(17) -radix unsigned} {/l0_dds_writer_test5_afk/uut/cc_seq_nr(0)(16) -radix unsigned} {/l0_dds_writer_test5_afk/uut/cc_seq_nr(0)(15) -radix unsigned} {/l0_dds_writer_test5_afk/uut/cc_seq_nr(0)(14) -radix unsigned} {/l0_dds_writer_test5_afk/uut/cc_seq_nr(0)(13) -radix unsigned} {/l0_dds_writer_test5_afk/uut/cc_seq_nr(0)(12) -radix unsigned} {/l0_dds_writer_test5_afk/uut/cc_seq_nr(0)(11) -radix unsigned} {/l0_dds_writer_test5_afk/uut/cc_seq_nr(0)(10) -radix unsigned} {/l0_dds_writer_test5_afk/uut/cc_seq_nr(0)(9) -radix unsigned} {/l0_dds_writer_test5_afk/uut/cc_seq_nr(0)(8) -radix unsigned} {/l0_dds_writer_test5_afk/uut/cc_seq_nr(0)(7) -radix unsigned} {/l0_dds_writer_test5_afk/uut/cc_seq_nr(0)(6) -radix unsigned} {/l0_dds_writer_test5_afk/uut/cc_seq_nr(0)(5) -radix unsigned} {/l0_dds_writer_test5_afk/uut/cc_seq_nr(0)(4) -radix unsigned} {/l0_dds_writer_test5_afk/uut/cc_seq_nr(0)(3) -radix unsigned} {/l0_dds_writer_test5_afk/uut/cc_seq_nr(0)(2) -radix unsigned} {/l0_dds_writer_test5_afk/uut/cc_seq_nr(0)(1) -radix unsigned} {/l0_dds_writer_test5_afk/uut/cc_seq_nr(0)(0) -radix unsigned}}} {/l0_dds_writer_test5_afk/uut/cc_seq_nr(1) -radix unsigned}} -subitemconfig {/l0_dds_writer_test5_afk/uut/cc_seq_nr(0) {-height 15 -radix unsigned -childformat {{/l0_dds_writer_test5_afk/uut/cc_seq_nr(0)(31) -radix unsigned} {/l0_dds_writer_test5_afk/uut/cc_seq_nr(0)(30) -radix unsigned} {/l0_dds_writer_test5_afk/uut/cc_seq_nr(0)(29) -radix unsigned} {/l0_dds_writer_test5_afk/uut/cc_seq_nr(0)(28) -radix unsigned} {/l0_dds_writer_test5_afk/uut/cc_seq_nr(0)(27) -radix unsigned} {/l0_dds_writer_test5_afk/uut/cc_seq_nr(0)(26) -radix unsigned} {/l0_dds_writer_test5_afk/uut/cc_seq_nr(0)(25) -radix unsigned} {/l0_dds_writer_test5_afk/uut/cc_seq_nr(0)(24) -radix unsigned} {/l0_dds_writer_test5_afk/uut/cc_seq_nr(0)(23) -radix unsigned} {/l0_dds_writer_test5_afk/uut/cc_seq_nr(0)(22) -radix unsigned} {/l0_dds_writer_test5_afk/uut/cc_seq_nr(0)(21) -radix unsigned} {/l0_dds_writer_test5_afk/uut/cc_seq_nr(0)(20) -radix unsigned} {/l0_dds_writer_test5_afk/uut/cc_seq_nr(0)(19) -radix unsigned} {/l0_dds_writer_test5_afk/uut/cc_seq_nr(0)(18) -radix unsigned} {/l0_dds_writer_test5_afk/uut/cc_seq_nr(0)(17) -radix unsigned} {/l0_dds_writer_test5_afk/uut/cc_seq_nr(0)(16) -radix unsigned} {/l0_dds_writer_test5_afk/uut/cc_seq_nr(0)(15) -radix unsigned} {/l0_dds_writer_test5_afk/uut/cc_seq_nr(0)(14) -radix unsigned} {/l0_dds_writer_test5_afk/uut/cc_seq_nr(0)(13) -radix unsigned} {/l0_dds_writer_test5_afk/uut/cc_seq_nr(0)(12) -radix unsigned} {/l0_dds_writer_test5_afk/uut/cc_seq_nr(0)(11) -radix unsigned} {/l0_dds_writer_test5_afk/uut/cc_seq_nr(0)(10) -radix unsigned} {/l0_dds_writer_test5_afk/uut/cc_seq_nr(0)(9) -radix unsigned} {/l0_dds_writer_test5_afk/uut/cc_seq_nr(0)(8) -radix unsigned} {/l0_dds_writer_test5_afk/uut/cc_seq_nr(0)(7) -radix unsigned} {/l0_dds_writer_test5_afk/uut/cc_seq_nr(0)(6) -radix unsigned} {/l0_dds_writer_test5_afk/uut/cc_seq_nr(0)(5) -radix unsigned} {/l0_dds_writer_test5_afk/uut/cc_seq_nr(0)(4) -radix unsigned} {/l0_dds_writer_test5_afk/uut/cc_seq_nr(0)(3) -radix unsigned} {/l0_dds_writer_test5_afk/uut/cc_seq_nr(0)(2) -radix unsigned} {/l0_dds_writer_test5_afk/uut/cc_seq_nr(0)(1) -radix unsigned} {/l0_dds_writer_test5_afk/uut/cc_seq_nr(0)(0) -radix unsigned}}} /l0_dds_writer_test5_afk/uut/cc_seq_nr(0)(31) {-height 15 -radix unsigned} /l0_dds_writer_test5_afk/uut/cc_seq_nr(0)(30) {-height 15 -radix unsigned} /l0_dds_writer_test5_afk/uut/cc_seq_nr(0)(29) {-height 15 -radix unsigned} /l0_dds_writer_test5_afk/uut/cc_seq_nr(0)(28) {-height 15 -radix unsigned} /l0_dds_writer_test5_afk/uut/cc_seq_nr(0)(27) {-height 15 -radix unsigned} /l0_dds_writer_test5_afk/uut/cc_seq_nr(0)(26) {-height 15 -radix unsigned} /l0_dds_writer_test5_afk/uut/cc_seq_nr(0)(25) {-height 15 -radix unsigned} /l0_dds_writer_test5_afk/uut/cc_seq_nr(0)(24) {-height 15 -radix unsigned} /l0_dds_writer_test5_afk/uut/cc_seq_nr(0)(23) {-height 15 -radix unsigned} /l0_dds_writer_test5_afk/uut/cc_seq_nr(0)(22) {-height 15 -radix unsigned} /l0_dds_writer_test5_afk/uut/cc_seq_nr(0)(21) {-height 15 -radix unsigned} /l0_dds_writer_test5_afk/uut/cc_seq_nr(0)(20) {-height 15 -radix unsigned} /l0_dds_writer_test5_afk/uut/cc_seq_nr(0)(19) {-height 15 -radix unsigned} /l0_dds_writer_test5_afk/uut/cc_seq_nr(0)(18) {-height 15 -radix unsigned} /l0_dds_writer_test5_afk/uut/cc_seq_nr(0)(17) {-height 15 -radix unsigned} /l0_dds_writer_test5_afk/uut/cc_seq_nr(0)(16) {-height 15 -radix unsigned} /l0_dds_writer_test5_afk/uut/cc_seq_nr(0)(15) {-height 15 -radix unsigned} /l0_dds_writer_test5_afk/uut/cc_seq_nr(0)(14) {-height 15 -radix unsigned} /l0_dds_writer_test5_afk/uut/cc_seq_nr(0)(13) {-height 15 -radix unsigned} /l0_dds_writer_test5_afk/uut/cc_seq_nr(0)(12) {-height 15 -radix unsigned} /l0_dds_writer_test5_afk/uut/cc_seq_nr(0)(11) {-height 15 -radix unsigned} /l0_dds_writer_test5_afk/uut/cc_seq_nr(0)(10) {-height 15 -radix unsigned} /l0_dds_writer_test5_afk/uut/cc_seq_nr(0)(9) {-height 15 -radix unsigned} /l0_dds_writer_test5_afk/uut/cc_seq_nr(0)(8) {-height 15 -radix unsigned} /l0_dds_writer_test5_afk/uut/cc_seq_nr(0)(7) {-height 15 -radix unsigned} /l0_dds_writer_test5_afk/uut/cc_seq_nr(0)(6) {-height 15 -radix unsigned} /l0_dds_writer_test5_afk/uut/cc_seq_nr(0)(5) {-height 15 -radix unsigned} /l0_dds_writer_test5_afk/uut/cc_seq_nr(0)(4) {-height 15 -radix unsigned} /l0_dds_writer_test5_afk/uut/cc_seq_nr(0)(3) {-height 15 -radix unsigned} /l0_dds_writer_test5_afk/uut/cc_seq_nr(0)(2) {-height 15 -radix unsigned} /l0_dds_writer_test5_afk/uut/cc_seq_nr(0)(1) {-height 15 -radix unsigned} /l0_dds_writer_test5_afk/uut/cc_seq_nr(0)(0) {-height 15 -radix unsigned} /l0_dds_writer_test5_afk/uut/cc_seq_nr(1) {-height 15 -radix unsigned}} /l0_dds_writer_test5_afk/uut/cc_seq_nr -add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test5_afk/uut/get_data_rtps -add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test5_afk/uut/ready_out_rtps -add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test5_afk/uut/valid_out_rtps -add wave -noupdate -group {RTPS OUT} -radix hexadecimal /l0_dds_writer_test5_afk/uut/data_out_rtps -add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test5_afk/uut/last_word_out_rtps -add wave -noupdate -divider DDS -add wave -noupdate /l0_dds_writer_test5_afk/uut/status -add wave -noupdate /l0_dds_writer_test5_afk/uut/liveliness_assertion -add wave -noupdate -expand -group DDS /l0_dds_writer_test5_afk/uut/start_dds -add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_writer_test5_afk/uut/instance_handle_dds -add wave -noupdate -expand -group DDS -radix unsigned /l0_dds_writer_test5_afk/uut/source_ts_dds -add wave -noupdate -expand -group DDS /l0_dds_writer_test5_afk/uut/opcode_dds -add wave -noupdate -expand -group DDS /l0_dds_writer_test5_afk/uut/ack_dds -add wave -noupdate -expand -group DDS /l0_dds_writer_test5_afk/uut/done_dds -add wave -noupdate -expand -group DDS -radix unsigned /l0_dds_writer_test5_afk/uut/return_code_dds -add wave -noupdate -expand -group DDS /l0_dds_writer_test5_afk/uut/ready_in_dds -add wave -noupdate -expand -group DDS /l0_dds_writer_test5_afk/uut/valid_in_dds -add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_writer_test5_afk/uut/data_in_dds -add wave -noupdate -expand -group DDS /l0_dds_writer_test5_afk/uut/last_word_in_dds -add wave -noupdate -expand -group DDS /l0_dds_writer_test5_afk/uut/ready_out_dds -add wave -noupdate -expand -group DDS /l0_dds_writer_test5_afk/uut/valid_out_dds -add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_writer_test5_afk/uut/data_out_dds -add wave -noupdate -expand -group DDS /l0_dds_writer_test5_afk/uut/last_word_out_dds -add wave -noupdate -divider {MAIN FSM} -add wave -noupdate /l0_dds_writer_test5_afk/uut/idle_sig -add wave -noupdate /l0_dds_writer_test5_afk/uut/stage -add wave -noupdate /l0_dds_writer_test5_afk/uut/stage_next -add wave -noupdate /l0_dds_writer_test5_afk/uut/cnt -add wave -noupdate -radix unsigned /l0_dds_writer_test5_afk/uut/global_seq_nr -add wave -noupdate -radix unsigned /l0_dds_writer_test5_afk/uut/global_sample_cnt -add wave -noupdate -radix unsigned /l0_dds_writer_test5_afk/uut/global_ack_cnt -add wave -noupdate -radix unsigned /l0_dds_writer_test5_afk/uut/stale_inst_cnt -add wave -noupdate /l0_dds_writer_test5_afk/uut/remove_oldest_inst_sample -add wave -noupdate /l0_dds_writer_test5_afk/uut/remove_oldest_sample -add wave -noupdate /l0_dds_writer_test5_afk/uut/remove_ack_sample -add wave -noupdate -radix unsigned /l0_dds_writer_test5_afk/uut/lifespan -add wave -noupdate -divider MEMORY -add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test5_afk/uut/sample_abort_read -add wave -noupdate -group {SAMPLE MEM} -radix unsigned -childformat {{/l0_dds_writer_test5_afk/uut/sample_mem_ctrl_inst/addr(5) -radix unsigned} {/l0_dds_writer_test5_afk/uut/sample_mem_ctrl_inst/addr(4) -radix unsigned} {/l0_dds_writer_test5_afk/uut/sample_mem_ctrl_inst/addr(3) -radix unsigned} {/l0_dds_writer_test5_afk/uut/sample_mem_ctrl_inst/addr(2) -radix unsigned} {/l0_dds_writer_test5_afk/uut/sample_mem_ctrl_inst/addr(1) -radix unsigned} {/l0_dds_writer_test5_afk/uut/sample_mem_ctrl_inst/addr(0) -radix unsigned}} -subitemconfig {/l0_dds_writer_test5_afk/uut/sample_mem_ctrl_inst/addr(5) {-height 15 -radix unsigned} /l0_dds_writer_test5_afk/uut/sample_mem_ctrl_inst/addr(4) {-height 15 -radix unsigned} /l0_dds_writer_test5_afk/uut/sample_mem_ctrl_inst/addr(3) {-height 15 -radix unsigned} /l0_dds_writer_test5_afk/uut/sample_mem_ctrl_inst/addr(2) {-height 15 -radix unsigned} /l0_dds_writer_test5_afk/uut/sample_mem_ctrl_inst/addr(1) {-height 15 -radix unsigned} /l0_dds_writer_test5_afk/uut/sample_mem_ctrl_inst/addr(0) {-height 15 -radix unsigned}} /l0_dds_writer_test5_afk/uut/sample_mem_ctrl_inst/addr -add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test5_afk/uut/sample_mem_ctrl_inst/read -add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test5_afk/uut/sample_mem_ctrl_inst/ready_in -add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test5_afk/uut/sample_mem_ctrl_inst/valid_in -add wave -noupdate -group {SAMPLE MEM} -radix hexadecimal /l0_dds_writer_test5_afk/uut/sample_mem_ctrl_inst/data_in -add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test5_afk/uut/sample_mem_ctrl_inst/ready_out -add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test5_afk/uut/sample_mem_ctrl_inst/valid_out -add wave -noupdate -group {SAMPLE MEM} -radix hexadecimal /l0_dds_writer_test5_afk/uut/sample_mem_ctrl_inst/data_out -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test5_afk/uut/payload_abort_read -add wave -noupdate -group {PAYLOAD MEM} -radix unsigned /l0_dds_writer_test5_afk/uut/payload_mem_ctrl_inst/addr -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test5_afk/uut/payload_mem_ctrl_inst/read -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test5_afk/uut/payload_mem_ctrl_inst/ready_in -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test5_afk/uut/payload_mem_ctrl_inst/valid_in -add wave -noupdate -group {PAYLOAD MEM} -radix hexadecimal /l0_dds_writer_test5_afk/uut/payload_mem_ctrl_inst/data_in -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test5_afk/uut/payload_mem_ctrl_inst/ready_out -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test5_afk/uut/payload_mem_ctrl_inst/valid_out -add wave -noupdate -group {PAYLOAD MEM} -radix hexadecimal /l0_dds_writer_test5_afk/uut/payload_mem_ctrl_inst/data_out -add wave -noupdate /l0_dds_writer_test5_afk/uut/inst_op_start -add wave -noupdate /l0_dds_writer_test5_afk/uut/inst_opcode -add wave -noupdate /l0_dds_writer_test5_afk/uut/inst_op_done -add wave -noupdate /l0_dds_writer_test5_afk/uut/inst_stage -add wave -noupdate /l0_dds_writer_test5_afk/uut/inst_stage_next -add wave -noupdate /l0_dds_writer_test5_afk/uut/inst_cnt -add wave -noupdate -radix unsigned /l0_dds_writer_test5_afk/uut/inst_addr_base -add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test5_afk/uut/inst_abort_read -add wave -noupdate -group {INSTANCE MEM} -radix unsigned /l0_dds_writer_test5_afk/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/addr -add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test5_afk/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/read -add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test5_afk/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/ready_in -add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test5_afk/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/valid_in -add wave -noupdate -group {INSTANCE MEM} -radix hexadecimal /l0_dds_writer_test5_afk/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/data_in -add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test5_afk/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/ready_out -add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test5_afk/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/valid_out -add wave -noupdate -group {INSTANCE MEM} -radix hexadecimal /l0_dds_writer_test5_afk/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/data_out -add wave -noupdate -childformat {{/l0_dds_writer_test5_afk/uut/inst_data.key_hash -radix hexadecimal} {/l0_dds_writer_test5_afk/uut/inst_data.status_info -radix binary} {/l0_dds_writer_test5_afk/uut/inst_data.sample_cnt -radix unsigned} {/l0_dds_writer_test5_afk/uut/inst_data.ack_cnt -radix unsigned}} -expand -subitemconfig {/l0_dds_writer_test5_afk/uut/inst_data.key_hash {-height 15 -radix hexadecimal} /l0_dds_writer_test5_afk/uut/inst_data.status_info {-height 15 -radix binary} /l0_dds_writer_test5_afk/uut/inst_data.sample_cnt {-height 15 -radix unsigned} /l0_dds_writer_test5_afk/uut/inst_data.ack_cnt {-height 15 -radix unsigned}} /l0_dds_writer_test5_afk/uut/inst_data -add wave -noupdate -radix unsigned /l0_dds_writer_test5_afk/uut/inst_next_addr_base -add wave -noupdate -radix unsigned /l0_dds_writer_test5_afk/uut/inst_prev_addr_base -add wave -noupdate -divider {KEY HOLDER} -add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test5_afk/uut/start_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test5_afk/uut/opcode_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test5_afk/uut/ack_kh -add wave -noupdate -group {KEY HOLDER} -radix hexadecimal /l0_dds_writer_test5_afk/uut/data_in_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test5_afk/uut/valid_in_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test5_afk/uut/ready_in_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test5_afk/uut/last_word_in_kh -add wave -noupdate -group {KEY HOLDER} -radix hexadecimal /l0_dds_writer_test5_afk/uut/data_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test5_afk/uut/valid_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test5_afk/uut/ready_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test5_afk/uut/last_word_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test5_afk/uut/abort_kh -add wave -noupdate -divider POINTERS -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test5_afk/uut/empty_sample_list_head -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test5_afk/uut/empty_sample_list_tail -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test5_afk/uut/empty_payload_list_head -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test5_afk/uut/oldest_sample -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test5_afk/uut/newest_sample -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test5_afk/uut/inst_empty_head -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test5_afk/uut/inst_occupied_head -add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test5_afk/uut/cur_sample -add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test5_afk/uut/prev_sample -add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test5_afk/uut/next_sample -add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test5_afk/uut/cur_payload -add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test5_afk/uut/next_payload -add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test5_afk/uut/cur_inst -add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test5_afk/uut/next_inst -add wave -noupdate -divider TESTBENCH -add wave -noupdate -group TESTBENCH /l0_dds_writer_test5_afk/stim_start -add wave -noupdate -group TESTBENCH /l0_dds_writer_test5_afk/stim_stage -add wave -noupdate -group TESTBENCH /l0_dds_writer_test5_afk/stim_cnt -add wave -noupdate -group TESTBENCH /l0_dds_writer_test5_afk/stim_done -add wave -noupdate -group TESTBENCH /l0_dds_writer_test5_afk/ref_start -add wave -noupdate -group TESTBENCH /l0_dds_writer_test5_afk/ref_stage -add wave -noupdate -group TESTBENCH /l0_dds_writer_test5_afk/ref_cnt -add wave -noupdate -group TESTBENCH /l0_dds_writer_test5_afk/ref_done -add wave -noupdate -group TESTBENCH /l0_dds_writer_test5_afk/kh_cnt -add wave -noupdate -group TESTBENCH /l0_dds_writer_test5_afk/kh_stage -add wave -noupdate -divider MISC -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {3322369 ps} 0} -quietly wave cursor active 1 -configure wave -namecolwidth 187 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -configure wave -timelineunits ns -update -WaveRestoreZoom {2626024 ps} {3626665 ps} diff --git a/src/Tests/Level_0/L0_dds_writer_test1.vhd b/src/Tests/Level_0/L0_dds_writer_test1.vhd new file mode 100644 index 0000000..a6162eb --- /dev/null +++ b/src/Tests/Level_0/L0_dds_writer_test1.vhd @@ -0,0 +1,6528 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library osvvm; -- Utility Library +context osvvm.OsvvmContext; + +use work.rtps_package.all; +use work.user_config.all; +use work.rtps_config_package.all; +use work.rtps_test_package.all; + +entity L0_dds_writer_test1 is +end entity; + +-- This testbench tests the General Operation of the DDS Writer. It tests the correctness of the RTPS +-- GET_MIN_SN, GET_MAX_SN, GET_CACHE_CHANGE, REMOVE_CACHE_CHANGE, ACK_CACHE_CHANGE, and NACK_CACHE_CHANGE Operations and the +-- DDS REGISTER_INSTANCE, UNREGISTER_INSTANCE, WRITE, DISPOSE, and LOOKUP_INSTANCE Operations. +-- More specifically the testbench covers following tests: +-- TEST: GET_MIN_SN/GET_MAX_SN ON EMPTY +-- TEST: GET_MIN_SN/GET_MAX_SN ON 1 SAMPLE +-- TEST: GET_MIN_SN/GET_MAX_SN ON >1 SAMPLE +-- TEST: ADD SAMPLE WITH KEY_HASH [UNKNOWN INSTANCE] +-- TEST: ADD SAMPLE WITH KEY_HASH [KNOWN INSTANCE] +-- TEST: ADD SAMPLE WITH HANDLE_NIL [UNKNOWN INSTANCE] +-- TEST: ADD SAMPLE WITH HANDLE_NIL [KNOWN INSTANCE] +-- TEST: NORMAL WRITE +-- TEST: WRITE ON PAYLOAD MEMORY FULL [WITHOUT ACKed SAMPLES] +-- TEST: WRITE ON PAYLOAD MEMORY FULL [WITH ACKed SAMPLES] +-- TEST: WRITE ON DISPOSED INSTANCE +-- TEST: WRITE ON UNREGISTERED INSTANCE +-- TEST: WRITE ALIGNED PAYLOAD +-- TEST: WRITE UNALIGNED PAYLOAD [>1 SLOT] +-- TEST: WRITE UNALIGNED PAYLOAD [<1 SLOT] +-- TEST: NORMAL REGISTER +-- TEST: REGISTER INSTANCE [KNOWN INSTANCE] +-- TEST: REGISTER INSTANCE ON MAX_INSTANCES [UNKNOWN INSTANCE, WITHOUT STALE INSTANCE] +-- TEST: REGISTER INSTANCE ON MAX_INSTANCES [UNKNOWN INSTANCE, WITH STALE INSTANCE] +-- TEST: REGISTER ON UNREGISTERED INSTANCE +-- TEST: NORMAL DISPOSE +-- TEST: DISPOSE ON PAYLOAD MEMORY FULL [WITHOUT ACKed SAMPLES] +-- TEST: DISPOSE ON PAYLOAD MEMORY FULL [WITH ACKed SAMPLES] +-- TEST: DISPOSE ON UNREGISTERED INSTANCE +-- TEST: GET_CACHE_CHANGE [UNKNOWN SN] +-- TEST: GET_CACHE_CHANGE [KNOWN SN, ALIGNED PAYLOAD] +-- TEST: GET_CACHE_CHANGE [KNOWN SN, UNALIGNED PAYLOAD, >1 SLOT] +-- TEST: GET_CACHE_CHANGE [KNOWN SN, UNALIGNED PAYLOAD, <1 SLOT] +-- TEST: NORMAL ACK_CACHE_CHANGE +-- TEST: ACK_CACHE_CHANGE [ALREADY ACKed SN] +-- TEST: ACK_CACHE_CHANGE [UNKNOWN SN] +-- TEST: NORMAL NACK_CACHE_CHANGE +-- TEST: REMOVE_CACHE_CHANGE [UNKNOWN SN] +-- TEST: REMOVE_CACHE_CHANGE [KNOWN SN] +-- TEST: NORMAL UNREGISTER +-- TEST: UNREGISTER INSTANCE ON PAYLOAD MEMORY FULL [WITHOUT ACKed SAMPLES] +-- TEST: UNREGISTER INSTANCE ON PAYLOAD MEMORY FULL [WITH ACKed SAMPLES] +-- TEST: UNREGISTER ON DISPOSED INSTANCE +-- TEST: UNREGISTER UNKNOWN INSTANCE +-- TEST: REMOVE STALE INSTANCE WITH 0 SAMPLES +-- TEST: REMOVE STALE INSTANCE WITH 1 SAMPLES +-- TEST: REMOVE STALE INSTANCE WITH >1 SAMPLES +-- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKNOWN INSTANCE, WITH STALE INSTANCE] +-- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKNOWN INSTANCE, WITHOUT STALE INSTANCES] +-- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKNOWN INSTANCE, WITH FULLY ACKed INSTANCE, WITHOUT STALE INSTANCE] +-- TEST: ADD SAMPLE ON MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE, WITHOUT ACKed SAMPLES] +-- TEST: ADD SAMPLE ON MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE, WITH ACKed SAMPLES, WITHOUT ACKed INSTANCE SAMPLES] +-- TEST: ADD SAMPLE ON MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE, WITH ACKed INSTANCE SAMPLE] +-- TEST: ADD SAMPLE ON MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE, WITH ACKed INSTANCE SAMPLES(>1)] +-- TEST: ADD SAMPLE ON MAX_SAMPLES [KNOWN INSTANCE,WITHOUT ACKed SAMPLES] +-- TEST: ADD SAMPLE ON MAX_SAMPLES [KNOWN INSTANCE,WITH ACKed SAMPLE] +-- TEST: ADD SAMPLE ON MAX_SAMPLES [KNOWN INSTANCE,WITH ACKed SAMPLES (>1)] +-- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE,WITHOUT ACKed SAMPLES] +-- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE,WITH ACKed SAMPLES, WITHOUT ACKed INSTANCE SAMPLES] +-- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE,WITH ACKed INSTANCE SAMPLES] +-- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE,WITH STALE INSTANCE, WITHOUT ACKed SAMPLE] +-- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE,WITHOUT STALE INSTANCES,WITHOUT ACKed SAMPLES] +-- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE,WITHOUT STALE INSTANCE, WITH ACKed SAMPLE] +-- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE,WITH STALE INSTANCE (>0 SAMPLES)] +-- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE,WITH STALE INSTANCE (>0 SAMPLES), OLDEST SAMPLE ACKed AND /= STALE INSTANCE] (Induce Double Removal) +-- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE,WITH STALE INSTANCE, WITH ACKed SAMPLE] +-- TEST: ADD SAMPLE ON PAYLOAD FULL & MAX_INSTANCES [UNKNOWN INSTANCE,WITH ACKed SAMPLES,WITH STALE INSTANCE (>= 1 SAMPLE)] (Induce Double Removal) +-- TEST: ADD SAMPLE BIGGER THAN AVAILABLE MEMORY SPACE [WITH ACKed SAMPLES] +-- TEST: INSTANCE LOOKUP [KNOWN INSTANCE] +-- TEST: INSTANCE LOOKUP [UNKNOWN INSTANCE] + +architecture testbench of L0_dds_writer_test1 is + + -- *CONSTANT DECLARATION* + constant MAX_REMOTE_ENDPOINTS : natural := 3; + constant NUM_WRITERS : natural := 4; + + impure function gen_test_config return CONFIG_ARRAY_TYPE is + variable ret : CONFIG_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => DEFAULT_WRITER_CONFIG); + begin + -- aik + ret(0).HISTORY_QOS := KEEP_ALL_HISTORY_QOS; + ret(0).DEADLINE_QOS := DURATION_INFINITE; + ret(0).LIFESPAN_QOS := DURATION_INFINITE; + ret(0).LEASE_DURATION := DURATION_INFINITE; + ret(0).WITH_KEY := TRUE; + ret(0).MAX_SAMPLES := std_logic_vector(to_unsigned(4,CDR_LONG_WIDTH)); + ret(0).MAX_INSTANCES := std_logic_vector(to_unsigned(3,CDR_LONG_WIDTH)); + ret(0).MAX_SAMPLES_PER_INSTANCE := std_logic_vector(to_unsigned(2,CDR_LONG_WIDTH)); + ret(0).MAX_PAYLOAD_SIZE := 40; + -- ain + ret(1).HISTORY_QOS := KEEP_ALL_HISTORY_QOS; + ret(1).DEADLINE_QOS := DURATION_INFINITE; + ret(1).LIFESPAN_QOS := DURATION_INFINITE; + ret(1).LEASE_DURATION := DURATION_INFINITE; + ret(1).WITH_KEY := FALSE; + ret(1).MAX_SAMPLES := std_logic_vector(to_unsigned(4,CDR_LONG_WIDTH)); + ret(1).MAX_INSTANCES := std_logic_vector(to_unsigned(3,CDR_LONG_WIDTH)); + ret(1).MAX_SAMPLES_PER_INSTANCE := std_logic_vector(to_unsigned(4,CDR_LONG_WIDTH)); + ret(1).MAX_PAYLOAD_SIZE := 40; + -- lik + ret(2).HISTORY_QOS := KEEP_LAST_HISTORY_QOS; + ret(2).DEADLINE_QOS := DURATION_INFINITE; + ret(2).LIFESPAN_QOS := DURATION_INFINITE; + ret(2).LEASE_DURATION := DURATION_INFINITE; + ret(2).WITH_KEY := TRUE; + ret(2).MAX_SAMPLES := std_logic_vector(to_unsigned(4,CDR_LONG_WIDTH)); + ret(2).MAX_INSTANCES := std_logic_vector(to_unsigned(3,CDR_LONG_WIDTH)); + ret(2).MAX_SAMPLES_PER_INSTANCE := std_logic_vector(to_unsigned(2,CDR_LONG_WIDTH)); + ret(2).MAX_PAYLOAD_SIZE := 35; + -- afk + ret(3).HISTORY_QOS := KEEP_ALL_HISTORY_QOS; + ret(3).DEADLINE_QOS := DURATION_INFINITE; + ret(3).LIFESPAN_QOS := gen_duration(1,0); + ret(3).LEASE_DURATION := DURATION_INFINITE; + ret(3).WITH_KEY := TRUE; + ret(3).MAX_SAMPLES := std_logic_vector(to_unsigned(3,CDR_LONG_WIDTH)); + ret(3).MAX_INSTANCES := std_logic_vector(to_unsigned(3,CDR_LONG_WIDTH)); + ret(3).MAX_SAMPLES_PER_INSTANCE := std_logic_vector(to_unsigned(2,CDR_LONG_WIDTH)); + ret(3).MAX_PAYLOAD_SIZE := 40; + return ret; + end function; + constant TEST_CONFIG : CONFIG_ARRAY_TYPE := gen_test_config; + + -- *TYPE DECLARATION* + type DDS_STAGE_TYPE is (IDLE, START, PUSH, DONE); + type RTPS_STAGE_TYPE is (IDLE, START, DONE, CHECK); + type EMPTY_HEAD_SIG_ARRAY_TYPE is array (0 to NUM_WRITERS-1) of natural; + + -- *SIGNAL DECLARATION* + signal clk : std_logic := '0'; + signal reset : std_logic := '1'; + signal check_time : TIME_TYPE := TIME_ZERO; + signal start_rtps, start_dds, ack_rtps, ack_dds, done_rtps, done_dds, w_map : std_logic_vector(0 to NUM_WRITERS-1) := (others => '0'); + signal opcode_rtps : HISTORY_CACHE_OPCODE_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => NOP); + signal opcode_dds : DDS_WRITER_OPCODE_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => NOP); + signal ret_rtps : HISTORY_CACHE_RESPONSE_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => ERROR); + signal seq_nr_rtps, cc_seq_nr : SEQUENCENUMBER_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => SEQUENCENUMBER_UNKNOWN); + signal ready_out_rtps, valid_out_rtps, last_word_out_rtps : std_logic_vector(0 to NUM_WRITERS-1) := (others => '0'); + signal ready_in_dds, ready_out_dds, valid_in_dds, valid_out_dds, last_word_in_dds, last_word_out_dds : std_logic_vector(0 to NUM_WRITERS-1) := (others => '0'); + signal data_out_rtps, data_in_dds, data_out_dds : WORD_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => (others => '0')); + signal get_data_rtps, liveliness_assertion, data_available : std_logic_vector(0 to NUM_WRITERS-1) := (others => '0'); + signal cc_source_timestamp, source_ts_dds : TIME_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => TIME_INVALID); + signal cc_kind : CACHE_CHANGE_KIND_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => ALIVE); + signal cc_instance_handle, instance_handle_in_dds, instance_handle_out_dds : INSTANCE_HANDLE_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => HANDLE_NIL); + signal max_wait_dds : DURATION_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => DURATION_INFINITE); + signal return_code_dds : RETURN_CODE_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => (others => '0')); + signal status : STATUS_KIND_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => (others => '0')); + + signal ind : natural := 0; + signal dds_start, dds_done, rtps_start, rtps_done : std_logic := '0'; + signal dds_cnt, rtps_cnt : natural := 0; + signal dds_stage : DDS_STAGE_TYPE := IDLE; + signal rtps_stage : RTPS_STAGE_TYPE := IDLE; + shared variable dds : DDS_WRITER_TEST_TYPE := DEFAULT_DDS_WRITER_TEST; + shared variable rtps : RTPS_WRITER_TEST_TYPE := DEFAULT_RTPS_WRITER_TEST; + signal inst_id, kind_id, sn_id, ts_id, data_id, ret_id, ih_id : AlertLogIDType; + + -- *FUNCTION DECLARATION* + function extract_key_hash (payload : TEST_PACKET_TYPE) return INSTANCE_HANDLE_TYPE is + variable ret : INSTANCE_HANDLE_TYPE := HANDLE_NIL; + begin + for i in 0 to 3 loop + ret(i) := not payload.data(i); + end loop; + + return ret; + end function; + + function gen_sn(input : natural) return SEQUENCENUMBER_TYPE is + variable ret : SEQUENCENUMBER_TYPE; + begin + ret(0) := (others => '0'); + ret(1) := unsigned(int(input, WORD_WIDTH)); + return ret; + end function; + + procedure wait_on_sig(signal sig : std_logic) is + begin + if (sig /= '1') then + wait on sig until sig = '1'; + end if; + end procedure; + +begin + + -- Unit Under Test + uut : entity work.dds_writer(arch) + generic map( + NUM_WRITERS => NUM_WRITERS, + CONFIG_ARRAY => to_QUARTUS_CONFIG_ARRAY_TYPE(TEST_CONFIG) + ) + port map ( + clk => clk, + reset => reset, + time => check_time, + start_rtps => start_rtps, + opcode_rtps => opcode_rtps, + ack_rtps => ack_rtps, + done_rtps => done_rtps, + ret_rtps => ret_rtps, + seq_nr_rtps => seq_nr_rtps, + get_data_rtps => get_data_rtps, + data_out_rtps => data_out_rtps, + valid_out_rtps => valid_out_rtps, + ready_out_rtps => ready_out_rtps, + last_word_out_rtps => last_word_out_rtps, + liveliness_assertion => liveliness_assertion, + data_available => data_available, + cc_instance_handle => cc_instance_handle, + cc_kind => cc_kind, + cc_source_timestamp => cc_source_timestamp, + cc_seq_nr => cc_seq_nr, + start_dds => start_dds, + ack_dds => ack_dds, + opcode_dds => opcode_dds, + instance_handle_in_dds => instance_handle_in_dds, + source_ts_dds => source_ts_dds, + max_wait_dds => max_wait_dds, + done_dds => done_dds, + return_code_dds => return_code_dds, + instance_handle_out_dds => instance_handle_out_dds, + ready_in_dds => ready_in_dds, + valid_in_dds => valid_in_dds, + data_in_dds => data_in_dds, + last_word_in_dds => last_word_in_dds, + ready_out_dds => ready_out_dds, + valid_out_dds => valid_out_dds, + data_out_dds => data_out_dds, + last_word_out_dds => last_word_out_dds, + status => status + ); + + stimulus_prc : process + variable RV : RandomPType; + variable kh1, kh2, kh3, kh4 : INSTANCE_HANDLE_TYPE := HANDLE_NIL; + variable cc1, cc2, cc3, cc4, cc : CACHE_CHANGE_TYPE := DEFAULT_CACHE_CHANGE; + + alias idle_sig is <>; + alias inst_op_done is <>; + alias empty_inst_head is <>; + alias empty_sample_head is <>; + alias empty_payload_head is <>; + + impure function gen_payload(key_hash : INSTANCE_HANDLE_TYPE; len : natural) return TEST_PACKET_TYPE is + variable ret : TEST_PACKET_TYPE := EMPTY_TEST_PACKET; + begin + assert (len >= 4) report "Payload length has to be at least 16 Bytes long" severity FAILURE; + + for i in 0 to len-1 loop + if (i < 4) then + -- NOTE: Beginning of payload is negated key to allow deterministic Key Hash generation from the kh_prc + ret.data(ret.length) := not key_hash(i); + else + ret.data(ret.length) := RV.RandSlv(WORD_WIDTH); + end if; + ret.length := ret.length + 1; + end loop; + ret.last(ret.length-1) := '1'; + + return ret; + end function; + + impure function gen_key_hash return KEY_HASH_TYPE is + variable ret : KEY_HASH_TYPE := KEY_HASH_NIL; + begin + for i in 0 to KEY_HASH_TYPE'length-1 loop + ret(i) := RV.RandSlv(WORD_WIDTH); + end loop; + return ret; + end function; + + procedure start_dds is + begin + dds_start <= '1'; + wait until rising_edge(clk); + dds_start <= '0'; + wait until rising_edge(clk); + end procedure; + + procedure start_rtps is + begin + rtps_start <= '1'; + wait until rising_edge(clk); + rtps_start <= '0'; + wait until rising_edge(clk); + end procedure; + + procedure wait_on_completion is + begin + if (rtps_done /= '1' or dds_done /= '1') then + wait until rtps_done = '1' and dds_done = '1'; + end if; + end procedure; + + -- NOTE: This procedure waits until the idle_sig is high for at least + -- two consecutive clock cycles. + procedure wait_on_idle is + variable first : boolean := TRUE; + begin + loop + if (idle_sig /= '1') then + wait until idle_sig = '1'; + elsif (not first) then + exit; + end if; + wait until rising_edge(clk); + wait until rising_edge(clk); + first := FALSE; + end loop; + wait_on_sig(inst_op_done); + end procedure; + + begin + SetAlertLogName("L0_dds_writer_test1 - General"); + SetAlertEnable(FAILURE, TRUE); + SetAlertEnable(ERROR, TRUE); + SetAlertEnable(WARNING, TRUE); + SetLogEnable(DEBUG, FALSE); + SetLogEnable(PASSED, FALSE); + SetLogEnable(INFO, TRUE); + RV.InitSeed(RV'instance_name); + inst_id <= GetAlertLogID("Instance", ALERTLOG_BASE_ID); + kind_id <= GetAlertLogID("Cache Change Kind", ALERTLOG_BASE_ID); + sn_id <= GetAlertLogID("SequenceNumber", ALERTLOG_BASE_ID); + ts_id <= GetAlertLogID("TimeStamp", ALERTLOG_BASE_ID); + ih_id <= GetAlertLogID("Instance Handle", ALERTLOG_BASE_ID); + data_id <= GetAlertLogID("Data Out", ALERTLOG_BASE_ID); + ret_id <= GetAlertLogID("Return Code", ALERTLOG_BASE_ID); + + -- Key Hashes + kh1 := gen_key_hash; + kh2 := gen_key_hash; + kh3 := gen_key_hash; + kh4 := gen_key_hash; + + Log("Initiating Test", INFO); + reset <= '1'; + wait until rising_edge(clk); + wait until rising_edge(clk); + reset <= '0'; + wait_on_idle; + + -- *WRITER 0 / WRITER 3* + Log("*WRITER 0 / WRITER 3*", INFO); + -- WRITER 0 + AlertIf(empty_sample_head(0) /= 0, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 0, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 0, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: -/0,11,22,33,44 + -- PAYLOAD MEMORY: -/0,11,22,33,44 + -- INSTANCE MEMORY: -/0,9,18 + -- WRITER 3 + AlertIf(empty_sample_head(3) /= 0, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(3) /= 0, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(3) /= 0, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: -/0,11,22,33 + -- PAYLOAD MEMORY: -/0,11,22,33 + -- INSTANCE MEMORY: -/0,9,18 + + + -- TEST: GET_MIN_SN/GET_MAX_SN ON EMPTY + + Log("W0,W3: RTPS Operation GET_MIN_SN", INFO); + Log("W0,W3: Expected SEQUENCENUMBER_UNKNOWN", DEBUG); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_MIN_SN; + rtps.cc.seq_nr := SEQUENCENUMBER_UNKNOWN; + -- WRITER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- WRITER 3 + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W0,W3: RTPS Operation GET_MAX_SN", INFO); + Log("W0,W3: Expected SEQUENCENUMBER_UNKNOWN", DEBUG); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_MAX_SN; + rtps.cc.seq_nr := SEQUENCENUMBER_UNKNOWN; + -- WRITE 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- WRITE 3 + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + -- TEST: WRITE ALIGNED PAYLOAD + -- TEST: NORMAL WRITE + -- TEST: ADD SAMPLE WITH KEY_HASH [UNKNOWN INSTANCE] + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh1; + cc.payload := gen_payload(kh1,10); + cc.seq_nr := gen_sn(1); + cc.src_timestamp := gen_duration(1,0); + + Log("W0,W3: DDS Operation WRITE [TS 1s, Instance 1]", INFO); + Log("W0,W3: REJECTED [Instance not Registered]", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := WRITE; + dds.cc := cc; + dds.ret_code := RETCODE_BAD_PARAMETER; + -- WRITER 0 + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- WRITER 3 + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + + -- TEST: ADD SAMPLE WITH HANDLE_NIL [UNKNOWN INSTANCE] + + Log("W0,W3: DDS Operation WRITE [TS 1s, Instance 1, HANDLE_NIL]", INFO); + Log("W0,W3: ACCEPTED", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := WRITE; + dds.cc := cc; + dds.cc.instance:= HANDLE_NIL; + dds.ret_code := RETCODE_OK; + -- WRITER 0 + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- WRITER 3 + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + cc1 := cc; + -- WRITER 0 + AlertIf(empty_sample_head(0) /= 11, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 11, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 9, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I1S1)/11,22,33,44 + -- PAYLOAD MEMORY: 0(I1S1)/11,22,33,44 + -- INSTANCE MEMORY: 0(I1)/9,18 + -- WRITER 3 + AlertIf(empty_sample_head(3) /= 11, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(3) /= 11, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(3) /= 9, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I1S1)/11,22,33 + -- PAYLOAD MEMORY: 0(I1S1)/11,22,33 + -- INSTANCE MEMORY: 0(I1)/9,18 + + -- TEST: GET_MIN_SN/GET_MAX_SN ON 1 SAMPLE + + Log("W0,W3: RTPS Operation GET_MIN_SN", INFO); + Log("W0,W3: Expected SN 1", DEBUG); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_MIN_SN; + rtps.cc.seq_nr := gen_sn(1); + -- WRITER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- WRITER 3 + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W0,W3: RTPS Operation GET_MAX_SN", INFO); + Log("W0,W3: Expected SN 1", DEBUG); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_MAX_SN; + rtps.cc.seq_nr := gen_sn(1); + -- WRITER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- WRITER 3 + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + -- TEST: WRITE UNALIGNED PAYLOAD [>1 SLOT] + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh2; + cc.payload := gen_payload(kh2,12); + cc.seq_nr := gen_sn(2); + cc.src_timestamp := gen_duration(2,0); + + Log("W0,W3: DDS Operation WRITE [TS 2s, Instance 2, Unaligned Payload (2 Slots)]", INFO); + Log("W0,W3: REJECTED [Instance not Registered]", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := WRITE; + dds.cc := cc; + dds.ret_code := RETCODE_BAD_PARAMETER; + -- WRITER 0 + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- WRITER 3 + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + + -- TEST: NORMAL REGISTER + + Log("W0,W3: DDS Operation REGISTER_INSTANCE 2", INFO); + Log("W0,W3: ACCEPTED", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := REGISTER_INSTANCE; + dds.cc := cc; + dds.ret_code := RETCODE_OK; + -- WRITER 0 + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- WRITER 3 + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- WRITER 0 + AlertIf(empty_sample_head(0) /= 11, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 11, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 18, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I1S1)/11,22,33,44 + -- PAYLOAD MEMORY: 0(I1S1)/11,22,33,44 + -- INSTANCE MEMORY: 9(I2),0(I1)/18 + -- WRITER 3 + AlertIf(empty_sample_head(3) /= 11, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(3) /= 11, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(3) /= 18, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I1S1)/11,22,33 + -- PAYLOAD MEMORY: 0(I1S1)/11,22,33 + -- INSTANCE MEMORY: 9(I2),0(I1)/18 + + -- TEST: ADD SAMPLE WITH KEY_HASH [KNOWN INSTANCE] + + Log("W0,W3: DDS Operation WRITE [TS 2s, Instance 2, Unaligned Payload (2 Slots)]", INFO); + Log("W0,W3: ACCEPTED", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := WRITE; + dds.cc := cc; + dds.ret_code := RETCODE_OK; + -- WRITER 0 + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- WRITER 3 + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + cc2 := cc; + -- WRITER 0 + AlertIf(empty_sample_head(0) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 33, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 18, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I1S1),11(I2S2)/22,33,44 + -- PAYLOAD MEMORY: 0(I1S1),11(I2S2),22(I2S2)/33,44 + -- INSTANCE MEMORY: 9(I2),0(I1)/18 + -- WRITER 3 + AlertIf(empty_sample_head(3) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(3) /= 33, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(3) /= 18, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I1S1),11(I2S2)/22,33 + -- PAYLOAD MEMORY: 0(I1S1),11(I2S2),22(I2S2)/33 + -- INSTANCE MEMORY: 9(I2),0(I1)/18 + + -- TEST: ADD SAMPLE WITH HANDLE_NIL [KNOWN INSTANCE] + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh1; + cc.payload := gen_payload(kh1,15); + cc.seq_nr := gen_sn(3); + cc.src_timestamp := gen_duration(3,0); + + Log("W0,W3: DDS Operation WRITE [TS 3s, Instance 1, Unaligned Payload (2 Slots)]", INFO); + Log("W0: ACCEPTED", DEBUG); + Log("W3: REJECTED [Payload memory Full]", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := WRITE; + dds.cc := cc; + dds.cc.instance:= HANDLE_NIL; + -- WRITER 0 + dds.ret_code := RETCODE_OK; + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- WRITER 3 + dds.ret_code := RETCODE_OUT_OF_RESOURCES; + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + cc3 := cc; + -- WRITER 0 + AlertIf(empty_sample_head(0) /= 33, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 54, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 18, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I1S1),11(I2S2),22(I1S3)/33,44 + -- PAYLOAD MEMORY: 0(I1S1),11(I2S2),22(I2S2),33(I1S3),44(I1S3)/- + -- INSTANCE MEMORY: 9(I2),0(I1)/18 + -- WRITER 3 + AlertIf(empty_sample_head(3) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(3) /= 33, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(3) /= 18, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I1S1),11(I2S2)/22,33 + -- PAYLOAD MEMORY: 0(I1S1),11(I2S2),22(I2S2)/33 + -- INSTANCE MEMORY: 9(I2),0(I1)/18 + + -- TEST: GET_CACHE_CHANGE [UNKNOWN SN] + + Log("W0,W3: RTPS Operation GET_CACHE_CHANGE SN 4", INFO); + Log("W0,W3: INVALID", DEBUG); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_CACHE_CHANGE; + rtps.cc.seq_nr := gen_sn(4); + rtps.ret_code := INVALID; + -- WRITER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- WRITER 3 + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + -- TEST: GET_CACHE_CHANGE [KNOWN SN, ALIGNED PAYLOAD] + + Log("W0,W3: RTPS Operation GET_CACHE_CHANGE SN 1", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_CACHE_CHANGE; + rtps.cc := cc1; + -- WRITER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- WRITER 3 + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + -- TEST: GET_CACHE_CHANGE [KNOWN SN, UNALIGNED PAYLOAD, >1 SLOT] + + Log("W0,W3: RTPS Operation GET_CACHE_CHANGE SN 2", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_CACHE_CHANGE; + rtps.cc := cc2; + -- WRITER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- WRITER 3 + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W0,W3: RTPS Operation GET_CACHE_CHANGE SN 3", INFO); + Log("W3: INVALID", DEBUG); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_CACHE_CHANGE; + rtps.cc := cc3; + -- WRITER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- WRITER 3 + rtps.ret_code := INVALID; + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + -- TEST: WRITE UNALIGNED PAYLOAD [<1 SLOT] + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh3; + cc.payload := gen_payload(kh3,8); + cc.seq_nr := gen_sn(4); + cc.src_timestamp := gen_duration(4,0); + + -- TEST: WRITE ON PAYLOAD MEMORY FULL [WITHOUT ACKed SAMPLES] + + Log("W0,W3: DDS Operation WRITE [TS 4s, Instance 3, HANDLE_NIL, Unaligned Payload (1 Slot)]", INFO); + Log("W0: REJECTED [Payload Memory Full]", DEBUG); + Log("W3: ACCEPTED", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := WRITE; + dds.cc := cc; + dds.cc.instance:= HANDLE_NIL; + -- WRITER 0 + dds.ret_code := RETCODE_OUT_OF_RESOURCES; + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- WRITER 3 + dds.ret_code := RETCODE_OK; + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- WRITER 3 + AlertIf(empty_sample_head(3) /= 33, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(3) /= 54, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(3) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I1S1),11(I2S2),22(I3S3)/33 + -- PAYLOAD MEMORY: 0(I1S1),11(I2S2),22(I2S2),33(I3S3)/- + -- INSTANCE MEMORY: 18(I3),9(I2),0(I1)/- + + -- TEST: REMOVE_CACHE_CHANGE [UNKNOWN SN] + + Log("W0,W3: RTPS Operation REMOVE_CACHE_CHANGE SN 5", INFO); + Log("W0,W3: INVALID", DEBUG); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := REMOVE_CACHE_CHANGE; + rtps.cc.seq_nr := gen_sn(5); + rtps.ret_code := INVALID; + -- WRITER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- WRITER 3 + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + -- TEST: REMOVE_CACHE_CHANGE [KNOWN SN] + + Log("W0,W3: RTPS Operation REMOVE_CACHE_CHANGE SN 2", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := REMOVE_CACHE_CHANGE; + rtps.cc.seq_nr := gen_sn(2); + -- WRITER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- WRITER 3 + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- WRITER 0 + AlertIf(empty_sample_head(0) /= 33, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 11, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 18, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I1S1),22(I1S3)/33,44,11 + -- PAYLOAD MEMORY: 0(I1S1),33(I1S3),44(I1S3)/11,22 + -- INSTANCE MEMORY: 9(I2),0(I1)/18 + -- WRITER 3 + AlertIf(empty_sample_head(3) /= 33, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(3) /= 11, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(3) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I1S1),22(I3S3)/33,11 + -- PAYLOAD MEMORY: 0(I1S1),33(I3S3)/11,22 + -- INSTANCE MEMORY: 18(I3),9(I2),0(I1)/- + + Log("W0: DDS Operation WRITE [TS 4s, Instance 3, HANDLE_NIL, Unaligned Payload (1 Slot)]", INFO); + Log("W0: ACCEPTED", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := WRITE; + dds.cc := cc; + dds.cc.instance:= HANDLE_NIL; + dds.ret_code := RETCODE_OK; + -- WRITER 0 + ind <= 0; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + cc2 := cc; + -- WRITER 0 + AlertIf(empty_sample_head(0) /= 44, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 22, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I1S1),22(I1S3),33(I3S4)/44,11 + -- PAYLOAD MEMORY: 0(I1S1),33(I1S3),44(I1S3),11(I3S4)/22 + -- INSTANCE MEMORY: 18(I3),9(I2),0(I1)/- + + -- TEST: GET_CACHE_CHANGE [KNOWN SN, UNALIGNED PAYLOAD, <1 SLOT] + + Log("W0,W3: RTPS Operation GET_CACHE_CHANGE SN 4", INFO); + Log("W3: INVALID", DEBUG); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_CACHE_CHANGE; + rtps.cc := cc2; + -- WRITER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- WRITER 3 + rtps.ret_code := INVALID; + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + -- TEST: REGISTER INSTANCE [KNOWN INSTANCE] + + Log("W0,W3: DDS Operation REGISTER_INSTANCE 3", INFO); + Log("W0,W3: No Change", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := REGISTER_INSTANCE; + dds.cc := cc2; + dds.ret_code := RETCODE_OK; + -- WRITER 0 + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- WRITER 3 + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + + -- TEST: NORMAL DISPOSE + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := TRUE; + cc.kind := NOT_ALIVE_DISPOSED; + cc.instance := kh1; + cc.payload := gen_payload(kh1,5); + cc.seq_nr := gen_sn(5); + cc.src_timestamp := gen_duration(5,0); + + -- TEST: ADD SAMPLE ON MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE, WITHOUT ACKed SAMPLES] + + Log("W0,W3: DDS Operation DISPOSE [TS 5s, Instance 1]", INFO); + Log("W0: REJECTED [MAX_SAMPLES_PER_INSTANCE Exceeded]", DEBUG); + Log("W3: ACCEPTED", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := DISPOSE; + dds.cc := cc; + -- WRITER 0 + dds.ret_code := RETCODE_OUT_OF_RESOURCES; + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- WRITER 3 + dds.ret_code := RETCODE_OK; + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- WRITER 3 + AlertIf(empty_sample_head(3) /= 11, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(3) /= 22, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(3) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I1S1),22(I3S3),33(I1S4)/11 + -- PAYLOAD MEMORY: 0(I1S1),33(I3S3),11(I1S4)/22 + -- INSTANCE MEMORY: 18(I3),9(I2),0(I1)/- + + -- TEST: NORMAL ACK_CACHE_CHANGE + + Log("W0,W3: RTPS Operation ACK_CACHE_CHANGE SN 4", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := ACK_CACHE_CHANGE; + rtps.cc.seq_nr := gen_sn(4); + -- WRITER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- WRITER 3 + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + -- TEST: ADD SAMPLE ON MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE, WITH ACKed SAMPLES, WITHOUT ACKed INSTANCE SAMPLES] + + Log("W0: DDS Operation DISPOSE [TS 5s, Instance 1]", INFO); + Log("W0: REJECTED [MAX_SAMPLES_PER_INSTANCE Exceeded]", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := DISPOSE; + dds.cc := cc; + dds.ret_code := RETCODE_OUT_OF_RESOURCES; + -- WRITER 0 + ind <= 0; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + + Log("W0,W3: RTPS Operation ACK_CACHE_CHANGE SN 1", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := ACK_CACHE_CHANGE; + rtps.cc.seq_nr := gen_sn(1); + -- WRITER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- WRITER 3 + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + -- TEST: ADD SAMPLE ON MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE, WITH ACKed INSTANCE SAMPLE] + + Log("W0: DDS Operation DISPOSE [TS 5s, Instance 1]", INFO); + Log("W0: ACCEPTED", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := DISPOSE; + dds.cc := cc; + dds.ret_code := RETCODE_OK; + -- WRITER 0 + ind <= 0; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + cc1 := cc; + -- WRITER 0 + AlertIf(empty_sample_head(0) /= 11, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 0, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 22(I1S3),33(I3S4),44(I1S5)/11,0 + -- PAYLOAD MEMORY: 33(I1S3),44(I1S3),11(I3S4),22(I1S5)/0 + -- INSTANCE MEMORY: 18(I3),9(I2),0(I1)/- + + -- VALIDATE STATE + -- TEST: GET_MIN_SN/GET_MAX_SN ON >1 SAMPLE + + Log("W0,W3: RTPS Operation GET_MIN_SN", INFO); + Log("W0: Expected SN 3", DEBUG); + Log("W3: Expected SN 1", DEBUG); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_MIN_SN; + -- WRITER 0 + rtps.cc.seq_nr := gen_sn(3); + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- WRITER 3 + rtps.cc.seq_nr := gen_sn(1); + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W0,W3: RTPS Operation GET_MAX_SN", INFO); + Log("W0: Expected SN 5", DEBUG); + Log("W3: Expected SN 4", DEBUG); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_MAX_SN; + -- WRITER 0 + rtps.cc.seq_nr := gen_sn(5); + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- WRITER 3 + rtps.cc.seq_nr := gen_sn(4); + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W0: RTPS Operation GET_CACHE_CHANGE SN 5", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_CACHE_CHANGE; + rtps.cc := cc1; + -- WRITER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W3: RTPS Operation GET_CACHE_CHANGE SN 4", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_CACHE_CHANGE; + rtps.cc := cc1; + -- WRITER 3 + rtps.cc.seq_nr := gen_sn(4); + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh4; + cc.payload := gen_payload(kh4,10); + cc.seq_nr := gen_sn(6); + cc.src_timestamp := gen_duration(6,0); + + -- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKNOWN INSTANCE, WITHOUT STALE INSTANCES] + + Log("W0,W3: DDS Operation WRITE [TS 6s, Instance 4, HANDLE_NIL, Aligned Payload]", INFO); + Log("W0,W3: REJECTED [MAX_INSTANCES exceeded]", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := WRITE; + dds.cc := cc; + dds.cc.instance:= HANDLE_NIL; + dds.ret_code := RETCODE_OUT_OF_RESOURCES; + -- WRITER 0 + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- WRITER 3 + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + + Log("W0,W3: RTPS Operation ACK_CACHE_CHANGE SN 3", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := ACK_CACHE_CHANGE; + rtps.cc.seq_nr := gen_sn(3); + -- WRITER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- WRITER 3 + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + -- TEST: ACK_CACHE_CHANGE [ALREADY ACKed SN] + + Log("W0,W3: RTPS Operation ACK_CACHE_CHANGE SN 4", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := ACK_CACHE_CHANGE; + rtps.cc.seq_nr := gen_sn(4); + -- WRITER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- WRITER 3 + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + -- TEST: ACK_CACHE_CHANGE [UNKNOWN SN] + + Log("W0,W3: RTPS Operation ACK_CACHE_CHANGE SN 5", INFO); + Log("W3: INVALID", DEBUG); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := ACK_CACHE_CHANGE; + rtps.cc.seq_nr := gen_sn(5); + -- WRITER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- WRITER 3 + rtps.ret_code := INVALID; + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + -- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKNOWN INSTANCE, WITH FULLY ACKed INSTANCE, WITHOUT STALE INSTANCE] + + Log("W0,W3: DDS Operation WRITE [TS 6s, Instance 4, HANDLE_NIL, Aligned Payload]", INFO); + Log("W0,W3: REJECTED [MAX_INSTANCES exceeded]", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := WRITE; + dds.cc := cc; + dds.cc.instance:= HANDLE_NIL; + dds.ret_code := RETCODE_OUT_OF_RESOURCES; + -- WRITER 0 + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- WRITER 3 + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + + -- TEST: NORMAL UNREGISTER + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := TRUE; + cc.kind := NOT_ALIVE_UNREGISTERED; + cc.instance := kh1; + cc.payload := gen_payload(kh1,5); + cc.seq_nr := gen_sn(6); + cc.src_timestamp := gen_duration(6,0); + + -- TEST: UNREGISTER ON DISPOSED INSTANCE + + Log("W0,W3: DDS Operation UNREGISTER_INSTANCE [TS 6s, Instance 1]", INFO); + Log("W0,W3: ACCEPTED", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := UNREGISTER_INSTANCE; + dds.cc := cc; + dds.ret_code := RETCODE_OK; + -- WRITER 0 + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- WRITER 3 + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + cc3 := cc; + -- WRITER 0 + AlertIf(empty_sample_head(0) /= 0, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 33, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 33(I3S4),44(I1S5),11(I1S6)/0,22 + -- PAYLOAD MEMORY: 11(I3S4),22(I1S5),0(I1S6)/33,44 + -- INSTANCE MEMORY: 18(I3),9(I2),0(I1)/- + -- WRITER 3 + AlertIf(empty_sample_head(3) /= 0, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(3) /= 0, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(3) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 22(I3S3),33(I1S4),11(I1S5)/0 + -- PAYLOAD MEMORY: 33(I3S3),11(I1S4),22(I1S5)/0 + -- INSTANCE MEMORY: 18(I3),9(I2),0(I1)/- + + -- VALIDATE STATE + + Log("W0,W3: RTPS Operation GET_MIN_SN", INFO); + Log("W0: Expected SN 4", DEBUG); + Log("W3: Expected SN 3", DEBUG); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_MIN_SN; + -- WRITER 0 + rtps.cc.seq_nr := gen_sn(4); + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- WRITER 3 + rtps.cc.seq_nr := gen_sn(3); + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W0,W3: RTPS Operation GET_MAX_SN", INFO); + Log("W0: Expected SN 6", DEBUG); + Log("W3: Expected SN 5", DEBUG); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_MAX_SN; + -- WRITER 0 + rtps.cc.seq_nr := gen_sn(6); + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- WRITER 3 + rtps.cc.seq_nr := gen_sn(5); + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W0,W3: RTPS Operation GET_CACHE_CHANGE SN 6", INFO); + Log("W3: INVALID", DEBUG); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_CACHE_CHANGE; + rtps.cc := cc3; + -- WRITER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- WRITER 3 + rtps.ret_code := INVALID; + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh4; + cc.payload := gen_payload(kh4,10); + cc.seq_nr := gen_sn(7); + cc.src_timestamp := gen_duration(7,0); + + Log("W0,W3: DDS Operation WRITE [TS 7s, Instance 4, HANDLE_NIL, Aligned Payload]", INFO); + Log("W0,W3: REJECTED [MAX_INSTANCES exceeded]", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := WRITE; + dds.cc := cc; + dds.cc.instance:= HANDLE_NIL; + dds.ret_code := RETCODE_OUT_OF_RESOURCES; + -- WRITER 0 + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- WRITE3R 3 + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + + Log("W0: RTPS Operation ACK_CACHE_CHANGE SN 6", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := ACK_CACHE_CHANGE; + rtps.cc.seq_nr := gen_sn(6); + -- WRITER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W3: RTPS Operation ACK_CACHE_CHANGE SN 5", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := ACK_CACHE_CHANGE; + rtps.cc.seq_nr := gen_sn(5); + -- WRITER 3 + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + -- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE,WITH STALE INSTANCE (>=1 SAMPLES), OLDEST SAMPLE ACKed AND /= STALE INSTANCE] (Induce Double Removal) + -- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKNOWN INSTANCE, WITH STALE INSTANCE] + -- TEST: REMOVE STALE INSTANCE WITH >1 SAMPLES + + Log("W0,W3: DDS Operation WRITE [TS 7s, Instance 4, HANDLE_NIL, Aligned Payload]", INFO); + Log("W0,W3: ACCEPTED", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := WRITE; + dds.cc := cc; + dds.cc.instance:= HANDLE_NIL; + dds.ret_code := RETCODE_OK; + -- WRITER 0 + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- WRITER 3 + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + cc1 := cc; + -- WRITER 0 + AlertIf(empty_sample_head(0) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 0, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 33(I3S4),0(I4S7)/22,44,11 + -- PAYLOAD MEMORY: 11(I3S4),33(I4S7)/0,22,44 + -- INSTANCE MEMORY: 0(I4),18(I3),9(I2)/- + -- WRITER 3 + AlertIf(empty_sample_head(3) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(3) /= 22, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(3) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I4S6)/22,33,11 + -- PAYLOAD MEMORY: 0(I4S6)/22,11,33 + -- INSTANCE MEMORY: 0(I4),18(I3),9(I2)/- + + Log("W0,W3: RTPS Operation GET_CACHE_CHANGE SN 5", INFO); + Log("W0,W3: INVALID", DEBUG); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_CACHE_CHANGE; + rtps.cc.seq_nr := gen_sn(5); + rtps.ret_code := INVALID; + -- WRITER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- WRITER 3 + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W0,W3: RTPS Operation GET_CACHE_CHANGE SN 6", INFO); + Log("W0: INVALID", DEBUG); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_CACHE_CHANGE; + rtps.cc := cc1; + rtps.cc.seq_nr := gen_sn(6); + -- WRITER 0 + rtps.ret_code := INVALID; + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- WRITER 3 + rtps.ret_code := OK; + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W0,W3: RTPS Operation GET_CACHE_CHANGE SN 7", INFO); + Log("W3: INVALID", DEBUG); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_CACHE_CHANGE; + rtps.cc := cc1; + -- WRITER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- WRITER 3 + rtps.ret_code := INVALID; + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh2; + cc.payload := gen_payload(kh2,15); + cc.seq_nr := gen_sn(8); + cc.src_timestamp := gen_duration(8,0); + + Log("W0,W3: DDS Operation WRITE [TS 8s, Instance 2, Unaligned Payload (2 Slot)]", INFO); + Log("W0,W3: ACCEPTED", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := WRITE; + dds.cc := cc; + dds.ret_code := RETCODE_OK; + -- WRITER 0 + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- WRITER 3 + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + cc3 := cc; + -- WRITER 0 + AlertIf(empty_sample_head(0) /= 44, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 33(I3S4),0(I4S7),22(I2S8)/44,11 + -- PAYLOAD MEMORY: 11(I3S4),33(I4S7),0(I2S8),22(I2S8)/44 + -- INSTANCE MEMORY: 0(I4),18(I3),9(I2)/- + -- WRITER 3 + AlertIf(empty_sample_head(3) /= 33, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(3) /= 33, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(3) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I4S6),22(I2S7)/33,11 + -- PAYLOAD MEMORY: 0(I4S6),22(I2S7),11(I2S7)/33 + -- INSTANCE MEMORY: 0(I4),18(I3),9(I2)/- + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh1; + cc.payload := gen_payload(kh1,10); + cc.seq_nr := gen_sn(9); + cc.src_timestamp := gen_duration(9,0); + + Log("W0,W3: DDS Operation WRITE [TS 9s, Instance 1, Aligned Payload]", INFO); + Log("W0,W3: REJECTED [Instance not Registered]", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := WRITE; + dds.cc := cc; + dds.ret_code := RETCODE_BAD_PARAMETER; + -- WRITER 0 + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- WRITER 3 + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + + -- TEST: REGISTER INSTANCE ON MAX_INSTANCES [UNKNOWN INSTANCE, WITHOUT STALE INSTANCE] + + Log("W0,W3: DDS Operation REGISTER_INSTANCE 1", INFO); + Log("W0,W3: REJECTED [MAX_INSTANCES exceeded]", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := REGISTER_INSTANCE; + dds.cc := cc; + dds.cc.instance:= HANDLE_NIL; + -- WRITER 0 + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- WRITER 3 + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := NOT_ALIVE_UNREGISTERED; + cc.instance := kh3; + cc.payload := gen_payload(kh3,5); + cc.seq_nr := gen_sn(9); + cc.src_timestamp := gen_duration(9,0); + + Log("W0,W3: DDS Operation UNREGISTER_INSTANCE [TS 9s, Instance 3]", INFO); + Log("W0,W3: ACCEPTED", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := UNREGISTER_INSTANCE; + dds.cc := cc; + dds.ret_code := RETCODE_OK; + -- WRITER 0 + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- WRITER 3 + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + cc4 := cc; + -- WRITER 0 + AlertIf(empty_sample_head(0) /= 11, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 54, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 33(I3S4),0(I4S7),22(I2S8),44(I3S9)/11 + -- PAYLOAD MEMORY: 11(I3S4),33(I4S7),0(I2S8),22(I2S8),44(I3S9)/- + -- INSTANCE MEMORY: 0(I4),18(I3),9(I2)/- + -- WRITER 3 + AlertIf(empty_sample_head(3) /= 11, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(3) /= 54, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(3) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I4S6),22(I2S7),33(I3S8)/11 + -- PAYLOAD MEMORY: 0(I4S6),22(I2S7),11(I2S7),33(I3S8)/- + -- INSTANCE MEMORY: 0(I4),18(I3),9(I2)/- + + -- VALIDATE STATE + + Log("W0,W3: RTPS Operation GET_MIN_SN", INFO); + Log("W0: Expected SN 4", DEBUG); + Log("W3: Expected SN 6", DEBUG); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_MIN_SN; + -- WRITER 0 + rtps.cc.seq_nr := gen_sn(4); + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- WRITER 3 + rtps.cc.seq_nr := gen_sn(6); + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W0,W3: RTPS Operation GET_MAX_SN", INFO); + Log("W0: Expected SN 9", DEBUG); + Log("W3: Expected SN 8", DEBUG); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_MAX_SN; + -- WRITER 0 + rtps.cc.seq_nr := gen_sn(9); + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- WRITER 3 + rtps.cc.seq_nr := gen_sn(8); + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W0,W3: RTPS Operation GET_CACHE_CHANGE SN 8", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_CACHE_CHANGE; + -- WRITER 0 + rtps.cc := cc3; + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- WRITER 3 + rtps.cc := cc4; + rtps.cc.seq_nr := gen_sn(8); + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W0,W3: RTPS Operation GET_CACHE_CHANGE SN 9", INFO); + Log("W3: INVALID", DEBUG); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_CACHE_CHANGE; + rtps.cc := cc4; + -- WRITER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- WRITER 3 + rtps.ret_code := INVALID; + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W0: RTPS Operation ACK_CACHE_CHANGE SN 9", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := ACK_CACHE_CHANGE; + rtps.cc.seq_nr := gen_sn(9); + -- WRITER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W3: RTPS Operation ACK_CACHE_CHANGE SN 8", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := ACK_CACHE_CHANGE; + rtps.cc.seq_nr := gen_sn(8); + -- WRITER 3 + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh1; + cc.payload := gen_payload(kh1,10); + cc.seq_nr := gen_sn(10); + cc.src_timestamp := gen_duration(10,0); + + -- TEST: REGISTER INSTANCE ON MAX_INSTANCES [UNKNOWN INSTANCE, WITH STALE INSTANCE] + + Log("W0,W3: DDS Operation REGISTER_INSTANCE 1", INFO); + Log("W0,W3: ACCEPTED", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := REGISTER_INSTANCE; + dds.cc := cc; + dds.ret_code := RETCODE_OK; + -- WRITER 0 + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- WRITER 3 + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- WRITER 0 + AlertIf(empty_sample_head(0) /= 11, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I4S7),22(I2S8)/11,33,44 + -- PAYLOAD MEMORY: 33(I4S7),0(I2S8),22(I2S8)/44,11 + -- INSTANCE MEMORY: 18(I1),0(I4),9(I2)/- + -- WRITER 3 + AlertIf(empty_sample_head(3) /= 11, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(3) /= 33, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(3) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I4S6),22(I2S7)/11,33 + -- PAYLOAD MEMORY: 0(I4S6),22(I2S7),11(I2S7)/33 + -- INSTANCE MEMORY: 18(I1),0(I4),9(I2)/- + + Log("W0,W3: DDS Operation WRITE [TS 10s, Instance 1, Aligned Payload]", INFO); + Log("W0,W3: ACCEPTED", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := WRITE; + dds.cc := cc; + dds.ret_code := RETCODE_OK; + -- WRITER 0 + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- WRITER 3 + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + cc2 := cc; + -- WRITER 0 + AlertIf(empty_sample_head(0) /= 33, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 11, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I4S7),22(I2S8),11(I1S10)/33,44 + -- PAYLOAD MEMORY: 33(I4S7),0(I2S8),22(I2S8),44(I1S10)/11 + -- INSTANCE MEMORY: 18(I1),0(I4),9(I2)/- + -- WRITER 3 + AlertIf(empty_sample_head(3) /= 33, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(3) /= 54, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(3) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I4S6),22(I2S7),11(I1S9)/33 + -- PAYLOAD MEMORY: 0(I4S6),22(I2S7),11(I2S7),33(I1S9)/- + -- INSTANCE MEMORY: 18(I1),0(I4),9(I2)/- + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh4; + cc.payload := gen_payload(kh4,10); + cc.seq_nr := gen_sn(11); + cc.src_timestamp := gen_duration(11,0); + + Log("W0,W3: DDS Operation WRITE [TS 11s, Instance 1, Aligned Payload]", INFO); + Log("W0: ACCEPTED", DEBUG); + Log("W3: REJECTED [Payload memory Full]", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := WRITE; + dds.cc := cc; + -- WRITER 0 + dds.ret_code := RETCODE_OK; + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- WRITER 3 + dds.ret_code := RETCODE_OUT_OF_RESOURCES; + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + cc4 := cc; + AlertIf(empty_sample_head(0) /= 44, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 54, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I4S7),22(I2S8),11(I1S10),33(I4S11)/44 + -- PAYLOAD MEMORY: 33(I4S7),0(I2S8),22(I2S8),44(I1S10),11(I4S11)/- + -- INSTANCE MEMORY: 18(I1),0(I4),9(I2)/- + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh2; + cc.payload := gen_payload(kh2,10); + cc.seq_nr := gen_sn(12); + cc.src_timestamp := gen_duration(12,0); + + Log("W0,W3: DDS Operation WRITE [TS 12s, Instance 2, Aligned Payload]", INFO); + Log("W0,W3: REJECTED [Payload Memory Full]", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := WRITE; + dds.cc := cc; + dds.ret_code := RETCODE_OUT_OF_RESOURCES; + -- WRITER 0 + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- WRITER 3 + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + + Log("W0: RTPS Operation ACK_CACHE_CHANGE SN 8", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := ACK_CACHE_CHANGE; + rtps.cc.seq_nr := gen_sn(8); + -- WRITER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W3: RTPS Operation ACK_CACHE_CHANGE SN 7", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := ACK_CACHE_CHANGE; + rtps.cc.seq_nr := gen_sn(7); + -- WRITER 3 + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + -- TEST: WRITE ON PAYLOAD MEMORY FULL [WITH ACKed SAMPLES] + + Log("W0,W3: DDS Operation WRITE [TS 12s, Instance 2, Aligned Payload]", INFO); + Log("W0,W3: ACCEPTED", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := WRITE; + dds.cc := cc; + dds.ret_code := RETCODE_OK; + -- WRITER 0 + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- WRITER 3 + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + cc3 := cc; + -- WRITER 0 + AlertIf(empty_sample_head(0) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 22, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I4S7),11(I1S10),33(I4S11),44(I2S12)/22 + -- PAYLOAD MEMORY: 33(I4S7),44(I1S10),11(I4S11),0(I2S12)/22 + -- INSTANCE MEMORY: 18(I1),0(I4),9(I2)/- + -- WRITER 3 + AlertIf(empty_sample_head(3) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(3) /= 11, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(3) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I4S6),11(I1S9),33(I2S10)/22 + -- PAYLOAD MEMORY: 0(I4S6),33(I1S9),22(I2S10)/11 + -- INSTANCE MEMORY: 18(I1),0(I4),9(I2)/- + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh4; + cc.payload := gen_payload(kh4,10); + cc.seq_nr := gen_sn(13); + cc.src_timestamp := gen_duration(13,0); + + -- TEST: ADD SAMPLE ON MAX_SAMPLES [KNOWN INSTANCE,WITHOUT ACKed SAMPLES] + + Log("W0,W3: DDS Operation WRITE [TS 13s, Instance 4, Aligned Payload]", INFO); + Log("W0,W3: REJECTED [MAX_SAMPLES exceeded]", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := WRITE; + dds.cc := cc; + dds.ret_code := RETCODE_OUT_OF_RESOURCES; + -- WRITER 0 + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- WRITER 3 + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + + Log("W0: RTPS Operation ACK_CACHE_CHANGE SN 7", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := ACK_CACHE_CHANGE; + rtps.cc.seq_nr := gen_sn(7); + -- WRITER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W3: RTPS Operation ACK_CACHE_CHANGE SN 6", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := ACK_CACHE_CHANGE; + rtps.cc.seq_nr := gen_sn(6); + -- WRITER 3 + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + -- TEST: ADD SAMPLE ON MAX_SAMPLES [KNOWN INSTANCE,WITH ACKed SAMPLES] + + Log("W0,W3: DDS Operation WRITE [TS 13s, Instance 4, Aligned Payload]", INFO); + Log("W0,W3: ACCEPTED", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := WRITE; + dds.cc := cc; + dds.ret_code := RETCODE_OK; + -- WRITER 0 + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- WRITER 3 + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + cc1 := cc; + -- WRITER 0 + AlertIf(empty_sample_head(0) /= 0, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 33, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 11(I1S10),33(I4S11),44(I2S12),22(I4S13)/0 + -- PAYLOAD MEMORY: 44(I1S10),11(I4S11),0(I2S12),22(I4S13)/33 + -- INSTANCE MEMORY: 18(I1),0(I4),9(I2)/- + -- WRITER 3 + AlertIf(empty_sample_head(3) /= 0, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(3) /= 0, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(3) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 11(I1S9),33(I2S10),22(I4S11)/0 + -- PAYLOAD MEMORY: 33(I1S9),22(I2S10),11(I4S11)/0 + -- INSTANCE MEMORY: 18(I1),0(I4),9(I2)/- + + -- VALIDATE STATE + + Log("W0,W3: RTPS Operation GET_MIN_SN", INFO); + Log("W0: Expected SN 10", DEBUG); + Log("W3: Expected SN 9", DEBUG); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_MIN_SN; + -- WRITER 0 + rtps.cc.seq_nr := gen_sn(10); + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- WRITER 3 + rtps.cc.seq_nr := gen_sn(9); + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W0,W3: RTPS Operation GET_MAX_SN", INFO); + Log("W0: Expected SN 13", DEBUG); + Log("W3: Expected SN 11", DEBUG); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_MAX_SN; + -- WRITER 0 + rtps.cc.seq_nr := gen_sn(13); + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- WRITER 3 + rtps.cc.seq_nr := gen_sn(11); + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W0,W3: RTPS Operation GET_CACHE_CHANGE SN 10", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_CACHE_CHANGE; + -- WRITER 0 + rtps.cc := cc2; + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- WRITER 3 + rtps.cc := cc3; + rtps.cc.seq_nr := gen_sn(10); + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W0,W3: RTPS Operation GET_CACHE_CHANGE SN 11", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_CACHE_CHANGE; + -- WRITER 0 + rtps.cc := cc4; + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- WRITER 3 + rtps.cc := cc1; + rtps.cc.seq_nr := gen_sn(11); + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W0: RTPS Operation GET_CACHE_CHANGE SN 12", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_CACHE_CHANGE; + rtps.cc := cc3; + -- WRITER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W0: RTPS Operation GET_CACHE_CHANGE SN 13", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_CACHE_CHANGE; + rtps.cc := cc1; + -- WRITER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W0: RTPS Operation ACK_CACHE_CHANGE SN 12", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := ACK_CACHE_CHANGE; + rtps.cc.seq_nr := gen_sn(12); + -- WRITER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W3: RTPS Operation ACK_CACHE_CHANGE SN 10", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := ACK_CACHE_CHANGE; + rtps.cc.seq_nr := gen_sn(10); + -- WRITER 3 + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := NOT_ALIVE_UNREGISTERED; + cc.instance := kh2; + cc.payload := gen_payload(kh2,5); + cc.seq_nr := gen_sn(14); + cc.src_timestamp := gen_duration(14,0); + + Log("W0,W3: DDS Operation UNREGISTER_INSTANCE [TS 14s, Instance 2]", INFO); + Log("W0,W3: ACCEPTED", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := UNREGISTER_INSTANCE; + dds.cc := cc; + dds.ret_code := RETCODE_OK; + -- WRITER 0 + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- WRITER 3 + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + cc3 := cc; + -- WRITER 0 + AlertIf(empty_sample_head(0) /= 44, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 0, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 11(I1S10),33(I4S11),22(I4S13),0(I2S14)/44 + -- PAYLOAD MEMORY: 44(I1S10),11(I4S11),22(I4S13),33(I2S14)/0 + -- INSTANCE MEMORY: 18(I1),0(I4),9(I2)/- + -- WRITER 3 + AlertIf(empty_sample_head(3) /= 33, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(3) /= 22, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(3) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 11(I1S9),22(I4S11),0(I2S12)/33 + -- PAYLOAD MEMORY: 33(I1S9),11(I4S11),0(I2S12)/22 + -- INSTANCE MEMORY: 18(I1),0(I4),9(I2)/- + + Log("W0,W3: RTPS Operation ACK_CACHE_CHANGE SN 11", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := ACK_CACHE_CHANGE; + rtps.cc.seq_nr := gen_sn(11); + -- WRITER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- WRITER 3 + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh4; + cc.payload := gen_payload(kh4,20); + cc.seq_nr := gen_sn(15); + cc.src_timestamp := gen_duration(15,0); + + -- TEST: ADD SAMPLE BIGGER THAN AVAILABLE MEMORY SPACE [WITH ACKed SAMPLES] + + Log("W0,W3: DDS Operation WRITE [TS 15s, Instance 4, Aligned Payload (2 Slots)]", INFO); + Log("W0,W3: REJECTED [Payload Memory Full]", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := WRITE; + dds.cc := cc; + dds.ret_code := RETCODE_OUT_OF_RESOURCES; + -- WRITER 0 + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- WRITER 3 + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + + Log("W0,W3: RTPS Operation REMOVE_CACHE_CHANGE SN 11", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := REMOVE_CACHE_CHANGE; + rtps.cc.seq_nr := gen_sn(11); + -- WRITER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- WRITER 3 + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- WRITER 0 + AlertIf(empty_sample_head(0) /= 44, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 11, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 11(I1S10),22(I4S13),0(I2S14)/44,33 + -- PAYLOAD MEMORY: 44(I1S10),22(I4S13),33(I2S14)/11,0 + -- INSTANCE MEMORY: 18(I1),0(I4),9(I2)/- + -- WRITER 3 + AlertIf(empty_sample_head(3) /= 33, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(3) /= 11, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(3) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 11(I1S9),0(I2S12)/33,22 + -- PAYLOAD MEMORY: 33(I1S9),0(I2S12)/11,22 + -- INSTANCE MEMORY: 18(I1),0(I4),9(I2)/- + + + + Log("W0,W3: DDS Operation WRITE [TS 15s, Instance 4, Aligned Payload (2 Slots)]", INFO); + Log("W0,W3: ACCEPTED", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := WRITE; + dds.cc := cc; + dds.ret_code := RETCODE_OK; + -- WRITER 0 + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- WRITER 3 + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + cc4 := cc; + -- WRITER 0 + AlertIf(empty_sample_head(0) /= 33, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 54, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 11(I1S10),22(I4S13),0(I2S14),44(I4S15)/33 + -- PAYLOAD MEMORY: 44(I1S10),22(I4S13),33(I2S14),11(I4S15),0(I4S15)/- + -- INSTANCE MEMORY: 18(I1),0(I4),9(I2)/- + -- WRITER 3 + AlertIf(empty_sample_head(3) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(3) /= 54, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(3) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 11(I1S9),0(I2S12),33(I4S13)/22 + -- PAYLOAD MEMORY: 33(I1S9),0(I2S12),11(I4S13),22(I4S13)/- + -- INSTANCE MEMORY: 18(I1),0(I4),9(I2)/- + + -- TEST: UNREGISTER INSTANCE ON PAYLOAD MEMORY FULL [WITHOUT ACKed SAMPLES] + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := NOT_ALIVE_UNREGISTERED; + cc.instance := kh1; + cc.payload := gen_payload(kh1,5); + cc.seq_nr := gen_sn(16); + cc.src_timestamp := gen_duration(16,0); + + Log("W0,W3: DDS Operation UNREGISTER_INSTANCE [TS 16s, Instance 1]", INFO); + Log("W0,W3: REJECTED [Payload memory Full, MAX_SAMPLES exceeded]", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := UNREGISTER_INSTANCE; + dds.cc := cc; + dds.ret_code := RETCODE_OUT_OF_RESOURCES; + -- WRITER 0 + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- WRITER 3 + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + + Log("W0: RTPS Operation ACK_CACHE_CHANGE SN 10", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := ACK_CACHE_CHANGE; + rtps.cc.seq_nr := gen_sn(10); + -- WRITER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W3: RTPS Operation ACK_CACHE_CHANGE SN 9", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := ACK_CACHE_CHANGE; + rtps.cc.seq_nr := gen_sn(9); + -- WRITER 3 + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + -- TEST: UNREGISTER INSTANCE ON PAYLOAD MEMORY FULL [WITH ACKed SAMPLES] + + Log("W0,W3: DDS Operation UNREGISTER_INSTANCE [TS 16s, Instance 1]", INFO); + Log("W0,W3: ACCEPTED", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := UNREGISTER_INSTANCE; + dds.cc := cc; + dds.ret_code := RETCODE_OK; + -- WRITER 0 + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- WRITER 3 + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + cc2 := cc; + -- WRITER 0 + AlertIf(empty_sample_head(0) /= 11, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 54, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 22(I4S13),0(I2S14),44(I4S15),33(I1S16)/11 + -- PAYLOAD MEMORY: 22(I4S13),33(I2S14),11(I4S15),0(I4S15),44(I1S16)/- + -- INSTANCE MEMORY: 18(I1),0(I4),9(I2)/- + -- WRITER 3 + AlertIf(empty_sample_head(3) /= 11, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(3) /= 54, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(3) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I2S12),33(I4S13),22(I1S14)/11 + -- PAYLOAD MEMORY: 0(I2S12),11(I4S13),22(I4S13),33(I1S14)/- + -- INSTANCE MEMORY: 18(I1),0(I4),9(I2)/- + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := NOT_ALIVE_DISPOSED; + cc.instance := kh3; + cc.payload := gen_payload(kh3,5); + cc.seq_nr := gen_sn(17); + cc.src_timestamp := gen_duration(17,0); + + -- TEST: DISPOSE ON PAYLOAD MEMORY FULL [WITHOUT ACKed SAMPLES] + + Log("W0,W3: DDS Operation DISPOSE [TS 17s, Instance 3]", INFO); + Log("W0,W3: REJECTED [Payload memory Full, MAX_SAMPLES exceeded]", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := DISPOSE; + dds.cc := cc; + dds.cc.instance:= HANDLE_NIL; + dds.ret_code := RETCODE_OUT_OF_RESOURCES; + -- WRITER 0 + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- WRITER 3 + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + + Log("W0,W3: RTPS Operation ACK_CACHE_CHANGE SN 13", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := ACK_CACHE_CHANGE; + rtps.cc.seq_nr := gen_sn(13); + -- WRITER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- WRITER 3 + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W0,W3: RTPS Operation ACK_CACHE_CHANGE SN 14", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := ACK_CACHE_CHANGE; + rtps.cc.seq_nr := gen_sn(14); + -- WRITER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- WRITER 3 + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W3: RTPS Operation ACK_CACHE_CHANGE SN 12", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := ACK_CACHE_CHANGE; + rtps.cc.seq_nr := gen_sn(12); + -- WRITER 3 + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + -- TEST: DISPOSE ON PAYLOAD MEMORY FULL [WITH ACKed SAMPLES] + -- TEST: ADD SAMPLE ON PAYLOAD FULL & MAX_INSTANCES [UNKNOWN INSTANCE,WITH ACKed SAMPLES,WITH STALE INSTANCE (>= 1 SAMPLE)] (Induce Double Remove) + -- TEST: REMOVE STALE INSTANCE WITH 1 SAMPLES + + Log("W0,W3: DDS Operation DISPOSE [TS 17s, Instance 3]", INFO); + Log("W0,W3: ACCEPTED", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := DISPOSE; + dds.cc := cc; + dds.cc.instance:= HANDLE_NIL; + dds.ret_code := RETCODE_OK; + -- WRITER 0 + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- WRITER 3 + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + cc1 := cc; + -- WRITER 0 + AlertIf(empty_sample_head(0) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 33, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 44(I4S15),33(I1S16),11(I3S17)/22,0 + -- PAYLOAD MEMORY: 11(I4S15),0(I4S15),44(I1S16),22(I3S17)/33 + -- INSTANCE MEMORY: 9(I3),18(I1),0(I4)/- + -- WRITER 3 + AlertIf(empty_sample_head(3) /= 0, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(3) /= 33, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(3) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 33(I4S13),11(I3S15)/0,22 + -- PAYLOAD MEMORY: 11(I4S13),22(I4S13),0(I3S15)/33 + -- INSTANCE MEMORY: 18(I3),0(I4),9(I2)/- + + -- VALIDATE STATE + + Log("W0,W3: RTPS Operation GET_MIN_SN", INFO); + Log("W0: Expected SN 15", DEBUG); + Log("W3: Expected SN 13", DEBUG); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_MIN_SN; + -- WRITER 0 + rtps.cc.seq_nr := gen_sn(15); + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- WRITER 3 + rtps.cc.seq_nr := gen_sn(13); + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W0,W3: RTPS Operation GET_MAX_SN", INFO); + Log("W0: Expected SN 17", DEBUG); + Log("W3: Expected SN 15", DEBUG); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_MAX_SN; + -- WRITER 0 + rtps.cc.seq_nr := gen_sn(17); + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- WRITER 3 + rtps.cc.seq_nr := gen_sn(15); + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W0,W3: RTPS Operation GET_CACHE_CHANGE SN 15", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_CACHE_CHANGE; + -- WRITER 0 + rtps.cc := cc4; + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- WRITER 3 + rtps.cc := cc1; + rtps.cc.seq_nr := gen_sn(15); + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W0: RTPS Operation GET_CACHE_CHANGE SN 16", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_CACHE_CHANGE; + rtps.cc := cc2; + -- WRITER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W0: RTPS Operation GET_CACHE_CHANGE SN 17", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_CACHE_CHANGE; + rtps.cc := cc1; + -- WRITER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W0,W3: RTPS Operation REMOVE_CACHE_CHANGE SN 15", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := REMOVE_CACHE_CHANGE; + rtps.cc.seq_nr := gen_sn(15); + -- WRITER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- WRITER 3 + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- WRITER 0 + AlertIf(empty_sample_head(0) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 11, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 33(I1S16),11(I3S17)/22,0,44 + -- PAYLOAD MEMORY: 44(I1S16),22(I3S17)/11,0,33 + -- INSTANCE MEMORY: 9(I3),18(I1),0(I4)/- + -- WRITER 3 + AlertIf(empty_sample_head(3) /= 0, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(3) /= 0, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(3) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 33(I4S13)/0,22,11 + -- PAYLOAD MEMORY: 11(I4S13),22(I4S13)/0,33 + -- INSTANCE MEMORY: 18(I3),0(I4),9(I2)/- + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh3; + cc.payload := gen_payload(kh3,10); + cc.seq_nr := gen_sn(18); + cc.src_timestamp := gen_duration(18,0); + + -- TEST: WRITE ON DISPOSED INSTANCE + + Log("W0,W3: DDS Operation WRITE [TS 18s, Instance 3, Aligned Payload]", INFO); + Log("W0,W3: ACCEPTED", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := WRITE; + dds.cc := cc; + dds.ret_code := RETCODE_OK; + -- WRITER 0 + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- WRITER 3 + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + cc3 := cc; + -- WRITER 0 + AlertIf(empty_sample_head(0) /= 0, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 0, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 33(I1S16),11(I3S17),22(I3S18)/0,44 + -- PAYLOAD MEMORY: 44(I1S16),22(I3S17),11(I3S18)/0,33 + -- INSTANCE MEMORY: 9(I3),18(I1),0(I4)/- + -- WRITER 3 + AlertIf(empty_sample_head(3) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(3) /= 33, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(3) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 33(I4S13),0(I3S16)/22,11 + -- PAYLOAD MEMORY: 11(I4S13),22(I4S13),0(I3S16)/33 + -- INSTANCE MEMORY: 18(I3),0(I4),9(I2)/- + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh4; + cc.payload := gen_payload(kh4,10); + cc.seq_nr := gen_sn(19); + cc.src_timestamp := gen_duration(19,0); + + Log("W0,W3: DDS Operation WRITE [TS 19s, Instance 4, Aligned Payload]", INFO); + Log("W0,W3: ACCEPTED", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := WRITE; + dds.cc := cc; + dds.ret_code := RETCODE_OK; + -- WRITER 0 + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- WRITER 3 + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + cc4 := cc; + -- WRITER 0 + AlertIf(empty_sample_head(0) /= 44, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 33, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 33(I1S16),11(I3S17),22(I3S18),0(I4S19)/44 + -- PAYLOAD MEMORY: 44(I1S16),22(I3S17),11(I3S18),0(I4S19)/33 + -- INSTANCE MEMORY: 9(I3),18(I1),0(I4)/- + -- WRITER 3 + AlertIf(empty_sample_head(3) /= 11, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(3) /= 54, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(3) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 33(I4S13),0(I3S16),22(I4S17)/11 + -- PAYLOAD MEMORY: 11(I4S13),22(I4S13),0(I3S16),33(I4S17)/- + -- INSTANCE MEMORY: 18(I3),0(I4),9(I2)/- + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh2; + cc.payload := gen_payload(kh2,10); + cc.seq_nr := gen_sn(20); + cc.src_timestamp := gen_duration(20,0); + + -- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE,WITHOUT STALE INSTANCES,WITHOUT ACKed SAMPLES] + + Log("W0,W3: DDS Operation WRITE [TS 20s, Instance 2, Aligned Payload]", INFO); + Log("W0: REJECTED [MAX_SAMPLES exceeded, MAX_INSTANCES exceeded]", DEBUG); + Log("W0: ACCEPTED", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := WRITE; + dds.cc := cc; + dds.cc.instance:= HANDLE_NIL; + -- WRITER 0 + dds.ret_code := RETCODE_OUT_OF_RESOURCES; + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- WRITER 3 + dds.ret_code := RETCODE_OK; + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- WRITER 3 + AlertIf(empty_sample_head(3) /= 33, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(3) /= 22, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(3) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I3S16),22(I4S17),11(I2S18)/33 + -- PAYLOAD MEMORY: 0(I3S16),33(I4S17),11(I2S18)/22 + -- INSTANCE MEMORY: 18(I3),0(I4),9(I2)/- + + Log("W0,W3: RTPS Operation ACK_CACHE_CHANGE SN 16", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := ACK_CACHE_CHANGE; + rtps.cc.seq_nr := gen_sn(16); + -- WRITER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- WRITER 3 + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + -- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE,WITH STALE INSTANCE (>0 SAMPLES)] + + Log("W0: DDS Operation WRITE [TS 20s, Instance 2, Aligned Payload]", INFO); + Log("W0: ACCEPTED", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := WRITE; + dds.cc := cc; + dds.cc.instance:= HANDLE_NIL; + dds.ret_code := RETCODE_OK; + -- WRITER 0 + ind <= 0; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + cc2 := cc; + -- WRITER 0 + AlertIf(empty_sample_head(0) /= 33, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 11(I3S17),22(I3S18),0(I4S19),44(I2S20)/33 + -- PAYLOAD MEMORY: 22(I3S17),11(I3S18),0(I4S19),33(I2S20)/44 + -- INSTANCE MEMORY: 18(I2),9(I3),0(I4)/- + + Log("W0,W3: RTPS Operation ACK_CACHE_CHANGE SN 17", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := ACK_CACHE_CHANGE; + rtps.cc.seq_nr := gen_sn(17); + -- WRITER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- WRITER 3 + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := NOT_ALIVE_UNREGISTERED; + cc.instance := kh4; + cc.payload := gen_payload(kh4,5); + cc.seq_nr := gen_sn(21); + cc.src_timestamp := gen_duration(21,0); + + Log("W0,W3: DDS Operation UNREGISTER_INSTANCE [TS 21s, Instance 4]", INFO); + Log("W0,W3: ACCEPTED", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := UNREGISTER_INSTANCE; + dds.cc := cc; + dds.ret_code := RETCODE_OK; + -- WRITER 0 + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- WRITER 3 + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + cc1 := cc; + -- WRITER 0 + AlertIf(empty_sample_head(0) /= 11, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 22, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 22(I3S18),0(I4S19),44(I2S20),33(I4S21)/11 + -- PAYLOAD MEMORY: 11(I3S18),0(I4S19),33(I2S20),44(I4S21)/22 + -- INSTANCE MEMORY: 18(I2),9(I3),0(I4)/- + -- WRITER 3 + AlertIf(empty_sample_head(3) /= 0, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(3) /= 0, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(3) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 22(I4S17),11(I2S18),33(I4S19)/0 + -- PAYLOAD MEMORY: 33(I4S17),11(I2S18),22(I4S19)/0 + -- INSTANCE MEMORY: 18(I3),0(I4),9(I2)/- + + Log("W0,W3: RTPS Operation ACK_CACHE_CHANGE SN 19", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := ACK_CACHE_CHANGE; + rtps.cc.seq_nr := gen_sn(19); + -- WRIITER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- WRIITER 3 + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh1; + cc.payload := gen_payload(kh1,10); + cc.seq_nr := gen_sn(22); + cc.src_timestamp := gen_duration(22,0); + + -- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE,WITHOUT STALE INSTANCE, WITH ACKed SAMPLE] + + Log("W0,W3: DDS Operation WRITE [TS 22s, Instance 1, Aligned Payload]", INFO); + Log("W0: REJECTED [MAX_SAMPLES exceeded, MAX_INSTANCES exceeded]", DEBUG); + Log("W3: ACCEPTED", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := WRITE; + dds.cc := cc; + dds.cc.instance:= HANDLE_NIL; + -- WRITER 0 + dds.ret_code := RETCODE_OUT_OF_RESOURCES; + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- WRITER 3 + dds.ret_code := RETCODE_OK; + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- WRITER 3 + AlertIf(empty_sample_head(3) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(3) /= 22, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(3) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 11(I2S18),0(I1S20)/22,33 + -- PAYLOAD MEMORY: 11(I2S18),0(I1S20)/22,33 + -- INSTANCE MEMORY: 0(I1),18(I3),9(I2)/- + + Log("W0,W3: RTPS Operation REMOVE_CACHE_CHANGE SN 19", INFO); + Log("W3: INVALID", DEBUG); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := REMOVE_CACHE_CHANGE; + rtps.cc.seq_nr := gen_sn(19); + -- WRITER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- WRITER 3 + rtps.ret_code := INVALID; + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- WRITER 0 + AlertIf(empty_sample_head(0) /= 11, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 0, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 22(I3S18),44(I2S20),33(I4S21)/11,0 + -- PAYLOAD MEMORY: 11(I3S18),33(I2S20),44(I4S21)/0,22 + -- INSTANCE MEMORY: 18(I2),9(I3),0(I4)/- + + Log("W0,W3: RTPS Operation REMOVE_CACHE_CHANGE SN 21", INFO); + Log("W3: INVALID", DEBUG); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := REMOVE_CACHE_CHANGE; + rtps.cc.seq_nr := gen_sn(21); + -- WRITER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- WRITER 3 + rtps.ret_code := INVALID; + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + wait_on_idle; + -- WRITER 0 + AlertIf(empty_sample_head(0) /= 11, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 22(I3S18),44(I2S20)/11,0,33 + -- PAYLOAD MEMORY: 11(I3S18),33(I2S20)/44,0,22 + -- INSTANCE MEMORY: 18(I2),9(I3),0(I4)/- + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := NOT_ALIVE_UNREGISTERED; + cc.instance := kh2; + cc.payload := gen_payload(kh2,5); + cc.seq_nr := gen_sn(22); + cc.src_timestamp := gen_duration(22,0); + + Log("W0,W3: DDS Operation UNREGISTER_INSTANCE [TS 22s, Instance 2]", INFO); + Log("W0,W3: ACCEPTED", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := UNREGISTER_INSTANCE; + dds.cc := cc; + dds.ret_code := RETCODE_OK; + -- WRITER 0 + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- WRITER 3 + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + cc1 := cc; + -- WRITER 0 + AlertIf(empty_sample_head(0) /= 0, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 0, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 22(I3S18),44(I2S20),11(I2S22)/0,33 + -- PAYLOAD MEMORY: 11(I3S18),33(I2S20),44(I2S22)/0,22 + -- INSTANCE MEMORY: 18(I2),9(I3),0(I4)/- + -- WRITER 3 + AlertIf(empty_sample_head(3) /= 33, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(3) /= 33, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(3) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 11(I2S18),0(I1S20),22(I2S21)/33 + -- PAYLOAD MEMORY: 11(I2S18),0(I1S20),22(I2S21)/33 + -- INSTANCE MEMORY: 0(I1),18(I3),9(I2)/- + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := NOT_ALIVE_UNREGISTERED; + cc.instance := kh3; + cc.payload := gen_payload(kh3,5); + cc.seq_nr := gen_sn(23); + cc.src_timestamp := gen_duration(23,0); + + Log("W0,W3: DDS Operation UNREGISTER_INSTANCE [TS 23s, Instance 3]", INFO); + Log("W0: ACCEPTED", DEBUG); + Log("W3: REJECTED (MAX SAMPLES)", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := UNREGISTER_INSTANCE; + dds.cc := cc; + -- WRITER 0 + dds.ret_code := RETCODE_OK; + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- WRITER 3 + dds.ret_code := RETCODE_OUT_OF_RESOURCES; + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + cc4 := cc; + -- WRITER 0 + AlertIf(empty_sample_head(0) /= 33, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 22, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 22(I3S18),44(I2S20),11(I2S22),0(I3S23)/33 + -- PAYLOAD MEMORY: 11(I3S18),33(I2S20),44(I2S22),0(I3S23)/22 + -- INSTANCE MEMORY: 18(I2),9(I3),0(I4)/- + + -- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE,WITH STALE INSTANCE, WITHOUT ACKed SAMPLE] + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh1; + cc.payload := gen_payload(kh1,10); + cc.seq_nr := gen_sn(24); + cc.src_timestamp := gen_duration(24,0); + + Log("W0,W3: DDS Operation WRITE [TS 24s, Instance 1, Aligned Payload]", INFO); + Log("W0,W3: REJECTED [MAX_SAMPLES exceeded, MAX_INSTANCES exceeded]", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := WRITE; + dds.cc := cc; + dds.cc.instance:= HANDLE_NIL; + dds.ret_code := RETCODE_OUT_OF_RESOURCES; + -- WRITER 0 + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- WRITER 3 + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + + Log("W0,W3: RTPS Operation ACK_CACHE_CHANGE SN 20", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := ACK_CACHE_CHANGE; + rtps.cc.seq_nr := gen_sn(20); + -- WRITER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- WRITER 3 + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + -- TEST: REMOVE STALE INSTANCE WITH 0 SAMPLES + -- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE,WITH STALE INSTANCE, WITH ACKed SAMPLE] + + Log("W0,W3: DDS Operation WRITE [TS 24s, Instance 1, Aligned Payload]", INFO); + Log("W0,W3: ACCEPTED", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := WRITE; + dds.cc := cc; + dds.cc.instance:= HANDLE_NIL; + dds.ret_code := RETCODE_OK; + -- WRITER 0 + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- WRITER 3 + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + cc2 := cc; + -- WRITER 0 + AlertIf(empty_sample_head(0) /= 44, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 33, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 22(I3S18),11(I2S22),0(I3S23),33(I1S24)/44 + -- PAYLOAD MEMORY: 11(I3S18),44(I2S22),0(I3S23),22(I1S24)/33 + -- INSTANCE MEMORY: 0(I1),18(I2),9(I3)/- + -- WRITER 3 + AlertIf(empty_sample_head(3) /= 0, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(3) /= 0, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(3) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 11(I2S18),22(I2S21),33(I1S22)/0 + -- PAYLOAD MEMORY: 11(I2S18),22(I2S21),33(I1S22)/0 + -- INSTANCE MEMORY: 0(I1),18(I3),9(I2)/- + + Log("W0,W3: RTPS Operation ACK_CACHE_CHANGE SN 22", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := ACK_CACHE_CHANGE; + rtps.cc.seq_nr := gen_sn(22); + -- WRITER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- WRITER 3 + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + -- TEST: NORMAL NACK_CACHE_CHANGE + + Log("W0,W3: RTPS Operation NACK_CACHE_CHANGE SN 22", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := NACK_CACHE_CHANGE; + rtps.cc.seq_nr := gen_sn(22); + -- WRITER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- WRITER 3 + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh4; + cc.payload := gen_payload(kh4,10); + cc.seq_nr := gen_sn(25); + cc.src_timestamp := gen_duration(25,0); + + Log("W0,W3: DDS Operation REGISTER_INSTANCE 4", INFO); + Log("W0,W3: REJECTED [MAX_INSTANCES exceeded]", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := REGISTER_INSTANCE; + dds.cc := cc; + dds.cc.instance:= HANDLE_NIL; + -- WRITER 0 + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- WRITER 3 + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + + Log("W0,W3: RTPS Operation ACK_CACHE_CHANGE SN 22", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := ACK_CACHE_CHANGE; + rtps.cc.seq_nr := gen_sn(22); + -- WRITER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- WRITER 3 + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + -- TEST: REGISTER ON UNREGISTERED INSTANCE + + Log("W0,W3: DDS Operation REGISTER_INSTANCE 2", INFO); + Log("W0,W3: ACCEPTED", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := REGISTER_INSTANCE; + dds.cc := cc1; + dds.ret_code := RETCODE_OK; + -- WRITER 0 + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- WRITER 3 + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + + Log("W0,W3: DDS Operation REGISTER_INSTANCE 4", INFO); + Log("W0,W3: REJECTED [MAX_INSTANCES exceeded]", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := REGISTER_INSTANCE; + dds.cc := cc; + dds.cc.instance:= HANDLE_NIL; + -- WRITER 0 + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- WRITER 3 + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + + Log("W0,W3: RTPS Operation ACK_CACHE_CHANGE SN 18", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := ACK_CACHE_CHANGE; + rtps.cc.seq_nr := gen_sn(18); + -- WRITER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- WRITER 3 + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W0,W3: RTPS Operation ACK_CACHE_CHANGE SN 23", INFO); + Log("W3: INVALID", DEBUG); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := ACK_CACHE_CHANGE; + rtps.cc.seq_nr := gen_sn(23); + -- WRITER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- WRITER 3 + rtps.ret_code := INVALID; + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh3; + cc.payload := gen_payload(kh3,10); + cc.seq_nr := gen_sn(25); + cc.src_timestamp := gen_duration(25,0); + + -- TEST: WRITE ON UNREGISTERED INSTANCE + + Log("W0,W3: DDS Operation WRITE [TS 25s, Instance 3, Aligned Payload]", INFO); + Log("W0,W3: ACCEPTED", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := WRITE; + dds.cc := cc; + dds.cc.instance:= HANDLE_NIL; + dds.ret_code := RETCODE_OK; + -- WRITER 0 + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- WRITER 3 + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + cc3 := cc; + -- WRITER 0 + AlertIf(empty_sample_head(0) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 11, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 11(I2S22),0(I3S23),33(I1S24),44(I3S25)/22 + -- PAYLOAD MEMORY: 44(I2S22),0(I3S23),22(I1S24),33(I3S25)/11 + -- INSTANCE MEMORY: 0(I1),18(I2),9(I3)/- + -- WRITER 3 + AlertIf(empty_sample_head(3) /= 11, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(3) /= 11, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(3) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 22(I2S21),33(I1S22),0(I3S23)/11 + -- PAYLOAD MEMORY: 22(I2S21),33(I1S22),0(I3S23)/11 + -- INSTANCE MEMORY: 0(I1),18(I3),9(I2)/- + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh4; + cc.payload := gen_payload(kh4,10); + cc.seq_nr := gen_sn(26); + cc.src_timestamp := gen_duration(26,0); + + Log("W0,W3: DDS Operation REGISTER_INSTANCE 4", INFO); + Log("W0,W3: REJECTED [MAX_INSTANCES exceeded]", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := REGISTER_INSTANCE; + dds.cc := cc; + -- WRITER 0 + dds.cc.instance:= HANDLE_NIL; + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- WRITER 3 + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := NOT_ALIVE_UNREGISTERED; + cc.instance := kh4; + cc.payload := gen_payload(kh4,5); + cc.seq_nr := gen_sn(26); + cc.src_timestamp := gen_duration(26,0); + + -- TEST: UNREGISTER UNKNOWN INSTANCE + + Log("W0,W3: DDS Operation UNREGISTER_INSTANCE [TS 26s, HANDLE_NIL, Instance 4]", INFO); + Log("W0,W3: IGNORED", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := UNREGISTER_INSTANCE; + dds.cc := cc; + dds.cc.instance:= HANDLE_NIL; + dds.ret_code := RETCODE_OK; + -- WRITER 0 + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- WRITER 3 + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + + Log("W0,W3: RTPS Operation NACK_CACHE_CHANGE SN 22", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := NACK_CACHE_CHANGE; + rtps.cc.seq_nr := gen_sn(22); + -- WRITER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- WRITER 3 + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W0,W3: RTPS Operation NACK_CACHE_CHANGE SN 23", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := NACK_CACHE_CHANGE; + rtps.cc.seq_nr := gen_sn(23); + -- WRITER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- WRITER 3 + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := TRUE; + cc.kind := NOT_ALIVE_UNREGISTERED; + cc.instance := kh3; + cc.payload := gen_payload(kh3,5); + cc.seq_nr := gen_sn(26); + cc.src_timestamp := gen_duration(26,0); + + -- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE,WITHOUT ACKed SAMPLES] + + Log("W0,W3: DDS Operation UNREGISTER_INSTANCE [TS 26s, Instance 3]", INFO); + Log("W0: REJECTED [MAX_SAMPLES_PER_INSTANCE exceeded, MAX_SAMPLES exceeded]", DEBUG); + Log("W3: REJECTED [MAX_SAMPLES exceeded]", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := UNREGISTER_INSTANCE; + dds.cc := cc; + dds.ret_code := RETCODE_OUT_OF_RESOURCES; + -- WRITER 0 + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- WRITER 3 + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + + Log("W0,W3: RTPS Operation ACK_CACHE_CHANGE SN 22", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := ACK_CACHE_CHANGE; + rtps.cc.seq_nr := gen_sn(22); + -- WRITER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- WRITER 3 + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + -- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE,WITH ACKed SAMPLES, WITHOUT ACKed INSTANCE SAMPLES] + + Log("W0,W3: DDS Operation UNREGISTER_INSTANCE [TS 26s, Instance 3]", INFO); + Log("W0: REJECTED [MAX_SAMPLES_PER_INSTANCE exceeded, MAX_SAMPLES exceeded]", DEBUG); + Log("W3: ACCEPTED", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := UNREGISTER_INSTANCE; + dds.cc := cc; + -- WRITER 0 + dds.ret_code := RETCODE_OUT_OF_RESOURCES; + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- WRITER 3 + dds.ret_code := RETCODE_OK; + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- WRITER 3 + AlertIf(empty_sample_head(3) /= 33, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(3) /= 33, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(3) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 22(I2S21),0(I3S23),11(I3S24)/33 + -- PAYLOAD MEMORY: 22(I2S21),0(I3S23),11(I3S24)/33 + -- INSTANCE MEMORY: 0(I1),18(I3),9(I2)/- + + Log("W0,W3: RTPS Operation ACK_CACHE_CHANGE SN 23", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := ACK_CACHE_CHANGE; + rtps.cc.seq_nr := gen_sn(23); + -- WRITER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- WRITER 3 + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + -- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE,WITH ACKed INSTANCE SAMPLES] + + Log("W0: DDS Operation UNREGISTER_INSTANCE [TS 26s, Instance 3]", INFO); + Log("W0: ACCEPTED", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := UNREGISTER_INSTANCE; + dds.cc := cc; + dds.ret_code := RETCODE_OK; + -- WRITER 0 + ind <= 0; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + cc4 := cc; + -- WRITER 0 + AlertIf(empty_sample_head(0) /= 0, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 0, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 11(I2S22),33(I1S24),44(I3S25),22(I3S26)/0 + -- PAYLOAD MEMORY: 44(I2S22),22(I1S24),33(I3S25),11(I3S26)/0 + -- INSTANCE MEMORY: 0(I1),18(I2),9(I3)/- + + Log("W0,W3: RTPS Operation ACK_CACHE_CHANGE SN 25", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := ACK_CACHE_CHANGE; + rtps.cc.seq_nr := gen_sn(25); + -- WRITER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- WRITER 3 + rtps.ret_code := INVALID; + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := TRUE; + cc.kind := NOT_ALIVE_DISPOSED; + cc.instance := kh3; + cc.payload := gen_payload(kh3,5); + cc.seq_nr := gen_sn(27); + cc.src_timestamp := gen_duration(27,0); + + -- TEST: DISPOSE ON UNREGISTERED INSTANCE + + Log("W0,W3: DDS Operation DISPOSE [TS 27s, Instance 3]", INFO); + Log("W0,W3: ACCEPTED", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := DISPOSE; + dds.cc := cc; + dds.ret_code := RETCODE_OK; + -- WRITER 0 + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- WRITER 3 + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + cc3 := cc; + -- WRITER 0 + AlertIf(empty_sample_head(0) /= 44, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 33, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 11(I2S22),33(I1S24),22(I3S26),0(I3S27)/44 + -- PAYLOAD MEMORY: 44(I2S22),22(I1S24),11(I3S26),0(I3S27)/33 + -- INSTANCE MEMORY: 0(I1),18(I2),9(I3)/- + -- WRITER 3 + AlertIf(empty_sample_head(3) /= 0, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(3) /= 0, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(3) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 22(I2S21),11(I3S24),33(I3S25)/0 + -- PAYLOAD MEMORY: 22(I2S21),11(I3S24),33(I3S25)/0 + -- INSTANCE MEMORY: 0(I1),18(I3),9(I2)/- + + Log("W0,W3: RTPS Operation ACK_CACHE_CHANGE SN 26", INFO); + Log("W3: INVALID", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := ACK_CACHE_CHANGE; + rtps.cc.seq_nr := gen_sn(26); + -- WRITER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- WRITER 3 + rtps.ret_code := INVALID; + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W0: RTPS Operation ACK_CACHE_CHANGE SN 27", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := ACK_CACHE_CHANGE; + rtps.cc.seq_nr := gen_sn(27); + -- WRITER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh4; + cc.payload := gen_payload(kh4,10); + cc.seq_nr := gen_sn(28); + cc.src_timestamp := gen_duration(28,0); + + Log("W0,W3: DDS Operation REGISTER_INSTANCE 4", INFO); + Log("W0: ACCEPTED", DEBUG); + Log("W0: REJECTED [MAX_INSTANCES exceeded]", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := REGISTER_INSTANCE; + dds.cc := cc; + dds.ret_code := RETCODE_OK; + -- WRITER 0 + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- WRITER 3 + dds.cc.instance := HANDLE_NIL; + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- WRITER 0 + AlertIf(empty_sample_head(0) /= 44, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 0, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 11(I2S22),33(I1S24)/44,22,0 + -- PAYLOAD MEMORY: 44(I2S22),22(I1S24)/0,11,33 + -- INSTANCE MEMORY: 9(I4),0(I1),18(I2)/- + + -- VALIDATE STATE + + Log("W0,W3: RTPS Operation GET_MIN_SN", INFO); + Log("W0: Expected SN 22", DEBUG); + Log("W0: Expected SN 21", DEBUG); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_MIN_SN; + -- WRITER 0 + rtps.cc.seq_nr := gen_sn(22); + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- WRITER 3 + rtps.cc.seq_nr := gen_sn(21); + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W0,W3: RTPS Operation GET_MAX_SN", INFO); + Log("W0: Expected SN 24", DEBUG); + Log("W3: Expected SN 25", DEBUG); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_MAX_SN; + -- WRITER 0 + rtps.cc.seq_nr := gen_sn(24); + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- WRITER 3 + rtps.cc.seq_nr := gen_sn(25); + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W0,W3: RTPS Operation GET_CACHE_CHANGE SN 22", INFO); + Log("W3: INVALID", DEBUG); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_CACHE_CHANGE; + rtps.cc := cc1; + -- WRITER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- WRITER 3 + rtps.ret_code := INVALID; + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W0,W3: RTPS Operation GET_CACHE_CHANGE SN 24", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_CACHE_CHANGE; + -- WRITER 0 + rtps.cc := cc2; + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- WRITER 3 + rtps.cc := cc4; + rtps.cc.seq_nr := gen_sn(24); + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W0: RTPS Operation NACK_CACHE_CHANGE SN 22", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := NACK_CACHE_CHANGE; + rtps.cc.seq_nr := gen_sn(22); + -- WRITER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W0,W3: RTPS Operation NACK_CACHE_CHANGE SN 24", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := NACK_CACHE_CHANGE; + rtps.cc.seq_nr := gen_sn(24); + -- WRITER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- WRITER 3 + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W0,W3: DDS Operation WRITE [TS 28s, Instance 4, Aligned Payload]", INFO); + Log("W0: ACCEPTED", DEBUG); + Log("W3: REJECTED [BAD PARAMETER, Instance 4 not registered]", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := WRITE; + dds.cc := cc; + -- WRITER 0 + dds.ret_code := RETCODE_OK; + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- WRITER 3 + dds.ret_code := RETCODE_BAD_PARAMETER; + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + cc3 := cc; + -- WRITER 0 + AlertIf(empty_sample_head(0) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 11, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 11(I2S22),33(I1S24),44(I4S28)/22,0 + -- PAYLOAD MEMORY: 44(I2S22),22(I1S24),0(I4S28)/11,33 + -- INSTANCE MEMORY: 9(I4),0(I1),18(I2)/- + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh2; + cc.payload := gen_payload(kh2,10); + cc.seq_nr := gen_sn(29); + cc.src_timestamp := gen_duration(29,0); + + Log("W0,W3: DDS Operation WRITE [TS 29s, Instance 2, Aligned Payload]", INFO); + Log("W0: ACCEPTED", DEBUG); + Log("W3: REJECTED [MAX_INSTANCES exceeded, MAX_SAMPLES exceeded]", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := WRITE; + dds.cc := cc; + -- WRITER 0 + dds.ret_code := RETCODE_OK; + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- WRITER 3 + dds.ret_code := RETCODE_OUT_OF_RESOURCES; + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + cc4 := cc; + -- WRITER 0 + AlertIf(empty_sample_head(0) /= 0, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 33, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 11(I2S22),33(I1S24),44(I4S28),22(I2S29)/0 + -- PAYLOAD MEMORY: 44(I2S22),22(I1S24),0(I4S28),11(I2S29)/33 + -- INSTANCE MEMORY: 9(I4),0(I1),18(I2)/- + + Log("W0,W3: RTPS Operation ACK_CACHE_CHANGE SN 24", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := ACK_CACHE_CHANGE; + rtps.cc.seq_nr := gen_sn(24); + -- WRITER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- WRITER 3 + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W0,W3: RTPS Operation ACK_CACHE_CHANGE SN 28", INFO); + Log("W3: INVALID", DEBUG); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := ACK_CACHE_CHANGE; + rtps.cc.seq_nr := gen_sn(28); + -- WRITER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- WRITER 3 + rtps.ret_code := INVALID; + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh1; + cc.payload := gen_payload(kh1,10); + cc.seq_nr := gen_sn(30); + cc.src_timestamp := gen_duration(30,0); + + -- TEST: ADD SAMPLE ON MAX_SAMPLES [KNOWN INSTANCE,WITH ACKed SAMPLES (>1)] + + Log("W0,W3: DDS Operation WRITE [TS 30s, Instance 1, Aligned Payload]", INFO); + Log("W0,W3: ACCEPTED", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := WRITE; + dds.cc := cc; + dds.ret_code := RETCODE_OK; + -- WRITER 0 + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- WRITER 3 + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + cc2 := cc; + -- WRITER 0 + AlertIf(empty_sample_head(0) /= 33, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 22, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 11(I2S22),44(I4S28),22(I2S29),0(I1S30)/33 + -- PAYLOAD MEMORY: 44(I2S22),0(I4S28),11(I2S29),33(I1S30)/22 + -- INSTANCE MEMORY: 9(I4),0(I1),18(I2)/- + -- WRITER 3 + AlertIf(empty_sample_head(3) /= 11, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(3) /= 11, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(3) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 22(I2S21),33(I3S25),0(I1S26)/11 + -- PAYLOAD MEMORY: 22(I2S21),33(I3S25),0(I1S26)/11 + -- INSTANCE MEMORY: 0(I1),18(I3),9(I2)/- + + Log("W0: RTPS Operation REMOVE_CACHE_CHANGE SN 28", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := REMOVE_CACHE_CHANGE; + rtps.cc.seq_nr := gen_sn(28); + -- WRITER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + AlertIf(empty_sample_head(0) /= 33, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 0, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 11(I2S22),22(I2S29),0(I1S30)/33,44 + -- PAYLOAD MEMORY: 44(I2S22),11(I2S29),33(I1S30)/0,22 + -- INSTANCE MEMORY: 9(I4),0(I1),18(I2)/- + + Log("W0: RTPS Operation ACK_CACHE_CHANGE SN 22", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := ACK_CACHE_CHANGE; + rtps.cc.seq_nr := gen_sn(22); + -- WRITER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W0: RTPS Operation ACK_CACHE_CHANGE SN 29", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := ACK_CACHE_CHANGE; + rtps.cc.seq_nr := gen_sn(29); + -- WRITER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh2; + cc.payload := gen_payload(kh2,10); + cc.seq_nr := gen_sn(31); + cc.src_timestamp := gen_duration(31,0); + + -- TEST: ADD SAMPLE ON MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE, WITH ACKed INSTANCE SAMPLES(>1)] + + Log("W0,W3: DDS Operation WRITE [TS 31s, Instance 2, Aligned Payload]", INFO); + Log("W0: ACCEPTED", DEBUG); + Log("W3: REJECTED [MAX_SAMPLES exceeded]", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := WRITE; + dds.cc := cc; + -- WRITER 0 + dds.ret_code := RETCODE_OK; + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- WRITER 3 + dds.ret_code := RETCODE_OUT_OF_RESOURCES; + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + cc1 := cc; + AlertIf(empty_sample_head(0) /= 44, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 22(I2S29),0(I1S30),33(I2S31)/44,11 + -- PAYLOAD MEMORY: 11(I2S29),33(I1S30),0(I2S31)/44,22 + -- INSTANCE MEMORY: 9(I4),0(I1),18(I2)/- + + -- VALIDATE STATE + + Log("W0,W3: RTPS Operation GET_MIN_SN", INFO); + Log("W0: Expected SN 29", DEBUG); + Log("W3: Expected SN 21", DEBUG); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_MIN_SN; + -- WRITER 0 + rtps.cc.seq_nr := gen_sn(29); + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- WRITER 3 + rtps.cc.seq_nr := gen_sn(21); + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W0: RTPS Operation GET_MAX_SN", INFO); + Log("W0: Expected SN 31", DEBUG); + Log("W3: Expected SN 26", DEBUG); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_MAX_SN; + -- WRITER 0 + rtps.cc.seq_nr := gen_sn(31); + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- WRITER 3 + rtps.cc.seq_nr := gen_sn(26); + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W0: RTPS Operation GET_CACHE_CHANGE SN 29", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_CACHE_CHANGE; + rtps.cc := cc4; + -- WRITER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W0: RTPS Operation GET_CACHE_CHANGE SN 30", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_CACHE_CHANGE; + rtps.cc := cc2; + -- WRITER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W0: RTPS Operation GET_CACHE_CHANGE SN 31", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_CACHE_CHANGE; + rtps.cc := cc1; + -- WRITER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh1; + cc.payload := gen_payload(kh1,10); + cc.seq_nr := gen_sn(1); + cc.src_timestamp := gen_duration(1,0); + + -- TEST: INSTANCE LOOKUP [KNOWN INSTANCE] + + Log("W0,W3: DDS Operation LOOKUP_INSTANCE [Instance 1]", INFO); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := LOOKUP_INSTANCE; + dds.cc := cc; + dds.ret_code := RETCODE_OK; + -- WRITER 0 + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- WRITER 3 + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh3; + cc.payload := gen_payload(kh3,10); + cc.seq_nr := gen_sn(1); + cc.src_timestamp := gen_duration(1,0); + + -- TEST: INSTANCE LOOKUP [UNKNOWN INSTANCE] + + Log("W0: DDS Operation LOOKUP_INSTANCE [Unknown Instance]", INFO); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := LOOKUP_INSTANCE; + dds.cc := cc; + dds.cc.instance:= HANDLE_NIL; + -- WRITER 0 + ind <= 0; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + + -- *WRITER 1* + Log("*WRITER 1*", INFO); + AlertIf(empty_sample_head(1) /= 0, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(1) /= 0, "Payload Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: -/0,11,22,33,44 + -- PAYLOAD MEMORY: -/0,11,22,33,44 + + -- TEST: GET_MIN_SN/GET_MAX_SN ON EMPTY + + Log("W1: RTPS Operation GET_MIN_SN ", INFO); + Log("W1: Expected SEQUENCENUMBER_UNKNOWN", DEBUG); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_MIN_SN; + rtps.cc.seq_nr := SEQUENCENUMBER_UNKNOWN; + ind <= 1; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W1: RTPS Operation GET_MAX_SN", INFO); + Log("W1: Expected SEQUENCENUMBER_UNKNOWN", DEBUG); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_MAX_SN; + rtps.cc.seq_nr := SEQUENCENUMBER_UNKNOWN; + ind <= 1; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + -- TEST: WRITE ALIGNED PAYLOAD + -- TEST: NORMAL WRITE + -- TEST: ADD SAMPLE WITH KEY_HASH + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh1; + cc.payload := gen_payload(kh1,10); + cc.seq_nr := gen_sn(1); + cc.src_timestamp := gen_duration(1,0); + + Log("W1: DDS Operation WRITE [TS 1s, Aligned Payload, Key Hash /= HANDLE_NIL]", INFO); + Log("W1: REJECTED [Key Hash /= HANDLE_NIL]", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := WRITE; + dds.cc := cc; + dds.ret_code := RETCODE_BAD_PARAMETER; + ind <= 1; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + + -- TEST: ADD SAMPLE WITH HANDLE_NIL + + Log("W1: DDS Operation WRITE [TS 1s, Aligned Payload]", INFO); + Log("W1: ACCEPTED", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := WRITE; + dds.cc := cc; + dds.cc.instance:= HANDLE_NIL; + dds.ret_code := RETCODE_OK; + ind <= 1; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + cc1 := cc; + AlertIf(empty_sample_head(1) /= 11, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(1) /= 11, "Payload Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(S1)/11,22,33,44 + -- PAYLOAD MEMORY: 0(S1)/11,22,33,44 + + -- TEST: GET_MIN_SN/GET_MAX_SN ON 1 SAMPLE + + Log("W1: RTPS Operation GET_MIN_SN", INFO); + Log("W1: Expected SN 1", DEBUG); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_MIN_SN; + rtps.cc.seq_nr := gen_sn(1); + ind <= 1; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W1: RTPS Operation GET_MAX_SN", INFO); + Log("W1: Expected SN 1", DEBUG); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_MAX_SN; + rtps.cc.seq_nr := gen_sn(1); + ind <= 1; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + -- TEST: WRITE UNALIGNED PAYLOAD [>1 SLOT] + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh1; + cc.payload := gen_payload(kh1,18); + cc.seq_nr := gen_sn(2); + cc.src_timestamp := gen_duration(2,0); + + Log("W1: DDS Operation WRITE [TS 2s, Unaligned Payload (2 Slots)]", INFO); + Log("W1: ACCEPTED", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := WRITE; + dds.cc := cc; + dds.cc.instance:= HANDLE_NIL; + dds.ret_code := RETCODE_OK; + ind <= 1; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + cc2 := cc; + AlertIf(empty_sample_head(1) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(1) /= 33, "Payload Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(S1),11(S2)/22,33,44 + -- PAYLOAD MEMORY: 0(S1),11(S2),22(S2)/33,44 + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh2; + cc.payload := gen_payload(kh2,10); + cc.seq_nr := gen_sn(3); + cc.src_timestamp := gen_duration(3,0); + + -- TEST: NORMAL REGISTER + + Log("W1: DDS Operation REGISTER_INSTANCE 2", INFO); + Log("W1: Illegal Operation", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := REGISTER_INSTANCE; + dds.cc := cc; + dds.cc.instance:= HANDLE_NIL; + ind <= 1; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + + -- TEST: NORMAL DISPOSE + -- TEST: WRITE UNALIGNED PAYLOAD [<1 SLOT] + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := TRUE; + cc.kind := NOT_ALIVE_DISPOSED; + cc.instance := kh1; + cc.payload := gen_payload(kh1,5); + cc.seq_nr := gen_sn(3); + cc.src_timestamp := gen_duration(3,0); + + Log("W1: DDS Operation DISPOSE [TS 3s, Key Hash /= HANDLE_NIL]", INFO); + Log("W1: REJECTED [Key Hash /= HANDLE_NIL]", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := DISPOSE; + dds.cc := cc; + dds.ret_code := RETCODE_BAD_PARAMETER; + ind <= 1; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + + Log("W1: DDS Operation DISPOSE [TS 3s]", INFO); + Log("W1: ACCEPTED", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := DISPOSE; + dds.cc := cc; + dds.cc.instance:= HANDLE_NIL; + dds.ret_code := RETCODE_OK; + ind <= 1; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + cc3 := cc; + AlertIf(empty_sample_head(1) /= 33, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(1) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(S1),11(S2),22(S3)/33,44 + -- PAYLOAD MEMORY: 0(S1),11(S2),22(S2),33(S3)/44 + + -- TEST: GET_MIN_SN/GET_MAX_SN ON >1 SAMPLE + + Log("W1: RTPS Operation GET_MIN_SN", INFO); + Log("W1: Expected SN 1", DEBUG); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_MIN_SN; + rtps.cc.seq_nr := gen_sn(1); + ind <= 1; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W1: RTPS Operation GET_MAX_SN", INFO); + Log("W1: Expected SN 3", DEBUG); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_MAX_SN; + rtps.cc.seq_nr := gen_sn(3); + ind <= 1; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + -- TEST: GET_CACHE_CHANGE [UNKNOWN SN] + + Log("W1: RTPS Operation GET_CACHE_CHANGE SN 4", INFO); + Log("W1: Invalid", DEBUG); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_CACHE_CHANGE; + rtps.cc.seq_nr := gen_sn(4); + rtps.ret_code := INVALID; + ind <= 1; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + -- TEST: GET_CACHE_CHANGE [KNOWN SN, ALIGNED PAYLOAD] + + Log("W1: RTPS Operation GET_CACHE_CHANGE SN 1", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_CACHE_CHANGE; + rtps.cc := cc1; + rtps.cc.instance := HANDLE_NIL; + ind <= 1; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + -- TEST: GET_CACHE_CHANGE [KNOWN SN, UNALIGNED PAYLOAD, >1 SLOT] + + Log("W1: RTPS Operation GET_CACHE_CHANGE SN 2", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_CACHE_CHANGE; + rtps.cc := cc2; + rtps.cc.instance := HANDLE_NIL; + ind <= 1; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + -- TEST: GET_CACHE_CHANGE [KNOWN SN, UNALIGNED PAYLOAD, <1 SLOT] + + Log("W1: RTPS Operation GET_CACHE_CHANGE SN 3", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_CACHE_CHANGE; + rtps.cc := cc3; + rtps.cc.instance := HANDLE_NIL; + ind <= 1; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh1; + cc.payload := gen_payload(kh1,10); + cc.seq_nr := gen_sn(4); + cc.src_timestamp := gen_duration(4,0); + + -- TEST: WRITE ON DISPOSED INSTANCE + + Log("W1: DDS Operation WRITE [TS 2s, Aligned Payload]", INFO); + Log("W1: ACCEPTED", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := WRITE; + dds.cc := cc; + dds.cc.instance:= HANDLE_NIL; + dds.ret_code := RETCODE_OK; + ind <= 1; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + cc4 := cc; + AlertIf(empty_sample_head(1) /= 44, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(1) /= 54, "Payload Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(S1),11(S2),22(S3),33(S4)/44 + -- PAYLOAD MEMORY: 0(S1),11(S2),22(S2),33(S3),44(S4)/- + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := TRUE; + cc.kind := NOT_ALIVE_UNREGISTERED; + cc.instance := kh1; + cc.payload := gen_payload(kh1,5); + cc.seq_nr := gen_sn(5); + cc.src_timestamp := gen_duration(5,0); + + -- TEST: UNREGISTER INSTANCE ON PAYLOAD MEMORY FULL [WITHOUT ACKed SAMPLES] + + Log("W1: DDS Operation UNREGISTER_INSTANCE [TS 5s]", INFO); + Log("W1: REJECTED [Payload Memory Full]", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := UNREGISTER_INSTANCE; + dds.cc := cc; + dds.cc.instance:= HANDLE_NIL; + dds.ret_code := RETCODE_OUT_OF_RESOURCES; + ind <= 1; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + + -- TEST: NORMAL ACK_CACHE_CHANGE + + Log("W1: RTPS Operation ACK_CACHE_CHANGE SN 1", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := ACK_CACHE_CHANGE; + rtps.cc.seq_nr := gen_sn(1); + ind <= 1; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + -- TEST: UNREGISTER INSTANCE ON PAYLOAD MEMORY FULL [WITH ACKed SAMPLES] + -- TEST: NORMAL UNREGISTER + + Log("W1: DDS Operation UNREGISTER_INSTANCE [TS 5s, Key Hash /= HANDLE_NIL]", INFO); + Log("W1: REJECTED [Key Hash /= HANDLE_NIL]", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := UNREGISTER_INSTANCE; + dds.cc := cc; + dds.ret_code := RETCODE_BAD_PARAMETER; + ind <= 1; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + + Log("W1: DDS Operation UNREGISTER_INSTANCE [TS 5s]", INFO); + Log("W1: ACCEPTED", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := UNREGISTER_INSTANCE; + dds.cc := cc; + dds.cc.instance:= HANDLE_NIL; + dds.ret_code := RETCODE_OK; + ind <= 1; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + cc1 := cc; + AlertIf(empty_sample_head(1) /= 0, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(1) /= 54, "Payload Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 11(S2),22(S3),33(S4),44(S5)/0 + -- PAYLOAD MEMORY: 11(S2),22(S2),33(S3),44(S4),0(S5)/- + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh1; + cc.payload := gen_payload(kh1,10); + cc.seq_nr := gen_sn(6); + cc.src_timestamp := gen_duration(6,0); + + -- TEST: WRITE ON PAYLOAD MEMORY FULL [WITHOUT ACKed SAMPLES] + + Log("W1: DDS Operation WRITE [TS 6s, Aligned Payload]", INFO); + Log("W1: REJECTED [Payload Memory Full]", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := WRITE; + dds.cc := cc; + dds.cc.instance:= HANDLE_NIL; + dds.ret_code := RETCODE_OUT_OF_RESOURCES; + ind <= 1; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + + Log("W1: RTPS Operation ACK_CACHE_CHANGE SN 2", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := ACK_CACHE_CHANGE; + rtps.cc.seq_nr := gen_sn(2); + ind <= 1; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W1: RTPS Operation ACK_CACHE_CHANGE SN 3", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := ACK_CACHE_CHANGE; + rtps.cc.seq_nr := gen_sn(3); + ind <= 1; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + -- TEST: NORMAL NACK_CACHE_CHANGE + + Log("W1: RTPS Operation NACK_CACHE_CHANGE SN 2", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := NACK_CACHE_CHANGE; + rtps.cc.seq_nr := gen_sn(2); + ind <= 1; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + -- TEST: WRITE ON PAYLOAD MEMORY FULL [WITH ACKed SAMPLES] + -- TEST: WRITE ON UNREGISTERED INSTANCE + + Log("W1: DDS Operation WRITE [TS 6s, Aligned Payload]", INFO); + Log("W1: ACCEPTED", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := WRITE; + dds.cc := cc; + dds.cc.instance:= HANDLE_NIL; + dds.ret_code := RETCODE_OK; + ind <= 1; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + cc3 := cc; + AlertIf(empty_sample_head(1) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(1) /= 54, "Payload Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 11(S2),33(S4),44(S5),0(S6)/22 + -- PAYLOAD MEMORY: 11(S2),22(S2),44(S4),0(S5),33(S6)/- + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := TRUE; + cc.kind := NOT_ALIVE_DISPOSED; + cc.instance := kh1; + cc.payload := gen_payload(kh1,5); + cc.seq_nr := gen_sn(7); + cc.src_timestamp := gen_duration(7,0); + + -- TEST: DISPOSE ON PAYLOAD MEMORY FULL [WITHOUT ACKed SAMPLES] + + Log("W1: DDS Operation DISPOSE [TS 7s]", INFO); + Log("W1: REJECTED [Payload Memory Full]", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := DISPOSE; + dds.cc := cc; + dds.cc.instance:= HANDLE_NIL; + dds.ret_code := RETCODE_OUT_OF_RESOURCES; + ind <= 1; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + + Log("W1: RTPS Operation ACK_CACHE_CHANGE SN 2", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := ACK_CACHE_CHANGE; + rtps.cc.seq_nr := gen_sn(2); + ind <= 1; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + -- TEST: ACK_CACHE_CHANGE [ALREADY ACKed SN] + + Log("W1: RTPS Operation ACK_CACHE_CHANGE SN 2", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := ACK_CACHE_CHANGE; + rtps.cc.seq_nr := gen_sn(2); + ind <= 1; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + -- TEST: DISPOSE ON PAYLOAD MEMORY FULL [WITH ACKed SAMPLES] + + Log("W1: DDS Operation DISPOSE [TS 7s]", INFO); + Log("W1: ACCEPTED", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := DISPOSE; + dds.cc := cc; + dds.cc.instance:= HANDLE_NIL; + dds.ret_code := RETCODE_OK; + ind <= 1; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + cc2 := cc; + AlertIf(empty_sample_head(1) /= 11, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(1) /= 22, "Payload Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 33(S4),44(S5),0(S6),22(S7)/11 + -- PAYLOAD MEMORY: 44(S4),0(S5),33(S6),11(S7)/22 + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := TRUE; + cc.kind := NOT_ALIVE_UNREGISTERED; + cc.instance := kh1; + cc.payload := gen_payload(kh1,5); + cc.seq_nr := gen_sn(8); + cc.src_timestamp := gen_duration(8,0); + + -- TEST: ADD SAMPLE ON MAX_SAMPLES [KNOWN INSTANCE,WITHOUT ACKed SAMPLES] + + Log("W1: DDS Operation UNREGISTER_INSTANCE [TS 8s]", INFO); + Log("W1: REJECTED [MAX_SAMPLES exceeded]", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := UNREGISTER_INSTANCE; + dds.cc := cc; + dds.cc.instance:= HANDLE_NIL; + dds.ret_code := RETCODE_OUT_OF_RESOURCES; + ind <= 1; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + + Log("W1: RTPS Operation ACK_CACHE_CHANGE SN 5", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := ACK_CACHE_CHANGE; + rtps.cc.seq_nr := gen_sn(5); + ind <= 1; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + -- TEST: ADD SAMPLE ON MAX_SAMPLES [KNOWN INSTANCE,WITH ACKed SAMPLES] + -- TEST: UNREGISTER ON DISPOSED INSTANCE + + Log("W1: DDS Operation UNREGISTER_INSTANCE [TS 8s]", INFO); + Log("W1: ACCEPTED", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := UNREGISTER_INSTANCE; + dds.cc := cc; + dds.cc.instance:= HANDLE_NIL; + dds.ret_code := RETCODE_OK; + ind <= 1; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + cc1 := cc; + AlertIf(empty_sample_head(1) /= 44, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(1) /= 0, "Payload Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 33(S4),0(S6),22(S7),11(S8)/44 + -- PAYLOAD MEMORY: 44(S4),33(S6),11(S7),22(S8)/0 + + -- VALIDATE STATE + + Log("W1: RTPS Operation GET_MIN_SN", INFO); + Log("W1: Expected SN 4", DEBUG); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_MIN_SN; + rtps.cc.seq_nr := gen_sn(4); + ind <= 1; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W1: RTPS Operation GET_MAX_SN", INFO); + Log("W1: Expected SN 8", DEBUG); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_MAX_SN; + rtps.cc.seq_nr := gen_sn(8); + ind <= 1; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W1: RTPS Operation GET_CACHE_CHANGE SN 4", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_CACHE_CHANGE; + rtps.cc := cc4; + rtps.cc.instance := HANDLE_NIL; + ind <= 1; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W1: RTPS Operation GET_CACHE_CHANGE SN 6", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_CACHE_CHANGE; + rtps.cc := cc3; + rtps.cc.instance := HANDLE_NIL; + ind <= 1; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W1: RTPS Operation GET_CACHE_CHANGE SN 7", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_CACHE_CHANGE; + rtps.cc := cc2; + rtps.cc.instance := HANDLE_NIL; + ind <= 1; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W1: RTPS Operation GET_CACHE_CHANGE SN 8", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_CACHE_CHANGE; + rtps.cc := cc1; + rtps.cc.instance := HANDLE_NIL; + ind <= 1; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W1: RTPS Operation ACK_CACHE_CHANGE SN 6", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := ACK_CACHE_CHANGE; + rtps.cc.seq_nr := gen_sn(6); + ind <= 1; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W1: RTPS Operation ACK_CACHE_CHANGE SN 8", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := ACK_CACHE_CHANGE; + rtps.cc.seq_nr := gen_sn(8); + ind <= 1; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := TRUE; + cc.kind := NOT_ALIVE_DISPOSED; + cc.instance := kh1; + cc.payload := gen_payload(kh1,5); + cc.seq_nr := gen_sn(9); + cc.src_timestamp := gen_duration(9,0); + + -- TEST: ADD SAMPLE ON MAX_SAMPLES [KNOWN INSTANCE,WITH ACKed SAMPLES (>1)] + + Log("W1: DDS Operation DISPOSE [TS 9s]", INFO); + Log("W1: ACCEPTED", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := DISPOSE; + dds.cc := cc; + dds.cc.instance:= HANDLE_NIL; + dds.ret_code := RETCODE_OK; + ind <= 1; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + cc3 := cc; + AlertIf(empty_sample_head(1) /= 0, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(1) /= 33, "Payload Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 33(S4),22(S7),11(S8),44(S9)/0 + -- PAYLOAD MEMORY: 44(S4),11(S7),22(S8),0(S9)/33 + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := TRUE; + cc.kind := NOT_ALIVE_UNREGISTERED; + cc.instance := kh1; + cc.payload := gen_payload(kh1,5); + cc.seq_nr := gen_sn(10); + cc.src_timestamp := gen_duration(10,0); + + -- TEST: DISPOSE ON UNREGISTERED INSTANCE + + Log("W1: DDS Operation UNREGISTER_INSTANCE [TS 10s]", INFO); + Log("W1: ACCEPTED", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := UNREGISTER_INSTANCE; + dds.cc := cc; + dds.cc.instance:= HANDLE_NIL; + dds.ret_code := RETCODE_OK; + ind <= 1; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + cc1 := cc; + AlertIf(empty_sample_head(1) /= 11, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(1) /= 22, "Payload Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 33(S4),22(S7),44(S9),0(S10)/11 + -- PAYLOAD MEMORY: 44(S4),11(S7),0(S9),33(S10)/22 + + Log("W1: RTPS Operation ACK_CACHE_CHANGE SN 7", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := ACK_CACHE_CHANGE; + rtps.cc.seq_nr := gen_sn(7); + ind <= 1; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh1; + cc.payload := gen_payload(kh1,20); + cc.seq_nr := gen_sn(11); + cc.src_timestamp := gen_duration(11,0); + + -- TEST: ADD SAMPLE BIGGER THAN AVAILABLE MEMORY SPACE [WITH ACKed SAMPLES] + + Log("W1: DDS Operation WRITE [TS 11s, Aligned Payload (2 Slots)]", INFO); + Log("W1: REJECTED [Payload Memory Full]", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := WRITE; + dds.cc := cc; + dds.cc.instance:= HANDLE_NIL; + dds.ret_code := RETCODE_OUT_OF_RESOURCES; + ind <= 1; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + + -- TEST: REMOVE_CACHE_CHANGE [UNKNOWN SN] + + Log("W1: RTPS Operation REMOVE_CACHE_CHANGE SN 12", INFO); + Log("W1: Invalid", DEBUG); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := REMOVE_CACHE_CHANGE; + rtps.cc.seq_nr := gen_sn(12); + rtps.ret_code := INVALID; + ind <= 1; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + -- TEST: REMOVE_CACHE_CHANGE [KNOWN SN] + + Log("W1: RTPS Operation REMOVE_CACHE_CHANGE SN 4", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := REMOVE_CACHE_CHANGE; + rtps.cc.seq_nr := gen_sn(4); + ind <= 1; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + AlertIf(empty_sample_head(1) /= 11, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(1) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 22(S7),44(S9),0(S10)/11,33 + -- PAYLOAD MEMORY: 11(S7),0(S9),33(S10)/44,22 + + Log("W1: DDS Operation WRITE [TS 11s, Aligned Payload (2 Slots)]", INFO); + Log("W1: ACCEPTED", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := WRITE; + dds.cc := cc; + dds.cc.instance:= HANDLE_NIL; + dds.ret_code := RETCODE_OK; + ind <= 1; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + cc4 := cc; + AlertIf(empty_sample_head(1) /= 33, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(1) /= 54, "Payload Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 22(S7),44(S9),0(S10),11(S11)/33 + -- PAYLOAD MEMORY: 11(S7),0(S9),33(S10),44(S11),22(S11)/- + + -- VALIDATE STATE + + Log("W1: RTPS Operation GET_MIN_SN", INFO); + Log("W1: Expected SN 7", DEBUG); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_MIN_SN; + rtps.cc.seq_nr := gen_sn(7); + ind <= 1; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W1: RTPS Operation GET_MAX_SN", INFO); + Log("W1: Expected SN 11", DEBUG); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_MAX_SN; + rtps.cc.seq_nr := gen_sn(11); + ind <= 1; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W1: RTPS Operation GET_CACHE_CHANGE SN 7", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_CACHE_CHANGE; + rtps.cc := cc2; + rtps.cc.instance := HANDLE_NIL; + ind <= 1; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W1: RTPS Operation GET_CACHE_CHANGE SN 9", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_CACHE_CHANGE; + rtps.cc := cc3; + rtps.cc.instance := HANDLE_NIL; + ind <= 1; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W1: RTPS Operation GET_CACHE_CHANGE SN 10", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_CACHE_CHANGE; + rtps.cc := cc1; + rtps.cc.instance := HANDLE_NIL; + ind <= 1; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W1: RTPS Operation GET_CACHE_CHANGE SN 11", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_CACHE_CHANGE; + rtps.cc := cc4; + rtps.cc.instance := HANDLE_NIL; + ind <= 1; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + -- TEST: INSTANCE LOOKUP [KNOWN INSTANCE] + + Log("W1: DDS Operation LOOKUP_INSTANCE", INFO); + Log("W1: Illegal Operation", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := LOOKUP_INSTANCE; + dds.cc := cc; + dds.cc.instance:= HANDLE_NIL; + ind <= 1; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + + -- *WRITER 2* + Log("*WRITER 2*", INFO); + AlertIf(empty_sample_head(2) /= 0, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(2) /= 0, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(2) /= 0, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: -/0,11,22,33,44 + -- PAYLOAD MEMORY: -/0,10,20,30,40 + -- INSTANCE MEMORY: -/0,9,18 + + -- TEST: GET_MIN_SN/GET_MAX_SN ON EMPTY + + Log("W2: RTPS Operation GET_MIN_SN", INFO); + Log("W2: Expected SEQUENCENUMBER_UNKNOWN", DEBUG); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_MIN_SN; + rtps.cc.seq_nr := SEQUENCENUMBER_UNKNOWN; + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W2: RTPS Operation GET_MAX_SN", INFO); + Log("W2: Expected SEQUENCENUMBER_UNKNOWN", DEBUG); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_MAX_SN; + rtps.cc.seq_nr := SEQUENCENUMBER_UNKNOWN; + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + -- TEST: ADD SAMPLE WITH KEY_HASH [UNKNOWN INSTANCE] + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh1; + cc.payload := gen_payload(kh1,9); + cc.seq_nr := gen_sn(1); + cc.src_timestamp := gen_duration(1,0); + + Log("W2: DDS Operation WRITE [TS 1s, Instance 1, Aligned Payload]", INFO); + Log("W2: REJECTED [Instance not Registered]", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := WRITE; + dds.cc := cc; + dds.ret_code := RETCODE_BAD_PARAMETER; + ind <= 2; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + + -- TEST: ADD SAMPLE WITH HANDLE_NIL [UNKNOWN INSTANCE] + -- TEST: NORMAL WRITE + -- TEST: WRITE ALIGNED PAYLOAD + + Log("W2: DDS Operation WRITE [TS 1s, Instance 1, HANDLE_NIL, Aligned Payload]", INFO); + Log("W2: ACCEPTED", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := WRITE; + dds.cc := cc; + dds.cc.instance:= HANDLE_NIL; + dds.ret_code := RETCODE_OK; + ind <= 2; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + cc1 := cc; + AlertIf(empty_sample_head(2) /= 11, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(2) /= 10, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(2) /= 9, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I1S1)/11,22,33,44 + -- PAYLOAD MEMORY: 0(I1S1)/10,20,30,40 + -- INSTANCE MEMORY: 0(I1)/9,18 + + -- TEST: GET_MIN_SN/GET_MAX_SN ON 1 SAMPLE + + Log("W2: RTPS Operation GET_MIN_SN", INFO); + Log("W2: Expected SN 1", DEBUG); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_MIN_SN; + rtps.cc.seq_nr := gen_sn(1); + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W2: RTPS Operation GET_MAX_SN", INFO); + Log("W2: Expected SN 1", DEBUG); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_MAX_SN; + rtps.cc.seq_nr := gen_sn(1); + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh1; + cc.payload := gen_payload(kh1,16); + cc.seq_nr := gen_sn(2); + cc.src_timestamp := gen_duration(2,0); + + -- TEST: ADD SAMPLE WITH KEY_HASH [KNOWN INSTANCE] + -- TEST: WRITE UNALIGNED PAYLOAD [>1 SLOT] + + Log("W2: DDS Operation WRITE [TS 2s, Instance 1, Unaligned Payload (2 Slot)]", INFO); + Log("W2: ACCEPTED", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := WRITE; + dds.cc := cc; + dds.ret_code := RETCODE_OK; + ind <= 2; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + cc2 := cc; + AlertIf(empty_sample_head(2) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(2) /= 30, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(2) /= 9, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I1S1),11(I1S2)/22,33,44 + -- PAYLOAD MEMORY: 0(I1S1),10(I1S2),20(I1S2)/30,40 + -- INSTANCE MEMORY: 0(I1)/9,18 + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := TRUE; + cc.kind := NOT_ALIVE_DISPOSED; + cc.instance := kh2; + cc.payload := gen_payload(kh2,5); + cc.seq_nr := gen_sn(3); + cc.src_timestamp := gen_duration(3,0); + + Log("W2: DDS Operation DISPOSE [TS 3s, Instance 2]", INFO); + Log("W2: REJECTED [Instance not Registered]", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := DISPOSE; + dds.cc := cc; + dds.ret_code := RETCODE_BAD_PARAMETER; + ind <= 2; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + + -- TEST: NORMAL REGISTER + + Log("W2: DDS Operation REGISTER_INSTANCE 2", INFO); + Log("W2: ACCEPTED", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := REGISTER_INSTANCE; + dds.cc := cc; + dds.ret_code := RETCODE_OK; + ind <= 2; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + AlertIf(empty_sample_head(2) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(2) /= 30, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(2) /= 18, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I1S1),11(I1S2)/22,33,44 + -- PAYLOAD MEMORY: 0(I1S1),10(I1S2),20(I1S2)/30,40 + -- INSTANCE MEMORY: 9(I2),0(I1)/18 + + -- TEST: NORMAL DISPOSE + -- TEST: WRITE UNALIGNED PAYLOAD [<1 SLOT] + + Log("W2: DDS Operation DISPOSE [TS 3s, Instance 2]", INFO); + Log("W2: ACCEPTED", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := DISPOSE; + dds.cc := cc; + dds.cc.instance:= HANDLE_NIL; + dds.ret_code := RETCODE_OK; + ind <= 2; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + cc3 := cc; + AlertIf(empty_sample_head(2) /= 33, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(2) /= 40, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(2) /= 18, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I1S1),11(I1S2),22(I2S3)/33,44 + -- PAYLOAD MEMORY: 0(I1S1),10(I1S2),20(I1S2),30(I2S3)/40 + -- INSTANCE MEMORY: 9(I2),0(I1)/18 + + -- TEST: GET_MIN_SN/GET_MAX_SN ON >1 SAMPLE + -- VALIDATE STATE + + Log("W2: RTPS Operation GET_MIN_SN", INFO); + Log("W2: Expected SN 1", DEBUG); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_MIN_SN; + rtps.cc.seq_nr := gen_sn(1); + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W2: RTPS Operation GET_MAX_SN", INFO); + Log("W2: Expected SN 3", DEBUG); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_MAX_SN; + rtps.cc.seq_nr := gen_sn(3); + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + -- TEST: GET_CACHE_CHANGE [UNKNOWN SN] + + Log("W2: RTPS Operation GET_CACHE_CHANGE SN 4", INFO); + Log("W2: INVALID", DEBUG); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_CACHE_CHANGE; + rtps.cc.seq_nr := gen_sn(4); + rtps.ret_code := INVALID; + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + -- TEST: GET_CACHE_CHANGE [KNOWN SN, ALIGNED PAYLOAD] + + Log("W2: RTPS Operation GET_CACHE_CHANGE SN 1", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_CACHE_CHANGE; + rtps.cc := cc1; + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + -- TEST: GET_CACHE_CHANGE [KNOWN SN, UNALIGNED PAYLOAD, >1 SLOT] + + Log("W2: RTPS Operation GET_CACHE_CHANGE SN 2", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_CACHE_CHANGE; + rtps.cc := cc2; + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + -- TEST: GET_CACHE_CHANGE [KNOWN SN, UNALIGNED PAYLOAD, <1 SLOT] + + Log("W2: RTPS Operation GET_CACHE_CHANGE SN 3", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_CACHE_CHANGE; + rtps.cc := cc3; + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh2; + cc.payload := gen_payload(kh2,9); + cc.seq_nr := gen_sn(4); + cc.src_timestamp := gen_duration(4,0); + + -- TEST: WRITE ON DISPOSED INSTANCE + -- TEST: ADD SAMPLE WITH HANDLE_NIL [KNOWN INSTANCE] + + Log("W2: DDS Operation WRITE [TS 4s, Instance 2, Aligned Payload]", INFO); + Log("W2: ACCEPTED", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := WRITE; + dds.cc := cc; + dds.cc.instance:= HANDLE_NIL; + dds.ret_code := RETCODE_OK; + ind <= 2; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + cc4 := cc; + AlertIf(empty_sample_head(2) /= 44, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(2) /= 54, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(2) /= 18, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I1S1),11(I1S2),22(I2S3),33(I2S4)/44 + -- PAYLOAD MEMORY: 0(I1S1),10(I1S2),20(I1S2),30(I2S3),40(I2S4)/- + -- INSTANCE MEMORY: 9(I2),0(I1)/18 + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh3; + cc.payload := gen_payload(kh3,9); + cc.seq_nr := gen_sn(5); + cc.src_timestamp := gen_duration(5,0); + + -- TEST: WRITE ON PAYLOAD MEMORY FULL [WITHOUT ACKed SAMPLES] + + Log("W2: DDS Operation WRITE [TS 5s, Instance 3, HANDLE_NIL, Aligned Payload]", INFO); + Log("W2: ACCEPTED", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := WRITE; + dds.cc := cc; + dds.cc.instance:= HANDLE_NIL; + dds.ret_code := RETCODE_OK; + ind <= 2; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + cc1 := cc; + AlertIf(empty_sample_head(2) /= 0, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(2) /= 54, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(2) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 11(I1S2),22(I2S3),33(I2S4),44(I3S5)/0 + -- PAYLOAD MEMORY: 10(I1S2),20(I1S2),30(I2S3),40(I2S4),0(I3S5)/- + -- INSTANCE MEMORY: 18(I3),9(I2),0(I1)/- + + -- TEST: NORMAL ACK_CACHE_CHANGE + + Log("W2: RTPS Operation ACK_CACHE_CHANGE SN 3", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := ACK_CACHE_CHANGE; + rtps.cc.seq_nr := gen_sn(3); + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh3; + cc.payload := gen_payload(kh3,9); + cc.seq_nr := gen_sn(6); + cc.src_timestamp := gen_duration(6,0); + + -- TEST: WRITE ON PAYLOAD MEMORY FULL [WITH ACKed SAMPLES] + + Log("W2: DDS Operation WRITE [TS 6s, Instance 3, Aligned Payload]", INFO); + Log("W2: ACCEPTED", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := WRITE; + dds.cc := cc; + dds.ret_code := RETCODE_OK; + ind <= 2; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + cc3 := cc; + AlertIf(empty_sample_head(2) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(2) /= 54, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(2) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 11(I1S2),33(I2S4),44(I3S5),0(I3S6)/22 + -- PAYLOAD MEMORY: 10(I1S2),20(I1S2),40(I2S4),0(I3S5),30(I3S6)/- + -- INSTANCE MEMORY: 18(I3),9(I2),0(I1)/- + + -- VALIDATE STATE + + Log("W2: RTPS Operation GET_MIN_SN", INFO); + Log("W2: Expected SN 2", DEBUG); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_MIN_SN; + rtps.cc.seq_nr := gen_sn(2); + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W2: RTPS Operation GET_MAX_SN", INFO); + Log("W2: Expected SN 6", DEBUG); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_MAX_SN; + rtps.cc.seq_nr := gen_sn(6); + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W2: RTPS Operation GET_CACHE_CHANGE SN 2", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_CACHE_CHANGE; + rtps.cc := cc2; + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W2: RTPS Operation GET_CACHE_CHANGE SN 4", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_CACHE_CHANGE; + rtps.cc := cc4; + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W2: RTPS Operation GET_CACHE_CHANGE SN 5", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_CACHE_CHANGE; + rtps.cc := cc1; + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W2: RTPS Operation GET_CACHE_CHANGE SN 6", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_CACHE_CHANGE; + rtps.cc := cc3; + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := TRUE; + cc.kind := NOT_ALIVE_DISPOSED; + cc.instance := kh1; + cc.payload := gen_payload(kh1,5); + cc.seq_nr := gen_sn(7); + cc.src_timestamp := gen_duration(7,0); + + -- TEST: DISPOSE ON PAYLOAD MEMORY FULL [WITHOUT ACKed SAMPLES] + + Log("W2: DDS Operation DISPOSE [TS 7s, Instance 1]", INFO); + Log("W2: ACCEPTED", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := DISPOSE; + dds.cc := cc; + dds.ret_code := RETCODE_OK; + ind <= 2; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + cc2 := cc; + AlertIf(empty_sample_head(2) /= 11, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(2) /= 20, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(2) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 33(I2S4),44(I3S5),0(I3S6),22(I1S7)/11 + -- PAYLOAD MEMORY: 40(I2S4),0(I3S5),30(I3S6),10(I1S7)/20 + -- INSTANCE MEMORY: 18(I3),9(I2),0(I1)/- + + Log("W2: RTPS Operation ACK_CACHE_CHANGE SN 5", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := ACK_CACHE_CHANGE; + rtps.cc.seq_nr := gen_sn(5); + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh2; + cc.payload := gen_payload(kh2,18); + cc.seq_nr := gen_sn(8); + cc.src_timestamp := gen_duration(8,0); + + -- TEST: ADD SAMPLE BIGGER THAN AVAILABLE MEMORY SPACE [WITH ACKed SAMPLES] + + Log("W2: DDS Operation WRITE [TS 8s, Instance 2, Aligned Payload (2 Slots)]", INFO); + Log("W2: REJECTED [Payload Memory Full]", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := WRITE; + dds.cc := cc; + dds.ret_code := RETCODE_OUT_OF_RESOURCES; + ind <= 2; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + + -- TEST: REMOVE_CACHE_CHANGE [UNKNOWN SN] + + Log("W2: RTPS Operation REMOVE_CACHE_CHANGE SN 3", INFO); + Log("W2: INVALID", DEBUG); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := REMOVE_CACHE_CHANGE; + rtps.cc.seq_nr := gen_sn(3); + rtps.ret_code := INVALID; + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + -- TEST: REMOVE_CACHE_CHANGE [KNOWN SN] + + Log("W2: RTPS Operation REMOVE_CACHE_CHANGE SN 5", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := REMOVE_CACHE_CHANGE; + rtps.cc.seq_nr := gen_sn(5); + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + AlertIf(empty_sample_head(2) /= 11, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(2) /= 0, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(2) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 33(I2S4),0(I3S6),22(I1S7)/11,44 + -- PAYLOAD MEMORY: 40(I2S4),30(I3S6),10(I1S7)/0,20 + -- INSTANCE MEMORY: 18(I3),9(I2),0(I1)/- + + Log("W2: DDS Operation WRITE [TS 8s, Instance 2, Aligned Payload (2 Slots)]", INFO); + Log("W2: ACCEPTED", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := WRITE; + dds.cc := cc; + dds.ret_code := RETCODE_OK; + ind <= 2; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + cc1 := cc; + AlertIf(empty_sample_head(2) /= 44, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(2) /= 54, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(2) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 33(I2S4),0(I3S6),22(I1S7),11(I2S8)/44 + -- PAYLOAD MEMORY: 40(I2S4),30(I3S6),10(I1S7),0(I2S8),20(I2S8)/- + -- INSTANCE MEMORY: 18(I3),9(I2),0(I1)/- + + Log("W2: RTPS Operation ACK_CACHE_CHANGE SN 7", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := ACK_CACHE_CHANGE; + rtps.cc.seq_nr := gen_sn(7); + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := TRUE; + cc.kind := NOT_ALIVE_DISPOSED; + cc.instance := kh3; + cc.payload := gen_payload(kh3,5); + cc.seq_nr := gen_sn(9); + cc.src_timestamp := gen_duration(9,0); + + -- TEST: DISPOSE ON PAYLOAD MEMORY FULL [WITH ACKed SAMPLES] + + Log("W2: DDS Operation DISPOSE [TS 9s, Instance 3]", INFO); + Log("W2: ACCEPTED", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := DISPOSE; + dds.cc := cc; + dds.ret_code := RETCODE_OK; + ind <= 2; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + cc2 := cc; + AlertIf(empty_sample_head(2) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(2) /= 54, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(2) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 33(I2S4),0(I3S6),11(I2S8),44(I3S9)/22 + -- PAYLOAD MEMORY: 40(I2S4),30(I3S6),0(I2S8),20(I2S8),10(I3S9)/- + -- INSTANCE MEMORY: 18(I3),9(I2),0(I1)/- + + -- VALIDATE STATE + + Log("W2: RTPS Operation GET_MIN_SN", INFO); + Log("W2: Expected SN 4", DEBUG); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_MIN_SN; + rtps.cc.seq_nr := gen_sn(4); + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W2: RTPS Operation GET_MAX_SN", INFO); + Log("W2: Expected SN 9", DEBUG); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_MAX_SN; + rtps.cc.seq_nr := gen_sn(9); + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W2: RTPS Operation GET_CACHE_CHANGE SN 4", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_CACHE_CHANGE; + rtps.cc := cc4; + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W2: RTPS Operation GET_CACHE_CHANGE SN 6", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_CACHE_CHANGE; + rtps.cc := cc3; + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W2: RTPS Operation GET_CACHE_CHANGE SN 8", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_CACHE_CHANGE; + rtps.cc := cc1; + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W2: RTPS Operation GET_CACHE_CHANGE SN 9", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_CACHE_CHANGE; + rtps.cc := cc2; + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := TRUE; + cc.kind := NOT_ALIVE_UNREGISTERED; + cc.instance := kh1; + cc.payload := gen_payload(kh1,5); + cc.seq_nr := gen_sn(10); + cc.src_timestamp := gen_duration(10,0); + + -- TEST: UNREGISTER ON DISPOSED INSTANCE + -- TEST: UNREGISTER INSTANCE ON PAYLOAD MEMORY FULL [WITHOUT ACKed SAMPLES] + + Log("W2: DDS Operation UNREGISTER_INSTANCE [TS 10s, Instance 1]", INFO); + Log("W2: ACCEPTED", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := UNREGISTER_INSTANCE; + dds.cc := cc; + dds.ret_code := RETCODE_OK; + ind <= 2; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + cc4 := cc; + AlertIf(empty_sample_head(2) /= 33, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(2) /= 54, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(2) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I3S6),11(I2S8),44(I3S9),22(I1S10)/33 + -- PAYLOAD MEMORY: 30(I3S6),0(I2S8),20(I2S8),10(I3S9),40(I1S10)/- + -- INSTANCE MEMORY: 18(I3),9(I2),0(I1)/- + + Log("W2: RTPS Operation ACK_CACHE_CHANGE SN 9", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := ACK_CACHE_CHANGE; + rtps.cc.seq_nr := gen_sn(9); + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := TRUE; + cc.kind := NOT_ALIVE_UNREGISTERED; + cc.instance := kh2; + cc.payload := gen_payload(kh2,5); + cc.seq_nr := gen_sn(11); + cc.src_timestamp := gen_duration(11,0); + + -- TEST: UNREGISTER INSTANCE ON PAYLOAD MEMORY FULL [WITH ACKed SAMPLES] + + Log("W2: DDS Operation UNREGISTER_INSTANCE [TS 11s, Instance 2]", INFO); + Log("W2: ACCEPTED", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := UNREGISTER_INSTANCE; + dds.cc := cc; + dds.ret_code := RETCODE_OK; + ind <= 2; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + cc2 := cc; + AlertIf(empty_sample_head(2) /= 44, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(2) /= 54, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(2) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I3S6),11(I2S8),22(I1S10),33(I2S11)/44 + -- PAYLOAD MEMORY: 30(I3S6),0(I2S8),20(I2S8),40(I1S10),10(I2S11)/- + -- INSTANCE MEMORY: 18(I3),9(I2),0(I1)/- + + Log("W2: RTPS Operation ACK_CACHE_CHANGE SN 6", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := ACK_CACHE_CHANGE; + rtps.cc.seq_nr := gen_sn(6); + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W2: RTPS Operation ACK_CACHE_CHANGE SN 8", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := ACK_CACHE_CHANGE; + rtps.cc.seq_nr := gen_sn(8); + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W2: RTPS Operation ACK_CACHE_CHANGE SN 11", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := ACK_CACHE_CHANGE; + rtps.cc.seq_nr := gen_sn(11); + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh4; + cc.payload := gen_payload(kh4,9); + cc.seq_nr := gen_sn(12); + cc.src_timestamp := gen_duration(12,0); + + -- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKNOWN INSTANCE, WITH STALE INSTANCE] + -- TEST: ADD SAMPLE ON PAYLOAD FULL & MAX_INSTANCES [UNKNOWN INSTANCE,WITH ACKed SAMPLES,WITH STALE INSTANCE (>= 1 SAMPLE)] (Induce Double Remove) + -- TEST: REMOVE STALE INSTANCE WITH >1 SAMPLES + + Log("W2: DDS Operation WRITE [TS 12s, Instance 4, HANDLE_NIL, Aligned Payload]", INFO); + Log("W2: ACCEPTED", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := WRITE; + dds.cc := cc; + dds.cc.instance:= HANDLE_NIL; + dds.ret_code := RETCODE_OK; + ind <= 2; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + cc1 := cc; + AlertIf(empty_sample_head(2) /= 0, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(2) /= 10, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(2) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 22(I1S10),44(I4S12)/0,11,33 + -- PAYLOAD MEMORY: 40(I1S10),30(I4S12)/10,0,20 + -- INSTANCE MEMORY: 9(I4),18(I3),0(I1)/- + + -- VALIDATE STATE + + Log("W2: RTPS Operation GET_MIN_SN", INFO); + Log("W2: Expected SN 10", DEBUG); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_MIN_SN; + rtps.cc.seq_nr := gen_sn(10); + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W2: RTPS Operation GET_MAX_SN", INFO); + Log("W2: Expected SN 12", DEBUG); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_MAX_SN; + rtps.cc.seq_nr := gen_sn(12); + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W2: RTPS Operation GET_CACHE_CHANGE SN 10", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_CACHE_CHANGE; + rtps.cc := cc4; + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W2: RTPS Operation GET_CACHE_CHANGE SN 12", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_CACHE_CHANGE; + rtps.cc := cc1; + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh2; + cc.payload := gen_payload(kh2,9); + cc.seq_nr := gen_sn(13); + cc.src_timestamp := gen_duration(13,0); + + -- TEST: REGISTER INSTANCE ON MAX_INSTANCES [UNKNOWN INSTANCE, WITHOUT STALE INSTANCE] + + Log("W2: DDS Operation REGISTER_INSTANCE 2", INFO); + Log("W2: REJECTED [MAX_INSTANCES exceeded]", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := REGISTER_INSTANCE; + dds.cc := cc; + dds.cc.instance:= HANDLE_NIL; + ind <= 2; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + + Log("W2: RTPS Operation ACK_CACHE_CHANGE SN 10", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := ACK_CACHE_CHANGE; + rtps.cc.seq_nr := gen_sn(10); + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + -- TEST: REGISTER INSTANCE ON MAX_INSTANCES [UNKNOWN INSTANCE, WITH STALE INSTANCE] + -- TEST: REMOVE STALE INSTANCE WITH 1 SAMPLES + + Log("W2: DDS Operation REGISTER_INSTANCE 2", INFO); + Log("W2: ACCEPTED", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := REGISTER_INSTANCE; + dds.cc := cc; + dds.ret_code := RETCODE_OK; + ind <= 2; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + AlertIf(empty_sample_head(2) /= 0, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(2) /= 40, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(2) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 44(I4S12)/0,11,33,22 + -- PAYLOAD MEMORY: 30(I4S12)/40,10,0,20 + -- INSTANCE MEMORY: 0(I2),9(I4),18(I3)/- + + Log("W2: DDS Operation WRITE [TS 13s, Instance 2, Aligned Payload]", INFO); + Log("W2: ACCEPTED", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := WRITE; + dds.cc := cc; + dds.ret_code := RETCODE_OK; + ind <= 2; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + cc2 := cc; + AlertIf(empty_sample_head(2) /= 11, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(2) /= 10, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(2) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 44(I4S12),0(I2S13)/11,33,22 + -- PAYLOAD MEMORY: 30(I4S12),40(I2S13)/10,0,20 + -- INSTANCE MEMORY: 0(I2),9(I4),18(I3)/- + + -- TEST: REGISTER INSTANCE [KNOWN INSTANCE] + + Log("W2: DDS Operation REGISTER_INSTANCE 2", INFO); + Log("W2: ACCEPTED", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := REGISTER_INSTANCE; + dds.cc := cc; + dds.ret_code := RETCODE_OK; + ind <= 2; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh2; + cc.payload := gen_payload(kh2,9); + cc.seq_nr := gen_sn(14); + cc.src_timestamp := gen_duration(14,0); + + Log("W2: DDS Operation WRITE [TS 14s, Instance 2, Aligned Payload]", INFO); + Log("W2: ACCEPTED", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := WRITE; + dds.cc := cc; + dds.ret_code := RETCODE_OK; + ind <= 2; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + cc3 := cc; + AlertIf(empty_sample_head(2) /= 33, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(2) /= 0, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(2) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 44(I4S12),0(I2S13),11(I2S14)/33,22 + -- PAYLOAD MEMORY: 30(I4S12),40(I2S13),10(I2S14)/0,20 + -- INSTANCE MEMORY: 0(I2),9(I4),18(I3)/- + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh2; + cc.payload := gen_payload(kh2,9); + cc.seq_nr := gen_sn(15); + cc.src_timestamp := gen_duration(15,0); + + -- TEST: ADD SAMPLE ON MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE, WITHOUT ACKed SAMPLES] + + Log("W2: DDS Operation WRITE [TS 15s, Instance 2, Aligned Payload]", INFO); + Log("W2: ACCEPTED", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := WRITE; + dds.cc := cc; + dds.ret_code := RETCODE_OK; + ind <= 2; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + cc2 := cc; + AlertIf(empty_sample_head(2) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(2) /= 40, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(2) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 44(I4S12),11(I2S14),33(I2S15)/22,0 + -- PAYLOAD MEMORY: 30(I4S12),10(I2S14),0(I2S15)/40,20 + -- INSTANCE MEMORY: 0(I2),9(I4),18(I3)/- + + Log("W2: RTPS Operation ACK_CACHE_CHANGE SN 15", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := ACK_CACHE_CHANGE; + rtps.cc.seq_nr := gen_sn(15); + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh2; + cc.payload := gen_payload(kh2,9); + cc.seq_nr := gen_sn(16); + cc.src_timestamp := gen_duration(16,0); + + -- TEST: ADD SAMPLE ON MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE, WITH ACKed INSTANCE SAMPLE] + + Log("W2: DDS Operation WRITE [TS 16s, Instance 2, Aligned Payload]", INFO); + Log("W2: ACCEPTED", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := WRITE; + dds.cc := cc; + dds.ret_code := RETCODE_OK; + ind <= 2; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + cc2 := cc; + AlertIf(empty_sample_head(2) /= 0, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(2) /= 0, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(2) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 44(I4S12),11(I2S14),22(I2S16)/0,33 + -- PAYLOAD MEMORY: 30(I4S12),10(I2S14),40(I2S16)/0,20 + -- INSTANCE MEMORY: 0(I2),9(I4),18(I3)/- + + Log("W2: RTPS Operation ACK_CACHE_CHANGE SN 12", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := ACK_CACHE_CHANGE; + rtps.cc.seq_nr := gen_sn(12); + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := TRUE; + cc.kind := NOT_ALIVE_UNREGISTERED; + cc.instance := kh2; + cc.payload := gen_payload(kh2,5); + cc.seq_nr := gen_sn(17); + cc.src_timestamp := gen_duration(17,0); + + -- TEST: NORMAL UNREGISTER + -- TEST: ADD SAMPLE ON MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE, WITH ACKed SAMPLES, WITHOUT ACKed INSTANCE SAMPLES] + + Log("W2: DDS Operation UNREGISTER_INSTANCE [TS 17s, Instance 2]", INFO); + Log("W2: ACCEPTED", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := UNREGISTER_INSTANCE; + dds.cc := cc; + dds.ret_code := RETCODE_OK; + ind <= 2; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + cc3 := cc; + AlertIf(empty_sample_head(2) /= 33, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(2) /= 10, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(2) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 44(I4S12),22(I2S16),0(I2S17)/33,11 + -- PAYLOAD MEMORY: 30(I4S12),40(I2S16),0(I2S17)/10,20 + -- INSTANCE MEMORY: 0(I2),9(I4),18(I3)/- + + -- VALIDATE STATE + + Log("W2: RTPS Operation GET_MIN_SN", INFO); + Log("W2: Expected SN 12", DEBUG); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_MIN_SN; + rtps.cc.seq_nr := gen_sn(12); + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W2: RTPS Operation GET_MAX_SN", INFO); + Log("W2: Expected SN 17", DEBUG); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_MAX_SN; + rtps.cc.seq_nr := gen_sn(17); + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W2: RTPS Operation GET_CACHE_CHANGE SN 12", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_CACHE_CHANGE; + rtps.cc := cc1; + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W2: RTPS Operation GET_CACHE_CHANGE SN 16", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_CACHE_CHANGE; + rtps.cc := cc2; + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W2: RTPS Operation GET_CACHE_CHANGE SN 17", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_CACHE_CHANGE; + rtps.cc := cc3; + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := TRUE; + cc.kind := NOT_ALIVE_UNREGISTERED; + cc.instance := kh4; + cc.payload := gen_payload(kh4,5); + cc.seq_nr := gen_sn(18); + cc.src_timestamp := gen_duration(18,0); + + Log("W2: DDS Operation UNREGISTER_INSTANCE [TS 18s, Instance 4]", INFO); + Log("W2: ACCEPTED", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := UNREGISTER_INSTANCE; + dds.cc := cc; + dds.ret_code := RETCODE_OK; + ind <= 2; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + cc4 := cc; + AlertIf(empty_sample_head(2) /= 11, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(2) /= 20, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(2) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 44(I4S12),22(I2S16),0(I2S17),33(I4S18)/11 + -- PAYLOAD MEMORY: 30(I4S12),40(I2S16),0(I2S17),10(I4S178)/20 + -- INSTANCE MEMORY: 0(I2),9(I4),18(I3)/- + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := TRUE; + cc.kind := NOT_ALIVE_UNREGISTERED; + cc.instance := kh3; + cc.payload := gen_payload(kh3,5); + cc.seq_nr := gen_sn(19); + cc.src_timestamp := gen_duration(19,0); + + -- TEST: NORMAL NACK_CACHE_CHANGE + + Log("W2: RTPS Operation NACK_CACHE_CHANGE SN 12", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := NACK_CACHE_CHANGE; + rtps.cc.seq_nr := gen_sn(12); + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W2: RTPS Operation ACK_CACHE_CHANGE SN 18", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := ACK_CACHE_CHANGE; + rtps.cc.seq_nr := gen_sn(18); + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + -- TEST: ADD SAMPLE ON MAX_SAMPLES [KNOWN INSTANCE,WITH ACKed SAMPLE] + + Log("W2: DDS Operation UNREGISTER_INSTANCE [TS 19s, Instance 3]", INFO); + Log("W2: ACCEPTED", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := UNREGISTER_INSTANCE; + dds.cc := cc; + dds.ret_code := RETCODE_OK; + ind <= 2; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + cc4 := cc; + AlertIf(empty_sample_head(2) /= 33, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(2) /= 10, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(2) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 44(I4S12),22(I2S16),0(I2S17),11(I3S19)/33 + -- PAYLOAD MEMORY: 30(I4S12),40(I2S16),0(I2S17),20(I3S19)/10 + -- INSTANCE MEMORY: 0(I2),9(I4),18(I3)/- + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh3; + cc.payload := gen_payload(kh3,9); + cc.seq_nr := gen_sn(20); + cc.src_timestamp := gen_duration(20,0); + + -- TEST: ADD SAMPLE ON MAX_SAMPLES [KNOWN INSTANCE,WITHOUT ACKed SAMPLES] + -- TEST: WRITE ON UNREGISTERED INSTANCE + + Log("W2: DDS Operation WRITE [TS 20s, Instance 3, Aligned Payload]", INFO); + Log("W2: ACCEPTED", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := WRITE; + dds.cc := cc; + dds.ret_code := RETCODE_OK; + ind <= 2; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + cc1 := cc; + AlertIf(empty_sample_head(2) /= 44, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(2) /= 30, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(2) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 22(I2S16),0(I2S17),11(I3S19),33(I3S20)/44 + -- PAYLOAD MEMORY: 40(I2S16),0(I2S17),20(I3S19),10(I3S20)/30 + -- INSTANCE MEMORY: 0(I2),9(I4),18(I3)/- + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh3; + cc.payload := gen_payload(kh3,9); + cc.seq_nr := gen_sn(21); + cc.src_timestamp := gen_duration(21,0); + + -- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE,WITHOUT ACKed SAMPLES] + + Log("W2: DDS Operation WRITE [TS 21s, Instance 3, Aligned Payload]", INFO); + Log("W2: ACCEPTED", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := WRITE; + dds.cc := cc; + dds.ret_code := RETCODE_OK; + ind <= 2; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + cc4 := cc; + AlertIf(empty_sample_head(2) /= 11, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(2) /= 20, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(2) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 22(I2S16),0(I2S17),33(I3S20),44(I3S21)/11 + -- PAYLOAD MEMORY: 40(I2S16),0(I2S17),10(I3S20),30(I3S21)/20 + -- INSTANCE MEMORY: 0(I2),9(I4),18(I3)/- + + Log("W2: RTPS Operation ACK_CACHE_CHANGE SN 16", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := ACK_CACHE_CHANGE; + rtps.cc.seq_nr := gen_sn(16); + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh3; + cc.payload := gen_payload(kh3,9); + cc.seq_nr := gen_sn(22); + cc.src_timestamp := gen_duration(22,0); + + -- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE,WITH ACKed SAMPLES, WITHOUT ACKed INSTANCE SAMPLES] + + Log("W2: DDS Operation WRITE [TS 22s, Instance 3, Aligned Payload]", INFO); + Log("W2: ACCEPTED", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := WRITE; + dds.cc := cc; + dds.ret_code := RETCODE_OK; + ind <= 2; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + cc1 := cc; + AlertIf(empty_sample_head(2) /= 33, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(2) /= 10, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(2) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 22(I2S16),0(I2S17),44(I3S21),11(I3S22)/33 + -- PAYLOAD MEMORY: 40(I2S16),0(I2S17),30(I3S21),20(I3S22)/10 + -- INSTANCE MEMORY: 0(I2),9(I4),18(I3)/- + + Log("W2: RTPS Operation ACK_CACHE_CHANGE SN 22", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := ACK_CACHE_CHANGE; + rtps.cc.seq_nr := gen_sn(22); + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh3; + cc.payload := gen_payload(kh3,9); + cc.seq_nr := gen_sn(23); + cc.src_timestamp := gen_duration(23,0); + + -- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE,WITH ACKed INSTANCE SAMPLES] + + Log("W2: DDS Operation WRITE [TS 23s, Instance 3, Aligned Payload]", INFO); + Log("W2: ACCEPTED", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := WRITE; + dds.cc := cc; + dds.ret_code := RETCODE_OK; + ind <= 2; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + cc1 := cc; + AlertIf(empty_sample_head(2) /= 11, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(2) /= 20, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(2) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 22(I2S16),0(I2S17),44(I3S21),33(I3S23)/11 + -- PAYLOAD MEMORY: 40(I2S16),0(I2S17),30(I3S21),10(I3S23)/20 + -- INSTANCE MEMORY: 0(I2),9(I4),18(I3)/- + + -- VALIDATE STATE + + Log("W2: RTPS Operation GET_MIN_SN", INFO); + Log("W2: Expected SN 16", DEBUG); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_MIN_SN; + rtps.cc.seq_nr := gen_sn(16); + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W2: RTPS Operation GET_MAX_SN", INFO); + Log("W2: Expected SN 23", DEBUG); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_MAX_SN; + rtps.cc.seq_nr := gen_sn(23); + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W2: RTPS Operation GET_CACHE_CHANGE SN 21", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_CACHE_CHANGE; + rtps.cc := cc4; + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W2: RTPS Operation GET_CACHE_CHANGE SN 22", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_CACHE_CHANGE; + rtps.cc.seq_nr := gen_sn(22); + rtps.ret_code := INVALID; + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W2: RTPS Operation GET_CACHE_CHANGE SN 23", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_CACHE_CHANGE; + rtps.cc := cc1; + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := TRUE; + cc.kind := NOT_ALIVE_UNREGISTERED; + cc.instance := kh1; + cc.payload := gen_payload(kh1,5); + cc.seq_nr := gen_sn(24); + cc.src_timestamp := gen_duration(24,0); + + -- TEST: UNREGISTER UNKNOWN INSTANCE + + Log("W2: DDS Operation UNREGISTER_INSTANCE [TS 24s, HANDLE_NIL, Instance 1]", INFO); + Log("W2: IGNORED [Instance not Registered]", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := UNREGISTER_INSTANCE; + dds.cc := cc; + dds.cc.instance:= HANDLE_NIL; + dds.ret_code := RETCODE_OK; + ind <= 2; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh1; + cc.payload := gen_payload(kh1,9); + cc.seq_nr := gen_sn(24); + cc.src_timestamp := gen_duration(24,0); + + -- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE,WITH STALE INSTANCE, WITHOUT ACKed SAMPLE] + -- TEST: REMOVE STALE INSTANCE WITH 0 SAMPLES + + Log("W2: DDS Operation WRITE [TS 24s, Instance 1, HANDLE_NIL, Aligned Payload]", INFO); + Log("W2: ACCEPTED", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := WRITE; + dds.cc := cc; + dds.cc.instance:= HANDLE_NIL; + dds.ret_code := RETCODE_OK; + ind <= 2; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + cc2 := cc; + AlertIf(empty_sample_head(2) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(2) /= 40, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(2) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I2S17),44(I3S21),33(I3S23),11(I1S24)/22 + -- PAYLOAD MEMORY: 0(I2S17),30(I3S21),10(I3S23),20(I1S24)/40 + -- INSTANCE MEMORY: 9(I1),0(I2),18(I3)/- + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh4; + cc.payload := gen_payload(kh4,9); + cc.seq_nr := gen_sn(25); + cc.src_timestamp := gen_duration(25,0); + + -- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE,WITHOUT STALE INSTANCES,WITHOUT ACKed SAMPLES] + + Log("W2: DDS Operation WRITE [TS 25s, Instance 4, HANDLE_NIL Aligned Payload]", INFO); + Log("W2: REJECTED [MAX_INSTANCES exceeded]", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := WRITE; + dds.cc := cc; + dds.cc.instance:= HANDLE_NIL; + dds.ret_code := RETCODE_OUT_OF_RESOURCES; + ind <= 2; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + + Log("W2: RTPS Operation ACK_CACHE_CHANGE SN 21", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := ACK_CACHE_CHANGE; + rtps.cc.seq_nr := gen_sn(21); + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + -- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE,WITHOUT STALE INSTANCE, WITH ACKed SAMPLE] + + Log("W2: DDS Operation WRITE [TS 25s, Instance 4, HANDLE_NIL, Aligned Payload]", INFO); + Log("W2: REJECTED [MAX_INSTANCES exceeded]", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := WRITE; + dds.cc := cc; + dds.cc.instance:= HANDLE_NIL; + dds.ret_code := RETCODE_OUT_OF_RESOURCES; + ind <= 2; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + + Log("W2: RTPS Operation ACK_CACHE_CHANGE SN 17", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := ACK_CACHE_CHANGE; + rtps.cc.seq_nr := gen_sn(17); + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + -- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE,WITH STALE INSTANCE (>0 SAMPLES)] + -- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE,WITH STALE INSTANCE, WITH ACKed SAMPLE] + + Log("W2: DDS Operation WRITE [TS 25s, Instance 4, HANDLE_NIL, Aligned Payload]", INFO); + Log("W2: ACCEPTED", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := WRITE; + dds.cc := cc; + dds.cc.instance:= HANDLE_NIL; + dds.ret_code := RETCODE_OK; + ind <= 2; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + cc3 := cc; + AlertIf(empty_sample_head(2) /= 0, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(2) /= 0, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(2) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 44(I3S21),33(I3S23),11(I1S24),22(I4S25)/0 + -- PAYLOAD MEMORY: 30(I3S21),10(I3S23),20(I1S24),40(I4S25)/0 + -- INSTANCE MEMORY: 0(I4),9(I1),18(I3)/- + + -- TEST: ACK_CACHE_CHANGE [ALREADY ACKed SN] + + Log("W2: RTPS Operation ACK_CACHE_CHANGE SN 21", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := ACK_CACHE_CHANGE; + rtps.cc.seq_nr := gen_sn(21); + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh2; + cc.payload := gen_payload(kh2,9); + cc.seq_nr := gen_sn(26); + cc.src_timestamp := gen_duration(26,0); + + -- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKNOWN INSTANCE, WITHOUT STALE INSTANCES] + + Log("W2: DDS Operation WRITE [TS 26s, Instance 2, HANDLE_NIL, Aligned Payload]", INFO); + Log("W2: REJECTED [MAX_INSTANCES exceeded]", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := WRITE; + dds.cc := cc; + dds.cc.instance:= HANDLE_NIL; + dds.ret_code := RETCODE_OUT_OF_RESOURCES; + ind <= 2; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + + Log("W2: RTPS Operation ACK_CACHE_CHANGE SN 24", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := ACK_CACHE_CHANGE; + rtps.cc.seq_nr := gen_sn(24); + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + -- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKNOWN INSTANCE, WITH FULLY ACKed INSTANCE, WITHOUT STALE INSTANCE] + + Log("W2: DDS Operation WRITE [TS 26s, Instance 2, HANDLE_NIL, Aligned Payload]", INFO); + Log("W2: REJECTED [MAX_INSTANCES exceeded]", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := WRITE; + dds.cc := cc; + dds.cc.instance:= HANDLE_NIL; + dds.ret_code := RETCODE_OUT_OF_RESOURCES; + ind <= 2; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := TRUE; + cc.kind := NOT_ALIVE_UNREGISTERED; + cc.instance := kh1; + cc.payload := gen_payload(kh1,5); + cc.seq_nr := gen_sn(26); + cc.src_timestamp := gen_duration(26,0); + + Log("W2: DDS Operation UNREGISTER_INSTANCE [TS 26s, Instance 1]", INFO); + Log("W2: ACCEPTED", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := UNREGISTER_INSTANCE; + dds.cc := cc; + dds.ret_code := RETCODE_OK; + ind <= 2; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + cc4 := cc; + AlertIf(empty_sample_head(2) /= 44, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(2) /= 30, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(2) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 33(I3S23),11(I1S24),22(I4S25),0(I1S26)/44 + -- PAYLOAD MEMORY: 10(I3S23),20(I1S24),40(I4S25),0(I1S26)/30 + -- INSTANCE MEMORY: 0(I4),9(I1),18(I3)/- + + Log("W2: RTPS Operation ACK_CACHE_CHANGE SN 24", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := ACK_CACHE_CHANGE; + rtps.cc.seq_nr := gen_sn(24); + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + -- TEST: REGISTER ON UNREGISTERED INSTANCE + + Log("W2: DDS Operation REGISTER_INSTANCE 1", INFO); + Log("W2: ACCEPTED", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := REGISTER_INSTANCE; + dds.cc := cc; + dds.ret_code := RETCODE_OK; + ind <= 2; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh2; + cc.payload := gen_payload(kh2,9); + cc.seq_nr := gen_sn(27); + cc.src_timestamp := gen_duration(27,0); + + Log("W2: DDS Operation WRITE [TS 27s, Instance 2, HANDLE_NIL, Aligned Payload]", INFO); + Log("W2: REJECTED [MAX_INSTANCES exceeded]", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := WRITE; + dds.cc := cc; + dds.cc.instance:= HANDLE_NIL; + dds.ret_code := RETCODE_OUT_OF_RESOURCES; + ind <= 2; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := TRUE; + cc.kind := NOT_ALIVE_UNREGISTERED; + cc.instance := kh3; + cc.payload := gen_payload(kh3,5); + cc.seq_nr := gen_sn(27); + cc.src_timestamp := gen_duration(27,0); + + Log("W2: DDS Operation UNREGISTER_INSTANCE [TS 27s, Instance 3]", INFO); + Log("W2: ACCEPTED", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := UNREGISTER_INSTANCE; + dds.cc := cc; + dds.ret_code := RETCODE_OK; + ind <= 2; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + cc2 := cc; + AlertIf(empty_sample_head(2) /= 11, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(2) /= 20, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(2) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 33(I3S23),22(I4S25),0(I1S26),44(I3S27)/11 + -- PAYLOAD MEMORY: 10(I3S23),40(I4S25),0(I1S26),30(I3S27)/20 + -- INSTANCE MEMORY: 0(I4),9(I1),18(I3)/- + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := TRUE; + cc.kind := NOT_ALIVE_DISPOSED; + cc.instance := kh3; + cc.payload := gen_payload(kh3,5); + cc.seq_nr := gen_sn(28); + cc.src_timestamp := gen_duration(28,0); + + -- TEST: DISPOSE ON UNREGISTERED INSTANCE + + Log("W2: DDS Operation DISPOSE [TS 28s, Instance 3]", INFO); + Log("W2: ACCEPTED", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := DISPOSE; + dds.cc := cc; + dds.ret_code := RETCODE_OK; + ind <= 2; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + cc1 := cc; + AlertIf(empty_sample_head(2) /= 33, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(2) /= 10, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(2) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 22(I4S25),0(I1S26),44(I3S27),11(I3S28)/33 + -- PAYLOAD MEMORY: 40(I4S25),0(I1S26),30(I3S27),20(I3S28)/10 + -- INSTANCE MEMORY: 0(I4),9(I1),18(I3)/- + + Log("W2: RTPS Operation ACK_CACHE_CHANGE SN 27", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := ACK_CACHE_CHANGE; + rtps.cc.seq_nr := gen_sn(27); + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W2: RTPS Operation ACK_CACHE_CHANGE SN 28", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := ACK_CACHE_CHANGE; + rtps.cc.seq_nr := gen_sn(28); + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh2; + cc.payload := gen_payload(kh2,9); + cc.seq_nr := gen_sn(29); + cc.src_timestamp := gen_duration(29,0); + + Log("W2: DDS Operation WRITE [TS 29s, Instance 2, HANDLE_NIL, Aligned Payload]", INFO); + Log("W2: ACCEPTED", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := WRITE; + dds.cc := cc; + dds.cc.instance:= HANDLE_NIL; + dds.ret_code := RETCODE_OK; + ind <= 2; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + cc1 := cc; + AlertIf(empty_sample_head(2) /= 44, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(2) /= 20, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(2) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 22(I4S25),0(I1S26),33(I2S29)/44,11 + -- PAYLOAD MEMORY: 40(I4S25),0(I1S26),10(I2S29)/20,30 + -- INSTANCE MEMORY: 18(I2),0(I4),9(I1)/- + + -- VALIDATE STATE + + Log("W2: RTPS Operation GET_MIN_SN", INFO); + Log("W2: Expected SN 25", DEBUG); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_MIN_SN; + rtps.cc.seq_nr := gen_sn(25); + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W2: RTPS Operation GET_MAX_SN", INFO); + Log("W2: Expected SN 28", DEBUG); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_MAX_SN; + rtps.cc.seq_nr := gen_sn(29); + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W2: RTPS Operation GET_CACHE_CHANGE SN 25", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_CACHE_CHANGE; + rtps.cc := cc3; + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W2: RTPS Operation GET_CACHE_CHANGE SN 26", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_CACHE_CHANGE; + rtps.cc := cc4; + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W2: RTPS Operation GET_CACHE_CHANGE SN 29", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_CACHE_CHANGE; + rtps.cc := cc1; + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh2; + cc.payload := gen_payload(kh2,9); + cc.seq_nr := gen_sn(30); + cc.src_timestamp := gen_duration(30,0); + + Log("W2: DDS Operation WRITE [TS 30s, Instance 2, Aligned Payload]", INFO); + Log("W2: ACCEPTED", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := WRITE; + dds.cc := cc; + dds.ret_code := RETCODE_OK; + ind <= 2; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + cc2 := cc; + AlertIf(empty_sample_head(2) /= 11, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(2) /= 30, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(2) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 22(I4S25),0(I1S26),33(I2S29),44(I2S30)/11 + -- PAYLOAD MEMORY: 40(I4S25),0(I1S26),10(I2S29),20(I2S30)/30 + -- INSTANCE MEMORY: 18(I2),0(I4),9(I1)/- + + Log("W2: RTPS Operation ACK_CACHE_CHANGE SN 25", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := ACK_CACHE_CHANGE; + rtps.cc.seq_nr := gen_sn(25); + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W2: RTPS Operation ACK_CACHE_CHANGE SN 26", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := ACK_CACHE_CHANGE; + rtps.cc.seq_nr := gen_sn(26); + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh4; + cc.payload := gen_payload(kh4,9); + cc.seq_nr := gen_sn(31); + cc.src_timestamp := gen_duration(31,0); + + -- TEST: ADD SAMPLE ON MAX_SAMPLES [KNOWN INSTANCE,WITH ACKed SAMPLES (>1)] + + Log("W2: DDS Operation WRITE [TS 31s, Instance 4, Aligned Payload]", INFO); + Log("W2: ACCEPTED", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := WRITE; + dds.cc := cc; + dds.ret_code := RETCODE_OK; + ind <= 2; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + cc3 := cc; + AlertIf(empty_sample_head(2) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(2) /= 40, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(2) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I1S26),33(I2S29),44(I2S30),11(I4S31)/22 + -- PAYLOAD MEMORY: 0(I1S26),10(I2S29),20(I2S30),30(I4S31)/40 + -- INSTANCE MEMORY: 18(I2),0(I4),9(I1)/- + + Log("W2: RTPS Operation REMOVE_CACHE_CHANGE SN 31", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := REMOVE_CACHE_CHANGE; + rtps.cc.seq_nr := gen_sn(31); + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + AlertIf(empty_sample_head(2) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(2) /= 30, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(2) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I1S26),33(I2S29),44(I2S30)/22,11 + -- PAYLOAD MEMORY: 0(I1S26),10(I2S29),20(I2S30)/30,40 + -- INSTANCE MEMORY: 18(I2),0(I4),9(I1)/- + + Log("W2: RTPS Operation ACK_CACHE_CHANGE SN 29", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := ACK_CACHE_CHANGE; + rtps.cc.seq_nr := gen_sn(29); + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W2: RTPS Operation ACK_CACHE_CHANGE SN 30", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := ACK_CACHE_CHANGE; + rtps.cc.seq_nr := gen_sn(30); + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh2; + cc.payload := gen_payload(kh2,9); + cc.seq_nr := gen_sn(32); + cc.src_timestamp := gen_duration(32,0); + + -- TEST: ADD SAMPLE ON MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE, WITH ACKed INSTANCE SAMPLES(>1)] + + Log("W2: DDS Operation WRITE [TS 32s, Instance 2, Aligned Payload]", INFO); + Log("W2: ACCEPTED", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := WRITE; + dds.cc := cc; + dds.ret_code := RETCODE_OK; + ind <= 2; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + cc1 := cc; + AlertIf(empty_sample_head(2) /= 11, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(2) /= 10, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(2) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I1S26),44(I2S30),22(I2S32)/11,33 + -- PAYLOAD MEMORY: 0(I1S26),20(I2S30),30(I2S32)/10,40 + -- INSTANCE MEMORY: 18(I2),0(I4),9(I1)/- + + -- VALIDATE STATE + + Log("W2: RTPS Operation GET_MIN_SN", INFO); + Log("W2: Expected SN 26", DEBUG); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_MIN_SN; + rtps.cc.seq_nr := gen_sn(26); + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W2: RTPS Operation GET_MAX_SN", INFO); + Log("W2: Expected SN 32", DEBUG); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_MAX_SN; + rtps.cc.seq_nr := gen_sn(32); + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W2: RTPS Operation GET_CACHE_CHANGE SN 26", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_CACHE_CHANGE; + rtps.cc := cc4; + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W2: RTPS Operation GET_CACHE_CHANGE SN 30", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_CACHE_CHANGE; + rtps.cc := cc2; + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("W2: RTPS Operation GET_CACHE_CHANGE SN 32", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := GET_CACHE_CHANGE; + rtps.cc := cc1; + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + -- TEST: INSTANCE LOOKUP [KNOWN INSTANCE] + + Log("W2: DDS Operation LOOKUP_INSTANCE [Instance 2]", INFO); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := LOOKUP_INSTANCE; + dds.cc := cc; + ind <= 2; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh3; + cc.payload := gen_payload(kh3,9); + + -- TEST: INSTANCE LOOKUP [UNKNOWN INSTANCE] + + Log("W2: DDS Operation LOOKUP_INSTANCE [Unknown Instance]", INFO); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := LOOKUP_INSTANCE; + dds.cc := cc; + dds.cc.instance:= HANDLE_NIL; + ind <= 2; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + + wait_on_completion; + TranscriptOpen(RESULTS_FILE, APPEND_MODE); + SetTranscriptMirror; + ReportAlerts; + TranscriptClose; + std.env.stop; + wait; + end process; + + clock_prc : process + begin + clk <= '0'; + wait for 25 ns; + clk <= '1'; + wait for 25 ns; + end process; + + dds_prc : process(all) + begin + if rising_edge(clk) then + dds_done <= '0'; + case (dds_stage) is + when IDLE => + if (dds_start = '1') then + dds_stage <= START; + else + dds_done <= '1'; + end if; + when START => + if (ack_dds(ind) = '1') then + dds_stage <= PUSH; + dds_cnt <= 0; + end if; + when PUSH => + if (ready_in_dds(ind) = '1') then + dds_cnt <= dds_cnt + 1; + if (dds_cnt = dds.cc.payload.length-1) then + -- DEFAULT + dds_stage <= DONE; + end if; + end if; + when DONE => + if (done_dds(ind) = '1') then + if (dds.opcode = REGISTER_INSTANCE or dds.opcode = LOOKUP_INSTANCE) then + AffirmIfEqual(ih_id, to_unsigned(instance_handle_out_dds(ind)), to_unsigned(dds.cc.instance)); + else + AffirmIfEqual(ret_id, return_code_dds(ind), dds.ret_code); + end if; + dds_stage <= IDLE; + end if; + end case; + end if; + + -- DEFAULT + start_dds <= (others => '0'); + opcode_dds <= (others => NOP); + valid_in_dds <= (others => '0'); + last_word_in_dds <= (others => '0'); + data_in_dds <= (others => (others => '0')); + instance_handle_in_dds <= (others => HANDLE_NIL); + source_ts_dds <= (others => TIME_INVALID); + ready_out_dds <= (others => '0'); + + case (dds_stage) is + when START => + start_dds(ind) <= '1'; + opcode_dds(ind) <= dds.opcode; + instance_handle_in_dds(ind) <= dds.cc.instance; + source_ts_dds(ind) <= dds.cc.src_timestamp; + when PUSH => + valid_in_dds(ind) <= '1'; + data_in_dds(ind) <= dds.cc.payload.data(dds_cnt); + last_word_in_dds(ind) <= dds.cc.payload.last(dds_cnt); + when others => + null; + end case; + end process; + + rtps_prc : process(all) + begin + if rising_edge(clk) then + rtps_done <= '0'; + case (rtps_stage) is + when IDLE => + if (rtps_start = '1') then + rtps_stage <= START; + else + rtps_done <= '1'; + end if; + when START => + if (ack_rtps(ind) = '1') then + rtps_stage <= DONE; + end if; + when DONE => + if (done_rtps(ind) = '1') then + -- DEFAULT + rtps_stage <= IDLE; + + AffirmIfEqual(ret_id, HISTORY_CACHE_RESPONSE_TYPE'pos(ret_rtps(ind)), HISTORY_CACHE_RESPONSE_TYPE'pos(rtps.ret_code)); + case (rtps.opcode) is + when GET_CACHE_CHANGE => + if (rtps.ret_code = OK) then + AffirmIfEqual(inst_id, to_unsigned(cc_instance_handle(ind)), to_unsigned(rtps.cc.instance)); + AffirmIfEqual(kind_id, CACHE_CHANGE_KIND_TYPE'pos(cc_kind(ind)), CACHE_CHANGE_KIND_TYPE'pos(rtps.cc.kind)); + AffirmIfEqual(sn_id, to_unsigned(cc_seq_nr(ind)), to_unsigned(rtps.cc.seq_nr)); + AffirmIfEqual(ts_id, to_unsigned(cc_source_timestamp(ind)), to_unsigned(rtps.cc.src_timestamp)); + rtps_stage <= CHECK; + rtps_cnt <= 0; + end if; + when GET_MIN_SN => + AffirmIfEqual(sn_id, to_unsigned(cc_seq_nr(ind)), to_unsigned(rtps.cc.seq_nr)); + when GET_MAX_SN => + AffirmIfEqual(sn_id, to_unsigned(cc_seq_nr(ind)), to_unsigned(rtps.cc.seq_nr)); + when others => + null; + end case; + end if; + when CHECK => + if (valid_out_rtps(ind) = '1') then + AffirmIfEqual(data_id, last_word_out_rtps(ind) & data_out_rtps(ind), rtps.cc.payload.last(rtps_cnt) & rtps.cc.payload.data(rtps_cnt)); + rtps_cnt <= rtps_cnt + 1; + if (rtps_cnt = rtps.cc.payload.length-1) then + rtps_stage <= IDLE; + end if; + end if; + end case; + end if; + + -- DEFAULT + start_rtps <= (others => '0'); + opcode_rtps <= (others => NOP); + seq_nr_rtps <= (others => SEQUENCENUMBER_UNKNOWN); + get_data_rtps <= (others => '0'); + ready_out_rtps <= (others => '0'); + + case (rtps_stage) is + when START => + start_rtps(ind) <= '1'; + opcode_rtps(ind) <= rtps.opcode; + seq_nr_rtps(ind) <= rtps.cc.seq_nr; + when DONE => + if (done_rtps(ind) = '1') then + case (rtps.opcode) is + when GET_CACHE_CHANGE => + get_data_rtps(ind) <= '1'; + when others => + null; + end case; + end if; + when CHECK => + ready_out_rtps(ind) <= '1'; + when others => + null; + end case; + end process; + + watchdog : process + begin + wait for 2 ms; + Alert("Test timeout", FAILURE); + std.env.stop; + end process; + +end architecture; \ No newline at end of file diff --git a/src/Tests/Level_0/L0_dds_writer_test1_afk.vhd b/src/Tests/Level_0/L0_dds_writer_test1_afk.vhd deleted file mode 100644 index 2cff3c1..0000000 --- a/src/Tests/Level_0/L0_dds_writer_test1_afk.vhd +++ /dev/null @@ -1,2116 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library osvvm; -- Utility Library -context osvvm.OsvvmContext; - -use work.rtps_package.all; -use work.user_config.all; -use work.rtps_config_package.all; -use work.rtps_test_package.all; - -entity L0_dds_writer_test1_afk is -end entity; - --- This testbench tests the General Operation of the DDS Writer. It tests the correctness of the RTPS --- GET_MIN_SN, GET_MAX_SN, GET_CACHE_CHANGE, REMOVE_CACHE_CHANGE, ACK_CACHE_CHANGE, and NACK_CACHE_CHANGE Operations and the --- DDS REGISTER_INSTANCE, UNREGISTER_INSTANCE, WRITE, DISPOSE, and LOOKUP_INSTANCE Operations. --- More specifically the testbench covers following tests: --- TEST: GET_MIN_SN/GET_MAX_SN ON EMPTY --- TEST: GET_MIN_SN/GET_MAX_SN ON 1 SAMPLE --- TEST: GET_MIN_SN/GET_MAX_SN ON >1 SAMPLE --- TEST: ADD SAMPLE WITH KEY_HASH [UNKNOWN INSTANCE] --- TEST: ADD SAMPLE WITH KEY_HASH [KNOWN INSTANCE] --- TEST: ADD SAMPLE WITH HANDLE_NIL [UNKNOWN INSTANCE] --- TEST: ADD SAMPLE WITH HANDLE_NIL [KNOWN INSTANCE] --- TEST: NORMAL WRITE --- TEST: WRITE ON PAYLOAD MEMORY FULL [WITHOUT ACKed SAMPLES] --- TEST: WRITE ON PAYLOAD MEMORY FULL [WITH ACKed SAMPLES] --- TEST: WRITE ON DISPOSED INSTANCE --- TEST: WRITE ON UNREGISTERED INSTANCE --- TEST: WRITE ALIGNED PAYLOAD --- TEST: WRITE UNALIGNED PAYLOAD [>1 SLOT] --- TEST: WRITE UNALIGNED PAYLOAD [<1 SLOT] --- TEST: NORMAL REGISTER --- TEST: REGISTER INSTANCE [KNOWN INSTANCE] --- TEST: REGISTER INSTANCE ON MAX_INSTANCES [UNKNOWN INSTANCE, WITHOUT STALE INSTANCE] --- TEST: REGISTER INSTANCE ON MAX_INSTANCES [UNKNOWN INSTANCE, WITH STALE INSTANCE] --- TEST: REGISTER ON UNREGISTERED INSTANCE --- TEST: NORMAL DISPOSE --- TEST: DISPOSE ON PAYLOAD MEMORY FULL [WITHOUT ACKed SAMPLES] --- TEST: DISPOSE ON PAYLOAD MEMORY FULL [WITH ACKed SAMPLES] --- TEST: DISPOSE ON UNREGISTERED INSTANCE --- TEST: GET_CACHE_CHANGE [UNKNOWN SN] --- TEST: GET_CACHE_CHANGE [KNOWN SN, ALIGNED PAYLOAD] --- TEST: GET_CACHE_CHANGE [KNOWN SN, UNALIGNED PAYLOAD, >1 SLOT] --- TEST: GET_CACHE_CHANGE [KNOWN SN, UNALIGNED PAYLOAD, <1 SLOT] --- TEST: NORMAL ACK_CACHE_CHANGE --- TEST: ACK_CACHE_CHANGE [ALREADY ACKed SN] --- TEST: NORMAL NACK_CACHE_CHANGE --- TEST: REMOVE_CACHE_CHANGE [UNKNOWN SN] --- TEST: REMOVE_CACHE_CHANGE [KNOWN SN] --- TEST: NORMAL UNREGISTER --- TEST: UNREGISTER INSTANCE ON PAYLOAD MEMORY FULL [WITHOUT ACKed SAMPLES] --- TEST: UNREGISTER INSTANCE ON PAYLOAD MEMORY FULL [WITH ACKed SAMPLES] --- TEST: UNREGISTER ON DISPOSED INSTANCE --- TEST: UNREGISTER UNKNOWN INSTANCE --- TEST: REMOVE STALE INSTANCE WITH 0 SAMPLES --- TEST: REMOVE STALE INSTANCE WITH 1 SAMPLES --- TEST: REMOVE STALE INSTANCE WITH >1 SAMPLES --- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKNOWN INSTANCE, WITH STALE INSTANCE] --- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKNOWN INSTANCE, WITHOUT STALE INSTANCES] --- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKNOWN INSTANCE, WITH FULLY ACKed INSTANCE, WITHOUT STALE INSTANCE] --- TEST: ADD SAMPLE ON MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE, WITHOUT ACKed SAMPLES] --- TEST: ADD SAMPLE ON MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE, WITH ACKed SAMPLES, WITHOUT ACKed INSTANCE SAMPLES] --- TEST: ADD SAMPLE ON MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE, WITH ACKed INSTANCE SAMPLE] --- TEST: ADD SAMPLE ON MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE, WITH ACKed INSTANCE SAMPLES(>1)] --- TEST: ADD SAMPLE ON MAX_SAMPLES [KNOWN INSTANCE,WITHOUT ACKed SAMPLES] --- TEST: ADD SAMPLE ON MAX_SAMPLES [KNOWN INSTANCE,WITH ACKed SAMPLE] --- TEST: ADD SAMPLE ON MAX_SAMPLES [KNOWN INSTANCE,WITH ACKed SAMPLES (>1)] --- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE,WITHOUT ACKed SAMPLES] --- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE,WITH ACKed SAMPLES, WITHOUT ACKed INSTANCE SAMPLES] --- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE,WITH ACKed INSTANCE SAMPLES] --- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE,WITH STALE INSTANCE, WITHOUT ACKed SAMPLE] --- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE,WITHOUT STALE INSTANCES,WITHOUT ACKed SAMPLES] --- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE,WITHOUT STALE INSTANCE, WITH ACKed SAMPLE] --- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE,WITH STALE INSTANCE (>0 SAMPLES)] --- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE,WITH STALE INSTANCE, WITH ACKed SAMPLE] --- TEST: ADD SAMPLE ON PAYLOAD FULL & MAX_INSTANCES [UNKNOWN INSTANCE,WITH ACKed SAMPLES,WITH STALE INSTANCE (>= 1 SAMPLE)] (Induce Double Remove) --- TEST: ADD SAMPLE BIGGER THAN AVAILABLE MEMORY SPACE [WITH ACKed SAMPLES] --- TEST: INSTANCE LOOKUP [KNOWN INSTANCE] --- TEST: INSTANCE LOOKUP [UNKNOWN INSTANCE] - -architecture testbench of L0_dds_writer_test1_afk is - - -- *CONSTANT DECLARATION* - constant MAX_REMOTE_ENDPOINTS : natural := 3; - - -- *TYPE DECLARATION* - type DDS_STAGE_TYPE is (IDLE, START, PUSH, DONE); - type RTPS_STAGE_TYPE is (IDLE, START, DONE, CHECK); - type RTPS_WRITER_TEST_TYPE is record - opcode : HISTORY_CACHE_OPCODE_TYPE; - cc : CACHE_CHANGE_TYPE; - ret_code : HISTORY_CACHE_RESPONSE_TYPE; - end record; - constant DEFAULT_RTPS_WRITER_TEST : RTPS_WRITER_TEST_TYPE := ( - opcode => NOP, - cc => DEFAULT_CACHE_CHANGE, - ret_code => OK - ); - type DDS_TEST_TYPE is record - opcode : DDS_WRITER_OPCODE_TYPE; - cc : CACHE_CHANGE_TYPE; - ret_code : std_logic_vector(RETURN_CODE_WIDTH-1 downto 0); - end record; - constant DEFAULT_DDS_TEST : DDS_TEST_TYPE := ( - opcode => NOP, - cc => DEFAULT_CACHE_CHANGE, - ret_code => RETCODE_OK - ); - - -- *SIGNAL DECLARATION* - signal clk : std_logic := '0'; - signal reset : std_logic := '1'; - signal check_time : TIME_TYPE := TIME_ZERO; - signal start_rtps, start_dds, ack_rtps, ack_dds, done_rtps, done_dds : std_logic := '0'; - signal opcode_rtps : HISTORY_CACHE_OPCODE_TYPE := NOP; - signal opcode_dds : DDS_WRITER_OPCODE_TYPE := NOP; - signal ret_rtps : HISTORY_CACHE_RESPONSE_TYPE := ERROR; - signal seq_nr_rtps, cc_seq_nr : SEQUENCENUMBER_TYPE := SEQUENCENUMBER_UNKNOWN; - signal ready_out_rtps, valid_out_rtps, last_word_out_rtps : std_logic := '0'; - signal ready_in_dds, ready_out_dds, valid_in_dds, valid_out_dds, last_word_in_dds, last_word_out_dds : std_logic := '0'; - signal data_out_rtps, data_in_dds, data_out_dds : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); - signal get_data_rtps, liveliness_assertion, data_available : std_logic := '0'; - signal cc_source_timestamp, source_ts_dds : TIME_TYPE := TIME_INVALID; - signal cc_kind : CACHE_CHANGE_KIND_TYPE := ALIVE; - signal cc_instance_handle, instance_handle_in_dds, instance_handle_out_dds : INSTANCE_HANDLE_TYPE := HANDLE_NIL; - signal max_wait_dds : DURATION_TYPE := DURATION_INFINITE; - signal return_code_dds : std_logic_vector(RETURN_CODE_WIDTH-1 downto 0) := (others => '0'); - signal status : std_logic_vector(STATUS_KIND_WIDTH-1 downto 0) := (others => '0'); - - signal dds_start, dds_done, rtps_start, rtps_done : std_logic := '0'; - signal dds_cnt, rtps_cnt : natural := 0; - signal dds_stage : DDS_STAGE_TYPE := IDLE; - signal rtps_stage : RTPS_STAGE_TYPE := IDLE; - shared variable dds : DDS_TEST_TYPE := DEFAULT_DDS_TEST; - shared variable rtps : RTPS_WRITER_TEST_TYPE := DEFAULT_RTPS_WRITER_TEST; - signal inst_id, kind_id, sn_id, ts_id, ih_id, ret_id, data_id : AlertLogIDType; - - -- *FUNCTION DECLARATION* - function extract_key_hash (payload : TEST_PACKET_TYPE) return INSTANCE_HANDLE_TYPE is - variable ret : INSTANCE_HANDLE_TYPE := HANDLE_NIL; - begin - for i in 0 to 3 loop - ret(i) := not payload.data(i); - end loop; - - return ret; - end function; - - function gen_sn(input : natural) return SEQUENCENUMBER_TYPE is - variable ret : SEQUENCENUMBER_TYPE; - begin - ret(0) := (others => '0'); - ret(1) := unsigned(int(input, WORD_WIDTH)); - return ret; - end function; - -begin - - -- Unit Under Test - uut : entity work.dds_writer(arch) - generic map( - HISTORY_QOS => KEEP_ALL_HISTORY_QOS, - DEADLINE_QOS => DURATION_INFINITE, - LIFESPAN_QOS => gen_duration(1,0), - LEASE_DURATION => DURATION_INFINITE, - WITH_KEY => TRUE, - MAX_SAMPLES => std_logic_vector(to_unsigned(4,CDR_LONG_WIDTH)), - MAX_INSTANCES => std_logic_vector(to_unsigned(3,CDR_LONG_WIDTH)), - MAX_SAMPLES_PER_INSTANCE => std_logic_vector(to_unsigned(2,CDR_LONG_WIDTH)), - PAYLOAD_FRAME_SIZE => 11 - ) - port map ( - clk => clk, - reset => reset, - time => check_time, - start_rtps => start_rtps, - opcode_rtps => opcode_rtps, - ack_rtps => ack_rtps, - done_rtps => done_rtps, - ret_rtps => ret_rtps, - seq_nr_rtps => seq_nr_rtps, - get_data_rtps => get_data_rtps, - data_out_rtps => data_out_rtps, - valid_out_rtps => valid_out_rtps, - ready_out_rtps => ready_out_rtps, - last_word_out_rtps => last_word_out_rtps, - liveliness_assertion => liveliness_assertion, - data_available => data_available, - cc_instance_handle => cc_instance_handle, - cc_kind => cc_kind, - cc_source_timestamp => cc_source_timestamp, - cc_seq_nr => cc_seq_nr, - start_dds => start_dds, - ack_dds => ack_dds, - opcode_dds => opcode_dds, - instance_handle_in_dds => instance_handle_in_dds, - source_ts_dds => source_ts_dds, - max_wait_dds => max_wait_dds, - done_dds => done_dds, - return_code_dds => return_code_dds, - instance_handle_out_dds => instance_handle_out_dds, - ready_in_dds => ready_in_dds, - valid_in_dds => valid_in_dds, - data_in_dds => data_in_dds, - last_word_in_dds => last_word_in_dds, - ready_out_dds => ready_out_dds, - valid_out_dds => valid_out_dds, - data_out_dds => data_out_dds, - last_word_out_dds => last_word_out_dds, - status => status - ); - - stimulus_prc : process - variable RV : RandomPType; - variable kh1, kh2, kh3, kh4 : INSTANCE_HANDLE_TYPE := HANDLE_NIL; - variable cc1, cc2, cc3, cc4, cc : CACHE_CHANGE_TYPE := DEFAULT_CACHE_CHANGE; - - impure function gen_payload(key_hash : INSTANCE_HANDLE_TYPE; len : natural) return TEST_PACKET_TYPE is - variable ret : TEST_PACKET_TYPE := EMPTY_TEST_PACKET; - begin - assert (len >= 4) report "Payload length has to be at least 16 Bytes long" severity FAILURE; - - for i in 0 to len-1 loop - if (i < 4) then - -- NOTE: Beginning of payload is negated key to allow deterministic Key Hash generation from the kh_prc - ret.data(ret.length) := not key_hash(i); - else - ret.data(ret.length) := RV.RandSlv(WORD_WIDTH); - end if; - ret.length := ret.length + 1; - end loop; - ret.last(ret.length-1) := '1'; - - return ret; - end function; - - impure function gen_key_hash return KEY_HASH_TYPE is - variable ret : KEY_HASH_TYPE := KEY_HASH_NIL; - begin - for i in 0 to KEY_HASH_TYPE'length-1 loop - ret(i) := RV.RandSlv(WORD_WIDTH); - end loop; - return ret; - end function; - - procedure start_dds is - begin - dds_start <= '1'; - wait until rising_edge(clk); - dds_start <= '0'; - wait until rising_edge(clk); - end procedure; - - procedure start_rtps is - begin - rtps_start <= '1'; - wait until rising_edge(clk); - rtps_start <= '0'; - wait until rising_edge(clk); - end procedure; - - procedure wait_on_dds is - begin - if (dds_done /= '1') then - wait until dds_done = '1'; - end if; - end procedure; - - procedure wait_on_rtps is - begin - if (rtps_done /= '1') then - wait until rtps_done = '1'; - end if; - end procedure; - - procedure wait_on_completion is - begin - if (rtps_done /= '1' or dds_done /= '1') then - wait until rtps_done = '1' and dds_done = '1'; - end if; - end procedure; - - begin - - SetAlertLogName("L0_dds_writer_test1_afk - (KEEP ALL, Finite Lifespan, Keyed) - General"); - SetAlertEnable(FAILURE, TRUE); - SetAlertEnable(ERROR, TRUE); - SetAlertEnable(WARNING, TRUE); - SetLogEnable(DEBUG, FALSE); - SetLogEnable(PASSED, FALSE); - SetLogEnable(INFO, TRUE); - RV.InitSeed(RV'instance_name); - inst_id <= GetAlertLogID("Instance", ALERTLOG_BASE_ID); - kind_id <= GetAlertLogID("Cache Change Kind", ALERTLOG_BASE_ID); - sn_id <= GetAlertLogID("SequenceNumber", ALERTLOG_BASE_ID); - ts_id <= GetAlertLogID("TimeStamp", ALERTLOG_BASE_ID); - ih_id <= GetAlertLogID("Instance Handle", ALERTLOG_BASE_ID); - data_id <= GetAlertLogID("Data Out", ALERTLOG_BASE_ID); - ret_id <= GetAlertLogID("Return Code", ALERTLOG_BASE_ID); - - -- Key Hashes - kh1 := gen_key_hash; - kh2 := gen_key_hash; - kh3 := gen_key_hash; - kh4 := gen_key_hash; - - - - Log("Initiating Test", INFO); - reset <= '1'; - wait until rising_edge(clk); - wait until rising_edge(clk); - reset <= '0'; - -- Stored CC: 0, 0, 0, 0 - - -- TEST: GET_MIN_SN/GET_MAX_SN ON EMPTY - - Log("RTPS Operation GET_MIN_SN (Expected SEQUENCENUMBER_UNKNOWN)", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_MIN_SN; - rtps.cc.seq_nr := SEQUENCENUMBER_UNKNOWN; - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_MAX_SN (Expected SEQUENCENUMBER_UNKNOWN)", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_MAX_SN; - rtps.cc.seq_nr := SEQUENCENUMBER_UNKNOWN; - start_rtps; - wait_on_rtps; - - -- TEST: WRITE ALIGNED PAYLOAD - -- TEST: NORMAL WRITE - -- TEST: ADD SAMPLE WITH KEY_HASH [UNKNOWN INSTANCE] - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh1; - cc.payload := gen_payload(kh1,10); - cc.seq_nr := gen_sn(1); - cc.src_timestamp := gen_duration(1,0); - - Log("DDS Operation WRITE [TS 1s, Instance 1] (REJECTED: Instance not Registered)", INFO); - dds := DEFAULT_DDS_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.ret_code := RETCODE_BAD_PARAMETER; - start_dds; - wait_on_dds; - - -- TEST: ADD SAMPLE WITH HANDLE_NIL [UNKNOWN INSTANCE] - - Log("DDS Operation WRITE [TS 1s, Instance 1, HANDLE_NIL] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.cc.instance:= HANDLE_NIL; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc1 := cc; - -- Stored CC: I1S1, 0, 0, 0 - - -- TEST: GET_MIN_SN/GET_MAX_SN ON 1 SAMPLE - - Log("RTPS Operation GET_MIN_SN (Expected SN 1)", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_MIN_SN; - rtps.cc.seq_nr := gen_sn(1); - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_MAX_SN (Expected SN 1)", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_MAX_SN; - rtps.cc.seq_nr := gen_sn(1); - start_rtps; - wait_on_rtps; - - -- TEST: WRITE UNALIGNED PAYLOAD [>1 SLOT] - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh2; - cc.payload := gen_payload(kh2,12); - cc.seq_nr := gen_sn(2); - cc.src_timestamp := gen_duration(2,0); - - Log("DDS Operation WRITE [TS 2s, Instance 2, Unaligned Payload (2 Slots)] (REJECTED: Instance not Registered)", INFO); - dds := DEFAULT_DDS_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.ret_code := RETCODE_BAD_PARAMETER; - start_dds; - wait_on_dds; - - -- TEST: NORMAL REGISTER - - Log("DDS Operation REGISTER_INSTANCE 2 (ACCEPTED)", INFO); - dds := DEFAULT_DDS_TEST; - dds.opcode := REGISTER_INSTANCE; - dds.cc := cc; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - - -- TEST: ADD SAMPLE WITH KEY_HASH [KNOWN INSTANCE] - - Log("DDS Operation WRITE [TS 2s, Instance 2, Unaligned Payload (2 Slots)] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc2 := cc; - -- Stored CC: I1S1, I2S2, 0, 0 - - -- TEST: ADD SAMPLE WITH HANDLE_NIL [KNOWN INSTANCE] - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh1; - cc.payload := gen_payload(kh1,15); - cc.seq_nr := gen_sn(3); - cc.src_timestamp := gen_duration(3,0); - - Log("DDS Operation WRITE [TS 3s, Instance 1, Unaligned Payload (2 Slots)] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.cc.instance:= HANDLE_NIL; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc3 := cc; - -- Stored CC: I1S1, I2S2, I1S3, 0 - - -- TEST: GET_CACHE_CHANGE [UNKNOWN SN] - - Log("RTPS Operation GET_CACHE_CHANGE SN 4 (Invalid)", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_CACHE_CHANGE; - rtps.cc.seq_nr := gen_sn(4); - rtps.ret_code := INVALID; - start_rtps; - wait_on_rtps; - - -- TEST: GET_CACHE_CHANGE [KNOWN SN, ALIGNED PAYLOAD] - - Log("RTPS Operation GET_CACHE_CHANGE SN 1", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_CACHE_CHANGE; - rtps.cc := cc1; - start_rtps; - wait_on_rtps; - - -- TEST: GET_CACHE_CHANGE [KNOWN SN, UNALIGNED PAYLOAD, >1 SLOT] - - Log("RTPS Operation GET_CACHE_CHANGE SN 2", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_CACHE_CHANGE; - rtps.cc := cc2; - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_CACHE_CHANGE SN 3", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_CACHE_CHANGE; - rtps.cc := cc3; - start_rtps; - wait_on_rtps; - - -- TEST: WRITE UNALIGNED PAYLOAD [<1 SLOT] - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh3; - cc.payload := gen_payload(kh3,8); - cc.seq_nr := gen_sn(4); - cc.src_timestamp := gen_duration(4,0); - - -- TEST: WRITE ON PAYLOAD MEMORY FULL [WITHOUT ACKed SAMPLES] - - Log("DDS Operation WRITE [TS 4s, Instance 3, HANDLE_NIL, Unaligned Payload (1 Slot)] (REJECTED: Payload Memory Full)", INFO); - dds := DEFAULT_DDS_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.cc.instance:= HANDLE_NIL; - dds.ret_code := RETCODE_OUT_OF_RESOURCES; - start_dds; - wait_on_dds; - -- Stored CC: I1S1, I2S2, I1S3, 0 - - -- TEST: REMOVE_CACHE_CHANGE [UNKNOWN SN] - - Log("RTPS Operation REMOVE_CACHE_CHANGE SN 5 (Invalid)", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := REMOVE_CACHE_CHANGE; - rtps.cc.seq_nr := gen_sn(5); - rtps.ret_code := INVALID; - start_rtps; - wait_on_rtps; - - -- TEST: REMOVE_CACHE_CHANGE [KNOWN SN] - - Log("RTPS Operation REMOVE_CACHE_CHANGE SN 2", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := REMOVE_CACHE_CHANGE; - rtps.cc := cc2; - start_rtps; - wait_on_rtps; - -- Stored CC: I1S1, 0, I1S3, 0 - - Log("DDS Operation WRITE [TS 4s, Instance 3, HANDLE_NIL, Unaligned Payload (1 Slot)] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.cc.instance:= HANDLE_NIL; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc2 := cc; - -- Stored CC: I1S1, I3S4, I1S3, 0 - - -- TEST: GET_CACHE_CHANGE [KNOWN SN, UNALIGNED PAYLOAD, <1 SLOT] - - Log("RTPS Operation GET_CACHE_CHANGE SN 4", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_CACHE_CHANGE; - rtps.cc := cc2; - start_rtps; - wait_on_rtps; - - -- TEST: REGISTER INSTANCE [KNOWN INSTANCE] - - Log("DDS Operation REGISTER_INSTANCE 3 (No Change)", INFO); - dds := DEFAULT_DDS_TEST; - dds.opcode := REGISTER_INSTANCE; - dds.cc := cc2; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - - -- TEST: NORMAL DISPOSE - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_DISPOSED; - cc.instance := kh1; - cc.payload := gen_payload(kh1,5); - cc.seq_nr := gen_sn(5); - cc.src_timestamp := gen_duration(5,0); - - -- TEST: ADD SAMPLE ON MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE, WITHOUT ACKed SAMPLES] - - Log("DDS Operation DISPOSE [TS 5s, Instance 1] (REJECTED: MAX_SAMPLES_PER_INSTANCE Exceeded)", INFO); - dds := DEFAULT_DDS_TEST; - dds.opcode := DISPOSE; - dds.cc := cc; - dds.ret_code := RETCODE_OUT_OF_RESOURCES; - start_dds; - wait_on_dds; - - -- TEST: NORMAL ACK_CACHE_CHANGE - - Log("RTPS Operation ACK_CACHE_CHANGE SN 4", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := ACK_CACHE_CHANGE; - rtps.cc := cc2; - start_rtps; - wait_on_rtps; - - -- TEST: ADD SAMPLE ON MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE, WITH ACKed SAMPLES, WITHOUT ACKed INSTANCE SAMPLES] - - Log("DDS Operation DISPOSE [TS 5s, Instance 1] (REJECTED: MAX_SAMPLES_PER_INSTANCE Exceeded)", INFO); - dds := DEFAULT_DDS_TEST; - dds.opcode := DISPOSE; - dds.cc := cc; - dds.ret_code := RETCODE_OUT_OF_RESOURCES; - start_dds; - wait_on_dds; - - Log("RTPS Operation ACK_CACHE_CHANGE SN 1", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := ACK_CACHE_CHANGE; - rtps.cc := cc1; - start_rtps; - wait_on_rtps; - - -- TEST: ADD SAMPLE ON MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE, WITH ACKed INSTANCE SAMPLE] - - Log("DDS Operation DISPOSE [TS 5s, Instance 1] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_TEST; - dds.opcode := DISPOSE; - dds.cc := cc; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc1 := cc; - -- Stored CC: I1S5, I3S4, I1S3, 0 - - -- VALIDATE STATE - -- TEST: GET_MIN_SN/GET_MAX_SN ON >1 SAMPLE - - Log("RTPS Operation GET_MIN_SN (Expected SN 3)", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_MIN_SN; - rtps.cc.seq_nr := gen_sn(3); - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_MAX_SN (Expected SN 5)", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_MAX_SN; - rtps.cc.seq_nr := gen_sn(5); - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_CACHE_CHANGE SN 5", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_CACHE_CHANGE; - rtps.cc := cc1; - start_rtps; - wait_on_rtps; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh4; - cc.payload := gen_payload(kh4,10); - cc.seq_nr := gen_sn(6); - cc.src_timestamp := gen_duration(6,0); - - -- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKNOWN INSTANCE, WITHOUT STALE INSTANCES] - - Log("DDS Operation WRITE [TS 6s, Instance 4, HANDLE_NIL, Aligned Payload] (REJECTED: MAX_INSTANCES exceeded)", INFO); - dds := DEFAULT_DDS_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.cc.instance:= HANDLE_NIL; - dds.ret_code := RETCODE_OUT_OF_RESOURCES; - start_dds; - wait_on_dds; - - Log("RTPS Operation ACK_CACHE_CHANGE SN 3", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := ACK_CACHE_CHANGE; - rtps.cc := cc3; - start_rtps; - wait_on_rtps; - - -- TEST: ACK_CACHE_CHANGE [ALREADY ACKed SN] - - Log("RTPS Operation ACK_CACHE_CHANGE SN 4", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := ACK_CACHE_CHANGE; - rtps.cc := cc2; - start_rtps; - wait_on_rtps; - - Log("RTPS Operation ACK_CACHE_CHANGE SN 5", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := ACK_CACHE_CHANGE; - rtps.cc := cc1; - start_rtps; - wait_on_rtps; - - -- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKNOWN INSTANCE, WITH FULLY ACKed INSTANCE, WITHOUT STALE INSTANCE] - - Log("DDS Operation WRITE [TS 6s, Instance 4, HANDLE_NIL, Aligned Payload] (REJECTED: MAX_INSTANCES exceeded)", INFO); - dds := DEFAULT_DDS_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.cc.instance:= HANDLE_NIL; - dds.ret_code := RETCODE_OUT_OF_RESOURCES; - start_dds; - wait_on_dds; - - -- TEST: NORMAL UNREGISTER - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_UNREGISTERED; - cc.instance := kh1; - cc.payload := gen_payload(kh1,5); - cc.seq_nr := gen_sn(6); - cc.src_timestamp := gen_duration(6,0); - - -- TEST: UNREGISTER ON DISPOSED INSTANCE - - Log("DDS Operation UNREGISTER_INSTANCE [TS 6s, Instance 1] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_TEST; - dds.opcode := UNREGISTER_INSTANCE; - dds.cc := cc; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc3 := cc; - -- Stored CC: I1S5, I3S4, I1S6, 0 - - -- VALIDATE STATE - - Log("RTPS Operation GET_MIN_SN (Expected SN 4)", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_MIN_SN; - rtps.cc.seq_nr := gen_sn(4); - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_MAX_SN (Expected SN 6)", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_MAX_SN; - rtps.cc.seq_nr := gen_sn(6); - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_CACHE_CHANGE SN 6", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_CACHE_CHANGE; - rtps.cc := cc3; - start_rtps; - wait_on_rtps; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh4; - cc.payload := gen_payload(kh4,10); - cc.seq_nr := gen_sn(7); - cc.src_timestamp := gen_duration(7,0); - - Log("DDS Operation WRITE [TS 7s, Instance 4, HANDLE_NIL, Aligned Payload] (REJECTED: MAX_INSTANCES exceeded)", INFO); - dds := DEFAULT_DDS_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.cc.instance:= HANDLE_NIL; - dds.ret_code := RETCODE_OUT_OF_RESOURCES; - start_dds; - wait_on_dds; - - Log("RTPS Operation ACK_CACHE_CHANGE SN 6", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := ACK_CACHE_CHANGE; - rtps.cc := cc3; - start_rtps; - wait_on_rtps; - - -- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKNOWN INSTANCE, WITH STALE INSTANCE] - -- TEST: REMOVE STALE INSTANCE WITH >1 SAMPLES - - Log("DDS Operation WRITE [TS 7s, Instance 4, HANDLE_NIL, Aligned Payload] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.cc.instance:= HANDLE_NIL; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc1 := cc; - -- Stored CC: I4S7, I3S4, 0, 0 - - Log("RTPS Operation GET_CACHE_CHANGE SN 5 (Invalid)", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_CACHE_CHANGE; - rtps.cc.seq_nr := gen_sn(5); - rtps.ret_code := INVALID; - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_CACHE_CHANGE SN 6 (Invalid)", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_CACHE_CHANGE; - rtps.cc.seq_nr := gen_sn(6); - rtps.ret_code := INVALID; - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_CACHE_CHANGE SN 7", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_CACHE_CHANGE; - rtps.cc := cc1; - start_rtps; - wait_on_rtps; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh2; - cc.payload := gen_payload(kh2,15); - cc.seq_nr := gen_sn(8); - cc.src_timestamp := gen_duration(8,0); - - Log("DDS Operation WRITE [TS 8s, Instance 2, Unaligned Payload (2 Slot)] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc3 := cc; - -- Stored CC: I4S7, I3S4, I2S8, 0 - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh1; - cc.payload := gen_payload(kh1,10); - cc.seq_nr := gen_sn(9); - cc.src_timestamp := gen_duration(9,0); - - Log("DDS Operation WRITE [TS 9s, Instance 1, Aligned Payload] (REJECTED: Instance not Registered)", INFO); - dds := DEFAULT_DDS_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.ret_code := RETCODE_BAD_PARAMETER; - start_dds; - wait_on_dds; - - -- TEST: REGISTER INSTANCE ON MAX_INSTANCES [UNKNOWN INSTANCE, WITHOUT STALE INSTANCE] - - Log("DDS Operation REGISTER_INSTANCE 1 (REJECTED: MAX_INSTANCES exceeded)", INFO); - dds := DEFAULT_DDS_TEST; - dds.opcode := REGISTER_INSTANCE; - dds.cc := cc; - dds.cc.instance:= HANDLE_NIL; - start_dds; - wait_on_dds; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := NOT_ALIVE_UNREGISTERED; - cc.instance := kh3; - cc.payload := gen_payload(kh3,5); - cc.seq_nr := gen_sn(9); - cc.src_timestamp := gen_duration(9,0); - - Log("DDS Operation UNREGISTER_INSTANCE [TS 9s, Instance 3] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_TEST; - dds.opcode := UNREGISTER_INSTANCE; - dds.cc := cc; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc4 := cc; - -- Stored CC: I4S7, I3S4, I2S8, I3S9 - - -- VALIDATE STATE - - Log("RTPS Operation GET_MIN_SN (Expected SN 4)", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_MIN_SN; - rtps.cc.seq_nr := gen_sn(4); - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_MAX_SN (Expected SN 9)", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_MAX_SN; - rtps.cc.seq_nr := gen_sn(9); - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_CACHE_CHANGE SN 8", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_CACHE_CHANGE; - rtps.cc := cc3; - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_CACHE_CHANGE SN 9", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_CACHE_CHANGE; - rtps.cc := cc4; - start_rtps; - wait_on_rtps; - - Log("RTPS Operation ACK_CACHE_CHANGE SN 9", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := ACK_CACHE_CHANGE; - rtps.cc := cc4; - start_rtps; - wait_on_rtps; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh1; - cc.payload := gen_payload(kh1,10); - cc.seq_nr := gen_sn(10); - cc.src_timestamp := gen_duration(10,0); - - -- TEST: REGISTER INSTANCE ON MAX_INSTANCES [UNKNOWN INSTANCE, WITH STALE INSTANCE] - - Log("DDS Operation REGISTER_INSTANCE 1 (ACCEPTED)", INFO); - dds := DEFAULT_DDS_TEST; - dds.opcode := REGISTER_INSTANCE; - dds.cc := cc; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - - Log("DDS Operation WRITE [TS 10s, Instance 1, Aligned Payload] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc2 := cc; - -- Stored CC: I4S7, I1S10, I2S8, 0 - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh4; - cc.payload := gen_payload(kh4,10); - cc.seq_nr := gen_sn(11); - cc.src_timestamp := gen_duration(11,0); - - Log("DDS Operation WRITE [TS 11s, Instance 1, Aligned Payload] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc4 := cc; - -- Stored CC: I4S7, I1S10, I2S8, I4S11 - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh2; - cc.payload := gen_payload(kh2,10); - cc.seq_nr := gen_sn(12); - cc.src_timestamp := gen_duration(12,0); - - Log("DDS Operation WRITE [TS 12s, Instance 2, Aligned Payload] (REJECTED: Payload Memory Full)", INFO); - dds := DEFAULT_DDS_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.ret_code := RETCODE_OUT_OF_RESOURCES; - start_dds; - wait_on_dds; - - Log("RTPS Operation ACK_CACHE_CHANGE SN 8", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := ACK_CACHE_CHANGE; - rtps.cc := cc3; - start_rtps; - wait_on_rtps; - - -- TEST: WRITE ON PAYLOAD MEMORY FULL [WITH ACKed SAMPLES] - - Log("DDS Operation WRITE [TS 12s, Instance 2, Aligned Payload] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc3 := cc; - -- Stored CC: I4S7, I1S10, I2S12, I4S11 - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh4; - cc.payload := gen_payload(kh4,10); - cc.seq_nr := gen_sn(13); - cc.src_timestamp := gen_duration(13,0); - - -- TEST: ADD SAMPLE ON MAX_SAMPLES [KNOWN INSTANCE,WITHOUT ACKed SAMPLES] - - Log("DDS Operation WRITE [TS 13s, Instance 4, Aligned Payload] (REJECTED: MAX_SAMPLES exceeded)", INFO); - dds := DEFAULT_DDS_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.ret_code := RETCODE_OUT_OF_RESOURCES; - start_dds; - wait_on_dds; - - Log("RTPS Operation ACK_CACHE_CHANGE SN 7", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := ACK_CACHE_CHANGE; - rtps.cc := cc1; - start_rtps; - wait_on_rtps; - - -- TEST: ADD SAMPLE ON MAX_SAMPLES [KNOWN INSTANCE,WITH ACKed SAMPLES] - - Log("DDS Operation WRITE [TS 13s, Instance 4, Aligned Payload] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc1 := cc; - -- Stored CC: I4S13, I1S10, I2S12, I4S11 - - -- VALIDATE STATE - - Log("RTPS Operation GET_MIN_SN (Expected SN 4)", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_MIN_SN; - rtps.cc.seq_nr := gen_sn(10); - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_MAX_SN (Expected SN 9)", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_MAX_SN; - rtps.cc.seq_nr := gen_sn(13); - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_CACHE_CHANGE SN 10", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_CACHE_CHANGE; - rtps.cc := cc2; - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_CACHE_CHANGE SN 11", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_CACHE_CHANGE; - rtps.cc := cc4; - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_CACHE_CHANGE SN 12", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_CACHE_CHANGE; - rtps.cc := cc3; - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_CACHE_CHANGE SN 13", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_CACHE_CHANGE; - rtps.cc := cc1; - start_rtps; - wait_on_rtps; - - Log("RTPS Operation ACK_CACHE_CHANGE SN 12", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := ACK_CACHE_CHANGE; - rtps.cc := cc3; - start_rtps; - wait_on_rtps; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := NOT_ALIVE_UNREGISTERED; - cc.instance := kh2; - cc.payload := gen_payload(kh2,5); - cc.seq_nr := gen_sn(14); - cc.src_timestamp := gen_duration(14,0); - - Log("DDS Operation UNREGISTER_INSTANCE [TS 14s, Instance 2] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_TEST; - dds.opcode := UNREGISTER_INSTANCE; - dds.cc := cc; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc3 := cc; - -- Stored CC: I4S13, I1S10, I2S14, I4S11 - - Log("RTPS Operation ACK_CACHE_CHANGE SN 11", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := ACK_CACHE_CHANGE; - rtps.cc := cc4; - start_rtps; - wait_on_rtps; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh4; - cc.payload := gen_payload(kh4,20); - cc.seq_nr := gen_sn(15); - cc.src_timestamp := gen_duration(15,0); - - -- TEST: ADD SAMPLE BIGGER THAN AVAILABLE MEMORY SPACE [WITH ACKed SAMPLES] - - Log("DDS Operation WRITE [TS 15s, Instance 4, Aligned Payload (2 Slots)] (REJECTED: Payload Memory Full)", INFO); - dds := DEFAULT_DDS_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.ret_code := RETCODE_OUT_OF_RESOURCES; - start_dds; - wait_on_dds; - - Log("RTPS Operation REMOVE_CACHE_CHANGE SN 11", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := REMOVE_CACHE_CHANGE; - rtps.cc := cc4; - start_rtps; - wait_on_rtps; - -- Stored CC: I4S13, I1S10, I2S14, 0 - - Log("DDS Operation WRITE [TS 15s, Instance 4, Aligned Payload (2 Slots)] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc4 := cc; - -- Stored CC: I4S13, I1S10, I2S14, I4S15 - - -- TEST: UNREGISTER INSTANCE ON PAYLOAD MEMORY FULL [WITHOUT ACKed SAMPLES] - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := NOT_ALIVE_UNREGISTERED; - cc.instance := kh1; - cc.payload := gen_payload(kh1,5); - cc.seq_nr := gen_sn(16); - cc.src_timestamp := gen_duration(16,0); - - Log("DDS Operation UNREGISTER_INSTANCE [TS 16s, Instance 1] (REJECTED: Payload memory Full, MAX_SAMPLES exceeded)", INFO); - dds := DEFAULT_DDS_TEST; - dds.opcode := UNREGISTER_INSTANCE; - dds.cc := cc; - dds.ret_code := RETCODE_OUT_OF_RESOURCES; - start_dds; - wait_on_dds; - - Log("RTPS Operation ACK_CACHE_CHANGE SN 10", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := ACK_CACHE_CHANGE; - rtps.cc := cc2; - start_rtps; - wait_on_rtps; - - -- TEST: UNREGISTER INSTANCE ON PAYLOAD MEMORY FULL [WITH ACKed SAMPLES] - - Log("DDS Operation UNREGISTER_INSTANCE [TS 16s, Instance 1] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_TEST; - dds.opcode := UNREGISTER_INSTANCE; - dds.cc := cc; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc2 := cc; - -- Stored CC: I4S13, I1S16, I2S14, I4S15 - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := NOT_ALIVE_DISPOSED; - cc.instance := kh3; - cc.payload := gen_payload(kh3,5); - cc.seq_nr := gen_sn(17); - cc.src_timestamp := gen_duration(17,0); - - -- TEST: DISPOSE ON PAYLOAD MEMORY FULL [WITHOUT ACKed SAMPLES] - - Log("DDS Operation DISPOSE [TS 17s, Instance 3] (REJECTED: Payload memory Full, MAX_SAMPLES exceeded)", INFO); - dds := DEFAULT_DDS_TEST; - dds.opcode := DISPOSE; - dds.cc := cc; - dds.cc.instance:= HANDLE_NIL; - dds.ret_code := RETCODE_OUT_OF_RESOURCES; - start_dds; - wait_on_dds; - - Log("RTPS Operation ACK_CACHE_CHANGE SN 13", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := ACK_CACHE_CHANGE; - rtps.cc := cc1; - start_rtps; - wait_on_rtps; - - Log("RTPS Operation ACK_CACHE_CHANGE SN 14", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := ACK_CACHE_CHANGE; - rtps.cc := cc3; - start_rtps; - wait_on_rtps; - - -- TEST: DISPOSE ON PAYLOAD MEMORY FULL [WITH ACKed SAMPLES] - -- TEST: ADD SAMPLE ON PAYLOAD FULL & MAX_INSTANCES [UNKNOWN INSTANCE,WITH ACKed SAMPLES,WITH STALE INSTANCE (>= 1 SAMPLE)] (Induce Double Remove) - -- TEST: REMOVE STALE INSTANCE WITH 1 SAMPLES - - Log("DDS Operation DISPOSE [TS 17s, Instance 3] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_TEST; - dds.opcode := DISPOSE; - dds.cc := cc; - dds.cc.instance:= HANDLE_NIL; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc1 := cc; - -- Stored CC: I3S17, I1S16, 0, I4S15 - - -- VALIDATE STATE - - Log("RTPS Operation GET_MIN_SN (Expected SN 15)", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_MIN_SN; - rtps.cc.seq_nr := gen_sn(15); - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_MAX_SN (Expected SN 17)", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_MAX_SN; - rtps.cc.seq_nr := gen_sn(17); - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_CACHE_CHANGE SN 15", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_CACHE_CHANGE; - rtps.cc := cc4; - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_CACHE_CHANGE SN 16", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_CACHE_CHANGE; - rtps.cc := cc2; - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_CACHE_CHANGE SN 17", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_CACHE_CHANGE; - rtps.cc := cc1; - start_rtps; - wait_on_rtps; - - Log("RTPS Operation REMOVE_CACHE_CHANGE SN 15", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := REMOVE_CACHE_CHANGE; - rtps.cc := cc4; - start_rtps; - wait_on_rtps; - -- Stored CC: I3S17, I1S16, 0, 0 - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh3; - cc.payload := gen_payload(kh3,10); - cc.seq_nr := gen_sn(18); - cc.src_timestamp := gen_duration(18,0); - - -- TEST: WRITE ON DISPOSED INSTANCE - - Log("DDS Operation WRITE [TS 18s, Instance 3, Aligned Payload] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc3 := cc; - -- Stored CC: I3S17, I1S16, I3S18, 0 - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh4; - cc.payload := gen_payload(kh4,10); - cc.seq_nr := gen_sn(19); - cc.src_timestamp := gen_duration(19,0); - - Log("DDS Operation WRITE [TS 19s, Instance 4, Aligned Payload] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc4 := cc; - -- Stored CC: I3S17, I1S16, I3S18, I4S19 - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh2; - cc.payload := gen_payload(kh2,10); - cc.seq_nr := gen_sn(20); - cc.src_timestamp := gen_duration(20,0); - - -- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE,WITHOUT STALE INSTANCES,WITHOUT ACKed SAMPLES] - - Log("DDS Operation WRITE [TS 20s, Instance 2, Aligned Payload] (REJECTED: MAX_SAMPLES exceeded, MAX_INSTANCES exceeded)", INFO); - dds := DEFAULT_DDS_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.cc.instance:= HANDLE_NIL; - dds.ret_code := RETCODE_OUT_OF_RESOURCES; - start_dds; - wait_on_dds; - - Log("RTPS Operation ACK_CACHE_CHANGE SN 16", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := ACK_CACHE_CHANGE; - rtps.cc := cc2; - start_rtps; - wait_on_rtps; - - -- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE,WITH STALE INSTANCE (>0 SAMPLES)] - - Log("DDS Operation WRITE [TS 20s, Instance 2, Aligned Payload] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.cc.instance:= HANDLE_NIL; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc2 := cc; - -- Stored CC: I3S17, I2S20, I3S18, I4S19 - - Log("RTPS Operation ACK_CACHE_CHANGE SN 17", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := ACK_CACHE_CHANGE; - rtps.cc := cc1; - start_rtps; - wait_on_rtps; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := NOT_ALIVE_UNREGISTERED; - cc.instance := kh4; - cc.payload := gen_payload(kh4,5); - cc.seq_nr := gen_sn(21); - cc.src_timestamp := gen_duration(21,0); - - Log("DDS Operation UNREGISTER_INSTANCE [TS 21s, Instance 4] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_TEST; - dds.opcode := UNREGISTER_INSTANCE; - dds.cc := cc; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc1 := cc; - -- Stored CC: I4S21, I2S20, I3S18, I4S19 - - Log("RTPS Operation ACK_CACHE_CHANGE SN 19", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := ACK_CACHE_CHANGE; - rtps.cc := cc4; - start_rtps; - wait_on_rtps; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh1; - cc.payload := gen_payload(kh1,10); - cc.seq_nr := gen_sn(22); - cc.src_timestamp := gen_duration(22,0); - - -- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE,WITHOUT STALE INSTANCE, WITH ACKed SAMPLE] - - Log("DDS Operation WRITE [TS 22s, Instance 1, Aligned Payload] (REJECTED: MAX_SAMPLES exceeded, MAX_INSTANCES exceeded)", INFO); - dds := DEFAULT_DDS_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.cc.instance:= HANDLE_NIL; - dds.ret_code := RETCODE_OUT_OF_RESOURCES; - start_dds; - wait_on_dds; - - Log("RTPS Operation REMOVE_CACHE_CHANGE SN 19", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := REMOVE_CACHE_CHANGE; - rtps.cc := cc4; - start_rtps; - wait_on_rtps; - -- Stored CC: I4S21, I2S20, I3S18, 0 - - Log("RTPS Operation REMOVE_CACHE_CHANGE SN 21", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := REMOVE_CACHE_CHANGE; - rtps.cc := cc1; - start_rtps; - wait_on_rtps; - -- Stored CC: 0, I2S20, I3S18, 0 - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := NOT_ALIVE_UNREGISTERED; - cc.instance := kh2; - cc.payload := gen_payload(kh2,5); - cc.seq_nr := gen_sn(22); - cc.src_timestamp := gen_duration(22,0); - - Log("DDS Operation UNREGISTER_INSTANCE [TS 22s, Instance 2] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_TEST; - dds.opcode := UNREGISTER_INSTANCE; - dds.cc := cc; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc1 := cc; - -- Stored CC: I2S22, I2S20, I3S18, 0 - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := NOT_ALIVE_UNREGISTERED; - cc.instance := kh3; - cc.payload := gen_payload(kh3,5); - cc.seq_nr := gen_sn(23); - cc.src_timestamp := gen_duration(23,0); - - Log("DDS Operation UNREGISTER_INSTANCE [TS 23s, Instance 3] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_TEST; - dds.opcode := UNREGISTER_INSTANCE; - dds.cc := cc; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc4 := cc; - -- Stored CC: I2S22, I2S20, I3S18, I3S23 - - -- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE,WITH STALE INSTANCE, WITHOUT ACKed SAMPLE] - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh1; - cc.payload := gen_payload(kh1,10); - cc.seq_nr := gen_sn(24); - cc.src_timestamp := gen_duration(24,0); - - Log("DDS Operation WRITE [TS 24s, Instance 1, Aligned Payload] (REJECTED: MAX_SAMPLES exceeded, MAX_INSTANCES exceeded)", INFO); - dds := DEFAULT_DDS_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.cc.instance:= HANDLE_NIL; - dds.ret_code := RETCODE_OUT_OF_RESOURCES; - start_dds; - wait_on_dds; - - Log("RTPS Operation ACK_CACHE_CHANGE SN 20", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := ACK_CACHE_CHANGE; - rtps.cc := cc2; - start_rtps; - wait_on_rtps; - - -- TEST: REMOVE STALE INSTANCE WITH 0 SAMPLES - -- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE,WITH STALE INSTANCE, WITH ACKed SAMPLE] - - Log("DDS Operation WRITE [TS 24s, Instance 1, Aligned Payload] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.cc.instance:= HANDLE_NIL; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc2 := cc; - -- Stored CC: I2S22, I1S24, I3S18, I3S23 - - Log("RTPS Operation ACK_CACHE_CHANGE SN 22", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := ACK_CACHE_CHANGE; - rtps.cc := cc1; - start_rtps; - wait_on_rtps; - - -- TEST: NORMAL NACK_CACHE_CHANGE - - Log("RTPS Operation NACK_CACHE_CHANGE SN 22", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := NACK_CACHE_CHANGE; - rtps.cc := cc1; - start_rtps; - wait_on_rtps; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh4; - cc.payload := gen_payload(kh4,10); - cc.seq_nr := gen_sn(25); - cc.src_timestamp := gen_duration(25,0); - - Log("DDS Operation REGISTER_INSTANCE 4 (REJECTED: MAX_INSTANCES exceeded)", INFO); - dds := DEFAULT_DDS_TEST; - dds.opcode := REGISTER_INSTANCE; - dds.cc := cc; - dds.cc.instance:= HANDLE_NIL; - start_dds; - wait_on_dds; - - Log("RTPS Operation ACK_CACHE_CHANGE SN 22", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := ACK_CACHE_CHANGE; - rtps.cc := cc1; - start_rtps; - wait_on_rtps; - - -- TEST: REGISTER ON UNREGISTERED INSTANCE - - Log("DDS Operation REGISTER_INSTANCE 2 (ACCEPTED)", INFO); - dds := DEFAULT_DDS_TEST; - dds.opcode := REGISTER_INSTANCE; - dds.cc := cc1; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - - Log("DDS Operation REGISTER_INSTANCE 4 (REJECTED: MAX_INSTANCES exceeded)", INFO); - dds := DEFAULT_DDS_TEST; - dds.opcode := REGISTER_INSTANCE; - dds.cc := cc; - dds.cc.instance:= HANDLE_NIL; - start_dds; - wait_on_dds; - - Log("RTPS Operation ACK_CACHE_CHANGE SN 18", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := ACK_CACHE_CHANGE; - rtps.cc := cc3; - start_rtps; - wait_on_rtps; - - Log("RTPS Operation ACK_CACHE_CHANGE SN 23", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := ACK_CACHE_CHANGE; - rtps.cc := cc4; - start_rtps; - wait_on_rtps; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh3; - cc.payload := gen_payload(kh3,10); - cc.seq_nr := gen_sn(25); - cc.src_timestamp := gen_duration(25,0); - - -- TEST: WRITE ON UNREGISTERED INSTANCE - - Log("DDS Operation WRITE [TS 25s, Instance 3, Aligned Payload] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.cc.instance:= HANDLE_NIL; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc3 := cc; - -- Stored CC: I2S22, I1S24, I3S25, I3S23 - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh4; - cc.payload := gen_payload(kh4,10); - cc.seq_nr := gen_sn(26); - cc.src_timestamp := gen_duration(26,0); - - Log("DDS Operation REGISTER_INSTANCE 4 (REJECTED: MAX_INSTANCES exceeded)", INFO); - dds := DEFAULT_DDS_TEST; - dds.opcode := REGISTER_INSTANCE; - dds.cc := cc; - dds.cc.instance:= HANDLE_NIL; - start_dds; - wait_on_dds; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := NOT_ALIVE_UNREGISTERED; - cc.instance := kh4; - cc.payload := gen_payload(kh4,5); - cc.seq_nr := gen_sn(26); - cc.src_timestamp := gen_duration(26,0); - - -- TEST: UNREGISTER UNKNOWN INSTANCE - - Log("DDS Operation UNREGISTER_INSTANCE [TS 26s, HANDLE_NIL, Instance 4] (IGNORED)", INFO); - dds := DEFAULT_DDS_TEST; - dds.opcode := UNREGISTER_INSTANCE; - dds.cc := cc; - dds.cc.instance:= HANDLE_NIL; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - - Log("RTPS Operation NACK_CACHE_CHANGE SN 22", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := NACK_CACHE_CHANGE; - rtps.cc := cc1; - start_rtps; - wait_on_rtps; - - Log("RTPS Operation NACK_CACHE_CHANGE SN 23", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := NACK_CACHE_CHANGE; - rtps.cc := cc4; - start_rtps; - wait_on_rtps; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_UNREGISTERED; - cc.instance := kh3; - cc.payload := gen_payload(kh3,5); - cc.seq_nr := gen_sn(26); - cc.src_timestamp := gen_duration(26,0); - - -- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE,WITHOUT ACKed SAMPLES] - - Log("DDS Operation UNREGISTER_INSTANCE [TS 26s, Instance 3] (REJECTED: MAX_SAMPLES_PER_INSTANCE exceeded, MAX_SAMPLES exceeded)", INFO); - dds := DEFAULT_DDS_TEST; - dds.opcode := UNREGISTER_INSTANCE; - dds.cc := cc; - dds.ret_code := RETCODE_OUT_OF_RESOURCES; - start_dds; - wait_on_dds; - - Log("RTPS Operation ACK_CACHE_CHANGE SN 22", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := ACK_CACHE_CHANGE; - rtps.cc := cc1; - start_rtps; - wait_on_rtps; - - -- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE,WITH ACKed SAMPLES, WITHOUT ACKed INSTANCE SAMPLES] - - Log("DDS Operation UNREGISTER_INSTANCE [TS 26s, Instance 3] (REJECTED: MAX_SAMPLES_PER_INSTANCE exceeded, MAX_SAMPLES exceeded)", INFO); - dds := DEFAULT_DDS_TEST; - dds.opcode := UNREGISTER_INSTANCE; - dds.cc := cc; - dds.ret_code := RETCODE_OUT_OF_RESOURCES; - start_dds; - wait_on_dds; - - Log("RTPS Operation ACK_CACHE_CHANGE SN 23", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := ACK_CACHE_CHANGE; - rtps.cc := cc4; - start_rtps; - wait_on_rtps; - - -- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE,WITH ACKed INSTANCE SAMPLES] - - Log("DDS Operation UNREGISTER_INSTANCE [TS 26s, Instance 3] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_TEST; - dds.opcode := UNREGISTER_INSTANCE; - dds.cc := cc; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc4 := cc; - -- Stored CC: I2S22, I1S24, I3S25, I3S26 - - Log("RTPS Operation ACK_CACHE_CHANGE SN 25", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := ACK_CACHE_CHANGE; - rtps.cc := cc3; - start_rtps; - wait_on_rtps; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_DISPOSED; - cc.instance := kh3; - cc.payload := gen_payload(kh3,5); - cc.seq_nr := gen_sn(27); - cc.src_timestamp := gen_duration(27,0); - - -- TEST: DISPOSE ON UNREGISTERED INSTANCE - - Log("DDS Operation DISPOSE [TS 27s, Instance 3] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_TEST; - dds.opcode := DISPOSE; - dds.cc := cc; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc3 := cc; - -- Stored CC: I2S22, I1S24, I3S27, I3S26 - - Log("RTPS Operation ACK_CACHE_CHANGE SN 26", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := ACK_CACHE_CHANGE; - rtps.cc := cc4; - start_rtps; - wait_on_rtps; - - Log("RTPS Operation ACK_CACHE_CHANGE SN 27", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := ACK_CACHE_CHANGE; - rtps.cc := cc3; - start_rtps; - wait_on_rtps; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh4; - cc.payload := gen_payload(kh4,10); - cc.seq_nr := gen_sn(28); - cc.src_timestamp := gen_duration(28,0); - - Log("DDS Operation REGISTER_INSTANCE 4 (ACCEPTED)", INFO); - dds := DEFAULT_DDS_TEST; - dds.opcode := REGISTER_INSTANCE; - dds.cc := cc; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - -- Stored CC: I2S22, I1S24, 0, 0 - - -- VALIDATE STATE - - Log("RTPS Operation GET_MIN_SN (Expected SN 22)", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_MIN_SN; - rtps.cc.seq_nr := gen_sn(22); - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_MAX_SN (Expected SN 24)", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_MAX_SN; - rtps.cc.seq_nr := gen_sn(24); - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_CACHE_CHANGE SN 22", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_CACHE_CHANGE; - rtps.cc := cc1; - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_CACHE_CHANGE SN 24", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_CACHE_CHANGE; - rtps.cc := cc2; - start_rtps; - wait_on_rtps; - - Log("RTPS Operation NACK_CACHE_CHANGE SN 22", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := NACK_CACHE_CHANGE; - rtps.cc := cc1; - start_rtps; - wait_on_rtps; - - Log("RTPS Operation NACK_CACHE_CHANGE SN 24", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := NACK_CACHE_CHANGE; - rtps.cc := cc2; - start_rtps; - wait_on_rtps; - - Log("DDS Operation WRITE [TS 28s, Instance 4, Aligned Payload] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc3 := cc; - -- Stored CC: I2S22, I1S24, I4S28, 0 - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh2; - cc.payload := gen_payload(kh2,10); - cc.seq_nr := gen_sn(29); - cc.src_timestamp := gen_duration(29,0); - - Log("DDS Operation WRITE [TS 29s, Instance 2, Aligned Payload] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc4 := cc; - -- Stored CC: I2S22, I1S24, I4S28, I2S29 - - Log("RTPS Operation ACK_CACHE_CHANGE SN 24", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := ACK_CACHE_CHANGE; - rtps.cc := cc2; - start_rtps; - wait_on_rtps; - - Log("RTPS Operation ACK_CACHE_CHANGE SN 28", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := ACK_CACHE_CHANGE; - rtps.cc := cc3; - start_rtps; - wait_on_rtps; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh1; - cc.payload := gen_payload(kh1,10); - cc.seq_nr := gen_sn(30); - cc.src_timestamp := gen_duration(30,0); - - -- TEST: ADD SAMPLE ON MAX_SAMPLES [KNOWN INSTANCE,WITH ACKed SAMPLES (>1)] - - Log("DDS Operation WRITE [TS 30s, Instance 1, Aligned Payload] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc2 := cc; - -- Stored CC: I2S22, I1S30, I4S28, I2S29 - - Log("RTPS Operation REMOVE_CACHE_CHANGE SN 28", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := REMOVE_CACHE_CHANGE; - rtps.cc := cc3; - start_rtps; - wait_on_rtps; - -- Stored CC: I2S22, I1S30, 0, I2S29 - - Log("RTPS Operation ACK_CACHE_CHANGE SN 22", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := ACK_CACHE_CHANGE; - rtps.cc := cc1; - start_rtps; - wait_on_rtps; - - Log("RTPS Operation ACK_CACHE_CHANGE SN 29", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := ACK_CACHE_CHANGE; - rtps.cc := cc4; - start_rtps; - wait_on_rtps; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh2; - cc.payload := gen_payload(kh2,10); - cc.seq_nr := gen_sn(31); - cc.src_timestamp := gen_duration(31,0); - - -- TEST: ADD SAMPLE ON MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE, WITH ACKed INSTANCE SAMPLES(>1)] - - Log("DDS Operation WRITE [TS 31s, Instance 2, Aligned Payload] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc1 := cc; - -- Stored CC: I2S31, I1S30, 0, I2S29 - - -- VALIDATE STATE - - Log("RTPS Operation GET_MIN_SN (Expected SN 29)", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_MIN_SN; - rtps.cc.seq_nr := gen_sn(29); - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_MAX_SN (Expected SN 31)", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_MAX_SN; - rtps.cc.seq_nr := gen_sn(31); - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_CACHE_CHANGE SN 29", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_CACHE_CHANGE; - rtps.cc := cc4; - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_CACHE_CHANGE SN 30", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_CACHE_CHANGE; - rtps.cc := cc2; - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_CACHE_CHANGE SN 31", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_CACHE_CHANGE; - rtps.cc := cc1; - start_rtps; - wait_on_rtps; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh1; - cc.payload := gen_payload(kh1,10); - cc.seq_nr := gen_sn(1); - cc.src_timestamp := gen_duration(1,0); - - -- TEST: INSTANCE LOOKUP [KNOWN INSTANCE] - - Log("DDS Operation LOOKUP_INSTANCE [Instance 1]", INFO); - dds := DEFAULT_DDS_TEST; - dds.opcode := LOOKUP_INSTANCE; - dds.cc := cc; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh3; - cc.payload := gen_payload(kh3,10); - cc.seq_nr := gen_sn(1); - cc.src_timestamp := gen_duration(1,0); - - -- TEST: INSTANCE LOOKUP [UNKNOWN INSTANCE] - - Log("DDS Operation LOOKUP_INSTANCE [Unknown Instance]", INFO); - dds := DEFAULT_DDS_TEST; - dds.opcode := LOOKUP_INSTANCE; - dds.cc := cc; - dds.cc.instance:= HANDLE_NIL; - start_dds; - wait_on_dds; - - wait_on_completion; - TranscriptOpen(RESULTS_FILE, APPEND_MODE); - SetTranscriptMirror; - ReportAlerts; - TranscriptClose; - std.env.stop; - wait; - end process; - - clock_prc : process - begin - clk <= '0'; - wait for 25 ns; - clk <= '1'; - wait for 25 ns; - end process; - - alert_prc : process(all) - begin - if rising_edge(clk) then - -- TODO - end if; - end process; - - dds_prc : process(all) - begin - if rising_edge(clk) then - dds_done <= '0'; - case (dds_stage) is - when IDLE => - if (dds_start = '1') then - dds_stage <= START; - else - dds_done <= '1'; - end if; - when START => - if (ack_dds = '1') then - dds_stage <= PUSH; - dds_cnt <= 0; - end if; - when PUSH => - if (ready_in_dds = '1') then - dds_cnt <= dds_cnt + 1; - if (dds_cnt = dds.cc.payload.length-1) then - -- DEFAULT - dds_stage <= DONE; - end if; - end if; - when DONE => - if (done_dds = '1') then - if (dds.opcode = REGISTER_INSTANCE or dds.opcode = LOOKUP_INSTANCE) then - AffirmIfEqual(ih_id, to_unsigned(instance_handle_out_dds), to_unsigned(dds.cc.instance)); - else - AffirmIfEqual(ret_id, return_code_dds, dds.ret_code); - end if; - dds_stage <= IDLE; - end if; - end case; - end if; - - -- DEFAULT - start_dds <= '0'; - opcode_dds <= NOP; - valid_in_dds <= '0'; - last_word_in_dds <= '0'; - data_in_dds <= (others => '0'); - instance_handle_in_dds <= HANDLE_NIL; - source_ts_dds <= TIME_INVALID; - ready_out_dds <= '0'; - - case (dds_stage) is - when START => - start_dds <= '1'; - opcode_dds <= dds.opcode; - instance_handle_in_dds <= dds.cc.instance; - source_ts_dds <= dds.cc.src_timestamp; - when PUSH => - valid_in_dds <= '1'; - data_in_dds <= dds.cc.payload.data(dds_cnt); - last_word_in_dds <= dds.cc.payload.last(dds_cnt); - when others => - null; - end case; - end process; - - rtps_prc : process(all) - begin - if rising_edge(clk) then - rtps_done <= '0'; - case (rtps_stage) is - when IDLE => - if (rtps_start = '1') then - rtps_stage <= START; - else - rtps_done <= '1'; - end if; - when START => - if (ack_rtps = '1') then - rtps_stage <= DONE; - end if; - when DONE => - if (done_rtps = '1') then - -- DEFAULT - rtps_stage <= IDLE; - - AffirmIfEqual(ret_id, HISTORY_CACHE_RESPONSE_TYPE'pos(ret_rtps), HISTORY_CACHE_RESPONSE_TYPE'pos(rtps.ret_code)); - case (rtps.opcode) is - when GET_CACHE_CHANGE => - if (rtps.ret_code = OK) then - AffirmIfEqual(inst_id, to_unsigned(cc_instance_handle), to_unsigned(rtps.cc.instance)); - AffirmIfEqual(kind_id, CACHE_CHANGE_KIND_TYPE'pos(cc_kind), CACHE_CHANGE_KIND_TYPE'pos(rtps.cc.kind)); - AffirmIfEqual(sn_id, to_unsigned(cc_seq_nr), to_unsigned(rtps.cc.seq_nr)); - AffirmIfEqual(ts_id, to_unsigned(cc_source_timestamp), to_unsigned(rtps.cc.src_timestamp)); - rtps_stage <= CHECK; - rtps_cnt <= 0; - end if; - when GET_MIN_SN => - AffirmIfEqual(sn_id, to_unsigned(cc_seq_nr), to_unsigned(rtps.cc.seq_nr)); - when GET_MAX_SN => - AffirmIfEqual(sn_id, to_unsigned(cc_seq_nr), to_unsigned(rtps.cc.seq_nr)); - when others => - null; - end case; - end if; - when CHECK => - if (valid_out_rtps = '1') then - AffirmIfEqual(ih_id, last_word_out_rtps & data_out_rtps, rtps.cc.payload.last(rtps_cnt) & rtps.cc.payload.data(rtps_cnt)); - rtps_cnt <= rtps_cnt + 1; - if (rtps_cnt = rtps.cc.payload.length-1) then - rtps_stage <= IDLE; - end if; - end if; - end case; - end if; - - -- DEFAULT - start_rtps <= '0'; - opcode_rtps <= NOP; - seq_nr_rtps <= SEQUENCENUMBER_UNKNOWN; - get_data_rtps <= '0'; - ready_out_rtps <= '0'; - - case (rtps_stage) is - when START => - start_rtps <= '1'; - opcode_rtps <= rtps.opcode; - seq_nr_rtps <= rtps.cc.seq_nr; - when DONE => - if (done_rtps = '1') then - case (rtps.opcode) is - when GET_CACHE_CHANGE => - get_data_rtps <= '1'; - when others => - null; - end case; - end if; - when CHECK => - ready_out_rtps <= '1'; - when others => - null; - end case; - end process; - - watchdog : process - begin - wait for 1 ms; - Alert("Test timeout", FAILURE); - std.env.stop; - end process; - -end architecture; \ No newline at end of file diff --git a/src/Tests/Level_0/L0_dds_writer_test1_aik.txt b/src/Tests/Level_0/L0_dds_writer_test1_aik.txt deleted file mode 100644 index 97efd6f..0000000 --- a/src/Tests/Level_0/L0_dds_writer_test1_aik.txt +++ /dev/null @@ -1,270 +0,0 @@ - SAMPLE MEMORY: -/0,9,18,27,36 - PAYLOAD MEMORY: -/0,11,22,33,44 - INSTANCE MEMORY: -/0,8,16 -RTPS Operation GET_MIN_SN (Expected SEQUENCENUMBER_UNKNOWN) -RTPS Operation GET_MAX_SN (Expected SEQUENCENUMBER_UNKNOWN) -DDS Operation WRITE [TS 1s, Instance 1] (REJECTED: Instance not Registered) -DDS Operation WRITE [TS 1s, Instance 1, HANDLE_NIL] (ACCEPTED) - SAMPLE MEMORY: 0(I1S1)/9,18,27,36 - PAYLOAD MEMORY: 0(I1S1)/11,22,33,44 - INSTANCE MEMORY: 0(I1)/8,16 -RTPS Operation GET_MIN_SN (Expected SN 1) -RTPS Operation GET_MAX_SN (Expected SN 1) -DDS Operation WRITE [TS 2s, Instance 2, Unaligned Payload (2 Slots)] (REJECTED: Instance not Registered) -DDS Operation REGISTER_INSTANCE 2 (ACCEPTED) - SAMPLE MEMORY: 0(I1S1)/9,18,27,36 - PAYLOAD MEMORY: 0(I1S1)/11,22,33,44 - INSTANCE MEMORY: 8(I2),0(I1)/16 -DDS Operation WRITE [TS 2s, Instance 2, Unaligned Payload (2 Slots)] (ACCEPTED) - SAMPLE MEMORY: 0(I1S1),9(I2S2)/18,27,36 - PAYLOAD MEMORY: 0(I1S1),11(I2S2),22(I2S2)/33,44 - INSTANCE MEMORY: 8(I2),0(I1)/16 -DDS Operation WRITE [TS 3s, Instance 1, Unaligned Payload (2 Slots)] (ACCEPTED) - SAMPLE MEMORY: 0(I1S1),9(I2S2),18(I1S3)/27,36 - PAYLOAD MEMORY: 0(I1S1),11(I2S2),22(I2S2),33(I1S3),44(I1S3)/- - INSTANCE MEMORY: 8(I2),0(I1)/16 -RTPS Operation GET_CACHE_CHANGE SN 4 (Invalid) -RTPS Operation GET_CACHE_CHANGE SN 1 -RTPS Operation GET_CACHE_CHANGE SN 2 -RTPS Operation GET_CACHE_CHANGE SN 3 -DDS Operation WRITE [TS 4s, Instance 3, HANDLE_NIL, Unaligned Payload (1 Slot)] (REJECTED: Payload Memory Full) -RTPS Operation REMOVE_CACHE_CHANGE SN 5 (Invalid) -RTPS Operation REMOVE_CACHE_CHANGE SN 2 - SAMPLE MEMORY: 0(I1S1),18(I1S3)/27,36,9 - PAYLOAD MEMORY: 0(I1S1),33(I1S3),44(I1S3)/11,22 - INSTANCE MEMORY: 8(I2),0(I1)/16 -DDS Operation WRITE [TS 4s, Instance 3, HANDLE_NIL, Unaligned Payload (1 Slot)] (ACCEPTED) - SAMPLE MEMORY: 0(I1S1),18(I1S3),27(I3S4)/36,9 - PAYLOAD MEMORY: 0(I1S1),33(I1S3),44(I1S3),11(I3S4)/22 - INSTANCE MEMORY: 16(I3),8(I2),0(I1)/- -RTPS Operation GET_CACHE_CHANGE SN 4 -DDS Operation REGISTER_INSTANCE 3 (No Change) -DDS Operation DISPOSE [TS 5s, Instance 1] (REJECTED: MAX_SAMPLES_PER_INSTANCE Exceeded) -RTPS Operation ACK_CACHE_CHANGE SN 4 -DDS Operation DISPOSE [TS 5s, Instance 1] (REJECTED: MAX_SAMPLES_PER_INSTANCE Exceeded) -RTPS Operation ACK_CACHE_CHANGE SN 1 -DDS Operation DISPOSE [TS 5s, Instance 1] (ACCEPTED) - SAMPLE MEMORY: 18(I1S3),27(I3S4),36(I1S5)/9,0 - PAYLOAD MEMORY: 33(I1S3),44(I1S3),11(I3S4),22(I1S5)/0 - INSTANCE MEMORY: 16(I3),8(I2),0(I1)/- -RTPS Operation GET_MIN_SN (Expected SN 3) -RTPS Operation GET_MAX_SN (Expected SN 5) -RTPS Operation GET_CACHE_CHANGE SN 5 -DDS Operation WRITE [TS 6s, Instance 4, HANDLE_NIL, Aligned Payload] (REJECTED: MAX_INSTANCES exceeded) -RTPS Operation ACK_CACHE_CHANGE SN 3 -RTPS Operation ACK_CACHE_CHANGE SN 4 -RTPS Operation ACK_CACHE_CHANGE SN 5 -DDS Operation WRITE [TS 6s, Instance 4, HANDLE_NIL, Aligned Payload] (REJECTED: MAX_INSTANCES exceeded) -DDS Operation UNREGISTER_INSTANCE [TS 6s, Instance 1] (ACCEPTED) - SAMPLE MEMORY: 27(I3S4),36(I1S5),9(I1S6)/0,18 - PAYLOAD MEMORY: 11(I3S4),22(I1S5),0(I1S6)/33,44 - INSTANCE MEMORY: 16(I3),8(I2),0(I1)/- -RTPS Operation GET_MIN_SN (Expected SN 4) -RTPS Operation GET_MAX_SN (Expected SN 6) -RTPS Operation GET_CACHE_CHANGE SN 6 -DDS Operation WRITE [TS 7s, Instance 4, HANDLE_NIL, Aligned Payload] (REJECTED: MAX_INSTANCES exceeded) -RTPS Operation ACK_CACHE_CHANGE SN 6 -DDS Operation WRITE [TS 7s, Instance 4, HANDLE_NIL, Aligned Payload] (ACCEPTED) - SAMPLE MEMORY: 27(I3S4),0(I4S7)/18,36,9 - PAYLOAD MEMORY: 11(I3S4),33(I4S7)/0,22,44 - INSTANCE MEMORY: 0(I4),16(I3),8(I2)/- -RTPS Operation GET_CACHE_CHANGE SN 5 (Invalid) -RTPS Operation GET_CACHE_CHANGE SN 6 (Invalid) -RTPS Operation GET_CACHE_CHANGE SN 7 -DDS Operation WRITE [TS 8s, Instance 2, Unaligned Payload (2 Slots)] (ACCEPTED) - SAMPLE MEMORY: 27(I3S4),0(I4S7),18(I2S8)/36,9 - PAYLOAD MEMORY: 11(I3S4),33(I4S7),0(I2S8),22(I2S8)/44 - INSTANCE MEMORY: 0(I4),16(I3),8(I2)/- -DDS Operation WRITE [TS 9s, Instance 1, Aligned Payload] (REJECTED: Instance not Registered) -DDS Operation REGISTER_INSTANCE 1 (REJECTED: MAX_INSTANCES exceeded) -DDS Operation UNREGISTER_INSTANCE [TS 9s, Instance 3] (ACCEPTED) - SAMPLE MEMORY: 27(I3S4),0(I4S7),18(I2S8),36(I3S9)/9 - PAYLOAD MEMORY: 11(I3S4),33(I4S7),0(I2S8),22(I2S8),44(I3S9)/- - INSTANCE MEMORY: 0(I4),16(I3),8(I2)/- -RTPS Operation GET_MIN_SN (Expected SN 4) -RTPS Operation GET_MAX_SN (Expected SN 9) -RTPS Operation GET_CACHE_CHANGE SN 8 -RTPS Operation GET_CACHE_CHANGE SN 9 -RTPS Operation ACK_CACHE_CHANGE SN 9 -DDS Operation REGISTER_INSTANCE 1 (ACCPETED) - SAMPLE MEMORY: 0(I4S7),18(I2S8)/9,27,36 - PAYLOAD MEMORY: 33(I4S7),0(I2S8),22(I2S8)/44,11 - INSTANCE MEMORY: 16(I1),0(I4),8(I2)/- -DDS Operation WRITE [TS 10s, Instance 1, Aligned Payload] (ACCEPTED) - SAMPLE MEMORY: 0(I4S7),18(I2S8),9(I1S10)/27,36 - PAYLOAD MEMORY: 33(I4S7),0(I2S8),22(I2S8),44(I1S10)/11 - INSTANCE MEMORY: 16(I1),0(I4),8(I2)/- -DDS Operation WRITE [TS 11s, Instance 1, Aligned Payload] (ACCEPTED) - SAMPLE MEMORY: 0(I4S7),18(I2S8),9(I1S10),27(I4S11)/36 - PAYLOAD MEMORY: 33(I4S7),0(I2S8),22(I2S8),44(I1S10),11(I4S11)/- - INSTANCE MEMORY: 16(I1),0(I4),8(I2)/- -DDS Operation WRITE [TS 12s, Instance 2, Aligned Payload] (REJECTED: Payload Memory Full) -RTPS Operation ACK_CACHE_CHANGE SN 8 -DDS Operation WRITE [TS 12s, Instance 2, Aligned Payload] (ACCEPTED) - SAMPLE MEMORY: 0(I4S7),9(I1S10),27(I4S11),36(I2S12)/18 - PAYLOAD MEMORY: 33(I4S7),44(I1S10),11(I4S11),0(I2S12)/22 - INSTANCE MEMORY: 16(I1),0(I4),8(I2)/- -DDS Operation WRITE [TS 13s, Instance 4, Aligned Payload] (REJECTED: MAX_SAMPLES exceeded) -RTPS Operation ACK_CACHE_CHANGE SN 7 -DDS Operation WRITE [TS 13s, Instance 4, Aligned Payload] (ACCEPTED) - SAMPLE MEMORY: 9(I1S10),27(I4S11),36(I2S12),18(I4S13)/0 - PAYLOAD MEMORY: 44(I1S10),11(I4S11),0(I2S12),22(I4S13)/33 - INSTANCE MEMORY: 16(I1),0(I4),8(I2)/- -RTPS Operation GET_MIN_SN (Expected SN 4) -RTPS Operation GET_MAX_SN (Expected SN 9) -RTPS Operation GET_CACHE_CHANGE SN 10 -RTPS Operation GET_CACHE_CHANGE SN 11 -RTPS Operation GET_CACHE_CHANGE SN 12 -RTPS Operation GET_CACHE_CHANGE SN 13 -RTPS Operation ACK_CACHE_CHANGE SN 12 -DDS Operation UNREGISTER_INSTANCE [TS 14s, Instance 2] (ACCEPTED) - SAMPLE MEMORY: 9(I1S10),27(I4S11),18(I4S13),0(I2S14)/36 - PAYLOAD MEMORY: 44(I1S10),11(I4S11),22(I4S13),33(I2S14)/0 - INSTANCE MEMORY: 16(I1),0(I4),8(I2)/- -RTPS Operation ACK_CACHE_CHANGE SN 11 -DDS Operation WRITE [TS 15s, Instance 4, Aligned Payload (2 Slots)] (REJECTED: Payload Memory Full) -RTPS Operation REMOVE_CACHE_CHANGE SN 11 - SAMPLE MEMORY: 9(I1S10),18(I4S13),0(I2S14)/36,27 - PAYLOAD MEMORY: 44(I1S10),22(I4S13),33(I2S14)/11,0 - INSTANCE MEMORY: 16(I1),0(I4),8(I2)/- -DDS Operation WRITE [TS 15s, Instance 4, Aligned Payload (2 Slots)] (ACCEPTED) - SAMPLE MEMORY: 9(I1S10),18(I4S13),0(I2S14),36(I4S15)/27 - PAYLOAD MEMORY: 44(I1S10),22(I4S13),33(I2S14),11(I4S15),0(I4S15)/- - INSTANCE MEMORY: 16(I1),0(I4),8(I2)/- -DDS Operation UNREGISTER_INSTANCE [TS 16s, Instance 1] (REJECTED: Payload memory Full, MAX_SAMPLES exceeded) -RTPS Operation ACK_CACHE_CHANGE SN 10 -DDS Operation UNREGISTER_INSTANCE [TS 16s, Instance 1] (ACCEPTED) - SAMPLE MEMORY: 18(I4S13),0(I2S14),36(I4S15),27(I1S16)/9 - PAYLOAD MEMORY: 22(I4S13),33(I2S14),11(I4S15),0(I4S15),44(I1S16)/- - INSTANCE MEMORY: 16(I1),0(I4),8(I2)/- -DDS Operation DISPOSE [TS 17s, Instance 3] (REJECTED: Payload memory Full, MAX_SAMPLES exceeded) -RTPS Operation ACK_CACHE_CHANGE SN 13 -RTPS Operation ACK_CACHE_CHANGE SN 14 -DDS Operation DISPOSE [TS 17s, Instance 3] (ACCEPTED) - SAMPLE MEMORY: 36(I4S15),27(I1S16),9(I3S17)/18,0 - PAYLOAD MEMORY: 11(I4S15),0(I4S15),44(I1S16),22(I3S17)/33 - INSTANCE MEMORY: 8(I3),16(I1),0(I4)/- -RTPS Operation GET_MIN_SN (Expected SN 15) -RTPS Operation GET_MAX_SN (Expected SN 17) -RTPS Operation GET_CACHE_CHANGE SN 15 -RTPS Operation GET_CACHE_CHANGE SN 16 -RTPS Operation GET_CACHE_CHANGE SN 17 -RTPS Operation REMOVE_CACHE_CHANGE SN 15 - SAMPLE MEMORY: 27(I1S16),9(I3S17)/18,0,36 - PAYLOAD MEMORY: 44(I1S16),22(I3S17)/11,0,33 - INSTANCE MEMORY: 8(I3),16(I1),0(I4)/- -DDS Operation WRITE [TS 18s, Instance 3, Aligned Payload] (ACCEPTED) - SAMPLE MEMORY: 27(I1S16),9(I3S17),18(I3S18)/0,36 - PAYLOAD MEMORY: 44(I1S16),22(I3S17),11(I3S18)/0,33 - INSTANCE MEMORY: 8(I3),16(I1),0(I4)/- -DDS Operation WRITE [TS 19s, Instance 4, Aligned Payload] (ACCEPTED) - SAMPLE MEMORY: 27(I1S16),9(I3S17),18(I3S18),0(I4S19)/36 - PAYLOAD MEMORY: 44(I1S16),22(I3S17),11(I3S18),0(I4S19)/33 - INSTANCE MEMORY: 8(I3),16(I1),0(I4)/- -DDS Operation WRITE [TS 20s, Instance 2, Aligned Payload] (REJECTED: MAX_SAMPLES exceeded, MAX_INSTANCES exceeded) -RTPS Operation ACK_CACHE_CHANGE SN 16 -DDS Operation WRITE [TS 20s, Instance 2, Aligned Payload] (ACCEPTED) - SAMPLE MEMORY: 9(I3S17),18(I3S18),0(I4S19),36(I2S20)/27 - PAYLOAD MEMORY: 22(I3S17),11(I3S18),0(I4S19),33(I2S20)/44 - INSTANCE MEMORY: 16(I2),8(I3),0(I4)/- -RTPS Operation ACK_CACHE_CHANGE SN 17 -DDS Operation UNREGISTER_INSTANCE [TS 21s, Instance 4] (ACCEPTED) - SAMPLE MEMORY: 18(I3S18),0(I4S19),36(I2S20),27(I4S21)/9 - PAYLOAD MEMORY: 11(I3S18),0(I4S19),33(I2S20),44(I4S21)/22 - INSTANCE MEMORY: 16(I2),8(I3),0(I4)/- -RTPS Operation ACK_CACHE_CHANGE SN 19 -DDS Operation WRITE [TS 22s, Instance 1, Aligned Payload] (REJECTED: MAX_SAMPLES exceeded, MAX_INSTANCES exceeded) -RTPS Operation REMOVE_CACHE_CHANGE SN 19 - SAMPLE MEMORY: 18(I3S18),36(I2S20),27(I4S21)/9,0 - PAYLOAD MEMORY: 11(I3S18),33(I2S20),44(I4S21)/0,22 - INSTANCE MEMORY: 16(I2),8(I3),0(I4)/- -RTPS Operation REMOVE_CACHE_CHANGE SN 21 - SAMPLE MEMORY: 18(I3S18),36(I2S20)/9,0,27 - PAYLOAD MEMORY: 11(I3S18),33(I2S20)/44,0,22 - INSTANCE MEMORY: 16(I2),8(I3),0(I4)/- -DDS Operation UNREGISTER_INSTANCE [TS 22s, Instance 2] (ACCEPTED) - SAMPLE MEMORY: 18(I3S18),36(I2S20),9(I2S22)/0,27 - PAYLOAD MEMORY: 11(I3S18),33(I2S20),44(I2S22)/0,22 - INSTANCE MEMORY: 16(I2),8(I3),0(I4)/- -DDS Operation UNREGISTER_INSTANCE [TS 23s, Instance 3] (ACCEPTED) - SAMPLE MEMORY: 18(I3S18),36(I2S20),9(I2S22),0(I3S23)/27 - PAYLOAD MEMORY: 11(I3S18),33(I2S20),44(I2S22),0(I3S23)/22 - INSTANCE MEMORY: 16(I2),8(I3),0(I4)/- -DDS Operation WRITE [TS 24s, Instance 1, Aligned Payload] (REJECTED: MAX_SAMPLES exceeded, MAX_INSTANCES exceeded) -RTPS Operation ACK_CACHE_CHANGE SN 20 -DDS Operation WRITE [TS 24s, Instance 1, Aligned Payload] (ACCEPTED) - SAMPLE MEMORY: 18(I3S18),9(I2S22),0(I3S23),27(I1S24)/36 - PAYLOAD MEMORY: 11(I3S18),44(I2S22),0(I3S23),22(I1S24)/33 - INSTANCE MEMORY: 0(I1),16(I2),8(I3)/- -RTPS Operation ACK_CACHE_CHANGE SN 22 -RTPS Operation NACK_CACHE_CHANGE SN 22 -DDS Operation REGISTER_INSTANCE 4 (REJECTED: MAX_INSTANCES exceeded) -RTPS Operation ACK_CACHE_CHANGE SN 22 -DDS Operation REGISTER_INSTANCE 2 (ACCEPTED) -DDS Operation REGISTER_INSTANCE 4 (REJECTED: MAX_INSTANCES exceeded) -RTPS Operation ACK_CACHE_CHANGE SN 18 -RTPS Operation ACK_CACHE_CHANGE SN 23 -DDS Operation WRITE [TS 25s, Instance 3, Aligned Payload] (ACCEPTED) - SAMPLE MEMORY: 9(I2S22),0(I3S23),27(I1S24),36(I3S25)/18 - PAYLOAD MEMORY: 44(I2S22),0(I3S23),22(I1S24),33(I3S25)/11 - INSTANCE MEMORY: 0(I1),16(I2),8(I3)/- -DDS Operation REGISTER_INSTANCE 4 (REJECTED: MAX_INSTANCES exceeded) -DDS Operation UNREGISTER_INSTANCE [TS 26s, Instance 4] (REJECTED: Instance not Registered) -RTPS Operation NACK_CACHE_CHANGE SN 22 -RTPS Operation NACK_CACHE_CHANGE SN 23 -DDS Operation UNREGISTER_INSTANCE [TS 26s, Instance 3] (REJECTED: MAX_SAMPLES_PER_INSTANCE exceeded, MAX_SAMPLES exceeded) -RTPS Operation ACK_CACHE_CHANGE SN 22 -DDS Operation UNREGISTER_INSTANCE [TS 26s, Instance 3] (REJECTED: MAX_SAMPLES_PER_INSTANCE exceeded, MAX_SAMPLES exceeded) -RTPS Operation ACK_CACHE_CHANGE SN 23 -DDS Operation UNREGISTER_INSTANCE [TS 26s, Instance 3] (ACCEPTED) - SAMPLE MEMORY: 9(I2S22),27(I1S24),36(I3S25),18(I3S26)/0 - PAYLOAD MEMORY: 44(I2S22),22(I1S24),33(I3S25),11(I3S26)/0 - INSTANCE MEMORY: 0(I1),16(I2),8(I3)/- -RTPS Operation ACK_CACHE_CHANGE SN 25 -DDS Operation DISPOSE [TS 27s, Instance 3] (ACCEPTED) - SAMPLE MEMORY: 9(I2S22),27(I1S24),18(I3S26),0(I3S27)/36 - PAYLOAD MEMORY: 44(I2S22),22(I1S24),11(I3S26),0(I3S27)/33 - INSTANCE MEMORY: 0(I1),16(I2),8(I3)/- -RTPS Operation ACK_CACHE_CHANGE SN 26 -RTPS Operation ACK_CACHE_CHANGE SN 27 -DDS Operation REGISTER_INSTANCE 4 (ACCEPTED) - SAMPLE MEMORY: 9(I2S22),27(I1S24)/36,18,0 - PAYLOAD MEMORY: 44(I2S22),22(I1S24)/0,11,33 - INSTANCE MEMORY: 8(I4),0(I1),16(I2)/- -RTPS Operation GET_MIN_SN (Expected SN 22) -RTPS Operation GET_MAX_SN (Expected SN 24) -RTPS Operation GET_CACHE_CHANGE SN 22 -RTPS Operation GET_CACHE_CHANGE SN 24 -RTPS Operation NACK_CACHE_CHANGE SN 22 -RTPS Operation NACK_CACHE_CHANGE SN 24 -DDS Operation WRITE [TS 28s, Instance 4, Aligned Payload] (ACCEPTED) - SAMPLE MEMORY: 9(I2S22),27(I1S24),36(I4S28)/18,0 - PAYLOAD MEMORY: 44(I2S22),22(I1S24),0(I4S28)/11,33 - INSTANCE MEMORY: 8(I4),0(I1),16(I2)/- -DDS Operation WRITE [TS 29s, Instance 2, Aligned Payload] (ACCEPTED) - SAMPLE MEMORY: 9(I2S22),27(I1S24),36(I4S28),18(I2S29)/0 - PAYLOAD MEMORY: 44(I2S22),22(I1S24),0(I4S28),11(I2S29)/33 - INSTANCE MEMORY: 8(I4),0(I1),16(I2)/- -RTPS Operation ACK_CACHE_CHANGE SN 24 -RTPS Operation ACK_CACHE_CHANGE SN 28 -DDS Operation WRITE [TS 30s, Instance 1, Aligned Payload] (ACCEPTED) - SAMPLE MEMORY: 9(I2S22),36(I4S28),18(I2S29),0(I1S30)/27 - PAYLOAD MEMORY: 44(I2S22),0(I4S28),11(I2S29),33(I1S30)/22 - INSTANCE MEMORY: 8(I4),0(I1),16(I2)/- -RTPS Operation REMOVE_CACHE_CHANGE SN 28 - SAMPLE MEMORY: 9(I2S22),18(I2S29),0(I1S30)/27,36 - PAYLOAD MEMORY: 44(I2S22),11(I2S29),33(I1S30)/0,22 - INSTANCE MEMORY: 8(I4),0(I1),16(I2)/- -RTPS Operation ACK_CACHE_CHANGE SN 22 -RTPS Operation ACK_CACHE_CHANGE SN 29 -DDS Operation WRITE [TS 31s, Instance 2, Aligned Payload] (ACCEPTED) - SAMPLE MEMORY: 18(I2S29),0(I1S30),27(I2S31)/36,9 - PAYLOAD MEMORY: 11(I2S29),33(I1S30),0(I2S31)/44,22 - INSTANCE MEMORY: 8(I4),0(I1),16(I2)/- -RTPS Operation GET_MIN_SN (Expected SN 29) -RTPS Operation GET_MAX_SN (Expected SN 31) -RTPS Operation GET_CACHE_CHANGE SN 29 -RTPS Operation GET_CACHE_CHANGE SN 30 -RTPS Operation GET_CACHE_CHANGE SN 31 -DDS Operation LOOKUP_INSTANCE [Instance 1] -DDS Operation LOOKUP_INSTANCE [Unknown Instance] \ No newline at end of file diff --git a/src/Tests/Level_0/L0_dds_writer_test1_aik.vhd b/src/Tests/Level_0/L0_dds_writer_test1_aik.vhd deleted file mode 100644 index 524f325..0000000 --- a/src/Tests/Level_0/L0_dds_writer_test1_aik.vhd +++ /dev/null @@ -1,2096 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library osvvm; -- Utility Library -context osvvm.OsvvmContext; - -use work.rtps_package.all; -use work.user_config.all; -use work.rtps_config_package.all; -use work.rtps_test_package.all; - -entity L0_dds_writer_test1_aik is -end entity; - --- This testbench tests the General Operation of the DDS Writer. It tests the correctness of the RTPS --- GET_MIN_SN, GET_MAX_SN, GET_CACHE_CHANGE, REMOVE_CACHE_CHANGE, ACK_CACHE_CHANGE, and NACK_CACHE_CHANGE Operations and the --- DDS REGISTER_INSTANCE, UNREGISTER_INSTANCE, WRITE, DISPOSE, and LOOKUP_INSTANCE Operations. --- More specifically the testbench covers following tests: --- TEST: GET_MIN_SN/GET_MAX_SN ON EMPTY --- TEST: GET_MIN_SN/GET_MAX_SN ON 1 SAMPLE --- TEST: GET_MIN_SN/GET_MAX_SN ON >1 SAMPLE --- TEST: ADD SAMPLE WITH KEY_HASH [UNKNOWN INSTANCE] --- TEST: ADD SAMPLE WITH KEY_HASH [KNOWN INSTANCE] --- TEST: ADD SAMPLE WITH HANDLE_NIL [UNKNOWN INSTANCE] --- TEST: ADD SAMPLE WITH HANDLE_NIL [KNOWN INSTANCE] --- TEST: NORMAL WRITE --- TEST: WRITE ON PAYLOAD MEMORY FULL [WITHOUT ACKed SAMPLES] --- TEST: WRITE ON PAYLOAD MEMORY FULL [WITH ACKed SAMPLES] --- TEST: WRITE ON DISPOSED INSTANCE --- TEST: WRITE ON UNREGISTERED INSTANCE --- TEST: WRITE ALIGNED PAYLOAD --- TEST: WRITE UNALIGNED PAYLOAD [>1 SLOT] --- TEST: WRITE UNALIGNED PAYLOAD [<1 SLOT] --- TEST: NORMAL REGISTER --- TEST: REGISTER INSTANCE [KNOWN INSTANCE] --- TEST: REGISTER INSTANCE ON MAX_INSTANCES [UNKNOWN INSTANCE, WITHOUT STALE INSTANCE] --- TEST: REGISTER INSTANCE ON MAX_INSTANCES [UNKNOWN INSTANCE, WITH STALE INSTANCE] --- TEST: REGISTER ON UNREGISTERED INSTANCE --- TEST: NORMAL DISPOSE --- TEST: DISPOSE ON PAYLOAD MEMORY FULL [WITHOUT ACKed SAMPLES] --- TEST: DISPOSE ON PAYLOAD MEMORY FULL [WITH ACKed SAMPLES] --- TEST: DISPOSE ON UNREGISTERED INSTANCE --- TEST: GET_CACHE_CHANGE [UNKNOWN SN] --- TEST: GET_CACHE_CHANGE [KNOWN SN, ALIGNED PAYLOAD] --- TEST: GET_CACHE_CHANGE [KNOWN SN, UNALIGNED PAYLOAD, >1 SLOT] --- TEST: GET_CACHE_CHANGE [KNOWN SN, UNALIGNED PAYLOAD, <1 SLOT] --- TEST: NORMAL ACK_CACHE_CHANGE --- TEST: ACK_CACHE_CHANGE [ALREADY ACKed SN] --- TEST: NORMAL NACK_CACHE_CHANGE --- TEST: REMOVE_CACHE_CHANGE [UNKNOWN SN] --- TEST: REMOVE_CACHE_CHANGE [KNOWN SN] --- TEST: NORMAL UNREGISTER --- TEST: UNREGISTER INSTANCE ON PAYLOAD MEMORY FULL [WITHOUT ACKed SAMPLES] --- TEST: UNREGISTER INSTANCE ON PAYLOAD MEMORY FULL [WITH ACKed SAMPLES] --- TEST: UNREGISTER ON DISPOSED INSTANCE --- TEST: UNREGISTER UNKNOWN INSTANCE --- TEST: REMOVE STALE INSTANCE WITH 0 SAMPLES --- TEST: REMOVE STALE INSTANCE WITH 1 SAMPLES --- TEST: REMOVE STALE INSTANCE WITH >1 SAMPLES --- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKNOWN INSTANCE, WITH STALE INSTANCE] --- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKNOWN INSTANCE, WITHOUT STALE INSTANCES] --- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKNOWN INSTANCE, WITH FULLY ACKed INSTANCE, WITHOUT STALE INSTANCE] --- TEST: ADD SAMPLE ON MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE, WITHOUT ACKed SAMPLES] --- TEST: ADD SAMPLE ON MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE, WITH ACKed SAMPLES, WITHOUT ACKed INSTANCE SAMPLES] --- TEST: ADD SAMPLE ON MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE, WITH ACKed INSTANCE SAMPLE] --- TEST: ADD SAMPLE ON MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE, WITH ACKed INSTANCE SAMPLES(>1)] --- TEST: ADD SAMPLE ON MAX_SAMPLES [KNOWN INSTANCE,WITHOUT ACKed SAMPLES] --- TEST: ADD SAMPLE ON MAX_SAMPLES [KNOWN INSTANCE,WITH ACKed SAMPLE] --- TEST: ADD SAMPLE ON MAX_SAMPLES [KNOWN INSTANCE,WITH ACKed SAMPLES (>1)] --- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE,WITHOUT ACKed SAMPLES] --- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE,WITH ACKed SAMPLES, WITHOUT ACKed INSTANCE SAMPLES] --- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE,WITH ACKed INSTANCE SAMPLES] --- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE,WITH STALE INSTANCE, WITHOUT ACKed SAMPLE] --- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE,WITHOUT STALE INSTANCES,WITHOUT ACKed SAMPLES] --- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE,WITHOUT STALE INSTANCE, WITH ACKed SAMPLE] --- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE,WITH STALE INSTANCE (>0 SAMPLES)] --- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE,WITH STALE INSTANCE, WITH ACKed SAMPLE] --- TEST: ADD SAMPLE ON PAYLOAD FULL & MAX_INSTANCES [UNKNOWN INSTANCE,WITH ACKed SAMPLES,WITH STALE INSTANCE (>= 1 SAMPLE)] (Induce Double Remove) --- TEST: ADD SAMPLE BIGGER THAN AVAILABLE MEMORY SPACE [WITH ACKed SAMPLES] --- TEST: INSTANCE LOOKUP [KNOWN INSTANCE] --- TEST: INSTANCE LOOKUP [UNKNOWN INSTANCE] - -architecture testbench of L0_dds_writer_test1_aik is - - -- *CONSTANT DECLARATION* - constant MAX_REMOTE_ENDPOINTS : natural := 3; - - -- *TYPE DECLARATION* - type DDS_STAGE_TYPE is (IDLE, START, PUSH, DONE); - type RTPS_STAGE_TYPE is (IDLE, START, DONE, CHECK); - - -- *SIGNAL DECLARATION* - signal clk : std_logic := '0'; - signal reset : std_logic := '1'; - signal check_time : TIME_TYPE := TIME_ZERO; - signal start_rtps, start_dds, ack_rtps, ack_dds, done_rtps, done_dds : std_logic := '0'; - signal opcode_rtps : HISTORY_CACHE_OPCODE_TYPE := NOP; - signal opcode_dds : DDS_WRITER_OPCODE_TYPE := NOP; - signal ret_rtps : HISTORY_CACHE_RESPONSE_TYPE := ERROR; - signal seq_nr_rtps, cc_seq_nr : SEQUENCENUMBER_TYPE := SEQUENCENUMBER_UNKNOWN; - signal ready_out_rtps, valid_out_rtps, last_word_out_rtps : std_logic := '0'; - signal ready_in_dds, ready_out_dds, valid_in_dds, valid_out_dds, last_word_in_dds, last_word_out_dds : std_logic := '0'; - signal data_out_rtps, data_in_dds, data_out_dds : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); - signal get_data_rtps, liveliness_assertion, data_available : std_logic := '0'; - signal cc_source_timestamp, source_ts_dds : TIME_TYPE := TIME_INVALID; - signal cc_kind : CACHE_CHANGE_KIND_TYPE := ALIVE; - signal cc_instance_handle, instance_handle_in_dds, instance_handle_out_dds : INSTANCE_HANDLE_TYPE := HANDLE_NIL; - signal max_wait_dds : DURATION_TYPE := DURATION_INFINITE; - signal return_code_dds : std_logic_vector(RETURN_CODE_WIDTH-1 downto 0) := (others => '0'); - signal status : std_logic_vector(STATUS_KIND_WIDTH-1 downto 0) := (others => '0'); - - signal dds_start, dds_done, rtps_start, rtps_done : std_logic := '0'; - signal dds_cnt, rtps_cnt : natural := 0; - signal dds_stage : DDS_STAGE_TYPE := IDLE; - signal rtps_stage : RTPS_STAGE_TYPE := IDLE; - shared variable dds : DDS_WRITER_TEST_TYPE := DEFAULT_DDS_WRITER_TEST; - shared variable rtps : RTPS_WRITER_TEST_TYPE := DEFAULT_RTPS_WRITER_TEST; - signal inst_id, kind_id, sn_id, ts_id, data_id, ret_id, ih_id : AlertLogIDType; - - -- *FUNCTION DECLARATION* - function extract_key_hash (payload : TEST_PACKET_TYPE) return INSTANCE_HANDLE_TYPE is - variable ret : INSTANCE_HANDLE_TYPE := HANDLE_NIL; - begin - for i in 0 to 3 loop - ret(i) := not payload.data(i); - end loop; - - return ret; - end function; - - function gen_sn(input : natural) return SEQUENCENUMBER_TYPE is - variable ret : SEQUENCENUMBER_TYPE; - begin - ret(0) := (others => '0'); - ret(1) := unsigned(int(input, WORD_WIDTH)); - return ret; - end function; - -begin - - -- Unit Under Test - uut : entity work.dds_writer(arch) - generic map( - HISTORY_QOS => KEEP_ALL_HISTORY_QOS, - DEADLINE_QOS => DURATION_INFINITE, - LIFESPAN_QOS => DURATION_INFINITE, - LEASE_DURATION => DURATION_INFINITE, - WITH_KEY => TRUE, - MAX_SAMPLES => std_logic_vector(to_unsigned(4,CDR_LONG_WIDTH)), - MAX_INSTANCES => std_logic_vector(to_unsigned(3,CDR_LONG_WIDTH)), - MAX_SAMPLES_PER_INSTANCE => std_logic_vector(to_unsigned(2,CDR_LONG_WIDTH)), - PAYLOAD_FRAME_SIZE => 11 - ) - port map ( - clk => clk, - reset => reset, - time => check_time, - start_rtps => start_rtps, - opcode_rtps => opcode_rtps, - ack_rtps => ack_rtps, - done_rtps => done_rtps, - ret_rtps => ret_rtps, - seq_nr_rtps => seq_nr_rtps, - get_data_rtps => get_data_rtps, - data_out_rtps => data_out_rtps, - valid_out_rtps => valid_out_rtps, - ready_out_rtps => ready_out_rtps, - last_word_out_rtps => last_word_out_rtps, - liveliness_assertion => liveliness_assertion, - data_available => data_available, - cc_instance_handle => cc_instance_handle, - cc_kind => cc_kind, - cc_source_timestamp => cc_source_timestamp, - cc_seq_nr => cc_seq_nr, - start_dds => start_dds, - ack_dds => ack_dds, - opcode_dds => opcode_dds, - instance_handle_in_dds => instance_handle_in_dds, - source_ts_dds => source_ts_dds, - max_wait_dds => max_wait_dds, - done_dds => done_dds, - return_code_dds => return_code_dds, - instance_handle_out_dds => instance_handle_out_dds, - ready_in_dds => ready_in_dds, - valid_in_dds => valid_in_dds, - data_in_dds => data_in_dds, - last_word_in_dds => last_word_in_dds, - ready_out_dds => ready_out_dds, - valid_out_dds => valid_out_dds, - data_out_dds => data_out_dds, - last_word_out_dds => last_word_out_dds, - status => status - ); - - stimulus_prc : process - variable RV : RandomPType; - variable kh1, kh2, kh3, kh4 : INSTANCE_HANDLE_TYPE := HANDLE_NIL; - variable cc1, cc2, cc3, cc4, cc : CACHE_CHANGE_TYPE := DEFAULT_CACHE_CHANGE; - - impure function gen_payload(key_hash : INSTANCE_HANDLE_TYPE; len : natural) return TEST_PACKET_TYPE is - variable ret : TEST_PACKET_TYPE := EMPTY_TEST_PACKET; - begin - assert (len >= 4) report "Payload length has to be at least 16 Bytes long" severity FAILURE; - - for i in 0 to len-1 loop - if (i < 4) then - -- NOTE: Beginning of payload is negated key to allow deterministic Key Hash generation from the kh_prc - ret.data(ret.length) := not key_hash(i); - else - ret.data(ret.length) := RV.RandSlv(WORD_WIDTH); - end if; - ret.length := ret.length + 1; - end loop; - ret.last(ret.length-1) := '1'; - - return ret; - end function; - - impure function gen_key_hash return KEY_HASH_TYPE is - variable ret : KEY_HASH_TYPE := KEY_HASH_NIL; - begin - for i in 0 to KEY_HASH_TYPE'length-1 loop - ret(i) := RV.RandSlv(WORD_WIDTH); - end loop; - return ret; - end function; - - procedure start_dds is - begin - dds_start <= '1'; - wait until rising_edge(clk); - dds_start <= '0'; - wait until rising_edge(clk); - end procedure; - - procedure start_rtps is - begin - rtps_start <= '1'; - wait until rising_edge(clk); - rtps_start <= '0'; - wait until rising_edge(clk); - end procedure; - - procedure wait_on_dds is - begin - if (dds_done /= '1') then - wait until dds_done = '1'; - end if; - end procedure; - - procedure wait_on_rtps is - begin - if (rtps_done /= '1') then - wait until rtps_done = '1'; - end if; - end procedure; - - procedure wait_on_completion is - begin - if (rtps_done /= '1' or dds_done /= '1') then - wait until rtps_done = '1' and dds_done = '1'; - end if; - end procedure; - - begin - - SetAlertLogName("L0_dds_writer_test1_aik - (KEEP ALL, Infinite Lifespan, Keyed) - General"); - SetAlertEnable(FAILURE, TRUE); - SetAlertEnable(ERROR, TRUE); - SetAlertEnable(WARNING, TRUE); - SetLogEnable(DEBUG, FALSE); - SetLogEnable(PASSED, FALSE); - SetLogEnable(INFO, TRUE); - RV.InitSeed(RV'instance_name); - inst_id <= GetAlertLogID("Instance", ALERTLOG_BASE_ID); - kind_id <= GetAlertLogID("Cache Change Kind", ALERTLOG_BASE_ID); - sn_id <= GetAlertLogID("SequenceNumber", ALERTLOG_BASE_ID); - ts_id <= GetAlertLogID("TimeStamp", ALERTLOG_BASE_ID); - ih_id <= GetAlertLogID("Instance Handle", ALERTLOG_BASE_ID); - data_id <= GetAlertLogID("Data Out", ALERTLOG_BASE_ID); - ret_id <= GetAlertLogID("Return Code", ALERTLOG_BASE_ID); - - -- Key Hashes - kh1 := gen_key_hash; - kh2 := gen_key_hash; - kh3 := gen_key_hash; - kh4 := gen_key_hash; - - - - Log("Initiating Test", INFO); - reset <= '1'; - wait until rising_edge(clk); - wait until rising_edge(clk); - reset <= '0'; - -- Stored CC: 0, 0, 0, 0 - - -- TEST: GET_MIN_SN/GET_MAX_SN ON EMPTY - - Log("RTPS Operation GET_MIN_SN (Expected SEQUENCENUMBER_UNKNOWN)", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_MIN_SN; - rtps.cc.seq_nr := SEQUENCENUMBER_UNKNOWN; - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_MAX_SN (Expected SEQUENCENUMBER_UNKNOWN)", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_MAX_SN; - rtps.cc.seq_nr := SEQUENCENUMBER_UNKNOWN; - start_rtps; - wait_on_rtps; - - -- TEST: WRITE ALIGNED PAYLOAD - -- TEST: NORMAL WRITE - -- TEST: ADD SAMPLE WITH KEY_HASH [UNKNOWN INSTANCE] - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh1; - cc.payload := gen_payload(kh1,10); - cc.seq_nr := gen_sn(1); - cc.src_timestamp := gen_duration(1,0); - - Log("DDS Operation WRITE [TS 1s, Instance 1] (REJECTED: Instance not Registered)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.ret_code := RETCODE_BAD_PARAMETER; - start_dds; - wait_on_dds; - - -- TEST: ADD SAMPLE WITH HANDLE_NIL [UNKNOWN INSTANCE] - - Log("DDS Operation WRITE [TS 1s, Instance 1, HANDLE_NIL] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.cc.instance:= HANDLE_NIL; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc1 := cc; - -- Stored CC: I1S1, 0, 0, 0 - - -- TEST: GET_MIN_SN/GET_MAX_SN ON 1 SAMPLE - - Log("RTPS Operation GET_MIN_SN (Expected SN 1)", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_MIN_SN; - rtps.cc.seq_nr := gen_sn(1); - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_MAX_SN (Expected SN 1)", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_MAX_SN; - rtps.cc.seq_nr := gen_sn(1); - start_rtps; - wait_on_rtps; - - -- TEST: WRITE UNALIGNED PAYLOAD [>1 SLOT] - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh2; - cc.payload := gen_payload(kh2,12); - cc.seq_nr := gen_sn(2); - cc.src_timestamp := gen_duration(2,0); - - Log("DDS Operation WRITE [TS 2s, Instance 2, Unaligned Payload (2 Slots)] (REJECTED: Instance not Registered)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.ret_code := RETCODE_BAD_PARAMETER; - start_dds; - wait_on_dds; - - -- TEST: NORMAL REGISTER - - Log("DDS Operation REGISTER_INSTANCE 2 (ACCEPTED)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := REGISTER_INSTANCE; - dds.cc := cc; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - - -- TEST: ADD SAMPLE WITH KEY_HASH [KNOWN INSTANCE] - - Log("DDS Operation WRITE [TS 2s, Instance 2, Unaligned Payload (2 Slots)] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc2 := cc; - -- Stored CC: I1S1, I2S2, 0, 0 - - -- TEST: ADD SAMPLE WITH HANDLE_NIL [KNOWN INSTANCE] - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh1; - cc.payload := gen_payload(kh1,15); - cc.seq_nr := gen_sn(3); - cc.src_timestamp := gen_duration(3,0); - - Log("DDS Operation WRITE [TS 3s, Instance 1, Unaligned Payload (2 Slots)] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.cc.instance:= HANDLE_NIL; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc3 := cc; - -- Stored CC: I1S1, I2S2, I1S3, 0 - - -- TEST: GET_CACHE_CHANGE [UNKNOWN SN] - - Log("RTPS Operation GET_CACHE_CHANGE SN 4 (Invalid)", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_CACHE_CHANGE; - rtps.cc.seq_nr := gen_sn(4); - rtps.ret_code := INVALID; - start_rtps; - wait_on_rtps; - - -- TEST: GET_CACHE_CHANGE [KNOWN SN, ALIGNED PAYLOAD] - - Log("RTPS Operation GET_CACHE_CHANGE SN 1", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_CACHE_CHANGE; - rtps.cc := cc1; - start_rtps; - wait_on_rtps; - - -- TEST: GET_CACHE_CHANGE [KNOWN SN, UNALIGNED PAYLOAD, >1 SLOT] - - Log("RTPS Operation GET_CACHE_CHANGE SN 2", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_CACHE_CHANGE; - rtps.cc := cc2; - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_CACHE_CHANGE SN 3", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_CACHE_CHANGE; - rtps.cc := cc3; - start_rtps; - wait_on_rtps; - - -- TEST: WRITE UNALIGNED PAYLOAD [<1 SLOT] - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh3; - cc.payload := gen_payload(kh3,8); - cc.seq_nr := gen_sn(4); - cc.src_timestamp := gen_duration(4,0); - - -- TEST: WRITE ON PAYLOAD MEMORY FULL [WITHOUT ACKed SAMPLES] - - Log("DDS Operation WRITE [TS 4s, Instance 3, HANDLE_NIL, Unaligned Payload (1 Slot)] (REJECTED: Payload Memory Full)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.cc.instance:= HANDLE_NIL; - dds.ret_code := RETCODE_OUT_OF_RESOURCES; - start_dds; - wait_on_dds; - -- Stored CC: I1S1, I2S2, I1S3, 0 - - -- TEST: REMOVE_CACHE_CHANGE [UNKNOWN SN] - - Log("RTPS Operation REMOVE_CACHE_CHANGE SN 5 (Invalid)", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := REMOVE_CACHE_CHANGE; - rtps.cc.seq_nr := gen_sn(5); - rtps.ret_code := INVALID; - start_rtps; - wait_on_rtps; - - -- TEST: REMOVE_CACHE_CHANGE [KNOWN SN] - - Log("RTPS Operation REMOVE_CACHE_CHANGE SN 2", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := REMOVE_CACHE_CHANGE; - rtps.cc := cc2; - start_rtps; - wait_on_rtps; - -- Stored CC: I1S1, 0, I1S3, 0 - - Log("DDS Operation WRITE [TS 4s, Instance 3, HANDLE_NIL, Unaligned Payload (1 Slot)] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.cc.instance:= HANDLE_NIL; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc2 := cc; - -- Stored CC: I1S1, I3S4, I1S3, 0 - - -- TEST: GET_CACHE_CHANGE [KNOWN SN, UNALIGNED PAYLOAD, <1 SLOT] - - Log("RTPS Operation GET_CACHE_CHANGE SN 4", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_CACHE_CHANGE; - rtps.cc := cc2; - start_rtps; - wait_on_rtps; - - -- TEST: REGISTER INSTANCE [KNOWN INSTANCE] - - Log("DDS Operation REGISTER_INSTANCE 3 (No Change)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := REGISTER_INSTANCE; - dds.cc := cc2; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - - -- TEST: NORMAL DISPOSE - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_DISPOSED; - cc.instance := kh1; - cc.payload := gen_payload(kh1,5); - cc.seq_nr := gen_sn(5); - cc.src_timestamp := gen_duration(5,0); - - -- TEST: ADD SAMPLE ON MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE, WITHOUT ACKed SAMPLES] - - Log("DDS Operation DISPOSE [TS 5s, Instance 1] (REJECTED: MAX_SAMPLES_PER_INSTANCE Exceeded)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := DISPOSE; - dds.cc := cc; - dds.ret_code := RETCODE_OUT_OF_RESOURCES; - start_dds; - wait_on_dds; - - -- TEST: NORMAL ACK_CACHE_CHANGE - - Log("RTPS Operation ACK_CACHE_CHANGE SN 4", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := ACK_CACHE_CHANGE; - rtps.cc := cc2; - start_rtps; - wait_on_rtps; - - -- TEST: ADD SAMPLE ON MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE, WITH ACKed SAMPLES, WITHOUT ACKed INSTANCE SAMPLES] - - Log("DDS Operation DISPOSE [TS 5s, Instance 1] (REJECTED: MAX_SAMPLES_PER_INSTANCE Exceeded)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := DISPOSE; - dds.cc := cc; - dds.ret_code := RETCODE_OUT_OF_RESOURCES; - start_dds; - wait_on_dds; - - Log("RTPS Operation ACK_CACHE_CHANGE SN 1", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := ACK_CACHE_CHANGE; - rtps.cc := cc1; - start_rtps; - wait_on_rtps; - - -- TEST: ADD SAMPLE ON MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE, WITH ACKed INSTANCE SAMPLE] - - Log("DDS Operation DISPOSE [TS 5s, Instance 1] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := DISPOSE; - dds.cc := cc; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc1 := cc; - -- Stored CC: I1S5, I3S4, I1S3, 0 - - -- VALIDATE STATE - -- TEST: GET_MIN_SN/GET_MAX_SN ON >1 SAMPLE - - Log("RTPS Operation GET_MIN_SN (Expected SN 3)", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_MIN_SN; - rtps.cc.seq_nr := gen_sn(3); - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_MAX_SN (Expected SN 5)", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_MAX_SN; - rtps.cc.seq_nr := gen_sn(5); - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_CACHE_CHANGE SN 5", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_CACHE_CHANGE; - rtps.cc := cc1; - start_rtps; - wait_on_rtps; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh4; - cc.payload := gen_payload(kh4,10); - cc.seq_nr := gen_sn(6); - cc.src_timestamp := gen_duration(6,0); - - -- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKNOWN INSTANCE, WITHOUT STALE INSTANCES] - - Log("DDS Operation WRITE [TS 6s, Instance 4, HANDLE_NIL, Aligned Payload] (REJECTED: MAX_INSTANCES exceeded)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.cc.instance:= HANDLE_NIL; - dds.ret_code := RETCODE_OUT_OF_RESOURCES; - start_dds; - wait_on_dds; - - Log("RTPS Operation ACK_CACHE_CHANGE SN 3", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := ACK_CACHE_CHANGE; - rtps.cc := cc3; - start_rtps; - wait_on_rtps; - - -- TEST: ACK_CACHE_CHANGE [ALREADY ACKed SN] - - Log("RTPS Operation ACK_CACHE_CHANGE SN 4", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := ACK_CACHE_CHANGE; - rtps.cc := cc2; - start_rtps; - wait_on_rtps; - - Log("RTPS Operation ACK_CACHE_CHANGE SN 5", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := ACK_CACHE_CHANGE; - rtps.cc := cc1; - start_rtps; - wait_on_rtps; - - -- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKNOWN INSTANCE, WITH FULLY ACKed INSTANCE, WITHOUT STALE INSTANCE] - - Log("DDS Operation WRITE [TS 6s, Instance 4, HANDLE_NIL, Aligned Payload] (REJECTED: MAX_INSTANCES exceeded)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.cc.instance:= HANDLE_NIL; - dds.ret_code := RETCODE_OUT_OF_RESOURCES; - start_dds; - wait_on_dds; - - -- TEST: NORMAL UNREGISTER - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_UNREGISTERED; - cc.instance := kh1; - cc.payload := gen_payload(kh1,5); - cc.seq_nr := gen_sn(6); - cc.src_timestamp := gen_duration(6,0); - - -- TEST: UNREGISTER ON DISPOSED INSTANCE - - Log("DDS Operation UNREGISTER_INSTANCE [TS 6s, Instance 1] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := UNREGISTER_INSTANCE; - dds.cc := cc; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc3 := cc; - -- Stored CC: I1S5, I3S4, I1S6, 0 - - -- VALIDATE STATE - - Log("RTPS Operation GET_MIN_SN (Expected SN 4)", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_MIN_SN; - rtps.cc.seq_nr := gen_sn(4); - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_MAX_SN (Expected SN 6)", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_MAX_SN; - rtps.cc.seq_nr := gen_sn(6); - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_CACHE_CHANGE SN 6", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_CACHE_CHANGE; - rtps.cc := cc3; - start_rtps; - wait_on_rtps; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh4; - cc.payload := gen_payload(kh4,10); - cc.seq_nr := gen_sn(7); - cc.src_timestamp := gen_duration(7,0); - - Log("DDS Operation WRITE [TS 7s, Instance 4, HANDLE_NIL, Aligned Payload] (REJECTED: MAX_INSTANCES exceeded)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.cc.instance:= HANDLE_NIL; - dds.ret_code := RETCODE_OUT_OF_RESOURCES; - start_dds; - wait_on_dds; - - Log("RTPS Operation ACK_CACHE_CHANGE SN 6", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := ACK_CACHE_CHANGE; - rtps.cc := cc3; - start_rtps; - wait_on_rtps; - - -- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKNOWN INSTANCE, WITH STALE INSTANCE] - -- TEST: REMOVE STALE INSTANCE WITH >1 SAMPLES - - Log("DDS Operation WRITE [TS 7s, Instance 4, HANDLE_NIL, Aligned Payload] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.cc.instance:= HANDLE_NIL; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc1 := cc; - -- Stored CC: I4S7, I3S4, 0, 0 - - Log("RTPS Operation GET_CACHE_CHANGE SN 5 (Invalid)", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_CACHE_CHANGE; - rtps.cc.seq_nr := gen_sn(5); - rtps.ret_code := INVALID; - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_CACHE_CHANGE SN 6 (Invalid)", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_CACHE_CHANGE; - rtps.cc.seq_nr := gen_sn(6); - rtps.ret_code := INVALID; - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_CACHE_CHANGE SN 7", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_CACHE_CHANGE; - rtps.cc := cc1; - start_rtps; - wait_on_rtps; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh2; - cc.payload := gen_payload(kh2,15); - cc.seq_nr := gen_sn(8); - cc.src_timestamp := gen_duration(8,0); - - Log("DDS Operation WRITE [TS 8s, Instance 2, Unaligned Payload (2 Slot)] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc3 := cc; - -- Stored CC: I4S7, I3S4, I2S8, 0 - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh1; - cc.payload := gen_payload(kh1,10); - cc.seq_nr := gen_sn(9); - cc.src_timestamp := gen_duration(9,0); - - Log("DDS Operation WRITE [TS 9s, Instance 1, Aligned Payload] (REJECTED: Instance not Registered)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.ret_code := RETCODE_BAD_PARAMETER; - start_dds; - wait_on_dds; - - -- TEST: REGISTER INSTANCE ON MAX_INSTANCES [UNKNOWN INSTANCE, WITHOUT STALE INSTANCE] - - Log("DDS Operation REGISTER_INSTANCE 1 (REJECTED: MAX_INSTANCES exceeded)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := REGISTER_INSTANCE; - dds.cc := cc; - dds.cc.instance:= HANDLE_NIL; - start_dds; - wait_on_dds; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := NOT_ALIVE_UNREGISTERED; - cc.instance := kh3; - cc.payload := gen_payload(kh3,5); - cc.seq_nr := gen_sn(9); - cc.src_timestamp := gen_duration(9,0); - - Log("DDS Operation UNREGISTER_INSTANCE [TS 9s, Instance 3] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := UNREGISTER_INSTANCE; - dds.cc := cc; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc4 := cc; - -- Stored CC: I4S7, I3S4, I2S8, I3S9 - - -- VALIDATE STATE - - Log("RTPS Operation GET_MIN_SN (Expected SN 4)", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_MIN_SN; - rtps.cc.seq_nr := gen_sn(4); - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_MAX_SN (Expected SN 9)", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_MAX_SN; - rtps.cc.seq_nr := gen_sn(9); - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_CACHE_CHANGE SN 8", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_CACHE_CHANGE; - rtps.cc := cc3; - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_CACHE_CHANGE SN 9", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_CACHE_CHANGE; - rtps.cc := cc4; - start_rtps; - wait_on_rtps; - - Log("RTPS Operation ACK_CACHE_CHANGE SN 9", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := ACK_CACHE_CHANGE; - rtps.cc := cc4; - start_rtps; - wait_on_rtps; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh1; - cc.payload := gen_payload(kh1,10); - cc.seq_nr := gen_sn(10); - cc.src_timestamp := gen_duration(10,0); - - -- TEST: REGISTER INSTANCE ON MAX_INSTANCES [UNKNOWN INSTANCE, WITH STALE INSTANCE] - - Log("DDS Operation REGISTER_INSTANCE 1 (ACCEPTED)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := REGISTER_INSTANCE; - dds.cc := cc; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - - Log("DDS Operation WRITE [TS 10s, Instance 1, Aligned Payload] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc2 := cc; - -- Stored CC: I4S7, I1S10, I2S8, 0 - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh4; - cc.payload := gen_payload(kh4,10); - cc.seq_nr := gen_sn(11); - cc.src_timestamp := gen_duration(11,0); - - Log("DDS Operation WRITE [TS 11s, Instance 1, Aligned Payload] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc4 := cc; - -- Stored CC: I4S7, I1S10, I2S8, I4S11 - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh2; - cc.payload := gen_payload(kh2,10); - cc.seq_nr := gen_sn(12); - cc.src_timestamp := gen_duration(12,0); - - Log("DDS Operation WRITE [TS 12s, Instance 2, Aligned Payload] (REJECTED: Payload Memory Full)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.ret_code := RETCODE_OUT_OF_RESOURCES; - start_dds; - wait_on_dds; - - Log("RTPS Operation ACK_CACHE_CHANGE SN 8", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := ACK_CACHE_CHANGE; - rtps.cc := cc3; - start_rtps; - wait_on_rtps; - - -- TEST: WRITE ON PAYLOAD MEMORY FULL [WITH ACKed SAMPLES] - - Log("DDS Operation WRITE [TS 12s, Instance 2, Aligned Payload] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc3 := cc; - -- Stored CC: I4S7, I1S10, I2S12, I4S11 - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh4; - cc.payload := gen_payload(kh4,10); - cc.seq_nr := gen_sn(13); - cc.src_timestamp := gen_duration(13,0); - - -- TEST: ADD SAMPLE ON MAX_SAMPLES [KNOWN INSTANCE,WITHOUT ACKed SAMPLES] - - Log("DDS Operation WRITE [TS 13s, Instance 4, Aligned Payload] (REJECTED: MAX_SAMPLES exceeded)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.ret_code := RETCODE_OUT_OF_RESOURCES; - start_dds; - wait_on_dds; - - Log("RTPS Operation ACK_CACHE_CHANGE SN 7", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := ACK_CACHE_CHANGE; - rtps.cc := cc1; - start_rtps; - wait_on_rtps; - - -- TEST: ADD SAMPLE ON MAX_SAMPLES [KNOWN INSTANCE,WITH ACKed SAMPLES] - - Log("DDS Operation WRITE [TS 13s, Instance 4, Aligned Payload] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc1 := cc; - -- Stored CC: I4S13, I1S10, I2S12, I4S11 - - -- VALIDATE STATE - - Log("RTPS Operation GET_MIN_SN (Expected SN 4)", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_MIN_SN; - rtps.cc.seq_nr := gen_sn(10); - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_MAX_SN (Expected SN 9)", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_MAX_SN; - rtps.cc.seq_nr := gen_sn(13); - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_CACHE_CHANGE SN 10", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_CACHE_CHANGE; - rtps.cc := cc2; - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_CACHE_CHANGE SN 11", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_CACHE_CHANGE; - rtps.cc := cc4; - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_CACHE_CHANGE SN 12", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_CACHE_CHANGE; - rtps.cc := cc3; - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_CACHE_CHANGE SN 13", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_CACHE_CHANGE; - rtps.cc := cc1; - start_rtps; - wait_on_rtps; - - Log("RTPS Operation ACK_CACHE_CHANGE SN 12", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := ACK_CACHE_CHANGE; - rtps.cc := cc3; - start_rtps; - wait_on_rtps; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := NOT_ALIVE_UNREGISTERED; - cc.instance := kh2; - cc.payload := gen_payload(kh2,5); - cc.seq_nr := gen_sn(14); - cc.src_timestamp := gen_duration(14,0); - - Log("DDS Operation UNREGISTER_INSTANCE [TS 14s, Instance 2] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := UNREGISTER_INSTANCE; - dds.cc := cc; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc3 := cc; - -- Stored CC: I4S13, I1S10, I2S14, I4S11 - - Log("RTPS Operation ACK_CACHE_CHANGE SN 11", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := ACK_CACHE_CHANGE; - rtps.cc := cc4; - start_rtps; - wait_on_rtps; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh4; - cc.payload := gen_payload(kh4,20); - cc.seq_nr := gen_sn(15); - cc.src_timestamp := gen_duration(15,0); - - -- TEST: ADD SAMPLE BIGGER THAN AVAILABLE MEMORY SPACE [WITH ACKed SAMPLES] - - Log("DDS Operation WRITE [TS 15s, Instance 4, Aligned Payload (2 Slots)] (REJECTED: Payload Memory Full)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.ret_code := RETCODE_OUT_OF_RESOURCES; - start_dds; - wait_on_dds; - - Log("RTPS Operation REMOVE_CACHE_CHANGE SN 11", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := REMOVE_CACHE_CHANGE; - rtps.cc := cc4; - start_rtps; - wait_on_rtps; - -- Stored CC: I4S13, I1S10, I2S14, 0 - - Log("DDS Operation WRITE [TS 15s, Instance 4, Aligned Payload (2 Slots)] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc4 := cc; - -- Stored CC: I4S13, I1S10, I2S14, I4S15 - - -- TEST: UNREGISTER INSTANCE ON PAYLOAD MEMORY FULL [WITHOUT ACKed SAMPLES] - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := NOT_ALIVE_UNREGISTERED; - cc.instance := kh1; - cc.payload := gen_payload(kh1,5); - cc.seq_nr := gen_sn(16); - cc.src_timestamp := gen_duration(16,0); - - Log("DDS Operation UNREGISTER_INSTANCE [TS 16s, Instance 1] (REJECTED: Payload memory Full, MAX_SAMPLES exceeded)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := UNREGISTER_INSTANCE; - dds.cc := cc; - dds.ret_code := RETCODE_OUT_OF_RESOURCES; - start_dds; - wait_on_dds; - - Log("RTPS Operation ACK_CACHE_CHANGE SN 10", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := ACK_CACHE_CHANGE; - rtps.cc := cc2; - start_rtps; - wait_on_rtps; - - -- TEST: UNREGISTER INSTANCE ON PAYLOAD MEMORY FULL [WITH ACKed SAMPLES] - - Log("DDS Operation UNREGISTER_INSTANCE [TS 16s, Instance 1] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := UNREGISTER_INSTANCE; - dds.cc := cc; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc2 := cc; - -- Stored CC: I4S13, I1S16, I2S14, I4S15 - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := NOT_ALIVE_DISPOSED; - cc.instance := kh3; - cc.payload := gen_payload(kh3,5); - cc.seq_nr := gen_sn(17); - cc.src_timestamp := gen_duration(17,0); - - -- TEST: DISPOSE ON PAYLOAD MEMORY FULL [WITHOUT ACKed SAMPLES] - - Log("DDS Operation DISPOSE [TS 17s, Instance 3] (REJECTED: Payload memory Full, MAX_SAMPLES exceeded)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := DISPOSE; - dds.cc := cc; - dds.cc.instance:= HANDLE_NIL; - dds.ret_code := RETCODE_OUT_OF_RESOURCES; - start_dds; - wait_on_dds; - - Log("RTPS Operation ACK_CACHE_CHANGE SN 13", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := ACK_CACHE_CHANGE; - rtps.cc := cc1; - start_rtps; - wait_on_rtps; - - Log("RTPS Operation ACK_CACHE_CHANGE SN 14", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := ACK_CACHE_CHANGE; - rtps.cc := cc3; - start_rtps; - wait_on_rtps; - - -- TEST: DISPOSE ON PAYLOAD MEMORY FULL [WITH ACKed SAMPLES] - -- TEST: ADD SAMPLE ON PAYLOAD FULL & MAX_INSTANCES [UNKNOWN INSTANCE,WITH ACKed SAMPLES,WITH STALE INSTANCE (>= 1 SAMPLE)] (Induce Double Remove) - -- TEST: REMOVE STALE INSTANCE WITH 1 SAMPLES - - Log("DDS Operation DISPOSE [TS 17s, Instance 3] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := DISPOSE; - dds.cc := cc; - dds.cc.instance:= HANDLE_NIL; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc1 := cc; - -- Stored CC: I3S17, I1S16, 0, I4S15 - - -- VALIDATE STATE - - Log("RTPS Operation GET_MIN_SN (Expected SN 15)", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_MIN_SN; - rtps.cc.seq_nr := gen_sn(15); - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_MAX_SN (Expected SN 17)", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_MAX_SN; - rtps.cc.seq_nr := gen_sn(17); - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_CACHE_CHANGE SN 15", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_CACHE_CHANGE; - rtps.cc := cc4; - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_CACHE_CHANGE SN 16", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_CACHE_CHANGE; - rtps.cc := cc2; - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_CACHE_CHANGE SN 17", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_CACHE_CHANGE; - rtps.cc := cc1; - start_rtps; - wait_on_rtps; - - Log("RTPS Operation REMOVE_CACHE_CHANGE SN 15", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := REMOVE_CACHE_CHANGE; - rtps.cc := cc4; - start_rtps; - wait_on_rtps; - -- Stored CC: I3S17, I1S16, 0, 0 - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh3; - cc.payload := gen_payload(kh3,10); - cc.seq_nr := gen_sn(18); - cc.src_timestamp := gen_duration(18,0); - - -- TEST: WRITE ON DISPOSED INSTANCE - - Log("DDS Operation WRITE [TS 18s, Instance 3, Aligned Payload] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc3 := cc; - -- Stored CC: I3S17, I1S16, I3S18, 0 - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh4; - cc.payload := gen_payload(kh4,10); - cc.seq_nr := gen_sn(19); - cc.src_timestamp := gen_duration(19,0); - - Log("DDS Operation WRITE [TS 19s, Instance 4, Aligned Payload] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc4 := cc; - -- Stored CC: I3S17, I1S16, I3S18, I4S19 - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh2; - cc.payload := gen_payload(kh2,10); - cc.seq_nr := gen_sn(20); - cc.src_timestamp := gen_duration(20,0); - - -- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE,WITHOUT STALE INSTANCES,WITHOUT ACKed SAMPLES] - - Log("DDS Operation WRITE [TS 20s, Instance 2, Aligned Payload] (REJECTED: MAX_SAMPLES exceeded, MAX_INSTANCES exceeded)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.cc.instance:= HANDLE_NIL; - dds.ret_code := RETCODE_OUT_OF_RESOURCES; - start_dds; - wait_on_dds; - - Log("RTPS Operation ACK_CACHE_CHANGE SN 16", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := ACK_CACHE_CHANGE; - rtps.cc := cc2; - start_rtps; - wait_on_rtps; - - -- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE,WITH STALE INSTANCE (>0 SAMPLES)] - - Log("DDS Operation WRITE [TS 20s, Instance 2, Aligned Payload] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.cc.instance:= HANDLE_NIL; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc2 := cc; - -- Stored CC: I3S17, I2S20, I3S18, I4S19 - - Log("RTPS Operation ACK_CACHE_CHANGE SN 17", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := ACK_CACHE_CHANGE; - rtps.cc := cc1; - start_rtps; - wait_on_rtps; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := NOT_ALIVE_UNREGISTERED; - cc.instance := kh4; - cc.payload := gen_payload(kh4,5); - cc.seq_nr := gen_sn(21); - cc.src_timestamp := gen_duration(21,0); - - Log("DDS Operation UNREGISTER_INSTANCE [TS 21s, Instance 4] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := UNREGISTER_INSTANCE; - dds.cc := cc; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc1 := cc; - -- Stored CC: I4S21, I2S20, I3S18, I4S19 - - Log("RTPS Operation ACK_CACHE_CHANGE SN 19", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := ACK_CACHE_CHANGE; - rtps.cc := cc4; - start_rtps; - wait_on_rtps; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh1; - cc.payload := gen_payload(kh1,10); - cc.seq_nr := gen_sn(22); - cc.src_timestamp := gen_duration(22,0); - - -- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE,WITHOUT STALE INSTANCE, WITH ACKed SAMPLE] - - Log("DDS Operation WRITE [TS 22s, Instance 1, Aligned Payload] (REJECTED: MAX_SAMPLES exceeded, MAX_INSTANCES exceeded)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.cc.instance:= HANDLE_NIL; - dds.ret_code := RETCODE_OUT_OF_RESOURCES; - start_dds; - wait_on_dds; - - Log("RTPS Operation REMOVE_CACHE_CHANGE SN 19", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := REMOVE_CACHE_CHANGE; - rtps.cc := cc4; - start_rtps; - wait_on_rtps; - -- Stored CC: I4S21, I2S20, I3S18, 0 - - Log("RTPS Operation REMOVE_CACHE_CHANGE SN 21", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := REMOVE_CACHE_CHANGE; - rtps.cc := cc1; - start_rtps; - wait_on_rtps; - -- Stored CC: 0, I2S20, I3S18, 0 - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := NOT_ALIVE_UNREGISTERED; - cc.instance := kh2; - cc.payload := gen_payload(kh2,5); - cc.seq_nr := gen_sn(22); - cc.src_timestamp := gen_duration(22,0); - - Log("DDS Operation UNREGISTER_INSTANCE [TS 22s, Instance 2] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := UNREGISTER_INSTANCE; - dds.cc := cc; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc1 := cc; - -- Stored CC: I2S22, I2S20, I3S18, 0 - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := NOT_ALIVE_UNREGISTERED; - cc.instance := kh3; - cc.payload := gen_payload(kh3,5); - cc.seq_nr := gen_sn(23); - cc.src_timestamp := gen_duration(23,0); - - Log("DDS Operation UNREGISTER_INSTANCE [TS 23s, Instance 3] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := UNREGISTER_INSTANCE; - dds.cc := cc; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc4 := cc; - -- Stored CC: I2S22, I2S20, I3S18, I3S23 - - -- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE,WITH STALE INSTANCE, WITHOUT ACKed SAMPLE] - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh1; - cc.payload := gen_payload(kh1,10); - cc.seq_nr := gen_sn(24); - cc.src_timestamp := gen_duration(24,0); - - Log("DDS Operation WRITE [TS 24s, Instance 1, Aligned Payload] (REJECTED: MAX_SAMPLES exceeded, MAX_INSTANCES exceeded)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.cc.instance:= HANDLE_NIL; - dds.ret_code := RETCODE_OUT_OF_RESOURCES; - start_dds; - wait_on_dds; - - Log("RTPS Operation ACK_CACHE_CHANGE SN 20", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := ACK_CACHE_CHANGE; - rtps.cc := cc2; - start_rtps; - wait_on_rtps; - - -- TEST: REMOVE STALE INSTANCE WITH 0 SAMPLES - -- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE,WITH STALE INSTANCE, WITH ACKed SAMPLE] - - Log("DDS Operation WRITE [TS 24s, Instance 1, Aligned Payload] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.cc.instance:= HANDLE_NIL; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc2 := cc; - -- Stored CC: I2S22, I1S24, I3S18, I3S23 - - Log("RTPS Operation ACK_CACHE_CHANGE SN 22", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := ACK_CACHE_CHANGE; - rtps.cc := cc1; - start_rtps; - wait_on_rtps; - - -- TEST: NORMAL NACK_CACHE_CHANGE - - Log("RTPS Operation NACK_CACHE_CHANGE SN 22", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := NACK_CACHE_CHANGE; - rtps.cc := cc1; - start_rtps; - wait_on_rtps; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh4; - cc.payload := gen_payload(kh4,10); - cc.seq_nr := gen_sn(25); - cc.src_timestamp := gen_duration(25,0); - - Log("DDS Operation REGISTER_INSTANCE 4 (REJECTED: MAX_INSTANCES exceeded)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := REGISTER_INSTANCE; - dds.cc := cc; - dds.cc.instance:= HANDLE_NIL; - start_dds; - wait_on_dds; - - Log("RTPS Operation ACK_CACHE_CHANGE SN 22", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := ACK_CACHE_CHANGE; - rtps.cc := cc1; - start_rtps; - wait_on_rtps; - - -- TEST: REGISTER ON UNREGISTERED INSTANCE - - Log("DDS Operation REGISTER_INSTANCE 2 (ACCEPTED)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := REGISTER_INSTANCE; - dds.cc := cc1; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - - Log("DDS Operation REGISTER_INSTANCE 4 (REJECTED: MAX_INSTANCES exceeded)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := REGISTER_INSTANCE; - dds.cc := cc; - dds.cc.instance:= HANDLE_NIL; - start_dds; - wait_on_dds; - - Log("RTPS Operation ACK_CACHE_CHANGE SN 18", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := ACK_CACHE_CHANGE; - rtps.cc := cc3; - start_rtps; - wait_on_rtps; - - Log("RTPS Operation ACK_CACHE_CHANGE SN 23", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := ACK_CACHE_CHANGE; - rtps.cc := cc4; - start_rtps; - wait_on_rtps; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh3; - cc.payload := gen_payload(kh3,10); - cc.seq_nr := gen_sn(25); - cc.src_timestamp := gen_duration(25,0); - - -- TEST: WRITE ON UNREGISTERED INSTANCE - - Log("DDS Operation WRITE [TS 25s, Instance 3, Aligned Payload] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.cc.instance:= HANDLE_NIL; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc3 := cc; - -- Stored CC: I2S22, I1S24, I3S25, I3S23 - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh4; - cc.payload := gen_payload(kh4,10); - cc.seq_nr := gen_sn(26); - cc.src_timestamp := gen_duration(26,0); - - Log("DDS Operation REGISTER_INSTANCE 4 (REJECTED: MAX_INSTANCES exceeded)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := REGISTER_INSTANCE; - dds.cc := cc; - dds.cc.instance:= HANDLE_NIL; - start_dds; - wait_on_dds; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := NOT_ALIVE_UNREGISTERED; - cc.instance := kh4; - cc.payload := gen_payload(kh4,5); - cc.seq_nr := gen_sn(26); - cc.src_timestamp := gen_duration(26,0); - - -- TEST: UNREGISTER UNKNOWN INSTANCE - - Log("DDS Operation UNREGISTER_INSTANCE [TS 26s, HANDLE_NIL, Instance 4] (IGNORED)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := UNREGISTER_INSTANCE; - dds.cc := cc; - dds.cc.instance:= HANDLE_NIL; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - - Log("RTPS Operation NACK_CACHE_CHANGE SN 22", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := NACK_CACHE_CHANGE; - rtps.cc := cc1; - start_rtps; - wait_on_rtps; - - Log("RTPS Operation NACK_CACHE_CHANGE SN 23", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := NACK_CACHE_CHANGE; - rtps.cc := cc4; - start_rtps; - wait_on_rtps; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_UNREGISTERED; - cc.instance := kh3; - cc.payload := gen_payload(kh3,5); - cc.seq_nr := gen_sn(26); - cc.src_timestamp := gen_duration(26,0); - - -- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE,WITHOUT ACKed SAMPLES] - - Log("DDS Operation UNREGISTER_INSTANCE [TS 26s, Instance 3] (REJECTED: MAX_SAMPLES_PER_INSTANCE exceeded, MAX_SAMPLES exceeded)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := UNREGISTER_INSTANCE; - dds.cc := cc; - dds.ret_code := RETCODE_OUT_OF_RESOURCES; - start_dds; - wait_on_dds; - - Log("RTPS Operation ACK_CACHE_CHANGE SN 22", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := ACK_CACHE_CHANGE; - rtps.cc := cc1; - start_rtps; - wait_on_rtps; - - -- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE,WITH ACKed SAMPLES, WITHOUT ACKed INSTANCE SAMPLES] - - Log("DDS Operation UNREGISTER_INSTANCE [TS 26s, Instance 3] (REJECTED: MAX_SAMPLES_PER_INSTANCE exceeded, MAX_SAMPLES exceeded)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := UNREGISTER_INSTANCE; - dds.cc := cc; - dds.ret_code := RETCODE_OUT_OF_RESOURCES; - start_dds; - wait_on_dds; - - Log("RTPS Operation ACK_CACHE_CHANGE SN 23", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := ACK_CACHE_CHANGE; - rtps.cc := cc4; - start_rtps; - wait_on_rtps; - - -- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE,WITH ACKed INSTANCE SAMPLES] - - Log("DDS Operation UNREGISTER_INSTANCE [TS 26s, Instance 3] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := UNREGISTER_INSTANCE; - dds.cc := cc; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc4 := cc; - -- Stored CC: I2S22, I1S24, I3S25, I3S26 - - Log("RTPS Operation ACK_CACHE_CHANGE SN 25", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := ACK_CACHE_CHANGE; - rtps.cc := cc3; - start_rtps; - wait_on_rtps; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_DISPOSED; - cc.instance := kh3; - cc.payload := gen_payload(kh3,5); - cc.seq_nr := gen_sn(27); - cc.src_timestamp := gen_duration(27,0); - - -- TEST: DISPOSE ON UNREGISTERED INSTANCE - - Log("DDS Operation DISPOSE [TS 27s, Instance 3] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := DISPOSE; - dds.cc := cc; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc3 := cc; - -- Stored CC: I2S22, I1S24, I3S27, I3S26 - - Log("RTPS Operation ACK_CACHE_CHANGE SN 26", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := ACK_CACHE_CHANGE; - rtps.cc := cc4; - start_rtps; - wait_on_rtps; - - Log("RTPS Operation ACK_CACHE_CHANGE SN 27", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := ACK_CACHE_CHANGE; - rtps.cc := cc3; - start_rtps; - wait_on_rtps; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh4; - cc.payload := gen_payload(kh4,10); - cc.seq_nr := gen_sn(28); - cc.src_timestamp := gen_duration(28,0); - - Log("DDS Operation REGISTER_INSTANCE 4 (ACCEPTED)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := REGISTER_INSTANCE; - dds.cc := cc; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - -- Stored CC: I2S22, I1S24, 0, 0 - - -- VALIDATE STATE - - Log("RTPS Operation GET_MIN_SN (Expected SN 22)", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_MIN_SN; - rtps.cc.seq_nr := gen_sn(22); - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_MAX_SN (Expected SN 24)", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_MAX_SN; - rtps.cc.seq_nr := gen_sn(24); - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_CACHE_CHANGE SN 22", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_CACHE_CHANGE; - rtps.cc := cc1; - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_CACHE_CHANGE SN 24", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_CACHE_CHANGE; - rtps.cc := cc2; - start_rtps; - wait_on_rtps; - - Log("RTPS Operation NACK_CACHE_CHANGE SN 22", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := NACK_CACHE_CHANGE; - rtps.cc := cc1; - start_rtps; - wait_on_rtps; - - Log("RTPS Operation NACK_CACHE_CHANGE SN 24", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := NACK_CACHE_CHANGE; - rtps.cc := cc2; - start_rtps; - wait_on_rtps; - - Log("DDS Operation WRITE [TS 28s, Instance 4, Aligned Payload] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc3 := cc; - -- Stored CC: I2S22, I1S24, I4S28, 0 - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh2; - cc.payload := gen_payload(kh2,10); - cc.seq_nr := gen_sn(29); - cc.src_timestamp := gen_duration(29,0); - - Log("DDS Operation WRITE [TS 29s, Instance 2, Aligned Payload] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc4 := cc; - -- Stored CC: I2S22, I1S24, I4S28, I2S29 - - Log("RTPS Operation ACK_CACHE_CHANGE SN 24", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := ACK_CACHE_CHANGE; - rtps.cc := cc2; - start_rtps; - wait_on_rtps; - - Log("RTPS Operation ACK_CACHE_CHANGE SN 28", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := ACK_CACHE_CHANGE; - rtps.cc := cc3; - start_rtps; - wait_on_rtps; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh1; - cc.payload := gen_payload(kh1,10); - cc.seq_nr := gen_sn(30); - cc.src_timestamp := gen_duration(30,0); - - -- TEST: ADD SAMPLE ON MAX_SAMPLES [KNOWN INSTANCE,WITH ACKed SAMPLES (>1)] - - Log("DDS Operation WRITE [TS 30s, Instance 1, Aligned Payload] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc2 := cc; - -- Stored CC: I2S22, I1S30, I4S28, I2S29 - - Log("RTPS Operation REMOVE_CACHE_CHANGE SN 28", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := REMOVE_CACHE_CHANGE; - rtps.cc := cc3; - start_rtps; - wait_on_rtps; - -- Stored CC: I2S22, I1S30, 0, I2S29 - - Log("RTPS Operation ACK_CACHE_CHANGE SN 22", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := ACK_CACHE_CHANGE; - rtps.cc := cc1; - start_rtps; - wait_on_rtps; - - Log("RTPS Operation ACK_CACHE_CHANGE SN 29", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := ACK_CACHE_CHANGE; - rtps.cc := cc4; - start_rtps; - wait_on_rtps; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh2; - cc.payload := gen_payload(kh2,10); - cc.seq_nr := gen_sn(31); - cc.src_timestamp := gen_duration(31,0); - - -- TEST: ADD SAMPLE ON MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE, WITH ACKed INSTANCE SAMPLES(>1)] - - Log("DDS Operation WRITE [TS 31s, Instance 2, Aligned Payload] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc1 := cc; - -- Stored CC: I2S31, I1S30, 0, I2S29 - - -- VALIDATE STATE - - Log("RTPS Operation GET_MIN_SN (Expected SN 29)", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_MIN_SN; - rtps.cc.seq_nr := gen_sn(29); - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_MAX_SN (Expected SN 31)", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_MAX_SN; - rtps.cc.seq_nr := gen_sn(31); - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_CACHE_CHANGE SN 29", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_CACHE_CHANGE; - rtps.cc := cc4; - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_CACHE_CHANGE SN 30", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_CACHE_CHANGE; - rtps.cc := cc2; - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_CACHE_CHANGE SN 31", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_CACHE_CHANGE; - rtps.cc := cc1; - start_rtps; - wait_on_rtps; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh1; - cc.payload := gen_payload(kh1,10); - cc.seq_nr := gen_sn(1); - cc.src_timestamp := gen_duration(1,0); - - -- TEST: INSTANCE LOOKUP [KNOWN INSTANCE] - - Log("DDS Operation LOOKUP_INSTANCE [Instance 1]", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := LOOKUP_INSTANCE; - dds.cc := cc; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh3; - cc.payload := gen_payload(kh3,10); - cc.seq_nr := gen_sn(1); - cc.src_timestamp := gen_duration(1,0); - - -- TEST: INSTANCE LOOKUP [UNKNOWN INSTANCE] - - Log("DDS Operation LOOKUP_INSTANCE [Unknown Instance]", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := LOOKUP_INSTANCE; - dds.cc := cc; - dds.cc.instance:= HANDLE_NIL; - start_dds; - wait_on_dds; - - wait_on_completion; - TranscriptOpen(RESULTS_FILE, APPEND_MODE); - SetTranscriptMirror; - ReportAlerts; - TranscriptClose; - std.env.stop; - wait; - end process; - - clock_prc : process - begin - clk <= '0'; - wait for 25 ns; - clk <= '1'; - wait for 25 ns; - end process; - - alert_prc : process(all) - begin - if rising_edge(clk) then - -- TODO - end if; - end process; - - dds_prc : process(all) - begin - if rising_edge(clk) then - dds_done <= '0'; - case (dds_stage) is - when IDLE => - if (dds_start = '1') then - dds_stage <= START; - else - dds_done <= '1'; - end if; - when START => - if (ack_dds = '1') then - dds_stage <= PUSH; - dds_cnt <= 0; - end if; - when PUSH => - if (ready_in_dds = '1') then - dds_cnt <= dds_cnt + 1; - if (dds_cnt = dds.cc.payload.length-1) then - -- DEFAULT - dds_stage <= DONE; - end if; - end if; - when DONE => - if (done_dds = '1') then - if (dds.opcode = REGISTER_INSTANCE or dds.opcode = LOOKUP_INSTANCE) then - AffirmIfEqual(ih_id, to_unsigned(instance_handle_out_dds), to_unsigned(dds.cc.instance)); - else - AffirmIfEqual(ret_id, return_code_dds, dds.ret_code); - end if; - dds_stage <= IDLE; - end if; - end case; - end if; - - -- DEFAULT - start_dds <= '0'; - opcode_dds <= NOP; - valid_in_dds <= '0'; - last_word_in_dds <= '0'; - data_in_dds <= (others => '0'); - instance_handle_in_dds <= HANDLE_NIL; - source_ts_dds <= TIME_INVALID; - ready_out_dds <= '0'; - - case (dds_stage) is - when START => - start_dds <= '1'; - opcode_dds <= dds.opcode; - instance_handle_in_dds <= dds.cc.instance; - source_ts_dds <= dds.cc.src_timestamp; - when PUSH => - valid_in_dds <= '1'; - data_in_dds <= dds.cc.payload.data(dds_cnt); - last_word_in_dds <= dds.cc.payload.last(dds_cnt); - when others => - null; - end case; - end process; - - rtps_prc : process(all) - begin - if rising_edge(clk) then - rtps_done <= '0'; - case (rtps_stage) is - when IDLE => - if (rtps_start = '1') then - rtps_stage <= START; - else - rtps_done <= '1'; - end if; - when START => - if (ack_rtps = '1') then - rtps_stage <= DONE; - end if; - when DONE => - if (done_rtps = '1') then - -- DEFAULT - rtps_stage <= IDLE; - - AffirmIfEqual(ret_id, HISTORY_CACHE_RESPONSE_TYPE'pos(ret_rtps), HISTORY_CACHE_RESPONSE_TYPE'pos(rtps.ret_code)); - case (rtps.opcode) is - when GET_CACHE_CHANGE => - if (rtps.ret_code = OK) then - AffirmIfEqual(inst_id, to_unsigned(cc_instance_handle), to_unsigned(rtps.cc.instance)); - AffirmIfEqual(kind_id, CACHE_CHANGE_KIND_TYPE'pos(cc_kind), CACHE_CHANGE_KIND_TYPE'pos(rtps.cc.kind)); - AffirmIfEqual(sn_id, to_unsigned(cc_seq_nr), to_unsigned(rtps.cc.seq_nr)); - AffirmIfEqual(ts_id, to_unsigned(cc_source_timestamp), to_unsigned(rtps.cc.src_timestamp)); - rtps_stage <= CHECK; - rtps_cnt <= 0; - end if; - when GET_MIN_SN => - AffirmIfEqual(sn_id, to_unsigned(cc_seq_nr), to_unsigned(rtps.cc.seq_nr)); - when GET_MAX_SN => - AffirmIfEqual(sn_id, to_unsigned(cc_seq_nr), to_unsigned(rtps.cc.seq_nr)); - when others => - null; - end case; - end if; - when CHECK => - if (valid_out_rtps = '1') then - AffirmIfEqual(data_id, last_word_out_rtps & data_out_rtps, rtps.cc.payload.last(rtps_cnt) & rtps.cc.payload.data(rtps_cnt)); - rtps_cnt <= rtps_cnt + 1; - if (rtps_cnt = rtps.cc.payload.length-1) then - rtps_stage <= IDLE; - end if; - end if; - end case; - end if; - - -- DEFAULT - start_rtps <= '0'; - opcode_rtps <= NOP; - seq_nr_rtps <= SEQUENCENUMBER_UNKNOWN; - get_data_rtps <= '0'; - ready_out_rtps <= '0'; - - case (rtps_stage) is - when START => - start_rtps <= '1'; - opcode_rtps <= rtps.opcode; - seq_nr_rtps <= rtps.cc.seq_nr; - when DONE => - if (done_rtps = '1') then - case (rtps.opcode) is - when GET_CACHE_CHANGE => - get_data_rtps <= '1'; - when others => - null; - end case; - end if; - when CHECK => - ready_out_rtps <= '1'; - when others => - null; - end case; - end process; - - watchdog : process - begin - wait for 1 ms; - Alert("Test timeout", FAILURE); - std.env.stop; - end process; - -end architecture; \ No newline at end of file diff --git a/src/Tests/Level_0/L0_dds_writer_test1_ain.txt b/src/Tests/Level_0/L0_dds_writer_test1_ain.txt deleted file mode 100644 index 00e05a4..0000000 --- a/src/Tests/Level_0/L0_dds_writer_test1_ain.txt +++ /dev/null @@ -1,69 +0,0 @@ - SAMPLE MEMORY: -/0,8,16,24,32 - PAYLOAD MEMORY: -/0,11,22,33,44 -RTPS Operation GET_MIN_SN (Expected SEQUENCENUMBER_UNKNOWN) -RTPS Operation GET_MAX_SN (Expected SEQUENCENUMBER_UNKNOWN) -DDS Operation WRITE [TS 1s, Aligned Payload] (ACCEPTED) - SAMPLE MEMORY: 0(S1)/8,16,24,32 - PAYLOAD MEMORY: 0(S1)/11,22,33,44 -DDS Operation WRITE [TS 2s, Unaligned Payload (2 Slots)] (ACCEPTED) - SAMPLE MEMORY: 0(S1),8(S2)/16,24,32 - PAYLOAD MEMORY: 0(S1),11(S2),22(S2)/33,44 -DDS Operation REGISTER_INSTANCE 2 (Illegal Operation) -DDS Operation DISPOSE [TS 3s] (ACCEPTED) - SAMPLE MEMORY: 0(S1),8(S2),16(S3)/24,32 - PAYLOAD MEMORY: 0(S1),11(S2),22(S2),33(S3)/44 -RTPS Operation GET_MIN_SN (Expected SN 1) -RTPS Operation GET_MAX_SN (Expected SN 3) -RTPS Operation GET_CACHE_CHANGE SN 4 (Invalid) -RTPS Operation GET_CACHE_CHANGE SN 1 -RTPS Operation GET_CACHE_CHANGE SN 2 -RTPS Operation GET_CACHE_CHANGE SN 3 -DDS Operation WRITE [TS 2s, Aligned Payload] (ACCEPTED) - SAMPLE MEMORY: 0(S1),8(S2),16(S3),24(S4)/32 - PAYLOAD MEMORY: 0(S1),11(S2),22(S2),33(S3),44(S4)/- -DDS Operation UNREGISTER_INSTANCE [TS 5s] (REJECTED: Payload Memory Full) -RTPS Operation ACK_CACHE_CHANGE SN 1 -DDS Operation UNREGISTER_INSTANCE [TS 5s] (ACCEPTED) - SAMPLE MEMORY: 8(S2),16(S3),24(S4),32(S5)/0 - PAYLOAD MEMORY: 11(S2),22(S2),33(S3),44(S4),0(S5)/- -DDS Operation WRITE [TS 6s, Aligned Payload] (REJECTED: Payload Memory Full) -RTPS Operation ACK_CACHE_CHANGE SN 2 -RTPS Operation ACK_CACHE_CHANGE SN 3 -RTPS Operation NACK_CACHE_CHANGE SN 2 -DDS Operation WRITE [TS 6s, Aligned Payload] (ACCEPTED) - SAMPLE MEMORY: 8(S2),24(S4),32(S5),0(S6)/16 - PAYLOAD MEMORY: 11(S2),22(S2),44(S4),0(S5),33(S6)/- -DDS Operation DISPOSE [TS 7s] (REJECTED: Payload Memory Full) -RTPS Operation ACK_CACHE_CHANGE SN 2 -RTPS Operation ACK_CACHE_CHANGE SN 2 -DDS Operation DISPOSE [TS 7s] (ACCEPTED) - SAMPLE MEMORY: 24(S4),32(S5),0(S6),16(S7)/8 - PAYLOAD MEMORY: 44(S4),0(S5),33(S6),11(S7)/22 -DDS Operation UNREGISTER_INSTANCE [TS 8s] (REJECTED: MAX_SAMPLES exceeded) -RTPS Operation ACK_CACHE_CHANGE SN 5 -DDS Operation UNREGISTER_INSTANCE [TS 8s] (ACCEPTED) - SAMPLE MEMORY: 24(S4),0(S6),16(S7),8(S8)/32 - PAYLOAD MEMORY: 44(S4),33(S6),11(S7),22(S8)/0 -RTPS Operation GET_MIN_SN (Expected SN 4) -RTPS Operation GET_MAX_SN (Expected SN 8) -RTPS Operation GET_CACHE_CHANGE SN 4 -RTPS Operation GET_CACHE_CHANGE SN 6 -RTPS Operation GET_CACHE_CHANGE SN 7 -RTPS Operation GET_CACHE_CHANGE SN 8 -RTPS Operation ACK_CACHE_CHANGE SN 6 -RTPS Operation ACK_CACHE_CHANGE SN 8 -DDS Operation DISPOSE [TS 9s] (ACCEPTED) - SAMPLE MEMORY: 24(S4),16(S7),8(S8),32(S9)/0 - PAYLOAD MEMORY: 44(S4),11(S7),22(S8),0(S9)/33 -DDS Operation UNREGISTER_INSTANCE [TS 10s] (ACCEPTED) - SAMPLE MEMORY: 24(S4),16(S7),32(S9),0(S10)/8 - PAYLOAD MEMORY: 44(S4),11(S7),0(S9),33(S10)/22 -RTPS Operation ACK_CACHE_CHANGE SN 7 -DDS Operation WRITE [TS 11s, Aligned Payload (2 Slots)] (REJECTED: Payload Memory Full) -RTPS Operation REMOVE_CACHE_CHANGE SN 12 (Invalid) -RTPS Operation REMOVE_CACHE_CHANGE SN 4 - SAMPLE MEMORY: 16(S7),32(S9),0(S10)/8,24 - PAYLOAD MEMORY: 11(S7),0(S9),33(S10)/44,22 -DDS Operation WRITE [TS 11s, Aligned Payload (2 Slots)] (ACCEPTED) - SAMPLE MEMORY: 16(S7),32(S9),0(S10),8(S11)/24 - PAYLOAD MEMORY: 11(S7),0(S9),33(S10),44(S11),22(S11)/- diff --git a/src/Tests/Level_0/L0_dds_writer_test1_ain.vhd b/src/Tests/Level_0/L0_dds_writer_test1_ain.vhd deleted file mode 100644 index 73fe88e..0000000 --- a/src/Tests/Level_0/L0_dds_writer_test1_ain.vhd +++ /dev/null @@ -1,1020 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library osvvm; -- Utility Library -context osvvm.OsvvmContext; - -use work.rtps_package.all; -use work.user_config.all; -use work.rtps_config_package.all; -use work.rtps_test_package.all; - --- This testbench tests the General Operation of the DDS Writer. It tests the correctness of the RTPS --- GET_MIN_SN, GET_MAX_SN, GET_CACHE_CHANGE, REMOVE_CACHE_CHANGE, ACK_CACHE_CHANGE, and NACK_CACHE_CHANGE Operations and the --- DDS REGISTER_INSTANCE, UNREGISTER_INSTANCE, WRITE, DISPOSE, and LOOKUP_INSTANCE Operations. --- More specifically the testbench covers following tests: --- TEST: GET_MIN_SN/GET_MAX_SN ON EMPTY --- TEST: GET_MIN_SN/GET_MAX_SN ON 1 SAMPLE --- TEST: GET_MIN_SN/GET_MAX_SN ON >1 SAMPLE --- TEST: WRITE ALIGNED PAYLOAD --- TEST: WRITE UNALIGNED PAYLOAD [>1 SLOT] --- TEST: WRITE UNALIGNED PAYLOAD [<1 SLOT] --- TEST: NORMAL WRITE --- TEST: WRITE ON DISPOSED INSTANCE --- TEST: WRITE ON PAYLOAD MEMORY FULL [WITHOUT ACKed SAMPLES] --- TEST: WRITE ON PAYLOAD MEMORY FULL [WITH ACKed SAMPLES] --- TEST: WRITE ON UNREGISTERED INSTANCE --- TEST: ADD SAMPLE WITH KEY_HASH --- TEST: ADD SAMPLE WITH HANDLE_NIL --- TEST: NORMAL REGISTER --- TEST: NORMAL DISPOSE --- TEST: DISPOSE ON PAYLOAD MEMORY FULL [WITHOUT ACKed SAMPLES] --- TEST: DISPOSE ON PAYLOAD MEMORY FULL [WITH ACKed SAMPLES] --- TEST: DISPOSE ON UNREGISTERED INSTANCE --- TEST: GET_CACHE_CHANGE [UNKNOWN SN] --- TEST: GET_CACHE_CHANGE [KNOWN SN, ALIGNED PAYLOAD] --- TEST: GET_CACHE_CHANGE [KNOWN SN, UNALIGNED PAYLOAD, >1 SLOT] --- TEST: GET_CACHE_CHANGE [KNOWN SN, UNALIGNED PAYLOAD, <1 SLOT] --- TEST: NORMAL UNREGISTER --- TEST: UNREGISTER INSTANCE ON PAYLOAD MEMORY FULL [WITH ACKed SAMPLES] --- TEST: UNREGISTER INSTANCE ON PAYLOAD MEMORY FULL [WITHOUT ACKed SAMPLES] --- TEST: UNREGISTER ON DISPOSED INSTANCE --- TEST: NORMAL ACK_CACHE_CHANGE --- TEST: ACK_CACHE_CHANGE [ALREADY ACKed SN] --- TEST: NORMAL NACK_CACHE_CHANGE --- TEST: ADD SAMPLE ON MAX_SAMPLES [KNOWN INSTANCE,WITHOUT ACKed SAMPLES] --- TEST: ADD SAMPLE ON MAX_SAMPLES [KNOWN INSTANCE,WITH ACKed SAMPLES] --- TEST: ADD SAMPLE ON MAX_SAMPLES [KNOWN INSTANCE,WITH ACKed SAMPLES (>1)] --- TEST: ADD SAMPLE BIGGER THAN AVAILABLE MEMORY SPACE [WITH ACKed SAMPLES] --- TEST: REMOVE_CACHE_CHANGE [UNKNOWN SN] --- TEST: REMOVE_CACHE_CHANGE [KNOWN SN] --- TEST: INSTANCE LOOKUP [KNOWN INSTANCE] - -entity L0_dds_writer_test1_ain is -end entity; - -architecture testbench of L0_dds_writer_test1_ain is - - -- *CONSTANT DECLARATION* - constant MAX_REMOTE_ENDPOINTS : natural := 3; - - -- *TYPE DECLARATION* - type DDS_STAGE_TYPE is (IDLE, START, PUSH, DONE); - type RTPS_STAGE_TYPE is (IDLE, START, DONE, CHECK); - - -- *SIGNAL DECLARATION* - signal clk : std_logic := '0'; - signal reset : std_logic := '1'; - signal check_time : TIME_TYPE := TIME_ZERO; - signal start_rtps, start_dds, ack_rtps, ack_dds, done_rtps, done_dds : std_logic := '0'; - signal opcode_rtps : HISTORY_CACHE_OPCODE_TYPE := NOP; - signal opcode_dds : DDS_WRITER_OPCODE_TYPE := NOP; - signal ret_rtps : HISTORY_CACHE_RESPONSE_TYPE := ERROR; - signal seq_nr_rtps, cc_seq_nr : SEQUENCENUMBER_TYPE := SEQUENCENUMBER_UNKNOWN; - signal ready_out_rtps, valid_out_rtps, last_word_out_rtps : std_logic := '0'; - signal ready_in_dds, ready_out_dds, valid_in_dds, valid_out_dds, last_word_in_dds, last_word_out_dds : std_logic := '0'; - signal data_out_rtps, data_in_dds, data_out_dds : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); - signal get_data_rtps, liveliness_assertion, data_available : std_logic := '0'; - signal cc_source_timestamp, source_ts_dds : TIME_TYPE := TIME_INVALID; - signal cc_kind : CACHE_CHANGE_KIND_TYPE := ALIVE; - signal cc_instance_handle, instance_handle_in_dds, instance_handle_out_dds : INSTANCE_HANDLE_TYPE := HANDLE_NIL; - signal max_wait_dds : DURATION_TYPE := DURATION_INFINITE; - signal return_code_dds : std_logic_vector(RETURN_CODE_WIDTH-1 downto 0) := (others => '0'); - signal status : std_logic_vector(STATUS_KIND_WIDTH-1 downto 0) := (others => '0'); - - signal dds_start, dds_done, rtps_start, rtps_done : std_logic := '0'; - signal dds_cnt, rtps_cnt : natural := 0; - signal dds_stage : DDS_STAGE_TYPE := IDLE; - signal rtps_stage : RTPS_STAGE_TYPE := IDLE; - shared variable dds : DDS_WRITER_TEST_TYPE := DEFAULT_DDS_WRITER_TEST; - shared variable rtps : RTPS_WRITER_TEST_TYPE := DEFAULT_RTPS_WRITER_TEST; - signal inst_id, kind_id, sn_id, ts_id, data_id, ih_id, ret_id : AlertLogIDType; - - -- *FUNCTION DECLARATION* - function extract_key_hash (payload : TEST_PACKET_TYPE) return INSTANCE_HANDLE_TYPE is - variable ret : INSTANCE_HANDLE_TYPE := HANDLE_NIL; - begin - for i in 0 to 3 loop - ret(i) := not payload.data(i); - end loop; - - return ret; - end function; - - function gen_sn(input : natural) return SEQUENCENUMBER_TYPE is - variable ret : SEQUENCENUMBER_TYPE; - begin - ret(0) := (others => '0'); - ret(1) := unsigned(int(input, WORD_WIDTH)); - return ret; - end function; - -begin - - -- Unit Under Test - uut : entity work.dds_writer(arch) - generic map( - HISTORY_QOS => KEEP_ALL_HISTORY_QOS, - DEADLINE_QOS => DURATION_INFINITE, - LIFESPAN_QOS => DURATION_INFINITE, - LEASE_DURATION => DURATION_INFINITE, - WITH_KEY => FALSE, - MAX_SAMPLES => std_logic_vector(to_unsigned(4,CDR_LONG_WIDTH)), - MAX_INSTANCES => std_logic_vector(to_unsigned(3,CDR_LONG_WIDTH)), - MAX_SAMPLES_PER_INSTANCE => std_logic_vector(to_unsigned(2,CDR_LONG_WIDTH)), - PAYLOAD_FRAME_SIZE => 11 - ) - port map ( - clk => clk, - reset => reset, - time => check_time, - start_rtps => start_rtps, - opcode_rtps => opcode_rtps, - ack_rtps => ack_rtps, - done_rtps => done_rtps, - ret_rtps => ret_rtps, - seq_nr_rtps => seq_nr_rtps, - get_data_rtps => get_data_rtps, - data_out_rtps => data_out_rtps, - valid_out_rtps => valid_out_rtps, - ready_out_rtps => ready_out_rtps, - last_word_out_rtps => last_word_out_rtps, - liveliness_assertion => liveliness_assertion, - data_available => data_available, - cc_instance_handle => cc_instance_handle, - cc_kind => cc_kind, - cc_source_timestamp => cc_source_timestamp, - cc_seq_nr => cc_seq_nr, - start_dds => start_dds, - ack_dds => ack_dds, - opcode_dds => opcode_dds, - instance_handle_in_dds => instance_handle_in_dds, - source_ts_dds => source_ts_dds, - max_wait_dds => max_wait_dds, - done_dds => done_dds, - return_code_dds => return_code_dds, - instance_handle_out_dds => instance_handle_out_dds, - ready_in_dds => ready_in_dds, - valid_in_dds => valid_in_dds, - data_in_dds => data_in_dds, - last_word_in_dds => last_word_in_dds, - ready_out_dds => ready_out_dds, - valid_out_dds => valid_out_dds, - data_out_dds => data_out_dds, - last_word_out_dds => last_word_out_dds, - status => status - ); - - stimulus_prc : process - variable RV : RandomPType; - variable kh1, kh2, kh3, kh4 : INSTANCE_HANDLE_TYPE := HANDLE_NIL; - variable cc1, cc2, cc3, cc4, cc : CACHE_CHANGE_TYPE := DEFAULT_CACHE_CHANGE; - - impure function gen_payload(key_hash : INSTANCE_HANDLE_TYPE; len : natural) return TEST_PACKET_TYPE is - variable ret : TEST_PACKET_TYPE := EMPTY_TEST_PACKET; - begin - assert (len >= 4) report "Payload length has to be at least 16 Bytes long" severity FAILURE; - - for i in 0 to len-1 loop - if (i < 4) then - -- NOTE: Beginning of payload is negated key to allow deterministic Key Hash generation from the kh_prc - ret.data(ret.length) := not key_hash(i); - else - ret.data(ret.length) := RV.RandSlv(WORD_WIDTH); - end if; - ret.length := ret.length + 1; - end loop; - ret.last(ret.length-1) := '1'; - - return ret; - end function; - - impure function gen_key_hash return KEY_HASH_TYPE is - variable ret : KEY_HASH_TYPE := KEY_HASH_NIL; - begin - for i in 0 to KEY_HASH_TYPE'length-1 loop - ret(i) := RV.RandSlv(WORD_WIDTH); - end loop; - return ret; - end function; - - procedure start_dds is - begin - dds_start <= '1'; - wait until rising_edge(clk); - dds_start <= '0'; - wait until rising_edge(clk); - end procedure; - - procedure start_rtps is - begin - rtps_start <= '1'; - wait until rising_edge(clk); - rtps_start <= '0'; - wait until rising_edge(clk); - end procedure; - - procedure wait_on_dds is - begin - if (dds_done /= '1') then - wait until dds_done = '1'; - end if; - end procedure; - - procedure wait_on_rtps is - begin - if (rtps_done /= '1') then - wait until rtps_done = '1'; - end if; - end procedure; - - procedure wait_on_completion is - begin - if (rtps_done /= '1' or dds_done /= '1') then - wait until rtps_done = '1' and dds_done = '1'; - end if; - end procedure; - - begin - - SetAlertLogName("L0_dds_writer_test1_ain - (KEEP ALL, Infinite Lifespan, Keyless) - General"); - SetAlertEnable(FAILURE, TRUE); - SetAlertEnable(ERROR, TRUE); - SetAlertEnable(WARNING, TRUE); - SetLogEnable(DEBUG, FALSE); - SetLogEnable(PASSED, FALSE); - SetLogEnable(INFO, TRUE); - RV.InitSeed(RV'instance_name); - kind_id <= GetAlertLogID("Cache Change Kind", ALERTLOG_BASE_ID); - sn_id <= GetAlertLogID("SequenceNumber", ALERTLOG_BASE_ID); - ts_id <= GetAlertLogID("TimeStamp", ALERTLOG_BASE_ID); - ih_id <= GetAlertLogID("Instance Handle", ALERTLOG_BASE_ID); - data_id <= GetAlertLogID("Data Out", ALERTLOG_BASE_ID); - ret_id <= GetAlertLogID("Return Code", ALERTLOG_BASE_ID); - - -- Key Hashes - kh1 := gen_key_hash; - kh2 := gen_key_hash; - kh3 := gen_key_hash; - kh4 := gen_key_hash; - - - - Log("Initiating Test", INFO); - reset <= '1'; - wait until rising_edge(clk); - wait until rising_edge(clk); - reset <= '0'; - -- Stored CC: 0, 0, 0, 0 - - -- TEST: GET_MIN_SN/GET_MAX_SN ON EMPTY - - Log("RTPS Operation GET_MIN_SN (Expected SEQUENCENUMBER_UNKNOWN)", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_MIN_SN; - rtps.cc.seq_nr := SEQUENCENUMBER_UNKNOWN; - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_MAX_SN (Expected SEQUENCENUMBER_UNKNOWN)", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_MAX_SN; - rtps.cc.seq_nr := SEQUENCENUMBER_UNKNOWN; - start_rtps; - wait_on_rtps; - - -- TEST: WRITE ALIGNED PAYLOAD - -- TEST: NORMAL WRITE - -- TEST: ADD SAMPLE WITH KEY_HASH - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh1; - cc.payload := gen_payload(kh1,10); - cc.seq_nr := gen_sn(1); - cc.src_timestamp := gen_duration(1,0); - - Log("DDS Operation WRITE [TS 1s, Aligned Payload] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc1 := cc; - -- Stored CC: S1, 0, 0, 0 - - -- TEST: GET_MIN_SN/GET_MAX_SN ON 1 SAMPLE - - Log("RTPS Operation GET_MIN_SN (Expected SN 1)", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_MIN_SN; - rtps.cc.seq_nr := gen_sn(1); - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_MAX_SN (Expected SN 1)", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_MAX_SN; - rtps.cc.seq_nr := gen_sn(1); - start_rtps; - wait_on_rtps; - - -- TEST: ADD SAMPLE WITH HANDLE_NIL - -- TEST: WRITE UNALIGNED PAYLOAD [>1 SLOT] - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh1; - cc.payload := gen_payload(kh1,18); - cc.seq_nr := gen_sn(2); - cc.src_timestamp := gen_duration(2,0); - - Log("DDS Operation WRITE [TS 2s, Unaligned Payload (2 Slots)] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.cc.instance:= HANDLE_NIL; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc2 := cc; - -- Stored CC: S1, S2, 0, 0 - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh2; - cc.payload := gen_payload(kh2,10); - cc.seq_nr := gen_sn(3); - cc.src_timestamp := gen_duration(3,0); - - -- TEST: NORMAL REGISTER - - Log("DDS Operation REGISTER_INSTANCE 2 (Illegal Operation)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := REGISTER_INSTANCE; - dds.cc := cc; - dds.cc.instance:= HANDLE_NIL; - start_dds; - wait_on_dds; - - -- TEST: NORMAL DISPOSE - -- TEST: WRITE UNALIGNED PAYLOAD [<1 SLOT] - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_DISPOSED; - cc.instance := kh1; - cc.payload := gen_payload(kh1,5); - cc.seq_nr := gen_sn(3); - cc.src_timestamp := gen_duration(3,0); - - Log("DDS Operation DISPOSE [TS 3s] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := DISPOSE; - dds.cc := cc; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc3 := cc; - -- Stored CC: S1, S2, S3, 0 - - -- TEST: GET_MIN_SN/GET_MAX_SN ON >1 SAMPLE - - Log("RTPS Operation GET_MIN_SN (Expected SN 1)", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_MIN_SN; - rtps.cc.seq_nr := gen_sn(1); - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_MAX_SN (Expected SN 3)", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_MAX_SN; - rtps.cc.seq_nr := gen_sn(3); - start_rtps; - wait_on_rtps; - - -- TEST: GET_CACHE_CHANGE [UNKNOWN SN] - - Log("RTPS Operation GET_CACHE_CHANGE SN 4 (Invalid)", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_CACHE_CHANGE; - rtps.cc.seq_nr := gen_sn(4); - rtps.ret_code := INVALID; - start_rtps; - wait_on_rtps; - - -- TEST: GET_CACHE_CHANGE [KNOWN SN, ALIGNED PAYLOAD] - - Log("RTPS Operation GET_CACHE_CHANGE SN 1", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_CACHE_CHANGE; - rtps.cc := cc1; - start_rtps; - wait_on_rtps; - - -- TEST: GET_CACHE_CHANGE [KNOWN SN, UNALIGNED PAYLOAD, >1 SLOT] - - Log("RTPS Operation GET_CACHE_CHANGE SN 2", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_CACHE_CHANGE; - rtps.cc := cc2; - start_rtps; - wait_on_rtps; - - -- TEST: GET_CACHE_CHANGE [KNOWN SN, UNALIGNED PAYLOAD, <1 SLOT] - - Log("RTPS Operation GET_CACHE_CHANGE SN 3", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_CACHE_CHANGE; - rtps.cc := cc3; - start_rtps; - wait_on_rtps; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh1; - cc.payload := gen_payload(kh1,10); - cc.seq_nr := gen_sn(4); - cc.src_timestamp := gen_duration(4,0); - - -- TEST: WRITE ON DISPOSED INSTANCE - - Log("DDS Operation WRITE [TS 2s, Aligned Payload] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.cc.instance:= HANDLE_NIL; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc4 := cc; - -- Stored CC: S1, S2, S3, S4 - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_UNREGISTERED; - cc.instance := kh1; - cc.payload := gen_payload(kh1,5); - cc.seq_nr := gen_sn(5); - cc.src_timestamp := gen_duration(5,0); - - -- TEST: UNREGISTER INSTANCE ON PAYLOAD MEMORY FULL [WITHOUT ACKed SAMPLES] - - Log("DDS Operation UNREGISTER_INSTANCE [TS 5s] (REJECTED: Payload Memory Full)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := UNREGISTER_INSTANCE; - dds.cc := cc; - dds.ret_code := RETCODE_OUT_OF_RESOURCES; - start_dds; - wait_on_dds; - - -- TEST: NORMAL ACK_CACHE_CHANGE - - Log("RTPS Operation ACK_CACHE_CHANGE SN 1", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := ACK_CACHE_CHANGE; - rtps.cc := cc1; - start_rtps; - wait_on_rtps; - - -- TEST: UNREGISTER INSTANCE ON PAYLOAD MEMORY FULL [WITH ACKed SAMPLES] - -- TEST: NORMAL UNREGISTER - - Log("DDS Operation UNREGISTER_INSTANCE [TS 5s] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := UNREGISTER_INSTANCE; - dds.cc := cc; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc1 := cc; - -- Stored CC: S5, S2, S3, S4 - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh1; - cc.payload := gen_payload(kh1,10); - cc.seq_nr := gen_sn(6); - cc.src_timestamp := gen_duration(6,0); - - -- TEST: WRITE ON PAYLOAD MEMORY FULL [WITHOUT ACKed SAMPLES] - - Log("DDS Operation WRITE [TS 6s, Aligned Payload] (REJECTED: Payload Memory Full)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.cc.instance:= HANDLE_NIL; - dds.ret_code := RETCODE_OUT_OF_RESOURCES; - start_dds; - wait_on_dds; - - Log("RTPS Operation ACK_CACHE_CHANGE SN 2", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := ACK_CACHE_CHANGE; - rtps.cc := cc2; - start_rtps; - wait_on_rtps; - - Log("RTPS Operation ACK_CACHE_CHANGE SN 3", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := ACK_CACHE_CHANGE; - rtps.cc := cc3; - start_rtps; - wait_on_rtps; - - -- TEST: NORMAL NACK_CACHE_CHANGE - - Log("RTPS Operation NACK_CACHE_CHANGE SN 2", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := NACK_CACHE_CHANGE; - rtps.cc := cc2; - start_rtps; - wait_on_rtps; - - -- TEST: WRITE ON PAYLOAD MEMORY FULL [WITH ACKed SAMPLES] - -- TEST: WRITE ON UNREGISTERED INSTANCE - - Log("DDS Operation WRITE [TS 6s, Aligned Payload] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.cc.instance:= HANDLE_NIL; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc3 := cc; - -- Stored CC: S5, S2, S6, S4 - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_DISPOSED; - cc.instance := kh1; - cc.payload := gen_payload(kh1,5); - cc.seq_nr := gen_sn(7); - cc.src_timestamp := gen_duration(7,0); - - -- TEST: DISPOSE ON PAYLOAD MEMORY FULL [WITHOUT ACKed SAMPLES] - - Log("DDS Operation DISPOSE [TS 7s] (REJECTED: Payload Memory Full)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := DISPOSE; - dds.cc := cc; - dds.ret_code := RETCODE_OUT_OF_RESOURCES; - start_dds; - wait_on_dds; - - Log("RTPS Operation ACK_CACHE_CHANGE SN 2", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := ACK_CACHE_CHANGE; - rtps.cc := cc2; - start_rtps; - wait_on_rtps; - - -- TEST: ACK_CACHE_CHANGE [ALREADY ACKed SN] - - Log("RTPS Operation ACK_CACHE_CHANGE SN 2", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := ACK_CACHE_CHANGE; - rtps.cc := cc2; - start_rtps; - wait_on_rtps; - - -- TEST: DISPOSE ON PAYLOAD MEMORY FULL [WITH ACKed SAMPLES] - - Log("DDS Operation DISPOSE [TS 7s] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := DISPOSE; - dds.cc := cc; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc2 := cc; - -- Stored CC: S5, S7, S6, S4 - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_UNREGISTERED; - cc.instance := kh1; - cc.payload := gen_payload(kh1,5); - cc.seq_nr := gen_sn(8); - cc.src_timestamp := gen_duration(8,0); - - -- TEST: ADD SAMPLE ON MAX_SAMPLES [KNOWN INSTANCE,WITHOUT ACKed SAMPLES] - - Log("DDS Operation UNREGISTER_INSTANCE [TS 8s] (REJECTED: MAX_SAMPLES exceeded)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := UNREGISTER_INSTANCE; - dds.cc := cc; - dds.ret_code := RETCODE_OUT_OF_RESOURCES; - start_dds; - wait_on_dds; - - Log("RTPS Operation ACK_CACHE_CHANGE SN 5", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := ACK_CACHE_CHANGE; - rtps.cc := cc1; - start_rtps; - wait_on_rtps; - - -- TEST: ADD SAMPLE ON MAX_SAMPLES [KNOWN INSTANCE,WITH ACKed SAMPLES] - -- TEST: UNREGISTER ON DISPOSED INSTANCE - - Log("DDS Operation UNREGISTER_INSTANCE [TS 8s] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := UNREGISTER_INSTANCE; - dds.cc := cc; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc1 := cc; - -- Stored CC: S8, S7, S6, S4 - - -- VALIDATE STATE - - Log("RTPS Operation GET_MIN_SN (Expected SN 4)", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_MIN_SN; - rtps.cc.seq_nr := gen_sn(4); - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_MAX_SN (Expected SN 8)", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_MAX_SN; - rtps.cc.seq_nr := gen_sn(8); - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_CACHE_CHANGE SN 4", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_CACHE_CHANGE; - rtps.cc := cc4; - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_CACHE_CHANGE SN 6", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_CACHE_CHANGE; - rtps.cc := cc3; - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_CACHE_CHANGE SN 7", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_CACHE_CHANGE; - rtps.cc := cc2; - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_CACHE_CHANGE SN 8", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_CACHE_CHANGE; - rtps.cc := cc1; - start_rtps; - wait_on_rtps; - - Log("RTPS Operation ACK_CACHE_CHANGE SN 6", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := ACK_CACHE_CHANGE; - rtps.cc := cc3; - start_rtps; - wait_on_rtps; - - Log("RTPS Operation ACK_CACHE_CHANGE SN 8", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := ACK_CACHE_CHANGE; - rtps.cc := cc1; - start_rtps; - wait_on_rtps; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_DISPOSED; - cc.instance := kh1; - cc.payload := gen_payload(kh1,5); - cc.seq_nr := gen_sn(9); - cc.src_timestamp := gen_duration(9,0); - - -- TEST: ADD SAMPLE ON MAX_SAMPLES [KNOWN INSTANCE,WITH ACKed SAMPLES (>1)] - - Log("DDS Operation DISPOSE [TS 9s] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := DISPOSE; - dds.cc := cc; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc3 := cc; - -- Stored CC: S8, S7, S9, S4 - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_UNREGISTERED; - cc.instance := kh1; - cc.payload := gen_payload(kh1,5); - cc.seq_nr := gen_sn(10); - cc.src_timestamp := gen_duration(10,0); - - -- TEST: DISPOSE ON UNREGISTERED INSTANCE - - Log("DDS Operation UNREGISTER_INSTANCE [TS 10s] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := UNREGISTER_INSTANCE; - dds.cc := cc; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc1 := cc; - -- Stored CC: S10, S7, S9, S4 - - Log("RTPS Operation ACK_CACHE_CHANGE SN 7", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := ACK_CACHE_CHANGE; - rtps.cc := cc2; - start_rtps; - wait_on_rtps; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh1; - cc.payload := gen_payload(kh1,20); - cc.seq_nr := gen_sn(11); - cc.src_timestamp := gen_duration(11,0); - - -- TEST: ADD SAMPLE BIGGER THAN AVAILABLE MEMORY SPACE [WITH ACKed SAMPLES] - - Log("DDS Operation WRITE [TS 11s, Aligned Payload (2 Slots)] (REJECTED: Payload Memory Full)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.ret_code := RETCODE_OUT_OF_RESOURCES; - start_dds; - wait_on_dds; - - -- TEST: REMOVE_CACHE_CHANGE [UNKNOWN SN] - - Log("RTPS Operation REMOVE_CACHE_CHANGE SN 12 (Invalid)", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := REMOVE_CACHE_CHANGE; - rtps.cc.seq_nr := gen_sn(12); - rtps.ret_code := INVALID; - start_rtps; - wait_on_rtps; - - -- TEST: REMOVE_CACHE_CHANGE [KNOWN SN] - - Log("RTPS Operation REMOVE_CACHE_CHANGE SN 4", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := REMOVE_CACHE_CHANGE; - rtps.cc := cc4; - start_rtps; - wait_on_rtps; - -- Stored CC: S10, S7, S9, 0 - - Log("DDS Operation WRITE [TS 11s, Aligned Payload (2 Slots)] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.cc.instance:= HANDLE_NIL; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc4 := cc; - -- Stored CC: S10, S7, S9, S11 - - -- VALIDATE STATE - - Log("RTPS Operation GET_MIN_SN (Expected SN 7)", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_MIN_SN; - rtps.cc.seq_nr := gen_sn(7); - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_MAX_SN (Expected SN 11)", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_MAX_SN; - rtps.cc.seq_nr := gen_sn(11); - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_CACHE_CHANGE SN 7", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_CACHE_CHANGE; - rtps.cc := cc2; - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_CACHE_CHANGE SN 9", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_CACHE_CHANGE; - rtps.cc := cc3; - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_CACHE_CHANGE SN 10", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_CACHE_CHANGE; - rtps.cc := cc1; - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_CACHE_CHANGE SN 11", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_CACHE_CHANGE; - rtps.cc := cc4; - start_rtps; - wait_on_rtps; - - -- TEST: INSTANCE LOOKUP [KNOWN INSTANCE] - - Log("DDS Operation LOOKUP_INSTANCE [Illegal Operation]", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := LOOKUP_INSTANCE; - dds.cc := cc; - dds.cc.instance:= HANDLE_NIL; - start_dds; - wait_on_dds; - - wait_on_completion; - TranscriptOpen(RESULTS_FILE, APPEND_MODE); - SetTranscriptMirror; - ReportAlerts; - TranscriptClose; - std.env.stop; - wait; - end process; - - clock_prc : process - begin - clk <= '0'; - wait for 25 ns; - clk <= '1'; - wait for 25 ns; - end process; - - alert_prc : process(all) - begin - if rising_edge(clk) then - -- TODO - end if; - end process; - - dds_prc : process(all) - begin - if rising_edge(clk) then - dds_done <= '0'; - case (dds_stage) is - when IDLE => - if (dds_start = '1') then - dds_stage <= START; - else - dds_done <= '1'; - end if; - when START => - if (ack_dds = '1') then - dds_stage <= PUSH; - dds_cnt <= 0; - end if; - when PUSH => - if (ready_in_dds = '1') then - dds_cnt <= dds_cnt + 1; - if (dds_cnt = dds.cc.payload.length-1) then - -- DEFAULT - dds_stage <= DONE; - end if; - elsif (done_dds = '1') then - AffirmIfEqual(ret_id, return_code_dds, dds.ret_code); - dds_stage <= IDLE; - end if; - when DONE => - if (done_dds = '1') then - if (dds.opcode = REGISTER_INSTANCE or dds.opcode = LOOKUP_INSTANCE) then - AffirmIfEqual(ih_id, to_unsigned(instance_handle_out_dds), to_unsigned(dds.cc.instance)); - else - AffirmIfEqual(ret_id, return_code_dds, dds.ret_code); - end if; - dds_stage <= IDLE; - end if; - end case; - end if; - - -- DEFAULT - start_dds <= '0'; - opcode_dds <= NOP; - valid_in_dds <= '0'; - last_word_in_dds <= '0'; - data_in_dds <= (others => '0'); - instance_handle_in_dds <= HANDLE_NIL; - source_ts_dds <= TIME_INVALID; - ready_out_dds <= '0'; - - case (dds_stage) is - when START => - start_dds <= '1'; - opcode_dds <= dds.opcode; - instance_handle_in_dds <= dds.cc.instance; - source_ts_dds <= dds.cc.src_timestamp; - when PUSH => - valid_in_dds <= '1'; - data_in_dds <= dds.cc.payload.data(dds_cnt); - last_word_in_dds <= dds.cc.payload.last(dds_cnt); - when others => - null; - end case; - end process; - - rtps_prc : process(all) - begin - if rising_edge(clk) then - rtps_done <= '0'; - case (rtps_stage) is - when IDLE => - if (rtps_start = '1') then - rtps_stage <= START; - else - rtps_done <= '1'; - end if; - when START => - if (ack_rtps = '1') then - rtps_stage <= DONE; - end if; - when DONE => - if (done_rtps = '1') then - -- DEFAULT - rtps_stage <= IDLE; - - AffirmIfEqual(ret_id, HISTORY_CACHE_RESPONSE_TYPE'pos(ret_rtps), HISTORY_CACHE_RESPONSE_TYPE'pos(rtps.ret_code)); - case (rtps.opcode) is - when GET_CACHE_CHANGE => - if (rtps.ret_code = OK) then - AffirmIfEqual(kind_id, CACHE_CHANGE_KIND_TYPE'pos(cc_kind), CACHE_CHANGE_KIND_TYPE'pos(rtps.cc.kind)); - AffirmIfEqual(sn_id, to_unsigned(cc_seq_nr), to_unsigned(rtps.cc.seq_nr)); - AffirmIfEqual(ts_id, to_unsigned(cc_source_timestamp), to_unsigned(rtps.cc.src_timestamp)); - rtps_stage <= CHECK; - rtps_cnt <= 0; - end if; - when GET_MIN_SN => - AffirmIfEqual(sn_id, to_unsigned(cc_seq_nr), to_unsigned(rtps.cc.seq_nr)); - when GET_MAX_SN => - AffirmIfEqual(sn_id, to_unsigned(cc_seq_nr), to_unsigned(rtps.cc.seq_nr)); - when others => - null; - end case; - end if; - when CHECK => - if (valid_out_rtps = '1') then - AffirmIfEqual(data_id, last_word_out_rtps & data_out_rtps, rtps.cc.payload.last(rtps_cnt) & rtps.cc.payload.data(rtps_cnt)); - rtps_cnt <= rtps_cnt + 1; - if (rtps_cnt = rtps.cc.payload.length-1) then - rtps_stage <= IDLE; - end if; - end if; - end case; - end if; - - -- DEFAULT - start_rtps <= '0'; - opcode_rtps <= NOP; - seq_nr_rtps <= SEQUENCENUMBER_UNKNOWN; - get_data_rtps <= '0'; - ready_out_rtps <= '0'; - - case (rtps_stage) is - when START => - start_rtps <= '1'; - opcode_rtps <= rtps.opcode; - seq_nr_rtps <= rtps.cc.seq_nr; - when DONE => - if (done_rtps = '1') then - case (rtps.opcode) is - when GET_CACHE_CHANGE => - get_data_rtps <= '1'; - when others => - null; - end case; - end if; - when CHECK => - ready_out_rtps <= '1'; - when others => - null; - end case; - end process; - - watchdog : process - begin - wait for 1 ms; - Alert("Test timeout", FAILURE); - std.env.stop; - end process; - -end architecture; \ No newline at end of file diff --git a/src/Tests/Level_0/L0_dds_writer_test1_lik.txt b/src/Tests/Level_0/L0_dds_writer_test1_lik.txt deleted file mode 100644 index aafa3f5..0000000 --- a/src/Tests/Level_0/L0_dds_writer_test1_lik.txt +++ /dev/null @@ -1,225 +0,0 @@ - SAMPLE MEMORY: -/0,9,18,27,36 - PAYLOAD MEMORY: -/0,11,22,33,44 - INSTANCE MEMORY: -/0,8,16 -RTPS Operation GET_MIN_SN (Expected SEQUENCENUMBER_UNKNOWN) -RTPS Operation GET_MAX_SN (Expected SEQUENCENUMBER_UNKNOWN) -DDS Operation WRITE [TS 1s, Instance 1, Aligned Payload] (REJECTED: Instance not Registered) -DDS Operation WRITE [TS 1s, Instance 1, HANDLE_NIL, Aligned Payload] (ACCEPTED) - SAMPLE MEMORY: 0(I1S1)/9,18,27,36 - PAYLOAD MEMORY: 0(I1S1)/11,22,33,44 - INSTANCE MEMORY: 0(I1)/8,16 -RTPS Operation GET_MIN_SN (Expected SN 1) -RTPS Operation GET_MAX_SN (Expected SN 1) -DDS Operation WRITE [TS 1s, Instance 1, Unaligned Payload (2 Slots)] (ACCEPTED) - SAMPLE MEMORY: 0(I1S1),9(I1S2)/18,27,36 - PAYLOAD MEMORY: 0(I1S1),11(I1S2),22(I1S2)/33,44 - INSTANCE MEMORY: 0(I1)/8,16 -DDS Operation DISPOSE [TS 3s, Instance 2] (REJECTED: Instance not Registered) -DDS Operation REGISTER_INSTANCE 2 (ACCEPTED) - SAMPLE MEMORY: 0(I1S1),9(I1S2)/18,27,36 - PAYLOAD MEMORY: 0(I1S1),11(I1S2),22(I1S2)/33,44 - INSTANCE MEMORY: 8(I2),0(I1)/16 -DDS Operation DISPOSE [TS 3s, Instance 1] (ACCEPTED) - SAMPLE MEMORY: 0(I1S1),9(I1S2),18(I2S3)/27,36 - PAYLOAD MEMORY: 0(I1S1),11(I1S2),22(I1S2),33(I2S3)/44 - INSTANCE MEMORY: 8(I2),0(I1)/16 -RTPS Operation GET_MIN_SN (Expected SN 1) -RTPS Operation GET_MAX_SN (Expected SN 3) -RTPS Operation GET_CACHE_CHANGE SN 4 (Invalid) -RTPS Operation GET_CACHE_CHANGE SN 1 -RTPS Operation GET_CACHE_CHANGE SN 2 -RTPS Operation GET_CACHE_CHANGE SN 3 -DDS Operation WRITE [TS 4s, Instance 1, Aligned Payload] (ACCEPTED) - SAMPLE MEMORY: 0(I1S1),9(I1S2),18(I2S3),27(I2S4)/36 - PAYLOAD MEMORY: 0(I1S1),11(I1S2),22(I1S2),33(I2S3),44(I2S4)/- - INSTANCE MEMORY: 8(I2),0(I1)/16 -DDS Operation WRITE [TS 5s, Instance 3, HANDLE_NIL, Aligned Payload] (ACCEPTED) - SAMPLE MEMORY: 9(I1S2),18(I2S3),27(I2S4),36(I3S5)/0 - PAYLOAD MEMORY: 11(I1S2),22(I1S2),33(I2S3),44(I2S4),0(I3S5)/- - INSTANCE MEMORY: 16(I3),8(I2),0(I1)/- -RTPS Operation ACK_CACHE_CHANGE SN 3 -DDS Operation WRITE [TS 6s, Instance 3, Aligned Payload] (ACCEPTED) - SAMPLE MEMORY: 9(I1S2),27(I2S4),36(I3S5),0(I3S6)/18 - PAYLOAD MEMORY: 11(I1S2),22(I1S2),44(I2S4),0(I3S5),33(I3S6)/- - INSTANCE MEMORY: 16(I3),8(I2),0(I1)/- -RTPS Operation GET_MIN_SN (Expected SN 2) -RTPS Operation GET_MAX_SN (Expected SN 6) -RTPS Operation GET_CACHE_CHANGE SN 2 -RTPS Operation GET_CACHE_CHANGE SN 4 -RTPS Operation GET_CACHE_CHANGE SN 5 -RTPS Operation GET_CACHE_CHANGE SN 6 -DDS Operation DISPOSE [TS 7s, Instance 1] (ACCEPTED) - SAMPLE MEMORY: 27(I2S4),36(I3S5),0(I3S6),18(I1S7)/9 - PAYLOAD MEMORY: 44(I2S4),0(I3S5),33(I3S6),11(I1S7)/22 - INSTANCE MEMORY: 16(I3),8(I2),0(I1)/- -RTPS Operation ACK_CACHE_CHANGE SN 5 -DDS Operation WRITE [TS 8s, Instance 2, Aligned Payload (2 Slots)] (REJECTED: Payload Memory Full) -RTPS Operation REMOVE_CACHE_CHANGE SN 3 (Invalid) -RTPS Operation REMOVE_CACHE_CHANGE SN 5 - SAMPLE MEMORY: 27(I2S4),0(I3S6),18(I1S7)/9,36 - PAYLOAD MEMORY: 44(I2S4),33(I3S6),11(I1S7)/0,22 - INSTANCE MEMORY: 16(I3),8(I2),0(I1)/- -DDS Operation WRITE [TS 8s, Instance 2, Aligned Payload (2 Slots)] (ACCEPTED) - SAMPLE MEMORY: 27(I2S4),0(I3S6),18(I1S7),9(I2S8)/36 - PAYLOAD MEMORY: 44(I2S4),33(I3S6),11(I1S7),0(I2S8),22(I2S8)/- - INSTANCE MEMORY: 16(I3),8(I2),0(I1)/- -RTPS Operation ACK_CACHE_CHANGE SN 7 -DDS Operation DISPOSE [TS 9s, Instance 3] (ACCEPTED) - SAMPLE MEMORY: 27(I2S4),0(I3S6),9(I2S8),36(I3S9)/18 - PAYLOAD MEMORY: 44(I2S4),33(I3S6),0(I2S8),22(I2S8),11(I3S9)/- - INSTANCE MEMORY: 16(I3),8(I2),0(I1)/- -RTPS Operation GET_MIN_SN (Expected SN 4) -RTPS Operation GET_MAX_SN (Expected SN 9) -RTPS Operation GET_CACHE_CHANGE SN 4 -RTPS Operation GET_CACHE_CHANGE SN 6 -RTPS Operation GET_CACHE_CHANGE SN 8 -RTPS Operation GET_CACHE_CHANGE SN 9 -DDS Operation UNREGISTER_INSTANCE [TS 10s, Instance 1] (ACCEPTED) - SAMPLE MEMORY: 0(I3S6),9(I2S8),36(I3S9),18(I1S10)/27 - PAYLOAD MEMORY: 33(I3S6),0(I2S8),22(I2S8),11(I3S9),44(I1S10)/- - INSTANCE MEMORY: 16(I3),8(I2),0(I1)/- -RTPS Operation ACK_CACHE_CHANGE SN 9 -DDS Operation UNREGISTER_INSTANCE [TS 11s, Instance 2] (ACCEPTED) - SAMPLE MEMORY: 0(I3S6),9(I2S8),18(I1S10),27(I2S11)/36 - PAYLOAD MEMORY: 33(I3S6),0(I2S8),22(I2S8),44(I1S10),11(I2S11)/- - INSTANCE MEMORY: 16(I3),8(I2),0(I1)/- -RTPS Operation ACK_CACHE_CHANGE SN 6 -RTPS Operation ACK_CACHE_CHANGE SN 8 -RTPS Operation ACK_CACHE_CHANGE SN 11 -DDS Operation WRITE [TS 12s, Instance 4, HANDLE_NIL, Aligned Payload] (ACCEPTED) - SAMPLE MEMORY: 18(I1S10),36(I4S12)/0,9,27 - PAYLOAD MEMORY: 44(I1S10),33(I4S12)/11,0,22 - INSTANCE MEMORY: 8(I4),16(I3),0(I1)/- -RTPS Operation GET_MIN_SN (Expected SN 10) -RTPS Operation GET_MAX_SN (Expected SN 12) -RTPS Operation GET_CACHE_CHANGE SN 10 -RTPS Operation GET_CACHE_CHANGE SN 12 -DDS Operation REGISTER_INSTANCE 2 (REJECTED: MAX_INSTANCES exceeded) -RTPS Operation ACK_CACHE_CHANGE SN 10 -DDS Operation REGISTER_INSTANCE 2 (ACCEPTED) - SAMPLE MEMORY: 36(I4S12)/0,9,27,18 - PAYLOAD MEMORY: 33(I4S12)/44,11,0,22 - INSTANCE MEMORY: 0(I2),8(I4),16(I3)/- -DDS Operation WRITE [TS 13s, Instance 2, Aligned Payload] (ACCEPTED) - SAMPLE MEMORY: 36(I4S12),0(I2S13)/9,27,18 - PAYLOAD MEMORY: 33(I4S12),44(I2S13)/11,0,22 - INSTANCE MEMORY: 0(I2),8(I4),16(I3)/- -DDS Operation REGISTER_INSTANCE 2 (ACCEPTED) -DDS Operation WRITE [TS 14s, Instance 2, Aligned Payload] (ACCEPTED) - SAMPLE MEMORY: 36(I4S12),0(I2S13),9(I2S14)/27,18 - PAYLOAD MEMORY: 33(I4S12),44(I2S13),11(I2S14)/0,22 - INSTANCE MEMORY: 0(I2),8(I4),16(I3)/- -DDS Operation WRITE [TS 15s, Instance 2, Aligned Payload] (ACCEPTED) - SAMPLE MEMORY: 36(I4S12),9(I2S14),27(I2S15)/18,0 - PAYLOAD MEMORY: 33(I4S12),11(I2S14),0(I2S15)/44,22 - INSTANCE MEMORY: 0(I2),8(I4),16(I3)/- -RTPS Operation ACK_CACHE_CHANGE SN 15 -DDS Operation WRITE [TS 16s, Instance 2, Aligned Payload] (ACCEPTED) - SAMPLE MEMORY: 36(I4S12),9(I2S14),18(I2S16)/0,27 - PAYLOAD MEMORY: 33(I4S12),11(I2S14),44(I2S16)/0,22 - INSTANCE MEMORY: 0(I2),8(I4),16(I3)/- -RTPS Operation ACK_CACHE_CHANGE SN 12 -DDS Operation UNREGISTER_INSTANCE [TS 17s, Instance 2] (ACCEPTED) - SAMPLE MEMORY: 36(I4S12),18(I2S16),0(I2S17)/27,9 - PAYLOAD MEMORY: 33(I4S12),44(I2S16),0(I2S17)/11,22 - INSTANCE MEMORY: 0(I2),8(I4),16(I3)/- -RTPS Operation GET_MIN_SN (Expected SN 12) -RTPS Operation GET_MAX_SN (Expected SN 17) -RTPS Operation GET_CACHE_CHANGE SN 12 -RTPS Operation GET_CACHE_CHANGE SN 16 -RTPS Operation GET_CACHE_CHANGE SN 17 -DDS Operation UNREGISTER_INSTANCE [TS 18s, Instance 4] (ACCEPTED) - SAMPLE MEMORY: 36(I4S12),18(I2S16),0(I2S17),27(I4S18)/9 - PAYLOAD MEMORY: 33(I4S12),44(I2S16),0(I2S17),11(I4S178)/22 - INSTANCE MEMORY: 0(I2),8(I4),16(I3)/- -RTPS Operation NACK_CACHE_CHANGE SN 12 -RTPS Operation ACK_CACHE_CHANGE SN 18 -DDS Operation UNREGISTER_INSTANCE [TS 19s, Instance 3] (ACCEPTED) - SAMPLE MEMORY: 36(I4S12),18(I2S16),0(I2S17),9(I3S19)/27 - PAYLOAD MEMORY: 33(I4S12),44(I2S16),0(I2S17),22(I3S19)/11 - INSTANCE MEMORY: 0(I2),8(I4),16(I3)/- -DDS Operation WRITE [TS 20s, Instance 3, Aligned Payload] (ACCEPTED) - SAMPLE MEMORY: 18(I2S16),0(I2S17),9(I3S19),27(I3S20)/36 - PAYLOAD MEMORY: 44(I2S16),0(I2S17),22(I3S19),11(I3S20)/33 - INSTANCE MEMORY: 0(I2),8(I4),16(I3)/- -DDS Operation WRITE [TS 21s, Instance 3, Aligned Payload] (ACCEPTED) - SAMPLE MEMORY: 18(I2S16),0(I2S17),27(I3S20),36(I3S21)/9 - PAYLOAD MEMORY: 44(I2S16),0(I2S17),11(I3S20),33(I3S21)/22 - INSTANCE MEMORY: 0(I2),8(I4),16(I3)/- -RTPS Operation ACK_CACHE_CHANGE SN 16 -DDS Operation WRITE [TS 22s, Instance 3, Aligned Payload] (ACCEPTED) - SAMPLE MEMORY: 18(I2S16),0(I2S17),36(I3S21),9(I3S22)/27 - PAYLOAD MEMORY: 44(I2S16),0(I2S17),33(I3S21),22(I3S22)/11 - INSTANCE MEMORY: 0(I2),8(I4),16(I3)/- -RTPS Operation ACK_CACHE_CHANGE SN 22 -DDS Operation WRITE [TS 23s, Instance 3, Aligned Payload] (ACCEPTED) - SAMPLE MEMORY: 18(I2S16),0(I2S17),36(I3S21),27(I3S23)/9 - PAYLOAD MEMORY: 44(I2S16),0(I2S17),33(I3S21),11(I3S23)/22 - INSTANCE MEMORY: 0(I2),8(I4),16(I3)/- -RTPS Operation GET_MIN_SN (Expected SN 16) -RTPS Operation GET_MAX_SN (Expected SN 23) -RTPS Operation GET_CACHE_CHANGE SN 21 -RTPS Operation GET_CACHE_CHANGE SN 22 -RTPS Operation GET_CACHE_CHANGE SN 23 -DDS Operation UNREGISTER_INSTANCE [TS 24s, HANDLE_NIL, Instance 1] (REJECTED: Instance not Registered) -DDS Operation WRITE [TS 24s, Instance 1, HANDLE_NIL, Aligned Payload] (ACCEPTED) - SAMPLE MEMORY: 0(I2S17),36(I3S21),27(I3S23),9(I1S24)/18 - PAYLOAD MEMORY: 0(I2S17),33(I3S21),11(I3S23),22(I1S24)/44 - INSTANCE MEMORY: 8(I1),0(I2),16(I3)/- -DDS Operation WRITE [TS 25s, Instance 4, HANDLE_NIL Aligned Payload] (REJECTED: MAX_INSTANCES exceeded) -RTPS Operation ACK_CACHE_CHANGE SN 21 -DDS Operation WRITE [TS 25s, Instance 4, HANDLE_NIL Aligned Payload] (REJECTED: MAX_INSTANCES exceeded) -RTPS Operation ACK_CACHE_CHANGE SN 17 -DDS Operation WRITE [TS 25s, Instance 4, HANDLE_NIL, Aligned Payload] (ACCEPTED) - SAMPLE MEMORY: 36(I3S21),27(I3S23),9(I1S24),18(I4S25)/0 - PAYLOAD MEMORY: 33(I3S21),11(I3S23),22(I1S24),22(I4S25)/0 - INSTANCE MEMORY: 0(I4),8(I1),16(I3)/- -RTPS Operation ACK_CACHE_CHANGE SN 21 -DDS Operation WRITE [TS 26s, Instance 2, HANDLE_NIL, Aligned Payload] (REJECTED: MAX_INSTANCES exceeded) -RTPS Operation ACK_CACHE_CHANGE SN 24 -DDS Operation WRITE [TS 26s, Instance 2, HANDLE_NIL, Aligned Payload] (REJECTED: MAX_INSTANCES exceeded) -DDS Operation UNREGISTER_INSTANCE [TS 26s, Instance 1] (ACCEPTED) - SAMPLE MEMORY: 27(I3S23),9(I1S24),18(I4S25),0(I1S26)/36 - PAYLOAD MEMORY: 11(I3S23),22(I1S24),22(I4S25),0(I1S26)/33 - INSTANCE MEMORY: 0(I4),8(I1),16(I3)/- -DDS Operation REGISTER_INSTANCE 1 (ACCEPTED) -DDS Operation WRITE [TS 27s, Instance 2, HANDLE_NIL, Aligned Payload] (REJECTED: MAX_INSTANCES exceeded) -DDS Operation UNREGISTER_INSTANCE [TS 27s, Instance 3] (ACCEPTED) - SAMPLE MEMORY: 27(I3S23),18(I4S25),0(I1S26),36(I3S27)/9 - PAYLOAD MEMORY: 11(I3S23),22(I4S25),0(I1S26),33(I3S27)/22 - INSTANCE MEMORY: 0(I4),8(I1),16(I3)/- -DDS Operation DISPOSE [TS 28s, Instance 3] (ACCEPTED) - SAMPLE MEMORY: 18(I4S25),0(I1S26),36(I3S27),9(I3S28)/27 - PAYLOAD MEMORY: 22(I4S25),0(I1S26),33(I3S27),22(I3S28)/11 - INSTANCE MEMORY: 0(I4),8(I1),16(I3)/- -RTPS Operation ACK_CACHE_CHANGE SN 27 -RTPS Operation ACK_CACHE_CHANGE SN 28 -DDS Operation WRITE [TS 29s, Instance 2, HANDLE_NIL, Aligned Payload] (ACCEPTED) - SAMPLE MEMORY: 18(I4S25),0(I1S26),27(I2S29)/36,9 - PAYLOAD MEMORY: 22(I4S25),0(I1S26),11(I2S29)/22,33 - INSTANCE MEMORY: 16(I2),0(I4),8(I1)/- -RTPS Operation GET_MIN_SN (Expected SN 25) -RTPS Operation GET_MAX_SN (Expected SN 29) -RTPS Operation GET_CACHE_CHANGE SN 25 -RTPS Operation GET_CACHE_CHANGE SN 26 -RTPS Operation GET_CACHE_CHANGE SN 29 -DDS Operation WRITE [TS 30s, Instance 2, Aligned Payload] (ACCEPTED) - SAMPLE MEMORY: 18(I4S25),0(I1S26),27(I2S29),36(I2S30)/9 - PAYLOAD MEMORY: 22(I4S25),0(I1S26),11(I2S29),22(I2S30)/33 - INSTANCE MEMORY: 16(I2),0(I4),8(I1)/- -RTPS Operation ACK_CACHE_CHANGE SN 25 -RTPS Operation ACK_CACHE_CHANGE SN 26 -DDS Operation WRITE [TS 31s, Instance 4, Aligned Payload] (ACCEPTED) - SAMPLE MEMORY: 0(I1S26),27(I2S29),36(I2S30),9(I4S31)/18 - PAYLOAD MEMORY: 0(I1S26),11(I2S29),22(I2S30),33(I4S31)/22 - INSTANCE MEMORY: 16(I2),0(I4),8(I1)/- -RTPS Operation REMOVE_CACHE_CHANGE SN 31 - SAMPLE MEMORY: 0(I1S26),27(I2S29),36(I2S30)/18,9 - PAYLOAD MEMORY: 0(I1S26),11(I2S29),22(I2S30)/33,22 - INSTANCE MEMORY: 16(I2),0(I4),8(I1)/- -RTPS Operation ACK_CACHE_CHANGE SN 29 -RTPS Operation ACK_CACHE_CHANGE SN 30 -DDS Operation WRITE [TS 32s, Instance 2, Aligned Payload] (ACCEPTED) - SAMPLE MEMORY: 0(I1S26),36(I2S30),18(I2S32)/9,27 - PAYLOAD MEMORY: 0(I1S26),22(I2S30),33(I2S32)/11,22 - INSTANCE MEMORY: 16(I2),0(I4),8(I1)/- \ No newline at end of file diff --git a/src/Tests/Level_0/L0_dds_writer_test1_lik.vhd b/src/Tests/Level_0/L0_dds_writer_test1_lik.vhd deleted file mode 100644 index f5d5b09..0000000 --- a/src/Tests/Level_0/L0_dds_writer_test1_lik.vhd +++ /dev/null @@ -1,1868 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library osvvm; -- Utility Library -context osvvm.OsvvmContext; - -use work.rtps_package.all; -use work.user_config.all; -use work.rtps_config_package.all; -use work.rtps_test_package.all; - --- This testbench tests the General Operation of the DDS Writer. It tests the correctness of the RTPS --- GET_MIN_SN, GET_MAX_SN, GET_CACHE_CHANGE, REMOVE_CACHE_CHANGE, ACK_CACHE_CHANGE, and NACK_CACHE_CHANGE Operations and the --- DDS REGISTER_INSTANCE, UNREGISTER_INSTANCE, WRITE, DISPOSE, and LOOKUP_INSTANCE Operations. --- More specifically the testbench covers following tests: --- TEST: GET_MIN_SN/GET_MAX_SN ON EMPTY --- TEST: GET_MIN_SN/GET_MAX_SN ON 1 SAMPLE --- TEST: GET_MIN_SN/GET_MAX_SN ON >1 SAMPLE --- TEST: ADD SAMPLE WITH KEY_HASH [UNKNOWN INSTANCE] --- TEST: ADD SAMPLE WITH KEY_HASH [KNOWN INSTANCE] --- TEST: ADD SAMPLE WITH HANDLE_NIL [UNKNOWN INSTANCE] --- TEST: ADD SAMPLE WITH HANDLE_NIL [KNOWN INSTANCE] --- TEST: NORMAL WRITE --- TEST: WRITE ON PAYLOAD MEMORY FULL [WITHOUT ACKed SAMPLES] --- TEST: WRITE ON PAYLOAD MEMORY FULL [WITH ACKed SAMPLES] --- TEST: WRITE ON DISPOSED INSTANCE --- TEST: WRITE ON UNREGISTERED INSTANCE --- TEST: WRITE ALIGNED PAYLOAD --- TEST: WRITE UNALIGNED PAYLOAD [>1 SLOT] --- TEST: WRITE UNALIGNED PAYLOAD [<1 SLOT] --- TEST: NORMAL REGISTER --- TEST: REGISTER INSTANCE [KNOWN INSTANCE] --- TEST: REGISTER INSTANCE ON MAX_INSTANCES [UNKNOWN INSTANCE, WITHOUT STALE INSTANCE] --- TEST: REGISTER INSTANCE ON MAX_INSTANCES [UNKNOWN INSTANCE, WITH STALE INSTANCE] --- TEST: REGISTER ON UNREGISTERED INSTANCE --- TEST: NORMAL DISPOSE --- TEST: DISPOSE ON PAYLOAD MEMORY FULL [WITHOUT ACKed SAMPLES] --- TEST: DISPOSE ON PAYLOAD MEMORY FULL [WITH ACKed SAMPLES] --- TEST: DISPOSE ON UNREGISTERED INSTANCE --- TEST: GET_CACHE_CHANGE [UNKNOWN SN] --- TEST: GET_CACHE_CHANGE [KNOWN SN, ALIGNED PAYLOAD] --- TEST: GET_CACHE_CHANGE [KNOWN SN, UNALIGNED PAYLOAD, >1 SLOT] --- TEST: GET_CACHE_CHANGE [KNOWN SN, UNALIGNED PAYLOAD, <1 SLOT] --- TEST: NORMAL ACK_CACHE_CHANGE --- TEST: ACK_CACHE_CHANGE [ALREADY ACKed SN] --- TEST: NORMAL NACK_CACHE_CHANGE --- TEST: REMOVE_CACHE_CHANGE [UNKNOWN SN] --- TEST: REMOVE_CACHE_CHANGE [KNOWN SN] --- TEST: NORMAL UNREGISTER --- TEST: UNREGISTER INSTANCE ON PAYLOAD MEMORY FULL [WITHOUT ACKed SAMPLES] --- TEST: UNREGISTER INSTANCE ON PAYLOAD MEMORY FULL [WITH ACKed SAMPLES] --- TEST: UNREGISTER ON DISPOSED INSTANCE --- TEST: UNREGISTER UNKNOWN INSTANCE --- TEST: REMOVE STALE INSTANCE WITH 0 SAMPLES --- TEST: REMOVE STALE INSTANCE WITH 1 SAMPLES --- TEST: REMOVE STALE INSTANCE WITH >1 SAMPLES --- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKNOWN INSTANCE, WITH STALE INSTANCE] --- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKNOWN INSTANCE, WITHOUT STALE INSTANCES] --- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKNOWN INSTANCE, WITH FULLY ACKed INSTANCE, WITHOUT STALE INSTANCE] --- TEST: ADD SAMPLE ON MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE, WITHOUT ACKed SAMPLES] --- TEST: ADD SAMPLE ON MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE, WITH ACKed SAMPLES, WITHOUT ACKed INSTANCE SAMPLES] --- TEST: ADD SAMPLE ON MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE, WITH ACKed INSTANCE SAMPLE] --- TEST: ADD SAMPLE ON MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE, WITH ACKed INSTANCE SAMPLES(>1)] --- TEST: ADD SAMPLE ON MAX_SAMPLES [KNOWN INSTANCE,WITHOUT ACKed SAMPLES] --- TEST: ADD SAMPLE ON MAX_SAMPLES [KNOWN INSTANCE,WITH ACKed SAMPLE] --- TEST: ADD SAMPLE ON MAX_SAMPLES [KNOWN INSTANCE,WITH ACKed SAMPLES (>1)] --- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE,WITHOUT ACKed SAMPLES] --- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE,WITH ACKed SAMPLES, WITHOUT ACKed INSTANCE SAMPLES] --- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE,WITH ACKed INSTANCE SAMPLES] --- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE,WITH STALE INSTANCE, WITHOUT ACKed SAMPLE] --- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE,WITHOUT STALE INSTANCES,WITHOUT ACKed SAMPLES] --- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE,WITHOUT STALE INSTANCE, WITH ACKed SAMPLE] --- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE,WITH STALE INSTANCE (>0 SAMPLES)] --- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE,WITH STALE INSTANCE, WITH ACKed SAMPLE] --- TEST: ADD SAMPLE ON PAYLOAD FULL & MAX_INSTANCES [UNKNOWN INSTANCE,WITH ACKed SAMPLES,WITH STALE INSTANCE (>= 1 SAMPLE)] (Induce Double Remove) --- TEST: ADD SAMPLE BIGGER THAN AVAILABLE MEMORY SPACE [WITH ACKed SAMPLES] --- TEST: INSTANCE LOOKUP [KNOWN INSTANCE] --- TEST: INSTANCE LOOKUP [UNKNOWN INSTANCE] - -entity L0_dds_writer_test1_lik is -end entity; - -architecture testbench of L0_dds_writer_test1_lik is - - -- *CONSTANT DECLARATION* - constant MAX_REMOTE_ENDPOINTS : natural := 3; - - -- *TYPE DECLARATION* - type DDS_STAGE_TYPE is (IDLE, START, PUSH, DONE); - type RTPS_STAGE_TYPE is (IDLE, START, DONE, CHECK); - - -- *SIGNAL DECLARATION* - signal clk : std_logic := '0'; - signal reset : std_logic := '1'; - signal check_time : TIME_TYPE := TIME_ZERO; - signal start_rtps, start_dds, ack_rtps, ack_dds, done_rtps, done_dds : std_logic := '0'; - signal opcode_rtps : HISTORY_CACHE_OPCODE_TYPE := NOP; - signal opcode_dds : DDS_WRITER_OPCODE_TYPE := NOP; - signal ret_rtps : HISTORY_CACHE_RESPONSE_TYPE := ERROR; - signal seq_nr_rtps, cc_seq_nr : SEQUENCENUMBER_TYPE := SEQUENCENUMBER_UNKNOWN; - signal ready_out_rtps, valid_out_rtps, last_word_out_rtps : std_logic := '0'; - signal ready_in_dds, ready_out_dds, valid_in_dds, valid_out_dds, last_word_in_dds, last_word_out_dds : std_logic := '0'; - signal data_out_rtps, data_in_dds, data_out_dds : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); - signal get_data_rtps, liveliness_assertion, data_available : std_logic := '0'; - signal cc_source_timestamp, source_ts_dds : TIME_TYPE := TIME_INVALID; - signal cc_kind : CACHE_CHANGE_KIND_TYPE := ALIVE; - signal cc_instance_handle, instance_handle_in_dds, instance_handle_out_dds : INSTANCE_HANDLE_TYPE := HANDLE_NIL; - signal max_wait_dds : DURATION_TYPE := DURATION_INFINITE; - signal return_code_dds : std_logic_vector(RETURN_CODE_WIDTH-1 downto 0) := (others => '0'); - signal status : std_logic_vector(STATUS_KIND_WIDTH-1 downto 0) := (others => '0'); - - signal dds_start, dds_done, rtps_start, rtps_done : std_logic := '0'; - signal dds_cnt, rtps_cnt : natural := 0; - signal dds_stage : DDS_STAGE_TYPE := IDLE; - signal rtps_stage : RTPS_STAGE_TYPE := IDLE; - shared variable dds : DDS_WRITER_TEST_TYPE := DEFAULT_DDS_WRITER_TEST; - shared variable rtps : RTPS_WRITER_TEST_TYPE := DEFAULT_RTPS_WRITER_TEST; - signal inst_id, kind_id, sn_id, ts_id, data_id, ret_id, ih_id : AlertLogIDType; - - -- *FUNCTION DECLARATION* - function extract_key_hash (payload : TEST_PACKET_TYPE) return INSTANCE_HANDLE_TYPE is - variable ret : INSTANCE_HANDLE_TYPE := HANDLE_NIL; - begin - for i in 0 to 3 loop - ret(i) := not payload.data(i); - end loop; - - return ret; - end function; - - function gen_sn(input : natural) return SEQUENCENUMBER_TYPE is - variable ret : SEQUENCENUMBER_TYPE; - begin - ret(0) := (others => '0'); - ret(1) := unsigned(int(input, WORD_WIDTH)); - return ret; - end function; - -begin - - -- Unit Under Test - uut : entity work.dds_writer(arch) - generic map( - HISTORY_QOS => KEEP_LAST_HISTORY_QOS, - DEADLINE_QOS => DURATION_INFINITE, - LIFESPAN_QOS => DURATION_INFINITE, - LEASE_DURATION => DURATION_INFINITE, - WITH_KEY => TRUE, - MAX_SAMPLES => std_logic_vector(to_unsigned(4,CDR_LONG_WIDTH)), - MAX_INSTANCES => std_logic_vector(to_unsigned(3,CDR_LONG_WIDTH)), - MAX_SAMPLES_PER_INSTANCE => std_logic_vector(to_unsigned(2,CDR_LONG_WIDTH)), - PAYLOAD_FRAME_SIZE => 11 - ) - port map ( - clk => clk, - reset => reset, - time => check_time, - start_rtps => start_rtps, - opcode_rtps => opcode_rtps, - ack_rtps => ack_rtps, - done_rtps => done_rtps, - ret_rtps => ret_rtps, - seq_nr_rtps => seq_nr_rtps, - get_data_rtps => get_data_rtps, - data_out_rtps => data_out_rtps, - valid_out_rtps => valid_out_rtps, - ready_out_rtps => ready_out_rtps, - last_word_out_rtps => last_word_out_rtps, - liveliness_assertion => liveliness_assertion, - data_available => data_available, - cc_instance_handle => cc_instance_handle, - cc_kind => cc_kind, - cc_source_timestamp => cc_source_timestamp, - cc_seq_nr => cc_seq_nr, - start_dds => start_dds, - ack_dds => ack_dds, - opcode_dds => opcode_dds, - instance_handle_in_dds => instance_handle_in_dds, - source_ts_dds => source_ts_dds, - max_wait_dds => max_wait_dds, - done_dds => done_dds, - return_code_dds => return_code_dds, - instance_handle_out_dds => instance_handle_out_dds, - ready_in_dds => ready_in_dds, - valid_in_dds => valid_in_dds, - data_in_dds => data_in_dds, - last_word_in_dds => last_word_in_dds, - ready_out_dds => ready_out_dds, - valid_out_dds => valid_out_dds, - data_out_dds => data_out_dds, - last_word_out_dds => last_word_out_dds, - status => status - ); - - stimulus_prc : process - variable RV : RandomPType; - variable kh1, kh2, kh3, kh4 : INSTANCE_HANDLE_TYPE := HANDLE_NIL; - variable cc1, cc2, cc3, cc4, cc : CACHE_CHANGE_TYPE := DEFAULT_CACHE_CHANGE; - - impure function gen_payload(key_hash : INSTANCE_HANDLE_TYPE; len : natural) return TEST_PACKET_TYPE is - variable ret : TEST_PACKET_TYPE := EMPTY_TEST_PACKET; - begin - assert (len >= 4) report "Payload length has to be at least 16 Bytes long" severity FAILURE; - - for i in 0 to len-1 loop - if (i < 4) then - -- NOTE: Beginning of payload is negated key to allow deterministic Key Hash generation from the kh_prc - ret.data(ret.length) := not key_hash(i); - else - ret.data(ret.length) := RV.RandSlv(WORD_WIDTH); - end if; - ret.length := ret.length + 1; - end loop; - ret.last(ret.length-1) := '1'; - - return ret; - end function; - - impure function gen_key_hash return KEY_HASH_TYPE is - variable ret : KEY_HASH_TYPE := KEY_HASH_NIL; - begin - for i in 0 to KEY_HASH_TYPE'length-1 loop - ret(i) := RV.RandSlv(WORD_WIDTH); - end loop; - return ret; - end function; - - procedure start_dds is - begin - dds_start <= '1'; - wait until rising_edge(clk); - dds_start <= '0'; - wait until rising_edge(clk); - end procedure; - - procedure start_rtps is - begin - rtps_start <= '1'; - wait until rising_edge(clk); - rtps_start <= '0'; - wait until rising_edge(clk); - end procedure; - - procedure wait_on_dds is - begin - if (dds_done /= '1') then - wait until dds_done = '1'; - end if; - end procedure; - - procedure wait_on_rtps is - begin - if (rtps_done /= '1') then - wait until rtps_done = '1'; - end if; - end procedure; - - procedure wait_on_completion is - begin - if (rtps_done /= '1' or dds_done /= '1') then - wait until rtps_done = '1' and dds_done = '1'; - end if; - end procedure; - - begin - - SetAlertLogName("L0_dds_writer_test1_lik - (KEEP ALL, Infinite Lifespan, Keyed) - General"); - SetAlertEnable(FAILURE, TRUE); - SetAlertEnable(ERROR, TRUE); - SetAlertEnable(WARNING, TRUE); - SetLogEnable(DEBUG, FALSE); - SetLogEnable(PASSED, FALSE); - SetLogEnable(INFO, TRUE); - RV.InitSeed(RV'instance_name); - inst_id <= GetAlertLogID("Instance", ALERTLOG_BASE_ID); - kind_id <= GetAlertLogID("Cache Change Kind", ALERTLOG_BASE_ID); - sn_id <= GetAlertLogID("SequenceNumber", ALERTLOG_BASE_ID); - ts_id <= GetAlertLogID("TimeStamp", ALERTLOG_BASE_ID); - ih_id <= GetAlertLogID("Instance Handle", ALERTLOG_BASE_ID); - data_id <= GetAlertLogID("Data Out", ALERTLOG_BASE_ID); - ret_id <= GetAlertLogID("Return Code", ALERTLOG_BASE_ID); - - -- Key Hashes - kh1 := gen_key_hash; - kh2 := gen_key_hash; - kh3 := gen_key_hash; - kh4 := gen_key_hash; - - - - Log("Initiating Test", INFO); - reset <= '1'; - wait until rising_edge(clk); - wait until rising_edge(clk); - reset <= '0'; - -- Stored CC: 0, 0, 0, 0 - - -- TEST: GET_MIN_SN/GET_MAX_SN ON EMPTY - - Log("RTPS Operation GET_MIN_SN (Expected SEQUENCENUMBER_UNKNOWN)", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_MIN_SN; - rtps.cc.seq_nr := SEQUENCENUMBER_UNKNOWN; - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_MAX_SN (Expected SEQUENCENUMBER_UNKNOWN)", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_MAX_SN; - rtps.cc.seq_nr := SEQUENCENUMBER_UNKNOWN; - start_rtps; - wait_on_rtps; - - -- TEST: ADD SAMPLE WITH KEY_HASH [UNKNOWN INSTANCE] - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh1; - cc.payload := gen_payload(kh1,10); - cc.seq_nr := gen_sn(1); - cc.src_timestamp := gen_duration(1,0); - - Log("DDS Operation WRITE [TS 1s, Instance 1, Aligned Payload] (REJECTED: Instance not Registered)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.ret_code := RETCODE_BAD_PARAMETER; - start_dds; - wait_on_dds; - - -- TEST: ADD SAMPLE WITH HANDLE_NIL [UNKNOWN INSTANCE] - -- TEST: NORMAL WRITE - -- TEST: WRITE ALIGNED PAYLOAD - - Log("DDS Operation WRITE [TS 1s, Instance 1, HANDLE_NIL, Aligned Payload] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.cc.instance:= HANDLE_NIL; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc1 := cc; - -- Stored CC: I1S1, 0, 0, 0 - - -- TEST: GET_MIN_SN/GET_MAX_SN ON 1 SAMPLE - - Log("RTPS Operation GET_MIN_SN (Expected SN 1)", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_MIN_SN; - rtps.cc.seq_nr := gen_sn(1); - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_MAX_SN (Expected SN 1)", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_MAX_SN; - rtps.cc.seq_nr := gen_sn(1); - start_rtps; - wait_on_rtps; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh1; - cc.payload := gen_payload(kh1,18); - cc.seq_nr := gen_sn(2); - cc.src_timestamp := gen_duration(2,0); - - -- TEST: ADD SAMPLE WITH KEY_HASH [KNOWN INSTANCE] - -- TEST: WRITE UNALIGNED PAYLOAD [>1 SLOT] - - Log("DDS Operation WRITE [TS 2s, Instance 1, Unaligned Payload (2 Slot)] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc2 := cc; - -- Stored CC: I1S1, I1S2, 0, 0 - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_DISPOSED; - cc.instance := kh2; - cc.payload := gen_payload(kh2,5); - cc.seq_nr := gen_sn(3); - cc.src_timestamp := gen_duration(3,0); - - Log("DDS Operation DISPOSE [TS 3s, Instance 2] (REJECTED: Instance not Registered)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := DISPOSE; - dds.cc := cc; - dds.ret_code := RETCODE_BAD_PARAMETER; - start_dds; - wait_on_dds; - - -- TEST: NORMAL REGISTER - - Log("DDS Operation REGISTER_INSTANCE 2 (ACCEPTED)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := REGISTER_INSTANCE; - dds.cc := cc; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - - -- TEST: NORMAL DISPOSE - -- TEST: WRITE UNALIGNED PAYLOAD [<1 SLOT] - - Log("DDS Operation DISPOSE [TS 3s, Instance 2] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := DISPOSE; - dds.cc := cc; - dds.cc.instance:= HANDLE_NIL; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc3 := cc; - -- Stored CC: I1S1, I1S2, I2S3, 0 - - -- TEST: GET_MIN_SN/GET_MAX_SN ON >1 SAMPLE - -- VALIDATE STATE - - Log("RTPS Operation GET_MIN_SN (Expected SN 1)", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_MIN_SN; - rtps.cc.seq_nr := gen_sn(1); - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_MAX_SN (Expected SN 3)", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_MAX_SN; - rtps.cc.seq_nr := gen_sn(3); - start_rtps; - wait_on_rtps; - - -- TEST: GET_CACHE_CHANGE [UNKNOWN SN] - - Log("RTPS Operation GET_CACHE_CHANGE SN 4 (Invalid)", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_CACHE_CHANGE; - rtps.cc.seq_nr := gen_sn(4); - rtps.ret_code := INVALID; - start_rtps; - wait_on_rtps; - - -- TEST: GET_CACHE_CHANGE [KNOWN SN, ALIGNED PAYLOAD] - - Log("RTPS Operation GET_CACHE_CHANGE SN 1", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_CACHE_CHANGE; - rtps.cc := cc1; - start_rtps; - wait_on_rtps; - - -- TEST: GET_CACHE_CHANGE [KNOWN SN, UNALIGNED PAYLOAD, >1 SLOT] - - Log("RTPS Operation GET_CACHE_CHANGE SN 2", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_CACHE_CHANGE; - rtps.cc := cc2; - start_rtps; - wait_on_rtps; - - -- TEST: GET_CACHE_CHANGE [KNOWN SN, UNALIGNED PAYLOAD, <1 SLOT] - - Log("RTPS Operation GET_CACHE_CHANGE SN 3", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_CACHE_CHANGE; - rtps.cc := cc3; - start_rtps; - wait_on_rtps; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh2; - cc.payload := gen_payload(kh2,10); - cc.seq_nr := gen_sn(4); - cc.src_timestamp := gen_duration(4,0); - - -- TEST: WRITE ON DISPOSED INSTANCE - -- TEST: ADD SAMPLE WITH HANDLE_NIL [KNOWN INSTANCE] - - Log("DDS Operation WRITE [TS 4s, Instance 2, Aligned Payload] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.cc.instance:= HANDLE_NIL; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc4 := cc; - -- Stored CC: I1S1, I1S2, I2S3, I2S4 - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh3; - cc.payload := gen_payload(kh3,10); - cc.seq_nr := gen_sn(5); - cc.src_timestamp := gen_duration(5,0); - - -- TEST: WRITE ON PAYLOAD MEMORY FULL [WITHOUT ACKed SAMPLES] - - Log("DDS Operation WRITE [TS 5s, Instance 3, HANDLE_NIL, Aligned Payload] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.cc.instance:= HANDLE_NIL; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc1 := cc; - -- Stored CC: I3S5, I1S2, I2S3, I2S4 - - -- TEST: NORMAL ACK_CACHE_CHANGE - - Log("RTPS Operation ACK_CACHE_CHANGE SN 3", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := ACK_CACHE_CHANGE; - rtps.cc := cc3; - start_rtps; - wait_on_rtps; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh3; - cc.payload := gen_payload(kh3,10); - cc.seq_nr := gen_sn(6); - cc.src_timestamp := gen_duration(6,0); - - -- TEST: WRITE ON PAYLOAD MEMORY FULL [WITH ACKed SAMPLES] - - Log("DDS Operation WRITE [TS 6s, Instance 3, Aligned Payload] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc3 := cc; - -- Stored CC: I3S5, I1S2, I3S6, I2S4 - - -- VALIDATE STATE - - Log("RTPS Operation GET_MIN_SN (Expected SN 2)", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_MIN_SN; - rtps.cc.seq_nr := gen_sn(2); - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_MAX_SN (Expected SN 6)", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_MAX_SN; - rtps.cc.seq_nr := gen_sn(6); - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_CACHE_CHANGE SN 2", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_CACHE_CHANGE; - rtps.cc := cc2; - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_CACHE_CHANGE SN 4", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_CACHE_CHANGE; - rtps.cc := cc4; - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_CACHE_CHANGE SN 5", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_CACHE_CHANGE; - rtps.cc := cc1; - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_CACHE_CHANGE SN 6", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_CACHE_CHANGE; - rtps.cc := cc3; - start_rtps; - wait_on_rtps; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_DISPOSED; - cc.instance := kh1; - cc.payload := gen_payload(kh1,5); - cc.seq_nr := gen_sn(7); - cc.src_timestamp := gen_duration(7,0); - - -- TEST: DISPOSE ON PAYLOAD MEMORY FULL [WITHOUT ACKed SAMPLES] - - Log("DDS Operation DISPOSE [TS 7s, Instance 1] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := DISPOSE; - dds.cc := cc; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc2 := cc; - -- Stored CC: I3S5, I1S7, I3S6, I2S4 - - Log("RTPS Operation ACK_CACHE_CHANGE SN 5", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := ACK_CACHE_CHANGE; - rtps.cc := cc1; - start_rtps; - wait_on_rtps; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh2; - cc.payload := gen_payload(kh2,20); - cc.seq_nr := gen_sn(8); - cc.src_timestamp := gen_duration(8,0); - - -- TEST: ADD SAMPLE BIGGER THAN AVAILABLE MEMORY SPACE [WITH ACKed SAMPLES] - - Log("DDS Operation WRITE [TS 8s, Instance 2, Aligned Payload (2 Slots)] (REJECTED: Payload Memory Full)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.ret_code := RETCODE_OUT_OF_RESOURCES; - start_dds; - wait_on_dds; - - -- TEST: REMOVE_CACHE_CHANGE [UNKNOWN SN] - - Log("RTPS Operation REMOVE_CACHE_CHANGE SN 3 (Invalid)", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := REMOVE_CACHE_CHANGE; - rtps.cc.seq_nr := gen_sn(3); - rtps.ret_code := INVALID; - start_rtps; - wait_on_rtps; - - -- TEST: REMOVE_CACHE_CHANGE [KNOWN SN] - - Log("RTPS Operation REMOVE_CACHE_CHANGE SN 5", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := REMOVE_CACHE_CHANGE; - rtps.cc := cc1; - start_rtps; - wait_on_rtps; - -- Stored CC: 0, I1S7, I3S6, I2S4 - - Log("DDS Operation WRITE [TS 8s, Instance 2, Aligned Payload (2 Slots)] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc1 := cc; - -- Stored CC: I2S8, I1S7, I3S6, I2S4 - - Log("RTPS Operation ACK_CACHE_CHANGE SN 7", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := ACK_CACHE_CHANGE; - rtps.cc := cc2; - start_rtps; - wait_on_rtps; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_DISPOSED; - cc.instance := kh3; - cc.payload := gen_payload(kh3,5); - cc.seq_nr := gen_sn(9); - cc.src_timestamp := gen_duration(9,0); - - -- TEST: DISPOSE ON PAYLOAD MEMORY FULL [WITH ACKed SAMPLES] - - Log("DDS Operation DISPOSE [TS 9s, Instance 3] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := DISPOSE; - dds.cc := cc; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc2 := cc; - -- Stored CC: I2S8, I3S9, I3S6, I2S4 - - -- VALIDATE STATE - - Log("RTPS Operation GET_MIN_SN (Expected SN 4)", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_MIN_SN; - rtps.cc.seq_nr := gen_sn(4); - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_MAX_SN (Expected SN 9)", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_MAX_SN; - rtps.cc.seq_nr := gen_sn(9); - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_CACHE_CHANGE SN 4", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_CACHE_CHANGE; - rtps.cc := cc4; - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_CACHE_CHANGE SN 6", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_CACHE_CHANGE; - rtps.cc := cc3; - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_CACHE_CHANGE SN 8", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_CACHE_CHANGE; - rtps.cc := cc1; - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_CACHE_CHANGE SN 9", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_CACHE_CHANGE; - rtps.cc := cc2; - start_rtps; - wait_on_rtps; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_UNREGISTERED; - cc.instance := kh1; - cc.payload := gen_payload(kh1,5); - cc.seq_nr := gen_sn(10); - cc.src_timestamp := gen_duration(10,0); - - -- TEST: UNREGISTER ON DISPOSED INSTANCE - -- TEST: UNREGISTER INSTANCE ON PAYLOAD MEMORY FULL [WITHOUT ACKed SAMPLES] - - Log("DDS Operation UNREGISTER_INSTANCE [TS 10s, Instance 1] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := UNREGISTER_INSTANCE; - dds.cc := cc; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc4 := cc; - -- Stored CC: I2S8, I3S9, I3S6, I1S10 - - Log("RTPS Operation ACK_CACHE_CHANGE SN 9", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := ACK_CACHE_CHANGE; - rtps.cc := cc2; - start_rtps; - wait_on_rtps; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_UNREGISTERED; - cc.instance := kh2; - cc.payload := gen_payload(kh2,5); - cc.seq_nr := gen_sn(11); - cc.src_timestamp := gen_duration(11,0); - - -- TEST: UNREGISTER INSTANCE ON PAYLOAD MEMORY FULL [WITH ACKed SAMPLES] - - Log("DDS Operation UNREGISTER_INSTANCE [TS 11s, Instance 2] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := UNREGISTER_INSTANCE; - dds.cc := cc; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc2 := cc; - -- Stored CC: I2S8, I2S11, I3S6, I1S10 - - Log("RTPS Operation ACK_CACHE_CHANGE SN 6", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := ACK_CACHE_CHANGE; - rtps.cc := cc3; - start_rtps; - wait_on_rtps; - - Log("RTPS Operation ACK_CACHE_CHANGE SN 8", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := ACK_CACHE_CHANGE; - rtps.cc := cc1; - start_rtps; - wait_on_rtps; - - Log("RTPS Operation ACK_CACHE_CHANGE SN 11", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := ACK_CACHE_CHANGE; - rtps.cc := cc2; - start_rtps; - wait_on_rtps; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh4; - cc.payload := gen_payload(kh4,10); - cc.seq_nr := gen_sn(12); - cc.src_timestamp := gen_duration(12,0); - - -- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKNOWN INSTANCE, WITH STALE INSTANCE] - -- TEST: ADD SAMPLE ON PAYLOAD FULL & MAX_INSTANCES [UNKNOWN INSTANCE,WITH ACKed SAMPLES,WITH STALE INSTANCE (>= 1 SAMPLE)] (Induce Double Remove) - -- TEST: REMOVE STALE INSTANCE WITH >1 SAMPLES - - Log("DDS Operation WRITE [TS 12s, Instance 4, HANDLE_NIL, Aligned Payload] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.cc.instance:= HANDLE_NIL; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc1 := cc; - -- Stored CC: I4S12, 0, 0, I1S10 - - -- VALIDATE STATE - - Log("RTPS Operation GET_MIN_SN (Expected SN 10)", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_MIN_SN; - rtps.cc.seq_nr := gen_sn(10); - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_MAX_SN (Expected SN 12)", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_MAX_SN; - rtps.cc.seq_nr := gen_sn(12); - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_CACHE_CHANGE SN 10", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_CACHE_CHANGE; - rtps.cc := cc4; - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_CACHE_CHANGE SN 12", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_CACHE_CHANGE; - rtps.cc := cc1; - start_rtps; - wait_on_rtps; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh2; - cc.payload := gen_payload(kh2,10); - cc.seq_nr := gen_sn(13); - cc.src_timestamp := gen_duration(13,0); - - -- TEST: REGISTER INSTANCE ON MAX_INSTANCES [UNKNOWN INSTANCE, WITHOUT STALE INSTANCE] - - Log("DDS Operation REGISTER_INSTANCE 2 (REJECTED: MAX_INSTANCES exceeded)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := REGISTER_INSTANCE; - dds.cc := cc; - dds.cc.instance:= HANDLE_NIL; - start_dds; - wait_on_dds; - - Log("RTPS Operation ACK_CACHE_CHANGE SN 10", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := ACK_CACHE_CHANGE; - rtps.cc := cc4; - start_rtps; - wait_on_rtps; - - -- TEST: REGISTER INSTANCE ON MAX_INSTANCES [UNKNOWN INSTANCE, WITH STALE INSTANCE] - -- TEST: REMOVE STALE INSTANCE WITH 1 SAMPLES - - Log("DDS Operation REGISTER_INSTANCE 2 (ACCEPTED)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := REGISTER_INSTANCE; - dds.cc := cc; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - -- Stored CC: I4S12, 0, 0, 0 - - Log("DDS Operation WRITE [TS 13s, Instance 2, Aligned Payload] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc2 := cc; - -- Stored CC: I4S12, I2S13, 0, 0 - - -- TEST: REGISTER INSTANCE [KNOWN INSTANCE] - - Log("DDS Operation REGISTER_INSTANCE 2 (ACCEPTED)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := REGISTER_INSTANCE; - dds.cc := cc; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh2; - cc.payload := gen_payload(kh2,10); - cc.seq_nr := gen_sn(14); - cc.src_timestamp := gen_duration(14,0); - - Log("DDS Operation WRITE [TS 14s, Instance 2, Aligned Payload] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc3 := cc; - -- Stored CC: I4S12, I2S13, I2S14, 0 - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh2; - cc.payload := gen_payload(kh2,10); - cc.seq_nr := gen_sn(15); - cc.src_timestamp := gen_duration(15,0); - - -- TEST: ADD SAMPLE ON MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE, WITHOUT ACKed SAMPLES] - - Log("DDS Operation WRITE [TS 15s, Instance 2, Aligned Payload] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc2 := cc; - -- Stored CC: I4S12, I2S15, I2S14, 0 - - Log("RTPS Operation ACK_CACHE_CHANGE SN 15", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := ACK_CACHE_CHANGE; - rtps.cc := cc2; - start_rtps; - wait_on_rtps; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh2; - cc.payload := gen_payload(kh2,10); - cc.seq_nr := gen_sn(16); - cc.src_timestamp := gen_duration(16,0); - - -- TEST: ADD SAMPLE ON MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE, WITH ACKed INSTANCE SAMPLE] - - Log("DDS Operation WRITE [TS 16s, Instance 2, Aligned Payload] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc2 := cc; - -- Stored CC: I4S12, I2S16, I2S14, 0 - - Log("RTPS Operation ACK_CACHE_CHANGE SN 12", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := ACK_CACHE_CHANGE; - rtps.cc := cc1; - start_rtps; - wait_on_rtps; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_UNREGISTERED; - cc.instance := kh2; - cc.payload := gen_payload(kh2,5); - cc.seq_nr := gen_sn(17); - cc.src_timestamp := gen_duration(17,0); - - -- TEST: NORMAL UNREGISTER - -- TEST: ADD SAMPLE ON MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE, WITH ACKed SAMPLES, WITHOUT ACKed INSTANCE SAMPLES] - - Log("DDS Operation UNREGISTER_INSTANCE [TS 17s, Instance 2] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := UNREGISTER_INSTANCE; - dds.cc := cc; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc3 := cc; - -- Stored CC: I4S12, I2S16, I2S17, 0 - - -- VALIDATE STATE - - Log("RTPS Operation GET_MIN_SN (Expected SN 12)", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_MIN_SN; - rtps.cc.seq_nr := gen_sn(12); - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_MAX_SN (Expected SN 17)", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_MAX_SN; - rtps.cc.seq_nr := gen_sn(17); - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_CACHE_CHANGE SN 12", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_CACHE_CHANGE; - rtps.cc := cc1; - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_CACHE_CHANGE SN 16", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_CACHE_CHANGE; - rtps.cc := cc2; - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_CACHE_CHANGE SN 17", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_CACHE_CHANGE; - rtps.cc := cc3; - start_rtps; - wait_on_rtps; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_UNREGISTERED; - cc.instance := kh4; - cc.payload := gen_payload(kh4,5); - cc.seq_nr := gen_sn(18); - cc.src_timestamp := gen_duration(18,0); - - Log("DDS Operation UNREGISTER_INSTANCE [TS 18s, Instance 4] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := UNREGISTER_INSTANCE; - dds.cc := cc; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc4 := cc; - -- Stored CC: I4S12, I2S16, I2S17, I4S18 - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_UNREGISTERED; - cc.instance := kh3; - cc.payload := gen_payload(kh3,5); - cc.seq_nr := gen_sn(19); - cc.src_timestamp := gen_duration(19,0); - - -- TEST: NORMAL NACK_CACHE_CHANGE - - Log("RTPS Operation NACK_CACHE_CHANGE SN 12", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := NACK_CACHE_CHANGE; - rtps.cc := cc1; - start_rtps; - wait_on_rtps; - - Log("RTPS Operation ACK_CACHE_CHANGE SN 18", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := ACK_CACHE_CHANGE; - rtps.cc := cc4; - start_rtps; - wait_on_rtps; - - -- TEST: ADD SAMPLE ON MAX_SAMPLES [KNOWN INSTANCE,WITH ACKed SAMPLE] - - Log("DDS Operation UNREGISTER_INSTANCE [TS 19s, Instance 3] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := UNREGISTER_INSTANCE; - dds.cc := cc; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc4 := cc; - -- Stored CC: I4S12, I2S16, I2S17, I3S19 - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh3; - cc.payload := gen_payload(kh3,10); - cc.seq_nr := gen_sn(20); - cc.src_timestamp := gen_duration(20,0); - - -- TEST: ADD SAMPLE ON MAX_SAMPLES [KNOWN INSTANCE,WITHOUT ACKed SAMPLES] - -- TEST: WRITE ON UNREGISTERED INSTANCE - - Log("DDS Operation WRITE [TS 20s, Instance 3, Aligned Payload] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc1 := cc; - -- Stored CC: I3S20, I2S16, I2S17, I3S19 - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh3; - cc.payload := gen_payload(kh3,10); - cc.seq_nr := gen_sn(21); - cc.src_timestamp := gen_duration(21,0); - - -- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE,WITHOUT ACKed SAMPLES] - - Log("DDS Operation WRITE [TS 21s, Instance 3, Aligned Payload] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc4 := cc; - -- Stored CC: I3S20, I2S16, I2S17, I3S21 - - Log("RTPS Operation ACK_CACHE_CHANGE SN 16", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := ACK_CACHE_CHANGE; - rtps.cc := cc2; - start_rtps; - wait_on_rtps; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh3; - cc.payload := gen_payload(kh3,10); - cc.seq_nr := gen_sn(22); - cc.src_timestamp := gen_duration(22,0); - - -- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE,WITH ACKed SAMPLES, WITHOUT ACKed INSTANCE SAMPLES] - - Log("DDS Operation WRITE [TS 22s, Instance 3, Aligned Payload] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc1 := cc; - -- Stored CC: I3S22, I2S16, I2S17, I3S21 - - Log("RTPS Operation ACK_CACHE_CHANGE SN 22", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := ACK_CACHE_CHANGE; - rtps.cc := cc1; - start_rtps; - wait_on_rtps; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh3; - cc.payload := gen_payload(kh3,10); - cc.seq_nr := gen_sn(23); - cc.src_timestamp := gen_duration(23,0); - - -- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE,WITH ACKed INSTANCE SAMPLES] - - Log("DDS Operation WRITE [TS 23s, Instance 3, Aligned Payload] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc1 := cc; - -- Stored CC: I3S23, I2S16, I2S17, I3S21 - - -- VALIDATE STATE - - Log("RTPS Operation GET_MIN_SN (Expected SN 16)", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_MIN_SN; - rtps.cc.seq_nr := gen_sn(16); - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_MAX_SN (Expected SN 23)", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_MAX_SN; - rtps.cc.seq_nr := gen_sn(23); - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_CACHE_CHANGE SN 21", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_CACHE_CHANGE; - rtps.cc := cc4; - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_CACHE_CHANGE SN 22", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_CACHE_CHANGE; - rtps.cc.seq_nr := gen_sn(22); - rtps.ret_code := INVALID; - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_CACHE_CHANGE SN 23", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_CACHE_CHANGE; - rtps.cc := cc1; - start_rtps; - wait_on_rtps; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_UNREGISTERED; - cc.instance := kh1; - cc.payload := gen_payload(kh1,5); - cc.seq_nr := gen_sn(24); - cc.src_timestamp := gen_duration(24,0); - - -- TEST: UNREGISTER UNKNOWN INSTANCE - - Log("DDS Operation UNREGISTER_INSTANCE [TS 24s, HANDLE_NIL, Instance 1] (IGNORED: Instance not Registered)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := UNREGISTER_INSTANCE; - dds.cc := cc; - dds.cc.instance:= HANDLE_NIL; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh1; - cc.payload := gen_payload(kh1,10); - cc.seq_nr := gen_sn(24); - cc.src_timestamp := gen_duration(24,0); - - -- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE,WITH STALE INSTANCE, WITHOUT ACKed SAMPLE] - -- TEST: REMOVE STALE INSTANCE WITH 0 SAMPLES - - Log("DDS Operation WRITE [TS 24s, Instance 1, HANDLE_NIL, Aligned Payload] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.cc.instance:= HANDLE_NIL; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc2 := cc; - -- Stored CC: I3S23, I1S24, I2S17, I3S21 - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh4; - cc.payload := gen_payload(kh4,10); - cc.seq_nr := gen_sn(25); - cc.src_timestamp := gen_duration(25,0); - - -- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE,WITHOUT STALE INSTANCES,WITHOUT ACKed SAMPLES] - - Log("DDS Operation WRITE [TS 25s, Instance 4, HANDLE_NIL Aligned Payload] (REJECTED: MAX_INSTANCES exceeded)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.cc.instance:= HANDLE_NIL; - dds.ret_code := RETCODE_OUT_OF_RESOURCES; - start_dds; - wait_on_dds; - - Log("RTPS Operation ACK_CACHE_CHANGE SN 21", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := ACK_CACHE_CHANGE; - rtps.cc := cc4; - start_rtps; - wait_on_rtps; - - -- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE,WITHOUT STALE INSTANCE, WITH ACKed SAMPLE] - - Log("DDS Operation WRITE [TS 25s, Instance 4, HANDLE_NIL, Aligned Payload] (REJECTED: MAX_INSTANCES exceeded)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.cc.instance:= HANDLE_NIL; - dds.ret_code := RETCODE_OUT_OF_RESOURCES; - start_dds; - wait_on_dds; - - Log("RTPS Operation ACK_CACHE_CHANGE SN 17", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := ACK_CACHE_CHANGE; - rtps.cc := cc3; - start_rtps; - wait_on_rtps; - - -- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE,WITH STALE INSTANCE (>0 SAMPLES)] - -- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE,WITH STALE INSTANCE, WITH ACKed SAMPLE] - - Log("DDS Operation WRITE [TS 25s, Instance 4, HANDLE_NIL, Aligned Payload] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.cc.instance:= HANDLE_NIL; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc3 := cc; - -- Stored CC: I3S23, I1S24, I4S25, I3S21 - - -- TEST: ACK_CACHE_CHANGE [ALREADY ACKed SN] - - Log("RTPS Operation ACK_CACHE_CHANGE SN 21", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := ACK_CACHE_CHANGE; - rtps.cc := cc4; - start_rtps; - wait_on_rtps; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh2; - cc.payload := gen_payload(kh2,10); - cc.seq_nr := gen_sn(26); - cc.src_timestamp := gen_duration(26,0); - - -- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKNOWN INSTANCE, WITHOUT STALE INSTANCES] - - Log("DDS Operation WRITE [TS 26s, Instance 2, HANDLE_NIL, Aligned Payload] (REJECTED: MAX_INSTANCES exceeded)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.cc.instance:= HANDLE_NIL; - dds.ret_code := RETCODE_OUT_OF_RESOURCES; - start_dds; - wait_on_dds; - - Log("RTPS Operation ACK_CACHE_CHANGE SN 24", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := ACK_CACHE_CHANGE; - rtps.cc := cc2; - start_rtps; - wait_on_rtps; - - -- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKNOWN INSTANCE, WITH FULLY ACKed INSTANCE, WITHOUT STALE INSTANCE] - - Log("DDS Operation WRITE [TS 26s, Instance 2, HANDLE_NIL, Aligned Payload] (REJECTED: MAX_INSTANCES exceeded)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.cc.instance:= HANDLE_NIL; - dds.ret_code := RETCODE_OUT_OF_RESOURCES; - start_dds; - wait_on_dds; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_UNREGISTERED; - cc.instance := kh1; - cc.payload := gen_payload(kh1,5); - cc.seq_nr := gen_sn(26); - cc.src_timestamp := gen_duration(26,0); - - Log("DDS Operation UNREGISTER_INSTANCE [TS 26s, Instance 1] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := UNREGISTER_INSTANCE; - dds.cc := cc; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc4 := cc; - -- Stored CC: I3S23, I1S24, I4S25, I1S26 - - Log("RTPS Operation ACK_CACHE_CHANGE SN 26", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := ACK_CACHE_CHANGE; - rtps.cc := cc2; - start_rtps; - wait_on_rtps; - - -- TEST: REGISTER ON UNREGISTERED INSTANCE - - Log("DDS Operation REGISTER_INSTANCE 1 (ACCEPTED)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := REGISTER_INSTANCE; - dds.cc := cc; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh2; - cc.payload := gen_payload(kh2,10); - cc.seq_nr := gen_sn(27); - cc.src_timestamp := gen_duration(27,0); - - Log("DDS Operation WRITE [TS 27s, Instance 2, HANDLE_NIL, Aligned Payload] (REJECTED: MAX_INSTANCES exceeded)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.cc.instance:= HANDLE_NIL; - dds.ret_code := RETCODE_OUT_OF_RESOURCES; - start_dds; - wait_on_dds; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_UNREGISTERED; - cc.instance := kh3; - cc.payload := gen_payload(kh3,5); - cc.seq_nr := gen_sn(27); - cc.src_timestamp := gen_duration(27,0); - - Log("DDS Operation UNREGISTER_INSTANCE [TS 27s, Instance 3] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := UNREGISTER_INSTANCE; - dds.cc := cc; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc2 := cc; - -- Stored CC: I3S23, I3S27, I4S25, I1S26 - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_DISPOSED; - cc.instance := kh3; - cc.payload := gen_payload(kh3,5); - cc.seq_nr := gen_sn(28); - cc.src_timestamp := gen_duration(28,0); - - -- TEST: DISPOSE ON UNREGISTERED INSTANCE - - Log("DDS Operation DISPOSE [TS 28s, Instance 3] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := DISPOSE; - dds.cc := cc; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc1 := cc; - -- Stored CC: I3S28, I3S27, I4S25, I1S26 - - Log("RTPS Operation ACK_CACHE_CHANGE SN 27", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := ACK_CACHE_CHANGE; - rtps.cc := cc2; - start_rtps; - wait_on_rtps; - - Log("RTPS Operation ACK_CACHE_CHANGE SN 28", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := ACK_CACHE_CHANGE; - rtps.cc := cc1; - start_rtps; - wait_on_rtps; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh2; - cc.payload := gen_payload(kh2,10); - cc.seq_nr := gen_sn(29); - cc.src_timestamp := gen_duration(29,0); - - Log("DDS Operation WRITE [TS 29s, Instance 2, HANDLE_NIL, Aligned Payload] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.cc.instance:= HANDLE_NIL; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc1 := cc; - -- Stored CC: I2S29, 0, I4S25, I1S26 - - -- VALIDATE STATE - - Log("RTPS Operation GET_MIN_SN (Expected SN 25)", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_MIN_SN; - rtps.cc.seq_nr := gen_sn(25); - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_MAX_SN (Expected SN 28)", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_MAX_SN; - rtps.cc.seq_nr := gen_sn(29); - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_CACHE_CHANGE SN 25", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_CACHE_CHANGE; - rtps.cc := cc3; - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_CACHE_CHANGE SN 26", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_CACHE_CHANGE; - rtps.cc := cc4; - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_CACHE_CHANGE SN 29", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_CACHE_CHANGE; - rtps.cc := cc1; - start_rtps; - wait_on_rtps; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh2; - cc.payload := gen_payload(kh2,10); - cc.seq_nr := gen_sn(30); - cc.src_timestamp := gen_duration(30,0); - - Log("DDS Operation WRITE [TS 30s, Instance 2, Aligned Payload] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc2 := cc; - -- Stored CC: I2S29, I2S30, I4S25, I1S26 - - Log("RTPS Operation ACK_CACHE_CHANGE SN 25", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := ACK_CACHE_CHANGE; - rtps.cc := cc3; - start_rtps; - wait_on_rtps; - - Log("RTPS Operation ACK_CACHE_CHANGE SN 26", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := ACK_CACHE_CHANGE; - rtps.cc := cc4; - start_rtps; - wait_on_rtps; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh4; - cc.payload := gen_payload(kh4,10); - cc.seq_nr := gen_sn(31); - cc.src_timestamp := gen_duration(31,0); - - -- TEST: ADD SAMPLE ON MAX_SAMPLES [KNOWN INSTANCE,WITH ACKed SAMPLES (>1)] - - Log("DDS Operation WRITE [TS 31s, Instance 4, Aligned Payload] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc3 := cc; - -- Stored CC: I2S29, I2S30, I4S31, I1S26 - - Log("RTPS Operation REMOVE_CACHE_CHANGE SN 31", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := REMOVE_CACHE_CHANGE; - rtps.cc := cc3; - start_rtps; - wait_on_rtps; - -- Stored CC: I2S29, I2S30, 0, I1S26 - - Log("RTPS Operation ACK_CACHE_CHANGE SN 29", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := ACK_CACHE_CHANGE; - rtps.cc := cc1; - start_rtps; - wait_on_rtps; - - Log("RTPS Operation ACK_CACHE_CHANGE SN 30", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := ACK_CACHE_CHANGE; - rtps.cc := cc2; - start_rtps; - wait_on_rtps; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh2; - cc.payload := gen_payload(kh2,10); - cc.seq_nr := gen_sn(32); - cc.src_timestamp := gen_duration(32,0); - - -- TEST: ADD SAMPLE ON MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE, WITH ACKed INSTANCE SAMPLES(>1)] - - Log("DDS Operation WRITE [TS 32s, Instance 2, Aligned Payload] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc1 := cc; - -- Stored CC: I2S32, I2S30, 0, I1S26 - - -- VALIDATE STATE - - Log("RTPS Operation GET_MIN_SN (Expected SN 26)", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_MIN_SN; - rtps.cc.seq_nr := gen_sn(26); - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_MAX_SN (Expected SN 32)", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_MAX_SN; - rtps.cc.seq_nr := gen_sn(32); - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_CACHE_CHANGE SN 26", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_CACHE_CHANGE; - rtps.cc := cc4; - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_CACHE_CHANGE SN 30", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_CACHE_CHANGE; - rtps.cc := cc2; - start_rtps; - wait_on_rtps; - - Log("RTPS Operation GET_CACHE_CHANGE SN 32", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := GET_CACHE_CHANGE; - rtps.cc := cc1; - start_rtps; - wait_on_rtps; - - -- TEST: INSTANCE LOOKUP [KNOWN INSTANCE] - - Log("DDS Operation LOOKUP_INSTANCE [Instance 2]", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := LOOKUP_INSTANCE; - dds.cc := cc; - start_dds; - wait_on_dds; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh3; - cc.payload := gen_payload(kh3,10); - - -- TEST: INSTANCE LOOKUP [UNKNOWN INSTANCE] - - Log("DDS Operation LOOKUP_INSTANCE [Unknown Instance]", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := LOOKUP_INSTANCE; - dds.cc := cc; - dds.cc.instance:= HANDLE_NIL; - start_dds; - wait_on_dds; - - wait_on_completion; - TranscriptOpen(RESULTS_FILE, APPEND_MODE); - SetTranscriptMirror; - ReportAlerts; - TranscriptClose; - std.env.stop; - wait; - end process; - - clock_prc : process - begin - clk <= '0'; - wait for 25 ns; - clk <= '1'; - wait for 25 ns; - end process; - - alert_prc : process(all) - begin - if rising_edge(clk) then - -- TODO - end if; - end process; - - dds_prc : process(all) - begin - if rising_edge(clk) then - dds_done <= '0'; - case (dds_stage) is - when IDLE => - if (dds_start = '1') then - dds_stage <= START; - else - dds_done <= '1'; - end if; - when START => - if (ack_dds = '1') then - dds_stage <= PUSH; - dds_cnt <= 0; - end if; - when PUSH => - if (ready_in_dds = '1') then - dds_cnt <= dds_cnt + 1; - if (dds_cnt = dds.cc.payload.length-1) then - -- DEFAULT - dds_stage <= DONE; - end if; - end if; - when DONE => - if (done_dds = '1') then - if (dds.opcode = REGISTER_INSTANCE or dds.opcode = LOOKUP_INSTANCE) then - AffirmIfEqual(ih_id, to_unsigned(instance_handle_out_dds), to_unsigned(dds.cc.instance)); - else - AffirmIfEqual(ret_id, return_code_dds, dds.ret_code); - end if; - dds_stage <= IDLE; - end if; - end case; - end if; - - -- DEFAULT - start_dds <= '0'; - opcode_dds <= NOP; - valid_in_dds <= '0'; - last_word_in_dds <= '0'; - data_in_dds <= (others => '0'); - instance_handle_in_dds <= HANDLE_NIL; - source_ts_dds <= TIME_INVALID; - ready_out_dds <= '0'; - - case (dds_stage) is - when START => - start_dds <= '1'; - opcode_dds <= dds.opcode; - instance_handle_in_dds <= dds.cc.instance; - source_ts_dds <= dds.cc.src_timestamp; - when PUSH => - valid_in_dds <= '1'; - data_in_dds <= dds.cc.payload.data(dds_cnt); - last_word_in_dds <= dds.cc.payload.last(dds_cnt); - when others => - null; - end case; - end process; - - rtps_prc : process(all) - begin - if rising_edge(clk) then - rtps_done <= '0'; - case (rtps_stage) is - when IDLE => - if (rtps_start = '1') then - rtps_stage <= START; - else - rtps_done <= '1'; - end if; - when START => - if (ack_rtps = '1') then - rtps_stage <= DONE; - end if; - when DONE => - if (done_rtps = '1') then - -- DEFAULT - rtps_stage <= IDLE; - - AffirmIfEqual(ret_id, HISTORY_CACHE_RESPONSE_TYPE'pos(ret_rtps), HISTORY_CACHE_RESPONSE_TYPE'pos(rtps.ret_code)); - case (rtps.opcode) is - when GET_CACHE_CHANGE => - if (rtps.ret_code = OK) then - AffirmIfEqual(inst_id, to_unsigned(cc_instance_handle), to_unsigned(rtps.cc.instance)); - AffirmIfEqual(kind_id, CACHE_CHANGE_KIND_TYPE'pos(cc_kind), CACHE_CHANGE_KIND_TYPE'pos(rtps.cc.kind)); - AffirmIfEqual(sn_id, to_unsigned(cc_seq_nr), to_unsigned(rtps.cc.seq_nr)); - AffirmIfEqual(ts_id, to_unsigned(cc_source_timestamp), to_unsigned(rtps.cc.src_timestamp)); - rtps_stage <= CHECK; - rtps_cnt <= 0; - end if; - when GET_MIN_SN => - AffirmIfEqual(sn_id, to_unsigned(cc_seq_nr), to_unsigned(rtps.cc.seq_nr)); - when GET_MAX_SN => - AffirmIfEqual(sn_id, to_unsigned(cc_seq_nr), to_unsigned(rtps.cc.seq_nr)); - when others => - null; - end case; - end if; - when CHECK => - if (valid_out_rtps = '1') then - AffirmIfEqual(data_id, last_word_out_rtps & data_out_rtps, rtps.cc.payload.last(rtps_cnt) & rtps.cc.payload.data(rtps_cnt)); - rtps_cnt <= rtps_cnt + 1; - if (rtps_cnt = rtps.cc.payload.length-1) then - rtps_stage <= IDLE; - end if; - end if; - end case; - end if; - - -- DEFAULT - start_rtps <= '0'; - opcode_rtps <= NOP; - seq_nr_rtps <= SEQUENCENUMBER_UNKNOWN; - get_data_rtps <= '0'; - ready_out_rtps <= '0'; - - case (rtps_stage) is - when START => - start_rtps <= '1'; - opcode_rtps <= rtps.opcode; - seq_nr_rtps <= rtps.cc.seq_nr; - when DONE => - if (done_rtps = '1') then - case (rtps.opcode) is - when GET_CACHE_CHANGE => - get_data_rtps <= '1'; - when others => - null; - end case; - end if; - when CHECK => - ready_out_rtps <= '1'; - when others => - null; - end case; - end process; - - watchdog : process - begin - wait for 1 ms; - Alert("Test timeout", FAILURE); - std.env.stop; - end process; - -end architecture; \ No newline at end of file diff --git a/src/Tests/Level_0/L0_dds_writer_test2.vhd b/src/Tests/Level_0/L0_dds_writer_test2.vhd new file mode 100644 index 0000000..81137ac --- /dev/null +++ b/src/Tests/Level_0/L0_dds_writer_test2.vhd @@ -0,0 +1,709 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library osvvm; -- Utility Library +context osvvm.OsvvmContext; + +use work.rtps_package.all; +use work.user_config.all; +use work.rtps_config_package.all; +use work.rtps_test_package.all; + +-- This testbench tests the DDS WAIT_FOR_ACKNOWLEDGEMENTS Operation of the DDS Writer. + +entity L0_dds_writer_test2 is +end entity; + +architecture testbench of L0_dds_writer_test2 is + + -- *CONSTANT DECLARATION* + constant MAX_REMOTE_ENDPOINTS : natural := 3; + constant NUM_WRITERS : natural := 2; + + impure function gen_test_config return CONFIG_ARRAY_TYPE is + variable ret : CONFIG_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => DEFAULT_WRITER_CONFIG); + begin + -- aik + ret(0).HISTORY_QOS := KEEP_ALL_HISTORY_QOS; + ret(0).DEADLINE_QOS := DURATION_INFINITE; + ret(0).LIFESPAN_QOS := DURATION_INFINITE; + ret(0).LEASE_DURATION := DURATION_INFINITE; + ret(0).WITH_KEY := TRUE; + ret(0).MAX_SAMPLES := std_logic_vector(to_unsigned(4,CDR_LONG_WIDTH)); + ret(0).MAX_INSTANCES := std_logic_vector(to_unsigned(3,CDR_LONG_WIDTH)); + ret(0).MAX_SAMPLES_PER_INSTANCE := std_logic_vector(to_unsigned(2,CDR_LONG_WIDTH)); + ret(0).MAX_PAYLOAD_SIZE := 40; + -- ain + ret(1).HISTORY_QOS := KEEP_ALL_HISTORY_QOS; + ret(1).DEADLINE_QOS := DURATION_INFINITE; + ret(1).LIFESPAN_QOS := DURATION_INFINITE; + ret(1).LEASE_DURATION := DURATION_INFINITE; + ret(1).WITH_KEY := FALSE; + ret(1).MAX_SAMPLES := std_logic_vector(to_unsigned(4,CDR_LONG_WIDTH)); + ret(1).MAX_INSTANCES := std_logic_vector(to_unsigned(3,CDR_LONG_WIDTH)); + ret(1).MAX_SAMPLES_PER_INSTANCE := std_logic_vector(to_unsigned(4,CDR_LONG_WIDTH)); + ret(1).MAX_PAYLOAD_SIZE := 40; + return ret; + end function; + constant TEST_CONFIG : CONFIG_ARRAY_TYPE := gen_test_config; + + -- *TYPE DECLARATION* + type DDS_STAGE_TYPE is (IDLE, START, PUSH, DONE); + type RTPS_STAGE_TYPE is (IDLE, START, DONE, CHECK); + + -- *SIGNAL DECLARATION* + signal clk : std_logic := '0'; + signal reset : std_logic := '1'; + signal check_time : TIME_TYPE := TIME_ZERO; + signal start_rtps, start_dds, ack_rtps, ack_dds, done_rtps, done_dds, w_map : std_logic_vector(0 to NUM_WRITERS-1) := (others => '0'); + signal opcode_rtps : HISTORY_CACHE_OPCODE_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => NOP); + signal opcode_dds : DDS_WRITER_OPCODE_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => NOP); + signal ret_rtps : HISTORY_CACHE_RESPONSE_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => ERROR); + signal seq_nr_rtps, cc_seq_nr : SEQUENCENUMBER_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => SEQUENCENUMBER_UNKNOWN); + signal ready_out_rtps, valid_out_rtps, last_word_out_rtps : std_logic_vector(0 to NUM_WRITERS-1) := (others => '0'); + signal ready_in_dds, ready_out_dds, valid_in_dds, valid_out_dds, last_word_in_dds, last_word_out_dds : std_logic_vector(0 to NUM_WRITERS-1) := (others => '0'); + signal data_out_rtps, data_in_dds, data_out_dds : WORD_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => (others => '0')); + signal get_data_rtps, liveliness_assertion, data_available : std_logic_vector(0 to NUM_WRITERS-1) := (others => '0'); + signal cc_source_timestamp, source_ts_dds : TIME_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => TIME_INVALID); + signal cc_kind : CACHE_CHANGE_KIND_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => ALIVE); + signal cc_instance_handle, instance_handle_in_dds, instance_handle_out_dds : INSTANCE_HANDLE_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => HANDLE_NIL); + signal max_wait_dds : DURATION_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => DURATION_INFINITE); + signal return_code_dds : RETURN_CODE_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => (others => '0')); + signal status : STATUS_KIND_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => (others => '0')); + + signal ind : natural := 0; + signal dds1_start, dds2_start, dds1_done, dds2_done, rtps_start, rtps_done : std_logic := '0'; + signal dds1_cnt, dds2_cnt, rtps_cnt : natural := 0; + signal dds1_stage, dds2_stage : DDS_STAGE_TYPE := IDLE; + signal rtps_stage : RTPS_STAGE_TYPE := IDLE; + shared variable dds1, dds2 : DDS_WRITER_TEST_TYPE := DEFAULT_DDS_WRITER_TEST; + shared variable rtps : RTPS_WRITER_TEST_TYPE := DEFAULT_RTPS_WRITER_TEST; + signal inst_id, kind_id, sn_id, ts_id, data_id, ret_id, ih_id : AlertLogIDType; + + -- *FUNCTION DECLARATION* + function extract_key_hash (payload : TEST_PACKET_TYPE) return INSTANCE_HANDLE_TYPE is + variable ret : INSTANCE_HANDLE_TYPE := HANDLE_NIL; + begin + for i in 0 to 3 loop + ret(i) := not payload.data(i); + end loop; + + return ret; + end function; + + function gen_sn(input : natural) return SEQUENCENUMBER_TYPE is + variable ret : SEQUENCENUMBER_TYPE; + begin + ret(0) := (others => '0'); + ret(1) := unsigned(int(input, WORD_WIDTH)); + return ret; + end function; + + procedure wait_on_sig(signal sig : std_logic) is + begin + if (sig /= '1') then + wait on sig until sig = '1'; + end if; + end procedure; + +begin + + -- Unit Under Test + uut : entity work.dds_writer(arch) + generic map( + NUM_WRITERS => NUM_WRITERS, + CONFIG_ARRAY => to_QUARTUS_CONFIG_ARRAY_TYPE(TEST_CONFIG) + ) + port map ( + clk => clk, + reset => reset, + time => check_time, + start_rtps => start_rtps, + opcode_rtps => opcode_rtps, + ack_rtps => ack_rtps, + done_rtps => done_rtps, + ret_rtps => ret_rtps, + seq_nr_rtps => seq_nr_rtps, + get_data_rtps => get_data_rtps, + data_out_rtps => data_out_rtps, + valid_out_rtps => valid_out_rtps, + ready_out_rtps => ready_out_rtps, + last_word_out_rtps => last_word_out_rtps, + liveliness_assertion => liveliness_assertion, + data_available => data_available, + cc_instance_handle => cc_instance_handle, + cc_kind => cc_kind, + cc_source_timestamp => cc_source_timestamp, + cc_seq_nr => cc_seq_nr, + start_dds => start_dds, + ack_dds => ack_dds, + opcode_dds => opcode_dds, + instance_handle_in_dds => instance_handle_in_dds, + source_ts_dds => source_ts_dds, + max_wait_dds => max_wait_dds, + done_dds => done_dds, + return_code_dds => return_code_dds, + instance_handle_out_dds => instance_handle_out_dds, + ready_in_dds => ready_in_dds, + valid_in_dds => valid_in_dds, + data_in_dds => data_in_dds, + last_word_in_dds => last_word_in_dds, + ready_out_dds => ready_out_dds, + valid_out_dds => valid_out_dds, + data_out_dds => data_out_dds, + last_word_out_dds => last_word_out_dds, + status => status + ); + + stimulus_prc : process + variable RV : RandomPType; + variable kh1, kh2, kh3, kh4 : INSTANCE_HANDLE_TYPE := HANDLE_NIL; + variable cc1, cc2, cc3, cc4, cc : CACHE_CHANGE_TYPE := DEFAULT_CACHE_CHANGE; + + alias idle_sig is <>; + + impure function gen_payload(key_hash : INSTANCE_HANDLE_TYPE; len : natural) return TEST_PACKET_TYPE is + variable ret : TEST_PACKET_TYPE := EMPTY_TEST_PACKET; + begin + assert (len >= 4) report "Payload length has to be at least 16 Bytes long" severity FAILURE; + + for i in 0 to len-1 loop + if (i < 4) then + -- NOTE: Beginning of payload is negated key to allow deterministic Key Hash generation from the kh_prc + ret.data(ret.length) := not key_hash(i); + else + ret.data(ret.length) := RV.RandSlv(WORD_WIDTH); + end if; + ret.length := ret.length + 1; + end loop; + ret.last(ret.length-1) := '1'; + + return ret; + end function; + + impure function gen_key_hash return KEY_HASH_TYPE is + variable ret : KEY_HASH_TYPE := KEY_HASH_NIL; + begin + for i in 0 to KEY_HASH_TYPE'length-1 loop + ret(i) := RV.RandSlv(WORD_WIDTH); + end loop; + return ret; + end function; + + procedure start_dds1 is + begin + dds1_start <= '1'; + wait until rising_edge(clk); + dds1_start <= '0'; + wait until rising_edge(clk); + end procedure; + + procedure start_dds2 is + begin + dds2_start <= '1'; + wait until rising_edge(clk); + dds2_start <= '0'; + wait until rising_edge(clk); + end procedure; + + procedure start_rtps is + begin + rtps_start <= '1'; + wait until rising_edge(clk); + rtps_start <= '0'; + wait until rising_edge(clk); + end procedure; + + procedure wait_on_completion is + begin + if (rtps_done /= '1' or dds1_done /= '1' or dds2_done /= '1') then + wait until rtps_done = '1' and dds1_done = '1' and dds2_done = '1'; + end if; + end procedure; + + -- NOTE: This procedure waits until the idle_sig is high for at least + -- two consecutive clock cycles. + procedure wait_on_idle is + variable first : boolean := TRUE; + begin + loop + if (idle_sig /= '1') then + wait until idle_sig = '1'; + elsif (not first) then + exit; + end if; + wait until rising_edge(clk); + wait until rising_edge(clk); + first := FALSE; + end loop; + end procedure; + + begin + + SetAlertLogName("L0_dds_writer_test2 - Wait For Acknowledgements"); + SetAlertEnable(FAILURE, TRUE); + SetAlertEnable(ERROR, TRUE); + SetAlertEnable(WARNING, TRUE); + SetLogEnable(DEBUG, FALSE); + SetLogEnable(PASSED, FALSE); + SetLogEnable(INFO, TRUE); + RV.InitSeed(RV'instance_name); + inst_id <= GetAlertLogID("Instance", ALERTLOG_BASE_ID); + kind_id <= GetAlertLogID("Cache Change Kind", ALERTLOG_BASE_ID); + sn_id <= GetAlertLogID("SequenceNumber", ALERTLOG_BASE_ID); + ts_id <= GetAlertLogID("TimeStamp", ALERTLOG_BASE_ID); + ih_id <= GetAlertLogID("Instance Handle", ALERTLOG_BASE_ID); + data_id <= GetAlertLogID("Data Out", ALERTLOG_BASE_ID); + ret_id <= GetAlertLogID("Return Code", ALERTLOG_BASE_ID); + + -- Key Hashes + kh1 := gen_key_hash; + kh2 := gen_key_hash; + kh3 := gen_key_hash; + kh4 := gen_key_hash; + + + Log("Initiating Test", INFO); + Log("Current Time: 0s", INFO); + max_wait_dds <= (others => DURATION_ZERO); + check_time <= TIME_ZERO; + reset <= '1'; + wait until rising_edge(clk); + wait until rising_edge(clk); + reset <= '0'; + + Log("W0,W1: DDS Operation WAIT_FOR_ACKNOWLEDGEMENTS [max_wait 0s]", INFO); + Log("W0,W1: OK", DEBUG); + dds1 := DEFAULT_DDS_WRITER_TEST; + dds1.opcode := WAIT_FOR_ACKNOWLEDGEMENTS; + dds1.ret_code := RETCODE_OK; + dds2 := dds1; + max_wait_dds <= (others => gen_duration(0 sec)); + start_dds1; + start_dds2; + wait_on_sig(dds1_done); + wait_on_sig(dds2_done); + wait_on_idle; + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh1; + cc.payload := gen_payload(kh1,10); + cc.seq_nr := gen_sn(1); + cc.src_timestamp := gen_duration(1 sec); + + Log("W0,W1: DDS Operation WRITE [TS 1s, Instance 1, HANDLE_NIL, Aligned Payload]", INFO); + Log("W0,W1: ACCEPTED", DEBUG); + dds1 := DEFAULT_DDS_WRITER_TEST; + dds1.opcode := WRITE; + dds1.cc := cc; + dds1.cc.instance:= HANDLE_NIL; + dds1.ret_code := RETCODE_OK; + dds2 := dds1; + start_dds1; + start_dds2; + wait_on_sig(dds1_done); + wait_on_sig(dds2_done); + wait_on_idle; + cc1 := cc; + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh2; + cc.payload := gen_payload(kh2,10); + cc.seq_nr := gen_sn(2); + cc.src_timestamp := gen_duration(2 sec); + + Log("W0,W1: DDS Operation WRITE [TS 2s, Instance 2, HANDLE_NIL, Aligned Payload]", INFO); + Log("W0,W1: ACCEPTED", DEBUG); + dds1 := DEFAULT_DDS_WRITER_TEST; + dds1.opcode := WRITE; + dds1.cc := cc; + dds1.cc.instance:= HANDLE_NIL; + dds1.ret_code := RETCODE_OK; + dds2 := dds1; + start_dds1; + start_dds2; + wait_on_sig(dds1_done); + wait_on_sig(dds2_done); + wait_on_idle; + cc2 := cc; + + Log("W0,W1: DDS Operation WAIT_FOR_ACKNOWLEDGEMENTS [max_wait 0s]", INFO); + Log("W0,W1: WAIT_FOR_ACKNOWLEDGEMENTS Return TIMEOUT", DEBUG); + dds1 := DEFAULT_DDS_WRITER_TEST; + dds1.opcode := WAIT_FOR_ACKNOWLEDGEMENTS; + dds1.ret_code := RETCODE_TIMEOUT; + max_wait_dds <= (others => gen_duration(0 sec)); + dds2 := dds1; + start_dds1; + start_dds2; + wait_on_sig(dds1_done); + wait_on_sig(dds2_done); + wait_on_idle; + + Log("W0: DDS Operation WAIT_FOR_ACKNOWLEDGEMENTS [max_wait 1s]", INFO); + Log("W1: DDS Operation WAIT_FOR_ACKNOWLEDGEMENTS [max_wait 2s]", INFO); + dds1 := DEFAULT_DDS_WRITER_TEST; + dds1.opcode := WAIT_FOR_ACKNOWLEDGEMENTS; + dds1.ret_code := RETCODE_TIMEOUT; + max_wait_dds(0) <= gen_duration(1 sec); + dds2 := DEFAULT_DDS_WRITER_TEST; + dds2.opcode := WAIT_FOR_ACKNOWLEDGEMENTS; + dds2.ret_code := RETCODE_OK; + max_wait_dds(1) <= gen_duration(2 sec); + start_dds1; + start_dds2; + wait_on_idle; + AlertIf(dds1_done = '1', "Writer 0 not waiting", FAILURE); + AlertIf(dds2_done = '1', "Writer 1 not waiting", FAILURE); + + Log("W0,W1: RTPS Operation ACK_CACHE_CHANGE SN 1", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := ACK_CACHE_CHANGE; + rtps.cc := cc1; + -- WRITER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- WRITER 1 + ind <= 1; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("Current Time: 1s", INFO); + Log("W0: WAIT_FOR_ACKNOWLEDGEMENTS Return TIMEOUT", DEBUG); + check_time <= gen_duration(1 sec); + wait until rising_edge(clk); + wait_on_sig(dds1_done); + wait_on_idle; + AlertIf(dds2_done = '1', "Writer 1 not waiting", FAILURE); + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh1; + cc.payload := gen_payload(kh1,10); + cc.seq_nr := gen_sn(3); + cc.src_timestamp := gen_duration(3 sec); + + Log("W0: DDS Operation WRITE [TS 3s, Instance 1, HANDLE_NIL, Aligned Payload]", INFO); + Log("W0: ACCEPTED", DEBUG); + dds1 := DEFAULT_DDS_WRITER_TEST; + dds1.opcode := WRITE; + dds1.cc := cc; + dds1.cc.instance:= HANDLE_NIL; + dds1.ret_code := RETCODE_OK; + start_dds1; + wait_on_sig(dds1_done); + wait_on_idle; + cc3 := cc; + AlertIf(dds2_done = '1', "Writer 1 not waiting", FAILURE); + + Log("W0: DDS Operation WAIT_FOR_ACKNOWLEDGEMENTS [max_wait 2s]", INFO); + dds1 := DEFAULT_DDS_WRITER_TEST; + dds1.opcode := WAIT_FOR_ACKNOWLEDGEMENTS; + dds1.ret_code := RETCODE_OK; + max_wait_dds(0) <= gen_duration(2 sec); + start_dds1; + AlertIf(dds1_done = '1', "Writer 0 not waiting", FAILURE); + AlertIf(dds2_done = '1', "Writer 1 not waiting", FAILURE); + + Log("W0,W1: RTPS Operation ACK_CACHE_CHANGE SN 2", INFO); + Log("W1: WAIT_FOR_ACKNOWLEDGEMENTS Return OK", DEBUG); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := ACK_CACHE_CHANGE; + rtps.cc := cc2; + -- WRITER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- WRITER 1 + ind <= 1; + start_rtps; + wait_on_sig(rtps_done); + wait_on_sig(dds2_done); + wait_on_idle; + AlertIf(dds1_done = '1', "Writer 0 not waiting", FAILURE); + + Log("W1: RTPS Operation NACK_CACHE_CHANGE SN 1", INFO); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := NACK_CACHE_CHANGE; + rtps.cc.seq_nr := gen_sn(1); + -- WRITER 1 + ind <= 1; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + AlertIf(dds1_done = '1', "Writer 0 not waiting", FAILURE); + + Log("W1: DDS Operation WAIT_FOR_ACKNOWLEDGEMENTS [max_wait 1s]", INFO); + dds2 := DEFAULT_DDS_WRITER_TEST; + dds2.opcode := WAIT_FOR_ACKNOWLEDGEMENTS; + dds2.ret_code := RETCODE_TIMEOUT; + max_wait_dds(1) <= gen_duration(1 sec); + start_dds2; + AlertIf(dds1_done = '1', "Writer 0 not waiting", FAILURE); + AlertIf(dds2_done = '1', "Writer 1 not waiting", FAILURE); + + Log("Current Time: 2s", INFO); + Log("W1: WAIT_FOR_ACKNOWLEDGEMENTS Return TIMEOUT", DEBUG); + check_time <= gen_duration(2 sec); + wait until rising_edge(clk); + wait_on_sig(dds2_done); + wait_on_idle; + AlertIf(dds1_done = '1', "Writer 0 not waiting", FAILURE); + + Log("W0: RTPS Operation ACK_CACHE_CHANGE SN 3", INFO); + Log("W0: WAIT_FOR_ACKNOWLEDGEMENTS Return OK", DEBUG); + rtps := DEFAULT_RTPS_WRITER_TEST; + rtps.opcode := ACK_CACHE_CHANGE; + rtps.cc := cc3; + -- WRITER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + wait_on_sig(dds1_done); + wait_on_idle; + + wait_on_completion; + TranscriptOpen(RESULTS_FILE, APPEND_MODE); + SetTranscriptMirror; + ReportAlerts; + TranscriptClose; + std.env.stop; + wait; + end process; + + clock_prc : process + begin + clk <= '0'; + wait for 25 ns; + clk <= '1'; + wait for 25 ns; + end process; + + dds1_prc : process(all) + begin + if rising_edge(clk) then + dds1_done <= '0'; + case (dds1_stage) is + when IDLE => + if (dds1_start = '1') then + dds1_stage <= START; + else + dds1_done <= '1'; + end if; + when START => + if (ack_dds(0) = '1') then + case (dds1.opcode) is + when WAIT_FOR_ACKNOWLEDGEMENTS => + dds1_stage <= DONE; + dds1_cnt <= 0; + when others => + dds1_stage <= PUSH; + dds1_cnt <= 0; + end case; + end if; + when PUSH => + if (ready_in_dds(0) = '1') then + dds1_cnt <= dds1_cnt + 1; + if (dds1_cnt = dds1.cc.payload.length-1) then + -- DEFAULT + dds1_stage <= DONE; + end if; + end if; + when DONE => + if (done_dds(0) = '1') then + if (dds1.opcode = REGISTER_INSTANCE or dds1.opcode = LOOKUP_INSTANCE) then + AffirmIfEqual(ih_id, to_unsigned(instance_handle_out_dds(0)), to_unsigned(dds1.cc.instance)); + else + AffirmIfEqual(ret_id, return_code_dds(0), dds1.ret_code); + end if; + dds1_stage <= IDLE; + end if; + end case; + end if; + + -- DEFAULT + start_dds(0) <= '0'; + opcode_dds(0) <= NOP; + valid_in_dds(0) <= '0'; + last_word_in_dds(0) <= '0'; + data_in_dds(0) <= (others => '0'); + instance_handle_in_dds(0) <= HANDLE_NIL; + source_ts_dds(0) <= TIME_INVALID; + ready_out_dds(0) <= '0'; + + case (dds1_stage) is + when START => + start_dds(0) <= '1'; + opcode_dds(0) <= dds1.opcode; + instance_handle_in_dds(0) <= dds1.cc.instance; + source_ts_dds(0) <= dds1.cc.src_timestamp; + when PUSH => + valid_in_dds(0) <= '1'; + data_in_dds(0) <= dds1.cc.payload.data(dds1_cnt); + last_word_in_dds(0) <= dds1.cc.payload.last(dds1_cnt); + when others => + null; + end case; + end process; + + dds2_prc : process(all) + begin + if rising_edge(clk) then + dds2_done <= '0'; + case (dds2_stage) is + when IDLE => + if (dds2_start = '1') then + dds2_stage <= START; + else + dds2_done <= '1'; + end if; + when START => + if (ack_dds(1) = '1') then + case (dds2.opcode) is + when WAIT_FOR_ACKNOWLEDGEMENTS => + dds2_stage <= DONE; + dds2_cnt <= 0; + when others => + dds2_stage <= PUSH; + dds2_cnt <= 0; + end case; + end if; + when PUSH => + if (ready_in_dds(1) = '1') then + dds2_cnt <= dds2_cnt + 1; + if (dds2_cnt = dds2.cc.payload.length-1) then + -- DEFAULT + dds2_stage <= DONE; + end if; + end if; + when DONE => + if (done_dds(1) = '1') then + if (dds2.opcode = REGISTER_INSTANCE or dds2.opcode = LOOKUP_INSTANCE) then + AffirmIfEqual(ih_id, to_unsigned(instance_handle_out_dds(1)), to_unsigned(dds2.cc.instance)); + else + AffirmIfEqual(ret_id, return_code_dds(1), dds2.ret_code); + end if; + dds2_stage <= IDLE; + end if; + end case; + end if; + + -- DEFAULT + start_dds(1) <= '0'; + opcode_dds(1) <= NOP; + valid_in_dds(1) <= '0'; + last_word_in_dds(1) <= '0'; + data_in_dds(1) <= (others => '0'); + instance_handle_in_dds(1) <= HANDLE_NIL; + source_ts_dds(1) <= TIME_INVALID; + ready_out_dds(1) <= '0'; + + case (dds2_stage) is + when START => + start_dds(1) <= '1'; + opcode_dds(1) <= dds2.opcode; + instance_handle_in_dds(1) <= dds2.cc.instance; + source_ts_dds(1) <= dds2.cc.src_timestamp; + when PUSH => + valid_in_dds(1) <= '1'; + data_in_dds(1) <= dds2.cc.payload.data(dds2_cnt); + last_word_in_dds(1) <= dds2.cc.payload.last(dds2_cnt); + when others => + null; + end case; + end process; + + rtps_prc : process(all) + begin + if rising_edge(clk) then + rtps_done <= '0'; + case (rtps_stage) is + when IDLE => + if (rtps_start = '1') then + rtps_stage <= START; + else + rtps_done <= '1'; + end if; + when START => + if (ack_rtps(ind) = '1') then + rtps_stage <= DONE; + end if; + when DONE => + if (done_rtps(ind) = '1') then + -- DEFAULT + rtps_stage <= IDLE; + + AffirmIfEqual(ret_id, HISTORY_CACHE_RESPONSE_TYPE'pos(ret_rtps(ind)), HISTORY_CACHE_RESPONSE_TYPE'pos(rtps.ret_code)); + case (rtps.opcode) is + when GET_CACHE_CHANGE => + if (rtps.ret_code = OK) then + AffirmIfEqual(inst_id, to_unsigned(cc_instance_handle(ind)), to_unsigned(rtps.cc.instance)); + AffirmIfEqual(kind_id, CACHE_CHANGE_KIND_TYPE'pos(cc_kind(ind)), CACHE_CHANGE_KIND_TYPE'pos(rtps.cc.kind)); + AffirmIfEqual(sn_id, to_unsigned(cc_seq_nr(ind)), to_unsigned(rtps.cc.seq_nr)); + AffirmIfEqual(ts_id, to_unsigned(cc_source_timestamp(ind)), to_unsigned(rtps.cc.src_timestamp)); + rtps_stage <= CHECK; + rtps_cnt <= 0; + end if; + when GET_MIN_SN => + AffirmIfEqual(sn_id, to_unsigned(cc_seq_nr(ind)), to_unsigned(rtps.cc.seq_nr)); + when GET_MAX_SN => + AffirmIfEqual(sn_id, to_unsigned(cc_seq_nr(ind)), to_unsigned(rtps.cc.seq_nr)); + when others => + null; + end case; + end if; + when CHECK => + if (valid_out_rtps(ind) = '1') then + AffirmIfEqual(data_id, last_word_out_rtps(ind) & data_out_rtps(ind), rtps.cc.payload.last(rtps_cnt) & rtps.cc.payload.data(rtps_cnt)); + rtps_cnt <= rtps_cnt + 1; + if (rtps_cnt = rtps.cc.payload.length-1) then + rtps_stage <= IDLE; + end if; + end if; + end case; + end if; + + -- DEFAULT + start_rtps <= (others => '0'); + opcode_rtps <= (others => NOP); + seq_nr_rtps <= (others => SEQUENCENUMBER_UNKNOWN); + get_data_rtps <= (others => '0'); + ready_out_rtps <= (others => '0'); + + case (rtps_stage) is + when START => + start_rtps(ind) <= '1'; + opcode_rtps(ind) <= rtps.opcode; + seq_nr_rtps(ind) <= rtps.cc.seq_nr; + when DONE => + if (done_rtps(ind) = '1') then + case (rtps.opcode) is + when GET_CACHE_CHANGE => + get_data_rtps(ind) <= '1'; + when others => + null; + end case; + end if; + when CHECK => + ready_out_rtps(ind) <= '1'; + when others => + null; + end case; + end process; + + watchdog : process + begin + wait for 1 ms; + Alert("Test timeout", FAILURE); + std.env.stop; + end process; + +end architecture; \ No newline at end of file diff --git a/src/Tests/Level_0/L0_dds_writer_test2_aik.vhd b/src/Tests/Level_0/L0_dds_writer_test2_aik.vhd deleted file mode 100644 index 996dc13..0000000 --- a/src/Tests/Level_0/L0_dds_writer_test2_aik.vhd +++ /dev/null @@ -1,500 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library osvvm; -- Utility Library -context osvvm.OsvvmContext; - -use work.rtps_package.all; -use work.user_config.all; -use work.rtps_config_package.all; -use work.rtps_test_package.all; - --- This testbench tests the DDS WAIT_FOR_ACKNOWLEDGEMENTS Operation of the DDS Writer. - -entity L0_dds_writer_test2_aik is -end entity; - -architecture testbench of L0_dds_writer_test2_aik is - - -- *CONSTANT DECLARATION* - constant MAX_REMOTE_ENDPOINTS : natural := 3; - - -- *TYPE DECLARATION* - type DDS_STAGE_TYPE is (IDLE, START, PUSH, DONE); - type RTPS_STAGE_TYPE is (IDLE, START, DONE, CHECK); - - -- *SIGNAL DECLARATION* - signal clk : std_logic := '0'; - signal reset : std_logic := '1'; - signal check_time : TIME_TYPE := TIME_ZERO; - signal start_rtps, start_dds, ack_rtps, ack_dds, done_rtps, done_dds : std_logic := '0'; - signal opcode_rtps : HISTORY_CACHE_OPCODE_TYPE := NOP; - signal opcode_dds : DDS_WRITER_OPCODE_TYPE := NOP; - signal ret_rtps : HISTORY_CACHE_RESPONSE_TYPE := ERROR; - signal seq_nr_rtps, cc_seq_nr : SEQUENCENUMBER_TYPE := SEQUENCENUMBER_UNKNOWN; - signal ready_out_rtps, valid_out_rtps, last_word_out_rtps : std_logic := '0'; - signal ready_in_dds, ready_out_dds, valid_in_dds, valid_out_dds, last_word_in_dds, last_word_out_dds : std_logic := '0'; - signal data_out_rtps, data_in_dds, data_out_dds : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); - signal get_data_rtps, liveliness_assertion, data_available : std_logic := '0'; - signal cc_source_timestamp, source_ts_dds : TIME_TYPE := TIME_INVALID; - signal cc_kind : CACHE_CHANGE_KIND_TYPE := ALIVE; - signal cc_instance_handle, instance_handle_in_dds, instance_handle_out_dds : INSTANCE_HANDLE_TYPE := HANDLE_NIL; - signal max_wait_dds : DURATION_TYPE := DURATION_INFINITE; - signal return_code_dds : std_logic_vector(RETURN_CODE_WIDTH-1 downto 0) := (others => '0'); - signal status : std_logic_vector(STATUS_KIND_WIDTH-1 downto 0) := (others => '0'); - - signal dds_start, dds_done, rtps_start, rtps_done : std_logic := '0'; - signal dds_cnt, rtps_cnt : natural := 0; - signal dds_stage : DDS_STAGE_TYPE := IDLE; - signal rtps_stage : RTPS_STAGE_TYPE := IDLE; - shared variable dds : DDS_WRITER_TEST_TYPE := DEFAULT_DDS_WRITER_TEST; - shared variable rtps : RTPS_WRITER_TEST_TYPE := DEFAULT_RTPS_WRITER_TEST; - signal inst_id, kind_id, sn_id, ts_id, data_id, ret_id, ih_id : AlertLogIDType; - - -- *FUNCTION DECLARATION* - function extract_key_hash (payload : TEST_PACKET_TYPE) return INSTANCE_HANDLE_TYPE is - variable ret : INSTANCE_HANDLE_TYPE := HANDLE_NIL; - begin - for i in 0 to 3 loop - ret(i) := not payload.data(i); - end loop; - - return ret; - end function; - - function gen_sn(input : natural) return SEQUENCENUMBER_TYPE is - variable ret : SEQUENCENUMBER_TYPE; - begin - ret(0) := (others => '0'); - ret(1) := unsigned(int(input, WORD_WIDTH)); - return ret; - end function; - -begin - - -- Unit Under Test - uut : entity work.dds_writer(arch) - generic map( - HISTORY_QOS => KEEP_ALL_HISTORY_QOS, - DEADLINE_QOS => DURATION_INFINITE, - LIFESPAN_QOS => DURATION_INFINITE, - LEASE_DURATION => DURATION_INFINITE, - WITH_KEY => TRUE, - MAX_SAMPLES => std_logic_vector(to_unsigned(4,CDR_LONG_WIDTH)), - MAX_INSTANCES => std_logic_vector(to_unsigned(3,CDR_LONG_WIDTH)), - MAX_SAMPLES_PER_INSTANCE => std_logic_vector(to_unsigned(2,CDR_LONG_WIDTH)), - PAYLOAD_FRAME_SIZE => 11 - ) - port map ( - clk => clk, - reset => reset, - time => check_time, - start_rtps => start_rtps, - opcode_rtps => opcode_rtps, - ack_rtps => ack_rtps, - done_rtps => done_rtps, - ret_rtps => ret_rtps, - seq_nr_rtps => seq_nr_rtps, - get_data_rtps => get_data_rtps, - data_out_rtps => data_out_rtps, - valid_out_rtps => valid_out_rtps, - ready_out_rtps => ready_out_rtps, - last_word_out_rtps => last_word_out_rtps, - liveliness_assertion => liveliness_assertion, - data_available => data_available, - cc_instance_handle => cc_instance_handle, - cc_kind => cc_kind, - cc_source_timestamp => cc_source_timestamp, - cc_seq_nr => cc_seq_nr, - start_dds => start_dds, - ack_dds => ack_dds, - opcode_dds => opcode_dds, - instance_handle_in_dds => instance_handle_in_dds, - source_ts_dds => source_ts_dds, - max_wait_dds => max_wait_dds, - done_dds => done_dds, - return_code_dds => return_code_dds, - ready_in_dds => ready_in_dds, - valid_in_dds => valid_in_dds, - data_in_dds => data_in_dds, - last_word_in_dds => last_word_in_dds, - ready_out_dds => ready_out_dds, - valid_out_dds => valid_out_dds, - data_out_dds => data_out_dds, - last_word_out_dds => last_word_out_dds, - status => status - ); - - stimulus_prc : process - variable RV : RandomPType; - variable kh1, kh2, kh3, kh4 : INSTANCE_HANDLE_TYPE := HANDLE_NIL; - variable cc1, cc2, cc3, cc4, cc : CACHE_CHANGE_TYPE := DEFAULT_CACHE_CHANGE; - - impure function gen_payload(key_hash : INSTANCE_HANDLE_TYPE; len : natural) return TEST_PACKET_TYPE is - variable ret : TEST_PACKET_TYPE := EMPTY_TEST_PACKET; - begin - assert (len >= 4) report "Payload length has to be at least 16 Bytes long" severity FAILURE; - - for i in 0 to len-1 loop - if (i < 4) then - -- NOTE: Beginning of payload is negated key to allow deterministic Key Hash generation from the kh_prc - ret.data(ret.length) := not key_hash(i); - else - ret.data(ret.length) := RV.RandSlv(WORD_WIDTH); - end if; - ret.length := ret.length + 1; - end loop; - ret.last(ret.length-1) := '1'; - - return ret; - end function; - - impure function gen_key_hash return KEY_HASH_TYPE is - variable ret : KEY_HASH_TYPE := KEY_HASH_NIL; - begin - for i in 0 to KEY_HASH_TYPE'length-1 loop - ret(i) := RV.RandSlv(WORD_WIDTH); - end loop; - return ret; - end function; - - procedure start_dds is - begin - dds_start <= '1'; - wait until rising_edge(clk); - dds_start <= '0'; - wait until rising_edge(clk); - end procedure; - - procedure start_rtps is - begin - rtps_start <= '1'; - wait until rising_edge(clk); - rtps_start <= '0'; - wait until rising_edge(clk); - end procedure; - - procedure wait_on_dds is - begin - if (dds_done /= '1') then - wait until dds_done = '1'; - end if; - end procedure; - - procedure wait_on_rtps is - begin - if (rtps_done /= '1') then - wait until rtps_done = '1'; - end if; - end procedure; - - procedure wait_on_completion is - begin - if (rtps_done /= '1' or dds_done /= '1') then - wait until rtps_done = '1' and dds_done = '1'; - end if; - end procedure; - - begin - - SetAlertLogName("L0_dds_writer_test2_aik - (KEEP ALL, Infinite Lifespan, Keyed) - Wait For Acknowledgements"); - SetAlertEnable(FAILURE, TRUE); - SetAlertEnable(ERROR, TRUE); - SetAlertEnable(WARNING, TRUE); - SetLogEnable(DEBUG, FALSE); - SetLogEnable(PASSED, FALSE); - SetLogEnable(INFO, TRUE); - RV.InitSeed(RV'instance_name); - inst_id <= GetAlertLogID("Instance", ALERTLOG_BASE_ID); - kind_id <= GetAlertLogID("Cache Change Kind", ALERTLOG_BASE_ID); - sn_id <= GetAlertLogID("SequenceNumber", ALERTLOG_BASE_ID); - ts_id <= GetAlertLogID("TimeStamp", ALERTLOG_BASE_ID); - ih_id <= GetAlertLogID("Instance Handle", ALERTLOG_BASE_ID); - data_id <= GetAlertLogID("Data Out", ALERTLOG_BASE_ID); - ret_id <= GetAlertLogID("Return Code", ALERTLOG_BASE_ID); - - -- Key Hashes - kh1 := gen_key_hash; - kh2 := gen_key_hash; - kh3 := gen_key_hash; - kh4 := gen_key_hash; - - - - Log("Initiating Test", INFO); - Log("Current Time: 0s", INFO); - check_time <= TIME_ZERO; - reset <= '1'; - wait until rising_edge(clk); - wait until rising_edge(clk); - reset <= '0'; - -- Stored CC: 0, 0, 0, 0 - - Log("DDS Operation WAIT_FOR_ACKNOWLEDGEMENTS [max_wait 0s] (OK)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := WAIT_FOR_ACKNOWLEDGEMENTS; - dds.ret_code := RETCODE_OK; - max_wait_dds <= gen_duration(0,0); - start_dds; - wait_on_dds; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh1; - cc.payload := gen_payload(kh1,10); - cc.seq_nr := gen_sn(1); - cc.src_timestamp := gen_duration(1,0); - - Log("DDS Operation WRITE [TS 1s, Instance 1, HANDLE_NIL, Aligned Payload] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.cc.instance:= HANDLE_NIL; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc1 := cc; - -- Stored CC: I1S1, 0, 0, 0 - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh2; - cc.payload := gen_payload(kh2,10); - cc.seq_nr := gen_sn(2); - cc.src_timestamp := gen_duration(2,0); - - Log("DDS Operation WRITE [TS 2s, Instance 2, HANDLE_NIL, Aligned Payload] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.cc.instance:= HANDLE_NIL; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc2 := cc; - -- Stored CC: I1S1, I2S2, 0, 0 - - Log("DDS Operation WAIT_FOR_ACKNOWLEDGEMENTS [max_wait 0s] (TIMEOUT)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := WAIT_FOR_ACKNOWLEDGEMENTS; - dds.ret_code := RETCODE_TIMEOUT; - max_wait_dds <= gen_duration(0,0); - start_dds; - wait_on_dds; - - Log("DDS Operation WAIT_FOR_ACKNOWLEDGEMENTS [max_wait 1s]", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := WAIT_FOR_ACKNOWLEDGEMENTS; - dds.ret_code := RETCODE_TIMEOUT; - max_wait_dds <= gen_duration(1,0); - start_dds; - - Log("RTPS Operation ACK_CACHE_CHANGE SN 1", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := ACK_CACHE_CHANGE; - rtps.cc := cc1; - start_rtps; - wait_on_rtps; - - Log("Current Time: 1s", INFO); - Log("WAIT_FOR_ACKNOWLEDGEMENTS Return (TIMEOUT)", INFO); - check_time <= gen_duration(1,0); - wait until rising_edge(clk); - wait_on_dds; - - Log("DDS Operation WAIT_FOR_ACKNOWLEDGEMENTS [max_wait 1s]", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := WAIT_FOR_ACKNOWLEDGEMENTS; - dds.ret_code := RETCODE_OK; - max_wait_dds <= gen_duration(1,0); - start_dds; - - Log("RTPS Operation ACK_CACHE_CHANGE SN 2", INFO); - Log("WAIT_FOR_ACKNOWLEDGEMENTS Return (OK)", INFO); - rtps := DEFAULT_RTPS_WRITER_TEST; - rtps.opcode := ACK_CACHE_CHANGE; - rtps.cc := cc2; - start_rtps; - wait_on_rtps; - wait_on_dds; - - wait_on_completion; - TranscriptOpen(RESULTS_FILE, APPEND_MODE); - SetTranscriptMirror; - ReportAlerts; - TranscriptClose; - std.env.stop; - wait; - end process; - - clock_prc : process - begin - clk <= '0'; - wait for 25 ns; - clk <= '1'; - wait for 25 ns; - end process; - - alert_prc : process(all) - begin - if rising_edge(clk) then - -- TODO - end if; - end process; - - dds_prc : process(all) - begin - if rising_edge(clk) then - dds_done <= '0'; - case (dds_stage) is - when IDLE => - if (dds_start = '1') then - dds_stage <= START; - else - dds_done <= '1'; - end if; - when START => - if (ack_dds = '1') then - case (dds.opcode) is - when WAIT_FOR_ACKNOWLEDGEMENTS => - dds_stage <= DONE; - dds_cnt <= 0; - when others => - dds_stage <= PUSH; - dds_cnt <= 0; - end case; - end if; - when PUSH => - if (ready_in_dds = '1') then - dds_cnt <= dds_cnt + 1; - if (dds_cnt = dds.cc.payload.length-1) then - -- DEFAULT - dds_stage <= DONE; - end if; - end if; - when DONE => - if (done_dds = '1') then - if (dds.opcode = REGISTER_INSTANCE or dds.opcode = LOOKUP_INSTANCE) then - AffirmIfEqual(ih_id, to_unsigned(instance_handle_out_dds), to_unsigned(dds.cc.instance)); - else - AffirmIfEqual(ret_id, return_code_dds, dds.ret_code); - end if; - dds_stage <= IDLE; - end if; - end case; - end if; - - -- DEFAULT - start_dds <= '0'; - opcode_dds <= NOP; - valid_in_dds <= '0'; - last_word_in_dds <= '0'; - data_in_dds <= (others => '0'); - instance_handle_in_dds <= HANDLE_NIL; - source_ts_dds <= TIME_INVALID; - ready_out_dds <= '0'; - - case (dds_stage) is - when START => - start_dds <= '1'; - opcode_dds <= dds.opcode; - instance_handle_in_dds <= dds.cc.instance; - source_ts_dds <= dds.cc.src_timestamp; - when PUSH => - valid_in_dds <= '1'; - data_in_dds <= dds.cc.payload.data(dds_cnt); - last_word_in_dds <= dds.cc.payload.last(dds_cnt); - when others => - null; - end case; - end process; - - rtps_prc : process(all) - begin - if rising_edge(clk) then - rtps_done <= '0'; - case (rtps_stage) is - when IDLE => - if (rtps_start = '1') then - rtps_stage <= START; - else - rtps_done <= '1'; - end if; - when START => - if (ack_rtps = '1') then - rtps_stage <= DONE; - end if; - when DONE => - if (done_rtps = '1') then - -- DEFAULT - rtps_stage <= IDLE; - - AffirmIfEqual(ret_id, HISTORY_CACHE_RESPONSE_TYPE'pos(ret_rtps), HISTORY_CACHE_RESPONSE_TYPE'pos(rtps.ret_code)); - case (rtps.opcode) is - when GET_CACHE_CHANGE => - if (rtps.ret_code = OK) then - AffirmIfEqual(inst_id, to_unsigned(cc_instance_handle), to_unsigned(rtps.cc.instance)); - AffirmIfEqual(kind_id, CACHE_CHANGE_KIND_TYPE'pos(cc_kind), CACHE_CHANGE_KIND_TYPE'pos(rtps.cc.kind)); - AffirmIfEqual(sn_id, to_unsigned(cc_seq_nr), to_unsigned(rtps.cc.seq_nr)); - AffirmIfEqual(ts_id, to_unsigned(cc_source_timestamp), to_unsigned(rtps.cc.src_timestamp)); - rtps_stage <= CHECK; - rtps_cnt <= 0; - end if; - when GET_MIN_SN => - AffirmIfEqual(sn_id, to_unsigned(cc_seq_nr), to_unsigned(rtps.cc.seq_nr)); - when GET_MAX_SN => - AffirmIfEqual(sn_id, to_unsigned(cc_seq_nr), to_unsigned(rtps.cc.seq_nr)); - when others => - null; - end case; - end if; - when CHECK => - if (valid_out_rtps = '1') then - AffirmIfEqual(data_id, last_word_out_rtps & data_out_rtps, rtps.cc.payload.last(rtps_cnt) & rtps.cc.payload.data(rtps_cnt)); - rtps_cnt <= rtps_cnt + 1; - if (rtps_cnt = rtps.cc.payload.length-1) then - rtps_stage <= IDLE; - end if; - end if; - end case; - end if; - - -- DEFAULT - start_rtps <= '0'; - opcode_rtps <= NOP; - seq_nr_rtps <= SEQUENCENUMBER_UNKNOWN; - get_data_rtps <= '0'; - ready_out_rtps <= '0'; - - case (rtps_stage) is - when START => - start_rtps <= '1'; - opcode_rtps <= rtps.opcode; - seq_nr_rtps <= rtps.cc.seq_nr; - when DONE => - if (done_rtps = '1') then - case (rtps.opcode) is - when GET_CACHE_CHANGE => - get_data_rtps <= '1'; - when others => - null; - end case; - end if; - when CHECK => - ready_out_rtps <= '1'; - when others => - null; - end case; - end process; - - watchdog : process - begin - wait for 1 ms; - Alert("Test timeout", FAILURE); - std.env.stop; - end process; - -end architecture; \ No newline at end of file diff --git a/src/Tests/Level_0/L0_dds_writer_test3.vhd b/src/Tests/Level_0/L0_dds_writer_test3.vhd new file mode 100644 index 0000000..ba1e5a0 --- /dev/null +++ b/src/Tests/Level_0/L0_dds_writer_test3.vhd @@ -0,0 +1,806 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library osvvm; -- Utility Library +context osvvm.OsvvmContext; + +use work.rtps_package.all; +use work.user_config.all; +use work.rtps_config_package.all; +use work.rtps_test_package.all; + +-- This testbench tests the Deadline Handling of the DDS Writer, and more specifically the GET_OFFERED_DEADLINE_MISSED_STATUS DDS Operation. + +entity L0_dds_writer_test3 is +end entity; + +architecture testbench of L0_dds_writer_test3 is + + -- *CONSTANT DECLARATION* + constant MAX_REMOTE_ENDPOINTS : natural := 3; + constant NUM_WRITERS : natural := 3; + + impure function gen_test_config return CONFIG_ARRAY_TYPE is + variable ret : CONFIG_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => DEFAULT_WRITER_CONFIG); + begin + -- aik + ret(0).HISTORY_QOS := KEEP_ALL_HISTORY_QOS; + ret(0).DEADLINE_QOS := gen_duration(1 sec); + ret(0).LIFESPAN_QOS := DURATION_INFINITE; + ret(0).LEASE_DURATION := DURATION_INFINITE; + ret(0).WITH_KEY := TRUE; + ret(0).MAX_SAMPLES := std_logic_vector(to_unsigned(4,CDR_LONG_WIDTH)); + ret(0).MAX_INSTANCES := std_logic_vector(to_unsigned(3,CDR_LONG_WIDTH)); + ret(0).MAX_SAMPLES_PER_INSTANCE := std_logic_vector(to_unsigned(2,CDR_LONG_WIDTH)); + ret(0).MAX_PAYLOAD_SIZE := 40; + -- ain + ret(1).HISTORY_QOS := KEEP_ALL_HISTORY_QOS; + ret(1).DEADLINE_QOS := gen_duration(1 sec); + ret(1).LIFESPAN_QOS := DURATION_INFINITE; + ret(1).LEASE_DURATION := DURATION_INFINITE; + ret(1).WITH_KEY := FALSE; + ret(1).MAX_SAMPLES := std_logic_vector(to_unsigned(4,CDR_LONG_WIDTH)); + ret(1).MAX_INSTANCES := std_logic_vector(to_unsigned(3,CDR_LONG_WIDTH)); + ret(1).MAX_SAMPLES_PER_INSTANCE := std_logic_vector(to_unsigned(4,CDR_LONG_WIDTH)); + ret(1).MAX_PAYLOAD_SIZE := 40; + -- aik + ret(2).HISTORY_QOS := KEEP_ALL_HISTORY_QOS; + ret(2).DEADLINE_QOS := gen_duration(2 sec); + ret(2).LIFESPAN_QOS := DURATION_INFINITE; + ret(2).LEASE_DURATION := DURATION_INFINITE; + ret(2).WITH_KEY := TRUE; + ret(2).MAX_SAMPLES := std_logic_vector(to_unsigned(4,CDR_LONG_WIDTH)); + ret(2).MAX_INSTANCES := std_logic_vector(to_unsigned(3,CDR_LONG_WIDTH)); + ret(2).MAX_SAMPLES_PER_INSTANCE := std_logic_vector(to_unsigned(2,CDR_LONG_WIDTH)); + ret(2).MAX_PAYLOAD_SIZE := 40; + return ret; + end function; + constant TEST_CONFIG : CONFIG_ARRAY_TYPE := gen_test_config; + + -- *TYPE DECLARATION* + type DDS_STAGE_TYPE is (IDLE, START, PUSH, DONE, CHECK_DEADLINE); + type RTPS_STAGE_TYPE is (IDLE, START, DONE, CHECK); + + -- *SIGNAL DECLARATION* + signal clk : std_logic := '0'; + signal reset : std_logic := '1'; + signal check_time : TIME_TYPE := TIME_ZERO; + signal start_rtps, start_dds, ack_rtps, ack_dds, done_rtps, done_dds, w_map : std_logic_vector(0 to NUM_WRITERS-1) := (others => '0'); + signal opcode_rtps : HISTORY_CACHE_OPCODE_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => NOP); + signal opcode_dds : DDS_WRITER_OPCODE_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => NOP); + signal ret_rtps : HISTORY_CACHE_RESPONSE_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => ERROR); + signal seq_nr_rtps, cc_seq_nr : SEQUENCENUMBER_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => SEQUENCENUMBER_UNKNOWN); + signal ready_out_rtps, valid_out_rtps, last_word_out_rtps : std_logic_vector(0 to NUM_WRITERS-1) := (others => '0'); + signal ready_in_dds, ready_out_dds, valid_in_dds, valid_out_dds, last_word_in_dds, last_word_out_dds : std_logic_vector(0 to NUM_WRITERS-1) := (others => '0'); + signal data_out_rtps, data_in_dds, data_out_dds : WORD_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => (others => '0')); + signal get_data_rtps, liveliness_assertion, data_available : std_logic_vector(0 to NUM_WRITERS-1) := (others => '0'); + signal cc_source_timestamp, source_ts_dds : TIME_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => TIME_INVALID); + signal cc_kind : CACHE_CHANGE_KIND_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => ALIVE); + signal cc_instance_handle, instance_handle_in_dds, instance_handle_out_dds : INSTANCE_HANDLE_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => HANDLE_NIL); + signal max_wait_dds : DURATION_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => DURATION_INFINITE); + signal return_code_dds : RETURN_CODE_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => (others => '0')); + signal status : STATUS_KIND_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => (others => '0')); + + signal ind : natural := 0; + signal dds_start, dds_done, rtps_start, rtps_done : std_logic := '0'; + signal dds_cnt, rtps_cnt : natural := 0; + signal dds_stage : DDS_STAGE_TYPE := IDLE; + signal rtps_stage : RTPS_STAGE_TYPE := IDLE; + shared variable dds : DDS_WRITER_TEST_TYPE := DEFAULT_DDS_WRITER_TEST; + shared variable rtps : RTPS_WRITER_TEST_TYPE := DEFAULT_RTPS_WRITER_TEST; + signal inst_id, kind_id, sn_id, ts_id, data_id, ret_id, status_id, ih_id : AlertLogIDType; + + -- *FUNCTION DECLARATION* + function extract_key_hash (payload : TEST_PACKET_TYPE) return INSTANCE_HANDLE_TYPE is + variable ret : INSTANCE_HANDLE_TYPE := HANDLE_NIL; + begin + for i in 0 to 3 loop + ret(i) := not payload.data(i); + end loop; + + return ret; + end function; + + function gen_sn(input : natural) return SEQUENCENUMBER_TYPE is + variable ret : SEQUENCENUMBER_TYPE; + begin + ret(0) := (others => '0'); + ret(1) := unsigned(int(input, WORD_WIDTH)); + return ret; + end function; + + procedure wait_on_sig(signal sig : std_logic) is + begin + if (sig /= '1') then + wait on sig until sig = '1'; + end if; + end procedure; + +begin + + -- Unit Under Test + uut : entity work.dds_writer(arch) + generic map( + NUM_WRITERS => NUM_WRITERS, + CONFIG_ARRAY => to_QUARTUS_CONFIG_ARRAY_TYPE(TEST_CONFIG) + ) + port map ( + clk => clk, + reset => reset, + time => check_time, + start_rtps => start_rtps, + opcode_rtps => opcode_rtps, + ack_rtps => ack_rtps, + done_rtps => done_rtps, + ret_rtps => ret_rtps, + seq_nr_rtps => seq_nr_rtps, + get_data_rtps => get_data_rtps, + data_out_rtps => data_out_rtps, + valid_out_rtps => valid_out_rtps, + ready_out_rtps => ready_out_rtps, + last_word_out_rtps => last_word_out_rtps, + liveliness_assertion => liveliness_assertion, + data_available => data_available, + cc_instance_handle => cc_instance_handle, + cc_kind => cc_kind, + cc_source_timestamp => cc_source_timestamp, + cc_seq_nr => cc_seq_nr, + start_dds => start_dds, + ack_dds => ack_dds, + opcode_dds => opcode_dds, + instance_handle_in_dds => instance_handle_in_dds, + source_ts_dds => source_ts_dds, + max_wait_dds => max_wait_dds, + done_dds => done_dds, + return_code_dds => return_code_dds, + instance_handle_out_dds => instance_handle_out_dds, + ready_in_dds => ready_in_dds, + valid_in_dds => valid_in_dds, + data_in_dds => data_in_dds, + last_word_in_dds => last_word_in_dds, + ready_out_dds => ready_out_dds, + valid_out_dds => valid_out_dds, + data_out_dds => data_out_dds, + last_word_out_dds => last_word_out_dds, + status => status + ); + + stimulus_prc : process + variable RV : RandomPType; + variable kh1, kh2, kh3, kh4 : INSTANCE_HANDLE_TYPE := HANDLE_NIL; + variable cc : CACHE_CHANGE_TYPE := DEFAULT_CACHE_CHANGE; + + alias idle_sig is <>; + + impure function gen_payload(key_hash : INSTANCE_HANDLE_TYPE; len : natural) return TEST_PACKET_TYPE is + variable ret : TEST_PACKET_TYPE := EMPTY_TEST_PACKET; + begin + assert (len >= 4) report "Payload length has to be at least 16 Bytes long" severity FAILURE; + + for i in 0 to len-1 loop + if (i < 4) then + -- NOTE: Beginning of payload is negated key to allow deterministic Key Hash generation from the kh_prc + ret.data(ret.length) := not key_hash(i); + else + ret.data(ret.length) := RV.RandSlv(WORD_WIDTH); + end if; + ret.length := ret.length + 1; + end loop; + ret.last(ret.length-1) := '1'; + + return ret; + end function; + + impure function gen_key_hash return KEY_HASH_TYPE is + variable ret : KEY_HASH_TYPE := KEY_HASH_NIL; + begin + for i in 0 to KEY_HASH_TYPE'length-1 loop + ret(i) := RV.RandSlv(WORD_WIDTH); + end loop; + return ret; + end function; + + procedure start_dds is + begin + dds_start <= '1'; + wait until rising_edge(clk); + dds_start <= '0'; + wait until rising_edge(clk); + end procedure; + + procedure start_rtps is + begin + rtps_start <= '1'; + wait until rising_edge(clk); + rtps_start <= '0'; + wait until rising_edge(clk); + end procedure; + + procedure wait_on_completion is + begin + if (rtps_done /= '1' or dds_done /= '1') then + wait until rtps_done = '1' and dds_done = '1'; + end if; + end procedure; + + -- NOTE: This procedure waits until the idle_sig is high for at least + -- two consecutive clock cycles. + procedure wait_on_idle is + variable first : boolean := TRUE; + begin + loop + if (idle_sig /= '1') then + wait until idle_sig = '1'; + elsif (not first) then + exit; + end if; + wait until rising_edge(clk); + wait until rising_edge(clk); + first := FALSE; + end loop; + end procedure; + + begin + + SetAlertLogName("L0_dds_writer_test3 - Deadline Handling"); + SetAlertEnable(FAILURE, TRUE); + SetAlertEnable(ERROR, TRUE); + SetAlertEnable(WARNING, TRUE); + SetLogEnable(DEBUG, FALSE); + SetLogEnable(PASSED, FALSE); + SetLogEnable(INFO, TRUE); + RV.InitSeed(RV'instance_name); + inst_id <= GetAlertLogID("Instance", ALERTLOG_BASE_ID); + kind_id <= GetAlertLogID("Cache Change Kind", ALERTLOG_BASE_ID); + sn_id <= GetAlertLogID("SequenceNumber", ALERTLOG_BASE_ID); + ts_id <= GetAlertLogID("TimeStamp", ALERTLOG_BASE_ID); + ih_id <= GetAlertLogID("Instance Handle", ALERTLOG_BASE_ID); + data_id <= GetAlertLogID("Data Out", ALERTLOG_BASE_ID); + ret_id <= GetAlertLogID("Return Code", ALERTLOG_BASE_ID); + status_id <= GetAlertLogID("Communication Status", ALERTLOG_BASE_ID); + + -- Key Hashes + kh1 := gen_key_hash; + kh2 := gen_key_hash; + kh3 := gen_key_hash; + kh4 := gen_key_hash; + + + + Log("Initiating Test", INFO); + Log("Current Time: 0s", INFO); + check_time <= TIME_ZERO; + reset <= '1'; + wait until rising_edge(clk); + wait until rising_edge(clk); + reset <= '0'; + wait_on_idle; + + AffirmIf(status_id,(status(0) and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(1) and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(2) and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1"); + + Log("Current Time: 1s", INFO); + check_time <= gen_duration(1 sec); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait_on_idle; + + AffirmIf(status_id,(status(0) and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(1) and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(2) and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1"); + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh1; + cc.payload := gen_payload(kh1,10); + + Log("W0,W1,W2: DDS Operation WRITE [Instance 1, HANDLE_NIL, Aligned Payload]", INFO); + Log("W0,W1,W2: ACCEPTED", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := WRITE; + dds.cc := cc; + dds.cc.instance:= HANDLE_NIL; + dds.ret_code := RETCODE_OK; + -- WRITER 0 + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- WRITER 1 + ind <= 1; + start_dds; + wait_on_sig(dds_done); + -- WRITER 2 + ind <= 2; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh2; + cc.payload := gen_payload(kh2,10); + + Log("W0,W2: DDS Operation WRITE [Instance 2, HANDLE_NIL, Aligned Payload]", INFO); + Log("W0,W2: ACCEPTED", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := WRITE; + dds.cc := cc; + dds.cc.instance:= HANDLE_NIL; + dds.ret_code := RETCODE_OK; + -- WRITER 0 + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- WRITER 2 + ind <= 2; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + + Log("Current Time: 2s", INFO); + check_time <= gen_duration(2 sec); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait_on_idle; + + AffirmIf(status_id,(status(0) and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(1) and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(2) and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1"); + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh1; + cc.payload := gen_payload(kh1,10); + + Log("W0,W2: DDS Operation WRITE [Instance 1, Aligned Payload]", INFO); + Log("W0,W2: ACCEPTED", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := WRITE; + dds.cc := cc; + dds.cc.instance:= HANDLE_NIL; + dds.ret_code := RETCODE_OK; + -- WRITER 0 + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- WRITER 2 + ind <= 2; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + + Log("Current Time: 3s", INFO); + check_time <= gen_duration(3 sec); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait_on_idle; + + AffirmIf(status_id,(status(0) and OFFERED_DEADLINE_MISSED_STATUS) = OFFERED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(1) and OFFERED_DEADLINE_MISSED_STATUS) = OFFERED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(2) and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1"); + + Log("W0: DDS Operation GET_OFFERED_DEADLINE_MISSED_STATUS", INFO); + Log("W0: Expected [count 1, change 1, Instance 2]", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := GET_OFFERED_DEADLINE_MISSED_STATUS; + dds.ret_code := RETCODE_OK; + dds.count := 1; + dds.change := 1; + dds.inst := kh2; + -- WRITER 0 + ind <= 0; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + + AffirmIf(status_id,(status(0) and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(1) and OFFERED_DEADLINE_MISSED_STATUS) = OFFERED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(2) and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1"); + + Log("W1: DDS Operation GET_OFFERED_DEADLINE_MISSED_STATUS", INFO); + Log("W1: Expected [count 1, change 1]", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := GET_OFFERED_DEADLINE_MISSED_STATUS; + dds.ret_code := RETCODE_OK; + dds.count := 1; + dds.change := 1; + dds.inst := HANDLE_NIL; + -- WRITER 1 + ind <= 1; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + + AffirmIf(status_id,(status(0) and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(1) and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(2) and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1"); + + Log("W2: DDS Operation GET_OFFERED_DEADLINE_MISSED_STATUS", INFO); + Log("W2: Expected [count 0, change 0, HANDLE_NIL]", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := GET_OFFERED_DEADLINE_MISSED_STATUS; + dds.ret_code := RETCODE_OK; + dds.count := 0; + dds.change := 0; + dds.inst := HANDLE_NIL; + -- WRITER 2 + ind <= 2; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + + AffirmIf(status_id,(status(0) and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(1) and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(2) and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1"); + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh3; + cc.payload := gen_payload(kh3,10); + + Log("W0,W2: DDS Operation WRITE [Instance 3, Aligned Payload]", INFO); + Log("W0,W2: ACCEPTED", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := WRITE; + dds.cc := cc; + dds.cc.instance:= HANDLE_NIL; + dds.ret_code := RETCODE_OK; + -- WRITER 0 + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- WRITER 2 + ind <= 2; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + + Log("Current Time: 4s", INFO); + check_time <= gen_duration(4 sec); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait_on_idle; + + AffirmIf(status_id,(status(0) and OFFERED_DEADLINE_MISSED_STATUS) = OFFERED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(1) and OFFERED_DEADLINE_MISSED_STATUS) = OFFERED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(2) and OFFERED_DEADLINE_MISSED_STATUS) = OFFERED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0"); + + Log("W0: DDS Operation GET_OFFERED_DEADLINE_MISSED_STATUS", INFO); + Log("W0: Expected [count 3, change 2, Instance 1]", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := GET_OFFERED_DEADLINE_MISSED_STATUS; + dds.ret_code := RETCODE_OK; + dds.count := 3; + dds.change := 2; + dds.inst := kh1; + -- WRITER 0 + ind <= 0; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + + AffirmIf(status_id,(status(0) and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(1) and OFFERED_DEADLINE_MISSED_STATUS) = OFFERED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(2) and OFFERED_DEADLINE_MISSED_STATUS) = OFFERED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0"); + + Log("W2: DDS Operation GET_OFFERED_DEADLINE_MISSED_STATUS", INFO); + Log("W2: Expected [count 1, change 1, Instance 2]", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := GET_OFFERED_DEADLINE_MISSED_STATUS; + dds.ret_code := RETCODE_OK; + dds.count := 1; + dds.change := 1; + dds.inst := kh2; + -- WRITER 2 + ind <= 2; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + + AffirmIf(status_id,(status(0) and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(1) and OFFERED_DEADLINE_MISSED_STATUS) = OFFERED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(2) and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1"); + + Log("Current Time: 5s", INFO); + check_time <= gen_duration(5 sec); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait_on_idle; + + AffirmIf(status_id,(status(0) and OFFERED_DEADLINE_MISSED_STATUS) = OFFERED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(1) and OFFERED_DEADLINE_MISSED_STATUS) = OFFERED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(2) and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1"); + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh1; + cc.payload := gen_payload(kh1,10); + + Log("W1: DDS Operation WRITE [Instance 1, Aligned Payload]", INFO); + Log("W1: ACCEPTED", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := WRITE; + dds.cc := cc; + dds.cc.instance:= HANDLE_NIL; + dds.ret_code := RETCODE_OK; + -- WRITER 1 + ind <= 1; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + + Log("Current Time: 6s", INFO); + check_time <= gen_duration(6 sec); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait_on_idle; + + AffirmIf(status_id,(status(0) and OFFERED_DEADLINE_MISSED_STATUS) = OFFERED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(1) and OFFERED_DEADLINE_MISSED_STATUS) = OFFERED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(2) and OFFERED_DEADLINE_MISSED_STATUS) = OFFERED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0"); + + Log("W0: DDS Operation GET_OFFERED_DEADLINE_MISSED_STATUS", INFO); + Log("W0: Expected [count 9, change 6, Instance 1]", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := GET_OFFERED_DEADLINE_MISSED_STATUS; + dds.ret_code := RETCODE_OK; + dds.count := 9; + dds.change := 6; + dds.inst := kh1; + -- WRITER 0 + ind <= 0; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + + AffirmIf(status_id,(status(0) and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(1) and OFFERED_DEADLINE_MISSED_STATUS) = OFFERED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(2) and OFFERED_DEADLINE_MISSED_STATUS) = OFFERED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0"); + + Log("W1: DDS Operation GET_OFFERED_DEADLINE_MISSED_STATUS", INFO); + Log("W1: Expected [count 3, change 2]", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := GET_OFFERED_DEADLINE_MISSED_STATUS; + dds.ret_code := RETCODE_OK; + dds.count := 3; + dds.change := 2; + dds.inst := HANDLE_NIL; + -- WRITER 1 + ind <= 1; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + + AffirmIf(status_id,(status(0) and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(1) and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(2) and OFFERED_DEADLINE_MISSED_STATUS) = OFFERED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0"); + + Log("W2: DDS Operation GET_OFFERED_DEADLINE_MISSED_STATUS", INFO); + Log("W2: Expected [count 4, change 3, Instance 1]", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := GET_OFFERED_DEADLINE_MISSED_STATUS; + dds.ret_code := RETCODE_OK; + dds.count := 4; + dds.change := 3; + dds.inst := kh1; + -- WRITER 2 + ind <= 2; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + + AffirmIf(status_id,(status(0) and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(1) and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(2) and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1"); + + wait_on_completion; + TranscriptOpen(RESULTS_FILE, APPEND_MODE); + SetTranscriptMirror; + ReportAlerts; + TranscriptClose; + std.env.stop; + wait; + end process; + + clock_prc : process + begin + clk <= '0'; + wait for 25 ns; + clk <= '1'; + wait for 25 ns; + end process; + + dds_prc : process(all) + begin + if rising_edge(clk) then + dds_done <= '0'; + case (dds_stage) is + when IDLE => + if (dds_start = '1') then + dds_stage <= START; + else + dds_done <= '1'; + end if; + when START => + if (ack_dds(ind) = '1') then + case (dds.opcode) is + when GET_OFFERED_DEADLINE_MISSED_STATUS => + dds_stage <= DONE; + dds_cnt <= 0; + when others => + dds_stage <= PUSH; + dds_cnt <= 0; + end case; + end if; + when PUSH => + if (ready_in_dds(ind) = '1') then + dds_cnt <= dds_cnt + 1; + if (dds_cnt = dds.cc.payload.length-1) then + -- DEFAULT + dds_stage <= DONE; + end if; + end if; + when DONE => + if (done_dds(ind) = '1') then + if (dds.opcode = REGISTER_INSTANCE or dds.opcode = LOOKUP_INSTANCE) then + AffirmIfEqual(ih_id, to_unsigned(instance_handle_out_dds(ind)), to_unsigned(dds.cc.instance)); + else + AffirmIfEqual(ret_id, return_code_dds(ind), dds.ret_code); + case (dds.opcode) is + when GET_OFFERED_DEADLINE_MISSED_STATUS => + if (dds.ret_code = RETCODE_OK) then + dds_stage <= CHECK_DEADLINE; + dds_cnt <= 0; + else + dds_stage <= IDLE; + end if; + when others => + dds_stage <= IDLE; + end case; + end if; + end if; + when CHECK_DEADLINE => + if (valid_out_dds(ind) = '1') then + dds_cnt <= dds_cnt + 1; + case (dds_cnt) is + when 0 => + AffirmIfEqual(data_id, data_out_dds(ind), std_logic_vector(to_unsigned(dds.count,CDR_LONG_WIDTH))); + when 1 => + AffirmIfEqual(data_id, data_out_dds(ind), std_logic_vector(to_unsigned(dds.change,CDR_LONG_WIDTH))); + when 2 => + AffirmIfEqual(data_id, data_out_dds(ind), std_logic_vector(dds.inst(0))); + when 3 => + AffirmIfEqual(data_id, data_out_dds(ind), std_logic_vector(dds.inst(1))); + when 4 => + AffirmIfEqual(data_id, data_out_dds(ind), std_logic_vector(dds.inst(2))); + when 5 => + AffirmIfEqual(data_id, data_out_dds(ind), std_logic_vector(dds.inst(3))); + AlertIf(data_id, last_word_out_dds(ind) /= '1', "Last Word Signal not pulled High", ERROR); + dds_stage <= IDLE; + when others => + null; + end case; + end if; + end case; + end if; + + -- DEFAULT + start_dds <= (others => '0'); + opcode_dds <= (others => NOP); + valid_in_dds <= (others => '0'); + last_word_in_dds <= (others => '0'); + data_in_dds <= (others => (others => '0')); + instance_handle_in_dds <= (others => HANDLE_NIL); + source_ts_dds <= (others => TIME_INVALID); + ready_out_dds <= (others => '0'); + + case (dds_stage) is + when START => + start_dds(ind) <= '1'; + opcode_dds(ind) <= dds.opcode; + instance_handle_in_dds(ind) <= dds.cc.instance; + source_ts_dds(ind) <= dds.cc.src_timestamp; + when PUSH => + valid_in_dds(ind) <= '1'; + data_in_dds(ind) <= dds.cc.payload.data(dds_cnt); + last_word_in_dds(ind) <= dds.cc.payload.last(dds_cnt); + when CHECK_DEADLINE => + ready_out_dds(ind) <= '1'; + when others => + null; + end case; + end process; + + rtps_prc : process(all) + begin + if rising_edge(clk) then + rtps_done <= '0'; + case (rtps_stage) is + when IDLE => + if (rtps_start = '1') then + rtps_stage <= START; + else + rtps_done <= '1'; + end if; + when START => + if (ack_rtps(ind) = '1') then + rtps_stage <= DONE; + end if; + when DONE => + if (done_rtps(ind) = '1') then + -- DEFAULT + rtps_stage <= IDLE; + + AffirmIfEqual(ret_id, HISTORY_CACHE_RESPONSE_TYPE'pos(ret_rtps(ind)), HISTORY_CACHE_RESPONSE_TYPE'pos(rtps.ret_code)); + case (rtps.opcode) is + when GET_CACHE_CHANGE => + if (rtps.ret_code = OK) then + AffirmIfEqual(inst_id, to_unsigned(cc_instance_handle(ind)), to_unsigned(rtps.cc.instance)); + AffirmIfEqual(kind_id, CACHE_CHANGE_KIND_TYPE'pos(cc_kind(ind)), CACHE_CHANGE_KIND_TYPE'pos(rtps.cc.kind)); + AffirmIfEqual(sn_id, to_unsigned(cc_seq_nr(ind)), to_unsigned(rtps.cc.seq_nr)); + AffirmIfEqual(ts_id, to_unsigned(cc_source_timestamp(ind)), to_unsigned(rtps.cc.src_timestamp)); + rtps_stage <= CHECK; + rtps_cnt <= 0; + end if; + when GET_MIN_SN => + AffirmIfEqual(sn_id, to_unsigned(cc_seq_nr(ind)), to_unsigned(rtps.cc.seq_nr)); + when GET_MAX_SN => + AffirmIfEqual(sn_id, to_unsigned(cc_seq_nr(ind)), to_unsigned(rtps.cc.seq_nr)); + when others => + null; + end case; + end if; + when CHECK => + if (valid_out_rtps(ind) = '1') then + AffirmIfEqual(data_id, last_word_out_rtps(ind) & data_out_rtps(ind), rtps.cc.payload.last(rtps_cnt) & rtps.cc.payload.data(rtps_cnt)); + rtps_cnt <= rtps_cnt + 1; + if (rtps_cnt = rtps.cc.payload.length-1) then + rtps_stage <= IDLE; + end if; + end if; + end case; + end if; + + -- DEFAULT + start_rtps <= (others => '0'); + opcode_rtps <= (others => NOP); + seq_nr_rtps <= (others => SEQUENCENUMBER_UNKNOWN); + get_data_rtps <= (others => '0'); + ready_out_rtps <= (others => '0'); + + case (rtps_stage) is + when START => + start_rtps(ind) <= '1'; + opcode_rtps(ind) <= rtps.opcode; + seq_nr_rtps(ind) <= rtps.cc.seq_nr; + when DONE => + if (done_rtps(ind) = '1') then + case (rtps.opcode) is + when GET_CACHE_CHANGE => + get_data_rtps(ind) <= '1'; + when others => + null; + end case; + end if; + when CHECK => + ready_out_rtps(ind) <= '1'; + when others => + null; + end case; + end process; + + watchdog : process + begin + wait for 1 ms; + Alert("Test timeout", FAILURE); + std.env.stop; + end process; + +end architecture; \ No newline at end of file diff --git a/src/Tests/Level_0/L0_dds_writer_test3_aik.vhd b/src/Tests/Level_0/L0_dds_writer_test3_aik.vhd deleted file mode 100644 index fb779fe..0000000 --- a/src/Tests/Level_0/L0_dds_writer_test3_aik.vhd +++ /dev/null @@ -1,628 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library osvvm; -- Utility Library -context osvvm.OsvvmContext; - -use work.rtps_package.all; -use work.user_config.all; -use work.rtps_config_package.all; -use work.rtps_test_package.all; - --- This testbench tests the Deadline Handling of the DDS Writer, and more specifically the GET_OFFERED_DEADLINE_MISSED_STATUS DDS Operation. - -entity L0_dds_writer_test3_aik is -end entity; - -architecture testbench of L0_dds_writer_test3_aik is - - -- *CONSTANT DECLARATION* - constant MAX_REMOTE_ENDPOINTS : natural := 3; - - -- *TYPE DECLARATION* - type DDS_STAGE_TYPE is (IDLE, START, PUSH, DONE, CHECK_DEADLINE); - type RTPS_STAGE_TYPE is (IDLE, START, DONE, CHECK); - - -- *SIGNAL DECLARATION* - signal clk : std_logic := '0'; - signal reset : std_logic := '1'; - signal check_time : TIME_TYPE := TIME_ZERO; - signal start_rtps, start_dds, ack_rtps, ack_dds, done_rtps, done_dds : std_logic := '0'; - signal opcode_rtps : HISTORY_CACHE_OPCODE_TYPE := NOP; - signal opcode_dds : DDS_WRITER_OPCODE_TYPE := NOP; - signal ret_rtps : HISTORY_CACHE_RESPONSE_TYPE := ERROR; - signal seq_nr_rtps, cc_seq_nr : SEQUENCENUMBER_TYPE := SEQUENCENUMBER_UNKNOWN; - signal ready_out_rtps, valid_out_rtps, last_word_out_rtps : std_logic := '0'; - signal ready_in_dds, ready_out_dds, valid_in_dds, valid_out_dds, last_word_in_dds, last_word_out_dds : std_logic := '0'; - signal data_out_rtps, data_in_dds, data_out_dds : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); - signal get_data_rtps, liveliness_assertion, data_available : std_logic := '0'; - signal cc_source_timestamp, source_ts_dds : TIME_TYPE := TIME_INVALID; - signal cc_kind : CACHE_CHANGE_KIND_TYPE := ALIVE; - signal cc_instance_handle, instance_handle_in_dds, instance_handle_out_dds : INSTANCE_HANDLE_TYPE := HANDLE_NIL; - signal max_wait_dds : DURATION_TYPE := DURATION_INFINITE; - signal return_code_dds : std_logic_vector(RETURN_CODE_WIDTH-1 downto 0) := (others => '0'); - signal status : std_logic_vector(STATUS_KIND_WIDTH-1 downto 0) := (others => '0'); - - signal dds_start, dds_done, rtps_start, rtps_done : std_logic := '0'; - signal dds_cnt, rtps_cnt : natural := 0; - signal dds_stage : DDS_STAGE_TYPE := IDLE; - signal rtps_stage : RTPS_STAGE_TYPE := IDLE; - shared variable dds : DDS_WRITER_TEST_TYPE := DEFAULT_DDS_WRITER_TEST; - shared variable rtps : RTPS_WRITER_TEST_TYPE := DEFAULT_RTPS_WRITER_TEST; - signal inst_id, kind_id, sn_id, ts_id, data_id, ret_id, status_id, ih_id : AlertLogIDType; - - -- *FUNCTION DECLARATION* - function extract_key_hash (payload : TEST_PACKET_TYPE) return INSTANCE_HANDLE_TYPE is - variable ret : INSTANCE_HANDLE_TYPE := HANDLE_NIL; - begin - for i in 0 to 3 loop - ret(i) := not payload.data(i); - end loop; - - return ret; - end function; - - function gen_sn(input : natural) return SEQUENCENUMBER_TYPE is - variable ret : SEQUENCENUMBER_TYPE; - begin - ret(0) := (others => '0'); - ret(1) := unsigned(int(input, WORD_WIDTH)); - return ret; - end function; - -begin - - -- Unit Under Test - uut : entity work.dds_writer(arch) - generic map( - HISTORY_QOS => KEEP_ALL_HISTORY_QOS, - DEADLINE_QOS => gen_duration(1,0), - LIFESPAN_QOS => DURATION_INFINITE, - LEASE_DURATION => DURATION_INFINITE, - WITH_KEY => TRUE, - MAX_SAMPLES => std_logic_vector(to_unsigned(4,CDR_LONG_WIDTH)), - MAX_INSTANCES => std_logic_vector(to_unsigned(3,CDR_LONG_WIDTH)), - MAX_SAMPLES_PER_INSTANCE => std_logic_vector(to_unsigned(2,CDR_LONG_WIDTH)), - PAYLOAD_FRAME_SIZE => 11 - ) - port map ( - clk => clk, - reset => reset, - time => check_time, - start_rtps => start_rtps, - opcode_rtps => opcode_rtps, - ack_rtps => ack_rtps, - done_rtps => done_rtps, - ret_rtps => ret_rtps, - seq_nr_rtps => seq_nr_rtps, - get_data_rtps => get_data_rtps, - data_out_rtps => data_out_rtps, - valid_out_rtps => valid_out_rtps, - ready_out_rtps => ready_out_rtps, - last_word_out_rtps => last_word_out_rtps, - liveliness_assertion => liveliness_assertion, - data_available => data_available, - cc_instance_handle => cc_instance_handle, - cc_kind => cc_kind, - cc_source_timestamp => cc_source_timestamp, - cc_seq_nr => cc_seq_nr, - start_dds => start_dds, - ack_dds => ack_dds, - opcode_dds => opcode_dds, - instance_handle_in_dds => instance_handle_in_dds, - source_ts_dds => source_ts_dds, - max_wait_dds => max_wait_dds, - done_dds => done_dds, - return_code_dds => return_code_dds, - instance_handle_out_dds => instance_handle_out_dds, - ready_in_dds => ready_in_dds, - valid_in_dds => valid_in_dds, - data_in_dds => data_in_dds, - last_word_in_dds => last_word_in_dds, - ready_out_dds => ready_out_dds, - valid_out_dds => valid_out_dds, - data_out_dds => data_out_dds, - last_word_out_dds => last_word_out_dds, - status => status - ); - - stimulus_prc : process - variable RV : RandomPType; - variable kh1, kh2, kh3, kh4 : INSTANCE_HANDLE_TYPE := HANDLE_NIL; - variable cc1, cc2, cc3, cc4, cc : CACHE_CHANGE_TYPE := DEFAULT_CACHE_CHANGE; - - alias idle_sig is <>; - - impure function gen_payload(key_hash : INSTANCE_HANDLE_TYPE; len : natural) return TEST_PACKET_TYPE is - variable ret : TEST_PACKET_TYPE := EMPTY_TEST_PACKET; - begin - assert (len >= 4) report "Payload length has to be at least 16 Bytes long" severity FAILURE; - - for i in 0 to len-1 loop - if (i < 4) then - -- NOTE: Beginning of payload is negated key to allow deterministic Key Hash generation from the kh_prc - ret.data(ret.length) := not key_hash(i); - else - ret.data(ret.length) := RV.RandSlv(WORD_WIDTH); - end if; - ret.length := ret.length + 1; - end loop; - ret.last(ret.length-1) := '1'; - - return ret; - end function; - - impure function gen_key_hash return KEY_HASH_TYPE is - variable ret : KEY_HASH_TYPE := KEY_HASH_NIL; - begin - for i in 0 to KEY_HASH_TYPE'length-1 loop - ret(i) := RV.RandSlv(WORD_WIDTH); - end loop; - return ret; - end function; - - procedure start_dds is - begin - dds_start <= '1'; - wait until rising_edge(clk); - dds_start <= '0'; - wait until rising_edge(clk); - end procedure; - - procedure start_rtps is - begin - rtps_start <= '1'; - wait until rising_edge(clk); - rtps_start <= '0'; - wait until rising_edge(clk); - end procedure; - - procedure wait_on_dds is - begin - if (dds_done /= '1') then - wait until dds_done = '1'; - end if; - end procedure; - - procedure wait_on_rtps is - begin - if (rtps_done /= '1') then - wait until rtps_done = '1'; - end if; - end procedure; - - procedure wait_on_completion is - begin - if (rtps_done /= '1' or dds_done /= '1') then - wait until rtps_done = '1' and dds_done = '1'; - end if; - end procedure; - - -- NOTE: This procedure waits until the idle_sig is high for at least - -- two consecutive clock cycles. - procedure wait_on_idle is - begin - loop - if (idle_sig /= '1') then - wait until idle_sig = '1'; - else - exit; - end if; - wait until rising_edge(clk); - wait until rising_edge(clk); - end loop; - end procedure; - - begin - - SetAlertLogName("L0_dds_writer_test3_aik - (KEEP ALL, Infinite Lifespan, Keyed) - Deadline Handling"); - SetAlertEnable(FAILURE, TRUE); - SetAlertEnable(ERROR, TRUE); - SetAlertEnable(WARNING, TRUE); - SetLogEnable(DEBUG, FALSE); - SetLogEnable(PASSED, FALSE); - SetLogEnable(INFO, TRUE); - RV.InitSeed(RV'instance_name); - inst_id <= GetAlertLogID("Instance", ALERTLOG_BASE_ID); - kind_id <= GetAlertLogID("Cache Change Kind", ALERTLOG_BASE_ID); - sn_id <= GetAlertLogID("SequenceNumber", ALERTLOG_BASE_ID); - ts_id <= GetAlertLogID("TimeStamp", ALERTLOG_BASE_ID); - ih_id <= GetAlertLogID("Instance Handle", ALERTLOG_BASE_ID); - data_id <= GetAlertLogID("Data Out", ALERTLOG_BASE_ID); - ret_id <= GetAlertLogID("Return Code", ALERTLOG_BASE_ID); - status_id <= GetAlertLogID("Communication Status", ALERTLOG_BASE_ID); - - -- Key Hashes - kh1 := gen_key_hash; - kh2 := gen_key_hash; - kh3 := gen_key_hash; - kh4 := gen_key_hash; - - - - Log("Initiating Test", INFO); - Log("Current Time: 0s", INFO); - check_time <= TIME_ZERO; - reset <= '1'; - wait until rising_edge(clk); - wait until rising_edge(clk); - reset <= '0'; - wait_on_idle; - -- Stored CC: 0, 0, 0, 0 - - AffirmIf(status_id,(status and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1"); - - Log("Current Time: 1s", INFO); - check_time <= gen_duration(1,0); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait_on_idle; - - AffirmIf(status_id,(status and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh1; - cc.payload := gen_payload(kh1,10); - cc.seq_nr := gen_sn(1); - - Log("DDS Operation WRITE [Instance 1, HANDLE_NIL, Aligned Payload] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.cc.instance:= HANDLE_NIL; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc1 := cc; - -- Stored CC: I1S1, 0, 0, 0 - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh2; - cc.payload := gen_payload(kh2,10); - cc.seq_nr := gen_sn(2); - - Log("DDS Operation WRITE [Instance 2, HANDLE_NIL, Aligned Payload] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.cc.instance:= HANDLE_NIL; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc2 := cc; - -- Stored CC: I1S1, I2S2, 0, 0 - - Log("Current Time: 2s", INFO); - check_time <= gen_duration(2,0); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait_on_idle; - - AffirmIf(status_id,(status and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh1; - cc.payload := gen_payload(kh1,10); - cc.seq_nr := gen_sn(3); - - Log("DDS Operation WRITE [Instance 1, Aligned Payload] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.cc.instance:= HANDLE_NIL; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc3 := cc; - -- Stored CC: I1S1, I2S2, I1S3, 0 - - Log("Current Time: 3s", INFO); - check_time <= gen_duration(3,0); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait_on_idle; - - AffirmIf(status_id,(status and OFFERED_DEADLINE_MISSED_STATUS) = OFFERED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0"); - - Log("DDS Operation GET_OFFERED_DEADLINE_MISSED_STATUS (Expected: count 1, change 1, Instance 2)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := GET_OFFERED_DEADLINE_MISSED_STATUS; - dds.ret_code := RETCODE_OK; - dds.count := 1; - dds.change := 1; - dds.inst := kh2; - start_dds; - wait_on_dds; - - wait_on_idle; - AffirmIf(status_id,(status and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh3; - cc.payload := gen_payload(kh3,10); - cc.seq_nr := gen_sn(4); - - Log("DDS Operation WRITE [Instance 3, Aligned Payload] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.cc.instance:= HANDLE_NIL; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc4 := cc; - -- Stored CC: I1S1, I2S2, I1S3, I3S4 - - Log("Current Time: 4s", INFO); - check_time <= gen_duration(4,0); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait_on_idle; - - AffirmIf(status_id,(status and OFFERED_DEADLINE_MISSED_STATUS) = OFFERED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0"); - - Log("DDS Operation GET_OFFERED_DEADLINE_MISSED_STATUS (Expected: count 3, change 2, Instance 1)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := GET_OFFERED_DEADLINE_MISSED_STATUS; - dds.ret_code := RETCODE_OK; - dds.count := 3; - dds.change := 2; - dds.inst := kh1; - start_dds; - wait_on_dds; - - wait_on_idle; - AffirmIf(status_id,(status and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1"); - - Log("Current Time: 5s", INFO); - check_time <= gen_duration(5,0); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait_on_idle; - - AffirmIf(status_id,(status and OFFERED_DEADLINE_MISSED_STATUS) = OFFERED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0"); - - Log("Current Time: 6s", INFO); - check_time <= gen_duration(6,0); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait_on_idle; - - AffirmIf(status_id,(status and OFFERED_DEADLINE_MISSED_STATUS) = OFFERED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0"); - - Log("DDS Operation GET_OFFERED_DEADLINE_MISSED_STATUS (Expected: count 9, change 6, Instance 1)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := GET_OFFERED_DEADLINE_MISSED_STATUS; - dds.ret_code := RETCODE_OK; - dds.count := 9; - dds.change := 6; - dds.inst := kh1; - start_dds; - wait_on_dds; - - wait_on_idle; - AffirmIf(status_id,(status and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1"); - - wait_on_completion; - TranscriptOpen(RESULTS_FILE, APPEND_MODE); - SetTranscriptMirror; - ReportAlerts; - TranscriptClose; - std.env.stop; - wait; - end process; - - clock_prc : process - begin - clk <= '0'; - wait for 25 ns; - clk <= '1'; - wait for 25 ns; - end process; - - alert_prc : process(all) - begin - if rising_edge(clk) then - -- TODO - end if; - end process; - - dds_prc : process(all) - begin - if rising_edge(clk) then - dds_done <= '0'; - case (dds_stage) is - when IDLE => - if (dds_start = '1') then - dds_stage <= START; - else - dds_done <= '1'; - end if; - when START => - if (ack_dds = '1') then - case (dds.opcode) is - when GET_OFFERED_DEADLINE_MISSED_STATUS => - dds_stage <= DONE; - dds_cnt <= 0; - when others => - dds_stage <= PUSH; - dds_cnt <= 0; - end case; - end if; - when PUSH => - if (ready_in_dds = '1') then - dds_cnt <= dds_cnt + 1; - if (dds_cnt = dds.cc.payload.length-1) then - -- DEFAULT - dds_stage <= DONE; - end if; - end if; - when DONE => - if (done_dds = '1') then - if (dds.opcode = REGISTER_INSTANCE or dds.opcode = LOOKUP_INSTANCE) then - AffirmIfEqual(ih_id, to_unsigned(instance_handle_out_dds), to_unsigned(dds.cc.instance)); - else - AffirmIfEqual(ret_id, return_code_dds, dds.ret_code); - case (dds.opcode) is - when GET_OFFERED_DEADLINE_MISSED_STATUS => - if (dds.ret_code = RETCODE_OK) then - dds_stage <= CHECK_DEADLINE; - dds_cnt <= 0; - else - dds_stage <= IDLE; - end if; - when others => - dds_stage <= IDLE; - end case; - end if; - end if; - when CHECK_DEADLINE => - if (valid_out_dds = '1') then - dds_cnt <= dds_cnt + 1; - case (dds_cnt) is - when 0 => - AffirmIfEqual(data_id, data_out_dds, std_logic_vector(to_unsigned(dds.count,CDR_LONG_WIDTH))); - when 1 => - AffirmIfEqual(data_id, data_out_dds, std_logic_vector(to_unsigned(dds.change,CDR_LONG_WIDTH))); - when 2 => - AffirmIfEqual(data_id, data_out_dds, std_logic_vector(dds.inst(0))); - when 3 => - AffirmIfEqual(data_id, data_out_dds, std_logic_vector(dds.inst(1))); - when 4 => - AffirmIfEqual(data_id, data_out_dds, std_logic_vector(dds.inst(2))); - when 5 => - AffirmIfEqual(data_id, data_out_dds, std_logic_vector(dds.inst(3))); - AlertIf(data_id, last_word_out_dds /= '1', "Last Word Signal not pulled High", ERROR); - dds_stage <= IDLE; - when others => - null; - end case; - end if; - end case; - end if; - - -- DEFAULT - start_dds <= '0'; - opcode_dds <= NOP; - valid_in_dds <= '0'; - last_word_in_dds <= '0'; - data_in_dds <= (others => '0'); - instance_handle_in_dds <= HANDLE_NIL; - source_ts_dds <= TIME_INVALID; - ready_out_dds <= '0'; - - case (dds_stage) is - when START => - start_dds <= '1'; - opcode_dds <= dds.opcode; - instance_handle_in_dds <= dds.cc.instance; - source_ts_dds <= dds.cc.src_timestamp; - when PUSH => - valid_in_dds <= '1'; - data_in_dds <= dds.cc.payload.data(dds_cnt); - last_word_in_dds <= dds.cc.payload.last(dds_cnt); - when CHECK_DEADLINE => - ready_out_dds <= '1'; - when others => - null; - end case; - end process; - - rtps_prc : process(all) - begin - if rising_edge(clk) then - rtps_done <= '0'; - case (rtps_stage) is - when IDLE => - if (rtps_start = '1') then - rtps_stage <= START; - else - rtps_done <= '1'; - end if; - when START => - if (ack_rtps = '1') then - rtps_stage <= DONE; - end if; - when DONE => - if (done_rtps = '1') then - -- DEFAULT - rtps_stage <= IDLE; - - AffirmIfEqual(ret_id, HISTORY_CACHE_RESPONSE_TYPE'pos(ret_rtps), HISTORY_CACHE_RESPONSE_TYPE'pos(rtps.ret_code)); - case (rtps.opcode) is - when GET_CACHE_CHANGE => - if (rtps.ret_code = OK) then - AffirmIfEqual(inst_id, cc_instance_handle(0), rtps.cc.instance(0)); - AffirmIfEqual(inst_id, cc_instance_handle(1), rtps.cc.instance(1)); - AffirmIfEqual(inst_id, cc_instance_handle(2), rtps.cc.instance(2)); - AffirmIfEqual(inst_id, cc_instance_handle(3), rtps.cc.instance(3)); - AffirmIfEqual(kind_id, CACHE_CHANGE_KIND_TYPE'pos(cc_kind), CACHE_CHANGE_KIND_TYPE'pos(rtps.cc.kind)); - AffirmIfEqual(sn_id, to_unsigned(cc_seq_nr), to_unsigned(rtps.cc.seq_nr)); - AffirmIfEqual(ts_id, to_unsigned(cc_source_timestamp), to_unsigned(rtps.cc.src_timestamp)); - rtps_stage <= CHECK; - rtps_cnt <= 0; - end if; - when GET_MIN_SN => - AffirmIfEqual(sn_id, to_unsigned(cc_seq_nr), to_unsigned(rtps.cc.seq_nr)); - when GET_MAX_SN => - AffirmIfEqual(sn_id, to_unsigned(cc_seq_nr), to_unsigned(rtps.cc.seq_nr)); - when others => - null; - end case; - end if; - when CHECK => - if (valid_out_rtps = '1') then - AffirmIfEqual(data_id, last_word_out_rtps & data_out_rtps, rtps.cc.payload.last(rtps_cnt) & rtps.cc.payload.data(rtps_cnt)); - rtps_cnt <= rtps_cnt + 1; - if (rtps_cnt = rtps.cc.payload.length-1) then - rtps_stage <= IDLE; - end if; - end if; - end case; - end if; - - -- DEFAULT - start_rtps <= '0'; - opcode_rtps <= NOP; - seq_nr_rtps <= SEQUENCENUMBER_UNKNOWN; - get_data_rtps <= '0'; - ready_out_rtps <= '0'; - - case (rtps_stage) is - when START => - start_rtps <= '1'; - opcode_rtps <= rtps.opcode; - seq_nr_rtps <= rtps.cc.seq_nr; - when DONE => - if (done_rtps = '1') then - case (rtps.opcode) is - when GET_CACHE_CHANGE => - get_data_rtps <= '1'; - when others => - null; - end case; - end if; - when CHECK => - ready_out_rtps <= '1'; - when others => - null; - end case; - end process; - - watchdog : process - begin - wait for 1 ms; - Alert("Test timeout", FAILURE); - std.env.stop; - end process; - -end architecture; \ No newline at end of file diff --git a/src/Tests/Level_0/L0_dds_writer_test3_ain.vhd b/src/Tests/Level_0/L0_dds_writer_test3_ain.vhd deleted file mode 100644 index 4059dc7..0000000 --- a/src/Tests/Level_0/L0_dds_writer_test3_ain.vhd +++ /dev/null @@ -1,543 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library osvvm; -- Utility Library -context osvvm.OsvvmContext; - -use work.rtps_package.all; -use work.user_config.all; -use work.rtps_config_package.all; -use work.rtps_test_package.all; - --- This testbench tests the Deadline Handling of the DDS Writer, and more specifically the GET_OFFERED_DEADLINE_MISSED_STATUS DDS Operation. - -entity L0_dds_writer_test3_ain is -end entity; - -architecture testbench of L0_dds_writer_test3_ain is - - -- *CONSTANT DECLARATION* - constant MAX_REMOTE_ENDPOINTS : natural := 3; - - -- *TYPE DECLARATION* - type DDS_STAGE_TYPE is (IDLE, START, PUSH, DONE, CHECK_DEADLINE); - type RTPS_STAGE_TYPE is (IDLE, START, DONE, CHECK); - - -- *SIGNAL DECLARATION* - signal clk : std_logic := '0'; - signal reset : std_logic := '1'; - signal check_time : TIME_TYPE := TIME_ZERO; - signal start_rtps, start_dds, ack_rtps, ack_dds, done_rtps, done_dds : std_logic := '0'; - signal opcode_rtps : HISTORY_CACHE_OPCODE_TYPE := NOP; - signal opcode_dds : DDS_WRITER_OPCODE_TYPE := NOP; - signal ret_rtps : HISTORY_CACHE_RESPONSE_TYPE := ERROR; - signal seq_nr_rtps, cc_seq_nr : SEQUENCENUMBER_TYPE := SEQUENCENUMBER_UNKNOWN; - signal ready_out_rtps, valid_out_rtps, last_word_out_rtps : std_logic := '0'; - signal ready_in_dds, ready_out_dds, valid_in_dds, valid_out_dds, last_word_in_dds, last_word_out_dds : std_logic := '0'; - signal data_out_rtps, data_in_dds, data_out_dds : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); - signal get_data_rtps, liveliness_assertion, data_available : std_logic := '0'; - signal cc_source_timestamp, source_ts_dds : TIME_TYPE := TIME_INVALID; - signal cc_kind : CACHE_CHANGE_KIND_TYPE := ALIVE; - signal cc_instance_handle, instance_handle_in_dds, instance_handle_out_dds : INSTANCE_HANDLE_TYPE := HANDLE_NIL; - signal max_wait_dds : DURATION_TYPE := DURATION_INFINITE; - signal return_code_dds : std_logic_vector(RETURN_CODE_WIDTH-1 downto 0) := (others => '0'); - signal status : std_logic_vector(STATUS_KIND_WIDTH-1 downto 0) := (others => '0'); - - signal dds_start, dds_done, rtps_start, rtps_done : std_logic := '0'; - signal dds_cnt, rtps_cnt : natural := 0; - signal dds_stage : DDS_STAGE_TYPE := IDLE; - signal rtps_stage : RTPS_STAGE_TYPE := IDLE; - shared variable dds : DDS_WRITER_TEST_TYPE := DEFAULT_DDS_WRITER_TEST; - shared variable rtps : RTPS_WRITER_TEST_TYPE := DEFAULT_RTPS_WRITER_TEST; - signal inst_id, kind_id, sn_id, ts_id, ih_id, ret_id, status_id, data_id : AlertLogIDType; - - -- *FUNCTION DECLARATION* - function extract_key_hash (payload : TEST_PACKET_TYPE) return INSTANCE_HANDLE_TYPE is - variable ret : INSTANCE_HANDLE_TYPE := HANDLE_NIL; - begin - for i in 0 to 3 loop - ret(i) := not payload.data(i); - end loop; - - return ret; - end function; - - function gen_sn(input : natural) return SEQUENCENUMBER_TYPE is - variable ret : SEQUENCENUMBER_TYPE; - begin - ret(0) := (others => '0'); - ret(1) := unsigned(int(input, WORD_WIDTH)); - return ret; - end function; - -begin - - -- Unit Under Test - uut : entity work.dds_writer(arch) - generic map( - HISTORY_QOS => KEEP_ALL_HISTORY_QOS, - DEADLINE_QOS => gen_duration(1,0), - LIFESPAN_QOS => DURATION_INFINITE, - LEASE_DURATION => DURATION_INFINITE, - WITH_KEY => FALSE, - MAX_SAMPLES => std_logic_vector(to_unsigned(4,CDR_LONG_WIDTH)), - MAX_INSTANCES => std_logic_vector(to_unsigned(3,CDR_LONG_WIDTH)), - MAX_SAMPLES_PER_INSTANCE => std_logic_vector(to_unsigned(2,CDR_LONG_WIDTH)), - PAYLOAD_FRAME_SIZE => 11 - ) - port map ( - clk => clk, - reset => reset, - time => check_time, - start_rtps => start_rtps, - opcode_rtps => opcode_rtps, - ack_rtps => ack_rtps, - done_rtps => done_rtps, - ret_rtps => ret_rtps, - seq_nr_rtps => seq_nr_rtps, - get_data_rtps => get_data_rtps, - data_out_rtps => data_out_rtps, - valid_out_rtps => valid_out_rtps, - ready_out_rtps => ready_out_rtps, - last_word_out_rtps => last_word_out_rtps, - liveliness_assertion => liveliness_assertion, - data_available => data_available, - cc_instance_handle => cc_instance_handle, - cc_kind => cc_kind, - cc_source_timestamp => cc_source_timestamp, - cc_seq_nr => cc_seq_nr, - start_dds => start_dds, - ack_dds => ack_dds, - opcode_dds => opcode_dds, - instance_handle_in_dds => instance_handle_in_dds, - source_ts_dds => source_ts_dds, - max_wait_dds => max_wait_dds, - done_dds => done_dds, - return_code_dds => return_code_dds, - instance_handle_out_dds => instance_handle_out_dds, - ready_in_dds => ready_in_dds, - valid_in_dds => valid_in_dds, - data_in_dds => data_in_dds, - last_word_in_dds => last_word_in_dds, - ready_out_dds => ready_out_dds, - valid_out_dds => valid_out_dds, - data_out_dds => data_out_dds, - last_word_out_dds => last_word_out_dds, - status => status - ); - - stimulus_prc : process - variable RV : RandomPType; - variable kh1, kh2, kh3, kh4 : INSTANCE_HANDLE_TYPE := HANDLE_NIL; - variable cc1, cc2, cc3, cc4, cc : CACHE_CHANGE_TYPE := DEFAULT_CACHE_CHANGE; - - alias idle_sig is <>; - - impure function gen_payload(key_hash : INSTANCE_HANDLE_TYPE; len : natural) return TEST_PACKET_TYPE is - variable ret : TEST_PACKET_TYPE := EMPTY_TEST_PACKET; - begin - assert (len >= 4) report "Payload length has to be at least 16 Bytes long" severity FAILURE; - - for i in 0 to len-1 loop - if (i < 4) then - -- NOTE: Beginning of payload is negated key to allow deterministic Key Hash generation from the kh_prc - ret.data(ret.length) := not key_hash(i); - else - ret.data(ret.length) := RV.RandSlv(WORD_WIDTH); - end if; - ret.length := ret.length + 1; - end loop; - ret.last(ret.length-1) := '1'; - - return ret; - end function; - - impure function gen_key_hash return KEY_HASH_TYPE is - variable ret : KEY_HASH_TYPE := KEY_HASH_NIL; - begin - for i in 0 to KEY_HASH_TYPE'length-1 loop - ret(i) := RV.RandSlv(WORD_WIDTH); - end loop; - return ret; - end function; - - procedure start_dds is - begin - dds_start <= '1'; - wait until rising_edge(clk); - dds_start <= '0'; - wait until rising_edge(clk); - end procedure; - - procedure start_rtps is - begin - rtps_start <= '1'; - wait until rising_edge(clk); - rtps_start <= '0'; - wait until rising_edge(clk); - end procedure; - - procedure wait_on_dds is - begin - if (dds_done /= '1') then - wait until dds_done = '1'; - end if; - end procedure; - - procedure wait_on_rtps is - begin - if (rtps_done /= '1') then - wait until rtps_done = '1'; - end if; - end procedure; - - procedure wait_on_completion is - begin - if (rtps_done /= '1' or dds_done /= '1') then - wait until rtps_done = '1' and dds_done = '1'; - end if; - end procedure; - - -- NOTE: This procedure waits until the idle_sig is high for at least - -- two consecutive clock cycles. - procedure wait_on_idle is - begin - loop - if (idle_sig /= '1') then - wait until idle_sig = '1'; - else - exit; - end if; - wait until rising_edge(clk); - wait until rising_edge(clk); - end loop; - end procedure; - - begin - - SetAlertLogName("L0_dds_writer_test3_ain - (KEEP ALL, Infinite Lifespan, Keyed) - Deadline Handling"); - SetAlertEnable(FAILURE, TRUE); - SetAlertEnable(ERROR, TRUE); - SetAlertEnable(WARNING, TRUE); - SetLogEnable(DEBUG, FALSE); - SetLogEnable(PASSED, FALSE); - SetLogEnable(INFO, TRUE); - RV.InitSeed(RV'instance_name); - inst_id <= GetAlertLogID("Instance", ALERTLOG_BASE_ID); - kind_id <= GetAlertLogID("Cache Change Kind", ALERTLOG_BASE_ID); - sn_id <= GetAlertLogID("SequenceNumber", ALERTLOG_BASE_ID); - ts_id <= GetAlertLogID("TimeStamp", ALERTLOG_BASE_ID); - ih_id <= GetAlertLogID("Instance Handle", ALERTLOG_BASE_ID); - data_id <= GetAlertLogID("Data Out", ALERTLOG_BASE_ID); - ret_id <= GetAlertLogID("Return Code", ALERTLOG_BASE_ID); - status_id <= GetAlertLogID("Communication Status", ALERTLOG_BASE_ID); - - -- Key Hashes - kh1 := gen_key_hash; - kh2 := gen_key_hash; - kh3 := gen_key_hash; - kh4 := gen_key_hash; - - - - Log("Initiating Test", INFO); - Log("Current Time: 0s", INFO); - check_time <= TIME_ZERO; - reset <= '1'; - wait until rising_edge(clk); - wait until rising_edge(clk); - reset <= '0'; - wait_on_idle; - -- Stored CC: 0, 0, 0, 0 - - AffirmIf(status_id,(status and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1"); - - Log("Current Time: 1s", INFO); - check_time <= gen_duration(1,0); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait_on_idle; - - AffirmIf(status_id,(status and OFFERED_DEADLINE_MISSED_STATUS) = OFFERED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0"); - - Log("DDS Operation GET_OFFERED_DEADLINE_MISSED_STATUS (Expected: count 1, change 1)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := GET_OFFERED_DEADLINE_MISSED_STATUS; - dds.ret_code := RETCODE_OK; - dds.count := 1; - dds.change := 1; - start_dds; - wait_on_dds; - - wait_on_idle; - AffirmIf(status_id,(status and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh1; - cc.payload := gen_payload(kh1,10); - cc.seq_nr := gen_sn(1); - - Log("DDS Operation WRITE [Aligned Payload] (ACCEPTED)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := WRITE; - dds.cc := cc; - dds.cc.instance:= HANDLE_NIL; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - cc1 := cc; - -- Stored CC: I1S1, 0, 0, 0 - - Log("Current Time: 2s", INFO); - check_time <= gen_duration(2,0); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait_on_idle; - - AffirmIf(status_id,(status and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1"); - - Log("Current Time: 3s", INFO); - check_time <= gen_duration(3,0); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait_on_idle; - - AffirmIf(status_id,(status and OFFERED_DEADLINE_MISSED_STATUS) = OFFERED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0"); - - Log("Current Time: 4s", INFO); - check_time <= gen_duration(4,0); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait_on_idle; - - AffirmIf(status_id,(status and OFFERED_DEADLINE_MISSED_STATUS) = OFFERED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0"); - - Log("DDS Operation GET_OFFERED_DEADLINE_MISSED_STATUS (Expected: count 3, change 2)", INFO); - dds := DEFAULT_DDS_WRITER_TEST; - dds.opcode := GET_OFFERED_DEADLINE_MISSED_STATUS; - dds.ret_code := RETCODE_OK; - dds.count := 3; - dds.change := 2; - start_dds; - wait_on_dds; - - wait_on_idle; - AffirmIf(status_id,(status and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1"); - - wait_on_completion; - TranscriptOpen(RESULTS_FILE, APPEND_MODE); - SetTranscriptMirror; - ReportAlerts; - TranscriptClose; - std.env.stop; - wait; - end process; - - clock_prc : process - begin - clk <= '0'; - wait for 25 ns; - clk <= '1'; - wait for 25 ns; - end process; - - alert_prc : process(all) - begin - if rising_edge(clk) then - -- TODO - end if; - end process; - - dds_prc : process(all) - begin - if rising_edge(clk) then - dds_done <= '0'; - case (dds_stage) is - when IDLE => - if (dds_start = '1') then - dds_stage <= START; - else - dds_done <= '1'; - end if; - when START => - if (ack_dds = '1') then - case (dds.opcode) is - when GET_OFFERED_DEADLINE_MISSED_STATUS => - dds_stage <= DONE; - dds_cnt <= 0; - when others => - dds_stage <= PUSH; - dds_cnt <= 0; - end case; - end if; - when PUSH => - if (ready_in_dds = '1') then - dds_cnt <= dds_cnt + 1; - if (dds_cnt = dds.cc.payload.length-1) then - -- DEFAULT - dds_stage <= DONE; - end if; - end if; - when DONE => - if (done_dds = '1') then - if (dds.opcode = REGISTER_INSTANCE or dds.opcode = LOOKUP_INSTANCE) then - AffirmIfEqual(ih_id, to_unsigned(instance_handle_out_dds), to_unsigned(dds.cc.instance)); - else - AffirmIfEqual(ret_id, return_code_dds, dds.ret_code); - case (dds.opcode) is - when GET_OFFERED_DEADLINE_MISSED_STATUS => - if (dds.ret_code = RETCODE_OK) then - dds_stage <= CHECK_DEADLINE; - dds_cnt <= 0; - else - dds_stage <= IDLE; - end if; - when others => - dds_stage <= IDLE; - end case; - end if; - end if; - when CHECK_DEADLINE => - if (valid_out_dds = '1') then - dds_cnt <= dds_cnt + 1; - case (dds_cnt) is - when 0 => - AffirmIfEqual(data_id, data_out_dds, std_logic_vector(to_unsigned(dds.count,CDR_LONG_WIDTH))); - when 1 => - AffirmIfEqual(data_id, data_out_dds, std_logic_vector(to_unsigned(dds.change,CDR_LONG_WIDTH))); - when 2 => - AffirmIfEqual(data_id, data_out_dds, std_logic_vector(dds.inst(0))); - when 3 => - AffirmIfEqual(data_id, data_out_dds, std_logic_vector(dds.inst(1))); - when 4 => - AffirmIfEqual(data_id, data_out_dds, std_logic_vector(dds.inst(2))); - when 5 => - AffirmIfEqual(data_id, data_out_dds, std_logic_vector(dds.inst(3))); - AlertIf(data_id, last_word_out_dds /= '1', "Last Word Signal not pulled High", ERROR); - dds_stage <= IDLE; - when others => - null; - end case; - end if; - end case; - end if; - - -- DEFAULT - start_dds <= '0'; - opcode_dds <= NOP; - valid_in_dds <= '0'; - last_word_in_dds <= '0'; - data_in_dds <= (others => '0'); - instance_handle_in_dds <= HANDLE_NIL; - source_ts_dds <= TIME_INVALID; - ready_out_dds <= '0'; - - case (dds_stage) is - when START => - start_dds <= '1'; - opcode_dds <= dds.opcode; - instance_handle_in_dds <= dds.cc.instance; - source_ts_dds <= dds.cc.src_timestamp; - when PUSH => - valid_in_dds <= '1'; - data_in_dds <= dds.cc.payload.data(dds_cnt); - last_word_in_dds <= dds.cc.payload.last(dds_cnt); - when CHECK_DEADLINE => - ready_out_dds <= '1'; - when others => - null; - end case; - end process; - - rtps_prc : process(all) - begin - if rising_edge(clk) then - rtps_done <= '0'; - case (rtps_stage) is - when IDLE => - if (rtps_start = '1') then - rtps_stage <= START; - else - rtps_done <= '1'; - end if; - when START => - if (ack_rtps = '1') then - rtps_stage <= DONE; - end if; - when DONE => - if (done_rtps = '1') then - -- DEFAULT - rtps_stage <= IDLE; - - AffirmIfEqual(ret_id, HISTORY_CACHE_RESPONSE_TYPE'pos(ret_rtps), HISTORY_CACHE_RESPONSE_TYPE'pos(rtps.ret_code)); - case (rtps.opcode) is - when GET_CACHE_CHANGE => - if (rtps.ret_code = OK) then - AffirmIfEqual(inst_id, cc_instance_handle(0), rtps.cc.instance(0)); - AffirmIfEqual(inst_id, cc_instance_handle(1), rtps.cc.instance(1)); - AffirmIfEqual(inst_id, cc_instance_handle(2), rtps.cc.instance(2)); - AffirmIfEqual(inst_id, cc_instance_handle(3), rtps.cc.instance(3)); - AffirmIfEqual(kind_id, CACHE_CHANGE_KIND_TYPE'pos(cc_kind), CACHE_CHANGE_KIND_TYPE'pos(rtps.cc.kind)); - AffirmIfEqual(sn_id, to_unsigned(cc_seq_nr), to_unsigned(rtps.cc.seq_nr)); - AffirmIfEqual(ts_id, to_unsigned(cc_source_timestamp), to_unsigned(rtps.cc.src_timestamp)); - rtps_stage <= CHECK; - rtps_cnt <= 0; - end if; - when GET_MIN_SN => - AffirmIfEqual(sn_id, to_unsigned(cc_seq_nr), to_unsigned(rtps.cc.seq_nr)); - when GET_MAX_SN => - AffirmIfEqual(sn_id, to_unsigned(cc_seq_nr), to_unsigned(rtps.cc.seq_nr)); - when others => - null; - end case; - end if; - when CHECK => - if (valid_out_rtps = '1') then - AffirmIfEqual(data_id, last_word_out_rtps & data_out_rtps, rtps.cc.payload.last(rtps_cnt) & rtps.cc.payload.data(rtps_cnt)); - rtps_cnt <= rtps_cnt + 1; - if (rtps_cnt = rtps.cc.payload.length-1) then - rtps_stage <= IDLE; - end if; - end if; - end case; - end if; - - -- DEFAULT - start_rtps <= '0'; - opcode_rtps <= NOP; - seq_nr_rtps <= SEQUENCENUMBER_UNKNOWN; - get_data_rtps <= '0'; - ready_out_rtps <= '0'; - - case (rtps_stage) is - when START => - start_rtps <= '1'; - opcode_rtps <= rtps.opcode; - seq_nr_rtps <= rtps.cc.seq_nr; - when DONE => - if (done_rtps = '1') then - case (rtps.opcode) is - when GET_CACHE_CHANGE => - get_data_rtps <= '1'; - when others => - null; - end case; - end if; - when CHECK => - ready_out_rtps <= '1'; - when others => - null; - end case; - end process; - - watchdog : process - begin - wait for 1 ms; - Alert("Test timeout", FAILURE); - std.env.stop; - end process; - -end architecture; \ No newline at end of file diff --git a/src/Tests/Level_0/L0_dds_writer_test4_aik.vhd b/src/Tests/Level_0/L0_dds_writer_test4.vhd similarity index 55% rename from src/Tests/Level_0/L0_dds_writer_test4_aik.vhd rename to src/Tests/Level_0/L0_dds_writer_test4.vhd index d79edde..c323bef 100644 --- a/src/Tests/Level_0/L0_dds_writer_test4_aik.vhd +++ b/src/Tests/Level_0/L0_dds_writer_test4.vhd @@ -12,13 +12,41 @@ use work.rtps_test_package.all; -- This testbench tests the Liveliness Handling of the DDS Writer, and more specifically the DDS GET_LIVELINESS_LOST_STATUS, and ASSERT_LIVELINESS Operations. -entity L0_dds_writer_test4_aik is +entity L0_dds_writer_test4 is end entity; -architecture testbench of L0_dds_writer_test4_aik is +architecture testbench of L0_dds_writer_test4 is -- *CONSTANT DECLARATION* - constant MAX_REMOTE_ENDPOINTS : natural := 3; + constant MAX_REMOTE_ENDPOINTS : natural := 3; + constant NUM_WRITERS : natural := 2; + + impure function gen_test_config return CONFIG_ARRAY_TYPE is + variable ret : CONFIG_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => DEFAULT_WRITER_CONFIG); + begin + -- aik + ret(0).HISTORY_QOS := KEEP_ALL_HISTORY_QOS; + ret(0).DEADLINE_QOS := DURATION_INFINITE; + ret(0).LIFESPAN_QOS := DURATION_INFINITE; + ret(0).LEASE_DURATION := gen_duration(1 sec); + ret(0).WITH_KEY := TRUE; + ret(0).MAX_SAMPLES := std_logic_vector(to_unsigned(4,CDR_LONG_WIDTH)); + ret(0).MAX_INSTANCES := std_logic_vector(to_unsigned(3,CDR_LONG_WIDTH)); + ret(0).MAX_SAMPLES_PER_INSTANCE := std_logic_vector(to_unsigned(4,CDR_LONG_WIDTH)); + ret(0).MAX_PAYLOAD_SIZE := 40; + -- ain + ret(1).HISTORY_QOS := KEEP_ALL_HISTORY_QOS; + ret(1).DEADLINE_QOS := DURATION_INFINITE; + ret(1).LIFESPAN_QOS := DURATION_INFINITE; + ret(1).LEASE_DURATION := gen_duration(2 sec); + ret(1).WITH_KEY := FALSE; + ret(1).MAX_SAMPLES := std_logic_vector(to_unsigned(4,CDR_LONG_WIDTH)); + ret(1).MAX_INSTANCES := std_logic_vector(to_unsigned(3,CDR_LONG_WIDTH)); + ret(1).MAX_SAMPLES_PER_INSTANCE := std_logic_vector(to_unsigned(4,CDR_LONG_WIDTH)); + ret(1).MAX_PAYLOAD_SIZE := 40; + return ret; + end function; + constant TEST_CONFIG : CONFIG_ARRAY_TYPE := gen_test_config; -- *TYPE DECLARATION* type DDS_STAGE_TYPE is (IDLE, START, PUSH, DONE, CHECK_LIVELINESS); @@ -28,22 +56,23 @@ architecture testbench of L0_dds_writer_test4_aik is signal clk : std_logic := '0'; signal reset : std_logic := '1'; signal check_time : TIME_TYPE := TIME_ZERO; - signal start_rtps, start_dds, ack_rtps, ack_dds, done_rtps, done_dds : std_logic := '0'; - signal opcode_rtps : HISTORY_CACHE_OPCODE_TYPE := NOP; - signal opcode_dds : DDS_WRITER_OPCODE_TYPE := NOP; - signal ret_rtps : HISTORY_CACHE_RESPONSE_TYPE := ERROR; - signal seq_nr_rtps, cc_seq_nr : SEQUENCENUMBER_TYPE := SEQUENCENUMBER_UNKNOWN; - signal ready_out_rtps, valid_out_rtps, last_word_out_rtps : std_logic := '0'; - signal ready_in_dds, ready_out_dds, valid_in_dds, valid_out_dds, last_word_in_dds, last_word_out_dds : std_logic := '0'; - signal data_out_rtps, data_in_dds, data_out_dds : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); - signal get_data_rtps, liveliness_assertion, data_available : std_logic := '0'; - signal cc_source_timestamp, source_ts_dds : TIME_TYPE := TIME_INVALID; - signal cc_kind : CACHE_CHANGE_KIND_TYPE := ALIVE; - signal cc_instance_handle, instance_handle_in_dds, instance_handle_out_dds : INSTANCE_HANDLE_TYPE := HANDLE_NIL; - signal max_wait_dds : DURATION_TYPE := DURATION_INFINITE; - signal return_code_dds : std_logic_vector(RETURN_CODE_WIDTH-1 downto 0) := (others => '0'); - signal status : std_logic_vector(STATUS_KIND_WIDTH-1 downto 0) := (others => '0'); + signal start_rtps, start_dds, ack_rtps, ack_dds, done_rtps, done_dds, w_map : std_logic_vector(0 to NUM_WRITERS-1) := (others => '0'); + signal opcode_rtps : HISTORY_CACHE_OPCODE_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => NOP); + signal opcode_dds : DDS_WRITER_OPCODE_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => NOP); + signal ret_rtps : HISTORY_CACHE_RESPONSE_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => ERROR); + signal seq_nr_rtps, cc_seq_nr : SEQUENCENUMBER_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => SEQUENCENUMBER_UNKNOWN); + signal ready_out_rtps, valid_out_rtps, last_word_out_rtps : std_logic_vector(0 to NUM_WRITERS-1) := (others => '0'); + signal ready_in_dds, ready_out_dds, valid_in_dds, valid_out_dds, last_word_in_dds, last_word_out_dds : std_logic_vector(0 to NUM_WRITERS-1) := (others => '0'); + signal data_out_rtps, data_in_dds, data_out_dds : WORD_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => (others => '0')); + signal get_data_rtps, liveliness_assertion, data_available : std_logic_vector(0 to NUM_WRITERS-1) := (others => '0'); + signal cc_source_timestamp, source_ts_dds : TIME_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => TIME_INVALID); + signal cc_kind : CACHE_CHANGE_KIND_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => ALIVE); + signal cc_instance_handle, instance_handle_in_dds, instance_handle_out_dds : INSTANCE_HANDLE_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => HANDLE_NIL); + signal max_wait_dds : DURATION_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => DURATION_INFINITE); + signal return_code_dds : RETURN_CODE_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => (others => '0')); + signal status : STATUS_KIND_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => (others => '0')); + signal ind : natural := 0; signal dds_start, dds_done, rtps_start, rtps_done : std_logic := '0'; signal dds_cnt, rtps_cnt : natural := 0; signal dds_stage : DDS_STAGE_TYPE := IDLE; @@ -71,20 +100,20 @@ architecture testbench of L0_dds_writer_test4_aik is return ret; end function; + procedure wait_on_sig(signal sig : std_logic) is + begin + if (sig /= '1') then + wait on sig until sig = '1'; + end if; + end procedure; + begin -- Unit Under Test uut : entity work.dds_writer(arch) generic map( - HISTORY_QOS => KEEP_ALL_HISTORY_QOS, - DEADLINE_QOS => DURATION_INFINITE, - LIFESPAN_QOS => DURATION_INFINITE, - LEASE_DURATION => gen_duration(1,0), - WITH_KEY => TRUE, - MAX_SAMPLES => std_logic_vector(to_unsigned(4,CDR_LONG_WIDTH)), - MAX_INSTANCES => std_logic_vector(to_unsigned(3,CDR_LONG_WIDTH)), - MAX_SAMPLES_PER_INSTANCE => std_logic_vector(to_unsigned(4,CDR_LONG_WIDTH)), - PAYLOAD_FRAME_SIZE => 11 + NUM_WRITERS => NUM_WRITERS, + CONFIG_ARRAY => to_QUARTUS_CONFIG_ARRAY_TYPE(TEST_CONFIG) ) port map ( clk => clk, @@ -178,20 +207,6 @@ begin wait until rising_edge(clk); end procedure; - procedure wait_on_dds is - begin - if (dds_done /= '1') then - wait until dds_done = '1'; - end if; - end procedure; - - procedure wait_on_rtps is - begin - if (rtps_done /= '1') then - wait until rtps_done = '1'; - end if; - end procedure; - procedure wait_on_completion is begin if (rtps_done /= '1' or dds_done /= '1') then @@ -202,21 +217,23 @@ begin -- NOTE: This procedure waits until the idle_sig is high for at least -- two consecutive clock cycles. procedure wait_on_idle is + variable first : boolean := TRUE; begin loop if (idle_sig /= '1') then wait until idle_sig = '1'; - else + elsif (not first) then exit; end if; wait until rising_edge(clk); wait until rising_edge(clk); + first := FALSE; end loop; end procedure; begin - SetAlertLogName("L0_dds_writer_test4_aik - (KEEP ALL, Infinite Lifespan, Keyed) - Liveliness Handling"); + SetAlertLogName("L0_dds_writer_test4 - Liveliness Handling"); SetAlertEnable(FAILURE, TRUE); SetAlertEnable(ERROR, TRUE); SetAlertEnable(WARNING, TRUE); @@ -248,37 +265,59 @@ begin wait until rising_edge(clk); reset <= '0'; wait_on_idle; - -- Stored CC: 0, 0, 0, 0 - AffirmIf(status_id,(status and LIVELINESS_LOST_STATUS) /= LIVELINESS_LOST_STATUS, "Expected: 0", "Received 1"); + AffirmIf(status_id,(status(0) and LIVELINESS_LOST_STATUS) /= LIVELINESS_LOST_STATUS, "Expected: 0", "Received 1"); + AffirmIf(status_id,(status(1) and LIVELINESS_LOST_STATUS) /= LIVELINESS_LOST_STATUS, "Expected: 0", "Received 1"); Log("Current Time: 1s", INFO); - check_time <= gen_duration(1,0); + check_time <= gen_duration(1 sec); wait until rising_edge(clk); wait until rising_edge(clk); wait_on_idle; - AffirmIf(status_id,(status and LIVELINESS_LOST_STATUS) = LIVELINESS_LOST_STATUS, "Expected: 1", "Received 0"); + AffirmIf(status_id,(status(0) and LIVELINESS_LOST_STATUS) = LIVELINESS_LOST_STATUS, "Expected: 1", "Received 0"); + AffirmIf(status_id,(status(1) and LIVELINESS_LOST_STATUS) /= LIVELINESS_LOST_STATUS, "Expected: 0", "Received 1"); - Log("DDS Operation GET_LIVELINESS_LOST_STATUS (Expected: count 1, change 1)", INFO); + Log("W0: DDS Operation GET_LIVELINESS_LOST_STATUS", INFO); + Log("W0: Expected [count 1, change 1]", DEBUG); dds := DEFAULT_DDS_WRITER_TEST; dds.opcode := GET_LIVELINESS_LOST_STATUS; dds.ret_code := RETCODE_OK; dds.count := 1; dds.change := 1; + -- WRITER 0 + ind <= 0; start_dds; - wait_on_dds; - + wait_on_sig(dds_done); wait_on_idle; - AffirmIf(status_id,(status and LIVELINESS_LOST_STATUS) /= LIVELINESS_LOST_STATUS, "Expected: 0", "Received 1"); + + AffirmIf(status_id,(status(0) and LIVELINESS_LOST_STATUS) /= LIVELINESS_LOST_STATUS, "Expected: 0", "Received 1"); + AffirmIf(status_id,(status(1) and LIVELINESS_LOST_STATUS) /= LIVELINESS_LOST_STATUS, "Expected: 0", "Received 1"); + + Log("W1: DDS Operation GET_LIVELINESS_LOST_STATUS", INFO); + Log("W1: Expected [count 0, change 0]", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := GET_LIVELINESS_LOST_STATUS; + dds.ret_code := RETCODE_OK; + dds.count := 0; + dds.change := 0; + -- WRITER 1 + ind <= 1; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + + AffirmIf(status_id,(status(0) and LIVELINESS_LOST_STATUS) /= LIVELINESS_LOST_STATUS, "Expected: 0", "Received 1"); + AffirmIf(status_id,(status(1) and LIVELINESS_LOST_STATUS) /= LIVELINESS_LOST_STATUS, "Expected: 0", "Received 1"); Log("Current Time: 1.5s", INFO); - check_time <= gen_duration(1,500); + check_time <= gen_duration(1.5 sec); wait until rising_edge(clk); wait until rising_edge(clk); wait_on_idle; - AffirmIf(status_id,(status and LIVELINESS_LOST_STATUS) /= LIVELINESS_LOST_STATUS, "Expected: 0", "Received 1"); + AffirmIf(status_id,(status(0) and LIVELINESS_LOST_STATUS) /= LIVELINESS_LOST_STATUS, "Expected: 0", "Received 1"); + AffirmIf(status_id,(status(1) and LIVELINESS_LOST_STATUS) /= LIVELINESS_LOST_STATUS, "Expected: 0", "Received 1"); cc := DEFAULT_CACHE_CHANGE; cc.serialized_key := FALSE; @@ -287,32 +326,40 @@ begin cc.payload := gen_payload(kh1,10); cc.seq_nr := gen_sn(1); - Log("DDS Operation WRITE [Instance 1, HANDLE_NIL, Aligned Payload] (ACCEPTED)", INFO); + Log("W0,W1: DDS Operation WRITE [Instance 1, HANDLE_NIL, Aligned Payload]", INFO); + Log("W0,W1: ACCEPTED", DEBUG); dds := DEFAULT_DDS_WRITER_TEST; dds.opcode := WRITE; dds.cc := cc; dds.cc.instance:= HANDLE_NIL; dds.ret_code := RETCODE_OK; + -- WRITER 0 + ind <= 0; start_dds; - wait_on_dds; - cc1 := cc; - -- Stored CC: I1S1, 0, 0, 0 + wait_on_sig(dds_done); + -- WRITER 1 + ind <= 1; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; Log("Current Time: 2s", INFO); - check_time <= gen_duration(2,0); + check_time <= gen_duration(2 sec); wait until rising_edge(clk); wait until rising_edge(clk); wait_on_idle; - AffirmIf(status_id,(status and LIVELINESS_LOST_STATUS) /= LIVELINESS_LOST_STATUS, "Expected: 0", "Received 1"); + AffirmIf(status_id,(status(0) and LIVELINESS_LOST_STATUS) /= LIVELINESS_LOST_STATUS, "Expected: 0", "Received 1"); + AffirmIf(status_id,(status(1) and LIVELINESS_LOST_STATUS) /= LIVELINESS_LOST_STATUS, "Expected: 0", "Received 1"); Log("Current Time: 2.4s", INFO); - check_time <= gen_duration(2,400); + check_time <= gen_duration(2.4 sec); wait until rising_edge(clk); wait until rising_edge(clk); wait_on_idle; - AffirmIf(status_id,(status and LIVELINESS_LOST_STATUS) /= LIVELINESS_LOST_STATUS, "Expected: 0", "Received 1"); + AffirmIf(status_id,(status(0) and LIVELINESS_LOST_STATUS) /= LIVELINESS_LOST_STATUS, "Expected: 0", "Received 1"); + AffirmIf(status_id,(status(1) and LIVELINESS_LOST_STATUS) /= LIVELINESS_LOST_STATUS, "Expected: 0", "Received 1"); cc := DEFAULT_CACHE_CHANGE; cc.serialized_key := TRUE; @@ -321,31 +368,40 @@ begin cc.payload := gen_payload(kh1,5); cc.seq_nr := gen_sn(2); - Log("DDS Operation DISPOSE [Instance 1] (ACCEPTED)", INFO); + Log("W0,W1: DDS Operation DISPOSE [Instance 1]", INFO); + Log("W0,W1: ACCEPTED", DEBUG); dds := DEFAULT_DDS_WRITER_TEST; dds.opcode := DISPOSE; dds.cc := cc; dds.ret_code := RETCODE_OK; + -- WRITER 0 + ind <= 0; start_dds; - wait_on_dds; - cc2 := cc; - -- Stored CC: I1S1, I1S2, 0, 0 + wait_on_sig(dds_done); + -- WRITER 1 + dds.cc.instance := HANDLE_NIL; + ind <= 1; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; Log("Current Time: 3s", INFO); - check_time <= gen_duration(3,0); + check_time <= gen_duration(3 sec); wait until rising_edge(clk); wait until rising_edge(clk); wait_on_idle; - AffirmIf(status_id,(status and LIVELINESS_LOST_STATUS) /= LIVELINESS_LOST_STATUS, "Expected: 0", "Received 1"); + AffirmIf(status_id,(status(0) and LIVELINESS_LOST_STATUS) /= LIVELINESS_LOST_STATUS, "Expected: 0", "Received 1"); + AffirmIf(status_id,(status(1) and LIVELINESS_LOST_STATUS) /= LIVELINESS_LOST_STATUS, "Expected: 0", "Received 1"); Log("Current Time: 3.3s", INFO); - check_time <= gen_duration(3,300); + check_time <= gen_duration(3.3 sec); wait until rising_edge(clk); wait until rising_edge(clk); wait_on_idle; - AffirmIf(status_id,(status and LIVELINESS_LOST_STATUS) /= LIVELINESS_LOST_STATUS, "Expected: 0", "Received 1"); + AffirmIf(status_id,(status(0) and LIVELINESS_LOST_STATUS) /= LIVELINESS_LOST_STATUS, "Expected: 0", "Received 1"); + AffirmIf(status_id,(status(1) and LIVELINESS_LOST_STATUS) /= LIVELINESS_LOST_STATUS, "Expected: 0", "Received 1"); cc := DEFAULT_CACHE_CHANGE; cc.serialized_key := TRUE; @@ -354,75 +410,143 @@ begin cc.payload := gen_payload(kh1,5); cc.seq_nr := gen_sn(3); - Log("DDS Operation UNREGISTER_INSTANCE [Instance 1] (ACCEPTED)", INFO); + Log("W0: DDS Operation UNREGISTER_INSTANCE [Instance 1]", INFO); + Log("W0: ACCEPTED", DEBUG); dds := DEFAULT_DDS_WRITER_TEST; dds.opcode := UNREGISTER_INSTANCE; dds.cc := cc; dds.ret_code := RETCODE_OK; + -- WRITER 0 + ind <= 0; start_dds; - wait_on_dds; - cc3 := cc; - -- Stored CC: I1S1, I1S2, I1S3, 0 + wait_on_sig(dds_done); + wait_on_idle; Log("Current Time: 4s", INFO); - check_time <= gen_duration(4,0); + check_time <= gen_duration(4 sec); wait until rising_edge(clk); wait until rising_edge(clk); wait_on_idle; - AffirmIf(status_id,(status and LIVELINESS_LOST_STATUS) /= LIVELINESS_LOST_STATUS, "Expected: 0", "Received 1"); + AffirmIf(status_id,(status(0) and LIVELINESS_LOST_STATUS) /= LIVELINESS_LOST_STATUS, "Expected: 0", "Received 1"); + AffirmIf(status_id,(status(1) and LIVELINESS_LOST_STATUS) /= LIVELINESS_LOST_STATUS, "Expected: 0", "Received 1"); Log("Current Time: 5s", INFO); - check_time <= gen_duration(5,0); + check_time <= gen_duration(5 sec); wait until rising_edge(clk); wait until rising_edge(clk); wait_on_idle; - AffirmIf(status_id,(status and LIVELINESS_LOST_STATUS) = LIVELINESS_LOST_STATUS, "Expected: 1", "Received 0"); + AffirmIf(status_id,(status(0) and LIVELINESS_LOST_STATUS) = LIVELINESS_LOST_STATUS, "Expected: 1", "Received 0"); + AffirmIf(status_id,(status(1) and LIVELINESS_LOST_STATUS) = LIVELINESS_LOST_STATUS, "Expected: 1", "Received 0"); + + Log("W1: DDS Operation ASSERT_LIVELINESS", INFO); + Log("W1: OK", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := ASSERT_LIVELINESS; + dds.ret_code := RETCODE_OK; + dds.assertion := '1'; + -- WRITER 1 + ind <= 1; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; Log("Current Time: 6s", INFO); - check_time <= gen_duration(6,0); + check_time <= gen_duration(6 sec); wait until rising_edge(clk); wait until rising_edge(clk); wait_on_idle; - AffirmIf(status_id,(status and LIVELINESS_LOST_STATUS) = LIVELINESS_LOST_STATUS, "Expected: 1", "Received 0"); + AffirmIf(status_id,(status(0) and LIVELINESS_LOST_STATUS) = LIVELINESS_LOST_STATUS, "Expected: 1", "Received 0"); + AffirmIf(status_id,(status(1) and LIVELINESS_LOST_STATUS) = LIVELINESS_LOST_STATUS, "Expected: 1", "Received 0"); - Log("DDS Operation GET_LIVELINESS_LOST_STATUS (Expected: count 3, change 2)", INFO); + Log("W0: DDS Operation GET_LIVELINESS_LOST_STATUS (Expected: count 3, change 2)", INFO); dds := DEFAULT_DDS_WRITER_TEST; dds.opcode := GET_LIVELINESS_LOST_STATUS; dds.ret_code := RETCODE_OK; dds.count := 3; dds.change := 2; + -- WRITER 0 + ind <= 0; start_dds; - wait_on_dds; - - wait_on_idle; - AffirmIf(status_id,(status and LIVELINESS_LOST_STATUS) /= LIVELINESS_LOST_STATUS, "Expected: 0", "Received 1"); - - Log("Current Time: 6.5s", INFO); - check_time <= gen_duration(6,500); - wait until rising_edge(clk); - wait until rising_edge(clk); + wait_on_sig(dds_done); wait_on_idle; - AffirmIf(status_id,(status and LIVELINESS_LOST_STATUS) /= LIVELINESS_LOST_STATUS, "Expected: 0", "Received 1"); + AffirmIf(status_id,(status(0) and LIVELINESS_LOST_STATUS) /= LIVELINESS_LOST_STATUS, "Expected: 0", "Received 1"); + AffirmIf(status_id,(status(1) and LIVELINESS_LOST_STATUS) = LIVELINESS_LOST_STATUS, "Expected: 1", "Received 0"); - Log("DDS Operation ASSERT_LIVELINESS (OK)", INFO); + Log("W1: DDS Operation GET_LIVELINESS_LOST_STATUS (Expected: count 1, change 1)", INFO); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := GET_LIVELINESS_LOST_STATUS; + dds.ret_code := RETCODE_OK; + dds.count := 1; + dds.change := 1; + -- WRITER 1 + ind <= 1; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + + AffirmIf(status_id,(status(0) and LIVELINESS_LOST_STATUS) /= LIVELINESS_LOST_STATUS, "Expected: 0", "Received 1"); + AffirmIf(status_id,(status(1) and LIVELINESS_LOST_STATUS) /= LIVELINESS_LOST_STATUS, "Expected: 0", "Received 1"); + + Log("W0: DDS Operation ASSERT_LIVELINESS", INFO); + Log("W0: OK", DEBUG); dds := DEFAULT_DDS_WRITER_TEST; dds.opcode := ASSERT_LIVELINESS; dds.ret_code := RETCODE_OK; dds.assertion := '1'; + -- WRITER 0 + ind <= 0; start_dds; - wait_on_dds; + wait_on_sig(dds_done); + wait_on_idle; - Log("Current Time: 7s", INFO); - check_time <= gen_duration(7,0); + Log("Current Time: 6.5s", INFO); + check_time <= gen_duration(6.5 sec); wait until rising_edge(clk); wait until rising_edge(clk); wait_on_idle; - AffirmIf(status_id,(status and LIVELINESS_LOST_STATUS) /= LIVELINESS_LOST_STATUS, "Expected: 0", "Received 1"); + AffirmIf(status_id,(status(0) and LIVELINESS_LOST_STATUS) /= LIVELINESS_LOST_STATUS, "Expected: 0", "Received 1"); + AffirmIf(status_id,(status(1) and LIVELINESS_LOST_STATUS) /= LIVELINESS_LOST_STATUS, "Expected: 0", "Received 1"); + + Log("W0: DDS Operation ASSERT_LIVELINESS", INFO); + Log("W0: OK", DEBUG); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := ASSERT_LIVELINESS; + dds.ret_code := RETCODE_OK; + dds.assertion := '1'; + -- WRITER 0 + ind <= 0; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + + Log("Current Time: 7s", INFO); + check_time <= gen_duration(7 sec); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait_on_idle; + + AffirmIf(status_id,(status(0) and LIVELINESS_LOST_STATUS) /= LIVELINESS_LOST_STATUS, "Expected: 0", "Received 1"); + AffirmIf(status_id,(status(1) and LIVELINESS_LOST_STATUS) = LIVELINESS_LOST_STATUS, "Expected: 1", "Received 0"); + + Log("W1: DDS Operation GET_LIVELINESS_LOST_STATUS (Expected: count 1, change 1)", INFO); + dds := DEFAULT_DDS_WRITER_TEST; + dds.opcode := GET_LIVELINESS_LOST_STATUS; + dds.ret_code := RETCODE_OK; + dds.count := 2; + dds.change := 1; + -- WRITER 1 + ind <= 1; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + + AffirmIf(status_id,(status(0) and LIVELINESS_LOST_STATUS) /= LIVELINESS_LOST_STATUS, "Expected: 0", "Received 1"); + AffirmIf(status_id,(status(1) and LIVELINESS_LOST_STATUS) /= LIVELINESS_LOST_STATUS, "Expected: 0", "Received 1"); wait_on_completion; TranscriptOpen(RESULTS_FILE, APPEND_MODE); @@ -441,13 +565,6 @@ begin wait for 25 ns; end process; - alert_prc : process(all) - begin - if rising_edge(clk) then - -- TODO - end if; - end process; - dds_prc : process(all) begin if rising_edge(clk) then @@ -460,7 +577,7 @@ begin dds_done <= '1'; end if; when START => - if (ack_dds = '1') then + if (ack_dds(ind) = '1') then case (dds.opcode) is when GET_LIVELINESS_LOST_STATUS => dds_stage <= DONE; @@ -474,7 +591,7 @@ begin end case; end if; when PUSH => - if (ready_in_dds = '1') then + if (ready_in_dds(ind) = '1') then dds_cnt <= dds_cnt + 1; if (dds_cnt = dds.cc.payload.length-1) then -- DEFAULT @@ -482,11 +599,11 @@ begin end if; end if; when DONE => - if (done_dds = '1') then + if (done_dds(ind) = '1') then if (dds.opcode = REGISTER_INSTANCE or dds.opcode = LOOKUP_INSTANCE) then - AffirmIfEqual(ih_id, to_unsigned(instance_handle_out_dds), to_unsigned(dds.cc.instance)); + AffirmIfEqual(ih_id, to_unsigned(instance_handle_out_dds(ind)), to_unsigned(dds.cc.instance)); else - AffirmIfEqual(ret_id, return_code_dds, dds.ret_code); + AffirmIfEqual(ret_id, return_code_dds(ind), dds.ret_code); case (dds.opcode) is when GET_LIVELINESS_LOST_STATUS => if (dds.ret_code = RETCODE_OK) then @@ -496,7 +613,7 @@ begin dds_stage <= IDLE; end if; when ASSERT_LIVELINESS => - AffirmIfEqual(assert_id, liveliness_assertion, dds.assertion); + AffirmIfEqual(assert_id, liveliness_assertion(ind), dds.assertion); dds_stage <= IDLE; when others => dds_stage <= IDLE; @@ -504,14 +621,14 @@ begin end if; end if; when CHECK_LIVELINESS => - if (valid_out_dds = '1') then + if (valid_out_dds(ind) = '1') then dds_cnt <= dds_cnt + 1; case (dds_cnt) is when 0 => - AffirmIfEqual(data_id, data_out_dds, std_logic_vector(to_unsigned(dds.count,CDR_LONG_WIDTH))); + AffirmIfEqual(data_id, data_out_dds(ind), std_logic_vector(to_unsigned(dds.count,CDR_LONG_WIDTH))); when 1 => - AffirmIfEqual(data_id, data_out_dds, std_logic_vector(to_unsigned(dds.change,CDR_LONG_WIDTH))); - AlertIf(data_id, last_word_out_dds /= '1', "Last Word Signal not pulled High", ERROR); + AffirmIfEqual(data_id, data_out_dds(ind), std_logic_vector(to_unsigned(dds.change,CDR_LONG_WIDTH))); + AlertIf(data_id, last_word_out_dds(ind) /= '1', "Last Word Signal not pulled High", ERROR); dds_stage <= IDLE; when others => null; @@ -521,27 +638,27 @@ begin end if; -- DEFAULT - start_dds <= '0'; - opcode_dds <= NOP; - valid_in_dds <= '0'; - last_word_in_dds <= '0'; - data_in_dds <= (others => '0'); - instance_handle_in_dds <= HANDLE_NIL; - source_ts_dds <= TIME_INVALID; - ready_out_dds <= '0'; + start_dds <= (others => '0'); + opcode_dds <= (others => NOP); + valid_in_dds <= (others => '0'); + last_word_in_dds <= (others => '0'); + data_in_dds <= (others => (others => '0')); + instance_handle_in_dds <= (others => HANDLE_NIL); + source_ts_dds <= (others => TIME_INVALID); + ready_out_dds <= (others => '0'); case (dds_stage) is when START => - start_dds <= '1'; - opcode_dds <= dds.opcode; - instance_handle_in_dds <= dds.cc.instance; - source_ts_dds <= dds.cc.src_timestamp; + start_dds(ind) <= '1'; + opcode_dds(ind) <= dds.opcode; + instance_handle_in_dds(ind) <= dds.cc.instance; + source_ts_dds(ind) <= dds.cc.src_timestamp; when PUSH => - valid_in_dds <= '1'; - data_in_dds <= dds.cc.payload.data(dds_cnt); - last_word_in_dds <= dds.cc.payload.last(dds_cnt); + valid_in_dds(ind) <= '1'; + data_in_dds(ind) <= dds.cc.payload.data(dds_cnt); + last_word_in_dds(ind) <= dds.cc.payload.last(dds_cnt); when CHECK_LIVELINESS => - ready_out_dds <= '1'; + ready_out_dds(ind) <= '1'; when others => null; end case; @@ -559,39 +676,36 @@ begin rtps_done <= '1'; end if; when START => - if (ack_rtps = '1') then + if (ack_rtps(ind) = '1') then rtps_stage <= DONE; end if; when DONE => - if (done_rtps = '1') then + if (done_rtps(ind) = '1') then -- DEFAULT rtps_stage <= IDLE; - AffirmIfEqual(ret_id, HISTORY_CACHE_RESPONSE_TYPE'pos(ret_rtps), HISTORY_CACHE_RESPONSE_TYPE'pos(rtps.ret_code)); + AffirmIfEqual(ret_id, HISTORY_CACHE_RESPONSE_TYPE'pos(ret_rtps(ind)), HISTORY_CACHE_RESPONSE_TYPE'pos(rtps.ret_code)); case (rtps.opcode) is when GET_CACHE_CHANGE => if (rtps.ret_code = OK) then - AffirmIfEqual(inst_id, cc_instance_handle(0), rtps.cc.instance(0)); - AffirmIfEqual(inst_id, cc_instance_handle(1), rtps.cc.instance(1)); - AffirmIfEqual(inst_id, cc_instance_handle(2), rtps.cc.instance(2)); - AffirmIfEqual(inst_id, cc_instance_handle(3), rtps.cc.instance(3)); - AffirmIfEqual(kind_id, CACHE_CHANGE_KIND_TYPE'pos(cc_kind), CACHE_CHANGE_KIND_TYPE'pos(rtps.cc.kind)); - AffirmIfEqual(sn_id, to_unsigned(cc_seq_nr), to_unsigned(rtps.cc.seq_nr)); - AffirmIfEqual(ts_id, to_unsigned(cc_source_timestamp), to_unsigned(rtps.cc.src_timestamp)); + AffirmIfEqual(inst_id, to_unsigned(cc_instance_handle(ind)), to_unsigned(rtps.cc.instance)); + AffirmIfEqual(kind_id, CACHE_CHANGE_KIND_TYPE'pos(cc_kind(ind)), CACHE_CHANGE_KIND_TYPE'pos(rtps.cc.kind)); + AffirmIfEqual(sn_id, to_unsigned(cc_seq_nr(ind)), to_unsigned(rtps.cc.seq_nr)); + AffirmIfEqual(ts_id, to_unsigned(cc_source_timestamp(ind)), to_unsigned(rtps.cc.src_timestamp)); rtps_stage <= CHECK; rtps_cnt <= 0; end if; when GET_MIN_SN => - AffirmIfEqual(sn_id, to_unsigned(cc_seq_nr), to_unsigned(rtps.cc.seq_nr)); + AffirmIfEqual(sn_id, to_unsigned(cc_seq_nr(ind)), to_unsigned(rtps.cc.seq_nr)); when GET_MAX_SN => - AffirmIfEqual(sn_id, to_unsigned(cc_seq_nr), to_unsigned(rtps.cc.seq_nr)); + AffirmIfEqual(sn_id, to_unsigned(cc_seq_nr(ind)), to_unsigned(rtps.cc.seq_nr)); when others => null; end case; end if; when CHECK => - if (valid_out_rtps = '1') then - AffirmIfEqual(data_id, last_word_out_rtps & data_out_rtps, rtps.cc.payload.last(rtps_cnt) & rtps.cc.payload.data(rtps_cnt)); + if (valid_out_rtps(ind) = '1') then + AffirmIfEqual(data_id, last_word_out_rtps(ind) & data_out_rtps(ind), rtps.cc.payload.last(rtps_cnt) & rtps.cc.payload.data(rtps_cnt)); rtps_cnt <= rtps_cnt + 1; if (rtps_cnt = rtps.cc.payload.length-1) then rtps_stage <= IDLE; @@ -601,28 +715,28 @@ begin end if; -- DEFAULT - start_rtps <= '0'; - opcode_rtps <= NOP; - seq_nr_rtps <= SEQUENCENUMBER_UNKNOWN; - get_data_rtps <= '0'; - ready_out_rtps <= '0'; + start_rtps <= (others => '0'); + opcode_rtps <= (others => NOP); + seq_nr_rtps <= (others => SEQUENCENUMBER_UNKNOWN); + get_data_rtps <= (others => '0'); + ready_out_rtps <= (others => '0'); case (rtps_stage) is when START => - start_rtps <= '1'; - opcode_rtps <= rtps.opcode; - seq_nr_rtps <= rtps.cc.seq_nr; + start_rtps(ind) <= '1'; + opcode_rtps(ind) <= rtps.opcode; + seq_nr_rtps(ind) <= rtps.cc.seq_nr; when DONE => - if (done_rtps = '1') then + if (done_rtps(ind) = '1') then case (rtps.opcode) is when GET_CACHE_CHANGE => - get_data_rtps <= '1'; + get_data_rtps(ind) <= '1'; when others => null; end case; end if; when CHECK => - ready_out_rtps <= '1'; + ready_out_rtps(ind) <= '1'; when others => null; end case; diff --git a/src/Tests/Level_0/L0_dds_writer_test5_afk.vhd b/src/Tests/Level_0/L0_dds_writer_test5.vhd similarity index 62% rename from src/Tests/Level_0/L0_dds_writer_test5_afk.vhd rename to src/Tests/Level_0/L0_dds_writer_test5.vhd index 50a44b3..fe9c8c4 100644 --- a/src/Tests/Level_0/L0_dds_writer_test5_afk.vhd +++ b/src/Tests/Level_0/L0_dds_writer_test5.vhd @@ -12,13 +12,41 @@ use work.rtps_test_package.all; -- This testbench tests the Lifespan Handling of the DDS Writer. -entity L0_dds_writer_test5_afk is +entity L0_dds_writer_test5 is end entity; -architecture testbench of L0_dds_writer_test5_afk is +architecture testbench of L0_dds_writer_test5 is -- *CONSTANT DECLARATION* constant MAX_REMOTE_ENDPOINTS : natural := 3; + constant NUM_WRITERS : natural := 2; + + impure function gen_test_config return CONFIG_ARRAY_TYPE is + variable ret : CONFIG_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => DEFAULT_WRITER_CONFIG); + begin + -- aik + ret(0).HISTORY_QOS := KEEP_ALL_HISTORY_QOS; + ret(0).DEADLINE_QOS := DURATION_INFINITE; + ret(0).LIFESPAN_QOS := gen_duration(2 sec); + ret(0).LEASE_DURATION := DURATION_INFINITE; + ret(0).WITH_KEY := TRUE; + ret(0).MAX_SAMPLES := std_logic_vector(to_unsigned(4,CDR_LONG_WIDTH)); + ret(0).MAX_INSTANCES := std_logic_vector(to_unsigned(2,CDR_LONG_WIDTH)); + ret(0).MAX_SAMPLES_PER_INSTANCE := std_logic_vector(to_unsigned(2,CDR_LONG_WIDTH)); + ret(0).MAX_PAYLOAD_SIZE := 40; + -- ain + ret(1).HISTORY_QOS := KEEP_ALL_HISTORY_QOS; + ret(1).DEADLINE_QOS := DURATION_INFINITE; + ret(1).LIFESPAN_QOS := gen_duration(3 sec); + ret(1).LEASE_DURATION := DURATION_INFINITE; + ret(1).WITH_KEY := FALSE; + ret(1).MAX_SAMPLES := std_logic_vector(to_unsigned(4,CDR_LONG_WIDTH)); + ret(1).MAX_INSTANCES := std_logic_vector(to_unsigned(2,CDR_LONG_WIDTH)); + ret(1).MAX_SAMPLES_PER_INSTANCE := std_logic_vector(to_unsigned(4,CDR_LONG_WIDTH)); + ret(1).MAX_PAYLOAD_SIZE := 40; + return ret; + end function; + constant TEST_CONFIG : CONFIG_ARRAY_TYPE := gen_test_config; -- *TYPE DECLARATION* type DDS_STAGE_TYPE is (IDLE, START, PUSH, DONE); @@ -28,22 +56,23 @@ architecture testbench of L0_dds_writer_test5_afk is signal clk : std_logic := '0'; signal reset : std_logic := '1'; signal check_time : TIME_TYPE := TIME_ZERO; - signal start_rtps, start_dds, ack_rtps, ack_dds, done_rtps, done_dds : std_logic := '0'; - signal opcode_rtps : HISTORY_CACHE_OPCODE_TYPE := NOP; - signal opcode_dds : DDS_WRITER_OPCODE_TYPE := NOP; - signal ret_rtps : HISTORY_CACHE_RESPONSE_TYPE := ERROR; - signal seq_nr_rtps, cc_seq_nr : SEQUENCENUMBER_TYPE := SEQUENCENUMBER_UNKNOWN; - signal ready_out_rtps, valid_out_rtps, last_word_out_rtps : std_logic := '0'; - signal ready_in_dds, ready_out_dds, valid_in_dds, valid_out_dds, last_word_in_dds, last_word_out_dds : std_logic := '0'; - signal data_out_rtps, data_in_dds, data_out_dds : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); - signal get_data_rtps, liveliness_assertion, data_available : std_logic := '0'; - signal cc_source_timestamp, source_ts_dds : TIME_TYPE := TIME_INVALID; - signal cc_kind : CACHE_CHANGE_KIND_TYPE := ALIVE; - signal cc_instance_handle, instance_handle_in_dds, instance_handle_out_dds : INSTANCE_HANDLE_TYPE := HANDLE_NIL; - signal max_wait_dds : DURATION_TYPE := DURATION_INFINITE; - signal return_code_dds : std_logic_vector(RETURN_CODE_WIDTH-1 downto 0) := (others => '0'); - signal status : std_logic_vector(STATUS_KIND_WIDTH-1 downto 0) := (others => '0'); + signal start_rtps, start_dds, ack_rtps, ack_dds, done_rtps, done_dds, w_map : std_logic_vector(0 to NUM_WRITERS-1) := (others => '0'); + signal opcode_rtps : HISTORY_CACHE_OPCODE_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => NOP); + signal opcode_dds : DDS_WRITER_OPCODE_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => NOP); + signal ret_rtps : HISTORY_CACHE_RESPONSE_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => ERROR); + signal seq_nr_rtps, cc_seq_nr : SEQUENCENUMBER_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => SEQUENCENUMBER_UNKNOWN); + signal ready_out_rtps, valid_out_rtps, last_word_out_rtps : std_logic_vector(0 to NUM_WRITERS-1) := (others => '0'); + signal ready_in_dds, ready_out_dds, valid_in_dds, valid_out_dds, last_word_in_dds, last_word_out_dds : std_logic_vector(0 to NUM_WRITERS-1) := (others => '0'); + signal data_out_rtps, data_in_dds, data_out_dds : WORD_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => (others => '0')); + signal get_data_rtps, liveliness_assertion, data_available : std_logic_vector(0 to NUM_WRITERS-1) := (others => '0'); + signal cc_source_timestamp, source_ts_dds : TIME_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => TIME_INVALID); + signal cc_kind : CACHE_CHANGE_KIND_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => ALIVE); + signal cc_instance_handle, instance_handle_in_dds, instance_handle_out_dds : INSTANCE_HANDLE_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => HANDLE_NIL); + signal max_wait_dds : DURATION_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => DURATION_INFINITE); + signal return_code_dds : RETURN_CODE_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => (others => '0')); + signal status : STATUS_KIND_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => (others => '0')); + signal ind : natural := 0; signal dds_start, dds_done, rtps_start, rtps_done : std_logic := '0'; signal dds_cnt, rtps_cnt : natural := 0; signal dds_stage : DDS_STAGE_TYPE := IDLE; @@ -71,20 +100,20 @@ architecture testbench of L0_dds_writer_test5_afk is return ret; end function; + procedure wait_on_sig(signal sig : std_logic) is + begin + if (sig /= '1') then + wait on sig until sig = '1'; + end if; + end procedure; + begin -- Unit Under Test uut : entity work.dds_writer(arch) generic map( - HISTORY_QOS => KEEP_ALL_HISTORY_QOS, - DEADLINE_QOS => DURATION_INFINITE, - LIFESPAN_QOS => gen_duration(2,0), - LEASE_DURATION => DURATION_INFINITE, - WITH_KEY => TRUE, - MAX_SAMPLES => std_logic_vector(to_unsigned(4,CDR_LONG_WIDTH)), - MAX_INSTANCES => std_logic_vector(to_unsigned(2,CDR_LONG_WIDTH)), - MAX_SAMPLES_PER_INSTANCE => std_logic_vector(to_unsigned(2,CDR_LONG_WIDTH)), - PAYLOAD_FRAME_SIZE => 11 + NUM_WRITERS => NUM_WRITERS, + CONFIG_ARRAY => to_QUARTUS_CONFIG_ARRAY_TYPE(TEST_CONFIG) ) port map ( clk => clk, @@ -178,20 +207,6 @@ begin wait until rising_edge(clk); end procedure; - procedure wait_on_dds is - begin - if (dds_done /= '1') then - wait until dds_done = '1'; - end if; - end procedure; - - procedure wait_on_rtps is - begin - if (rtps_done /= '1') then - wait until rtps_done = '1'; - end if; - end procedure; - procedure wait_on_completion is begin if (rtps_done /= '1' or dds_done /= '1') then @@ -202,21 +217,23 @@ begin -- NOTE: This procedure waits until the idle_sig is high for at least -- two consecutive clock cycles. procedure wait_on_idle is + variable first : boolean := TRUE; begin loop if (idle_sig /= '1') then wait until idle_sig = '1'; - else + elsif (not first) then exit; end if; wait until rising_edge(clk); wait until rising_edge(clk); + first := FALSE; end loop; end procedure; begin - SetAlertLogName("L0_dds_writer_test5_afk - (KEEP ALL, Infinite Lifespan, Keyed) - Lifespan Handling"); + SetAlertLogName("L0_dds_writer_test5 - Lifespan Handling"); SetAlertEnable(FAILURE, TRUE); SetAlertEnable(ERROR, TRUE); SetAlertEnable(WARNING, TRUE); @@ -248,7 +265,6 @@ begin wait until rising_edge(clk); reset <= '0'; wait_on_idle; - -- Stored CC: 0, 0, 0, 0 cc := DEFAULT_CACHE_CHANGE; cc.serialized_key := FALSE; @@ -257,16 +273,22 @@ begin cc.payload := gen_payload(kh1,10); cc.seq_nr := gen_sn(1); - Log("DDS Operation WRITE [Instance 1, HANDLE_NIL, Aligned Payload] (ACCEPTED)", INFO); + Log("W0,W1: DDS Operation WRITE [Instance 1, HANDLE_NIL, Aligned Payload] (ACCEPTED)", INFO); + Log("W0,W1: ACCEPTED", DEBUG); dds := DEFAULT_DDS_WRITER_TEST; dds.opcode := WRITE; dds.cc := cc; dds.cc.instance:= HANDLE_NIL; dds.ret_code := RETCODE_OK; + -- WRITER 0 + ind <= 0; start_dds; - wait_on_dds; - cc1 := cc; - -- Stored CC: I1S1, 0, 0, 0 + wait_on_sig(dds_done); + -- WRITER 1 + ind <= 1; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; cc := DEFAULT_CACHE_CHANGE; cc.serialized_key := FALSE; @@ -275,19 +297,25 @@ begin cc.payload := gen_payload(kh2,10); cc.seq_nr := gen_sn(2); - Log("DDS Operation WRITE [Instance 2, HANDLE_NIL, Aligned Payload] (ACCEPTED)", INFO); + Log("W0,W1: DDS Operation WRITE [Instance 2, HANDLE_NIL, Aligned Payload]", INFO); + Log("W0,W1: ACCEPTED", DEBUG); dds := DEFAULT_DDS_WRITER_TEST; dds.opcode := WRITE; dds.cc := cc; dds.cc.instance:= HANDLE_NIL; dds.ret_code := RETCODE_OK; + -- WRITER 0 + ind <= 0; start_dds; - wait_on_dds; - cc2 := cc; - -- Stored CC: I1S1, I2S2, 0, 0 + wait_on_sig(dds_done); + -- WRITER 1 + ind <= 1; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; Log("Current Time: 1s", INFO); - check_time <= gen_duration(1,0); + check_time <= gen_duration(1 sec); wait until rising_edge(clk); wait until rising_edge(clk); wait_on_idle; @@ -299,16 +327,22 @@ begin cc.payload := gen_payload(kh1,10); cc.seq_nr := gen_sn(3); - Log("DDS Operation WRITE [Instance 1, HANDLE_NIL, Aligned Payload] (ACCEPTED)", INFO); + Log("W0,W1: DDS Operation WRITE [Instance 1, HANDLE_NIL, Aligned Payload]", INFO); + Log("W0,W1: ACCEPTED", DEBUG); dds := DEFAULT_DDS_WRITER_TEST; dds.opcode := WRITE; dds.cc := cc; dds.cc.instance:= HANDLE_NIL; dds.ret_code := RETCODE_OK; + -- WRITER 0 + ind <= 0; start_dds; - wait_on_dds; - cc3 := cc; - -- Stored CC: I1S1, I2S2, I1S3, 0 + wait_on_sig(dds_done); + -- WRITER 1 + ind <= 1; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; cc := DEFAULT_CACHE_CHANGE; cc.serialized_key := FALSE; @@ -317,14 +351,24 @@ begin cc.payload := gen_payload(kh1,10); cc.seq_nr := gen_sn(4); - Log("DDS Operation WRITE [Instance 1, HANDLE_NIL, Aligned Payload] (REJECTED: MAX_SAMPLES_PER_INSTANCE exceeded)", INFO); + Log("W0,W1: DDS Operation WRITE [Instance 1, HANDLE_NIL, Aligned Payload]", INFO); + Log("W0: REJECTED [MAX_SAMPLES_PER_INSTANCE exceeded]", DEBUG); + Log("W1: ACCEPTED", DEBUG); dds := DEFAULT_DDS_WRITER_TEST; dds.opcode := WRITE; dds.cc := cc; dds.cc.instance:= HANDLE_NIL; + -- WRITER 0 dds.ret_code := RETCODE_OUT_OF_RESOURCES; + ind <= 0; start_dds; - wait_on_dds; + wait_on_sig(dds_done); + -- WRITER 1 + dds.ret_code := RETCODE_OK; + ind <= 1; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; cc := DEFAULT_CACHE_CHANGE; cc.serialized_key := TRUE; @@ -333,38 +377,66 @@ begin cc.payload := gen_payload(kh2,5); cc.seq_nr := gen_sn(4); - Log("DDS Operation UNREGISTER_INSTANCE [Instance 2] (ACCEPTED)", INFO); + Log("W0,W1: DDS Operation UNREGISTER_INSTANCE [Instance 2]", INFO); + Log("W0: ACCEPTED", DEBUG); + Log("W1: REJECTED [MAX_SAMPLES exceeded]", DEBUG); dds := DEFAULT_DDS_WRITER_TEST; dds.opcode := UNREGISTER_INSTANCE; dds.cc := cc; + -- WRITER 0 dds.ret_code := RETCODE_OK; + ind <= 0; start_dds; - wait_on_dds; - cc4 := cc; - -- Stored CC: I1S1, I2S2, I1S3, I2S4 + wait_on_sig(dds_done); + -- WRITER 1 + dds.cc.instance := HANDLE_NIL; + dds.ret_code := RETCODE_OUT_OF_RESOURCES; + ind <= 1; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; Log("Current Time: 2s", INFO); - check_time <= gen_duration(2,0); + check_time <= gen_duration(2 sec); wait until rising_edge(clk); wait until rising_edge(clk); wait_on_idle; - -- Stored CC: 0, 0, I1S3, I2S4 -- VALIDATE STATE - Log("RTPS Operation GET_MIN_SN (Expected SN 3)", INFO); + Log("W0,W1: RTPS Operation GET_MIN_SN", INFO); + Log("W0: Expected SN 3", DEBUG); + Log("W1: Expected SN 1", DEBUG); rtps := DEFAULT_RTPS_WRITER_TEST; rtps.opcode := GET_MIN_SN; + -- WRITER 0 rtps.cc.seq_nr := gen_sn(3); + ind <= 0; start_rtps; - wait_on_rtps; + wait_on_sig(rtps_done); + -- WRITER 1 + rtps.cc.seq_nr := gen_sn(1); + ind <= 1; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; - Log("RTPS Operation GET_MAX_SN (Expected SN 4)", INFO); + Log("W0,W1: RTPS Operation GET_MAX_SN", INFO); + Log("W0: Expected SN 4", DEBUG); + Log("W1: Expected SN 4", DEBUG); rtps := DEFAULT_RTPS_WRITER_TEST; rtps.opcode := GET_MAX_SN; + -- WRITER 0 rtps.cc.seq_nr := gen_sn(4); + ind <= 0; start_rtps; - wait_on_rtps; + wait_on_sig(rtps_done); + -- WRITER 1 + rtps.cc.seq_nr := gen_sn(4); + ind <= 1; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; cc := DEFAULT_CACHE_CHANGE; cc.serialized_key := FALSE; @@ -373,16 +445,24 @@ begin cc.payload := gen_payload(kh1,10); cc.seq_nr := gen_sn(5); - Log("DDS Operation WRITE [Instance 1, HANDLE_NIL, Aligned Payload] (ACCEPTED)", INFO); + Log("W0,W1: DDS Operation WRITE [Instance 1, HANDLE_NIL, Aligned Payload]", INFO); + Log("W0: ACCEPTED", DEBUG); + Log("W1: REJECTED [MAX_SAMPLES exceeded]", DEBUG); dds := DEFAULT_DDS_WRITER_TEST; dds.opcode := WRITE; dds.cc := cc; dds.cc.instance:= HANDLE_NIL; + -- WRITER 0 dds.ret_code := RETCODE_OK; + ind <= 0; start_dds; - wait_on_dds; - cc1 := cc; - -- Stored CC: I1S5, 0, I1S3, I2S4 + wait_on_sig(dds_done); + -- WRITER 1 + dds.ret_code := RETCODE_OUT_OF_RESOURCES; + ind <= 1; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; cc := DEFAULT_CACHE_CHANGE; cc.serialized_key := FALSE; @@ -391,37 +471,66 @@ begin cc.payload := gen_payload(kh3,10); cc.seq_nr := gen_sn(6); - Log("DDS Operation WRITE [Instance 3, HANDLE_NIL, Aligned Payload] (REJECTED: MAX_INSTANCES exceeded)", INFO); + Log("W0,W1: DDS Operation WRITE [Instance 3, HANDLE_NIL, Aligned Payload]", INFO); + Log("W0: REJECTED [MAX_INSTANCES exceeded]", DEBUG); + Log("W1: REJECTED [MAX_SAMPLES exceeded]", DEBUG); dds := DEFAULT_DDS_WRITER_TEST; dds.opcode := WRITE; dds.cc := cc; dds.cc.instance:= HANDLE_NIL; + -- WRITER 0 dds.ret_code := RETCODE_OUT_OF_RESOURCES; + ind <= 0; start_dds; - wait_on_dds; + wait_on_sig(dds_done); + -- WRITER 1 + dds.ret_code := RETCODE_OUT_OF_RESOURCES; + ind <= 1; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; Log("Current Time: 3s", INFO); - check_time <= gen_duration(3,0); + check_time <= gen_duration(3 sec); wait until rising_edge(clk); wait until rising_edge(clk); wait_on_idle; - -- Stored CC: I1S5, 0, 0, 0 -- VALIDATE STATE - Log("RTPS Operation GET_MIN_SN (Expected SN 5)", INFO); + Log("W0,W1: RTPS Operation GET_MIN_SN", INFO); + Log("W0: Expected SN 5", DEBUG); + Log("W1: Expected SN 3", DEBUG); rtps := DEFAULT_RTPS_WRITER_TEST; rtps.opcode := GET_MIN_SN; + -- WRITER 0 rtps.cc.seq_nr := gen_sn(5); + ind <= 0; start_rtps; - wait_on_rtps; + wait_on_sig(rtps_done); + -- WRITER 1 + rtps.cc.seq_nr := gen_sn(3); + ind <= 1; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; - Log("RTPS Operation GET_MAX_SN (Expected SN 5)", INFO); + Log("W0,W1: RTPS Operation GET_MAX_SN", INFO); + Log("W0: Expected SN 5", DEBUG); + Log("W1: Expected SN 4", DEBUG); rtps := DEFAULT_RTPS_WRITER_TEST; rtps.opcode := GET_MAX_SN; + -- WRITER 0 rtps.cc.seq_nr := gen_sn(5); + ind <= 0; start_rtps; - wait_on_rtps; + wait_on_sig(rtps_done); + -- WRITER 1 + rtps.cc.seq_nr := gen_sn(4); + ind <= 1; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; cc := DEFAULT_CACHE_CHANGE; cc.serialized_key := FALSE; @@ -430,16 +539,22 @@ begin cc.payload := gen_payload(kh3,10); cc.seq_nr := gen_sn(6); - Log("DDS Operation WRITE [Instance 3, HANDLE_NIL, Aligned Payload] (ACCEPTED)", INFO); + Log("W0,W1: DDS Operation WRITE [Instance 3, HANDLE_NIL, Aligned Payload]", INFO); + Log("W0,W1: ACCEPTED", DEBUG); dds := DEFAULT_DDS_WRITER_TEST; dds.opcode := WRITE; dds.cc := cc; dds.cc.instance:= HANDLE_NIL; dds.ret_code := RETCODE_OK; + -- WRITER 0 + ind <= 0; start_dds; - wait_on_dds; - cc2 := cc; - -- Stored CC: I1S5, I3S6, 0, 0 + wait_on_sig(dds_done); + -- WRITER 1 + ind <= 1; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; wait_on_completion; TranscriptOpen(RESULTS_FILE, APPEND_MODE); @@ -458,13 +573,6 @@ begin wait for 25 ns; end process; - alert_prc : process(all) - begin - if rising_edge(clk) then - -- TODO - end if; - end process; - dds_prc : process(all) begin if rising_edge(clk) then @@ -477,15 +585,12 @@ begin dds_done <= '1'; end if; when START => - if (ack_dds = '1') then - case (dds.opcode) is - when others => - dds_stage <= PUSH; - dds_cnt <= 0; - end case; + if (ack_dds(ind) = '1') then + dds_stage <= PUSH; + dds_cnt <= 0; end if; when PUSH => - if (ready_in_dds = '1') then + if (ready_in_dds(ind) = '1') then dds_cnt <= dds_cnt + 1; if (dds_cnt = dds.cc.payload.length-1) then -- DEFAULT @@ -493,11 +598,11 @@ begin end if; end if; when DONE => - if (done_dds = '1') then + if (done_dds(ind) = '1') then if (dds.opcode = REGISTER_INSTANCE or dds.opcode = LOOKUP_INSTANCE) then - AffirmIfEqual(ih_id, to_unsigned(instance_handle_out_dds), to_unsigned(dds.cc.instance)); + AffirmIfEqual(ih_id, to_unsigned(instance_handle_out_dds(ind)), to_unsigned(dds.cc.instance)); else - AffirmIfEqual(ret_id, return_code_dds, dds.ret_code); + AffirmIfEqual(ret_id, return_code_dds(ind), dds.ret_code); end if; dds_stage <= IDLE; end if; @@ -505,25 +610,25 @@ begin end if; -- DEFAULT - start_dds <= '0'; - opcode_dds <= NOP; - valid_in_dds <= '0'; - last_word_in_dds <= '0'; - data_in_dds <= (others => '0'); - instance_handle_in_dds <= HANDLE_NIL; - source_ts_dds <= TIME_INVALID; - ready_out_dds <= '0'; + start_dds <= (others => '0'); + opcode_dds <= (others => NOP); + valid_in_dds <= (others => '0'); + last_word_in_dds <= (others => '0'); + data_in_dds <= (others => (others => '0')); + instance_handle_in_dds <= (others => HANDLE_NIL); + source_ts_dds <= (others => TIME_INVALID); + ready_out_dds <= (others => '0'); case (dds_stage) is when START => - start_dds <= '1'; - opcode_dds <= dds.opcode; - instance_handle_in_dds <= dds.cc.instance; - source_ts_dds <= dds.cc.src_timestamp; + start_dds(ind) <= '1'; + opcode_dds(ind) <= dds.opcode; + instance_handle_in_dds(ind) <= dds.cc.instance; + source_ts_dds(ind) <= dds.cc.src_timestamp; when PUSH => - valid_in_dds <= '1'; - data_in_dds <= dds.cc.payload.data(dds_cnt); - last_word_in_dds <= dds.cc.payload.last(dds_cnt); + valid_in_dds(ind) <= '1'; + data_in_dds(ind) <= dds.cc.payload.data(dds_cnt); + last_word_in_dds(ind) <= dds.cc.payload.last(dds_cnt); when others => null; end case; @@ -541,36 +646,36 @@ begin rtps_done <= '1'; end if; when START => - if (ack_rtps = '1') then + if (ack_rtps(ind) = '1') then rtps_stage <= DONE; end if; when DONE => - if (done_rtps = '1') then + if (done_rtps(ind) = '1') then -- DEFAULT rtps_stage <= IDLE; - AffirmIfEqual(ret_id, HISTORY_CACHE_RESPONSE_TYPE'pos(ret_rtps), HISTORY_CACHE_RESPONSE_TYPE'pos(rtps.ret_code)); + AffirmIfEqual(ret_id, HISTORY_CACHE_RESPONSE_TYPE'pos(ret_rtps(ind)), HISTORY_CACHE_RESPONSE_TYPE'pos(rtps.ret_code)); case (rtps.opcode) is when GET_CACHE_CHANGE => if (rtps.ret_code = OK) then - AffirmIfEqual(inst_id, to_unsigned(cc_instance_handle), to_unsigned(rtps.cc.instance)); - AffirmIfEqual(kind_id, CACHE_CHANGE_KIND_TYPE'pos(cc_kind), CACHE_CHANGE_KIND_TYPE'pos(rtps.cc.kind)); - AffirmIfEqual(sn_id, to_unsigned(cc_seq_nr), to_unsigned(rtps.cc.seq_nr)); - AffirmIfEqual(ts_id, to_unsigned(cc_source_timestamp), to_unsigned(rtps.cc.src_timestamp)); + AffirmIfEqual(inst_id, to_unsigned(cc_instance_handle(ind)), to_unsigned(rtps.cc.instance)); + AffirmIfEqual(kind_id, CACHE_CHANGE_KIND_TYPE'pos(cc_kind(ind)), CACHE_CHANGE_KIND_TYPE'pos(rtps.cc.kind)); + AffirmIfEqual(sn_id, to_unsigned(cc_seq_nr(ind)), to_unsigned(rtps.cc.seq_nr)); + AffirmIfEqual(ts_id, to_unsigned(cc_source_timestamp(ind)), to_unsigned(rtps.cc.src_timestamp)); rtps_stage <= CHECK; rtps_cnt <= 0; end if; when GET_MIN_SN => - AffirmIfEqual(sn_id, to_unsigned(cc_seq_nr), to_unsigned(rtps.cc.seq_nr)); + AffirmIfEqual(sn_id, to_unsigned(cc_seq_nr(ind)), to_unsigned(rtps.cc.seq_nr)); when GET_MAX_SN => - AffirmIfEqual(sn_id, to_unsigned(cc_seq_nr), to_unsigned(rtps.cc.seq_nr)); + AffirmIfEqual(sn_id, to_unsigned(cc_seq_nr(ind)), to_unsigned(rtps.cc.seq_nr)); when others => null; end case; end if; when CHECK => - if (valid_out_rtps = '1') then - AffirmIfEqual(data_id, last_word_out_rtps & data_out_rtps, rtps.cc.payload.last(rtps_cnt) & rtps.cc.payload.data(rtps_cnt)); + if (valid_out_rtps(ind) = '1') then + AffirmIfEqual(data_id, last_word_out_rtps(ind) & data_out_rtps(ind), rtps.cc.payload.last(rtps_cnt) & rtps.cc.payload.data(rtps_cnt)); rtps_cnt <= rtps_cnt + 1; if (rtps_cnt = rtps.cc.payload.length-1) then rtps_stage <= IDLE; @@ -580,28 +685,28 @@ begin end if; -- DEFAULT - start_rtps <= '0'; - opcode_rtps <= NOP; - seq_nr_rtps <= SEQUENCENUMBER_UNKNOWN; - get_data_rtps <= '0'; - ready_out_rtps <= '0'; + start_rtps <= (others => '0'); + opcode_rtps <= (others => NOP); + seq_nr_rtps <= (others => SEQUENCENUMBER_UNKNOWN); + get_data_rtps <= (others => '0'); + ready_out_rtps <= (others => '0'); case (rtps_stage) is when START => - start_rtps <= '1'; - opcode_rtps <= rtps.opcode; - seq_nr_rtps <= rtps.cc.seq_nr; + start_rtps(ind) <= '1'; + opcode_rtps(ind) <= rtps.opcode; + seq_nr_rtps(ind) <= rtps.cc.seq_nr; when DONE => - if (done_rtps = '1') then + if (done_rtps(ind) = '1') then case (rtps.opcode) is when GET_CACHE_CHANGE => - get_data_rtps <= '1'; + get_data_rtps(ind) <= '1'; when others => null; end case; end if; when CHECK => - ready_out_rtps <= '1'; + ready_out_rtps(ind) <= '1'; when others => null; end case; diff --git a/src/Tests/Level_0/dds_writer_tests.txt b/src/Tests/Level_0/dds_writer_tests.txt deleted file mode 100644 index 740cf5a..0000000 --- a/src/Tests/Level_0/dds_writer_tests.txt +++ /dev/null @@ -1,81 +0,0 @@ --- TEST: GET_MIN_SN/GET_MAX_SN ON EMPTY --- TEST: GET_MIN_SN/GET_MAX_SN ON 1 SAMPLE --- TEST: GET_MIN_SN/GET_MAX_SN ON >1 SAMPLE - --- TEST: ADD SAMPLE WITH KEY_HASH [UNKNOWN INSTANCE] --- TEST: ADD SAMPLE WITH KEY_HASH [KNOWN INSTANCE] --- TEST: ADD SAMPLE WITH HANDLE_NIL [UNKNOWN INSTANCE] --- TEST: ADD SAMPLE WITH HANDLE_NIL [KNOWN INSTANCE] - --- TEST: NORMAL WRITE --- TEST: WRITE ON PAYLOAD MEMORY FULL [WITHOUT ACKed SAMPLES] --- TEST: WRITE ON PAYLOAD MEMORY FULL [WITH ACKed SAMPLES] --- TEST: WRITE ON DISPOSED INSTANCE --- TEST: WRITE ON UNREGISTERED INSTANCE - --- TEST: WRITE ALIGNED PAYLOAD --- TEST: WRITE UNALIGNED PAYLOAD [>1 SLOT] --- TEST: WRITE UNALIGNED PAYLOAD [<1 SLOT] - --- TEST: NORMAL REGISTER --- TEST: REGISTER INSTANCE [KNOWN INSTANCE] --- TEST: REGISTER INSTANCE ON MAX_INSTANCES [UNKNOWN INSTANCE, WITHOUT STALE INSTANCE] --- TEST: REGISTER INSTANCE ON MAX_INSTANCES [UNKNOWN INSTANCE, WITH STALE INSTANCE] --- TEST: REGISTER ON UNREGISTERED INSTANCE - --- TEST: NORMAL DISPOSE --- TEST: DISPOSE ON PAYLOAD MEMORY FULL [WITHOUT ACKed SAMPLES] --- TEST: DISPOSE ON PAYLOAD MEMORY FULL [WITH ACKed SAMPLES] --- TEST: DISPOSE ON UNREGISTERED INSTANCE - --- TEST: GET_CACHE_CHANGE [UNKNOWN SN] --- TEST: GET_CACHE_CHANGE [KNOWN SN, ALIGNED PAYLOAD] --- TEST: GET_CACHE_CHANGE [KNOWN SN, UNALIGNED PAYLOAD, >1 SLOT] --- TEST: GET_CACHE_CHANGE [KNOWN SN, UNALIGNED PAYLOAD, <1 SLOT] - --- TEST: NORMAL ACK_CACHE_CHANGE --- TEST: ACK_CACHE_CHANGE [ALREADY ACKed SN] --- TEST: NORMAL NACK_CACHE_CHANGE - --- TEST: REMOVE_CACHE_CHANGE [UNKNOWN SN] --- TEST: REMOVE_CACHE_CHANGE [KNOWN SN] - --- TEST: NORMAL UNREGISTER --- TEST: UNREGISTER INSTANCE ON PAYLOAD MEMORY FULL [WITHOUT ACKed SAMPLES] --- TEST: UNREGISTER INSTANCE ON PAYLOAD MEMORY FULL [WITH ACKed SAMPLES] --- TEST: UNREGISTER ON DISPOSED INSTANCE --- TEST: UNREGISTER UNKNOWN INSTANCE - --- TEST: REMOVE STALE INSTANCE WITH 0 SAMPLES --- TEST: REMOVE STALE INSTANCE WITH 1 SAMPLES --- TEST: REMOVE STALE INSTANCE WITH >1 SAMPLES - --- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKNOWN INSTANCE, WITH STALE INSTANCE] --- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKNOWN INSTANCE, WITHOUT STALE INSTANCES] --- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKNOWN INSTANCE, WITH FULLY ACKed INSTANCE, WITHOUT STALE INSTANCE] - --- TEST: ADD SAMPLE ON MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE, WITHOUT ACKed SAMPLES] --- TEST: ADD SAMPLE ON MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE, WITH ACKed SAMPLES, WITHOUT ACKed INSTANCE SAMPLES] --- TEST: ADD SAMPLE ON MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE, WITH ACKed INSTANCE SAMPLE] --- TEST: ADD SAMPLE ON MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE, WITH ACKed INSTANCE SAMPLES(>1)] - --- TEST: ADD SAMPLE ON MAX_SAMPLES [KNOWN INSTANCE,WITHOUT ACKed SAMPLES] --- TEST: ADD SAMPLE ON MAX_SAMPLES [KNOWN INSTANCE,WITH ACKed SAMPLE] --- TEST: ADD SAMPLE ON MAX_SAMPLES [KNOWN INSTANCE,WITH ACKed SAMPLES (>1)] - --- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE,WITHOUT ACKed SAMPLES] --- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE,WITH ACKed SAMPLES, WITHOUT ACKed INSTANCE SAMPLES] --- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE,WITH ACKed INSTANCE SAMPLES] - --- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE,WITH STALE INSTANCE, WITHOUT ACKed SAMPLE] --- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE,WITHOUT STALE INSTANCES,WITHOUT ACKed SAMPLES] --- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE,WITHOUT STALE INSTANCE, WITH ACKed SAMPLE] --- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE,WITH STALE INSTANCE (>0 SAMPLES)] --- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE,WITH STALE INSTANCE, WITH ACKed SAMPLE] - --- TEST: ADD SAMPLE ON PAYLOAD MEMORY FULL & MAX_INSTANCES [UNKNOWN INSTANCE,WITH ACKed SAMPLES,WITH STALE INSTANCE (>= 1 SAMPLE)] (Induce Double Remove) - --- TEST: ADD SAMPLE BIGGER THAN AVAILABLE MEMORY SPACE [WITH ACKed SAMPLES] - --- TEST: INSTANCE LOOKUP [KNOWN INSTANCE] --- TEST: INSTANCE LOOKUP [UNKNOWN INSTANCE] \ No newline at end of file diff --git a/src/Tests/Level_2/L2_Testbench_Lib2.vhd b/src/Tests/Level_2/L2_Testbench_Lib2.vhd index 7105c8f..3900281 100644 --- a/src/Tests/Level_2/L2_Testbench_Lib2.vhd +++ b/src/Tests/Level_2/L2_Testbench_Lib2.vhd @@ -365,122 +365,114 @@ begin ); end generate; - dds_endpoint_gen : for i in 0 to NUM_ENDPOINTS-1 generate - dds_endpoint_if : if (i < NUM_READERS) generate - dds_reader_inst : entity work.dds_reader(arch) - generic map ( - TIME_BASED_FILTER_QOS => ENDPOINT_CONFIG(i).TIME_BASED_FILTER_QOS, - DEADLINE_QOS => ENDPOINT_CONFIG(i).DEADLINE_QOS, - MAX_INSTANCES => ENDPOINT_CONFIG(i).MAX_INSTANCES, - MAX_SAMPLES_PER_INSTANCE => ENDPOINT_CONFIG(i).MAX_SAMPLES_PER_INSTANCE, - MAX_SAMPLES => ENDPOINT_CONFIG(i).MAX_SAMPLES, - HISTORY_QOS => ENDPOINT_CONFIG(i).HISTORY_QOS, - RELIABILITY_QOS => ENDPOINT_CONFIG(i).RELIABILITY_QOS, - PRESENTATION_QOS => ENDPOINT_CONFIG(i).PRESENTATION_QOS, - DESTINATION_ORDER_QOS => ENDPOINT_CONFIG(i).DESTINATION_ORDER_QOS, - COHERENT_ACCESS => ENDPOINT_CONFIG(i).COHERENT_ACCESS, - ORDERED_ACCESS => ENDPOINT_CONFIG(i).ORDERED_ACCESS, - WITH_KEY => ENDPOINT_CONFIG(i).WITH_KEY, - PAYLOAD_FRAME_SIZE => ENDPOINT_CONFIG(i).MAX_PAYLOAD_SIZE, - MAX_REMOTE_ENDPOINTS => MAX_REMOTE_ENDPOINTS - ) - port map ( - -- SYSTEM - clk => clk, - reset => reset, - time => time, - -- FROM RTPS ENDPOINT - start_rtps => start_rr_dr(i), - opcode_rtps => opcode_rr_dr(i), - ack_rtps => ack_dr_rr(i), - done_rtps => done_dr_rr(i), - ret_rtps => ret_dr_rr(i), - valid_in_rtps => valid_rr_dr(i), - ready_in_rtps => ready_dr_rr(i), - data_in_rtps => data_rr_dr(i), - last_word_in_rtps => last_word_rr_dr(i), - -- TO USER ENTITY - start_dds => start_ri_dr(i), - ack_dds => ack_dr_ri(i), - opcode_dds => opcode_ri_dr(i), - instance_state_dds => instance_state_ri_dr(i), - view_state_dds => view_state_ri_dr(i), - sample_state_dds => sample_state_ri_dr(i), - instance_handle_dds => instance_handle_ri_dr(i), - max_samples_dds => max_samples_ri_dr(i), - get_data_dds => get_data_ri_dr(i), - done_dds => done_dr_ri(i), - return_code_dds => return_code_dr_ri(i), - valid_out_dds => valid_dr_ri(i), - ready_out_dds => ready_ri_dr(i), - data_out_dds => data_dr_ri(i), - last_word_out_dds => last_word_dr_ri(i), - sample_info => sample_info_dr_ri(i), - sample_info_valid => sample_info_valid_dr_ri(i), - sample_info_ack => sample_info_ack_ri_dr(i), - eoc => eoc_dr_ri(i), - -- Communication Status - status => status_dr_ri(i) - ); - else generate - dds_writer_inst : entity work.dds_writer(arch) - generic map ( - HISTORY_QOS => ENDPOINT_CONFIG(i).HISTORY_QOS, - DEADLINE_QOS => ENDPOINT_CONFIG(i).DEADLINE_QOS, - LIFESPAN_QOS => ENDPOINT_CONFIG(i).LIFESPAN_QOS, - LEASE_DURATION => ENDPOINT_CONFIG(i).LEASE_DURATION, - WITH_KEY => ENDPOINT_CONFIG(i).WITH_KEY, - MAX_SAMPLES => ENDPOINT_CONFIG(i).MAX_SAMPLES, - MAX_INSTANCES => ENDPOINT_CONFIG(i).MAX_INSTANCES, - MAX_SAMPLES_PER_INSTANCE => ENDPOINT_CONFIG(i).MAX_SAMPLES_PER_INSTANCE, - PAYLOAD_FRAME_SIZE => ENDPOINT_CONFIG(i).MAX_PAYLOAD_SIZE - ) - port map ( - -- SYSTEM - clk => clk, - reset => reset, - time => time, - -- TO/FROM RTPS ENDPOINT - start_rtps => start_rw_dw(i-NUM_READERS), - opcode_rtps => opcode_rw_dw(i-NUM_READERS), - ack_rtps => ack_dw_rw(i-NUM_READERS), - done_rtps => done_rw_dw(i-NUM_READERS), - ret_rtps => ret_dw_rw(i-NUM_READERS), - seq_nr_rtps => seq_nr_rw_dw(i-NUM_READERS), - get_data_rtps => get_data_rw_dw(i-NUM_READERS), - valid_out_rtps => valid_dw_rw(i-NUM_READERS), - ready_out_rtps => ready_rw_dw(i-NUM_READERS), - data_out_rtps => data_dw_rw(i-NUM_READERS), - last_word_out_rtps => last_word_dw_rw(i-NUM_READERS), - liveliness_assertion => liveliness_assertion_dw_rw(i-NUM_READERS), - data_available => data_available_dw_rw(i-NUM_READERS), - -- Cache Change - cc_instance_handle => cc_instance_handle_dw_rw(i-NUM_READERS), - cc_kind => cc_kind_dw_rw(i-NUM_READERS), - cc_source_timestamp => cc_source_timestamp_dw_rw(i-NUM_READERS), - cc_seq_nr => cc_seq_nr_dw_rw(i-NUM_READERS), - -- TO/FROM USER ENTITY - start_dds => start_wi_dw(i-NUM_READERS), - ack_dds => ack_dw_wi(i-NUM_READERS), - opcode_dds => opcode_wi_dw(i-NUM_READERS), - instance_handle_in_dds => instance_handle_wi_dw(i-NUM_READERS), - source_ts_dds => source_ts_wi_dw(i-NUM_READERS), - max_wait_dds => max_wait_wi_dw(i-NUM_READERS), - done_dds => done_dw_wi(i-NUM_READERS), - return_code_dds => return_code_dw_wi(i-NUM_READERS), - instance_handle_out_dds => instance_handle_dw_wi(i-NUM_READERS), - valid_in_dds => valid_wi_dw(i-NUM_READERS), - ready_in_dds => ready_dw_wi(i-NUM_READERS), - data_in_dds => data_wi_dw(i-NUM_READERS), - last_word_in_dds => last_word_wi_dw(i-NUM_READERS), - valid_out_dds => valid_dw_wi(i-NUM_READERS), - ready_out_dds => ready_wi_dw(i-NUM_READERS), - data_out_dds => data_dw_wi(i-NUM_READERS), - last_word_out_dds => last_word_dw_wi(i-NUM_READERS), - -- Communication Status - status => status_dw_wi(i-NUM_READERS) - ); - end generate; + dds_endpoint_w_if : if (NUM_WRITERS > 0) generate + dds_writer_inst : entity work.dds_writer(arch) + generic map ( + NUM_WRITERS => NUM_WRITERS, + CONFIG_ARRAY => to_QUARTUS_CONFIG_ARRAY_TYPE(ENDPOINT_CONFIG(NUM_READERS to NUM_ENDPOINTS-1)) + ) + port map ( + -- SYSTEM + clk => clk, + reset => reset, + time => time, + -- TO/FROM RTPS ENDPOINT + start_rtps => start_rw_dw(0 to NUM_WRITERS-1), + opcode_rtps => opcode_rw_dw(0 to NUM_WRITERS-1), + ack_rtps => ack_dw_rw(0 to NUM_WRITERS-1), + done_rtps => done_rw_dw(0 to NUM_WRITERS-1), + ret_rtps => ret_dw_rw(0 to NUM_WRITERS-1), + seq_nr_rtps => seq_nr_rw_dw(0 to NUM_WRITERS-1), + get_data_rtps => get_data_rw_dw(0 to NUM_WRITERS-1), + valid_out_rtps => valid_dw_rw(0 to NUM_WRITERS-1), + ready_out_rtps => ready_rw_dw(0 to NUM_WRITERS-1), + data_out_rtps => data_dw_rw(0 to NUM_WRITERS-1), + last_word_out_rtps => last_word_dw_rw(0 to NUM_WRITERS-1), + liveliness_assertion => liveliness_assertion_dw_rw(0 to NUM_WRITERS-1), + data_available => data_available_dw_rw(0 to NUM_WRITERS-1), + -- Cache Change + cc_instance_handle => cc_instance_handle_dw_rw(0 to NUM_WRITERS-1), + cc_kind => cc_kind_dw_rw(0 to NUM_WRITERS-1), + cc_source_timestamp => cc_source_timestamp_dw_rw(0 to NUM_WRITERS-1), + cc_seq_nr => cc_seq_nr_dw_rw(0 to NUM_WRITERS-1), + -- TO/FROM USER ENTITY + start_dds => start_wi_dw(0 to NUM_WRITERS-1), + ack_dds => ack_dw_wi(0 to NUM_WRITERS-1), + opcode_dds => opcode_wi_dw(0 to NUM_WRITERS-1), + instance_handle_in_dds => instance_handle_wi_dw(0 to NUM_WRITERS-1), + source_ts_dds => source_ts_wi_dw(0 to NUM_WRITERS-1), + max_wait_dds => max_wait_wi_dw(0 to NUM_WRITERS-1), + done_dds => done_dw_wi(0 to NUM_WRITERS-1), + return_code_dds => return_code_dw_wi(0 to NUM_WRITERS-1), + instance_handle_out_dds => instance_handle_dw_wi(0 to NUM_WRITERS-1), + valid_in_dds => valid_wi_dw(0 to NUM_WRITERS-1), + ready_in_dds => ready_dw_wi(0 to NUM_WRITERS-1), + data_in_dds => data_wi_dw(0 to NUM_WRITERS-1), + last_word_in_dds => last_word_wi_dw(0 to NUM_WRITERS-1), + valid_out_dds => valid_dw_wi(0 to NUM_WRITERS-1), + ready_out_dds => ready_wi_dw(0 to NUM_WRITERS-1), + data_out_dds => data_dw_wi(0 to NUM_WRITERS-1), + last_word_out_dds => last_word_dw_wi(0 to NUM_WRITERS-1), + -- Communication Status + status => status_dw_wi(0 to NUM_WRITERS-1) + ); + end generate; + dds_endpoint_gen : for i in 0 to NUM_READERS-1 generate + dds_reader_inst : entity work.dds_reader(arch) + generic map ( + TIME_BASED_FILTER_QOS => ENDPOINT_CONFIG(i).TIME_BASED_FILTER_QOS, + DEADLINE_QOS => ENDPOINT_CONFIG(i).DEADLINE_QOS, + MAX_INSTANCES => ENDPOINT_CONFIG(i).MAX_INSTANCES, + MAX_SAMPLES_PER_INSTANCE => ENDPOINT_CONFIG(i).MAX_SAMPLES_PER_INSTANCE, + MAX_SAMPLES => ENDPOINT_CONFIG(i).MAX_SAMPLES, + HISTORY_QOS => ENDPOINT_CONFIG(i).HISTORY_QOS, + RELIABILITY_QOS => ENDPOINT_CONFIG(i).RELIABILITY_QOS, + PRESENTATION_QOS => ENDPOINT_CONFIG(i).PRESENTATION_QOS, + DESTINATION_ORDER_QOS => ENDPOINT_CONFIG(i).DESTINATION_ORDER_QOS, + COHERENT_ACCESS => ENDPOINT_CONFIG(i).COHERENT_ACCESS, + ORDERED_ACCESS => ENDPOINT_CONFIG(i).ORDERED_ACCESS, + WITH_KEY => ENDPOINT_CONFIG(i).WITH_KEY, + PAYLOAD_FRAME_SIZE => ENDPOINT_CONFIG(i).MAX_PAYLOAD_SIZE, + MAX_REMOTE_ENDPOINTS => MAX_REMOTE_ENDPOINTS + ) + port map ( + -- SYSTEM + clk => clk, + reset => reset, + time => time, + -- FROM RTPS ENDPOINT + start_rtps => start_rr_dr(i), + opcode_rtps => opcode_rr_dr(i), + ack_rtps => ack_dr_rr(i), + done_rtps => done_dr_rr(i), + ret_rtps => ret_dr_rr(i), + valid_in_rtps => valid_rr_dr(i), + ready_in_rtps => ready_dr_rr(i), + data_in_rtps => data_rr_dr(i), + last_word_in_rtps => last_word_rr_dr(i), + -- TO USER ENTITY + start_dds => start_ri_dr(i), + ack_dds => ack_dr_ri(i), + opcode_dds => opcode_ri_dr(i), + instance_state_dds => instance_state_ri_dr(i), + view_state_dds => view_state_ri_dr(i), + sample_state_dds => sample_state_ri_dr(i), + instance_handle_dds => instance_handle_ri_dr(i), + max_samples_dds => max_samples_ri_dr(i), + get_data_dds => get_data_ri_dr(i), + done_dds => done_dr_ri(i), + return_code_dds => return_code_dr_ri(i), + valid_out_dds => valid_dr_ri(i), + ready_out_dds => ready_ri_dr(i), + data_out_dds => data_dr_ri(i), + last_word_out_dds => last_word_dr_ri(i), + sample_info => sample_info_dr_ri(i), + sample_info_valid => sample_info_valid_dr_ri(i), + sample_info_ack => sample_info_ack_ri_dr(i), + eoc => eoc_dr_ri(i), + -- Communication Status + status => status_dr_ri(i) + ); end generate; diff --git a/src/Tests/Level_2/L2_Testbench_Lib3.vhd b/src/Tests/Level_2/L2_Testbench_Lib3.vhd index fae521d..a66ca19 100644 --- a/src/Tests/Level_2/L2_Testbench_Lib3.vhd +++ b/src/Tests/Level_2/L2_Testbench_Lib3.vhd @@ -372,122 +372,114 @@ begin ); end generate; - dds_endpoint_gen : for i in 0 to NUM_ENDPOINTS-1 generate - dds_endpoint_if : if (i < NUM_READERS) generate - dds_reader_inst : entity work.dds_reader(arch) - generic map ( - TIME_BASED_FILTER_QOS => ENDPOINT_CONFIG(i).TIME_BASED_FILTER_QOS, - DEADLINE_QOS => ENDPOINT_CONFIG(i).DEADLINE_QOS, - MAX_INSTANCES => ENDPOINT_CONFIG(i).MAX_INSTANCES, - MAX_SAMPLES_PER_INSTANCE => ENDPOINT_CONFIG(i).MAX_SAMPLES_PER_INSTANCE, - MAX_SAMPLES => ENDPOINT_CONFIG(i).MAX_SAMPLES, - HISTORY_QOS => ENDPOINT_CONFIG(i).HISTORY_QOS, - RELIABILITY_QOS => ENDPOINT_CONFIG(i).RELIABILITY_QOS, - PRESENTATION_QOS => ENDPOINT_CONFIG(i).PRESENTATION_QOS, - DESTINATION_ORDER_QOS => ENDPOINT_CONFIG(i).DESTINATION_ORDER_QOS, - COHERENT_ACCESS => ENDPOINT_CONFIG(i).COHERENT_ACCESS, - ORDERED_ACCESS => ENDPOINT_CONFIG(i).ORDERED_ACCESS, - WITH_KEY => ENDPOINT_CONFIG(i).WITH_KEY, - PAYLOAD_FRAME_SIZE => ENDPOINT_CONFIG(i).MAX_PAYLOAD_SIZE, - MAX_REMOTE_ENDPOINTS => MAX_REMOTE_ENDPOINTS - ) - port map ( - -- SYSTEM - clk => clk, - reset => reset, - time => time, - -- FROM RTPS ENDPOINT - start_rtps => start_rr_dr(i), - opcode_rtps => opcode_rr_dr(i), - ack_rtps => ack_dr_rr(i), - done_rtps => done_dr_rr(i), - ret_rtps => ret_dr_rr(i), - valid_in_rtps => valid_rr_dr(i), - ready_in_rtps => ready_dr_rr(i), - data_in_rtps => data_rr_dr(i), - last_word_in_rtps => last_word_rr_dr(i), - -- TO USER ENTITY - start_dds => start_ri_dr(i), - ack_dds => ack_dr_ri(i), - opcode_dds => opcode_ri_dr(i), - instance_state_dds => instance_state_ri_dr(i), - view_state_dds => view_state_ri_dr(i), - sample_state_dds => sample_state_ri_dr(i), - instance_handle_dds => instance_handle_ri_dr(i), - max_samples_dds => max_samples_ri_dr(i), - get_data_dds => get_data_ri_dr(i), - done_dds => done_dr_ri(i), - return_code_dds => return_code_dr_ri(i), - valid_out_dds => valid_dr_ri(i), - ready_out_dds => ready_ri_dr(i), - data_out_dds => data_dr_ri(i), - last_word_out_dds => last_word_dr_ri(i), - sample_info => sample_info_dr_ri(i), - sample_info_valid => sample_info_valid_dr_ri(i), - sample_info_ack => sample_info_ack_ri_dr(i), - eoc => eoc_dr_ri(i), - -- Communication Status - status => status_dr_ri(i) - ); - else generate - dds_writer_inst : entity work.dds_writer(arch) - generic map ( - HISTORY_QOS => ENDPOINT_CONFIG(i).HISTORY_QOS, - DEADLINE_QOS => ENDPOINT_CONFIG(i).DEADLINE_QOS, - LIFESPAN_QOS => ENDPOINT_CONFIG(i).LIFESPAN_QOS, - LEASE_DURATION => ENDPOINT_CONFIG(i).LEASE_DURATION, - WITH_KEY => ENDPOINT_CONFIG(i).WITH_KEY, - MAX_SAMPLES => ENDPOINT_CONFIG(i).MAX_SAMPLES, - MAX_INSTANCES => ENDPOINT_CONFIG(i).MAX_INSTANCES, - MAX_SAMPLES_PER_INSTANCE => ENDPOINT_CONFIG(i).MAX_SAMPLES_PER_INSTANCE, - PAYLOAD_FRAME_SIZE => ENDPOINT_CONFIG(i).MAX_PAYLOAD_SIZE - ) - port map ( - -- SYSTEM - clk => clk, - reset => reset, - time => time, - -- TO/FROM RTPS ENDPOINT - start_rtps => start_rw_dw(i-NUM_READERS), - opcode_rtps => opcode_rw_dw(i-NUM_READERS), - ack_rtps => ack_dw_rw(i-NUM_READERS), - done_rtps => done_rw_dw(i-NUM_READERS), - ret_rtps => ret_dw_rw(i-NUM_READERS), - seq_nr_rtps => seq_nr_rw_dw(i-NUM_READERS), - get_data_rtps => get_data_rw_dw(i-NUM_READERS), - valid_out_rtps => valid_dw_rw(i-NUM_READERS), - ready_out_rtps => ready_rw_dw(i-NUM_READERS), - data_out_rtps => data_dw_rw(i-NUM_READERS), - last_word_out_rtps => last_word_dw_rw(i-NUM_READERS), - liveliness_assertion => liveliness_assertion_dw_rw(i-NUM_READERS), - data_available => data_available_dw_rw(i-NUM_READERS), - -- Cache Change - cc_instance_handle => cc_instance_handle_dw_rw(i-NUM_READERS), - cc_kind => cc_kind_dw_rw(i-NUM_READERS), - cc_source_timestamp => cc_source_timestamp_dw_rw(i-NUM_READERS), - cc_seq_nr => cc_seq_nr_dw_rw(i-NUM_READERS), - -- TO/FROM USER ENTITY - start_dds => start_wi_dw(i-NUM_READERS), - ack_dds => ack_dw_wi(i-NUM_READERS), - opcode_dds => opcode_wi_dw(i-NUM_READERS), - instance_handle_in_dds => instance_handle_wi_dw(i-NUM_READERS), - source_ts_dds => source_ts_wi_dw(i-NUM_READERS), - max_wait_dds => max_wait_wi_dw(i-NUM_READERS), - done_dds => done_dw_wi(i-NUM_READERS), - return_code_dds => return_code_dw_wi(i-NUM_READERS), - instance_handle_out_dds => instance_handle_dw_wi(i-NUM_READERS), - valid_in_dds => valid_wi_dw(i-NUM_READERS), - ready_in_dds => ready_dw_wi(i-NUM_READERS), - data_in_dds => data_wi_dw(i-NUM_READERS), - last_word_in_dds => last_word_wi_dw(i-NUM_READERS), - valid_out_dds => valid_dw_wi(i-NUM_READERS), - ready_out_dds => ready_wi_dw(i-NUM_READERS), - data_out_dds => data_dw_wi(i-NUM_READERS), - last_word_out_dds => last_word_dw_wi(i-NUM_READERS), - -- Communication Status - status => status_dw_wi(i-NUM_READERS) - ); - end generate; + dds_endpoint_w_if : if (NUM_WRITERS > 0) generate + dds_writer_inst : entity work.dds_writer(arch) + generic map ( + NUM_WRITERS => NUM_WRITERS, + CONFIG_ARRAY => to_QUARTUS_CONFIG_ARRAY_TYPE(ENDPOINT_CONFIG(NUM_READERS to NUM_ENDPOINTS-1)) + ) + port map ( + -- SYSTEM + clk => clk, + reset => reset, + time => time, + -- TO/FROM RTPS ENDPOINT + start_rtps => start_rw_dw(0 to NUM_WRITERS-1), + opcode_rtps => opcode_rw_dw(0 to NUM_WRITERS-1), + ack_rtps => ack_dw_rw(0 to NUM_WRITERS-1), + done_rtps => done_rw_dw(0 to NUM_WRITERS-1), + ret_rtps => ret_dw_rw(0 to NUM_WRITERS-1), + seq_nr_rtps => seq_nr_rw_dw(0 to NUM_WRITERS-1), + get_data_rtps => get_data_rw_dw(0 to NUM_WRITERS-1), + valid_out_rtps => valid_dw_rw(0 to NUM_WRITERS-1), + ready_out_rtps => ready_rw_dw(0 to NUM_WRITERS-1), + data_out_rtps => data_dw_rw(0 to NUM_WRITERS-1), + last_word_out_rtps => last_word_dw_rw(0 to NUM_WRITERS-1), + liveliness_assertion => liveliness_assertion_dw_rw(0 to NUM_WRITERS-1), + data_available => data_available_dw_rw(0 to NUM_WRITERS-1), + -- Cache Change + cc_instance_handle => cc_instance_handle_dw_rw(0 to NUM_WRITERS-1), + cc_kind => cc_kind_dw_rw(0 to NUM_WRITERS-1), + cc_source_timestamp => cc_source_timestamp_dw_rw(0 to NUM_WRITERS-1), + cc_seq_nr => cc_seq_nr_dw_rw(0 to NUM_WRITERS-1), + -- TO/FROM USER ENTITY + start_dds => start_wi_dw(0 to NUM_WRITERS-1), + ack_dds => ack_dw_wi(0 to NUM_WRITERS-1), + opcode_dds => opcode_wi_dw(0 to NUM_WRITERS-1), + instance_handle_in_dds => instance_handle_wi_dw(0 to NUM_WRITERS-1), + source_ts_dds => source_ts_wi_dw(0 to NUM_WRITERS-1), + max_wait_dds => max_wait_wi_dw(0 to NUM_WRITERS-1), + done_dds => done_dw_wi(0 to NUM_WRITERS-1), + return_code_dds => return_code_dw_wi(0 to NUM_WRITERS-1), + instance_handle_out_dds => instance_handle_dw_wi(0 to NUM_WRITERS-1), + valid_in_dds => valid_wi_dw(0 to NUM_WRITERS-1), + ready_in_dds => ready_dw_wi(0 to NUM_WRITERS-1), + data_in_dds => data_wi_dw(0 to NUM_WRITERS-1), + last_word_in_dds => last_word_wi_dw(0 to NUM_WRITERS-1), + valid_out_dds => valid_dw_wi(0 to NUM_WRITERS-1), + ready_out_dds => ready_wi_dw(0 to NUM_WRITERS-1), + data_out_dds => data_dw_wi(0 to NUM_WRITERS-1), + last_word_out_dds => last_word_dw_wi(0 to NUM_WRITERS-1), + -- Communication Status + status => status_dw_wi(0 to NUM_WRITERS-1) + ); + end generate; + dds_endpoint_gen : for i in 0 to NUM_READERS-1 generate + dds_reader_inst : entity work.dds_reader(arch) + generic map ( + TIME_BASED_FILTER_QOS => ENDPOINT_CONFIG(i).TIME_BASED_FILTER_QOS, + DEADLINE_QOS => ENDPOINT_CONFIG(i).DEADLINE_QOS, + MAX_INSTANCES => ENDPOINT_CONFIG(i).MAX_INSTANCES, + MAX_SAMPLES_PER_INSTANCE => ENDPOINT_CONFIG(i).MAX_SAMPLES_PER_INSTANCE, + MAX_SAMPLES => ENDPOINT_CONFIG(i).MAX_SAMPLES, + HISTORY_QOS => ENDPOINT_CONFIG(i).HISTORY_QOS, + RELIABILITY_QOS => ENDPOINT_CONFIG(i).RELIABILITY_QOS, + PRESENTATION_QOS => ENDPOINT_CONFIG(i).PRESENTATION_QOS, + DESTINATION_ORDER_QOS => ENDPOINT_CONFIG(i).DESTINATION_ORDER_QOS, + COHERENT_ACCESS => ENDPOINT_CONFIG(i).COHERENT_ACCESS, + ORDERED_ACCESS => ENDPOINT_CONFIG(i).ORDERED_ACCESS, + WITH_KEY => ENDPOINT_CONFIG(i).WITH_KEY, + PAYLOAD_FRAME_SIZE => ENDPOINT_CONFIG(i).MAX_PAYLOAD_SIZE, + MAX_REMOTE_ENDPOINTS => MAX_REMOTE_ENDPOINTS + ) + port map ( + -- SYSTEM + clk => clk, + reset => reset, + time => time, + -- FROM RTPS ENDPOINT + start_rtps => start_rr_dr(i), + opcode_rtps => opcode_rr_dr(i), + ack_rtps => ack_dr_rr(i), + done_rtps => done_dr_rr(i), + ret_rtps => ret_dr_rr(i), + valid_in_rtps => valid_rr_dr(i), + ready_in_rtps => ready_dr_rr(i), + data_in_rtps => data_rr_dr(i), + last_word_in_rtps => last_word_rr_dr(i), + -- TO USER ENTITY + start_dds => start_ri_dr(i), + ack_dds => ack_dr_ri(i), + opcode_dds => opcode_ri_dr(i), + instance_state_dds => instance_state_ri_dr(i), + view_state_dds => view_state_ri_dr(i), + sample_state_dds => sample_state_ri_dr(i), + instance_handle_dds => instance_handle_ri_dr(i), + max_samples_dds => max_samples_ri_dr(i), + get_data_dds => get_data_ri_dr(i), + done_dds => done_dr_ri(i), + return_code_dds => return_code_dr_ri(i), + valid_out_dds => valid_dr_ri(i), + ready_out_dds => ready_ri_dr(i), + data_out_dds => data_dr_ri(i), + last_word_out_dds => last_word_dr_ri(i), + sample_info => sample_info_dr_ri(i), + sample_info_valid => sample_info_valid_dr_ri(i), + sample_info_ack => sample_info_ack_ri_dr(i), + eoc => eoc_dr_ri(i), + -- Communication Status + status => status_dr_ri(i) + ); end generate; diff --git a/src/Tests/Level_2/L2_testbench_Lib4.vhd b/src/Tests/Level_2/L2_testbench_Lib4.vhd index ae9127a..1ef7d7b 100644 --- a/src/Tests/Level_2/L2_testbench_Lib4.vhd +++ b/src/Tests/Level_2/L2_testbench_Lib4.vhd @@ -368,122 +368,114 @@ begin ); end generate; - dds_endpoint_gen : for i in 0 to NUM_ENDPOINTS-1 generate - dds_endpoint_if : if (i < NUM_READERS) generate - dds_reader_inst : entity work.dds_reader(arch) - generic map ( - TIME_BASED_FILTER_QOS => ENDPOINT_CONFIG(i).TIME_BASED_FILTER_QOS, - DEADLINE_QOS => ENDPOINT_CONFIG(i).DEADLINE_QOS, - MAX_INSTANCES => ENDPOINT_CONFIG(i).MAX_INSTANCES, - MAX_SAMPLES_PER_INSTANCE => ENDPOINT_CONFIG(i).MAX_SAMPLES_PER_INSTANCE, - MAX_SAMPLES => ENDPOINT_CONFIG(i).MAX_SAMPLES, - HISTORY_QOS => ENDPOINT_CONFIG(i).HISTORY_QOS, - RELIABILITY_QOS => ENDPOINT_CONFIG(i).RELIABILITY_QOS, - PRESENTATION_QOS => ENDPOINT_CONFIG(i).PRESENTATION_QOS, - DESTINATION_ORDER_QOS => ENDPOINT_CONFIG(i).DESTINATION_ORDER_QOS, - COHERENT_ACCESS => ENDPOINT_CONFIG(i).COHERENT_ACCESS, - ORDERED_ACCESS => ENDPOINT_CONFIG(i).ORDERED_ACCESS, - WITH_KEY => ENDPOINT_CONFIG(i).WITH_KEY, - PAYLOAD_FRAME_SIZE => ENDPOINT_CONFIG(i).MAX_PAYLOAD_SIZE, - MAX_REMOTE_ENDPOINTS => MAX_REMOTE_ENDPOINTS - ) - port map ( - -- SYSTEM - clk => clk, - reset => reset, - time => time, - -- FROM RTPS ENDPOINT - start_rtps => start_rr_dr(i), - opcode_rtps => opcode_rr_dr(i), - ack_rtps => ack_dr_rr(i), - done_rtps => done_dr_rr(i), - ret_rtps => ret_dr_rr(i), - valid_in_rtps => valid_rr_dr(i), - ready_in_rtps => ready_dr_rr(i), - data_in_rtps => data_rr_dr(i), - last_word_in_rtps => last_word_rr_dr(i), - -- TO USER ENTITY - start_dds => start_ri_dr(i), - ack_dds => ack_dr_ri(i), - opcode_dds => opcode_ri_dr(i), - instance_state_dds => instance_state_ri_dr(i), - view_state_dds => view_state_ri_dr(i), - sample_state_dds => sample_state_ri_dr(i), - instance_handle_dds => instance_handle_ri_dr(i), - max_samples_dds => max_samples_ri_dr(i), - get_data_dds => get_data_ri_dr(i), - done_dds => done_dr_ri(i), - return_code_dds => return_code_dr_ri(i), - valid_out_dds => valid_dr_ri(i), - ready_out_dds => ready_ri_dr(i), - data_out_dds => data_dr_ri(i), - last_word_out_dds => last_word_dr_ri(i), - sample_info => sample_info_dr_ri(i), - sample_info_valid => sample_info_valid_dr_ri(i), - sample_info_ack => sample_info_ack_ri_dr(i), - eoc => eoc_dr_ri(i), - -- Communication Status - status => status_dr_ri(i) - ); - else generate - dds_writer_inst : entity work.dds_writer(arch) - generic map ( - HISTORY_QOS => ENDPOINT_CONFIG(i).HISTORY_QOS, - DEADLINE_QOS => ENDPOINT_CONFIG(i).DEADLINE_QOS, - LIFESPAN_QOS => ENDPOINT_CONFIG(i).LIFESPAN_QOS, - LEASE_DURATION => ENDPOINT_CONFIG(i).LEASE_DURATION, - WITH_KEY => ENDPOINT_CONFIG(i).WITH_KEY, - MAX_SAMPLES => ENDPOINT_CONFIG(i).MAX_SAMPLES, - MAX_INSTANCES => ENDPOINT_CONFIG(i).MAX_INSTANCES, - MAX_SAMPLES_PER_INSTANCE => ENDPOINT_CONFIG(i).MAX_SAMPLES_PER_INSTANCE, - PAYLOAD_FRAME_SIZE => ENDPOINT_CONFIG(i).MAX_PAYLOAD_SIZE - ) - port map ( - -- SYSTEM - clk => clk, - reset => reset, - time => time, - -- TO/FROM RTPS ENDPOINT - start_rtps => start_rw_dw(i-NUM_READERS), - opcode_rtps => opcode_rw_dw(i-NUM_READERS), - ack_rtps => ack_dw_rw(i-NUM_READERS), - done_rtps => done_rw_dw(i-NUM_READERS), - ret_rtps => ret_dw_rw(i-NUM_READERS), - seq_nr_rtps => seq_nr_rw_dw(i-NUM_READERS), - get_data_rtps => get_data_rw_dw(i-NUM_READERS), - valid_out_rtps => valid_dw_rw(i-NUM_READERS), - ready_out_rtps => ready_rw_dw(i-NUM_READERS), - data_out_rtps => data_dw_rw(i-NUM_READERS), - last_word_out_rtps => last_word_dw_rw(i-NUM_READERS), - liveliness_assertion => liveliness_assertion_dw_rw(i-NUM_READERS), - data_available => data_available_dw_rw(i-NUM_READERS), - -- Cache Change - cc_instance_handle => cc_instance_handle_dw_rw(i-NUM_READERS), - cc_kind => cc_kind_dw_rw(i-NUM_READERS), - cc_source_timestamp => cc_source_timestamp_dw_rw(i-NUM_READERS), - cc_seq_nr => cc_seq_nr_dw_rw(i-NUM_READERS), - -- TO/FROM USER ENTITY - start_dds => start_wi_dw(i-NUM_READERS), - ack_dds => ack_dw_wi(i-NUM_READERS), - opcode_dds => opcode_wi_dw(i-NUM_READERS), - instance_handle_in_dds => instance_handle_wi_dw(i-NUM_READERS), - source_ts_dds => source_ts_wi_dw(i-NUM_READERS), - max_wait_dds => max_wait_wi_dw(i-NUM_READERS), - done_dds => done_dw_wi(i-NUM_READERS), - return_code_dds => return_code_dw_wi(i-NUM_READERS), - instance_handle_out_dds => instance_handle_dw_wi(i-NUM_READERS), - valid_in_dds => valid_wi_dw(i-NUM_READERS), - ready_in_dds => ready_dw_wi(i-NUM_READERS), - data_in_dds => data_wi_dw(i-NUM_READERS), - last_word_in_dds => last_word_wi_dw(i-NUM_READERS), - valid_out_dds => valid_dw_wi(i-NUM_READERS), - ready_out_dds => ready_wi_dw(i-NUM_READERS), - data_out_dds => data_dw_wi(i-NUM_READERS), - last_word_out_dds => last_word_dw_wi(i-NUM_READERS), - -- Communication Status - status => status_dw_wi(i-NUM_READERS) - ); - end generate; + dds_endpoint_w_if : if (NUM_WRITERS > 0) generate + dds_writer_inst : entity work.dds_writer(arch) + generic map ( + NUM_WRITERS => NUM_WRITERS, + CONFIG_ARRAY => to_QUARTUS_CONFIG_ARRAY_TYPE(ENDPOINT_CONFIG(NUM_READERS to NUM_ENDPOINTS-1)) + ) + port map ( + -- SYSTEM + clk => clk, + reset => reset, + time => time, + -- TO/FROM RTPS ENDPOINT + start_rtps => start_rw_dw(0 to NUM_WRITERS-1), + opcode_rtps => opcode_rw_dw(0 to NUM_WRITERS-1), + ack_rtps => ack_dw_rw(0 to NUM_WRITERS-1), + done_rtps => done_rw_dw(0 to NUM_WRITERS-1), + ret_rtps => ret_dw_rw(0 to NUM_WRITERS-1), + seq_nr_rtps => seq_nr_rw_dw(0 to NUM_WRITERS-1), + get_data_rtps => get_data_rw_dw(0 to NUM_WRITERS-1), + valid_out_rtps => valid_dw_rw(0 to NUM_WRITERS-1), + ready_out_rtps => ready_rw_dw(0 to NUM_WRITERS-1), + data_out_rtps => data_dw_rw(0 to NUM_WRITERS-1), + last_word_out_rtps => last_word_dw_rw(0 to NUM_WRITERS-1), + liveliness_assertion => liveliness_assertion_dw_rw(0 to NUM_WRITERS-1), + data_available => data_available_dw_rw(0 to NUM_WRITERS-1), + -- Cache Change + cc_instance_handle => cc_instance_handle_dw_rw(0 to NUM_WRITERS-1), + cc_kind => cc_kind_dw_rw(0 to NUM_WRITERS-1), + cc_source_timestamp => cc_source_timestamp_dw_rw(0 to NUM_WRITERS-1), + cc_seq_nr => cc_seq_nr_dw_rw(0 to NUM_WRITERS-1), + -- TO/FROM USER ENTITY + start_dds => start_wi_dw(0 to NUM_WRITERS-1), + ack_dds => ack_dw_wi(0 to NUM_WRITERS-1), + opcode_dds => opcode_wi_dw(0 to NUM_WRITERS-1), + instance_handle_in_dds => instance_handle_wi_dw(0 to NUM_WRITERS-1), + source_ts_dds => source_ts_wi_dw(0 to NUM_WRITERS-1), + max_wait_dds => max_wait_wi_dw(0 to NUM_WRITERS-1), + done_dds => done_dw_wi(0 to NUM_WRITERS-1), + return_code_dds => return_code_dw_wi(0 to NUM_WRITERS-1), + instance_handle_out_dds => instance_handle_dw_wi(0 to NUM_WRITERS-1), + valid_in_dds => valid_wi_dw(0 to NUM_WRITERS-1), + ready_in_dds => ready_dw_wi(0 to NUM_WRITERS-1), + data_in_dds => data_wi_dw(0 to NUM_WRITERS-1), + last_word_in_dds => last_word_wi_dw(0 to NUM_WRITERS-1), + valid_out_dds => valid_dw_wi(0 to NUM_WRITERS-1), + ready_out_dds => ready_wi_dw(0 to NUM_WRITERS-1), + data_out_dds => data_dw_wi(0 to NUM_WRITERS-1), + last_word_out_dds => last_word_dw_wi(0 to NUM_WRITERS-1), + -- Communication Status + status => status_dw_wi(0 to NUM_WRITERS-1) + ); + end generate; + dds_endpoint_gen : for i in 0 to NUM_READERS-1 generate + dds_reader_inst : entity work.dds_reader(arch) + generic map ( + TIME_BASED_FILTER_QOS => ENDPOINT_CONFIG(i).TIME_BASED_FILTER_QOS, + DEADLINE_QOS => ENDPOINT_CONFIG(i).DEADLINE_QOS, + MAX_INSTANCES => ENDPOINT_CONFIG(i).MAX_INSTANCES, + MAX_SAMPLES_PER_INSTANCE => ENDPOINT_CONFIG(i).MAX_SAMPLES_PER_INSTANCE, + MAX_SAMPLES => ENDPOINT_CONFIG(i).MAX_SAMPLES, + HISTORY_QOS => ENDPOINT_CONFIG(i).HISTORY_QOS, + RELIABILITY_QOS => ENDPOINT_CONFIG(i).RELIABILITY_QOS, + PRESENTATION_QOS => ENDPOINT_CONFIG(i).PRESENTATION_QOS, + DESTINATION_ORDER_QOS => ENDPOINT_CONFIG(i).DESTINATION_ORDER_QOS, + COHERENT_ACCESS => ENDPOINT_CONFIG(i).COHERENT_ACCESS, + ORDERED_ACCESS => ENDPOINT_CONFIG(i).ORDERED_ACCESS, + WITH_KEY => ENDPOINT_CONFIG(i).WITH_KEY, + PAYLOAD_FRAME_SIZE => ENDPOINT_CONFIG(i).MAX_PAYLOAD_SIZE, + MAX_REMOTE_ENDPOINTS => MAX_REMOTE_ENDPOINTS + ) + port map ( + -- SYSTEM + clk => clk, + reset => reset, + time => time, + -- FROM RTPS ENDPOINT + start_rtps => start_rr_dr(i), + opcode_rtps => opcode_rr_dr(i), + ack_rtps => ack_dr_rr(i), + done_rtps => done_dr_rr(i), + ret_rtps => ret_dr_rr(i), + valid_in_rtps => valid_rr_dr(i), + ready_in_rtps => ready_dr_rr(i), + data_in_rtps => data_rr_dr(i), + last_word_in_rtps => last_word_rr_dr(i), + -- TO USER ENTITY + start_dds => start_ri_dr(i), + ack_dds => ack_dr_ri(i), + opcode_dds => opcode_ri_dr(i), + instance_state_dds => instance_state_ri_dr(i), + view_state_dds => view_state_ri_dr(i), + sample_state_dds => sample_state_ri_dr(i), + instance_handle_dds => instance_handle_ri_dr(i), + max_samples_dds => max_samples_ri_dr(i), + get_data_dds => get_data_ri_dr(i), + done_dds => done_dr_ri(i), + return_code_dds => return_code_dr_ri(i), + valid_out_dds => valid_dr_ri(i), + ready_out_dds => ready_ri_dr(i), + data_out_dds => data_dr_ri(i), + last_word_out_dds => last_word_dr_ri(i), + sample_info => sample_info_dr_ri(i), + sample_info_valid => sample_info_valid_dr_ri(i), + sample_info_ack => sample_info_ack_ri_dr(i), + eoc => eoc_dr_ri(i), + -- Communication Status + status => status_dr_ri(i) + ); end generate; diff --git a/src/Tests/Level_2/L2_testbench_Lib5.vhd b/src/Tests/Level_2/L2_testbench_Lib5.vhd index 6b930b8..0b526f2 100644 --- a/src/Tests/Level_2/L2_testbench_Lib5.vhd +++ b/src/Tests/Level_2/L2_testbench_Lib5.vhd @@ -383,122 +383,114 @@ begin ); end generate; - dds_endpoint_gen : for i in 0 to NUM_ENDPOINTS-1 generate - dds_endpoint_if : if (i < NUM_READERS) generate - dds_reader_inst : entity work.dds_reader(arch) - generic map ( - TIME_BASED_FILTER_QOS => ENDPOINT_CONFIG(i).TIME_BASED_FILTER_QOS, - DEADLINE_QOS => ENDPOINT_CONFIG(i).DEADLINE_QOS, - MAX_INSTANCES => ENDPOINT_CONFIG(i).MAX_INSTANCES, - MAX_SAMPLES_PER_INSTANCE => ENDPOINT_CONFIG(i).MAX_SAMPLES_PER_INSTANCE, - MAX_SAMPLES => ENDPOINT_CONFIG(i).MAX_SAMPLES, - HISTORY_QOS => ENDPOINT_CONFIG(i).HISTORY_QOS, - RELIABILITY_QOS => ENDPOINT_CONFIG(i).RELIABILITY_QOS, - PRESENTATION_QOS => ENDPOINT_CONFIG(i).PRESENTATION_QOS, - DESTINATION_ORDER_QOS => ENDPOINT_CONFIG(i).DESTINATION_ORDER_QOS, - COHERENT_ACCESS => ENDPOINT_CONFIG(i).COHERENT_ACCESS, - ORDERED_ACCESS => ENDPOINT_CONFIG(i).ORDERED_ACCESS, - WITH_KEY => ENDPOINT_CONFIG(i).WITH_KEY, - PAYLOAD_FRAME_SIZE => ENDPOINT_CONFIG(i).MAX_PAYLOAD_SIZE, - MAX_REMOTE_ENDPOINTS => MAX_REMOTE_ENDPOINTS - ) - port map ( - -- SYSTEM - clk => clk, - reset => reset, - time => time, - -- FROM RTPS ENDPOINT - start_rtps => start_rr_dr(i), - opcode_rtps => opcode_rr_dr(i), - ack_rtps => ack_dr_rr(i), - done_rtps => done_dr_rr(i), - ret_rtps => ret_dr_rr(i), - valid_in_rtps => valid_rr_dr(i), - ready_in_rtps => ready_dr_rr(i), - data_in_rtps => data_rr_dr(i), - last_word_in_rtps => last_word_rr_dr(i), - -- TO USER ENTITY - start_dds => start_ri_dr(i), - ack_dds => ack_dr_ri(i), - opcode_dds => opcode_ri_dr(i), - instance_state_dds => instance_state_ri_dr(i), - view_state_dds => view_state_ri_dr(i), - sample_state_dds => sample_state_ri_dr(i), - instance_handle_dds => instance_handle_ri_dr(i), - max_samples_dds => max_samples_ri_dr(i), - get_data_dds => get_data_ri_dr(i), - done_dds => done_dr_ri(i), - return_code_dds => return_code_dr_ri(i), - valid_out_dds => valid_dr_ri(i), - ready_out_dds => ready_ri_dr(i), - data_out_dds => data_dr_ri(i), - last_word_out_dds => last_word_dr_ri(i), - sample_info => sample_info_dr_ri(i), - sample_info_valid => sample_info_valid_dr_ri(i), - sample_info_ack => sample_info_ack_ri_dr(i), - eoc => eoc_dr_ri(i), - -- Communication Status - status => status_dr_ri(i) - ); - else generate - dds_writer_inst : entity work.dds_writer(arch) - generic map ( - HISTORY_QOS => ENDPOINT_CONFIG(i).HISTORY_QOS, - DEADLINE_QOS => ENDPOINT_CONFIG(i).DEADLINE_QOS, - LIFESPAN_QOS => ENDPOINT_CONFIG(i).LIFESPAN_QOS, - LEASE_DURATION => ENDPOINT_CONFIG(i).LEASE_DURATION, - WITH_KEY => ENDPOINT_CONFIG(i).WITH_KEY, - MAX_SAMPLES => ENDPOINT_CONFIG(i).MAX_SAMPLES, - MAX_INSTANCES => ENDPOINT_CONFIG(i).MAX_INSTANCES, - MAX_SAMPLES_PER_INSTANCE => ENDPOINT_CONFIG(i).MAX_SAMPLES_PER_INSTANCE, - PAYLOAD_FRAME_SIZE => ENDPOINT_CONFIG(i).MAX_PAYLOAD_SIZE - ) - port map ( - -- SYSTEM - clk => clk, - reset => reset, - time => time, - -- TO/FROM RTPS ENDPOINT - start_rtps => start_rw_dw(i-NUM_READERS), - opcode_rtps => opcode_rw_dw(i-NUM_READERS), - ack_rtps => ack_dw_rw(i-NUM_READERS), - done_rtps => done_rw_dw(i-NUM_READERS), - ret_rtps => ret_dw_rw(i-NUM_READERS), - seq_nr_rtps => seq_nr_rw_dw(i-NUM_READERS), - get_data_rtps => get_data_rw_dw(i-NUM_READERS), - valid_out_rtps => valid_dw_rw(i-NUM_READERS), - ready_out_rtps => ready_rw_dw(i-NUM_READERS), - data_out_rtps => data_dw_rw(i-NUM_READERS), - last_word_out_rtps => last_word_dw_rw(i-NUM_READERS), - liveliness_assertion => liveliness_assertion_dw_rw(i-NUM_READERS), - data_available => data_available_dw_rw(i-NUM_READERS), - -- Cache Change - cc_instance_handle => cc_instance_handle_dw_rw(i-NUM_READERS), - cc_kind => cc_kind_dw_rw(i-NUM_READERS), - cc_source_timestamp => cc_source_timestamp_dw_rw(i-NUM_READERS), - cc_seq_nr => cc_seq_nr_dw_rw(i-NUM_READERS), - -- TO/FROM USER ENTITY - start_dds => start_wi_dw(i-NUM_READERS), - ack_dds => ack_dw_wi(i-NUM_READERS), - opcode_dds => opcode_wi_dw(i-NUM_READERS), - instance_handle_in_dds => instance_handle_wi_dw(i-NUM_READERS), - source_ts_dds => source_ts_wi_dw(i-NUM_READERS), - max_wait_dds => max_wait_wi_dw(i-NUM_READERS), - done_dds => done_dw_wi(i-NUM_READERS), - return_code_dds => return_code_dw_wi(i-NUM_READERS), - instance_handle_out_dds => instance_handle_dw_wi(i-NUM_READERS), - valid_in_dds => valid_wi_dw(i-NUM_READERS), - ready_in_dds => ready_dw_wi(i-NUM_READERS), - data_in_dds => data_wi_dw(i-NUM_READERS), - last_word_in_dds => last_word_wi_dw(i-NUM_READERS), - valid_out_dds => valid_dw_wi(i-NUM_READERS), - ready_out_dds => ready_wi_dw(i-NUM_READERS), - data_out_dds => data_dw_wi(i-NUM_READERS), - last_word_out_dds => last_word_dw_wi(i-NUM_READERS), - -- Communication Status - status => status_dw_wi(i-NUM_READERS) - ); - end generate; + dds_endpoint_w_if : if (NUM_WRITERS > 0) generate + dds_writer_inst : entity work.dds_writer(arch) + generic map ( + NUM_WRITERS => NUM_WRITERS, + CONFIG_ARRAY => to_QUARTUS_CONFIG_ARRAY_TYPE(ENDPOINT_CONFIG(NUM_READERS to NUM_ENDPOINTS-1)) + ) + port map ( + -- SYSTEM + clk => clk, + reset => reset, + time => time, + -- TO/FROM RTPS ENDPOINT + start_rtps => start_rw_dw(0 to NUM_WRITERS-1), + opcode_rtps => opcode_rw_dw(0 to NUM_WRITERS-1), + ack_rtps => ack_dw_rw(0 to NUM_WRITERS-1), + done_rtps => done_rw_dw(0 to NUM_WRITERS-1), + ret_rtps => ret_dw_rw(0 to NUM_WRITERS-1), + seq_nr_rtps => seq_nr_rw_dw(0 to NUM_WRITERS-1), + get_data_rtps => get_data_rw_dw(0 to NUM_WRITERS-1), + valid_out_rtps => valid_dw_rw(0 to NUM_WRITERS-1), + ready_out_rtps => ready_rw_dw(0 to NUM_WRITERS-1), + data_out_rtps => data_dw_rw(0 to NUM_WRITERS-1), + last_word_out_rtps => last_word_dw_rw(0 to NUM_WRITERS-1), + liveliness_assertion => liveliness_assertion_dw_rw(0 to NUM_WRITERS-1), + data_available => data_available_dw_rw(0 to NUM_WRITERS-1), + -- Cache Change + cc_instance_handle => cc_instance_handle_dw_rw(0 to NUM_WRITERS-1), + cc_kind => cc_kind_dw_rw(0 to NUM_WRITERS-1), + cc_source_timestamp => cc_source_timestamp_dw_rw(0 to NUM_WRITERS-1), + cc_seq_nr => cc_seq_nr_dw_rw(0 to NUM_WRITERS-1), + -- TO/FROM USER ENTITY + start_dds => start_wi_dw(0 to NUM_WRITERS-1), + ack_dds => ack_dw_wi(0 to NUM_WRITERS-1), + opcode_dds => opcode_wi_dw(0 to NUM_WRITERS-1), + instance_handle_in_dds => instance_handle_wi_dw(0 to NUM_WRITERS-1), + source_ts_dds => source_ts_wi_dw(0 to NUM_WRITERS-1), + max_wait_dds => max_wait_wi_dw(0 to NUM_WRITERS-1), + done_dds => done_dw_wi(0 to NUM_WRITERS-1), + return_code_dds => return_code_dw_wi(0 to NUM_WRITERS-1), + instance_handle_out_dds => instance_handle_dw_wi(0 to NUM_WRITERS-1), + valid_in_dds => valid_wi_dw(0 to NUM_WRITERS-1), + ready_in_dds => ready_dw_wi(0 to NUM_WRITERS-1), + data_in_dds => data_wi_dw(0 to NUM_WRITERS-1), + last_word_in_dds => last_word_wi_dw(0 to NUM_WRITERS-1), + valid_out_dds => valid_dw_wi(0 to NUM_WRITERS-1), + ready_out_dds => ready_wi_dw(0 to NUM_WRITERS-1), + data_out_dds => data_dw_wi(0 to NUM_WRITERS-1), + last_word_out_dds => last_word_dw_wi(0 to NUM_WRITERS-1), + -- Communication Status + status => status_dw_wi(0 to NUM_WRITERS-1) + ); + end generate; + dds_endpoint_gen : for i in 0 to NUM_READERS-1 generate + dds_reader_inst : entity work.dds_reader(arch) + generic map ( + TIME_BASED_FILTER_QOS => ENDPOINT_CONFIG(i).TIME_BASED_FILTER_QOS, + DEADLINE_QOS => ENDPOINT_CONFIG(i).DEADLINE_QOS, + MAX_INSTANCES => ENDPOINT_CONFIG(i).MAX_INSTANCES, + MAX_SAMPLES_PER_INSTANCE => ENDPOINT_CONFIG(i).MAX_SAMPLES_PER_INSTANCE, + MAX_SAMPLES => ENDPOINT_CONFIG(i).MAX_SAMPLES, + HISTORY_QOS => ENDPOINT_CONFIG(i).HISTORY_QOS, + RELIABILITY_QOS => ENDPOINT_CONFIG(i).RELIABILITY_QOS, + PRESENTATION_QOS => ENDPOINT_CONFIG(i).PRESENTATION_QOS, + DESTINATION_ORDER_QOS => ENDPOINT_CONFIG(i).DESTINATION_ORDER_QOS, + COHERENT_ACCESS => ENDPOINT_CONFIG(i).COHERENT_ACCESS, + ORDERED_ACCESS => ENDPOINT_CONFIG(i).ORDERED_ACCESS, + WITH_KEY => ENDPOINT_CONFIG(i).WITH_KEY, + PAYLOAD_FRAME_SIZE => ENDPOINT_CONFIG(i).MAX_PAYLOAD_SIZE, + MAX_REMOTE_ENDPOINTS => MAX_REMOTE_ENDPOINTS + ) + port map ( + -- SYSTEM + clk => clk, + reset => reset, + time => time, + -- FROM RTPS ENDPOINT + start_rtps => start_rr_dr(i), + opcode_rtps => opcode_rr_dr(i), + ack_rtps => ack_dr_rr(i), + done_rtps => done_dr_rr(i), + ret_rtps => ret_dr_rr(i), + valid_in_rtps => valid_rr_dr(i), + ready_in_rtps => ready_dr_rr(i), + data_in_rtps => data_rr_dr(i), + last_word_in_rtps => last_word_rr_dr(i), + -- TO USER ENTITY + start_dds => start_ri_dr(i), + ack_dds => ack_dr_ri(i), + opcode_dds => opcode_ri_dr(i), + instance_state_dds => instance_state_ri_dr(i), + view_state_dds => view_state_ri_dr(i), + sample_state_dds => sample_state_ri_dr(i), + instance_handle_dds => instance_handle_ri_dr(i), + max_samples_dds => max_samples_ri_dr(i), + get_data_dds => get_data_ri_dr(i), + done_dds => done_dr_ri(i), + return_code_dds => return_code_dr_ri(i), + valid_out_dds => valid_dr_ri(i), + ready_out_dds => ready_ri_dr(i), + data_out_dds => data_dr_ri(i), + last_word_out_dds => last_word_dr_ri(i), + sample_info => sample_info_dr_ri(i), + sample_info_valid => sample_info_valid_dr_ri(i), + sample_info_ack => sample_info_ack_ri_dr(i), + eoc => eoc_dr_ri(i), + -- Communication Status + status => status_dr_ri(i) + ); end generate; diff --git a/src/Tests/Type1_cfg.vhd b/src/Tests/Type1_cfg.vhd index 710f944..b4a60bd 100644 --- a/src/Tests/Type1_cfg.vhd +++ b/src/Tests/Type1_cfg.vhd @@ -1,6 +1,6 @@ configuration key_holder_conf1 of dds_writer is for arch - for key_holder_inst : key_holder + for all : key_holder use entity work.key_holder(TYPE1); end for; end for; @@ -8,7 +8,7 @@ end configuration; configuration key_holder_conf2 of dds_reader is for arch - for key_holder_inst : key_holder + for all : key_holder use entity work.key_holder(TYPE1); end for; end for; diff --git a/src/Tests/test_cfg.vhd b/src/Tests/test_cfg.vhd index 62d71cb..f2559e2 100644 --- a/src/Tests/test_cfg.vhd +++ b/src/Tests/test_cfg.vhd @@ -1,6 +1,6 @@ configuration key_holder_conf1 of dds_writer is for arch - for key_holder_inst : key_holder + for all : key_holder use entity work.key_holder(test); end for; end for; @@ -8,7 +8,7 @@ end configuration; configuration key_holder_conf2 of dds_reader is for arch - for key_holder_inst : key_holder + for all : key_holder use entity work.key_holder(test); end for; end for; diff --git a/src/Tests/testbench.pro b/src/Tests/testbench.pro index eec44cd..b440b28 100644 --- a/src/Tests/testbench.pro +++ b/src/Tests/testbench.pro @@ -204,15 +204,11 @@ analyze Level_0/L0_rtps_writer_test2.vhd analyze Level_1/L1_rtps_writer_test1.vhd analyze Level_1/L1_rtps_writer_test2.vhd analyze Level_1/L1_rtps_writer_test3.vhd -analyze Level_0/L0_dds_writer_test1_aik.vhd -analyze Level_0/L0_dds_writer_test1_ain.vhd -analyze Level_0/L0_dds_writer_test1_lik.vhd -analyze Level_0/L0_dds_writer_test1_afk.vhd -analyze Level_0/L0_dds_writer_test2_aik.vhd -analyze Level_0/L0_dds_writer_test3_aik.vhd -analyze Level_0/L0_dds_writer_test3_ain.vhd -analyze Level_0/L0_dds_writer_test4_aik.vhd -analyze Level_0/L0_dds_writer_test5_afk.vhd +analyze Level_0/L0_dds_writer_test1.vhd +analyze Level_0/L0_dds_writer_test2.vhd +analyze Level_0/L0_dds_writer_test3.vhd +analyze Level_0/L0_dds_writer_test4.vhd +analyze Level_0/L0_dds_writer_test5.vhd analyze Level_0/L0_dds_reader_test1_arzkriu.vhd analyze Level_0/L0_dds_reader_test1_lrzkriu.vhd analyze Level_0/L0_dds_reader_test1_lbzkriu.vhd @@ -265,15 +261,11 @@ simulate L0_rtps_writer_test2 simulate L1_rtps_writer_test1 simulate L1_rtps_writer_test2 simulate L1_rtps_writer_test3 -simulate L0_dds_writer_test1_aik -simulate L0_dds_writer_test1_ain -simulate L0_dds_writer_test1_lik -simulate L0_dds_writer_test1_afk -simulate L0_dds_writer_test2_aik -simulate L0_dds_writer_test3_aik -simulate L0_dds_writer_test3_ain -simulate L0_dds_writer_test4_aik -simulate L0_dds_writer_test5_afk +simulate L0_dds_writer_test1 +simulate L0_dds_writer_test2 +simulate L0_dds_writer_test3 +simulate L0_dds_writer_test4 +simulate L0_dds_writer_test5 simulate L0_dds_reader_test1_arzkriu simulate L0_dds_reader_test1_lrzkriu simulate L0_dds_reader_test1_lbzkriu diff --git a/src/dds_writer.vhd b/src/dds_writer.vhd index 6969868..8a3d718 100644 --- a/src/dds_writer.vhd +++ b/src/dds_writer.vhd @@ -10,21 +10,19 @@ use work.rtps_package.all; use work.user_config.all; use work.rtps_config_package.all; --- TODO: Check if sample_cnt is always maintained (also with MAX_SAMPLES_PER_INSTANCE = LENGTH_UNLIMITED) - entity dds_writer is generic ( - -- XXX: Quartus Limitation [VHDL error at : generic "" cannot be used in its own interface list (ID: 10556)] - --ID : ID_TYPE := 0; - HISTORY_QOS : std_logic_vector(CDR_ENUMERATION_WIDTH-1 downto 0);-- := ENDPOINT_CONFIG(ID).HISTORY_QOS; - DEADLINE_QOS : DURATION_TYPE;-- := ENDPOINT_CONFIG(ID).DEADLINE_QOS; - LIFESPAN_QOS : DURATION_TYPE;-- := ENDPOINT_CONFIG(ID).LIFESPAN_QOS; - LEASE_DURATION : DURATION_TYPE;-- := ENDPOINT_CONFIG(ID).LEASE_DURATION; - WITH_KEY : boolean;-- := ENDPOINT_CONFIG(ID).WITH_KEY; - MAX_SAMPLES : std_logic_vector(CDR_LONG_WIDTH-1 downto 0);-- := ENDPOINT_CONFIG(ID).MAX_SAMPLES; - MAX_INSTANCES : std_logic_vector(CDR_LONG_WIDTH-1 downto 0);-- := ENDPOINT_CONFIG(ID).MAX_INSTANCES; - MAX_SAMPLES_PER_INSTANCE : std_logic_vector(CDR_LONG_WIDTH-1 downto 0);-- := ENDPOINT_CONFIG(ID).MAX_SAMPLES_PER_INSTANCE; - PAYLOAD_FRAME_SIZE : natural + NUM_WRITERS : natural; + CONFIG_ARRAY : QUARTUS_CONFIG_ARRAY_TYPE + -- HISTORY_QOS + -- DEADLINE_QOS + -- LIFESPAN_QOS + -- LEASE_DURATION + -- WITH_KEY + -- MAX_SAMPLES + -- MAX_INSTANCES + -- MAX_SAMPLES_PER_INSTANCE + -- MAX_PAYLOAD_SIZE ); port ( -- SYSTEM @@ -32,49 +30,51 @@ entity dds_writer is reset : in std_logic; time : in TIME_TYPE; -- TO/FROM RTPS ENDPOINT - start_rtps : in std_logic; - opcode_rtps : in HISTORY_CACHE_OPCODE_TYPE; - ack_rtps : out std_logic; - done_rtps : out std_logic; - ret_rtps : out HISTORY_CACHE_RESPONSE_TYPE; - seq_nr_rtps : in SEQUENCENUMBER_TYPE; - get_data_rtps : in std_logic; - data_out_rtps : out std_logic_vector(WORD_WIDTH-1 downto 0); - valid_out_rtps : out std_logic; - ready_out_rtps : in std_logic; - last_word_out_rtps : out std_logic; - liveliness_assertion : out std_logic; - data_available : out std_logic; + start_rtps : in std_logic_vector(0 to NUM_WRITERS-1); + opcode_rtps : in HISTORY_CACHE_OPCODE_ARRAY_TYPE(0 to NUM_WRITERS-1); + ack_rtps : out std_logic_vector(0 to NUM_WRITERS-1); + done_rtps : out std_logic_vector(0 to NUM_WRITERS-1); + ret_rtps : out HISTORY_CACHE_RESPONSE_ARRAY_TYPE(0 to NUM_WRITERS-1); + seq_nr_rtps : in SEQUENCENUMBER_ARRAY_TYPE(0 to NUM_WRITERS-1); + get_data_rtps : in std_logic_vector(0 to NUM_WRITERS-1); + data_out_rtps : out WORD_ARRAY_TYPE(0 to NUM_WRITERS-1); + valid_out_rtps : out std_logic_vector(0 to NUM_WRITERS-1); + ready_out_rtps : in std_logic_vector(0 to NUM_WRITERS-1); + last_word_out_rtps : out std_logic_vector(0 to NUM_WRITERS-1); + liveliness_assertion : out std_logic_vector(0 to NUM_WRITERS-1); + data_available : out std_logic_vector(0 to NUM_WRITERS-1); -- Cache Change - cc_instance_handle : out INSTANCE_HANDLE_TYPE; - cc_kind : out CACHE_CHANGE_KIND_TYPE; - cc_source_timestamp : out TIME_TYPE; - cc_seq_nr : out SEQUENCENUMBER_TYPE; + cc_instance_handle : out INSTANCE_HANDLE_ARRAY_TYPE(0 to NUM_WRITERS-1); + cc_kind : out CACHE_CHANGE_KIND_ARRAY_TYPE(0 to NUM_WRITERS-1); + cc_source_timestamp : out TIME_ARRAY_TYPE(0 to NUM_WRITERS-1); + cc_seq_nr : out SEQUENCENUMBER_ARRAY_TYPE(0 to NUM_WRITERS-1); -- TO/FROM USER ENTITY - start_dds : in std_logic; - ack_dds : out std_logic; - opcode_dds : in DDS_WRITER_OPCODE_TYPE; - instance_handle_in_dds : in INSTANCE_HANDLE_TYPE; - source_ts_dds : in TIME_TYPE; - max_wait_dds : in DURATION_TYPE; - done_dds : out std_logic; - return_code_dds : out std_logic_vector(RETURN_CODE_WIDTH-1 downto 0); - instance_handle_out_dds : out INSTANCE_HANDLE_TYPE; - valid_in_dds : in std_logic; - ready_in_dds : out std_logic; - data_in_dds : in std_logic_vector(WORD_WIDTH-1 downto 0); - last_word_in_dds : in std_logic; - valid_out_dds : out std_logic; - ready_out_dds : in std_logic; - data_out_dds : out std_logic_vector(WORD_WIDTH-1 downto 0); - last_word_out_dds : out std_logic; + start_dds : in std_logic_vector(0 to NUM_WRITERS-1); + ack_dds : out std_logic_vector(0 to NUM_WRITERS-1); + opcode_dds : in DDS_WRITER_OPCODE_ARRAY_TYPE(0 to NUM_WRITERS-1); + instance_handle_in_dds : in INSTANCE_HANDLE_ARRAY_TYPE(0 to NUM_WRITERS-1); + source_ts_dds : in TIME_ARRAY_TYPE(0 to NUM_WRITERS-1); + max_wait_dds : in DURATION_ARRAY_TYPE(0 to NUM_WRITERS-1); + done_dds : out std_logic_vector(0 to NUM_WRITERS-1); + return_code_dds : out RETURN_CODE_ARRAY_TYPE(0 to NUM_WRITERS-1); + instance_handle_out_dds : out INSTANCE_HANDLE_ARRAY_TYPE(0 to NUM_WRITERS-1); + valid_in_dds : in std_logic_vector(0 to NUM_WRITERS-1); + ready_in_dds : out std_logic_vector(0 to NUM_WRITERS-1); + data_in_dds : in WORD_ARRAY_TYPE(0 to NUM_WRITERS-1); + last_word_in_dds : in std_logic_vector(0 to NUM_WRITERS-1); + valid_out_dds : out std_logic_vector(0 to NUM_WRITERS-1); + ready_out_dds : in std_logic_vector(0 to NUM_WRITERS-1); + data_out_dds : out WORD_ARRAY_TYPE(0 to NUM_WRITERS-1); + last_word_out_dds : out std_logic_vector(0 to NUM_WRITERS-1); -- Communication Status - status : out std_logic_vector(STATUS_KIND_WIDTH-1 downto 0) + status : out STATUS_KIND_ARRAY_TYPE(0 to NUM_WRITERS-1) ); end entity; architecture arch of dds_writer is + constant CONFIG_ARRAY_T : QUARTUS_CONFIG_ARRAY_TYPE(0 to NUM_WRITERS-1) := CONFIG_ARRAY; + --*****COMPONENT DECLARATION***** component key_holder is port ( @@ -100,43 +100,133 @@ architecture arch of dds_writer is ); end component; + type NATURAL_ARRAY_TYPE is array (0 to NUM_WRITERS-1) of natural; + function get_max_samples(qos : QUARTUS_CONFIG_ARRAY_TYPE) return natural is + variable ret : natural := 0; + begin + assert (qos'length = NUM_WRITERS) severity FAILURE; + for i in 0 to NUM_WRITERS-1 loop + if (unsigned(qos(i).MAX_SAMPLES) > ret) then + ret := to_integer(unsigned(qos(i).MAX_SAMPLES)); + end if; + end loop; + return ret; + end function; + type MAX_SAMPLES_NATURAL_ARRAY_TYPE is array (0 to NUM_WRITERS-1) of natural range 0 to get_max_samples(CONFIG_ARRAY_T)+1; + function get_max_instances(qos : QUARTUS_CONFIG_ARRAY_TYPE) return natural is + variable ret : natural := 0; + begin + assert (qos'length = NUM_WRITERS) severity FAILURE; + for i in 0 to NUM_WRITERS-1 loop + if (unsigned(qos(i).MAX_INSTANCES) > ret) then + ret := to_integer(unsigned(qos(i).MAX_INSTANCES)); + end if; + end loop; + return ret; + end function; + type MAX_INSTANCES_NATURAL_ARRAY_TYPE is array (0 to NUM_WRITERS-1) of natural range 0 to get_max_instances(CONFIG_ARRAY_T); + + --*****CONSTANT DECLARATION***** + -- NOTE: Because we need to first determine the Instance before making the ACCEPT/REJECT/DROP decision + -- we need to latch the cache change first, calculate the Key Hash if necessary, fetch the associated + -- Instance, and then decide on it. This in effect means that we always need an extra slot in sample and + -- payload memory that is only used as a latch. -- *SAMPLE MEMORY* -- 4-Byte Word Size of a Sample Info Entry in Memory - function gen_frame_size(lifespan : DURATION_TYPE; WITH_KEY : boolean) return natural is - variable ret : natural := 0; - begin - if (lifespan /= DURATION_INFINITE and WITH_KEY) then - return 11; - elsif (lifespan /= DURATION_INFINITE and (not WITH_KEY)) then - return 10; - elsif (lifespan = DURATION_INFINITE and WITH_KEY) then - return 9; - else --lifespan = DURATION_INFINITE and (not WITH_KEY) - return 8; - end if; - end function; - constant SAMPLE_FRAME_SIZE : natural := gen_frame_size(LIFESPAN_QOS,WITH_KEY); + constant SAMPLE_FRAME_SIZE : natural := 11; -- Sample Info Memory Size in 4-Byte Words - constant SAMPLE_MEMORY_SIZE : natural := to_integer(unsigned(MAX_SAMPLES)+1) * SAMPLE_FRAME_SIZE; + function gen_sample_memory_size(qos : QUARTUS_CONFIG_ARRAY_TYPE; size : natural) return NATURAL_ARRAY_TYPE is + variable ret : NATURAL_ARRAY_TYPE; + begin + assert (qos'length = NUM_WRITERS) severity FAILURE; + + for i in 0 to NUM_WRITERS-1 loop + ret(i) := to_integer(unsigned(qos(i).MAX_SAMPLES)+1) * size; + end loop; + + return ret; + end function; + constant SAMPLE_MEMORY_SIZE : NATURAL_ARRAY_TYPE := gen_sample_memory_size(CONFIG_ARRAY_T,SAMPLE_FRAME_SIZE); -- Sample Info Memory Address Width - constant SAMPLE_MEMORY_ADDR_WIDTH : natural := log2c(SAMPLE_MEMORY_SIZE); + function get_max_sample_memory_size(sizes : NATURAL_ARRAY_TYPE) return natural is + variable ret : natural := 0; + begin + for i in 0 to NUM_WRITERS-1 loop + if (sizes(i) > ret) then + ret := sizes(i); + end if; + end loop; + return ret; + end function; + constant SAMPLE_MEMORY_ADDR_WIDTH : natural := log2c(get_max_sample_memory_size(SAMPLE_MEMORY_SIZE)); + type SAMPLE_MEMORY_ADDR_ARRAY_TYPE is array (0 to NUM_WRITERS-1) of unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0); -- Highest Sample Info Memory Address - constant SAMPLE_MEMORY_MAX_ADDRESS : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) := to_unsigned(SAMPLE_MEMORY_SIZE-1, SAMPLE_MEMORY_ADDR_WIDTH); + constant SAMPLE_MEMORY_MAX_ADDRESS : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) := to_unsigned(get_max_sample_memory_size(SAMPLE_MEMORY_SIZE)-1, SAMPLE_MEMORY_ADDR_WIDTH); -- Highest Sample Info Frame Address - constant MAX_SAMPLE_ADDRESS : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) := SAMPLE_MEMORY_MAX_ADDRESS - SAMPLE_FRAME_SIZE + 1; + function gen_max_sample_address(sizes : NATURAL_ARRAY_TYPE; size : natural) return SAMPLE_MEMORY_ADDR_ARRAY_TYPE is + variable ret : SAMPLE_MEMORY_ADDR_ARRAY_TYPE; + begin + for i in 0 to NUM_WRITERS-1 loop + ret(i) := to_unsigned(sizes(i) - size, SAMPLE_MEMORY_ADDR_WIDTH); + end loop; + return ret; + end function; + constant MAX_SAMPLE_ADDRESS : SAMPLE_MEMORY_ADDR_ARRAY_TYPE := gen_max_sample_address(SAMPLE_MEMORY_SIZE, SAMPLE_FRAME_SIZE); -- Address pointing to the beginning of the first Sample Data Frame constant FIRST_SAMPLE_ADDRESS : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); -- *PAYLOAD MEMORY* + function gen_payload_frame_size(qos : QUARTUS_CONFIG_ARRAY_TYPE) return NATURAL_ARRAY_TYPE is + variable ret : NATURAL_ARRAY_TYPE; + begin + assert (qos'length = NUM_WRITERS) severity FAILURE; + + for i in 0 to NUM_WRITERS-1 loop + ret(i) := round_div(qos(i).MAX_PAYLOAD_SIZE + 4, WORD_WIDTH/BYTE_WIDTH); -- (+ NEXT ADDR Field) + end loop; + + return ret; + end function; + constant PAYLOAD_FRAME_SIZE : NATURAL_ARRAY_TYPE := gen_payload_frame_size(CONFIG_ARRAY_T); -- Payload Memory Size in 4-Byte Words - constant PAYLOAD_MEMORY_SIZE : natural := to_integer(unsigned(MAX_SAMPLES)+1) * PAYLOAD_FRAME_SIZE; + function gen_payload_memory_size(qos : QUARTUS_CONFIG_ARRAY_TYPE; size : NATURAL_ARRAY_TYPE) return NATURAL_ARRAY_TYPE is + variable ret : NATURAL_ARRAY_TYPE; + begin + assert (qos'length = NUM_WRITERS) severity FAILURE; + + for i in 0 to NUM_WRITERS-1 loop + ret(i) := to_integer(unsigned(qos(i).MAX_SAMPLES)+1) * size(i); + end loop; + + return ret; + end function; + constant PAYLOAD_MEMORY_SIZE : NATURAL_ARRAY_TYPE := gen_payload_memory_size(CONFIG_ARRAY_T, PAYLOAD_FRAME_SIZE); -- Payload Memory Address Width - constant PAYLOAD_MEMORY_ADDR_WIDTH : natural := log2c(PAYLOAD_MEMORY_SIZE); + function get_max_payload_memory_size(sizes : NATURAL_ARRAY_TYPE) return natural is + variable ret : natural := 0; + begin + for i in 0 to NUM_WRITERS-1 loop + if (sizes(i) > ret) then + ret := sizes(i); + end if; + end loop; + return ret; + end function; + constant PAYLOAD_MEMORY_ADDR_WIDTH : natural := log2c(get_max_payload_memory_size(PAYLOAD_MEMORY_SIZE)); + type PAYLOAD_MEMORY_ADDR_ARRAY_TYPE is array (0 to NUM_WRITERS-1) of unsigned(PAYLOAD_MEMORY_ADDR_WIDTH-1 downto 0); -- Highest Payload Memory Address - constant PAYLOAD_MEMORY_MAX_ADDRESS : unsigned(PAYLOAD_MEMORY_ADDR_WIDTH-1 downto 0) := to_unsigned(PAYLOAD_MEMORY_SIZE-1, PAYLOAD_MEMORY_ADDR_WIDTH); + constant PAYLOAD_MEMORY_MAX_ADDRESS : unsigned(PAYLOAD_MEMORY_ADDR_WIDTH-1 downto 0) := to_unsigned(get_max_payload_memory_size(PAYLOAD_MEMORY_SIZE)-1, PAYLOAD_MEMORY_ADDR_WIDTH); -- Highest Payload Frame Address - constant MAX_PAYLOAD_ADDRESS : unsigned(PAYLOAD_MEMORY_ADDR_WIDTH-1 downto 0) := PAYLOAD_MEMORY_MAX_ADDRESS - PAYLOAD_FRAME_SIZE + 1; + function gen_max_payload_address(sizes : NATURAL_ARRAY_TYPE; size : NATURAL_ARRAY_TYPE) return PAYLOAD_MEMORY_ADDR_ARRAY_TYPE is + variable ret : PAYLOAD_MEMORY_ADDR_ARRAY_TYPE; + begin + for i in 0 to NUM_WRITERS-1 loop + ret(i) := to_unsigned(sizes(i) - size(i), PAYLOAD_MEMORY_ADDR_WIDTH); + end loop; + return ret; + end function; + constant MAX_PAYLOAD_ADDRESS : PAYLOAD_MEMORY_ADDR_ARRAY_TYPE := gen_max_payload_address(PAYLOAD_MEMORY_SIZE, PAYLOAD_FRAME_SIZE); -- Address pointing to the beginning of the first Payload Data Frame constant FIRST_PAYLOAD_ADDRESS : unsigned(PAYLOAD_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); @@ -144,13 +234,47 @@ architecture arch of dds_writer is -- 4-Byte Word Size of a Instance Entry in Memory constant INSTANCE_FRAME_SIZE : natural := 9; -- Instance Memory Size in 4-Byte Words - constant INSTANCE_MEMORY_SIZE : natural := to_integer(unsigned(MAX_INSTANCES)) * INSTANCE_FRAME_SIZE; + function gen_instance_memory_size(qos : QUARTUS_CONFIG_ARRAY_TYPE; size : natural) return NATURAL_ARRAY_TYPE is + variable ret : NATURAL_ARRAY_TYPE; + begin + assert (qos'length = NUM_WRITERS) severity FAILURE; + + for i in 0 to NUM_WRITERS-1 loop + if (qos(i).WITH_KEY) then + ret(i) := to_integer(unsigned(qos(i).MAX_INSTANCES)) * size; + else + ret(i) := size; + end if; + end loop; + + return ret; + end function; + constant INSTANCE_MEMORY_SIZE : NATURAL_ARRAY_TYPE := gen_instance_memory_size(CONFIG_ARRAY_T, INSTANCE_FRAME_SIZE); -- Instance Memory Address Width - constant INSTANCE_MEMORY_ADDR_WIDTH : natural := log2c(INSTANCE_MEMORY_SIZE); + function get_max_instance_memory_size(sizes : NATURAL_ARRAY_TYPE) return natural is + variable ret : natural := 0; + begin + for i in 0 to NUM_WRITERS-1 loop + if (sizes(i) > ret) then + ret := sizes(i); + end if; + end loop; + return ret; + end function; + constant INSTANCE_MEMORY_ADDR_WIDTH : natural := log2c(get_max_instance_memory_size(INSTANCE_MEMORY_SIZE)); + type INSTANCE_MEMORY_ADDR_ARRAY_TYPE is array (0 to NUM_WRITERS-1) of unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0); -- Highest Instance Memory Address - constant INSTANCE_MEMORY_MAX_ADDRESS: unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0) := to_unsigned(INSTANCE_MEMORY_SIZE-1, INSTANCE_MEMORY_ADDR_WIDTH); + constant INSTANCE_MEMORY_MAX_ADDRESS: unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0) := to_unsigned(get_max_instance_memory_size(INSTANCE_MEMORY_SIZE)-1, INSTANCE_MEMORY_ADDR_WIDTH); -- Highest Instance Frame Address - constant MAX_INSTANCE_ADDRESS : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0) := INSTANCE_MEMORY_MAX_ADDRESS - INSTANCE_FRAME_SIZE + 1; + function gen_max_instance_address(sizes : NATURAL_ARRAY_TYPE; size : natural) return INSTANCE_MEMORY_ADDR_ARRAY_TYPE is + variable ret : INSTANCE_MEMORY_ADDR_ARRAY_TYPE; + begin + for i in 0 to NUM_WRITERS-1 loop + ret(i) := to_unsigned(sizes(i) - size, INSTANCE_MEMORY_ADDR_WIDTH); + end loop; + return ret; + end function; + constant MAX_INSTANCE_ADDRESS : INSTANCE_MEMORY_ADDR_ARRAY_TYPE := gen_max_instance_address(INSTANCE_MEMORY_SIZE, INSTANCE_FRAME_SIZE); -- Address pointing to the beginning of the first Instance Data Frame constant FIRST_INSTANCE_ADDRESS : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); @@ -160,30 +284,10 @@ architecture arch of dds_writer is constant SMF_SEQ_NR_OFFSET : natural := 1; constant SMF_TIMESTAMP_OFFSET : natural := 3; constant SMF_LIFESPAN_DEADLINE_OFFSET : natural := 5; - function gen_smf_payload_addr_offset(lifespan : DURATION_TYPE) return natural is - variable ret : natural := 0; - begin - if (lifespan /= DURATION_INFINITE) then - ret := SMF_LIFESPAN_DEADLINE_OFFSET + 2; - else - ret := SMF_LIFESPAN_DEADLINE_OFFSET; - end if; - return ret; - end function; - constant SMF_PAYLOAD_ADDR_OFFSET : natural := gen_smf_payload_addr_offset(LIFESPAN_QOS); - constant SMF_INSTANCE_ADDR_OFFSET : natural := SMF_PAYLOAD_ADDR_OFFSET + 1; - function gen_smf_prev_addr_offset(WITH_KEY : boolean) return natural is - variable ret : natural := 0; - begin - if (WITH_KEY) then - ret := SMF_INSTANCE_ADDR_OFFSET + 1; - else - ret := SMF_INSTANCE_ADDR_OFFSET; - end if; - return ret; - end function; - constant SMF_PREV_ADDR_OFFSET : natural := gen_smf_prev_addr_offset(WITH_KEY); - constant SMF_NEXT_ADDR_OFFSET : natural := SMF_PREV_ADDR_OFFSET + 1; + constant SMF_PAYLOAD_ADDR_OFFSET : natural := 7; + constant SMF_INSTANCE_ADDR_OFFSET : natural := 8; + constant SMF_PREV_ADDR_OFFSET : natural := 9; + constant SMF_NEXT_ADDR_OFFSET : natural := 10; -- *PAYLOAD MEMORY FRAME FIELD OFFSETS* -- 4-Byte Word Offsets to Beginning of Respective Fields in the Endpoint Memory Frame @@ -210,10 +314,10 @@ architecture arch of dds_writer is --*****TYPE DECLARATION***** -- FSM states. Explained below in detail type STAGE_TYPE is (IDLE, UNKNOWN_OPERATION_DDS, UNKNOWN_OPERATION_RTPS, UNKNOWN_SEQ_NR, ASSERT_LIVELINESS, ADD_SAMPLE_INFO, ADD_PAYLOAD, NEXT_PAYLOAD_SLOT, - ALIGN_PAYLOAD, GET_KEY_HASH, INITIATE_INSTANCE_SEARCH, REGISTER_OPERATION, LOOKUP_OPERATION, PUSH_KEY_HASH, FILTER_STAGE, UPDATE_INSTANCE, + ALIGN_PAYLOAD, GET_KEY_HASH, INITIATE_INSTANCE_SEARCH, REGISTER_OPERATION, LOOKUP_OPERATION, PUSH_KEY_HASH, FILTER_STAGE, UPDATE_INSTANCE, CHECK_ACK_WAIT, FINALIZE_PAYLOAD, FINALIZE_SAMPLE, GET_OLDEST_SAMPLE_INSTANCE, FIND_SAMPLE, REMOVE_ORPHAN_SAMPLES, REMOVE_SAMPLE, POST_SAMPLE_REMOVE, SKIP_AND_RETURN, SKIP, REMOVE_STALE_INSTANCE, GET_SEQ_NR, FIND_SEQ_NR, ACKNACK_SAMPLE, GET_SAMPLE, GET_PAYLOAD, - CHECK_LIFESPAN, GET_LIVELINESS_LOST_STATUS, GET_OFFERED_DEADLINE_MISSED_STATUS, CHECK_DEADLINE, RESET_SAMPLE_MEMORY, RESET_PAYLOAD_MEMORY); + CHECK_LIFESPAN, GET_LIVELINESS_LOST_STATUS, GET_OFFERED_DEADLINE_MISSED_STATUS, CHECK_DEADLINE, CHECK_LIVELINESS, RESET_SAMPLE_MEMORY, RESET_PAYLOAD_MEMORY); -- Instance Memory FSM states. Explained below in detail type INST_STAGE_TYPE is (IDLE, SEARCH_INSTANCE, GET_NEXT_INSTANCE, GET_INSTANCE_DATA, INSERT_INSTANCE, UPDATE_INSTANCE, REMOVE_INSTANCE, RESET_MEMORY); @@ -233,6 +337,7 @@ architecture arch of dds_writer is type INSTANCE_OPCODE_TYPE is (NOP, SEARCH_INSTANCE, INSERT_INSTANCE, UPDATE_INSTANCE, GET_INSTANCE, GET_NEXT_INSTANCE, REMOVE_INSTANCE); -- Record of Instance Data type INSTANCE_DATA_TYPE is record + i : natural range 0 to NUM_WRITERS-1; addr : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0); key_hash : KEY_HASH_TYPE; status_info : std_logic_vector(CDR_LONG_WIDTH-1 downto 0); @@ -242,6 +347,7 @@ architecture arch of dds_writer is end record; -- Zero initialized Endpoint Data constant ZERO_INSTANCE_DATA : INSTANCE_DATA_TYPE := ( + i => 0, addr => INSTANCE_MEMORY_MAX_ADDRESS, key_hash => KEY_HASH_NIL, status_info => (others => '0'), @@ -252,12 +358,18 @@ architecture arch of dds_writer is --*****SIGNAL DECLARATION***** -- *SAMPLE MEMORY CONNECTION SIGNALS* - signal sample_addr : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0); - signal sample_read : std_logic; - signal sample_read_data, sample_write_data : std_logic_vector(WORD_WIDTH-1 downto 0); - signal sample_ready_in, sample_valid_in : std_logic; - signal sample_ready_out, sample_valid_out : std_logic; - signal sample_abort_read : std_logic; + signal sample_addr : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); + signal sample_read : std_logic := '0'; + signal sample_read_data, sample_write_data : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); + signal sample_ready_in, sample_valid_in : std_logic := '0'; + signal sample_ready_out, sample_valid_out : std_logic := '0'; + signal sample_abort_read : std_logic := '0'; + signal sample_addr_i : SAMPLE_MEMORY_ADDR_ARRAY_TYPE; + signal sample_read_i : std_logic_vector(0 to NUM_WRITERS-1); + signal sample_read_data_i, sample_write_data_i : WORD_ARRAY_TYPE(0 to NUM_WRITERS-1); + signal sample_ready_in_i, sample_valid_in_i : std_logic_vector(0 to NUM_WRITERS-1); + signal sample_ready_out_i, sample_valid_out_i : std_logic_vector(0 to NUM_WRITERS-1); + signal sample_abort_read_i : std_logic_vector(0 to NUM_WRITERS-1); -- *PAYLOAD MEMORY CONNECTION SIGNALS* signal payload_addr : unsigned(PAYLOAD_MEMORY_ADDR_WIDTH-1 downto 0); @@ -266,6 +378,12 @@ architecture arch of dds_writer is signal payload_ready_in, payload_valid_in : std_logic; signal payload_ready_out, payload_valid_out : std_logic; signal payload_abort_read : std_logic; + signal payload_addr_i : PAYLOAD_MEMORY_ADDR_ARRAY_TYPE; + signal payload_read_i : std_logic_vector(0 to NUM_WRITERS-1); + signal payload_read_data_i, payload_write_data_i : WORD_ARRAY_TYPE(0 to NUM_WRITERS-1); + signal payload_ready_in_i, payload_valid_in_i : std_logic_vector(0 to NUM_WRITERS-1); + signal payload_ready_out_i, payload_valid_out_i : std_logic_vector(0 to NUM_WRITERS-1); + signal payload_abort_read_i : std_logic_vector(0 to NUM_WRITERS-1); -- *INSTANCE MEMORY CONNECTION SIGNALS* signal inst_addr : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0); @@ -274,11 +392,17 @@ architecture arch of dds_writer is signal inst_ready_in, inst_valid_in : std_logic; signal inst_ready_out, inst_valid_out : std_logic; signal inst_abort_read : std_logic; + signal inst_addr_i : INSTANCE_MEMORY_ADDR_ARRAY_TYPE; + signal inst_read_i : std_logic_vector(0 to NUM_WRITERS-1); + signal inst_read_data_i, inst_write_data_i : WORD_ARRAY_TYPE(0 to NUM_WRITERS-1); + signal inst_ready_in_i, inst_valid_in_i : std_logic_vector(0 to NUM_WRITERS-1); + signal inst_ready_out_i, inst_valid_out_i : std_logic_vector(0 to NUM_WRITERS-1); + signal inst_abort_read_i : std_logic_vector(0 to NUM_WRITERS-1); -- *KEY HOLDER CONNECTION SIGNALS* - signal start_kh, ack_kh, valid_in_kh, ready_in_kh, last_word_in_kh, valid_out_kh, ready_out_kh, last_word_out_kh, abort_kh : std_logic; - signal opcode_kh : KEY_HOLDER_OPCODE_TYPE; - signal data_in_kh, data_out_kh : std_logic_vector(WORD_WIDTH-1 downto 0); + signal start_kh, ack_kh, valid_in_kh, ready_in_kh, last_word_in_kh, valid_out_kh, ready_out_kh, last_word_out_kh, abort_kh : std_logic_vector(0 to NUM_WRITERS-1); + signal opcode_kh : KEY_HOLDER_OPCODE_ARRAY_TYPE(0 to NUM_WRITERS-1); + signal data_in_kh, data_out_kh : WORD_ARRAY_TYPE(0 to NUM_WRITERS-1); -- *MAIN PROCESS* -- FSM state @@ -288,19 +412,19 @@ architecture arch of dds_writer is -- General Purpose Counter signal cnt, cnt_next : natural range 0 to 14; -- Counter used to read/write Payload Fames - signal cnt2, cnt2_next : natural range 0 to max(PAYLOAD_FRAME_SIZE, INSTANCE_HANDLE_TYPE'length-1); + signal cnt2, cnt2_next : natural range 0 to max(get_max_payload_memory_size(PAYLOAD_FRAME_SIZE), INSTANCE_HANDLE_TYPE'length-1); -- Counter used to read/write Payload Fames - signal cnt3, cnt3_next : natural range 0 to PAYLOAD_FRAME_SIZE; + signal cnt3, cnt3_next : natural range 0 to get_max_payload_memory_size(PAYLOAD_FRAME_SIZE); -- Head of Empty Sample List - signal empty_sample_list_head, empty_sample_list_head_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0); + signal empty_sample_list_head, empty_sample_list_head_next : SAMPLE_MEMORY_ADDR_ARRAY_TYPE; -- Tail of Empty Sample List - signal empty_sample_list_tail, empty_sample_list_tail_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0); + signal empty_sample_list_tail, empty_sample_list_tail_next : SAMPLE_MEMORY_ADDR_ARRAY_TYPE; -- Head of Empty Payload List - signal empty_payload_list_head, empty_payload_list_head_next : unsigned(PAYLOAD_MEMORY_ADDR_WIDTH-1 downto 0); + signal empty_payload_list_head, empty_payload_list_head_next : PAYLOAD_MEMORY_ADDR_ARRAY_TYPE; -- Oldest Sample (Head of Occupied Sample List) - signal oldest_sample, oldest_sample_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0); + signal oldest_sample, oldest_sample_next : SAMPLE_MEMORY_ADDR_ARRAY_TYPE; -- Newest Sample (Tail of Occupied Sample List) - signal newest_sample, newest_sample_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0); + signal newest_sample, newest_sample_next : SAMPLE_MEMORY_ADDR_ARRAY_TYPE; -- Denotes if the oldest Sample should be removed signal remove_oldest_sample, remove_oldest_sample_next : std_logic; -- Denotes if the oldest sample of the Instance with 'key_hash' should be removed @@ -353,40 +477,50 @@ architecture arch of dds_writer is signal is_lifespan_check, is_lifespan_check_next : std_logic; -- Signal used to generate the monotonically rising Sequence Numbers -- It contains the next applicable Sequence Number - signal global_seq_nr, global_seq_nr_next : SEQUENCENUMBER_TYPE; + signal global_seq_nr, global_seq_nr_next : SEQUENCENUMBER_ARRAY_TYPE(0 to NUM_WRITERS-1); -- Signal containing the current number of stored samples - signal global_sample_cnt, global_sample_cnt_next : natural range 0 to to_integer(unsigned(MAX_SAMPLES)+1); + signal global_sample_cnt, global_sample_cnt_next : MAX_SAMPLES_NATURAL_ARRAY_TYPE; -- Signal containing the current number of ACKed stored samples - signal global_ack_cnt, global_ack_cnt_next : natural range 0 to to_integer(unsigned(MAX_SAMPLES)+1); + signal global_ack_cnt, global_ack_cnt_next : MAX_SAMPLES_NATURAL_ARRAY_TYPE; -- Signal containing the number of currently stale Instances - signal stale_inst_cnt, stale_inst_cnt_next : natural range 0 to to_integer(unsigned(MAX_INSTANCES)); + signal stale_inst_cnt, stale_inst_cnt_next : MAX_INSTANCES_NATURAL_ARRAY_TYPE; -- Signifies if a Instance Register Operation is in progress signal register_op, register_op_next : std_logic; -- Signifies if a Instance Lookup Operation is in progress signal lookup_op, lookup_op_next : std_logic; -- Signifies if a WAIT_FOR_ACKNOWLEDGEMENT Operation is in progress - signal ack_wait, ack_wait_next : std_logic; - -- Timout time for DDS Operation - signal timeout_time, timeout_time_next : TIME_TYPE; + signal ack_wait, ack_wait_next : std_logic_vector(0 to NUM_WRITERS-1); + -- Triggers an ACK Wait Check + signal ack_wait_check, ack_wait_check_next : std_logic; + -- Time of next Timeout Check Trigger + signal timeout_check_time, timeout_check_time_next : TIME_TYPE; + -- Timeout time for DDS Operation + signal timeout_time, timeout_time_next : TIME_ARRAY_TYPE(0 to NUM_WRITERS-1); -- Signal used to differentiate between ACK and NACK Operations signal is_ack, is_ack_next : std_logic; -- Signal used to differentiate between RTPS and DDS Operations signal is_rtps, is_rtps_next : std_logic; -- Signifies if new Samples are available for RTPS Writer - signal data_available_sig, data_available_sig_next : std_logic; + signal data_available_sig, data_available_sig_next : std_logic_vector(0 to NUM_WRITERS-1); -- Denotes if Orphan Samples (of an removed stale instance) need to be removed signal orphan_samples, orphan_samples_next : std_logic; - -- Test signal used for testbench synchronisation + -- Signal used to index the writers + signal ind, ind_next : natural range 0 to NUM_WRITERS-1; + -- Test signals used in testbenches signal idle_sig : std_logic; + signal empty_inst_head_sig : NATURAL_ARRAY_TYPE; + signal empty_sample_head_sig : NATURAL_ARRAY_TYPE; + signal empty_payload_head_sig : NATURAL_ARRAY_TYPE; -- *COMMUNICATION STATUS* - signal status_sig, status_sig_next : std_logic_vector(STATUS_KIND_WIDTH-1 downto 0); + signal status_sig, status_sig_next : STATUS_KIND_ARRAY_TYPE(0 to NUM_WRITERS-1); -- LIVELINESS LOST STATUS -- Time of next Liveliness Deadline - signal lease_deadline, lease_deadline_next : TIME_TYPE; - signal liveliness_lost_cnt, liveliness_lost_cnt_next : unsigned(LIVELINESS_LOST_STATUS_COUNT_WIDTH-1 downto 0); - signal liveliness_lost_cnt_change, liveliness_lost_cnt_change_next : unsigned(LIVELINESS_LOST_STATUS_COUNT_WIDTH-1 downto 0); + signal lease_check_time, lease_check_time_next : TIME_TYPE; + signal lease_deadline, lease_deadline_next : TIME_ARRAY_TYPE(0 to NUM_WRITERS-1); + signal liveliness_lost_cnt, liveliness_lost_cnt_next : LIVELINESS_LOST_STATUS_COUNT_ARRAY_TYPE(0 to NUM_WRITERS-1); + signal liveliness_lost_cnt_change, liveliness_lost_cnt_change_next : LIVELINESS_LOST_STATUS_COUNT_ARRAY_TYPE(0 to NUM_WRITERS-1); -- SAMPLE REJECT STATUS signal sample_rej_cnt, sample_rej_cnt_next : unsigned(SAMPLE_REJECTED_STATUS_COUNT_WIDTH-1 downto 0); signal sample_rej_cnt_change, sample_rej_cnt_change_next : unsigned(SAMPLE_REJECTED_STATUS_COUNT_WIDTH-1 downto 0); @@ -394,10 +528,11 @@ architecture arch of dds_writer is signal sample_rej_last_inst, sample_rej_last_inst_next : INSTANCE_HANDLE_TYPE; -- OFFERED DEADLINE MISSED STATUS -- Time of next Deadline Miss Check - signal deadline_time, deadline_time_next : TIME_TYPE; - signal deadline_miss_cnt, deadline_miss_cnt_next : unsigned(REQUESTED_DEADLINE_MISSED_STATUS_COUNT_WIDTH-1 downto 0); - signal deadline_miss_cnt_change, deadline_miss_cnt_change_next : unsigned(REQUESTED_DEADLINE_MISSED_STATUS_COUNT_WIDTH-1 downto 0); - signal deadline_miss_last_inst, deadline_miss_last_inst_next : INSTANCE_HANDLE_TYPE; + signal deadline_check_time , deadline_check_time_next : TIME_TYPE; + signal deadline_time, deadline_time_next : TIME_ARRAY_TYPE(0 to NUM_WRITERS-1); + signal deadline_miss_cnt, deadline_miss_cnt_next : OFFERED_DEADLINE_MISSED_STATUS_COUNT_ARRAY_TYPE(0 to NUM_WRITERS-1); + signal deadline_miss_cnt_change, deadline_miss_cnt_change_next : OFFERED_DEADLINE_MISSED_STATUS_COUNT_ARRAY_TYPE(0 to NUM_WRITERS-1); + signal deadline_miss_last_inst, deadline_miss_last_inst_next : INSTANCE_HANDLE_ARRAY_TYPE(0 to NUM_WRITERS-1); -- *CACHE CHANGE* signal cc_instance_handle_sig, cc_instance_handle_sig_next : INSTANCE_HANDLE_TYPE; @@ -413,15 +548,13 @@ architecture arch of dds_writer is -- General Purpose Instance Memory Address Latch signal inst_addr_latch, inst_addr_latch_next : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0); -- Head of Empty Instance List - signal inst_empty_head, inst_empty_head_next : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0); + signal inst_empty_head, inst_empty_head_next : INSTANCE_MEMORY_ADDR_ARRAY_TYPE; -- Head of Occupied Instance List - signal inst_occupied_head, inst_occupied_head_next : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0); + signal inst_occupied_head, inst_occupied_head_next : INSTANCE_MEMORY_ADDR_ARRAY_TYPE; -- Latch for Instance Data from main process signal inst_latch_data, inst_latch_data_next : INSTANCE_DATA_TYPE; - -- NOTE: The next signal is driven by the inst_ctrl_prc. In case WITH_KEY is FALSE, no inst_ctrl_prc is generated and the inst_data is - -- set by the main process directly by drivng the next2 signal. The sync_prc is responsible for latching the correct next signal. -- Latch for Instance Data from memory - signal inst_data, inst_data_next, inst_data_next2 : INSTANCE_DATA_TYPE; + signal inst_data, inst_data_next : INSTANCE_DATA_TYPE; -- General Purpose Counter signal inst_cnt, inst_cnt_next : natural range 0 to 13; -- General Purpose Long Latch @@ -474,98 +607,166 @@ begin --*****COMPONENT INSTANTIATION***** - key_holder_inst : key_holder - port map ( - -- SYSTEM - clk => clk, - reset => reset, - -- CONTROL - start => start_kh, - opcode => opcode_kh, - ack => ack_kh, - decode_error => open, - abort => abort_kh, - -- INPUT - ready_in => ready_out_kh, - valid_in => valid_out_kh, - data_in => data_out_kh, - last_word_in => last_word_out_kh, - -- OUTPUT - ready_out => ready_in_kh, - valid_out => valid_in_kh, - data_out => data_in_kh, - last_word_out => last_word_in_kh - ); + key_holder_gen : for i in 0 to NUM_WRITERS-1 generate + key_holder_inst : key_holder + port map ( + -- SYSTEM + clk => clk, + reset => reset, + -- CONTROL + start => start_kh(i), + opcode => opcode_kh(i), + ack => ack_kh(i), + decode_error => open, + abort => abort_kh(i), + -- INPUT + ready_in => ready_out_kh(i), + valid_in => valid_out_kh(i), + data_in => data_out_kh(i), + last_word_in => last_word_out_kh(i), + -- OUTPUT + ready_out => ready_in_kh(i), + valid_out => valid_in_kh(i), + data_out => data_in_kh(i), + last_word_out => last_word_in_kh(i) + ); + end generate; - sample_mem_ctrl_inst : entity work.mem_ctrl(arch) - generic map ( - ADDR_WIDTH => SAMPLE_MEMORY_ADDR_WIDTH, - DATA_WIDTH => WORD_WIDTH, - MEMORY_DEPTH => SAMPLE_MEMORY_SIZE, - MAX_BURST_LENGTH => SAMPLE_FRAME_SIZE - ) - port map ( - clk => clk, - reset => reset or sample_abort_read, - addr => std_logic_vector(sample_addr), - read => sample_read, - ready_in => sample_ready_in, - valid_in => sample_valid_in, - data_in => sample_write_data, - ready_out => sample_ready_out, - valid_out => sample_valid_out, - data_out => sample_read_data - ); + sample_mem_ctrl_gen : for i in 0 to NUM_WRITERS-1 generate + sample_mem_ctrl_inst : entity work.mem_ctrl(arch) + generic map ( + ADDR_WIDTH => SAMPLE_MEMORY_ADDR_WIDTH, + DATA_WIDTH => WORD_WIDTH, + MEMORY_DEPTH => SAMPLE_MEMORY_SIZE(i), + MAX_BURST_LENGTH => SAMPLE_FRAME_SIZE + ) + port map ( + clk => clk, + reset => reset or sample_abort_read_i(i), + addr => std_logic_vector(sample_addr_i(i)), + read => sample_read_i(i), + ready_in => sample_ready_in_i(i), + valid_in => sample_valid_in_i(i), + data_in => sample_write_data_i(i), + ready_out => sample_ready_out_i(i), + valid_out => sample_valid_out_i(i), + data_out => sample_read_data_i(i) + ); + end generate; - payload_mem_ctrl_inst : entity work.mem_ctrl(arch) - generic map ( - ADDR_WIDTH => PAYLOAD_MEMORY_ADDR_WIDTH, - DATA_WIDTH => WORD_WIDTH, - MEMORY_DEPTH => PAYLOAD_MEMORY_SIZE, - MAX_BURST_LENGTH => PAYLOAD_FRAME_SIZE - ) - port map ( - clk => clk, - reset => reset or payload_abort_read, - addr => std_logic_vector(payload_addr), - read => payload_read, - ready_in => payload_ready_in, - valid_in => payload_valid_in, - data_in => payload_write_data, - ready_out => payload_ready_out, - valid_out => payload_valid_out, - data_out => payload_read_data - ); + payload_mem_ctrl_gen : for i in 0 to NUM_WRITERS-1 generate + payload_mem_ctrl_inst : entity work.mem_ctrl(arch) + generic map ( + ADDR_WIDTH => PAYLOAD_MEMORY_ADDR_WIDTH, + DATA_WIDTH => WORD_WIDTH, + MEMORY_DEPTH => PAYLOAD_MEMORY_SIZE(i), + MAX_BURST_LENGTH => PAYLOAD_FRAME_SIZE(i) + ) + port map ( + clk => clk, + reset => reset or payload_abort_read_i(i), + addr => std_logic_vector(payload_addr_i(i)), + read => payload_read_i(i), + ready_in => payload_ready_in_i(i), + valid_in => payload_valid_in_i(i), + data_in => payload_write_data_i(i), + ready_out => payload_ready_out_i(i), + valid_out => payload_valid_out_i(i), + data_out => payload_read_data_i(i) + ); + end generate; - gen_instance_mem_ctrl_inst : if WITH_KEY generate + instance_mem_ctrl_gen : for i in 0 to NUM_WRITERS-1 generate instance_mem_ctrl_inst : entity work.mem_ctrl(arch) generic map ( ADDR_WIDTH => INSTANCE_MEMORY_ADDR_WIDTH, DATA_WIDTH => WORD_WIDTH, - MEMORY_DEPTH => INSTANCE_MEMORY_SIZE, + MEMORY_DEPTH => INSTANCE_MEMORY_SIZE(i), MAX_BURST_LENGTH => INSTANCE_FRAME_SIZE ) port map ( clk => clk, - reset => reset or inst_abort_read, - addr => std_logic_vector(inst_addr), - read => inst_read, - ready_in => inst_ready_in, - valid_in => inst_valid_in, - data_in => inst_write_data, - ready_out => inst_ready_out, - valid_out => inst_valid_out, - data_out => inst_read_data + reset => reset or inst_abort_read_i(i), + addr => std_logic_vector(inst_addr_i(i)), + read => inst_read_i(i), + ready_in => inst_ready_in_i(i), + valid_in => inst_valid_in_i(i), + data_in => inst_write_data_i(i), + ready_out => inst_ready_out_i(i), + valid_out => inst_valid_out_i(i), + data_out => inst_read_data_i(i) ); - end generate; + inst_memory_mux : process (all) + begin + inst_abort_read_i <= (others => '0'); + inst_addr_i <= (others => (others => '0')); + inst_read_i <= (others => '0'); + inst_valid_in_i <= (others => '0'); + inst_write_data_i <= (others => (others => '0')); + inst_ready_out_i <= (others => '0'); + + inst_abort_read_i(inst_latch_data.i) <= inst_abort_read; + inst_addr_i(inst_latch_data.i) <= inst_addr; + inst_read_i(inst_latch_data.i) <= inst_read; + inst_valid_in_i(inst_latch_data.i) <= inst_valid_in; + inst_write_data_i(inst_latch_data.i) <= inst_write_data; + inst_ready_out_i(inst_latch_data.i) <= inst_ready_out; + + inst_ready_in <= inst_ready_in_i(inst_latch_data.i); + inst_valid_out <= inst_valid_out_i(inst_latch_data.i); + inst_read_data <= inst_read_data_i(inst_latch_data.i); + end process; + + sample_memory_mux : process (all) + begin + sample_abort_read_i <= (others => '0'); + sample_addr_i <= (others => (others => '0')); + sample_read_i <= (others => '0'); + sample_valid_in_i <= (others => '0'); + sample_write_data_i <= (others => (others => '0')); + sample_ready_out_i <= (others => '0'); + + sample_abort_read_i(ind) <= sample_abort_read; + sample_addr_i(ind) <= sample_addr; + sample_read_i(ind) <= sample_read; + sample_valid_in_i(ind) <= sample_valid_in; + sample_write_data_i(ind) <= sample_write_data; + sample_ready_out_i(ind) <= sample_ready_out; + + sample_ready_in <= sample_ready_in_i(ind); + sample_valid_out <= sample_valid_out_i(ind); + sample_read_data <= sample_read_data_i(ind); + end process; + + payload_memory_mux : process (all) + begin + payload_abort_read_i <= (others => '0'); + payload_addr_i <= (others => (others => '0')); + payload_read_i <= (others => '0'); + payload_valid_in_i <= (others => '0'); + payload_write_data_i <= (others => (others => '0')); + payload_ready_out_i <= (others => '0'); + + payload_abort_read_i(ind) <= payload_abort_read; + payload_addr_i(ind) <= payload_addr; + payload_read_i(ind) <= payload_read; + payload_valid_in_i(ind) <= payload_valid_in; + payload_write_data_i(ind) <= payload_write_data; + payload_ready_out_i(ind) <= payload_ready_out; + + payload_ready_in <= payload_ready_in_i(ind); + payload_valid_out <= payload_valid_out_i(ind); + payload_read_data <= payload_read_data_i(ind); + end process; + status <= status_sig; data_available <= data_available_sig; - cc_instance_handle <= cc_instance_handle_sig; - cc_kind <= cc_kind_sig; - cc_source_timestamp <= cc_source_timestamp_sig; - cc_seq_nr <= cc_seq_nr_sig; + cc_instance_handle <= (others => cc_instance_handle_sig); + cc_kind <= (others => cc_kind_sig); + cc_source_timestamp <= (others => cc_source_timestamp_sig); + cc_seq_nr <= (others => cc_seq_nr_sig); -- *Main State Machine* -- STATE DESCRIPTION @@ -604,6 +805,8 @@ begin -- GET_LIVELINESS_LOST_STATUS Return Liveliness Loss Status -- GET_OFFERED_DEADLINE_MISSED_STATUS Return Offered Deadline Missed Status -- CHECK_DEADLINE Check and Mark Instances with missed Deadlines + -- CHECK_LIVELINESS Check liveliness status of all Writers + -- CHECK_ACK_WAIT Check WAIT_FOR_ACKNOWLEDGEMENT operation exit conditions -- RESET_SAMPLE_MEMORY Reset Sample Memory to Empty State -- RESET_PAYLOAD_MEMORY Reset Payload Memory to Empty State parse_a_prc : process (all) @@ -635,6 +838,7 @@ begin sample_rej_cnt_change_next <= sample_rej_cnt_change; sample_rej_last_reason_next <= sample_rej_last_reason; sample_rej_last_inst_next <= sample_rej_last_inst; + deadline_check_time_next <= deadline_check_time; deadline_time_next <= deadline_time; deadline_miss_cnt_next <= deadline_miss_cnt; deadline_miss_cnt_change_next <= deadline_miss_cnt_change; @@ -656,7 +860,10 @@ begin register_op_next <= register_op; lookup_op_next <= lookup_op; ack_wait_next <= ack_wait; + ack_wait_check_next <= ack_wait_check; + timeout_check_time_next <= timeout_check_time; timeout_time_next <= timeout_time; + lease_check_time_next <= lease_check_time; lease_deadline_next <= lease_deadline; seq_nr_next <= seq_nr; return_stage_next <= return_stage; @@ -669,18 +876,18 @@ begin data_available_sig_next <= data_available_sig; orphan_samples_next <= orphan_samples; key_hash_next <= key_hash; - inst_data_next2 <= inst_data; return_code_latch_next <= return_code_latch; + ind_next <= ind; -- DEFAULT Unregistered inst_opcode <= NOP; - ret_rtps <= ERROR; - return_code_dds <= RETCODE_UNSUPPORTED; - opcode_kh <= NOP; - instance_handle_out_dds <= HANDLE_NIL; - ack_dds <= '0'; - done_dds <= '0'; - ack_rtps <= '0'; - done_rtps <= '0'; + ret_rtps <= (others => ERROR); + return_code_dds <= (others => RETCODE_UNSUPPORTED); + opcode_kh <= (others => NOP); + instance_handle_out_dds <= (others => HANDLE_NIL); + ack_dds <= (others => '0'); + done_dds <= (others => '0'); + ack_rtps <= (others => '0'); + done_rtps <= (others => '0'); inst_op_start <= '0'; sample_read <= '0'; sample_ready_out <= '0'; @@ -690,25 +897,25 @@ begin payload_ready_out <= '0'; payload_valid_in <= '0'; payload_abort_read <= '0'; - ready_in_dds <= '0'; - liveliness_assertion <= '0'; - valid_out_rtps <= '0'; - last_word_out_rtps <= '0'; - valid_out_dds <= '0'; - last_word_out_dds <= '0'; - start_kh <= '0'; - ready_in_kh <= '0'; - valid_out_kh <= '0'; - last_word_out_kh <= '0'; - abort_kh <= '0'; + ready_in_dds <= (others => '0'); + liveliness_assertion <= (others => '0'); + valid_out_rtps <= (others => '0'); + last_word_out_rtps <= (others => '0'); + valid_out_dds <= (others => '0'); + last_word_out_dds <= (others => '0'); + start_kh <= (others => '0'); + ready_in_kh <= (others => '0'); + valid_out_kh <= (others => '0'); + last_word_out_kh <= (others => '0'); + abort_kh <= (others => '0'); idle_sig <= '0'; - data_out_kh <= (others => '0'); + data_out_kh <= (others => (others => '0')); sample_addr <= (others => '0'); sample_write_data <= (others => '0'); payload_addr <= (others => '0'); payload_write_data <= (others => '0'); - data_out_rtps <= (others => '0'); - data_out_dds <= (others => '0'); + data_out_rtps <= (others => (others => '0')); + data_out_dds <= (others => (others => '0')); inst_r <= ZERO_INSTANCE_DATA; @@ -726,426 +933,396 @@ begin -- Orphan Samples Available if (orphan_samples = '1') then - assert (oldest_sample /= SAMPLE_MEMORY_MAX_ADDRESS) severity FAILURE; - cur_sample_next <= oldest_sample; + assert (oldest_sample(ind) /= SAMPLE_MEMORY_MAX_ADDRESS) severity FAILURE; + cur_sample_next <= oldest_sample(ind); stage_next <= REMOVE_ORPHAN_SAMPLES; cnt_next <= 0; -- DEADLINE QoS - elsif (DEADLINE_QOS /= DURATION_INFINITE and deadline_time <= time) then - -- Reset Timeout - deadline_time_next <= deadline_time + DEADLINE_QOS; + elsif (deadline_check_time <= time) then + -- Reset + deadline_check_time_next <= TIME_INFINITE; - -- Synthesis Guard - if (WITH_KEY) then - stage_next <= CHECK_DEADLINE; - cnt_next <= 0; - else - if (inst_data.status_info(ISI_LIVELINESS_FLAG) = '1') then - -- Reset Liveliness Flag - inst_data_next2.status_info(ISI_LIVELINESS_FLAG) <= '0'; - else - -- Update Requested Deadline Missed Status - status_sig_next <= status_sig or OFFERED_DEADLINE_MISSED_STATUS; - deadline_miss_cnt_next <= deadline_miss_cnt + 1; - deadline_miss_cnt_change_next <= deadline_miss_cnt_change + 1; - end if; - end if; + ind_next <= 0; + stage_next <= CHECK_DEADLINE; + cnt_next <= 1; -- CHECK DEADLINE -- Liveliness Deadline - elsif (LEASE_DURATION /= DURATION_INFINITE and lease_deadline <= time) then - liveliness_lost_cnt_next <= liveliness_lost_cnt + 1; - liveliness_lost_cnt_change_next <= liveliness_lost_cnt_change + 1; - status_sig_next <= status_sig or LIVELINESS_LOST_STATUS; - + elsif (lease_check_time <= time) then -- Reset - lease_deadline_next <= time + LEASE_DURATION; - -- WAIT_FOR_ACKNOWLEDGEMENT Done - elsif (ack_wait = '1' and global_ack_cnt = global_sample_cnt) then - -- Reset - ack_wait_next <= '0'; + lease_check_time_next <= TIME_INFINITE; - -- DONE - done_dds <= '1'; - return_code_dds <= RETCODE_OK; - -- WAIT_FOR_ACKNOWLEDGEMENT Timeout - elsif (ack_wait = '1' and timeout_time <= time) then - -- Reset - ack_wait_next <= '0'; + ind_next <= 0; + stage_next <= CHECK_LIVELINESS; + cnt_next <= 1; -- CHECK LEASE + -- WAIT_FOR_ACKNOWLEDGEMENT Trigger + elsif (ack_wait /= (ack_wait'range => '0') and (ack_wait_check = '1' or timeout_check_time <= time)) then + ind_next <= 0; - -- DONE - done_dds <= '1'; - return_code_dds <= RETCODE_TIMEOUT; + -- RESET + timeout_check_time_next <= TIME_INFINITE; + + stage_next <= CHECK_ACK_WAIT; + cnt_next <= 1; -- CHECK ACK STATE -- LIFESPAN QoS elsif (lifespan_time <= time) then -- Reset Timeout lifespan_time_next <= TIME_INFINITE; + is_lifespan_check_next <= '1'; + ind_next <= 0; - -- Samples Available - if (oldest_sample /= SAMPLE_MEMORY_MAX_ADDRESS) then - is_lifespan_check_next <= '1'; - cur_sample_next <= oldest_sample; - stage_next <= CHECK_LIFESPAN; - cnt_next <= 0; - end if; + stage_next <= CHECK_LIFESPAN; + cnt_next <= 1; -- CHECK LIFESPAN -- RTPS Operation - elsif (start_rtps = '1') then - is_rtps_next <= '1'; - -- Latch Input Signal - seq_nr_next <= seq_nr_rtps; - -- Reset - is_ack_next <= '0'; - - case (opcode_rtps) is - when GET_MIN_SN => - ack_rtps <= '1'; - if (oldest_sample = SAMPLE_MEMORY_MAX_ADDRESS) then - -- NOTE: If the HC is empty we return the Special value SEQUENCENUMBER_UNKNOWN - stage_next <= GET_SEQ_NR; - cnt_next <= 4; - cc_seq_nr_sig_next <= SEQUENCENUMBER_UNKNOWN; - else - cur_sample_next <= oldest_sample; - stage_next <= GET_SEQ_NR; - cnt_next <= 0; - end if; - when GET_MAX_SN => - ack_rtps <= '1'; - - -- Reset Data Availability - data_available_sig_next <= '0'; - - if (newest_sample = SAMPLE_MEMORY_MAX_ADDRESS) then - -- NOTE: If the HC is empty we return the Special value SEQUENCENUMBER_UNKNOWN - stage_next <= GET_SEQ_NR; - cnt_next <= 4; - cc_seq_nr_sig_next <= SEQUENCENUMBER_UNKNOWN; - else - cur_sample_next <= newest_sample; - stage_next <= GET_SEQ_NR; - cnt_next <= 0; - end if; - when GET_CACHE_CHANGE => - ack_rtps <= '1'; - - -- No Samples Available - if (newest_sample = SAMPLE_MEMORY_MAX_ADDRESS) then - stage_next <= UNKNOWN_SEQ_NR; - cc_seq_nr_sig_next <= SEQUENCENUMBER_UNKNOWN; - else - cc_seq_nr_sig_next <= seq_nr_rtps; - cur_sample_next <= newest_sample; - stage_next <= FIND_SEQ_NR; - cnt_next <= 0; - return_stage_next <= GET_SAMPLE; - end if; - when ACK_CACHE_CHANGE => - ack_rtps <= '1'; - is_ack_next <= '1'; - - -- No Samples Available - if (newest_sample = SAMPLE_MEMORY_MAX_ADDRESS) then - stage_next <= UNKNOWN_SEQ_NR; - cc_seq_nr_sig_next <= SEQUENCENUMBER_UNKNOWN; - else - cur_sample_next <= newest_sample; - stage_next <= FIND_SEQ_NR; - cnt_next <= 0; - return_stage_next <= ACKNACK_SAMPLE; - end if; - when NACK_CACHE_CHANGE => - ack_rtps <= '1'; - - -- No Samples Available - if (newest_sample = SAMPLE_MEMORY_MAX_ADDRESS) then - stage_next <= UNKNOWN_SEQ_NR; - cc_seq_nr_sig_next <= SEQUENCENUMBER_UNKNOWN; - else - cur_sample_next <= newest_sample; - stage_next <= FIND_SEQ_NR; - cnt_next <= 0; - return_stage_next <= ACKNACK_SAMPLE; - end if; - when REMOVE_CACHE_CHANGE => - ack_rtps <= '1'; - - -- No Samples Available - if (newest_sample = SAMPLE_MEMORY_MAX_ADDRESS) then - stage_next <= UNKNOWN_SEQ_NR; - cc_seq_nr_sig_next <= SEQUENCENUMBER_UNKNOWN; - else - cur_sample_next <= newest_sample; - stage_next <= FIND_SEQ_NR; - cnt_next <= 0; - return_stage_next <= REMOVE_SAMPLE; - end if; - when others => - ack_rtps <= '1'; - - stage_next <= UNKNOWN_OPERATION_RTPS; - end case; + elsif (start_rtps /= (start_rtps'range => '0')) then + if (start_rtps(ind) /= '1') then + if (ind = NUM_WRITERS-1) then + ind_next <= 0; + else + ind_next <= ind + 1; + end if; + else + is_rtps_next <= '1'; + -- Latch Input Signal + seq_nr_next <= seq_nr_rtps(ind); + -- Reset + is_ack_next <= '0'; + + case (opcode_rtps(ind)) is + when GET_MIN_SN => + ack_rtps(ind) <= '1'; + if (oldest_sample(ind) = SAMPLE_MEMORY_MAX_ADDRESS) then + -- NOTE: If the HC is empty we return the Special value SEQUENCENUMBER_UNKNOWN + stage_next <= GET_SEQ_NR; + cnt_next <= 4; -- Return Code + cc_seq_nr_sig_next <= SEQUENCENUMBER_UNKNOWN; + else + cur_sample_next <= oldest_sample(ind); + stage_next <= GET_SEQ_NR; + cnt_next <= 0; + end if; + when GET_MAX_SN => + ack_rtps(ind) <= '1'; + + -- Reset Data Availability + data_available_sig_next(ind) <= '0'; + + if (newest_sample(ind) = SAMPLE_MEMORY_MAX_ADDRESS) then + -- NOTE: If the HC is empty we return the Special value SEQUENCENUMBER_UNKNOWN + stage_next <= GET_SEQ_NR; + cnt_next <= 4; -- Return Code + cc_seq_nr_sig_next <= SEQUENCENUMBER_UNKNOWN; + else + cur_sample_next <= newest_sample(ind); + stage_next <= GET_SEQ_NR; + cnt_next <= 0; + end if; + when GET_CACHE_CHANGE => + ack_rtps(ind) <= '1'; + + -- No Samples Available + if (newest_sample(ind) = SAMPLE_MEMORY_MAX_ADDRESS) then + stage_next <= UNKNOWN_SEQ_NR; + cc_seq_nr_sig_next <= SEQUENCENUMBER_UNKNOWN; + else + cc_seq_nr_sig_next <= seq_nr_rtps(ind); + cur_sample_next <= newest_sample(ind); + stage_next <= FIND_SEQ_NR; + cnt_next <= 0; + return_stage_next <= GET_SAMPLE; + end if; + when ACK_CACHE_CHANGE => + ack_rtps(ind) <= '1'; + is_ack_next <= '1'; + + -- No Samples Available + if (newest_sample(ind) = SAMPLE_MEMORY_MAX_ADDRESS) then + stage_next <= UNKNOWN_SEQ_NR; + cc_seq_nr_sig_next <= SEQUENCENUMBER_UNKNOWN; + else + cur_sample_next <= newest_sample(ind); + stage_next <= FIND_SEQ_NR; + cnt_next <= 0; + return_stage_next <= ACKNACK_SAMPLE; + end if; + when NACK_CACHE_CHANGE => + ack_rtps(ind) <= '1'; + + -- No Samples Available + if (newest_sample(ind) = SAMPLE_MEMORY_MAX_ADDRESS) then + stage_next <= UNKNOWN_SEQ_NR; + cc_seq_nr_sig_next <= SEQUENCENUMBER_UNKNOWN; + else + cur_sample_next <= newest_sample(ind); + stage_next <= FIND_SEQ_NR; + cnt_next <= 0; + return_stage_next <= ACKNACK_SAMPLE; + end if; + when REMOVE_CACHE_CHANGE => + ack_rtps(ind) <= '1'; + + -- No Samples Available + if (newest_sample(ind) = SAMPLE_MEMORY_MAX_ADDRESS) then + stage_next <= UNKNOWN_SEQ_NR; + cc_seq_nr_sig_next <= SEQUENCENUMBER_UNKNOWN; + else + cur_sample_next <= newest_sample(ind); + stage_next <= FIND_SEQ_NR; + cnt_next <= 0; + return_stage_next <= REMOVE_SAMPLE; + end if; + when others => + ack_rtps(ind) <= '1'; + + stage_next <= UNKNOWN_OPERATION_RTPS; + end case; + end if; -- DDS Operation (Stall DDS Operation if a wait Operation is in progress) - elsif (ack_wait = '0' and start_dds = '1') then - -- Reset - register_op_next <= '0'; - instance_handle_next <= HANDLE_NIL; - source_ts_next <= TIME_INVALID; - sample_status_info_next <= (others => '0'); - key_hash_next <= KEY_HASH_NIL; - new_sample_next <= SAMPLE_MEMORY_MAX_ADDRESS; - return_code_latch_next <= RETCODE_UNSUPPORTED; - - case (opcode_dds) is - when REGISTER_INSTANCE => - -- Synthesis Guard - if (WITH_KEY) then - start_kh <= '1'; - opcode_kh <= PUSH_DATA; + elsif (((not ack_wait) and start_dds) /= (start_dds'range => '0')) then + if not (ack_wait(ind) = '0' and start_dds(ind) = '1') then + if (ind = NUM_WRITERS-1) then + ind_next <= 0; + else + ind_next <= ind + 1; + end if; + else + -- Reset + register_op_next <= '0'; + instance_handle_next <= HANDLE_NIL; + source_ts_next <= TIME_INVALID; + sample_status_info_next <= (others => '0'); + key_hash_next <= KEY_HASH_NIL; + new_sample_next <= SAMPLE_MEMORY_MAX_ADDRESS; + return_code_latch_next <= RETCODE_UNSUPPORTED; + + case (opcode_dds(ind)) is + when REGISTER_INSTANCE => + -- Synthesis Guard + if (CONFIG_ARRAY_T(ind).WITH_KEY) then + start_kh(ind) <= '1'; + opcode_kh(ind) <= PUSH_DATA; + + if (ack_kh(ind) = '1') then + ack_dds(ind) <= '1'; + register_op_next <= '1'; + stage_next <= ADD_PAYLOAD; + cnt_next <= 1; + end if; + else + ack_dds(ind) <= '1'; + key_hash_next <= KEY_HASH_NIL; + stage_next <= SKIP; + return_stage_next <= PUSH_KEY_HASH; + end if; + when WRITE => + ack_dds(ind) <= '1'; - if (ack_kh = '1') then - ack_dds <= '1'; - register_op_next <= '1'; - stage_next <= ADD_PAYLOAD; - cnt_next <= 1; - end if; - else - ack_dds <= '1'; - key_hash_next <= KEY_HASH_NIL; - stage_next <= SKIP; - return_stage_next <= PUSH_KEY_HASH; - end if; - when WRITE => - ack_dds <= '1'; - - -- Reset Liveliness - lease_deadline_next <= time + LEASE_DURATION; - - -- Latch Input Signals - instance_handle_next <= instance_handle_in_dds; - source_ts_next <= source_ts_dds; - - -- NOTE: The ALIGNED_FLAG is set by default. if actual Payload is not aligned, need to reset. - sample_status_info_next <= (SSI_DATA_FLAG => '1', SSI_ALIGNED_FLAG => '1', others => '0'); - cur_sample_next <= empty_sample_list_head; - - -- NOTE: We have to explicitly check the Payload Memory, as it may be "unaligned" with our Sample Memory - -- (Sample Memory has available Slot, but Payload Memory not) - -- Payload Memory Full - if (empty_payload_list_head = PAYLOAD_MEMORY_MAX_ADDRESS) then - if (global_ack_cnt = 0 and HISTORY_QOS = KEEP_ALL_HISTORY_QOS) then - -- Reject Change - stage_next <= SKIP_AND_RETURN; - cnt_next <= 0; - return_code_latch_next <= RETCODE_OUT_OF_RESOURCES; - else - assert (oldest_sample /= SAMPLE_MEMORY_MAX_ADDRESS) severity FAILURE; - -- Do not ACK Operation - ack_dds <= '0'; - - - if (global_ack_cnt /= 0) then - -- Remove Oldest ACKed Sample - remove_oldest_sample_next <= '1'; - remove_ack_sample_next <= '1'; - - cur_sample_next <= oldest_sample; - stage_next <= FIND_SAMPLE; - cnt_next <= 0; - elsif (WITH_KEY) then - stage_next <= GET_OLDEST_SAMPLE_INSTANCE; - cnt_next <= 0; - else - cur_sample_next <= oldest_sample; - stage_next <= REMOVE_SAMPLE; - cnt_next <= 0; - end if; - end if; - else - -- Instance Handle provided - if (WITH_KEY and instance_handle_in_dds /= HANDLE_NIL) then - key_hash_next <= instance_handle_in_dds; - stage_next <= INITIATE_INSTANCE_SEARCH; - cnt_next <= 0; - else - stage_next <= ADD_SAMPLE_INFO; - cnt_next <= 0; - end if; - end if; - when DISPOSE => - ack_dds <= '1'; - - -- Reset Liveliness - lease_deadline_next <= time + LEASE_DURATION; - - -- Latch Input Signals - instance_handle_next <= instance_handle_in_dds; - source_ts_next <= source_ts_dds; - - -- NOTE: The ALIGNED_FLAG is set by default. if actual Payload is not aligned, need to reset. - sample_status_info_next <= (SSI_DATA_FLAG => '1', SSI_ALIGNED_FLAG => '1', SSI_DISPOSED_FLAG => '1', others => '0'); - cur_sample_next <= empty_sample_list_head; - - -- NOTE: We always expect a Serialized Key as Input of this Opration, so we also check the Payload memory - -- Payload Memory Full - if (empty_payload_list_head = PAYLOAD_MEMORY_MAX_ADDRESS) then - if (global_ack_cnt = 0 and HISTORY_QOS = KEEP_ALL_HISTORY_QOS) then - -- Reject Change - stage_next <= SKIP_AND_RETURN; - cnt_next <= 0; - return_code_latch_next <= RETCODE_OUT_OF_RESOURCES; - else - assert (oldest_sample /= SAMPLE_MEMORY_MAX_ADDRESS) severity FAILURE; - -- Do not ACK Operation - ack_dds <= '0'; - - if (global_ack_cnt /= 0) then - -- Remove Oldest ACKed Sample - remove_oldest_sample_next <= '1'; - remove_ack_sample_next <= '1'; - - cur_sample_next <= oldest_sample; - stage_next <= FIND_SAMPLE; - cnt_next <= 0; - elsif (WITH_KEY) then - stage_next <= GET_OLDEST_SAMPLE_INSTANCE; - cnt_next <= 0; - else - cur_sample_next <= oldest_sample; - stage_next <= REMOVE_SAMPLE; - cnt_next <= 0; - end if; - end if; - else - -- Instance Handle provided - if (WITH_KEY and instance_handle_in_dds /= HANDLE_NIL) then - key_hash_next <= instance_handle_in_dds; - stage_next <= INITIATE_INSTANCE_SEARCH; - cnt_next <= 0; - else - stage_next <= ADD_SAMPLE_INFO; - cnt_next <= 0; - end if; - end if; - when UNREGISTER_INSTANCE => - ack_dds <= '1'; - - -- Reset Liveliness - lease_deadline_next <= time + LEASE_DURATION; - - -- Latch Input Signals - instance_handle_next <= instance_handle_in_dds; - source_ts_next <= source_ts_dds; - - -- NOTE: The ALIGNED_FLAG is set by default. if actual Payload is not aligned, need to reset. - sample_status_info_next <= (SSI_DATA_FLAG => '1', SSI_ALIGNED_FLAG => '1', SSI_UNREGISTERED_FLAG => '1', others => '0'); - cur_sample_next <= empty_sample_list_head; - - -- NOTE: We always expect a Serialized Key as Input of this Opration, so we also check the Payload memory - -- Payload Memory Full - if (empty_payload_list_head = PAYLOAD_MEMORY_MAX_ADDRESS) then - if (global_ack_cnt = 0 and HISTORY_QOS = KEEP_ALL_HISTORY_QOS) then - -- Reject Change - stage_next <= SKIP_AND_RETURN; - cnt_next <= 0; - return_code_latch_next <= RETCODE_OUT_OF_RESOURCES; - else - assert (oldest_sample /= SAMPLE_MEMORY_MAX_ADDRESS) severity FAILURE; - -- Do not ACK Operation - ack_dds <= '0'; - - if (global_ack_cnt /= 0) then - -- Remove Oldest ACKed Sample - remove_oldest_sample_next <= '1'; - remove_ack_sample_next <= '1'; - - cur_sample_next <= oldest_sample; - stage_next <= FIND_SAMPLE; - cnt_next <= 0; - elsif (WITH_KEY) then - stage_next <= GET_OLDEST_SAMPLE_INSTANCE; - cnt_next <= 0; - else - cur_sample_next <= oldest_sample; - stage_next <= REMOVE_SAMPLE; - cnt_next <= 0; - end if; - end if; - else - -- Instance Handle provided - if (WITH_KEY and instance_handle_in_dds /= HANDLE_NIL) then - key_hash_next <= instance_handle_in_dds; - stage_next <= INITIATE_INSTANCE_SEARCH; - cnt_next <= 0; - else - stage_next <= ADD_SAMPLE_INFO; - cnt_next <= 0; - end if; - end if; - when LOOKUP_INSTANCE => - -- Synthesis Guard - if (WITH_KEY) then - start_kh <= '1'; - opcode_kh <= PUSH_DATA; + -- Reset Liveliness + lease_deadline_next(ind) <= time + CONFIG_ARRAY_T(ind).LEASE_DURATION; - if (ack_kh = '1') then - ack_dds <= '1'; - lookup_op_next <= '1'; - stage_next <= ADD_PAYLOAD; - cnt_next <= 1; + -- Latch Input Signals + key_hash_next <= instance_handle_in_dds(ind); + instance_handle_next <= instance_handle_in_dds(ind); + source_ts_next <= source_ts_dds(ind); + + -- NOTE: The ALIGNED_FLAG is set by default. If actual Payload is not aligned, need to reset. + sample_status_info_next <= (SSI_DATA_FLAG => '1', SSI_ALIGNED_FLAG => '1', others => '0'); + cur_sample_next <= empty_sample_list_head(ind); + + -- NOTE: We have to explicitly check the Payload Memory, as it may be "unaligned" with our Sample Memory + -- (Sample Memory has available Slot, but Payload Memory not) + -- Payload Memory Full + if (empty_payload_list_head(ind) = PAYLOAD_MEMORY_MAX_ADDRESS) then + if (global_ack_cnt(ind) = 0 and CONFIG_ARRAY_T(ind).HISTORY_QOS = KEEP_ALL_HISTORY_QOS) then + -- Reject Change + stage_next <= SKIP_AND_RETURN; + cnt_next <= 0; + return_code_latch_next <= RETCODE_OUT_OF_RESOURCES; + else + assert (oldest_sample(ind) /= SAMPLE_MEMORY_MAX_ADDRESS) severity FAILURE; + + -- Do not ACK Operation + ack_dds(ind) <= '0'; + + + if (global_ack_cnt(ind) /= 0) then + -- Remove Oldest ACKed Sample + remove_oldest_sample_next <= '1'; + remove_ack_sample_next <= '1'; + + cur_sample_next <= oldest_sample(ind); + stage_next <= FIND_SAMPLE; + cnt_next <= 0; + else + stage_next <= GET_OLDEST_SAMPLE_INSTANCE; + cnt_next <= 0; + end if; + end if; + else + stage_next <= ADD_SAMPLE_INFO; + cnt_next <= 0; end if; - else - ack_dds <= '1'; - key_hash_next <= KEY_HASH_NIL; - stage_next <= SKIP; - return_stage_next <= PUSH_KEY_HASH; - end if; - when WAIT_FOR_ACKNOWLEDGEMENTS => - -- NOTE: In case of BEST_EFFORT the RTPS Writer still manually ACKs the Samples, so we do not handle this case differently here. - ack_dds <= '1'; - ack_wait_next <= '1'; - timeout_time_next <= time + max_wait_dds; - when GET_OFFERED_DEADLINE_MISSED_STATUS => - ack_dds <= '1'; - stage_next <= GET_OFFERED_DEADLINE_MISSED_STATUS; - cnt_next <= 0; - when ASSERT_LIVELINESS => - -- Reset Liveliness - lease_deadline_next <= time + LEASE_DURATION; - - ack_dds <= '1'; - stage_next <= ASSERT_LIVELINESS; - when GET_LIVELINESS_LOST_STATUS => - ack_dds <= '1'; - stage_next <= GET_LIVELINESS_LOST_STATUS; - cnt_next <= 0; - when others => - ack_dds <= '1'; - stage_next <= UNKNOWN_OPERATION_DDS; - end case; + when DISPOSE => + ack_dds(ind) <= '1'; + + -- Reset Liveliness + lease_deadline_next(ind) <= time + CONFIG_ARRAY_T(ind).LEASE_DURATION; + + -- Latch Input Signals + key_hash_next <= instance_handle_in_dds(ind); + instance_handle_next <= instance_handle_in_dds(ind); + source_ts_next <= source_ts_dds(ind); + + -- NOTE: The ALIGNED_FLAG is set by default. if actual Payload is not aligned, need to reset. + sample_status_info_next <= (SSI_DATA_FLAG => '1', SSI_ALIGNED_FLAG => '1', SSI_DISPOSED_FLAG => '1', others => '0'); + cur_sample_next <= empty_sample_list_head(ind); + + -- NOTE: We always expect a Serialized Key as Input of this Opration, so we also check the Payload memory + -- Payload Memory Full + if (empty_payload_list_head(ind) = PAYLOAD_MEMORY_MAX_ADDRESS) then + if (global_ack_cnt(ind) = 0 and CONFIG_ARRAY_T(ind).HISTORY_QOS = KEEP_ALL_HISTORY_QOS) then + -- Reject Change + stage_next <= SKIP_AND_RETURN; + cnt_next <= 0; + return_code_latch_next <= RETCODE_OUT_OF_RESOURCES; + else + assert (oldest_sample(ind) /= SAMPLE_MEMORY_MAX_ADDRESS) severity FAILURE; + -- Do not ACK Operation + ack_dds(ind) <= '0'; + + if (global_ack_cnt(ind) /= 0) then + -- Remove Oldest ACKed Sample + remove_oldest_sample_next <= '1'; + remove_ack_sample_next <= '1'; + + cur_sample_next <= oldest_sample(ind); + stage_next <= FIND_SAMPLE; + cnt_next <= 0; + else + stage_next <= GET_OLDEST_SAMPLE_INSTANCE; + cnt_next <= 0; + end if; + end if; + else + stage_next <= ADD_SAMPLE_INFO; + cnt_next <= 0; + end if; + when UNREGISTER_INSTANCE => + ack_dds(ind) <= '1'; + + -- Reset Liveliness + lease_deadline_next(ind) <= time + CONFIG_ARRAY_T(ind).LEASE_DURATION; + + -- Latch Input Signals + key_hash_next <= instance_handle_in_dds(ind); + instance_handle_next <= instance_handle_in_dds(ind); + source_ts_next <= source_ts_dds(ind); + + -- NOTE: The ALIGNED_FLAG is set by default. if actual Payload is not aligned, need to reset. + sample_status_info_next <= (SSI_DATA_FLAG => '1', SSI_ALIGNED_FLAG => '1', SSI_UNREGISTERED_FLAG => '1', others => '0'); + cur_sample_next <= empty_sample_list_head(ind); + + -- NOTE: We always expect a Serialized Key as Input of this Operation, so we also check the Payload memory + -- Payload Memory Full + if (empty_payload_list_head(ind) = PAYLOAD_MEMORY_MAX_ADDRESS) then + if (global_ack_cnt(ind) = 0 and CONFIG_ARRAY_T(ind).HISTORY_QOS = KEEP_ALL_HISTORY_QOS) then + -- Reject Change + stage_next <= SKIP_AND_RETURN; + cnt_next <= 0; + return_code_latch_next <= RETCODE_OUT_OF_RESOURCES; + else + assert (oldest_sample(ind) /= SAMPLE_MEMORY_MAX_ADDRESS) severity FAILURE; + -- Do not ACK Operation + ack_dds(ind) <= '0'; + + if (global_ack_cnt(ind) /= 0) then + -- Remove Oldest ACKed Sample + remove_oldest_sample_next <= '1'; + remove_ack_sample_next <= '1'; + + cur_sample_next <= oldest_sample(ind); + stage_next <= FIND_SAMPLE; + cnt_next <= 0; + else + stage_next <= GET_OLDEST_SAMPLE_INSTANCE; + cnt_next <= 0; + end if; + end if; + else + stage_next <= ADD_SAMPLE_INFO; + cnt_next <= 0; + end if; + when LOOKUP_INSTANCE => + -- Synthesis Guard + if (CONFIG_ARRAY_T(ind).WITH_KEY) then + start_kh(ind) <= '1'; + opcode_kh(ind) <= PUSH_DATA; + + if (ack_kh(ind) = '1') then + ack_dds(ind) <= '1'; + lookup_op_next <= '1'; + stage_next <= ADD_PAYLOAD; + cnt_next <= 1; + end if; + else + ack_dds(ind) <= '1'; + key_hash_next <= KEY_HASH_NIL; + stage_next <= SKIP; + return_stage_next <= PUSH_KEY_HASH; + end if; + when WAIT_FOR_ACKNOWLEDGEMENTS => + -- NOTE: In case of BEST_EFFORT the RTPS Writer still manually ACK the Samples, so we do not handle this case differently here. + ack_dds(ind) <= '1'; + ack_wait_next(ind) <= '1'; + tmp_dw := time + max_wait_dds(ind); + timeout_time_next(ind) <= tmp_dw; + + if (tmp_dw < timeout_check_time) then + timeout_check_time_next <= tmp_dw; + end if; + when GET_OFFERED_DEADLINE_MISSED_STATUS => + ack_dds(ind) <= '1'; + stage_next <= GET_OFFERED_DEADLINE_MISSED_STATUS; + cnt_next <= 0; + when ASSERT_LIVELINESS => + -- Reset Liveliness + lease_deadline_next(ind) <= time + CONFIG_ARRAY_T(ind).LEASE_DURATION; + + ack_dds(ind) <= '1'; + stage_next <= ASSERT_LIVELINESS; + when GET_LIVELINESS_LOST_STATUS => + ack_dds(ind) <= '1'; + stage_next <= GET_LIVELINESS_LOST_STATUS; + cnt_next <= 0; + when others => + ack_dds(ind) <= '1'; + stage_next <= UNKNOWN_OPERATION_DDS; + end case; + end if; end if; when UNKNOWN_OPERATION_DDS => - done_dds <= '1'; - return_code_dds <= RETCODE_ILLEGAL_OPERATION; + done_dds(ind) <= '1'; + return_code_dds(ind) <= RETCODE_ILLEGAL_OPERATION; -- DONE stage_next <= IDLE; when UNKNOWN_OPERATION_RTPS => - done_rtps <= '1'; - ret_rtps <= ERROR; + done_rtps(ind) <= '1'; + ret_rtps(ind) <= ERROR; -- DONE stage_next <= IDLE; when UNKNOWN_SEQ_NR => - done_rtps <= '1'; - ret_rtps <= INVALID; + done_rtps(ind) <= '1'; + ret_rtps(ind) <= INVALID; -- DONE stage_next <= IDLE; when ASSERT_LIVELINESS => -- Propagate Liveliness Assertion - liveliness_assertion <= '1'; + liveliness_assertion(ind) <= '1'; - done_dds <= '1'; - return_code_dds <= RETCODE_OK; + done_dds(ind) <= '1'; + return_code_dds(ind) <= RETCODE_OK; -- DONE stage_next <= IDLE; @@ -1166,7 +1343,7 @@ begin when 1 => sample_valid_in <= '1'; sample_addr <= cur_sample + SMF_SEQ_NR_OFFSET; - sample_write_data <= std_logic_vector(global_seq_nr(0)); + sample_write_data <= std_logic_vector(global_seq_nr(ind)(0)); -- Memory Flow Control Guard if (sample_ready_in = '1') then cnt_next <= cnt + 1; @@ -1175,7 +1352,7 @@ begin when 2 => sample_valid_in <= '1'; sample_addr <= cur_sample + SMF_SEQ_NR_OFFSET + 1; - sample_write_data <= std_logic_vector(global_seq_nr(1)); + sample_write_data <= std_logic_vector(global_seq_nr(ind)(1)); -- Memory Flow Control Guard if (sample_ready_in = '1') then cnt_next <= cnt + 1; @@ -1204,49 +1381,43 @@ begin end if; -- Memory Flow Control Guard if (sample_ready_in = '1') then - -- Synthesis Guard - if (LIFESPAN_QOS /= DURATION_INFINITE) then - cnt_next <= cnt + 1; - lifespan_next <= time + LIFESPAN_QOS; + if (CONFIG_ARRAY_T(ind).LIFESPAN_QOS /= DURATION_INFINITE) then + lifespan_next <= time + CONFIG_ARRAY_T(ind).LIFESPAN_QOS; else - cnt_next <= cnt + 3; -- Skip + lifespan_next <= TIME_INVALID; end if; + cnt_next <= cnt + 1; end if; -- Lifespan Deadline 1/2 when 5 => - -- Synthesis Guard - if (LIFESPAN_QOS /= DURATION_INFINITE) then - sample_valid_in <= '1'; - sample_addr <= cur_sample + SMF_LIFESPAN_DEADLINE_OFFSET; - sample_write_data <= std_logic_vector(lifespan(0)); - -- Memory Flow Control Guard - if (sample_ready_in = '1') then - cnt_next <= cnt + 1; - end if; + sample_valid_in <= '1'; + sample_addr <= cur_sample + SMF_LIFESPAN_DEADLINE_OFFSET; + sample_write_data <= std_logic_vector(lifespan(0)); + -- Memory Flow Control Guard + if (sample_ready_in = '1') then + cnt_next <= cnt + 1; end if; -- Lifespan Deadline 2/2 when 6 => - -- Synthesis Guard - if (LIFESPAN_QOS /= DURATION_INFINITE) then - sample_valid_in <= '1'; - sample_addr <= cur_sample + SMF_LIFESPAN_DEADLINE_OFFSET + 1; - sample_write_data <= std_logic_vector(lifespan(1)); - -- Memory Flow Control Guard - if (sample_ready_in = '1') then - cnt_next <= cnt + 1; - end if; + sample_valid_in <= '1'; + sample_addr <= cur_sample + SMF_LIFESPAN_DEADLINE_OFFSET + 1; + sample_write_data <= std_logic_vector(lifespan(1)); + -- Memory Flow Control Guard + if (sample_ready_in = '1') then + cnt_next <= cnt + 1; end if; -- Payload Address when 7 => - assert (empty_payload_list_head /= PAYLOAD_MEMORY_MAX_ADDRESS) severity FAILURE; + assert (empty_payload_list_head(ind) /= PAYLOAD_MEMORY_MAX_ADDRESS) severity FAILURE; + sample_valid_in <= '1'; sample_addr <= cur_sample + SMF_PAYLOAD_ADDR_OFFSET; - sample_write_data <= std_logic_vector(resize(empty_payload_list_head, WORD_WIDTH)); - cur_payload_next <= empty_payload_list_head; + sample_write_data <= std_logic_vector(resize(empty_payload_list_head(ind), WORD_WIDTH)); + cur_payload_next <= empty_payload_list_head(ind); -- Memory Flow Control Guard if (sample_ready_in = '1') then -- Key Hash needs to be calculated - if (WITH_KEY and instance_handle = HANDLE_NIL) then + if (CONFIG_ARRAY_T(ind).WITH_KEY and instance_handle = HANDLE_NIL) then cnt_next <= cnt + 1; else stage_next <= ADD_PAYLOAD; @@ -1256,21 +1427,20 @@ begin end if; -- Initiate KH Operation when 8 => - -- Synthesis Guard - if (WITH_KEY) then - start_kh <= '1'; - -- Payload is Serialized Key - if (sample_status_info(SSI_DISPOSED_FLAG) = '1' or sample_status_info(SSI_UNREGISTERED_FLAG) = '1' or sample_status_info(SSI_FILTERED_FLAG) = '1') then - opcode_kh <= PUSH_SERIALIZED_KEY; - else - opcode_kh <= PUSH_DATA; - end if; - - if (ack_kh = '1') then - stage_next <= ADD_PAYLOAD; - cnt_next <= 0; - cnt2_next <= 1; - end if; + assert (CONFIG_ARRAY_T(ind).WITH_KEY) severity FAILURE; + + start_kh(ind) <= '1'; + -- Payload is Serialized Key + if (sample_status_info(SSI_DISPOSED_FLAG) = '1' or sample_status_info(SSI_UNREGISTERED_FLAG) = '1' or sample_status_info(SSI_FILTERED_FLAG) = '1') then + opcode_kh(ind) <= PUSH_SERIALIZED_KEY; + else + opcode_kh(ind) <= PUSH_DATA; + end if; + + if (ack_kh(ind) = '1') then + stage_next <= ADD_PAYLOAD; + cnt_next <= 0; + cnt2_next <= 1; end if; when others => null; @@ -1282,29 +1452,29 @@ begin -- Push to memory when 0 => -- Input Guard - if (valid_in_dds = '1') then + if (valid_in_dds(ind) = '1') then payload_valid_in <= '1'; payload_addr <= cur_payload + cnt2; - payload_write_data <= data_in_dds; + payload_write_data <= data_in_dds(ind); -- Memory Control Flow Guard if (payload_ready_in = '1') then -- Key Hash needs to be calculated - if (WITH_KEY and instance_handle = HANDLE_NIL) then + if (CONFIG_ARRAY_T(ind).WITH_KEY and instance_handle = HANDLE_NIL) then cnt_next <= cnt + 1; else - ready_in_dds <= '1'; + ready_in_dds(ind) <= '1'; -- End of Payload - if (last_word_in_dds = '1') then + if (last_word_in_dds(ind) = '1') then -- End of Payload Slot - if (cnt2 = PAYLOAD_FRAME_SIZE-1) then - stage_next <= FILTER_STAGE; + if (cnt2 = PAYLOAD_FRAME_SIZE(ind)-1) then + stage_next <= INITIATE_INSTANCE_SEARCH; else stage_next <= ALIGN_PAYLOAD; cnt_next <= 0; end if; else -- End of Payload Slot - if (cnt2 = PAYLOAD_FRAME_SIZE-1) then + if (cnt2 = PAYLOAD_FRAME_SIZE(ind)-1) then stage_next <= NEXT_PAYLOAD_SLOT; cnt_next <= 0; else @@ -1317,54 +1487,53 @@ begin end if; -- Push to KH when 1 => - -- Synthesis Guard - if (WITH_KEY) then - -- Input Guard - if (valid_in_dds = '1') then + assert (CONFIG_ARRAY_T(ind).WITH_KEY) severity FAILURE; + + -- Input Guard + if (valid_in_dds(ind) = '1') then + + valid_out_kh(ind) <= '1'; + data_out_kh(ind) <= data_in_dds(ind); - valid_out_kh <= '1'; - data_out_kh <= data_in_dds; - - -- Output Guard - if (ready_out_kh = '1') then - ready_in_dds <= '1'; - -- Operation does not have Payload to store - if (sample_status_info(SSI_DATA_FLAG) = '0') then - -- End of Payload - if (last_word_in_dds = '1') then - last_word_out_kh <= '1'; + -- Output Guard + if (ready_out_kh(ind) = '1') then + ready_in_dds(ind) <= '1'; + -- Operation does not have Payload to store + if (sample_status_info(SSI_DATA_FLAG) = '0') then + -- End of Payload + if (last_word_in_dds(ind) = '1') then + last_word_out_kh(ind) <= '1'; + -- Fetch the Key Hash + stage_next <= GET_KEY_HASH; + cnt_next <= 0; + cnt2_next <= 0; + else + -- Next Word + cnt_next <= 1; -- Same Sub-state + end if; + else + -- End of Payload + if (last_word_in_dds(ind) = '1') then + last_word_out_kh(ind) <= '1'; + -- End of Payload Slot + if (cnt2 = PAYLOAD_FRAME_SIZE(ind)-1) then -- Fetch the Key Hash stage_next <= GET_KEY_HASH; cnt_next <= 0; cnt2_next <= 0; else - -- Next Word - cnt_next <= 1; -- Same Sub-state + stage_next <= ALIGN_PAYLOAD; + cnt_next <= 0; end if; else - -- End of Payload - if (last_word_in_dds = '1') then - last_word_out_kh <= '1'; - -- End of Payload Slot - if (cnt2 = PAYLOAD_FRAME_SIZE-1) then - -- Fetch the Key Hash - stage_next <= GET_KEY_HASH; - cnt_next <= 0; - cnt2_next <= 0; - else - stage_next <= ALIGN_PAYLOAD; - cnt_next <= 0; - end if; + -- End of Payload Slot + if (cnt2 = PAYLOAD_FRAME_SIZE(ind)-1) then + stage_next <= NEXT_PAYLOAD_SLOT; + cnt_next <= 0; else - -- End of Payload Slot - if (cnt2 = PAYLOAD_FRAME_SIZE-1) then - stage_next <= NEXT_PAYLOAD_SLOT; - cnt_next <= 0; - else - -- Next Word - cnt_next <= 0; - cnt2_next <= cnt2 + 1; - end if; + -- Next Word + cnt_next <= 0; + cnt2_next <= cnt2 + 1; end if; end if; end if; @@ -1400,7 +1569,7 @@ begin cnt_next <= 0; return_code_latch_next <= RETCODE_OUT_OF_RESOURCES; -- Abort Key Hash Generation - abort_kh <= '1'; + abort_kh(ind) <= '1'; else -- Latch next Payload Slot and Continue cur_payload_next <= resize(unsigned(payload_read_data), PAYLOAD_MEMORY_ADDR_WIDTH); @@ -1428,187 +1597,182 @@ begin -- Store Payload End Offset when 1 => payload_valid_in <= '1'; - payload_addr <= cur_payload + PAYLOAD_FRAME_SIZE-1; + payload_addr <= cur_payload + PAYLOAD_FRAME_SIZE(ind)-1; payload_write_data <= std_logic_vector(to_unsigned(cnt2, WORD_WIDTH)); -- Memory Control Flow Guard if (payload_ready_in = '1') then - if (WITH_KEY and instance_handle = HANDLE_NIL) then + if (CONFIG_ARRAY_T(ind).WITH_KEY and instance_handle = HANDLE_NIL) then stage_next <= GET_KEY_HASH; cnt_next <= 0; cnt2_next <= 0; else - stage_next <= FILTER_STAGE; + stage_next <= INITIATE_INSTANCE_SEARCH; end if; end if; when others => null; end case; when GET_KEY_HASH => - -- Synthesis Guard - if (WITH_KEY) then - case (cnt) is - -- Initiate READ Operation - when 0 => - start_kh <= '1'; - opcode_kh <= READ_KEY_HASH; - - if (ack_kh = '1') then - cnt_next <= cnt + 1; - end if; - -- READ Key Hash - when 1 => - ready_in_kh <= '1'; - - if (valid_in_kh = '1') then - cnt2_next <= cnt2 + 1; - - -- Latch Key Hash - key_hash_next(cnt2) <= data_in_kh; - - -- Exit Condition - if (last_word_in_kh = '1') then - -- DONE - stage_next <= INITIATE_INSTANCE_SEARCH; - end if; - end if; - when others => - null; - end case; - end if; - when INITIATE_INSTANCE_SEARCH => - -- Synthesis Guard - if (WITH_KEY) then - -- Memory Operation Guard - if (inst_op_done = '1') then - inst_op_start <= '1'; - inst_opcode <= SEARCH_INSTANCE; - inst_r.key_hash <= key_hash; - inst_r.field_flags <= IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_ACK_CNT_FLAG; + assert (CONFIG_ARRAY_T(ind).WITH_KEY) severity FAILURE; + + case (cnt) is + -- Initiate READ Operation + when 0 => + start_kh(ind) <= '1'; + opcode_kh(ind) <= READ_KEY_HASH; - -- Register Operation in Progress - if (WITH_KEY and register_op = '1') then - stage_next <= REGISTER_OPERATION; - -- Lookup Operation in Progress - elsif (WITH_KEY and lookup_op = '1') then - stage_next <= LOOKUP_OPERATION; - -- Cache Change not yet Stored - elsif (instance_handle /= HANDLE_NIL) then - stage_next <= ADD_SAMPLE_INFO; - cnt_next <= 0; - else - stage_next <= FILTER_STAGE; + if (ack_kh(ind) = '1') then + cnt_next <= cnt + 1; end if; + -- READ Key Hash + when 1 => + ready_in_kh(ind) <= '1'; + + if (valid_in_kh(ind) = '1') then + cnt2_next <= cnt2 + 1; + + -- Latch Key Hash + key_hash_next(cnt2) <= data_in_kh(ind); + + -- Exit Condition + if (last_word_in_kh(ind) = '1') then + -- DONE + stage_next <= INITIATE_INSTANCE_SEARCH; + end if; + end if; + when others => + null; + end case; + when INITIATE_INSTANCE_SEARCH => + -- Memory Operation Guard + if (inst_op_done = '1') then + inst_op_start <= '1'; + inst_opcode <= SEARCH_INSTANCE; + inst_r.i <= ind; + inst_r.key_hash <= key_hash; + inst_r.field_flags <= IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_ACK_CNT_FLAG; + + -- Register Operation in Progress + if (register_op = '1') then + stage_next <= REGISTER_OPERATION; + -- Lookup Operation in Progress + elsif (lookup_op = '1') then + stage_next <= LOOKUP_OPERATION; + else + stage_next <= FILTER_STAGE; end if; end if; when REGISTER_OPERATION => - -- Synthesis Guard - if (WITH_KEY) then - -- Wait for Instance Search to finish - if (inst_op_done = '1') then - -- Instance already in Memory - if (inst_data.addr /= INSTANCE_MEMORY_MAX_ADDRESS) then - assert stable(clk, check_mask(inst_data.field_flags, IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_ACK_CNT_FLAG)) severity FAILURE; + assert (CONFIG_ARRAY_T(ind).WITH_KEY) severity FAILURE; + + -- Wait for Instance Search to finish + if (inst_op_done = '1') then + -- Instance already in Memory + if (inst_data.addr /= INSTANCE_MEMORY_MAX_ADDRESS) then + assert stable(clk, inst_data.i = ind and check_mask(inst_data.field_flags, IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_ACK_CNT_FLAG)) severity FAILURE; + + -- Accept Registration + stage_next <= PUSH_KEY_HASH; + + -- Instance is Unregistered + if (inst_data.status_info(ISI_UNREGISTERED_FLAG) = '1') then + -- Re-register Instance + inst_op_start <= '1'; + inst_opcode <= UPDATE_INSTANCE; + inst_r.i <= ind; + inst_r.addr <= inst_data.addr; + inst_r.field_flags <= IMF_STATUS_FLAG; + inst_r.status_info <= inst_data.status_info; + inst_r.status_info(ISI_UNREGISTERED_FLAG) <= '0'; + -- Update Stale Instance Count + if (inst_data.sample_cnt = inst_data.ack_cnt) then + stale_inst_cnt_next(ind) <= stale_inst_cnt(ind) - 1; + end if; + end if; + else + -- RESOURCE_LIMITS_QOS (MAX_INSTANCES) (Instance Memory Full) + if (inst_empty_head(ind) = INSTANCE_MEMORY_MAX_ADDRESS) then + -- Stale Instances are available + if (stale_inst_cnt(ind) /= 0) then + + -- Remove Stale and insert new Instance + inst_op_start <= '1'; + inst_opcode <= GET_INSTANCE; + inst_r.i <= ind; + inst_r.addr <= inst_occupied_head(ind); + inst_r.field_flags <= IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_ACK_CNT_FLAG; + stage_next <= REMOVE_STALE_INSTANCE; + cnt_next <= 0; + else + -- Reject Registration + key_hash_next <= KEY_HASH_NIL; + stage_next <= PUSH_KEY_HASH; + end if; + else -- Accept Registration stage_next <= PUSH_KEY_HASH; - -- Instance is Unregistered - if (inst_data.status_info(ISI_UNREGISTERED_FLAG) = '1') then - -- Re-register Instance - inst_op_start <= '1'; - inst_opcode <= UPDATE_INSTANCE; - inst_r.addr <= inst_data.addr; - inst_r.field_flags <= IMF_STATUS_FLAG; - inst_r.status_info <= inst_data.status_info; - inst_r.status_info(ISI_UNREGISTERED_FLAG) <= '0'; - - -- Update Stale Instance Count - if (inst_data.sample_cnt = inst_data.ack_cnt) then - stale_inst_cnt_next <= stale_inst_cnt - 1; - end if; - end if; - else - -- RESOURCE_LIMITS_QOS (MAX_INSTANCES) (Instance Memory Full) - if (inst_empty_head = INSTANCE_MEMORY_MAX_ADDRESS) then - -- Stale Instances are available - if (stale_inst_cnt /= 0) then - - -- Remove Stale and insert new Instance - inst_op_start <= '1'; - inst_opcode <= GET_INSTANCE; - inst_r.addr <= inst_occupied_head; - inst_r.field_flags <= IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_ACK_CNT_FLAG; - stage_next <= REMOVE_STALE_INSTANCE; - cnt_next <= 0; - else - -- Reject Registration - key_hash_next <= KEY_HASH_NIL; - stage_next <= PUSH_KEY_HASH; - end if; - else - -- Accept Registration - stage_next <= PUSH_KEY_HASH; - - -- Insert New Instance - inst_op_start <= '1'; - inst_opcode <= INSERT_INSTANCE; - inst_r.key_hash <= key_hash; - end if; + -- Insert New Instance + inst_op_start <= '1'; + inst_opcode <= INSERT_INSTANCE; + inst_r.i <= ind; + inst_r.key_hash <= key_hash; end if; end if; end if; when LOOKUP_OPERATION => - -- Synthesis Guard - if (WITH_KEY) then - -- Wait for Instance Search to finish - if (inst_op_done = '1') then - -- Instance Found - if (inst_data.addr /= INSTANCE_MEMORY_MAX_ADDRESS) then - stage_next <= PUSH_KEY_HASH; - else - -- Return Special Value - key_hash_next <= KEY_HASH_NIL; - stage_next <= PUSH_KEY_HASH; - end if; + assert (CONFIG_ARRAY_T(ind).WITH_KEY) severity FAILURE; + + -- Wait for Instance Search to finish + if (inst_op_done = '1') then + -- Instance Found + if (inst_data.addr /= INSTANCE_MEMORY_MAX_ADDRESS) then + stage_next <= PUSH_KEY_HASH; + else + -- Return Special Value + key_hash_next <= KEY_HASH_NIL; + stage_next <= PUSH_KEY_HASH; end if; end if; when PUSH_KEY_HASH => - done_dds <= '1'; - instance_handle_out_dds <= key_hash; + done_dds(ind) <= '1'; + instance_handle_out_dds(ind) <= key_hash; -- DONE - stage_next <= IDLE; + stage_next <= IDLE; when FILTER_STAGE => -- Precondition: cur_sample set, inst_data set (IMF_SAMPLE_CNT_FLAG, IMF_ACK_CNT_FLAG) -- Wait for Instance Search to finish - if (not WITH_KEY or inst_op_done = '1') then + if (inst_op_done = '1') then -- Instance Found - if (not WITH_KEY or inst_data.addr /= INSTANCE_MEMORY_MAX_ADDRESS) then - assert (not WITH_KEY or stable(clk,check_mask(inst_data.field_flags, IMF_SAMPLE_CNT_FLAG or IMF_ACK_CNT_FLAG))) severity FAILURE; + if (inst_data.addr /= INSTANCE_MEMORY_MAX_ADDRESS) then + assert (stable(clk, inst_data.i = ind and check_mask(inst_data.field_flags, IMF_SAMPLE_CNT_FLAG or IMF_ACK_CNT_FLAG))) severity FAILURE; -- Latch Instance Pointer cur_inst_next <= inst_data.addr; -- RESOURCE_LIMITS_QOS (MAX_SAMPLES_PER_INSTANCE) - if (WITH_KEY and MAX_SAMPLES_PER_INSTANCE /= LENGTH_UNLIMITED and inst_data.sample_cnt = unsigned(MAX_SAMPLES_PER_INSTANCE)) then - -- Synthesis Guard - if (HISTORY_QOS = KEEP_ALL_HISTORY_QOS) then + if (CONFIG_ARRAY_T(ind).MAX_SAMPLES_PER_INSTANCE /= LENGTH_UNLIMITED and inst_data.sample_cnt = unsigned(CONFIG_ARRAY_T(ind).MAX_SAMPLES_PER_INSTANCE)) then + if (CONFIG_ARRAY_T(ind).HISTORY_QOS = KEEP_ALL_HISTORY_QOS) then -- No ACKed Instance Samples exist if (inst_data.ack_cnt = 0) then -- Reject Change - done_dds <= '1'; - return_code_dds <= RETCODE_OUT_OF_RESOURCES; - stage_next <= IDLE; + done_dds(ind) <= '1'; + return_code_dds(ind) <= RETCODE_OUT_OF_RESOURCES; + stage_next <= IDLE; else -- Accept Change (Remove Oldest ACKed Instance Sample) remove_oldest_inst_sample_next <= '1'; remove_ack_sample_next <= '1'; - done_dds <= '1'; - return_code_dds <= RETCODE_OK; - stage_next <= UPDATE_INSTANCE; + done_dds(ind) <= '1'; + return_code_dds(ind) <= RETCODE_OK; + stage_next <= UPDATE_INSTANCE; end if; - else -- HISTORY_QOS = KEEP_LAST_HISTORY_QOS + else + assert (CONFIG_ARRAY_T(ind).HISTORY_QOS = KEEP_LAST_HISTORY_QOS) severity FAILURE; + -- Accept Change (Remove Oldest (ACKed) Instance Sample) remove_oldest_inst_sample_next <= '1'; if (inst_data.ack_cnt /= 0) then @@ -1616,150 +1780,157 @@ begin else remove_ack_sample_next <= '0'; end if; - done_dds <= '1'; - return_code_dds <= RETCODE_OK; - stage_next <= UPDATE_INSTANCE; + done_dds(ind) <= '1'; + return_code_dds(ind) <= RETCODE_OK; + stage_next <= UPDATE_INSTANCE; end if; -- RESOURCE_LIMITS_QOS (MAX_SAMPLES) - elsif (empty_sample_list_head = empty_sample_list_tail) then - -- Synthesis Guard - if (HISTORY_QOS = KEEP_ALL_HISTORY_QOS) then + elsif (empty_sample_list_head(ind) = empty_sample_list_tail(ind)) then + if (CONFIG_ARRAY_T(ind).HISTORY_QOS = KEEP_ALL_HISTORY_QOS) then -- No ACKed Samples exist - if (global_ack_cnt = 0) then + if (global_ack_cnt(ind) = 0) then -- Reject Change - done_dds <= '1'; - return_code_dds <= RETCODE_OUT_OF_RESOURCES; - stage_next <= IDLE; + done_dds(ind) <= '1'; + return_code_dds(ind) <= RETCODE_OUT_OF_RESOURCES; + stage_next <= IDLE; else -- Accept Change (Remove Oldest ACKed Sample) remove_oldest_sample_next <= '1'; remove_ack_sample_next <= '1'; - done_dds <= '1'; - return_code_dds <= RETCODE_OK; - stage_next <= UPDATE_INSTANCE; + done_dds(ind) <= '1'; + return_code_dds(ind) <= RETCODE_OK; + stage_next <= UPDATE_INSTANCE; end if; - else -- HISTORY_QOS = KEEP_LAST_HISTORY_QOS + else + assert (CONFIG_ARRAY_T(ind).HISTORY_QOS = KEEP_LAST_HISTORY_QOS) severity FAILURE; + -- Accept Change (Remove Oldest (ACKed) Sample) remove_oldest_sample_next <= '1'; - if (global_ack_cnt /= 0) then + if (global_ack_cnt(ind) /= 0) then remove_ack_sample_next <= '1'; else remove_ack_sample_next <= '0'; end if; - done_dds <= '1'; - return_code_dds <= RETCODE_OK; - stage_next <= UPDATE_INSTANCE; + done_dds(ind) <= '1'; + return_code_dds(ind) <= RETCODE_OK; + stage_next <= UPDATE_INSTANCE; end if; else -- Accept Change - done_dds <= '1'; - return_code_dds <= RETCODE_OK; - stage_next <= UPDATE_INSTANCE; + done_dds(ind) <= '1'; + return_code_dds(ind) <= RETCODE_OK; + stage_next <= UPDATE_INSTANCE; end if; - else -- (WITH_KEY) + else -- Latch Instance Pointer - cur_inst_next <= inst_empty_head; + cur_inst_next <= inst_empty_head(ind); -- Provided Instance Handle Invalid if (instance_handle /= HANDLE_NIL) then -- Invalid Operation - done_dds <= '1'; - return_code_dds <= RETCODE_BAD_PARAMETER; + done_dds(ind) <= '1'; + return_code_dds(ind) <= RETCODE_BAD_PARAMETER; -- DONE stage_next <= IDLE; -- Ignore Unregister Operation on Unknown Instance elsif (sample_status_info(SSI_UNREGISTERED_FLAG) = '1') then -- Drop Change - done_dds <= '1'; - return_code_dds <= RETCODE_OK; + done_dds(ind) <= '1'; + return_code_dds(ind) <= RETCODE_OK; -- DONE stage_next <= IDLE; -- RESOURCE_LIMITS_QOS (MAX_INSTANCES) (Instance Memory Full) - elsif (inst_empty_head = INSTANCE_MEMORY_MAX_ADDRESS) then + elsif (inst_empty_head(ind) = INSTANCE_MEMORY_MAX_ADDRESS) then + assert (stable(clk,CONFIG_ARRAY_T(ind).WITH_KEY)) severity FAILURE; + -- No Stale Instances available - if (stale_inst_cnt = 0) then + if (stale_inst_cnt(ind) = 0) then -- Reject Change - done_dds <= '1'; - return_code_dds <= RETCODE_OUT_OF_RESOURCES; - stage_next <= IDLE; + done_dds(ind) <= '1'; + return_code_dds(ind) <= RETCODE_OUT_OF_RESOURCES; + stage_next <= IDLE; -- RESOURCE_LIMITS_QOS (MAX_SAMPLES) - elsif (empty_sample_list_head = empty_sample_list_tail) then - -- Synthesis Guard - if (HISTORY_QOS = KEEP_ALL_HISTORY_QOS) then + elsif (empty_sample_list_head(ind) = empty_sample_list_tail(ind)) then + if (CONFIG_ARRAY_T(ind).HISTORY_QOS = KEEP_ALL_HISTORY_QOS) then -- No ACKed Samples exist - if (global_ack_cnt = 0) then + if (global_ack_cnt(ind) = 0) then -- Reject Change - done_dds <= '1'; - return_code_dds <= RETCODE_OUT_OF_RESOURCES; - stage_next <= IDLE; + done_dds(ind) <= '1'; + return_code_dds(ind) <= RETCODE_OUT_OF_RESOURCES; + stage_next <= IDLE; else -- Accept Change (Remove Oldest ACKed Sample) remove_oldest_sample_next <= '1'; remove_ack_sample_next <= '1'; - done_dds <= '1'; - return_code_dds <= RETCODE_OK; + done_dds(ind) <= '1'; + return_code_dds(ind) <= RETCODE_OK; -- Remove Stale and insert new Instance inst_op_start <= '1'; inst_opcode <= GET_INSTANCE; - inst_r.addr <= inst_occupied_head; + inst_r.i <= ind; + inst_r.addr <= inst_occupied_head(ind); inst_r.field_flags <= IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_ACK_CNT_FLAG; stage_next <= REMOVE_STALE_INSTANCE; cnt_next <= 0; end if; - else -- HISTORY_QOS = KEEP_LAST_HISTORY_QOS + else + assert (CONFIG_ARRAY_T(ind).HISTORY_QOS = KEEP_LAST_HISTORY_QOS) severity FAILURE; + -- Accept Change (Remove Oldest (ACKed) Sample) remove_oldest_sample_next <= '1'; - if (global_ack_cnt /= 0) then + if (global_ack_cnt(ind) /= 0) then remove_ack_sample_next <= '1'; else remove_ack_sample_next <= '0'; end if; - done_dds <= '1'; - return_code_dds <= RETCODE_OK; + done_dds(ind) <= '1'; + return_code_dds(ind) <= RETCODE_OK; -- Remove Stale and insert new Instance inst_op_start <= '1'; inst_opcode <= GET_INSTANCE; - inst_r.addr <= inst_occupied_head; + inst_r.i <= ind; + inst_r.addr <= inst_occupied_head(ind); inst_r.field_flags <= IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_ACK_CNT_FLAG; stage_next <= REMOVE_STALE_INSTANCE; cnt_next <= 0; end if; else -- Accept Change - done_dds <= '1'; - return_code_dds <= RETCODE_OK; + done_dds(ind) <= '1'; + return_code_dds(ind) <= RETCODE_OK; -- Remove Stale and insert new Instance inst_op_start <= '1'; inst_opcode <= GET_INSTANCE; - inst_r.addr <= inst_occupied_head; + inst_r.i <= ind; + inst_r.addr <= inst_occupied_head(ind); inst_r.field_flags <= IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_ACK_CNT_FLAG; stage_next <= REMOVE_STALE_INSTANCE; cnt_next <= 0; end if; else -- RESOURCE_LIMITS_QOS (MAX_SAMPLES) - if (empty_sample_list_head = empty_sample_list_tail) then - -- Synthesis Guard - if (HISTORY_QOS = KEEP_ALL_HISTORY_QOS) then + if (empty_sample_list_head(ind) = empty_sample_list_tail(ind)) then + if (CONFIG_ARRAY_T(ind).HISTORY_QOS = KEEP_ALL_HISTORY_QOS) then -- No ACKed Samples exist - if (global_ack_cnt = 0) then + if (global_ack_cnt(ind) = 0) then -- Reject Change - done_dds <= '1'; - return_code_dds <= RETCODE_OUT_OF_RESOURCES; - stage_next <= IDLE; + done_dds(ind) <= '1'; + return_code_dds(ind) <= RETCODE_OUT_OF_RESOURCES; + stage_next <= IDLE; else -- Accept Change (Remove Oldest ACKed Sample) remove_oldest_sample_next <= '1'; remove_ack_sample_next <= '1'; - done_dds <= '1'; - return_code_dds <= RETCODE_OK; + done_dds(ind) <= '1'; + return_code_dds(ind) <= RETCODE_OK; -- Insert New Instance inst_op_start <= '1'; inst_opcode <= INSERT_INSTANCE; + inst_r.i <= ind; inst_r.key_hash <= key_hash; inst_r.status_info <= (ISI_LIVELINESS_FLAG => '1', others => '0'); inst_r.sample_cnt <= to_unsigned(1, WORD_WIDTH); @@ -1768,20 +1939,23 @@ begin stage_next <= FINALIZE_PAYLOAD; cnt_next <= 0; end if; - else -- HISTORY_QOS = KEEP_LAST_HISTORY_QOS + else + assert (CONFIG_ARRAY_T(ind).HISTORY_QOS = KEEP_LAST_HISTORY_QOS) severity FAILURE; + -- Accept Change (Remove Oldest (ACKed) Sample) remove_oldest_sample_next <= '1'; - if (global_ack_cnt /= 0) then + if (global_ack_cnt(ind) /= 0) then remove_ack_sample_next <= '1'; else remove_ack_sample_next <= '0'; end if; - done_dds <= '1'; - return_code_dds <= RETCODE_OK; + done_dds(ind) <= '1'; + return_code_dds(ind) <= RETCODE_OK; -- Insert New Instance inst_op_start <= '1'; inst_opcode <= INSERT_INSTANCE; + inst_r.i <= ind; inst_r.key_hash <= key_hash; inst_r.status_info <= (ISI_LIVELINESS_FLAG => '1', others => '0'); inst_r.sample_cnt <= to_unsigned(1, WORD_WIDTH); @@ -1792,12 +1966,13 @@ begin end if; else -- Accept Change - done_dds <= '1'; - return_code_dds <= RETCODE_OK; + done_dds(ind) <= '1'; + return_code_dds(ind) <= RETCODE_OK; -- Insert New Instance inst_op_start <= '1'; inst_opcode <= INSERT_INSTANCE; + inst_r.i <= ind; inst_r.key_hash <= key_hash; inst_r.status_info <= (ISI_LIVELINESS_FLAG => '1', others => '0'); inst_r.sample_cnt <= to_unsigned(1, WORD_WIDTH); @@ -1813,45 +1988,32 @@ begin -- Precondition: inst_data set (IMF_STATUS_FLAG, IMF_SAMPLE_CNT_FLAG, IMF_ACK_CNT_FLAG) -- Memory Operation Guard - if (not WITH_KEY or inst_op_done = '1') then - -- Synthesis Guard - if (WITH_KEY) then - assert (inst_data.addr /= INSTANCE_MEMORY_MAX_ADDRESS) severity FAILURE; - assert stable(clk,check_mask(inst_data.field_flags, IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_ACK_CNT_FLAG)) severity FAILURE; - - inst_op_start <= '1'; - inst_opcode <= UPDATE_INSTANCE; - inst_r.addr <= inst_data.addr; - inst_r.field_flags <= IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG; - inst_r.status_info <= inst_data.status_info; - inst_r.status_info(ISI_LIVELINESS_FLAG) <= '1'; - if (sample_status_info(SSI_DISPOSED_FLAG) = '0' and sample_status_info(SSI_UNREGISTERED_FLAG) = '0') then - inst_r.status_info(ISI_DISPOSED_FLAG) <= '0'; - inst_r.status_info(ISI_UNREGISTERED_FLAG) <= '0'; - elsif (sample_status_info(SSI_DISPOSED_FLAG) = '1') then - inst_r.status_info(ISI_DISPOSED_FLAG) <= '1'; - elsif (sample_status_info(SSI_UNREGISTERED_FLAG) = '1') then - inst_r.status_info(ISI_UNREGISTERED_FLAG) <= '1'; - end if; - inst_r.sample_cnt <= inst_data.sample_cnt + 1; - - -- Update Stale Instance Count - -- NOTE: We enter this state only when we have a new sample, so an instance cannot turn stale, but only - -- become relevant again. - if (inst_data.status_info(ISI_UNREGISTERED_FLAG) = '1' and inst_data.sample_cnt = inst_data.ack_cnt) then - stale_inst_cnt_next <= stale_inst_cnt - 1; - end if; - else - if (sample_status_info(SSI_DISPOSED_FLAG) = '0' and sample_status_info(SSI_UNREGISTERED_FLAG) = '0') then - inst_data_next2.status_info(ISI_DISPOSED_FLAG) <= '0'; - inst_data_next2.status_info(ISI_UNREGISTERED_FLAG) <= '0'; - elsif (sample_status_info(SSI_DISPOSED_FLAG) = '1') then - inst_data_next2.status_info(ISI_DISPOSED_FLAG) <= '1'; - elsif (sample_status_info(SSI_UNREGISTERED_FLAG) = '1') then - inst_data_next2.status_info(ISI_UNREGISTERED_FLAG) <= '1'; - end if; - inst_data_next2.status_info(ISI_LIVELINESS_FLAG) <= '1'; - inst_data_next2.sample_cnt <= inst_data.sample_cnt + 1; + if (inst_op_done = '1') then + assert (inst_data.addr /= INSTANCE_MEMORY_MAX_ADDRESS) severity FAILURE; + assert stable(clk, inst_data.i = ind and check_mask(inst_data.field_flags, IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_ACK_CNT_FLAG)) severity FAILURE; + + inst_op_start <= '1'; + inst_opcode <= UPDATE_INSTANCE; + inst_r.i <= ind; + inst_r.addr <= inst_data.addr; + inst_r.field_flags <= IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG; + inst_r.status_info <= inst_data.status_info; + inst_r.status_info(ISI_LIVELINESS_FLAG) <= '1'; + if (sample_status_info(SSI_DISPOSED_FLAG) = '0' and sample_status_info(SSI_UNREGISTERED_FLAG) = '0') then + inst_r.status_info(ISI_DISPOSED_FLAG) <= '0'; + inst_r.status_info(ISI_UNREGISTERED_FLAG) <= '0'; + elsif (sample_status_info(SSI_DISPOSED_FLAG) = '1') then + inst_r.status_info(ISI_DISPOSED_FLAG) <= '1'; + elsif (sample_status_info(SSI_UNREGISTERED_FLAG) = '1') then + inst_r.status_info(ISI_UNREGISTERED_FLAG) <= '1'; + end if; + inst_r.sample_cnt <= inst_data.sample_cnt + 1; + + -- Update Stale Instance Count + -- NOTE: We enter this state only when we have a new sample, so an instance cannot turn stale, but only + -- become relevant again. + if (inst_data.status_info(ISI_UNREGISTERED_FLAG) = '1' and inst_data.sample_cnt = inst_data.ack_cnt) then + stale_inst_cnt_next(ind) <= stale_inst_cnt(ind) - 1; end if; stage_next <= FINALIZE_PAYLOAD; @@ -1889,10 +2051,10 @@ begin -- Memory Control Flow Guard if (payload_valid_out = '1') then -- Fix New Empty List Head - empty_payload_list_head_next <= resize(unsigned(payload_read_data), PAYLOAD_MEMORY_ADDR_WIDTH); + empty_payload_list_head_next(ind) <= resize(unsigned(payload_read_data), PAYLOAD_MEMORY_ADDR_WIDTH); stage_next <= FINALIZE_SAMPLE; - cur_sample_next <= empty_sample_list_head; + cur_sample_next <= empty_sample_list_head(ind); cnt_next <= 0; end if; when others => @@ -1910,13 +2072,9 @@ begin -- Memory Flow Control Guard if (sample_ready_in = '1') then -- Sample Memory Empty (No previous Sample) - if (newest_sample = SAMPLE_MEMORY_MAX_ADDRESS) then - assert (oldest_sample = SAMPLE_MEMORY_MAX_ADDRESS) severity FAILURE; - if (WITH_KEY) then - cnt_next <= cnt + 2; -- Skip Next Step - else - cnt_next <= cnt + 3; -- Skip Next 2 Steps - end if; + if (newest_sample(ind) = SAMPLE_MEMORY_MAX_ADDRESS) then + assert (oldest_sample(ind) = SAMPLE_MEMORY_MAX_ADDRESS) severity FAILURE; + cnt_next <= cnt + 2; -- SET INSTANCE POINTER else cnt_next <= cnt + 1; end if; @@ -1924,35 +2082,28 @@ begin -- SET Next Pointer (Previous Sample) when 1 => sample_valid_in <= '1'; - sample_addr <= newest_sample + SMF_NEXT_ADDR_OFFSET; + sample_addr <= newest_sample(ind) + SMF_NEXT_ADDR_OFFSET; sample_write_data <= std_logic_vector(resize(cur_sample, WORD_WIDTH)); -- Memory Flow Control Guard if (sample_ready_in = '1') then - if (WITH_KEY) then - cnt_next <= cnt + 1; - else - cnt_next <= cnt + 2; --Skip Next Step - end if; + cnt_next <= cnt + 1; end if; -- SET Instance Pointer when 2 => - -- Synthesis Guard - if (WITH_KEY) then - sample_valid_in <= '1'; - sample_addr <= cur_sample + SMF_INSTANCE_ADDR_OFFSET; - sample_write_data <= std_logic_vector(resize(cur_inst, WORD_WIDTH)); - - -- Memory Flow Control Guard - if (sample_ready_in = '1') then - cnt_next <= cnt + 1; - end if; + sample_valid_in <= '1'; + sample_addr <= cur_sample + SMF_INSTANCE_ADDR_OFFSET; + sample_write_data <= std_logic_vector(resize(cur_inst, WORD_WIDTH)); + + -- Memory Flow Control Guard + if (sample_ready_in = '1') then + cnt_next <= cnt + 1; end if; -- SET Previous Pointer when 3 => sample_valid_in <= '1'; sample_addr <= cur_sample + SMF_PREV_ADDR_OFFSET; - sample_write_data <= std_logic_vector(resize(newest_sample, WORD_WIDTH)); + sample_write_data <= std_logic_vector(resize(newest_sample(ind), WORD_WIDTH)); -- Memory Flow Control Guard if (sample_ready_in = '1') then @@ -1978,51 +2129,46 @@ begin if (sample_valid_out = '1') then -- Fix new Empty List Head - empty_sample_list_head_next <= resize(unsigned(sample_read_data), SAMPLE_MEMORY_ADDR_WIDTH); + empty_sample_list_head_next(ind) <= resize(unsigned(sample_read_data), SAMPLE_MEMORY_ADDR_WIDTH); -- Fix List Pointers - newest_sample_next <= cur_sample; - if (oldest_sample = SAMPLE_MEMORY_MAX_ADDRESS) then - oldest_sample_next <= cur_sample; + newest_sample_next(ind) <= cur_sample; + if (oldest_sample(ind) = SAMPLE_MEMORY_MAX_ADDRESS) then + oldest_sample_next(ind) <= cur_sample; end if; -- Increment Global Sequence Number - global_seq_nr_next <= global_seq_nr + 1; + global_seq_nr_next(ind) <= global_seq_nr(ind) + 1; -- Increment Global Sample Count - global_sample_cnt_next <= global_sample_cnt + 1; + global_sample_cnt_next(ind) <= global_sample_cnt(ind) + 1; + -- Trigger ACK Wait Check + ack_wait_check_next <= '1'; -- Signal Data Available - data_available_sig_next <= '1'; + data_available_sig_next(ind) <= '1'; - -- NOTE: This is needed to prevent the new Sample to be selected during an Orphan Sample + -- NOTE: This is needed to prevent the new Sample from being selected during an Orphan Sample -- Search, since the Dead Instance Address is the same as the new Sample Instance Address. -- Latch Sample Address new_sample_next <= cur_sample; -- Update Lifespan Check Time - if (LIFESPAN_QOS /= DURATION_INFINITE and lifespan < lifespan_time) then + if (CONFIG_ARRAY_T(ind).LIFESPAN_QOS /= DURATION_INFINITE and lifespan < lifespan_time) then lifespan_time_next <= lifespan; end if; if (remove_oldest_inst_sample = '1' or (remove_oldest_sample = '1' and remove_ack_sample = '1')) then - assert (oldest_sample /= SAMPLE_MEMORY_MAX_ADDRESS) severity FAILURE; + assert (oldest_sample(ind) /= SAMPLE_MEMORY_MAX_ADDRESS) severity FAILURE; - cur_sample_next <= oldest_sample; + cur_sample_next <= oldest_sample(ind); stage_next <= FIND_SAMPLE; cnt_next <= 0; elsif (remove_oldest_sample = '1') then - assert (oldest_sample /= SAMPLE_MEMORY_MAX_ADDRESS) severity FAILURE; + assert (oldest_sample(ind) /= SAMPLE_MEMORY_MAX_ADDRESS) severity FAILURE; - -- Synthesis Guard - if (WITH_KEY) then - stage_next <= GET_OLDEST_SAMPLE_INSTANCE; - cnt_next <= 0; - else - cur_sample_next <= oldest_sample; - stage_next <= REMOVE_SAMPLE; - cnt_next <= 0; - end if; + stage_next <= GET_OLDEST_SAMPLE_INSTANCE; + cnt_next <= 0; else -- DONE stage_next <= IDLE; @@ -2032,41 +2178,39 @@ begin null; end case; when GET_OLDEST_SAMPLE_INSTANCE => - -- Synthesis Guard - if (WITH_KEY) then - case (cnt) is - -- GET Instance Pointer (Oldest Sample) - when 0 => - sample_valid_in <= '1'; - sample_addr <= oldest_sample + SMF_INSTANCE_ADDR_OFFSET; - sample_read <= '1'; + case (cnt) is + -- GET Instance Pointer (Oldest Sample) + when 0 => + sample_valid_in <= '1'; + sample_addr <= oldest_sample(ind) + SMF_INSTANCE_ADDR_OFFSET; + sample_read <= '1'; + + -- Memory Flow Control Guard + if (sample_ready_in = '1') then + cnt_next <= cnt + 1; + end if; + -- READ Instance Pointer (Oldest Sample) + when 1 => + -- Memory Operation Guard + if (inst_op_done = '1') then + sample_ready_out <= '1'; -- Memory Flow Control Guard - if (sample_ready_in = '1') then - cnt_next <= cnt + 1; - end if; - -- READ Instance Pointer (Oldest Sample) - when 1 => - -- Memory Operation Guard - if (inst_op_done = '1') then - sample_ready_out <= '1'; + if (sample_valid_out = '1') then + inst_op_start <= '1'; + inst_opcode <= GET_INSTANCE; + inst_r.i <= ind; + inst_r.addr <= resize(unsigned(sample_read_data), INSTANCE_MEMORY_ADDR_WIDTH); + inst_r.field_flags <= IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_ACK_CNT_FLAG; - -- Memory Flow Control Guard - if (sample_valid_out = '1') then - inst_op_start <= '1'; - inst_opcode <= GET_INSTANCE; - inst_r.addr <= resize(unsigned(sample_read_data), INSTANCE_MEMORY_ADDR_WIDTH); - inst_r.field_flags <= IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_ACK_CNT_FLAG; - - cur_sample_next <= oldest_sample; - stage_next <= REMOVE_SAMPLE; - cnt_next <= 0; - end if; + cur_sample_next <= oldest_sample(ind); + stage_next <= REMOVE_SAMPLE; + cnt_next <= 0; end if; - when others => - null; - end case; - end if; + end if; + when others => + null; + end case; when FIND_SAMPLE => -- Precondition: cur_sample set @@ -2084,7 +2228,7 @@ begin else assert(remove_oldest_inst_sample = '1') severity FAILURE; - cnt_next <= cnt + 2; -- Skip Next Step + cnt_next <= cnt + 2; -- GET INSTANCE POINTER end if; end if; -- GET Status Info @@ -2095,25 +2239,17 @@ begin -- Memory Flow Control Guard if (sample_ready_in = '1') then - -- Synthesis Guard - if (WITH_KEY) then - cnt_next <= cnt + 1; - else - cnt_next <= cnt + 2; -- Skip Next Step - end if; + cnt_next <= cnt + 1; end if; -- GET Instance Pointer when 2 => - -- Synthesis Guard - if (WITH_KEY) then - sample_valid_in <= '1'; - sample_addr <= cur_sample + SMF_INSTANCE_ADDR_OFFSET; - sample_read <= '1'; - - -- Memory Flow Control Guard - if (sample_ready_in = '1') then - cnt_next <= cnt + 1; - end if; + sample_valid_in <= '1'; + sample_addr <= cur_sample + SMF_INSTANCE_ADDR_OFFSET; + sample_read <= '1'; + + -- Memory Flow Control Guard + if (sample_ready_in = '1') then + cnt_next <= cnt + 1; end if; -- READ Next Sample when 3 => @@ -2127,9 +2263,8 @@ begin cnt_next <= cnt + 1; else assert(remove_oldest_inst_sample = '1') severity FAILURE; - assert(WITH_KEY) severity FAILURE; - cnt_next <= cnt + 2; -- Skip Next Step + cnt_next <= cnt + 2; -- READ INSTANCE POINTER end if; end if; -- READ Status Info @@ -2140,12 +2275,7 @@ begin if (sample_valid_out = '1') then -- Sample is ACKed if (sample_read_data(SSI_ACK_FLAG) = '1') then - if (WITH_KEY) then - cnt_next <= cnt + 1; - else - stage_next <= REMOVE_SAMPLE; - cnt_next <= 0; - end if; + cnt_next <= cnt + 1; else -- Continue sample_abort_read <= '1'; @@ -2155,92 +2285,89 @@ begin end if; -- READ Instance Pointer when 5 => - -- Synthesis Guard - if (WITH_KEY) then - sample_ready_out <= '1'; - - -- Memory Flow Control Guard - if (sample_valid_out = '1') then - if (remove_oldest_sample = '1') then - inst_op_start <= '1'; - inst_opcode <= GET_INSTANCE; - inst_r.addr <= resize(unsigned(sample_read_data), INSTANCE_MEMORY_ADDR_WIDTH); - inst_r.field_flags <= IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_ACK_CNT_FLAG; - - stage_next <= REMOVE_SAMPLE; - cnt_next <= 0; - -- Oldest Instance Sample Found - elsif (resize(unsigned(sample_read_data),INSTANCE_MEMORY_ADDR_WIDTH) = cur_inst) then - -- NOTE: Instance Data already valid - stage_next <= REMOVE_SAMPLE; - cnt_next <= 0; - else - -- Continue - cur_sample_next <= next_sample; - cnt_next <= 0; - end if; + sample_ready_out <= '1'; + + -- Memory Flow Control Guard + if (sample_valid_out = '1') then + if (remove_oldest_sample = '1') then + inst_op_start <= '1'; + inst_opcode <= GET_INSTANCE; + inst_r.i <= ind; + inst_r.addr <= resize(unsigned(sample_read_data), INSTANCE_MEMORY_ADDR_WIDTH); + inst_r.field_flags <= IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_ACK_CNT_FLAG; + + stage_next <= REMOVE_SAMPLE; + cnt_next <= 0; + -- Oldest Instance Sample Found + elsif (resize(unsigned(sample_read_data),INSTANCE_MEMORY_ADDR_WIDTH) = cur_inst) then + -- NOTE: Instance Data already valid + stage_next <= REMOVE_SAMPLE; + cnt_next <= 0; + else + -- Continue + cur_sample_next <= next_sample; + cnt_next <= 0; end if; end if; when others => null; end case; when REMOVE_ORPHAN_SAMPLES => - -- Synthesis Guard - if (WITH_KEY) then - case (cnt) is - -- GET Instance Pointer - when 0 => - sample_valid_in <= '1'; - sample_addr <= cur_sample + SMF_INSTANCE_ADDR_OFFSET; - sample_read <= '1'; - -- Memory Flow Control Guard - if (sample_ready_in = '1') then + assert (CONFIG_ARRAY_T(ind).WITH_KEY) severity FAILURE; + + case (cnt) is + -- GET Instance Pointer + when 0 => + sample_valid_in <= '1'; + sample_addr <= cur_sample + SMF_INSTANCE_ADDR_OFFSET; + sample_read <= '1'; + -- Memory Flow Control Guard + if (sample_ready_in = '1') then + cnt_next <= cnt + 1; + end if; + -- GET Next Sample + when 1 => + sample_valid_in <= '1'; + sample_addr <= cur_sample + SMF_NEXT_ADDR_OFFSET; + sample_read <= '1'; + -- Memory Flow Control Guard + if (sample_ready_in = '1') then + cnt_next <= cnt + 1; + end if; + -- READ Instance Pointer + when 2 => + sample_ready_out <= '1'; + -- Memory Flow Control Guard + if (sample_valid_out = '1') then + -- Sample is Orphan (And not newly added sample of new instance) + if (resize(unsigned(sample_read_data),INSTANCE_MEMORY_ADDR_WIDTH) = dead_inst and cur_sample /= new_sample) then + -- Remove Orphan Sample + stage_next <= REMOVE_SAMPLE; + cnt_next <= 0; + sample_abort_read <= '1'; + else cnt_next <= cnt + 1; end if; - -- GET Next Sample - when 1 => - sample_valid_in <= '1'; - sample_addr <= cur_sample + SMF_NEXT_ADDR_OFFSET; - sample_read <= '1'; - -- Memory Flow Control Guard - if (sample_ready_in = '1') then - cnt_next <= cnt + 1; + end if; + -- READ Next Sample + when 3 => + sample_ready_out <= '1'; + -- Memory Flow Control Guard + if (sample_valid_out = '1') then + -- End of Samples + if (resize(unsigned(sample_read_data),SAMPLE_MEMORY_ADDR_WIDTH) = SAMPLE_MEMORY_MAX_ADDRESS) then + -- DONE + orphan_samples_next <= '0'; + stage_next <= IDLE; + else + -- Continue + cur_sample_next <= resize(unsigned(sample_read_data),SAMPLE_MEMORY_ADDR_WIDTH); + cnt_next <= 0; end if; - -- READ Instance Pointer - when 2 => - sample_ready_out <= '1'; - -- Memory Flow Control Guard - if (sample_valid_out = '1') then - -- Sample is Orphan (And not newly added sample of new instance) - if (resize(unsigned(sample_read_data),INSTANCE_MEMORY_ADDR_WIDTH) = dead_inst and cur_sample /= new_sample) then - -- Remove Orphan Sample - stage_next <= REMOVE_SAMPLE; - cnt_next <= 0; - sample_abort_read <= '1'; - else - cnt_next <= cnt + 1; - end if; - end if; - -- READ Next Sample - when 3 => - sample_ready_out <= '1'; - -- Memory Flow Control Guard - if (sample_valid_out = '1') then - -- End of Samples - if (resize(unsigned(sample_read_data),SAMPLE_MEMORY_ADDR_WIDTH) = SAMPLE_MEMORY_MAX_ADDRESS) then - -- DONE - orphan_samples_next <= '0'; - stage_next <= IDLE; - else - -- Continue - cur_sample_next <= resize(unsigned(sample_read_data),SAMPLE_MEMORY_ADDR_WIDTH); - cnt_next <= 0; - end if; - end if; - when others => - null; - end case; - end if; + end if; + when others => + null; + end case; when REMOVE_SAMPLE => -- Precondition: cur_sample set @@ -2310,10 +2437,10 @@ begin next_sample_next <= resize(unsigned(sample_read_data),SAMPLE_MEMORY_ADDR_WIDTH); -- Sample Memory Full - if (empty_sample_list_head = SAMPLE_MEMORY_MAX_ADDRESS) then - empty_sample_list_head_next <= cur_sample; - empty_sample_list_tail_next <= cur_sample; - cnt_next <= cnt + 2; --Skip Next Step + if (empty_sample_list_head(ind) = SAMPLE_MEMORY_MAX_ADDRESS) then + empty_sample_list_head_next(ind) <= cur_sample; + empty_sample_list_tail_next(ind) <= cur_sample; + cnt_next <= cnt + 2; -- SET NEXT POINTER else cnt_next <= cnt + 1; end if; @@ -2322,7 +2449,7 @@ begin when 7 => -- Add Current Sample after Empty List Tail sample_valid_in <= '1'; - sample_addr <= empty_sample_list_tail + SMF_NEXT_ADDR_OFFSET; + sample_addr <= empty_sample_list_tail(ind) + SMF_NEXT_ADDR_OFFSET; sample_write_data <= std_logic_vector(resize(cur_sample,WORD_WIDTH)); -- Memory Flow Control Guard @@ -2339,27 +2466,27 @@ begin -- Memory Flow Control Guard if (sample_ready_in = '1') then -- Fix Empty List Pointers - empty_sample_list_tail_next <= cur_sample; + empty_sample_list_tail_next(ind) <= cur_sample; -- Current Sample is Newest (Occupied List Tail) if (next_sample = SAMPLE_MEMORY_MAX_ADDRESS) then - assert (cur_sample = newest_sample) severity FAILURE; + assert (cur_sample = newest_sample(ind)) severity FAILURE; -- Fix Newest Pointer - newest_sample_next <= prev_sample; + newest_sample_next(ind) <= prev_sample; -- Current Sample is Oldest (List Head) if (prev_sample = SAMPLE_MEMORY_MAX_ADDRESS) then - assert (cur_sample = oldest_sample) severity FAILURE; - assert (newest_sample = oldest_sample) severity FAILURE; + assert (cur_sample = oldest_sample(ind)) severity FAILURE; + assert (newest_sample(ind) = oldest_sample(ind)) severity FAILURE; -- NOTE: Sample Memory Empty (newest_sample also set to MAX_ADDR) -- Fix Oldest Pointer - oldest_sample_next <= SAMPLE_MEMORY_MAX_ADDRESS; + oldest_sample_next(ind) <= SAMPLE_MEMORY_MAX_ADDRESS; - cnt_next <= cnt + 3; -- Skip next 2 steps + cnt_next <= cnt + 3; -- READ PAYLOAD POINTER else - cnt_next <= cnt + 2; -- Skip next step + cnt_next <= cnt + 2; -- SET NEXT POINTER (Previous Sample) end if; else cnt_next <= cnt + 1; @@ -2376,12 +2503,12 @@ begin if (sample_ready_in = '1') then -- Current Sample is oldest sample (List Head) if (prev_sample = SAMPLE_MEMORY_MAX_ADDRESS) then - assert (cur_sample = oldest_sample) report "Previous Sample is MAX_ADDR, but cur_sample /= oldest_sample" severity FAILURE; + assert (cur_sample = oldest_sample(ind)) severity FAILURE; -- Fix Oldest Pointer - oldest_sample_next <= next_sample; + oldest_sample_next(ind) <= next_sample; - cnt_next <= cnt + 2; -- Skip next step + cnt_next <= cnt + 2; -- READ PAYLOAD POINTER else cnt_next <= cnt + 1; end if; @@ -2404,12 +2531,14 @@ begin -- Memory Flow Control Guard if (sample_valid_out = '1') then -- Update Global Sample Count - global_sample_cnt_next <= global_sample_cnt - 1; + global_sample_cnt_next(ind) <= global_sample_cnt(ind) - 1; + -- Trigger ACK Wait Check + ack_wait_check_next <= '1'; -- Update Global ACK Count -- Sample was ACKed if (sample_status_info(SSI_ACK_FLAG) = '1') then - global_ack_cnt_next <= global_ack_cnt - 1; + global_ack_cnt_next(ind) <= global_ack_cnt(ind) - 1; end if; cur_payload_next <= resize(unsigned(sample_read_data),PAYLOAD_MEMORY_ADDR_WIDTH); @@ -2432,9 +2561,9 @@ begin stage_next <= POST_SAMPLE_REMOVE; end if; -- Payload Memory Full - elsif (empty_payload_list_head = PAYLOAD_MEMORY_MAX_ADDRESS) then + elsif (empty_payload_list_head(ind) = PAYLOAD_MEMORY_MAX_ADDRESS) then -- Fix Empty List Head - empty_payload_list_head_next <= resize(unsigned(sample_read_data),PAYLOAD_MEMORY_ADDR_WIDTH); + empty_payload_list_head_next(ind) <= resize(unsigned(sample_read_data),PAYLOAD_MEMORY_ADDR_WIDTH); -- Orphan Sample Removal in progress if (orphan_samples = '1') then @@ -2479,17 +2608,17 @@ begin cnt_next <= cnt + 1; else cur_payload_next <= resize(unsigned(payload_read_data),PAYLOAD_MEMORY_ADDR_WIDTH); - cnt_next <= cnt - 1; + cnt_next <= 12; -- GET NEXT PAYLOAD end if; end if; - -- SET Next Payload Pointer (Last Payload of Current Sample) + -- SET Next Payload Pointer (Last Payload Slot of Current Sample) when 14 => payload_valid_in <= '1'; payload_addr <= cur_payload + PMF_NEXT_ADDR_OFFSET; - payload_write_data <= std_logic_vector(resize(empty_payload_list_head,WORD_WIDTH)); + payload_write_data <= std_logic_vector(resize(empty_payload_list_head(ind),WORD_WIDTH)); -- Fix Empty List Head - empty_payload_list_head_next <= first_payload; + empty_payload_list_head_next(ind) <= first_payload; -- Memory Flow Control Guard if (payload_ready_in = '1') then @@ -2517,51 +2646,44 @@ begin -- Precondition: inst_data set (IMF_STATUS_FLAG, IMF_SAMPLE_CNT_FLAG, IMF_ACK_CNT_FLAG) -- Memory Operation Guard - if (not WITH_KEY or inst_op_done = '1') then - -- Synthesis Guard - if (WITH_KEY) then - assert (inst_data.addr /= INSTANCE_MEMORY_MAX_ADDRESS) severity FAILURE; - assert stable(clk, check_mask(inst_data.field_flags, IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_ACK_CNT_FLAG)) severity FAILURE; - - inst_op_start <= '1'; - inst_opcode <= UPDATE_INSTANCE; - inst_r.addr <= inst_data.addr; - inst_r.field_flags <= IMF_SAMPLE_CNT_FLAG; - inst_r.sample_cnt <= inst_data.sample_cnt - 1; - -- Sample was ACKed - if (sample_status_info(SSI_ACK_FLAG) = '1') then - inst_r.field_flags <= IMF_SAMPLE_CNT_FLAG or IMF_ACK_CNT_FLAG; - inst_r.ack_cnt <= inst_data.ack_cnt - 1; - else - -- Update Stale Instance Count - -- Instance is Unregistered and last NACKed sample is removed - if (inst_data.status_info(ISI_UNREGISTERED_FLAG) = '1' and inst_data.sample_cnt = 1) then - stale_inst_cnt_next <= stale_inst_cnt + 1; - end if; - end if; + if (inst_op_done = '1') then + assert (inst_data.addr /= INSTANCE_MEMORY_MAX_ADDRESS) severity FAILURE; + assert stable(clk, inst_data.i = ind and check_mask(inst_data.field_flags, IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_ACK_CNT_FLAG)) severity FAILURE; + + inst_op_start <= '1'; + inst_opcode <= UPDATE_INSTANCE; + inst_r.i <= ind; + inst_r.addr <= inst_data.addr; + inst_r.field_flags <= IMF_SAMPLE_CNT_FLAG; + inst_r.sample_cnt <= inst_data.sample_cnt - 1; + -- Sample was ACKed + if (sample_status_info(SSI_ACK_FLAG) = '1') then + inst_r.field_flags <= IMF_SAMPLE_CNT_FLAG or IMF_ACK_CNT_FLAG; + inst_r.ack_cnt <= inst_data.ack_cnt - 1; else - inst_data_next2.sample_cnt <= inst_data.sample_cnt - 1; - -- Sample was ACKed - if (sample_status_info(SSI_ACK_FLAG) = '1') then - inst_data_next2.ack_cnt <= inst_data.ack_cnt - 1; + -- Update Stale Instance Count + -- Instance is Unregistered and last NACKed sample is removed + if (inst_data.status_info(ISI_UNREGISTERED_FLAG) = '1' and inst_data.sample_cnt = 1) then + stale_inst_cnt_next(ind) <= stale_inst_cnt(ind) + 1; end if; end if; if (is_rtps = '1') then -- DONE - done_rtps <= '1'; - ret_rtps <= OK; - stage_next <= IDLE; + done_rtps(ind) <= '1'; + ret_rtps(ind) <= OK; + stage_next <= IDLE; elsif (is_lifespan_check = '1') then -- Reached End of Samples if (next_sample = SAMPLE_MEMORY_MAX_ADDRESS) then - -- DONE - stage_next <= IDLE; + -- Continue + stage_next <= CHECK_LIFESPAN; + cnt_next <= 0; -- GET NEXT WRITER else -- Continue Search cur_sample_next <= next_sample; stage_next <= CHECK_LIFESPAN; - cnt_next <= 0; + cnt_next <= 2; -- GET NEXT SAMPLE end if; else -- DONE @@ -2572,15 +2694,15 @@ begin case (cnt) is -- SKIP READ when 0 => - ready_in_dds <= '1'; + ready_in_dds(ind) <= '1'; -- Wait until last word from input - if (last_word_in_dds = '1') then + if (last_word_in_dds(ind) = '1') then cnt_next <= cnt + 1; end if; -- Return Code when 1 => - done_dds <= '1'; - return_code_dds <= return_code_latch; + done_dds(ind) <= '1'; + return_code_dds(ind) <= return_code_latch; -- DONE stage_next <= IDLE; @@ -2588,85 +2710,87 @@ begin null; end case; when SKIP => - ready_in_dds <= '1'; + ready_in_dds(ind) <= '1'; -- Wait until last word from input - if (last_word_in_dds = '1') then + if (last_word_in_dds(ind) = '1') then stage_next <= return_stage; cnt_next <= 0; end if; when REMOVE_STALE_INSTANCE => - -- Synthesis Guard - if (WITH_KEY) then - -- Wait for Instance Data - if (inst_op_done = '1') then - case (cnt) is - -- Find and Remove First Stale Instance - when 0 => - -- Iterated through all Instances - if (inst_data.addr = INSTANCE_MEMORY_MAX_ADDRESS) then - -- NOTE: We should enter this state only if there is at least one stale Instance to be removed, so we should never enter this branch. - assert stable(clk,FALSE) severity FAILURE; - stage_next <= IDLE; - else - assert stable(clk,check_mask(inst_data.field_flags, IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_ACK_CNT_FLAG)) severity FAILURE; + assert (CONFIG_ARRAY_T(ind).WITH_KEY) severity FAILURE; + + -- Wait for Instance Data + if (inst_op_done = '1') then + case (cnt) is + -- Find and Remove First Stale Instance + when 0 => + -- Iterated through all Instances + if (inst_data.addr = INSTANCE_MEMORY_MAX_ADDRESS) then + -- NOTE: We should enter this state only if there is at least one stale Instance to be removed, so we should never enter this branch. + assert stable(clk,FALSE) severity FAILURE; + stage_next <= IDLE; + else + assert stable(clk, inst_data.i = ind and check_mask(inst_data.field_flags, IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_ACK_CNT_FLAG)) severity FAILURE; + + -- Found Stale Instance (Unregistered and all Samples ACKed) + if (inst_data.status_info(ISI_UNREGISTERED_FLAG) = '1' and inst_data.sample_cnt = inst_data.ack_cnt) then + -- Remove Stale Instance + inst_op_start <= '1'; + inst_opcode <= REMOVE_INSTANCE; + inst_r.i <= ind; + inst_r.addr <= inst_data.addr; + -- Update Stale Instance Count + stale_inst_cnt_next(ind) <= stale_inst_cnt(ind) - 1; - -- Found Stale Instance (Unregistered and all Samples ACKed) - if (inst_data.status_info(ISI_UNREGISTERED_FLAG) = '1' and inst_data.sample_cnt = inst_data.ack_cnt) then - -- Remove Stale Instance - inst_op_start <= '1'; - inst_opcode <= REMOVE_INSTANCE; - inst_r.addr <= inst_data.addr; - -- Update Stale Instance Count - stale_inst_cnt_next <= stale_inst_cnt - 1; - - -- Instance has Samples - if (inst_data.sample_cnt /= 0) then - -- NOTE: The Stale Instance has Samples that need to be removed, but we cannot do that now, - -- because that would mess with our current Sample that is currently in "limbo" until - -- finalized. So we postpone the Sample removal until after the finalization of the - -- current sample. - orphan_samples_next <= '1'; - dead_inst_next <= inst_data.addr; - end if; - - cnt_next <= cnt + 1; - else - -- Continue Search - inst_op_start <= '1'; - inst_opcode <= GET_NEXT_INSTANCE; - inst_r.addr <= inst_data.addr; - inst_r.field_flags <= IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_ACK_CNT_FLAG; + -- Instance has Samples + if (inst_data.sample_cnt /= 0) then + -- NOTE: The Stale Instance has Samples that need to be removed, but we cannot do that now, + -- because that would mess with our current Sample that is currently in "limbo" until + -- finalized. So we postpone the Sample removal until after the finalization of the + -- current sample. + orphan_samples_next <= '1'; + dead_inst_next <= inst_data.addr; end if; - end if; - -- Insert New Instance - when 1 => - inst_op_start <= '1'; - inst_opcode <= INSERT_INSTANCE; - inst_r.key_hash <= key_hash; - inst_r.ack_cnt <= (others => '0'); - if (register_op = '1') then - inst_r.status_info <= (others => '0'); - inst_r.sample_cnt <= (others => '0'); + + cnt_next <= cnt + 1; else - inst_r.status_info <= (ISI_LIVELINESS_FLAG => '1', others => '0'); - inst_r.sample_cnt <= to_unsigned(1, WORD_WIDTH); + -- Continue Search + inst_op_start <= '1'; + inst_opcode <= GET_NEXT_INSTANCE; + inst_r.i <= ind; + inst_r.addr <= inst_data.addr; + inst_r.field_flags <= IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_ACK_CNT_FLAG; end if; - - -- Latch Instance Pointer - cur_inst_next <= inst_empty_head; - - -- Register Operation in progress - if (register_op = '1') then - -- DONE - stage_next <= PUSH_KEY_HASH; - else - stage_next <= FINALIZE_PAYLOAD; - cnt_next <= 0; - end if; - when others => - null; - end case; - end if; + end if; + -- Insert New Instance + when 1 => + inst_op_start <= '1'; + inst_opcode <= INSERT_INSTANCE; + inst_r.i <= ind; + inst_r.key_hash <= key_hash; + inst_r.ack_cnt <= (others => '0'); + if (register_op = '1') then + inst_r.status_info <= (others => '0'); + inst_r.sample_cnt <= (others => '0'); + else + inst_r.status_info <= (ISI_LIVELINESS_FLAG => '1', others => '0'); + inst_r.sample_cnt <= to_unsigned(1, WORD_WIDTH); + end if; + + -- Latch Instance Pointer + cur_inst_next <= inst_empty_head(ind); + + -- Register Operation in progress + if (register_op = '1') then + -- DONE + stage_next <= PUSH_KEY_HASH; + else + stage_next <= FINALIZE_PAYLOAD; + cnt_next <= 0; + end if; + when others => + null; + end case; end if; when GET_SEQ_NR => -- Precondition: cur_sample set @@ -2710,8 +2834,8 @@ begin end if; -- Return Code when 4 => - done_rtps <= '1'; - ret_rtps <= OK; + done_rtps(ind) <= '1'; + ret_rtps(ind) <= OK; -- DONE stage_next <= IDLE; @@ -2749,24 +2873,17 @@ begin -- Memory Flow Control Guard if (sample_ready_in = '1') then - if (WITH_KEY) then - cnt_next <= cnt + 1; - else - cnt_next <= cnt + 2; -- Skip Next Step - end if; + cnt_next <= cnt + 1; end if; -- GET Instance Pointer when 3 => - -- Synthesis Guard - if (WITH_KEY) then - sample_valid_in <= '1'; - sample_addr <= cur_sample + SMF_INSTANCE_ADDR_OFFSET; - sample_read <= '1'; - - -- Memory Flow Control Guard - if (sample_ready_in = '1') then - cnt_next <= cnt + 1; - end if; + sample_valid_in <= '1'; + sample_addr <= cur_sample + SMF_INSTANCE_ADDR_OFFSET; + sample_read <= '1'; + + -- Memory Flow Control Guard + if (sample_ready_in = '1') then + cnt_next <= cnt + 1; end if; -- READ Previous Sample when 4 => @@ -2820,49 +2937,37 @@ begin cnt_next <= 0; end if; else - if (WITH_KEY) then - cnt_next <= cnt + 1; - else - cnt_next <= cnt + 2; -- Skip Next Step - end if; + cnt_next <= cnt + 1; end if; end if; -- READ Instance Pointer when 7 => - -- Synthesis Guard - if (WITH_KEY) then - sample_ready_out <= '1'; - - -- Memory Flow Control Guard - if (sample_valid_out = '1') then - cur_inst_next <= resize(unsigned(sample_read_data),INSTANCE_MEMORY_ADDR_WIDTH); - cnt_next <= cnt + 1; - end if; + sample_ready_out <= '1'; + + -- Memory Flow Control Guard + if (sample_valid_out = '1') then + cur_inst_next <= resize(unsigned(sample_read_data),INSTANCE_MEMORY_ADDR_WIDTH); + cnt_next <= cnt + 1; end if; -- Check Result when 8 => -- No Sample with Requested Sequence Number found if (cur_sample = SAMPLE_MEMORY_MAX_ADDRESS) then - done_rtps <= '1'; - ret_rtps <= INVALID; + done_rtps(ind) <= '1'; + ret_rtps(ind) <= INVALID; -- DONE stage_next <= IDLE; else - -- Synthesis Guard - if (WITH_KEY) then - -- Memory Operation Guard - if (inst_op_done = '1') then - -- Fetch Instance Data - inst_op_start <= '1'; - inst_opcode <= GET_INSTANCE; - inst_r.addr <= cur_inst; - inst_r.field_flags <= IMF_KEY_HASH_FLAG or IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_ACK_CNT_FLAG; - - stage_next <= return_stage; - cnt_next <= 0; - end if; - else + -- Memory Operation Guard + if (inst_op_done = '1') then + -- Fetch Instance Data + inst_op_start <= '1'; + inst_opcode <= GET_INSTANCE; + inst_r.i <= ind; + inst_r.addr <= cur_inst; + inst_r.field_flags <= IMF_KEY_HASH_FLAG or IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_ACK_CNT_FLAG; + stage_next <= return_stage; cnt_next <= 0; end if; @@ -2892,8 +2997,8 @@ begin -- Sample Already ACKed/NACKed if ((is_ack = '1' and sample_read_data(SSI_ACK_FLAG) = '1') or (is_ack = '0' and sample_read_data(SSI_ACK_FLAG) = '0')) then - done_rtps <= '1'; - ret_rtps <= OK; + done_rtps(ind) <= '1'; + ret_rtps(ind) <= OK; -- DONE stage_next <= IDLE; else @@ -2912,56 +3017,46 @@ begin end if; -- Memory Flow Control Guard if (sample_ready_in = '1') then + -- Trigger ACK Wait Check + ack_wait_check_next <= '1'; if (is_ack = '1') then - global_ack_cnt_next <= global_ack_cnt + 1; + global_ack_cnt_next(ind) <= global_ack_cnt(ind) + 1; else - global_ack_cnt_next <= global_ack_cnt - 1; + global_ack_cnt_next(ind) <= global_ack_cnt(ind) - 1; end if; cnt_next <= cnt + 1; end if; -- SET Instance Data when 3 => - if (WITH_KEY) then - -- Wait for Instance Data - if (inst_op_done = '1') then - assert (inst_data.addr /= INSTANCE_MEMORY_MAX_ADDRESS) severity FAILURE; - assert stable(clk, check_mask(inst_data.field_flags, IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_ACK_CNT_FLAG)) severity FAILURE; - - -- Update - inst_op_start <= '1'; - inst_opcode <= UPDATE_INSTANCE; - inst_r.addr <= cur_inst; - inst_r.field_flags <= IMF_ACK_CNT_FLAG; - if (is_ack = '1') then - inst_r.ack_cnt <= inst_data.ack_cnt + 1; - else - inst_r.ack_cnt <= inst_data.ack_cnt - 1; - end if; - - -- Update Stale Instance Count - -- XXX: Possible Worst Case Path (Addition and Comparison in same clock) - if (is_ack = '1' and inst_data.status_info(ISI_UNREGISTERED_FLAG) = '1' and (inst_data.ack_cnt+1) = inst_data.sample_cnt) then - stale_inst_cnt_next <= stale_inst_cnt + 1; - elsif (is_ack = '0' and inst_data.status_info(ISI_UNREGISTERED_FLAG) = '1' and inst_data.ack_cnt = inst_data.sample_cnt) then - stale_inst_cnt_next <= stale_inst_cnt - 1; - end if; - - -- DONE - done_rtps <= '1'; - ret_rtps <= OK; - stage_next <= IDLE; - end if; - else + -- Wait for Instance Data + if (inst_op_done = '1') then + assert (inst_data.addr /= INSTANCE_MEMORY_MAX_ADDRESS) severity FAILURE; + assert stable(clk, inst_data.i = ind and check_mask(inst_data.field_flags, IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_ACK_CNT_FLAG)) severity FAILURE; + + -- Update + inst_op_start <= '1'; + inst_opcode <= UPDATE_INSTANCE; + inst_r.i <= ind; + inst_r.addr <= cur_inst; + inst_r.field_flags <= IMF_ACK_CNT_FLAG; if (is_ack = '1') then - inst_data_next2.ack_cnt <= inst_data.ack_cnt + 1; + inst_r.ack_cnt <= inst_data.ack_cnt + 1; else - inst_data_next2.ack_cnt <= inst_data.ack_cnt - 1; + inst_r.ack_cnt <= inst_data.ack_cnt - 1; + end if; + + -- Update Stale Instance Count + -- XXX: Possible Worst Case Path (Addition and Comparison in same clock) + if (is_ack = '1' and inst_data.status_info(ISI_UNREGISTERED_FLAG) = '1' and (inst_data.ack_cnt+1) = inst_data.sample_cnt) then + stale_inst_cnt_next(ind) <= stale_inst_cnt(ind) + 1; + elsif (is_ack = '0' and inst_data.status_info(ISI_UNREGISTERED_FLAG) = '1' and inst_data.ack_cnt = inst_data.sample_cnt) then + stale_inst_cnt_next(ind) <= stale_inst_cnt(ind) - 1; end if; -- DONE - done_rtps <= '1'; - ret_rtps <= OK; - stage_next <= IDLE; + done_rtps(ind) <= '1'; + ret_rtps(ind) <= OK; + stage_next <= IDLE; end if; when others => null; @@ -3054,33 +3149,26 @@ begin if (sample_valid_out = '1') then cur_payload_next <= resize(unsigned(sample_read_data),PAYLOAD_MEMORY_ADDR_WIDTH); - if (WITH_KEY) then - cnt_next <= cnt + 1; - else - cnt_next <= cnt + 2; -- Skip Next Step - end if; + cnt_next <= cnt + 1; end if; -- Instance Handle when 8 => - -- Synthesis Guard - if (WITH_KEY) then - -- Wait for Instance Data - if (inst_op_done = '1') then - assert (inst_data.addr /= INSTANCE_MEMORY_MAX_ADDRESS) severity FAILURE; - assert stable(clk, check_mask(inst_data.field_flags, IMF_KEY_HASH_FLAG)) severity FAILURE; - - cc_instance_handle_sig_next <= inst_data.key_hash; - - cnt_next <= cnt + 1; - end if; + -- Wait for Instance Data + if (inst_op_done = '1') then + assert (inst_data.addr /= INSTANCE_MEMORY_MAX_ADDRESS) severity FAILURE; + assert stable(clk, inst_data.i = ind and check_mask(inst_data.field_flags, IMF_KEY_HASH_FLAG)) severity FAILURE; + + cc_instance_handle_sig_next <= inst_data.key_hash; + + cnt_next <= cnt + 1; end if; -- Present Sample when 9 => - done_rtps <= '1'; - ret_rtps <= OK; + done_rtps(ind) <= '1'; + ret_rtps(ind) <= OK; -- RTPS Requestes Payload - if (get_data_rtps = '1') then + if (get_data_rtps(ind) = '1') then if (cur_payload /= PAYLOAD_MEMORY_MAX_ADDRESS) then -- Get Payload stage_next <= GET_PAYLOAD; @@ -3139,13 +3227,13 @@ begin cnt_next <= cnt + 1; else cnt_next <= cnt + 3; - long_latch_next <= std_logic_vector(to_unsigned(PAYLOAD_FRAME_SIZE-1,CDR_LONG_WIDTH)); + long_latch_next <= std_logic_vector(to_unsigned(PAYLOAD_FRAME_SIZE(ind)-1,CDR_LONG_WIDTH)); end if; end if; -- GET Payload Offset when 2 => payload_valid_in <= '1'; - payload_addr <= cur_payload + PAYLOAD_FRAME_SIZE-1; + payload_addr <= cur_payload + PAYLOAD_FRAME_SIZE(ind)-1; payload_read <= '1'; -- Memory Flow Control Guard @@ -3194,16 +3282,16 @@ begin if (cnt3 /= 0) then -- Memory Flow Control Guard if (payload_valid_out = '1') then - valid_out_rtps <= '1'; - data_out_rtps <= payload_read_data; + valid_out_rtps(ind) <= '1'; + data_out_rtps(ind) <= payload_read_data; -- End of Payload if (cnt3 = 1 and cnt = 5) then - last_word_out_rtps <= '1'; + last_word_out_rtps(ind) <= '1'; end if; -- DDS Read - if (ready_out_rtps = '1') then + if (ready_out_rtps(ind) = '1') then payload_ready_out <= '1'; -- NOTE: We are using the tmp_bool variable to signal if there is an increment -- on the same clock cycle. @@ -3225,8 +3313,31 @@ begin -- Precondition: cur_sample set, case (cnt) is - -- GET Next Sample + -- GET NEXT WRITER when 0 => + if (ind = NUM_WRITERS-1) then + -- Reset + is_lifespan_check_next <= '0'; + + -- DONE + stage_next <= IDLE; + else + -- Next Writer + ind_next <= ind + 1; + cnt_next <= cnt + 1; + end if; + -- CHECK LIFESPAN + when 1 => + -- Samples Available (And Writer has Lifespan enabled) + if (CONFIG_ARRAY_T(ind).LIFESPAN_QOS /= DURATION_INFINITE and oldest_sample(ind) /= SAMPLE_MEMORY_MAX_ADDRESS) then + cur_sample_next <= oldest_sample(ind); + cnt_next <= cnt + 1; + else + -- Continue + cnt_next <= 0; -- GET NEXT WRITER + end if; + -- GET NEXT Sample + when 2 => sample_valid_in <= '1'; sample_addr <= cur_sample + SMF_NEXT_ADDR_OFFSET; sample_read <= '1'; @@ -3236,7 +3347,7 @@ begin cnt_next <= cnt + 1; end if; -- GET Lifespan 1/2 - when 1 => + when 3 => sample_valid_in <= '1'; sample_addr <= cur_sample + SMF_LIFESPAN_DEADLINE_OFFSET; sample_read <= '1'; @@ -3246,34 +3357,27 @@ begin cnt_next <= cnt + 1; end if; -- GET Lifespan 2/2 - when 2 => + when 4 => sample_valid_in <= '1'; sample_addr <= cur_sample + SMF_LIFESPAN_DEADLINE_OFFSET + 1; sample_read <= '1'; -- Memory Control Flow Guard if (sample_ready_in = '1') then - if (WITH_KEY) then - cnt_next <= cnt + 1; - else - cnt_next <= cnt + 2; --Skip Next Step - end if; + cnt_next <= cnt + 1; end if; -- GET Instance Pointer - when 3 => - -- Synthesis Guard - if (WITH_KEY) then - sample_valid_in <= '1'; - sample_addr <= cur_sample + SMF_INSTANCE_ADDR_OFFSET; - sample_read <= '1'; - - -- Memory Control Flow Guard - if (sample_ready_in = '1') then - cnt_next <= cnt + 1; - end if; + when 5 => + sample_valid_in <= '1'; + sample_addr <= cur_sample + SMF_INSTANCE_ADDR_OFFSET; + sample_read <= '1'; + + -- Memory Control Flow Guard + if (sample_ready_in = '1') then + cnt_next <= cnt + 1; end if; -- READ Next Sample - when 4 => + when 6 => sample_ready_out <= '1'; -- Memory Control Flow Guard @@ -3282,7 +3386,7 @@ begin cnt_next <= cnt + 1; end if; -- READ Lifespan 1/2 - when 5 => + when 7 => sample_ready_out <= '1'; -- Memory Control Flow Guard @@ -3291,7 +3395,7 @@ begin cnt_next <= cnt + 1; end if; -- READ Lifespan 2/2 - when 6 => + when 8 => sample_ready_out <= '1'; -- Memory Control Flow Guard @@ -3300,13 +3404,7 @@ begin -- Sample Lifespan Expired if (tmp_dw /= TIME_INVALID and time >= tmp_dw) then - if (WITH_KEY) then - cnt_next <= cnt + 1; - else - -- Remove Sample - stage_next <= REMOVE_SAMPLE; - cnt_next <= 0; - end if; + cnt_next <= cnt + 1; else sample_abort_read <= '1'; @@ -3317,35 +3415,33 @@ begin -- Reached End of Samples if (next_sample = SAMPLE_MEMORY_MAX_ADDRESS) then - -- DONE - stage_next <= IDLE; + -- Continue + cnt_next <= 0; -- GET NEXT WRITER else -- Continue Search cur_sample_next <= next_sample; - cnt_next <= 0; + cnt_next <= 2; -- GET NEXT SAMPLE end if; end if; end if; -- READ Instance Pointer - when 7 => - -- Synthesis Guard - if (WITH_KEY) then - -- Memory Operation Guard - if (inst_op_done = '1') then - sample_ready_out <= '1'; + when 9 => + -- Memory Operation Guard + if (inst_op_done = '1') then + sample_ready_out <= '1'; + + -- Memory Control Flow Guard + if (sample_valid_out = '1') then + -- Fetch Instance Data + inst_op_start <= '1'; + inst_opcode <= GET_INSTANCE; + inst_r.i <= ind; + inst_r.addr <= resize(unsigned(sample_read_data),INSTANCE_MEMORY_ADDR_WIDTH); + inst_r.field_flags <= IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_ACK_CNT_FLAG; - -- Memory Control Flow Guard - if (sample_valid_out = '1') then - -- Fetch Instance Data - inst_op_start <= '1'; - inst_opcode <= GET_INSTANCE; - inst_r.addr <= resize(unsigned(sample_read_data),INSTANCE_MEMORY_ADDR_WIDTH); - inst_r.field_flags <= IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_ACK_CNT_FLAG; - - -- Remove Sample - stage_next <= REMOVE_SAMPLE; - cnt_next <= 0; - end if; + -- Remove Sample + stage_next <= REMOVE_SAMPLE; + cnt_next <= 0; end if; end if; when others => @@ -3355,27 +3451,27 @@ begin case (cnt) is -- Return Code when 0 => - done_dds <= '1'; - return_code_dds <= RETCODE_OK; - cnt_next <= cnt + 1; + done_dds(ind) <= '1'; + return_code_dds(ind) <= RETCODE_OK; + cnt_next <= cnt + 1; -- Total Count when 1 => - data_out_dds <= std_logic_vector(liveliness_lost_cnt); - valid_out_dds <= '1'; + data_out_dds(ind) <= std_logic_vector(liveliness_lost_cnt(ind)); + valid_out_dds(ind) <= '1'; - if (ready_out_dds = '1') then + if (ready_out_dds(ind) = '1') then cnt_next <= cnt + 1; end if; -- Total Count Change when 2 => - data_out_dds <= std_logic_vector(liveliness_lost_cnt_change); - valid_out_dds <= '1'; - last_word_out_dds <= '1'; + data_out_dds(ind) <= std_logic_vector(liveliness_lost_cnt_change(ind)); + valid_out_dds(ind) <= '1'; + last_word_out_dds(ind) <= '1'; - if (ready_out_dds = '1') then + if (ready_out_dds(ind) = '1') then -- Reset - liveliness_lost_cnt_change_next <= (others => '0'); - status_sig_next <= status_sig and (not LIVELINESS_LOST_STATUS); + liveliness_lost_cnt_change_next(ind) <= (others => '0'); + status_sig_next(ind) <= status_sig(ind) and (not LIVELINESS_LOST_STATUS); -- DONE stage_next <= IDLE; @@ -3387,58 +3483,58 @@ begin case (cnt) is -- Return Code when 0 => - done_dds <= '1'; - return_code_dds <= RETCODE_OK; - cnt_next <= cnt + 1; + done_dds(ind) <= '1'; + return_code_dds(ind) <= RETCODE_OK; + cnt_next <= cnt + 1; -- Total Count when 1 => - data_out_dds <= std_logic_vector(deadline_miss_cnt); - valid_out_dds <= '1'; + data_out_dds(ind) <= std_logic_vector(deadline_miss_cnt(ind)); + valid_out_dds(ind) <= '1'; - if (ready_out_dds = '1') then + if (ready_out_dds(ind) = '1') then cnt_next <= cnt + 1; end if; -- Total Count Change when 2 => - data_out_dds <= std_logic_vector(deadline_miss_cnt_change); - valid_out_dds <= '1'; + data_out_dds(ind) <= std_logic_vector(deadline_miss_cnt_change(ind)); + valid_out_dds(ind) <= '1'; - if (ready_out_dds = '1') then + if (ready_out_dds(ind) = '1') then -- Reset - deadline_miss_cnt_change_next <= (others => '0'); + deadline_miss_cnt_change_next(ind) <= (others => '0'); cnt_next <= cnt + 1; end if; -- Last Instance Handle 1/4 when 3 => - data_out_dds <= deadline_miss_last_inst(0); - valid_out_dds <= '1'; - if (ready_out_dds = '1') then + data_out_dds(ind) <= deadline_miss_last_inst(ind)(0); + valid_out_dds(ind) <= '1'; + if (ready_out_dds(ind) = '1') then cnt_next <= cnt + 1; end if; -- Last Instance Handle 2/4 when 4 => - data_out_dds <= deadline_miss_last_inst(1); - valid_out_dds <= '1'; - if (ready_out_dds = '1') then + data_out_dds(ind) <= deadline_miss_last_inst(ind)(1); + valid_out_dds(ind) <= '1'; + if (ready_out_dds(ind) = '1') then cnt_next <= cnt + 1; end if; -- Last Instance Handle 3/4 when 5 => - data_out_dds <= deadline_miss_last_inst(2); - valid_out_dds <= '1'; - if (ready_out_dds = '1') then + data_out_dds(ind) <= deadline_miss_last_inst(ind)(2); + valid_out_dds(ind) <= '1'; + if (ready_out_dds(ind) = '1') then cnt_next <= cnt + 1; end if; -- Last Instance Handle 4/4 when 6 => - data_out_dds <= deadline_miss_last_inst(3); - valid_out_dds <= '1'; - last_word_out_dds <= '1'; - if (ready_out_dds = '1') then + data_out_dds(ind) <= deadline_miss_last_inst(ind)(3); + valid_out_dds(ind) <= '1'; + last_word_out_dds(ind) <= '1'; + if (ready_out_dds(ind) = '1') then -- Reset - deadline_miss_last_inst_next <= HANDLE_NIL; - status_sig_next <= status_sig and (not OFFERED_DEADLINE_MISSED_STATUS); + deadline_miss_last_inst_next(ind) <= HANDLE_NIL; + status_sig_next(ind) <= status_sig(ind) and (not OFFERED_DEADLINE_MISSED_STATUS); -- DONE stage_next <= IDLE; @@ -3447,67 +3543,200 @@ begin null; end case; when CHECK_DEADLINE => - -- Synthesis Guard - if (WITH_KEY) then - -- Memory Operation Guard - if (inst_op_done = '1') then - case (cnt) is - -- Get First Instance - when 0 => - inst_op_start <= '1'; - inst_opcode <= GET_INSTANCE; - inst_r.addr <= inst_occupied_head; - inst_r.field_flags <= IMF_KEY_HASH_FLAG or IMF_STATUS_FLAG; - cnt_next <= 2; - -- Get Next Instance - when 1 => - inst_op_start <= '1'; - inst_opcode <= GET_NEXT_INSTANCE; - inst_r.addr <= inst_data.addr; - inst_r.field_flags <= IMF_KEY_HASH_FLAG or IMF_STATUS_FLAG; - cnt_next <= 2; - -- Check Instance - when 2 => - -- Reached End of Instances - if (inst_data.addr = INSTANCE_MEMORY_MAX_ADDRESS) then - -- DONE - stage_next <= IDLE; - else - assert stable(clk, check_mask(inst_data.field_flags, IMF_STATUS_FLAG or IMF_KEY_HASH_FLAG)) severity FAILURE; - - -- Instance received Sample - if (inst_data.status_info(ISI_LIVELINESS_FLAG) = '1') then - -- Reset Liveliness Flag - inst_op_start <= '1'; - inst_opcode <= UPDATE_INSTANCE; - inst_r.addr <= inst_data.addr; - inst_r.field_flags <= IMF_STATUS_FLAG; - inst_r.status_info <= inst_data.status_info; - inst_r.status_info(ISI_LIVELINESS_FLAG) <= '0'; - cnt_next <= 1; - else - -- Update Requested Deadline Missed Status - status_sig_next <= status_sig or OFFERED_DEADLINE_MISSED_STATUS; - deadline_miss_cnt_next <= deadline_miss_cnt + 1; - deadline_miss_cnt_change_next <= deadline_miss_cnt_change + 1; - deadline_miss_last_inst_next <= inst_data.key_hash; - cnt_next <= 1; - end if; + -- Memory Operation Guard + if (inst_op_done = '1') then + case (cnt) is + -- GET NEXT WRITER + when 0 => + if (ind = NUM_WRITERS-1) then + -- DONE + stage_next <= IDLE; + else + -- Next Writer + ind_next <= ind + 1; + cnt_next <= cnt + 1; + end if; + -- CHECK DEADLINE + when 1 => + -- Deadline Check Trigger + if (CONFIG_ARRAY_T(ind).DEADLINE_QOS /= DURATION_INFINITE and deadline_time(ind) <= time) then + tmp_dw := deadline_time(ind) + CONFIG_ARRAY_T(ind).DEADLINE_QOS; + deadline_time_next(ind) <= tmp_dw; + + -- XXX: Possible Worst Case Path (64-bit addition and comparison in same clock) + -- Update Check Time + if (tmp_dw < deadline_check_time) then + deadline_check_time_next <= tmp_dw; end if; - when others => - null; - end case; - end if; + + cnt_next <= cnt + 1; + else + if (CONFIG_ARRAY_T(ind).DEADLINE_QOS /= DURATION_INFINITE and deadline_time(ind) <= deadline_check_time) then + deadline_check_time_next <= deadline_time(ind); + end if; + + -- Continue + cnt_next <= 0; -- GET NEXT WRITER + end if; + -- GET FIRST Instance + when 2 => + inst_op_start <= '1'; + inst_opcode <= GET_INSTANCE; + inst_r.i <= ind; + inst_r.addr <= inst_occupied_head(ind); + inst_r.field_flags <= IMF_KEY_HASH_FLAG or IMF_STATUS_FLAG; + cnt_next <= 4; -- CHECK INSTANCE + -- GET NEXT Instance + when 3 => + inst_op_start <= '1'; + inst_opcode <= GET_NEXT_INSTANCE; + inst_r.i <= ind; + inst_r.addr <= inst_data.addr; + inst_r.field_flags <= IMF_KEY_HASH_FLAG or IMF_STATUS_FLAG; + cnt_next <= 4; -- CHECK INSTANCE + -- CHECK Instance + when 4 => + -- Reached End of Instances + if (inst_data.addr = INSTANCE_MEMORY_MAX_ADDRESS) then + -- Continue + cnt_next <= 0; -- GET NEXT WRITER + else + assert stable(clk, inst_data.i = ind and check_mask(inst_data.field_flags, IMF_STATUS_FLAG or IMF_KEY_HASH_FLAG)) severity FAILURE; + + -- Instance received Sample + if (inst_data.status_info(ISI_LIVELINESS_FLAG) = '1') then + -- Reset Liveliness Flag + inst_op_start <= '1'; + inst_opcode <= UPDATE_INSTANCE; + inst_r.i <= ind; + inst_r.addr <= inst_data.addr; + inst_r.field_flags <= IMF_STATUS_FLAG; + inst_r.status_info <= inst_data.status_info; + inst_r.status_info(ISI_LIVELINESS_FLAG) <= '0'; + cnt_next <= 3; -- GET NEXT INSTANCE + else + -- Update Requested Deadline Missed Status + status_sig_next(ind) <= status_sig(ind) or OFFERED_DEADLINE_MISSED_STATUS; + deadline_miss_cnt_next(ind) <= std_logic_vector(unsigned(deadline_miss_cnt(ind)) + 1); + deadline_miss_cnt_change_next(ind) <= std_logic_vector(unsigned(deadline_miss_cnt_change(ind)) + 1); + deadline_miss_last_inst_next(ind) <= inst_data.key_hash; + cnt_next <= 3; -- GET NEXT INSTANCE + end if; + end if; + when others => + null; + end case; end if; + when CHECK_LIVELINESS => + -- Memory Operation Guard + if (inst_op_done = '1') then + case (cnt) is + -- GET NEXT WRITER + when 0 => + if (ind = NUM_WRITERS-1) then + -- DONE + stage_next <= IDLE; + else + -- Next Writer + ind_next <= ind + 1; + cnt_next <= cnt + 1; + end if; + -- CHECK LEASE + when 1 => + -- Deadline Check Trigger + if (CONFIG_ARRAY_T(ind).LEASE_DURATION /= DURATION_INFINITE and lease_deadline(ind) <= time) then + tmp_dw := lease_deadline(ind) + CONFIG_ARRAY_T(ind).LEASE_DURATION; + lease_deadline_next(ind) <= tmp_dw; + + -- XXX: Possible Worst Case Path (64-bit addition and comparison in same clock) + -- Update Check Time + if (tmp_dw < lease_check_time) then + lease_check_time_next <= tmp_dw; + end if; + + status_sig_next(ind) <= status_sig(ind) or LIVELINESS_LOST_STATUS; + liveliness_lost_cnt_next(ind) <= std_logic_vector(unsigned(liveliness_lost_cnt(ind)) + 1); + liveliness_lost_cnt_change_next(ind) <= std_logic_vector(unsigned(liveliness_lost_cnt_change(ind)) + 1); + + -- Continue + cnt_next <= 0; -- GET NEXT WRITER + else + if (CONFIG_ARRAY_T(ind).LEASE_DURATION /= DURATION_INFINITE and lease_deadline(ind) <= lease_check_time) then + lease_check_time_next <= lease_deadline(ind); + end if; + + -- Continue + cnt_next <= 0; -- GET NEXT WRITER + end if; + when others => + null; + end case; + end if; + when CHECK_ACK_WAIT => + case (cnt) is + -- GET NEXT WRITER + when 0 => + if (ind = NUM_WRITERS-1) then + -- Reset + ack_wait_check_next <= '0'; + -- DONE + stage_next <= IDLE; + else + -- Next Writer + ind_next <= ind + 1; + cnt_next <= cnt + 1; + end if; + -- CHECK ACK STATE + when 1 => + -- Writer in WAIT_FOR_ACKNOWLEDGEMENT Operation + if(ack_wait(ind) = '1') then + -- All Writer Samples are ACKed + if (global_ack_cnt(ind) = global_sample_cnt(ind)) then + -- Reset + ack_wait_next(ind) <= '0'; + -- DONE + done_dds(ind) <= '1'; + return_code_dds(ind) <= RETCODE_OK; + + -- Continue + cnt_next <= 0; -- GET NEXT WRITER + else + cnt_next <= cnt + 1; + end if; + else + -- Continue + cnt_next <= 0; -- GET NEXT WRITER + end if; + -- CHECK OPERATION TIMEOUT + when 2 => + assert (ack_wait(ind) = '1') severity FAILURE; + + -- WAIT_FOR_ACKNOWLEDGEMENT Operation Timeout + if (timeout_time(ind) <= time) then + -- Reset + ack_wait_next(ind) <= '0'; + + -- DONE + done_dds(ind) <= '1'; + return_code_dds(ind) <= RETCODE_TIMEOUT; + + -- Continue + cnt_next <= 0; -- GET NEXT WRITER + else + if (timeout_time(ind) <= timeout_check_time) then + timeout_check_time_next <= timeout_time(ind); + end if; + + -- Continue + cnt_next <= 0; -- GET NEXT WRITER + end if; + when others => + null; + end case; when RESET_SAMPLE_MEMORY => case (cnt) is - -- Initialize - when 0 => - prev_sample_next <= SAMPLE_MEMORY_MAX_ADDRESS; - cur_sample_next <= (others => '0'); - cnt_next <= cnt + 1; -- SET Previous Pointer - when 1 => + when 0 => sample_valid_in <= '1'; sample_addr <= cur_sample + SMF_PREV_ADDR_OFFSET; sample_write_data <= std_logic_vector(resize(prev_sample,WORD_WIDTH)); @@ -3517,10 +3746,10 @@ begin cnt_next <= cnt + 1; end if; -- SET Next Pointer - when 2 => + when 1 => sample_valid_in <= '1'; sample_addr <= cur_sample + SMF_NEXT_ADDR_OFFSET; - if (cur_sample = MAX_SAMPLE_ADDRESS) then + if (cur_sample = MAX_SAMPLE_ADDRESS(ind)) then sample_write_data <= std_logic_vector(resize(SAMPLE_MEMORY_MAX_ADDRESS,WORD_WIDTH)); else sample_write_data <= std_logic_vector(resize(cur_sample + SAMPLE_FRAME_SIZE,WORD_WIDTH)); @@ -3528,46 +3757,914 @@ begin -- Memory Flow Control Guard if (sample_ready_in = '1') then - if (cur_sample = MAX_SAMPLE_ADDRESS) then + if (cur_sample = MAX_SAMPLE_ADDRESS(ind)) then + empty_sample_list_head_next(ind) <= FIRST_SAMPLE_ADDRESS; + empty_sample_list_tail_next(ind) <= MAX_SAMPLE_ADDRESS(ind); -- DONE - stage_next <= RESET_PAYLOAD_MEMORY; - cnt_next <= 0; - empty_sample_list_head_next <= FIRST_SAMPLE_ADDRESS; - empty_sample_list_tail_next <= MAX_SAMPLE_ADDRESS; + cur_payload_next <= FIRST_PAYLOAD_ADDRESS; + stage_next <= RESET_PAYLOAD_MEMORY; else -- Continue cur_sample_next <= cur_sample + SAMPLE_FRAME_SIZE; prev_sample_next <= cur_sample; - cnt_next <= 1; + cnt_next <= 0; -- SET Previous Pointer end if; end if; when others => null; end case; when RESET_PAYLOAD_MEMORY => - case (cnt) is - -- Initialize - when 0 => - cur_payload_next <= (others => '0'); - cnt_next <= cnt + 1; - -- SET Next Pointer - when 1 => - payload_valid_in <= '1'; - payload_addr <= cur_payload + PMF_NEXT_ADDR_OFFSET; - if (cur_payload = MAX_PAYLOAD_ADDRESS) then - payload_write_data <= std_logic_vector(resize(PAYLOAD_MEMORY_MAX_ADDRESS,WORD_WIDTH)); + -- SET Next Pointer + payload_valid_in <= '1'; + payload_addr <= cur_payload + PMF_NEXT_ADDR_OFFSET; + if (cur_payload = MAX_PAYLOAD_ADDRESS(ind)) then + payload_write_data <= std_logic_vector(resize(PAYLOAD_MEMORY_MAX_ADDRESS,WORD_WIDTH)); + else + payload_write_data <= std_logic_vector(resize(cur_payload + PAYLOAD_FRAME_SIZE(ind),WORD_WIDTH)); + end if; + + -- Memory Flow Control Guard + if (payload_ready_in = '1') then + if (cur_payload = MAX_PAYLOAD_ADDRESS(ind)) then + empty_payload_list_head_next(ind) <= FIRST_PAYLOAD_ADDRESS; + + if (ind = NUM_WRITERS-1) then + -- DONE + stage_next <= IDLE; else - payload_write_data <= std_logic_vector(resize(cur_payload + PAYLOAD_FRAME_SIZE,WORD_WIDTH)); + -- Continue (Next Writer) + ind_next <= ind + 1; + prev_sample_next <= SAMPLE_MEMORY_MAX_ADDRESS; + cur_sample_next <= FIRST_SAMPLE_ADDRESS; + stage_next <= RESET_SAMPLE_MEMORY; + cnt_next <= 0; + end if; + else + cur_payload_next <= cur_payload + PAYLOAD_FRAME_SIZE(ind); + end if; + end if; + end case; + end process; + + empty_head_sig_prc : process(all) + begin + for i in 0 to NUM_WRITERS-1 loop + empty_inst_head_sig(i) <= to_integer(inst_empty_head(i)); + empty_sample_head_sig(i) <= to_integer(empty_sample_list_head(i)); + empty_payload_head_sig(i) <= to_integer(empty_payload_list_head(i)); + end loop; + end process; + + -- *Instance Memory Process* + -- STATE DESCRIPTION + -- IDLE Idle State. Done Signal is pulled high and Memory FSM accepts new memory operations + -- SEARCH_INSTANCE See Memory OPCODE Description + -- GET_NEXT_INSTANCE See Memory OPCODE Description + -- GET_INSTANCE_DATA Latch specified Instance Data for use by main process + -- INSERT_INSTANCE See Memory OPCODE Description + -- UPDATE_INSTANCE See Memory OPCODE Description + -- REMOVE_INSTANCE See Memory OPCODE Description + -- RESET_MEMORY Reset Endpoint Memory to Empty State + inst_ctrl_prc : process(all) + begin + -- DEFAULT Registered + inst_stage_next <= inst_stage; + inst_addr_base_next <= inst_addr_base; + inst_addr_latch_next <= inst_addr_latch; + inst_empty_head_next <= inst_empty_head; + inst_occupied_head_next <= inst_occupied_head; + inst_latch_data_next <= inst_latch_data; + inst_cnt_next <= inst_cnt; + inst_data_next <= inst_data; + inst_long_latch_next <= inst_long_latch; + -- DEFAULT Unregistered + inst_ready_out <= '0'; + inst_valid_in <= '0'; + inst_read <= '0'; + inst_op_done <= '0'; + inst_abort_read <= '0'; + inst_addr <= (others => '0'); + inst_write_data <= (others => '0'); + + + case (inst_stage) is + when IDLE => + inst_op_done <= '1'; + + if (inst_op_start = '1') then + inst_latch_data_next <= inst_r; + + case(inst_opcode) is + when SEARCH_INSTANCE => + -- Reset Data + inst_data_next <= ZERO_INSTANCE_DATA; + inst_data_next.i <= inst_r.i; + + -- No Instances available + if (inst_occupied_head(inst_r.i) /= INSTANCE_MEMORY_MAX_ADDRESS) then + inst_addr_base_next <= inst_occupied_head(inst_r.i); + inst_stage_next <= SEARCH_INSTANCE; + inst_cnt_next <= 0; + end if; + when INSERT_INSTANCE => + assert (inst_empty_head(inst_r.i) /= INSTANCE_MEMORY_MAX_ADDRESS) severity FAILURE; + + inst_data_next <= ZERO_INSTANCE_DATA; + inst_data_next.i <= inst_r.i; + + inst_data_next.addr <= inst_empty_head(inst_r.i); + inst_addr_base_next <= inst_empty_head(inst_r.i); + inst_stage_next <= INSERT_INSTANCE; + inst_cnt_next <= 0; + when UPDATE_INSTANCE => + if (inst_r.addr = INSTANCE_MEMORY_MAX_ADDRESS) then + inst_data_next <= ZERO_INSTANCE_DATA; + inst_data_next.i <= inst_r.i; + else + if (inst_r.i /= inst_data.i or inst_r.addr /= inst_data.addr) then + inst_data_next <= ZERO_INSTANCE_DATA; + inst_data_next.i <= inst_r.i; + end if; + + inst_data_next.addr <= inst_r.addr; + inst_addr_base_next <= inst_r.addr; + inst_stage_next <= UPDATE_INSTANCE; + if check_mask(inst_r.field_flags,IMF_STATUS_FLAG) then + inst_cnt_next <= 0; + elsif check_mask(inst_r.field_flags,IMF_SAMPLE_CNT_FLAG) then + inst_cnt_next <= 1; + elsif check_mask(inst_r.field_flags,IMF_ACK_CNT_FLAG) then + inst_cnt_next <= 2; + else + -- DONE + inst_stage_next <= IDLE; + end if; + end if; + when REMOVE_INSTANCE => + inst_data_next <= ZERO_INSTANCE_DATA; + inst_data_next.i <= inst_r.i; + + if (inst_r.addr /= INSTANCE_MEMORY_MAX_ADDRESS) then + inst_addr_base_next <= inst_r.addr; + inst_stage_next <= REMOVE_INSTANCE; + inst_cnt_next <= 0; + end if; + when GET_NEXT_INSTANCE => + inst_data_next <= ZERO_INSTANCE_DATA; + inst_data_next.i <= inst_r.i; + + -- No Instances available + if (inst_r.addr /= INSTANCE_MEMORY_MAX_ADDRESS) then + inst_addr_base_next <= inst_r.addr; + inst_stage_next <= GET_NEXT_INSTANCE; + inst_cnt_next <= 0; + end if; + when GET_INSTANCE => + if (inst_r.addr = INSTANCE_MEMORY_MAX_ADDRESS) then + inst_data_next <= ZERO_INSTANCE_DATA; + inst_data_next.i <= inst_r.i; + else + if (inst_r.i /= inst_data.i or inst_r.addr /= inst_data.addr) then + inst_data_next <= ZERO_INSTANCE_DATA; + inst_data_next.i <= inst_r.i; + end if; + + inst_data_next.addr <= inst_r.addr; + inst_addr_base_next <= inst_r.addr; + inst_stage_next <= GET_INSTANCE_DATA; + if check_mask(inst_r.field_flags,IMF_KEY_HASH_FLAG) then + inst_cnt_next <= 0; + elsif check_mask(inst_r.field_flags,IMF_STATUS_FLAG) then + inst_cnt_next <= 4; + elsif check_mask(inst_r.field_flags,IMF_SAMPLE_CNT_FLAG) then + inst_cnt_next <= 5; + elsif check_mask(inst_r.field_flags,IMF_ACK_CNT_FLAG) then + inst_cnt_next <= 6; + else + -- DONE + inst_stage_next <= IDLE; + end if; + end if; + when others => + null; + end case; + end if; + when SEARCH_INSTANCE => + + case (inst_cnt) is + -- GET Key Hash 1/4 + when 0 => + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_KEY_HASH_OFFSET; + inst_read <= '1'; + + -- Memory Flow Control Guard + if (inst_ready_in = '1') then + inst_cnt_next <= inst_cnt + 1; + end if; + -- GET Key Hash 2/4 + when 1 => + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_KEY_HASH_OFFSET + 1; + inst_read <= '1'; + + -- Memory Flow Control Guard + if (inst_ready_in = '1') then + inst_cnt_next <= inst_cnt + 1; + end if; + -- GET Key Hash 3/4 + when 2 => + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_KEY_HASH_OFFSET + 2; + inst_read <= '1'; + + -- Memory Flow Control Guard + if (inst_ready_in = '1') then + inst_cnt_next <= inst_cnt + 1; + end if; + -- GET Key Hash 4/4 + when 3 => + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_KEY_HASH_OFFSET + 3; + inst_read <= '1'; + + -- Memory Flow Control Guard + if (inst_ready_in = '1') then + inst_cnt_next <= inst_cnt + 1; + end if; + -- READ Key Hash 1/4 + when 4 => + inst_ready_out <= '1'; + + -- Memory Flow Control Guard + if (inst_valid_out = '1') then + -- No Match + if (inst_read_data /= inst_latch_data.key_hash(0)) then + inst_abort_read <= '1'; + inst_cnt_next <= 8; -- GET NEXT INSTANCE + else + inst_cnt_next <= inst_cnt + 1; + end if; + end if; + -- READ Key Hash 2/4 + when 5 => + inst_ready_out <= '1'; + + -- Memory Flow Control Guard + if (inst_valid_out = '1') then + -- No Match + if (inst_read_data /= inst_latch_data.key_hash(1)) then + inst_abort_read <= '1'; + inst_cnt_next <= 8; -- GET NEXT INSTANCE + else + inst_cnt_next <= inst_cnt + 1; + end if; + end if; + -- READ Key Hash 3/4 + when 6 => + inst_ready_out <= '1'; + + -- Memory Flow Control Guard + if (inst_valid_out = '1') then + -- No Match + if (inst_read_data /= inst_latch_data.key_hash(2)) then + inst_abort_read <= '1'; + inst_cnt_next <= 8; -- GET NEXT INSTANCE + else + inst_cnt_next <= inst_cnt + 1; + end if; + end if; + -- READ Key Hash 4/4 + when 7 => + inst_ready_out <= '1'; + + -- Memory Flow Control Guard + if (inst_valid_out = '1') then + -- No Match + if (inst_read_data /= inst_latch_data.key_hash(3)) then + inst_cnt_next <= 8; -- GET NEXT INSTANCE + else + inst_data_next.addr <= inst_addr_base; + -- Get Instance Data + inst_stage_next <= GET_INSTANCE_DATA; + if check_mask(inst_latch_data.field_flags,IMF_KEY_HASH_FLAG) then + inst_cnt_next <= 0; + elsif check_mask(inst_latch_data.field_flags,IMF_STATUS_FLAG) then + inst_cnt_next <= 4; + elsif check_mask(inst_latch_data.field_flags,IMF_SAMPLE_CNT_FLAG) then + inst_cnt_next <= 5; + elsif check_mask(inst_latch_data.field_flags,IMF_ACK_CNT_FLAG) then + inst_cnt_next <= 6; + else + -- DONE + inst_stage_next <= IDLE; + end if; + end if; + end if; + -- GET Next Instance + when 8 => + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_NEXT_ADDR_OFFSET; + inst_read <= '1'; + + -- Memory Flow Control Guard + if (inst_ready_in = '1') then + inst_cnt_next <= inst_cnt + 1; + end if; + -- READ Next Instance + when 9 => + inst_ready_out <= '1'; + + -- Memory Flow Control Guard + if (inst_valid_out = '1') then + -- No more Endpoints + if (resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH) = INSTANCE_MEMORY_MAX_ADDRESS) then + inst_data_next.addr <= INSTANCE_MEMORY_MAX_ADDRESS; --No match + -- DONE + inst_stage_next <= IDLE; + else + -- Continue + inst_addr_base_next <= resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH); + inst_cnt_next <= 0; + end if; + end if; + when others => + null; + end case; + when GET_NEXT_INSTANCE => + case (inst_cnt) is + -- GET Next Instance + when 0 => + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_NEXT_ADDR_OFFSET; + inst_read <= '1'; + + -- Memory Flow Control Guard + if (inst_ready_in = '1') then + inst_cnt_next <= inst_cnt + 1; + end if; + -- READ Next Instance + when 1 => + inst_ready_out <= '1'; + + -- Memory Flow Control Guard + if (inst_valid_out = '1') then + if (resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH) = INSTANCE_MEMORY_MAX_ADDRESS) then + inst_data_next.addr <= INSTANCE_MEMORY_MAX_ADDRESS; + -- DONE + inst_stage_next <= IDLE; + else + inst_data_next.addr <= resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH); + + -- Get Instance Data + inst_addr_base_next <= resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH); + inst_stage_next <= GET_INSTANCE_DATA; + if check_mask(inst_latch_data.field_flags,IMF_KEY_HASH_FLAG) then + inst_cnt_next <= 0; + elsif check_mask(inst_latch_data.field_flags,IMF_STATUS_FLAG) then + inst_cnt_next <= 4; + elsif check_mask(inst_latch_data.field_flags,IMF_SAMPLE_CNT_FLAG) then + inst_cnt_next <= 5; + elsif check_mask(inst_latch_data.field_flags,IMF_ACK_CNT_FLAG) then + inst_cnt_next <= 6; + else + -- DONE + inst_stage_next <= IDLE; + end if; + end if; + end if; + when others => + null; + end case; + when GET_INSTANCE_DATA => + case (inst_cnt) is + -- GET Key Hash 1/4 + when 0 => + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_KEY_HASH_OFFSET; + inst_read <= '1'; + + -- Memory Flow Control Guard + if (inst_ready_in = '1') then + inst_cnt_next <= inst_cnt + 1; + end if; + -- GET Key Hash 2/4 + when 1 => + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_KEY_HASH_OFFSET + 1; + inst_read <= '1'; + + -- Memory Flow Control Guard + if (inst_ready_in = '1') then + inst_cnt_next <= inst_cnt + 1; + end if; + -- GET Key Hash 3/4 + when 2 => + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_KEY_HASH_OFFSET + 2; + inst_read <= '1'; + + -- Memory Flow Control Guard + if (inst_ready_in = '1') then + inst_cnt_next <= inst_cnt + 1; + end if; + -- GET Key Hash 4/4 + when 3 => + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_KEY_HASH_OFFSET + 3; + inst_read <= '1'; + + -- Memory Flow Control Guard + if (inst_ready_in = '1') then + if check_mask(inst_latch_data.field_flags,IMF_STATUS_FLAG) then + inst_cnt_next <= 4; + elsif check_mask(inst_latch_data.field_flags,IMF_SAMPLE_CNT_FLAG) then + inst_cnt_next <= 5; + elsif check_mask(inst_latch_data.field_flags,IMF_ACK_CNT_FLAG) then + inst_cnt_next <= 6; + else + inst_cnt_next <= 7; + end if; + end if; + -- GET Status Info + when 4 => + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_STATUS_INFO_OFFSET; + inst_read <= '1'; + + -- Memory Flow Control Guard + if (inst_ready_in = '1') then + if check_mask(inst_latch_data.field_flags,IMF_SAMPLE_CNT_FLAG) then + inst_cnt_next <= 5; + elsif check_mask(inst_latch_data.field_flags,IMF_ACK_CNT_FLAG) then + inst_cnt_next <= 6; + else + if check_mask(inst_latch_data.field_flags,IMF_KEY_HASH_FLAG) then + inst_cnt_next <= 7; + else + inst_cnt_next <= 11; + end if; + end if; + end if; + -- GET Sample Count + when 5 => + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_SAMPLE_CNT_OFFSET; + inst_read <= '1'; + + -- Memory Flow Control Guard + if (inst_ready_in = '1') then + if check_mask(inst_latch_data.field_flags,IMF_ACK_CNT_FLAG) then + inst_cnt_next <= 6; + else + if check_mask(inst_latch_data.field_flags,IMF_KEY_HASH_FLAG) then + inst_cnt_next <= 7; + elsif check_mask(inst_latch_data.field_flags,IMF_STATUS_FLAG) then + inst_cnt_next <= 11; + else + inst_cnt_next <= 12; + end if; + end if; + end if; + -- GET ACK Count + when 6 => + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_ACK_CNT_OFFSET; + inst_read <= '1'; + + -- Memory Flow Control Guard + if (inst_ready_in = '1') then + if check_mask(inst_latch_data.field_flags,IMF_KEY_HASH_FLAG) then + inst_cnt_next <= 7; + elsif check_mask(inst_latch_data.field_flags,IMF_STATUS_FLAG) then + inst_cnt_next <= 11; + elsif check_mask(inst_latch_data.field_flags,IMF_SAMPLE_CNT_FLAG) then + inst_cnt_next <= 12; + else + inst_cnt_next <= 13; + end if; + end if; + -- READ Key Hash 1/4 + when 7 => + inst_ready_out <= '1'; + + -- Memory Flow Control Guard + if (inst_valid_out = '1') then + inst_data_next.key_hash(0) <= inst_read_data; + inst_cnt_next <= inst_cnt + 1; + end if; + -- READ Key Hash 2/4 + when 8 => + inst_ready_out <= '1'; + + -- Memory Flow Control Guard + if (inst_valid_out = '1') then + inst_data_next.key_hash(1) <= inst_read_data; + inst_cnt_next <= inst_cnt + 1; + end if; + -- READ Key Hash 3/4 + when 9 => + inst_ready_out <= '1'; + + -- Memory Flow Control Guard + if (inst_valid_out = '1') then + inst_data_next.key_hash(2) <= inst_read_data; + inst_cnt_next <= inst_cnt + 1; + end if; + -- READ Key Hash 4/4 + when 10 => + inst_ready_out <= '1'; + + -- Memory Flow Control Guard + if (inst_valid_out = '1') then + inst_data_next.key_hash(3) <= inst_read_data; + inst_data_next.field_flags <= inst_data.field_flags or IMF_KEY_HASH_FLAG; + + if check_mask(inst_latch_data.field_flags,IMF_STATUS_FLAG) then + inst_cnt_next <= 11; + elsif check_mask(inst_latch_data.field_flags,IMF_SAMPLE_CNT_FLAG) then + inst_cnt_next <= 12; + elsif check_mask(inst_latch_data.field_flags,IMF_ACK_CNT_FLAG) then + inst_cnt_next <= 13; + else + -- DONE + inst_stage_next <= IDLE; + end if; + end if; + -- READ Status Info + when 11 => + inst_ready_out <= '1'; + + -- Memory Flow Control Guard + if (inst_valid_out = '1') then + inst_data_next.status_info <= inst_read_data; + inst_data_next.field_flags <= inst_data.field_flags or IMF_STATUS_FLAG; + + if check_mask(inst_latch_data.field_flags,IMF_SAMPLE_CNT_FLAG) then + inst_cnt_next <= 12; + elsif check_mask(inst_latch_data.field_flags,IMF_ACK_CNT_FLAG) then + inst_cnt_next <= 13; + else + -- DONE + inst_stage_next <= IDLE; + end if; + end if; + -- READ Sample Count + when 12 => + inst_ready_out <= '1'; + + -- Memory Flow Control Guard + if (inst_valid_out = '1') then + inst_data_next.sample_cnt <= unsigned(inst_read_data); + inst_data_next.field_flags <= inst_data.field_flags or IMF_SAMPLE_CNT_FLAG; + + if check_mask(inst_latch_data.field_flags,IMF_ACK_CNT_FLAG) then + inst_cnt_next <= 13; + else + -- DONE + inst_stage_next <= IDLE; + end if; + end if; + -- READ ACK Count + when 13 => + inst_ready_out <= '1'; + + -- Memory Flow Control Guard + if (inst_valid_out = '1') then + inst_data_next.ack_cnt <= unsigned(inst_read_data); + inst_data_next.field_flags <= inst_data.field_flags or IMF_ACK_CNT_FLAG; + + -- DONE + inst_stage_next <= IDLE; + end if; + end case; + when INSERT_INSTANCE => + case (inst_cnt) is + -- GET Next Instance + when 0 => + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_NEXT_ADDR_OFFSET; + inst_read <= '1'; + + -- Memory Flow Control Guard + if (inst_ready_in = '1') then + inst_cnt_next <= inst_cnt + 1; + end if; + -- SET Key Hash 1/4 + when 1 => + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_KEY_HASH_OFFSET; + inst_write_data <= inst_latch_data.key_hash(0); + + -- Memory Flow Control Guard + if (inst_ready_in = '1') then + inst_cnt_next <= inst_cnt + 1; + end if; + -- SET Key Hash 2/4 + when 2 => + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_KEY_HASH_OFFSET + 1; + inst_write_data <= inst_latch_data.key_hash(1); + + -- Memory Flow Control Guard + if (inst_ready_in = '1') then + inst_cnt_next <= inst_cnt + 1; + end if; + -- SET Key Hash 3/4 + when 3 => + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_KEY_HASH_OFFSET + 2; + inst_write_data <= inst_latch_data.key_hash(2); + + -- Memory Flow Control Guard + if (inst_ready_in = '1') then + inst_cnt_next <= inst_cnt + 1; + end if; + -- SET Key Hash 4/4 + when 4 => + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_KEY_HASH_OFFSET + 3; + inst_write_data <= inst_latch_data.key_hash(3); + inst_data_next.field_flags <= inst_data.field_flags or IMF_KEY_HASH_FLAG; + + -- Memory Flow Control Guard + if (inst_ready_in = '1') then + inst_cnt_next <= inst_cnt + 1; + end if; + -- SET Status Info + when 5 => + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_STATUS_INFO_OFFSET; + inst_write_data <= inst_latch_data.status_info; + inst_data_next.field_flags <= inst_data.field_flags or IMF_STATUS_FLAG; + + -- Memory Flow Control Guard + if (inst_ready_in = '1') then + inst_cnt_next <= inst_cnt + 1; + end if; + -- SET Sample Count + when 6 => + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_SAMPLE_CNT_OFFSET; + inst_write_data <= std_logic_vector(inst_latch_data.sample_cnt); + inst_data_next.field_flags <= inst_data.field_flags or IMF_SAMPLE_CNT_FLAG; + + -- Memory Flow Control Guard + if (inst_ready_in = '1') then + inst_cnt_next <= inst_cnt + 1; + end if; + -- SET ACK Count + when 7 => + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_ACK_CNT_OFFSET; + inst_write_data <= std_logic_vector(inst_latch_data.ack_cnt); + inst_data_next.field_flags <= inst_data.field_flags or IMF_ACK_CNT_FLAG; + + -- Memory Flow Control Guard + if (inst_ready_in = '1') then + inst_cnt_next <= inst_cnt + 1; + end if; + -- SET Next Addr + when 8 => + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_NEXT_ADDR_OFFSET; + inst_write_data <= std_logic_vector(resize(inst_occupied_head(inst_latch_data.i),WORD_WIDTH)); + + -- Memory Flow Control Guard + if (inst_ready_in = '1') then + inst_cnt_next <= inst_cnt + 1; + end if; + -- SET Prev Addr + when 9 => + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_PREV_ADDR_OFFSET; + inst_write_data <= std_logic_vector(resize(INSTANCE_MEMORY_MAX_ADDRESS,WORD_WIDTH)); + + -- Memory Flow Control Guard + if (inst_ready_in = '1') then + if (inst_occupied_head(inst_latch_data.i) = INSTANCE_MEMORY_MAX_ADDRESS) then + inst_cnt_next <= inst_cnt + 2; -- Skip Next Step + else + inst_cnt_next <= inst_cnt + 1; + end if; + end if; + -- SET Prev Addr (Occupied Head) + when 10 => + inst_valid_in <= '1'; + inst_addr <= inst_occupied_head(inst_latch_data.i) + IMF_PREV_ADDR_OFFSET; + inst_write_data <= std_logic_vector(resize(inst_addr_base,WORD_WIDTH)); + + -- Memory Flow Control Guard + if (inst_ready_in = '1') then + inst_cnt_next <= inst_cnt + 1; + end if; + -- READ Next Addr + when 11 => + inst_ready_out <= '1'; + -- Memory Flow Control Guard + if (inst_valid_out = '1') then + + -- Update List Heads + inst_empty_head_next(inst_latch_data.i) <= resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH); + inst_occupied_head_next(inst_latch_data.i) <= inst_addr_base; + + -- DONE + inst_stage_next <= IDLE; + end if; + when others => + null; + end case; + when UPDATE_INSTANCE => + case (inst_cnt) is + -- Status Info + when 0 => + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_STATUS_INFO_OFFSET; + inst_write_data <= inst_latch_data.status_info; + inst_data_next.status_info <= inst_latch_data.status_info; + inst_data_next.field_flags <= inst_data.field_flags or IMF_STATUS_FLAG; + -- Memory Flow Control Guard + if (inst_ready_in = '1') then + if check_mask(inst_latch_data.field_flags,IMF_SAMPLE_CNT_FLAG) then + inst_cnt_next <= 1; + elsif check_mask(inst_latch_data.field_flags,IMF_ACK_CNT_FLAG) then + inst_cnt_next <= 2; + else + -- DONE + inst_stage_next <= IDLE; + end if; + end if; + -- Sample Count + when 1 => + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_SAMPLE_CNT_OFFSET; + inst_write_data <= std_logic_vector(inst_latch_data.sample_cnt); + inst_data_next.sample_cnt <= inst_latch_data.sample_cnt; + inst_data_next.field_flags <= inst_data.field_flags or IMF_SAMPLE_CNT_FLAG; + -- Memory Flow Control Guard + if (inst_ready_in = '1') then + if check_mask(inst_latch_data.field_flags,IMF_ACK_CNT_FLAG) then + inst_cnt_next <= 2; + else + -- DONE + inst_stage_next <= IDLE; + end if; + end if; + -- ACK Count + when 2 => + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_ACK_CNT_OFFSET; + inst_write_data <= std_logic_vector(inst_latch_data.ack_cnt); + inst_data_next.ack_cnt <= inst_latch_data.ack_cnt; + inst_data_next.field_flags <= inst_data.field_flags or IMF_ACK_CNT_FLAG; + -- Memory Flow Control Guard + if (inst_ready_in = '1') then + -- DONE + inst_stage_next <= IDLE; + end if; + when others => + null; + end case; + when REMOVE_INSTANCE => + case (inst_cnt) is + -- GET Next Addr + when 0 => + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_NEXT_ADDR_OFFSET; + inst_read <= '1'; + -- Memory Flow Control Guard + if (inst_ready_in = '1') then + inst_cnt_next <= inst_cnt + 1; + end if; + -- GET Prev Addr + when 1 => + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_PREV_ADDR_OFFSET; + inst_read <= '1'; + -- Memory Flow Control Guard + if (inst_ready_in = '1') then + inst_cnt_next <= inst_cnt + 1; + end if; + -- SET Next Addr + when 2 => + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_NEXT_ADDR_OFFSET; + inst_write_data <= std_logic_vector(resize(inst_empty_head(inst_latch_data.i),WORD_WIDTH)); + + if (inst_ready_in = '1') then + -- Set New Empty Head + inst_empty_head_next(inst_latch_data.i) <= inst_addr_base; + + inst_cnt_next <= inst_cnt + 1; + end if; + -- READ Next Addr + when 3 => + inst_ready_out <= '1'; + -- Memory Flow Control Guard + if (inst_valid_out = '1') then + inst_addr_latch_next <= resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH); + inst_cnt_next <= inst_cnt + 1; + end if; + -- READ Prev Addr + when 4 => + inst_ready_out <= '1'; + -- Memory Flow Control Guard + if (inst_valid_out = '1') then + if (inst_addr_latch = INSTANCE_MEMORY_MAX_ADDRESS) then + if (resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH) = INSTANCE_MEMORY_MAX_ADDRESS) then + -- RESET Occupied List Head + inst_occupied_head_next(inst_latch_data.i) <= INSTANCE_MEMORY_MAX_ADDRESS; + + inst_data_next.addr <= INSTANCE_MEMORY_MAX_ADDRESS; + -- DONE + inst_stage_next <= IDLE; + else + inst_addr_base_next <= resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH); + inst_cnt_next <= inst_cnt + 2; -- Skip Next Step + end if; + else + inst_addr_base_next <= inst_addr_latch; + inst_addr_latch_next <= resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH); + inst_cnt_next <= inst_cnt + 1; + end if; + end if; + -- SET Prev Addr (Next Slot) + when 5 => + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_PREV_ADDR_OFFSET; + inst_write_data <= std_logic_vector(resize(inst_addr_latch,WORD_WIDTH)); + + if (inst_ready_in = '1') then + if (inst_addr_latch = INSTANCE_MEMORY_MAX_ADDRESS) then + -- Set New Occupied List Head + inst_occupied_head_next(inst_latch_data.i) <= inst_addr_base; + + inst_data_next.addr <= inst_addr_base; + -- DONE + inst_stage_next <= IDLE; + else + inst_addr_base_next <= inst_addr_latch; + inst_addr_latch_next <= inst_addr_base; + inst_cnt_next <= inst_cnt + 1; + end if; + end if; + -- SET Next Addr (Previous Slot) + when 6 => + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_NEXT_ADDR_OFFSET; + inst_write_data <= std_logic_vector(resize(inst_addr_latch,WORD_WIDTH)); + + if (inst_ready_in = '1') then + inst_data_next.addr <= inst_addr_latch; + -- DONE + inst_stage_next <= IDLE; + end if; + when others => + null; + end case; + when RESET_MEMORY => + case (inst_cnt) is + -- SET Next Pointer + when 0 => + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_NEXT_ADDR_OFFSET; + if (inst_addr_base = MAX_INSTANCE_ADDRESS(inst_latch_data.i)) then + inst_write_data <= std_logic_vector(resize(INSTANCE_MEMORY_MAX_ADDRESS,WORD_WIDTH)); + else + inst_write_data <= std_logic_vector(resize(inst_addr_base + INSTANCE_FRAME_SIZE,WORD_WIDTH)); end if; -- Memory Flow Control Guard - if (payload_ready_in = '1') then - if (cur_payload = MAX_PAYLOAD_ADDRESS) then - -- DONE - stage_next <= IDLE; - empty_payload_list_head_next <= FIRST_PAYLOAD_ADDRESS; + if (inst_ready_in = '1') then + inst_cnt_next <= inst_cnt + 1; + end if; + -- SET Previous Pointer + when 1 => + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_PREV_ADDR_OFFSET; + inst_write_data <= std_logic_vector(resize(inst_addr_latch,WORD_WIDTH)); + + -- Memory Flow Control Guard + if (inst_ready_in = '1') then + if (inst_addr_base = MAX_INSTANCE_ADDRESS(inst_latch_data.i)) then + -- Initialize Empty and Occupied Heads + inst_empty_head_next(inst_latch_data.i) <= FIRST_INSTANCE_ADDRESS; + inst_occupied_head_next(inst_latch_data.i) <= INSTANCE_MEMORY_MAX_ADDRESS; + + if (inst_latch_data.i = NUM_WRITERS-1) then + -- DONE + inst_stage_next <= IDLE; + else + -- NEXT MEMORY + inst_latch_data_next.i <= inst_latch_data.i + 1; + inst_addr_base_next <= FIRST_INSTANCE_ADDRESS; + inst_addr_latch_next <= INSTANCE_MEMORY_MAX_ADDRESS; + inst_cnt_next <= 0; + end if; else - cur_payload_next <= cur_payload + PAYLOAD_FRAME_SIZE; + inst_addr_latch_next <= inst_addr_base; + inst_addr_base_next <= inst_addr_base + INSTANCE_FRAME_SIZE; + inst_cnt_next <= 0; end if; end if; when others => @@ -3576,851 +4673,6 @@ begin end case; end process; - gen_inst_ctrl_prc : if WITH_KEY generate - - -- *Instance Memory Process* - -- STATE DESCRIPTION - -- IDLE Idle State. Done Signal is pulled high and Memory FSM accepts new memory operations - -- SEARCH_INSTANCE See Memory OPCODE Description - -- GET_NEXT_INSTANCE See Memory OPCODE Description - -- GET_INSTANCE_DATA Latch specified Instance Data for use by main process - -- INSERT_INSTANCE See Memory OPCODE Description - -- UPDATE_INSTANCE See Memory OPCODE Description - -- REMOVE_INSTANCE See Memory OPCODE Description - -- RESET_MEMORY Reset Endpoint Memory to Empty State - inst_ctrl_prc : process(all) - begin - -- DEFAULT Registered - inst_stage_next <= inst_stage; - inst_addr_base_next <= inst_addr_base; - inst_addr_latch_next <= inst_addr_latch; - inst_empty_head_next <= inst_empty_head; - inst_occupied_head_next <= inst_occupied_head; - inst_latch_data_next <= inst_latch_data; - inst_cnt_next <= inst_cnt; - inst_data_next <= inst_data; - inst_long_latch_next <= inst_long_latch; - -- DEFAULT Unregistered - inst_ready_out <= '0'; - inst_valid_in <= '0'; - inst_read <= '0'; - inst_op_done <= '0'; - inst_abort_read <= '0'; - inst_addr <= (others => '0'); - inst_write_data <= (others => '0'); - - - case (inst_stage) is - when IDLE => - inst_op_done <= '1'; - - if (inst_op_start = '1') then - inst_latch_data_next <= inst_r; - - case(inst_opcode) is - when SEARCH_INSTANCE => - -- Reset Data - inst_data_next <= ZERO_INSTANCE_DATA; - - -- No Instances available - if (inst_occupied_head /= INSTANCE_MEMORY_MAX_ADDRESS) then - inst_addr_base_next <= inst_occupied_head; - inst_stage_next <= SEARCH_INSTANCE; - inst_cnt_next <= 0; - end if; - when INSERT_INSTANCE => - assert (inst_empty_head /= INSTANCE_MEMORY_MAX_ADDRESS) severity FAILURE; - - inst_data_next <= ZERO_INSTANCE_DATA; - - inst_data_next.addr <= inst_empty_head; - inst_addr_base_next <= inst_empty_head; - inst_stage_next <= INSERT_INSTANCE; - inst_cnt_next <= 0; - when UPDATE_INSTANCE => - if (inst_r.addr = INSTANCE_MEMORY_MAX_ADDRESS) then - inst_data_next <= ZERO_INSTANCE_DATA; - else - if (inst_r.addr /= inst_data.addr) then - inst_data_next <= ZERO_INSTANCE_DATA; - end if; - - inst_data_next.addr <= inst_r.addr; - inst_addr_base_next <= inst_r.addr; - inst_stage_next <= UPDATE_INSTANCE; - if check_mask(inst_r.field_flags,IMF_STATUS_FLAG) then - inst_cnt_next <= 0; - elsif check_mask(inst_r.field_flags,IMF_SAMPLE_CNT_FLAG) then - inst_cnt_next <= 1; - elsif check_mask(inst_r.field_flags,IMF_ACK_CNT_FLAG) then - inst_cnt_next <= 2; - else - -- DONE - inst_stage_next <= IDLE; - end if; - end if; - when REMOVE_INSTANCE => - inst_data_next <= ZERO_INSTANCE_DATA; - - if (inst_r.addr /= INSTANCE_MEMORY_MAX_ADDRESS) then - inst_addr_base_next <= inst_r.addr; - inst_stage_next <= REMOVE_INSTANCE; - inst_cnt_next <= 0; - end if; - when GET_NEXT_INSTANCE => - inst_data_next <= ZERO_INSTANCE_DATA; - - -- No Instances available - if (inst_r.addr /= INSTANCE_MEMORY_MAX_ADDRESS) then - inst_addr_base_next <= inst_r.addr; - inst_stage_next <= GET_NEXT_INSTANCE; - inst_cnt_next <= 0; - end if; - when GET_INSTANCE => - if (inst_r.addr = INSTANCE_MEMORY_MAX_ADDRESS) then - inst_data_next <= ZERO_INSTANCE_DATA; - else - if (inst_r.addr /= inst_data.addr) then - inst_data_next <= ZERO_INSTANCE_DATA; - end if; - - inst_data_next.addr <= inst_r.addr; - inst_addr_base_next <= inst_r.addr; - inst_stage_next <= GET_INSTANCE_DATA; - if check_mask(inst_r.field_flags,IMF_KEY_HASH_FLAG) then - inst_cnt_next <= 0; - elsif check_mask(inst_r.field_flags,IMF_STATUS_FLAG) then - inst_cnt_next <= 4; - elsif check_mask(inst_r.field_flags,IMF_SAMPLE_CNT_FLAG) then - inst_cnt_next <= 5; - elsif check_mask(inst_r.field_flags,IMF_ACK_CNT_FLAG) then - inst_cnt_next <= 6; - else - -- DONE - inst_stage_next <= IDLE; - end if; - end if; - when others => - null; - end case; - end if; - when SEARCH_INSTANCE => - - case (inst_cnt) is - -- GET Key Hash 1/4 - when 0 => - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_KEY_HASH_OFFSET; - inst_read <= '1'; - - -- Memory Flow Control Guard - if (inst_ready_in = '1') then - inst_cnt_next <= inst_cnt + 1; - end if; - -- GET Key Hash 2/4 - when 1 => - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_KEY_HASH_OFFSET + 1; - inst_read <= '1'; - - -- Memory Flow Control Guard - if (inst_ready_in = '1') then - inst_cnt_next <= inst_cnt + 1; - end if; - -- GET Key Hash 3/4 - when 2 => - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_KEY_HASH_OFFSET + 2; - inst_read <= '1'; - - -- Memory Flow Control Guard - if (inst_ready_in = '1') then - inst_cnt_next <= inst_cnt + 1; - end if; - -- GET Key Hash 4/4 - when 3 => - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_KEY_HASH_OFFSET + 3; - inst_read <= '1'; - - -- Memory Flow Control Guard - if (inst_ready_in = '1') then - inst_cnt_next <= inst_cnt + 1; - end if; - -- READ Key Hash 1/4 - when 4 => - inst_ready_out <= '1'; - - -- Memory Flow Control Guard - if (inst_valid_out = '1') then - -- No Match - if (inst_read_data /= inst_latch_data.key_hash(0)) then - inst_abort_read <= '1'; - inst_cnt_next <= 8; -- GET NEXT INSTANCE - else - inst_cnt_next <= inst_cnt + 1; - end if; - end if; - -- READ Key Hash 2/4 - when 5 => - inst_ready_out <= '1'; - - -- Memory Flow Control Guard - if (inst_valid_out = '1') then - -- No Match - if (inst_read_data /= inst_latch_data.key_hash(1)) then - inst_abort_read <= '1'; - inst_cnt_next <= 8; -- GET NEXT INSTANCE - else - inst_cnt_next <= inst_cnt + 1; - end if; - end if; - -- READ Key Hash 3/4 - when 6 => - inst_ready_out <= '1'; - - -- Memory Flow Control Guard - if (inst_valid_out = '1') then - -- No Match - if (inst_read_data /= inst_latch_data.key_hash(2)) then - inst_abort_read <= '1'; - inst_cnt_next <= 8; -- GET NEXT INSTANCE - else - inst_cnt_next <= inst_cnt + 1; - end if; - end if; - -- READ Key Hash 4/4 - when 7 => - inst_ready_out <= '1'; - - -- Memory Flow Control Guard - if (inst_valid_out = '1') then - -- No Match - if (inst_read_data /= inst_latch_data.key_hash(3)) then - inst_cnt_next <= 8; -- GET NEXT INSTANCE - else - inst_data_next.addr <= inst_addr_base; - -- Get Instance Data - inst_stage_next <= GET_INSTANCE_DATA; - if check_mask(inst_latch_data.field_flags,IMF_KEY_HASH_FLAG) then - inst_cnt_next <= 0; - elsif check_mask(inst_latch_data.field_flags,IMF_STATUS_FLAG) then - inst_cnt_next <= 4; - elsif check_mask(inst_latch_data.field_flags,IMF_SAMPLE_CNT_FLAG) then - inst_cnt_next <= 5; - elsif check_mask(inst_latch_data.field_flags,IMF_ACK_CNT_FLAG) then - inst_cnt_next <= 6; - else - -- DONE - inst_stage_next <= IDLE; - end if; - end if; - end if; - -- GET Next Instance - when 8 => - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_NEXT_ADDR_OFFSET; - inst_read <= '1'; - - -- Memory Flow Control Guard - if (inst_ready_in = '1') then - inst_cnt_next <= inst_cnt + 1; - end if; - -- READ Next Instance - when 9 => - inst_ready_out <= '1'; - - -- Memory Flow Control Guard - if (inst_valid_out = '1') then - -- No more Endpoints - if (resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH) = INSTANCE_MEMORY_MAX_ADDRESS) then - inst_data_next.addr <= INSTANCE_MEMORY_MAX_ADDRESS; --No match - -- DONE - inst_stage_next <= IDLE; - else - -- Continue - inst_addr_base_next <= resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH); - inst_cnt_next <= 0; - end if; - end if; - when others => - null; - end case; - when GET_NEXT_INSTANCE => - case (inst_cnt) is - -- GET Next Instance - when 0 => - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_NEXT_ADDR_OFFSET; - inst_read <= '1'; - - -- Memory Flow Control Guard - if (inst_ready_in = '1') then - inst_cnt_next <= inst_cnt + 1; - end if; - -- READ Next Instance - when 1 => - inst_ready_out <= '1'; - - -- Memory Flow Control Guard - if (inst_valid_out = '1') then - if (resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH) = INSTANCE_MEMORY_MAX_ADDRESS) then - inst_data_next.addr <= INSTANCE_MEMORY_MAX_ADDRESS; - -- DONE - inst_stage_next <= IDLE; - else - inst_data_next.addr <= resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH); - - -- Get Instance Data - inst_addr_base_next <= resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH); - inst_stage_next <= GET_INSTANCE_DATA; - if check_mask(inst_latch_data.field_flags,IMF_KEY_HASH_FLAG) then - inst_cnt_next <= 0; - elsif check_mask(inst_latch_data.field_flags,IMF_STATUS_FLAG) then - inst_cnt_next <= 4; - elsif check_mask(inst_latch_data.field_flags,IMF_SAMPLE_CNT_FLAG) then - inst_cnt_next <= 5; - elsif check_mask(inst_latch_data.field_flags,IMF_ACK_CNT_FLAG) then - inst_cnt_next <= 6; - else - -- DONE - inst_stage_next <= IDLE; - end if; - end if; - end if; - when others => - null; - end case; - when GET_INSTANCE_DATA => - case (inst_cnt) is - -- GET Key Hash 1/4 - when 0 => - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_KEY_HASH_OFFSET; - inst_read <= '1'; - - -- Memory Flow Control Guard - if (inst_ready_in = '1') then - inst_cnt_next <= inst_cnt + 1; - end if; - -- GET Key Hash 2/4 - when 1 => - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_KEY_HASH_OFFSET + 1; - inst_read <= '1'; - - -- Memory Flow Control Guard - if (inst_ready_in = '1') then - inst_cnt_next <= inst_cnt + 1; - end if; - -- GET Key Hash 3/4 - when 2 => - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_KEY_HASH_OFFSET + 2; - inst_read <= '1'; - - -- Memory Flow Control Guard - if (inst_ready_in = '1') then - inst_cnt_next <= inst_cnt + 1; - end if; - -- GET Key Hash 4/4 - when 3 => - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_KEY_HASH_OFFSET + 3; - inst_read <= '1'; - - -- Memory Flow Control Guard - if (inst_ready_in = '1') then - if check_mask(inst_latch_data.field_flags,IMF_STATUS_FLAG) then - inst_cnt_next <= 4; - elsif check_mask(inst_latch_data.field_flags,IMF_SAMPLE_CNT_FLAG) then - inst_cnt_next <= 5; - elsif check_mask(inst_latch_data.field_flags,IMF_ACK_CNT_FLAG) then - inst_cnt_next <= 6; - else - inst_cnt_next <= 7; - end if; - end if; - -- GET Status Info - when 4 => - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_STATUS_INFO_OFFSET; - inst_read <= '1'; - - -- Memory Flow Control Guard - if (inst_ready_in = '1') then - if check_mask(inst_latch_data.field_flags,IMF_SAMPLE_CNT_FLAG) then - inst_cnt_next <= 5; - elsif check_mask(inst_latch_data.field_flags,IMF_ACK_CNT_FLAG) then - inst_cnt_next <= 6; - else - if check_mask(inst_latch_data.field_flags,IMF_KEY_HASH_FLAG) then - inst_cnt_next <= 7; - else - inst_cnt_next <= 11; - end if; - end if; - end if; - -- GET Sample Count - when 5 => - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_SAMPLE_CNT_OFFSET; - inst_read <= '1'; - - -- Memory Flow Control Guard - if (inst_ready_in = '1') then - if check_mask(inst_latch_data.field_flags,IMF_ACK_CNT_FLAG) then - inst_cnt_next <= 6; - else - if check_mask(inst_latch_data.field_flags,IMF_KEY_HASH_FLAG) then - inst_cnt_next <= 7; - elsif check_mask(inst_latch_data.field_flags,IMF_STATUS_FLAG) then - inst_cnt_next <= 11; - else - inst_cnt_next <= 12; - end if; - end if; - end if; - -- GET ACK Count - when 6 => - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_ACK_CNT_OFFSET; - inst_read <= '1'; - - -- Memory Flow Control Guard - if (inst_ready_in = '1') then - if check_mask(inst_latch_data.field_flags,IMF_KEY_HASH_FLAG) then - inst_cnt_next <= 7; - elsif check_mask(inst_latch_data.field_flags,IMF_STATUS_FLAG) then - inst_cnt_next <= 11; - elsif check_mask(inst_latch_data.field_flags,IMF_SAMPLE_CNT_FLAG) then - inst_cnt_next <= 12; - else - inst_cnt_next <= 13; - end if; - end if; - -- READ Key Hash 1/4 - when 7 => - inst_ready_out <= '1'; - - -- Memory Flow Control Guard - if (inst_valid_out = '1') then - inst_data_next.key_hash(0) <= inst_read_data; - inst_cnt_next <= inst_cnt + 1; - end if; - -- READ Key Hash 2/4 - when 8 => - inst_ready_out <= '1'; - - -- Memory Flow Control Guard - if (inst_valid_out = '1') then - inst_data_next.key_hash(1) <= inst_read_data; - inst_cnt_next <= inst_cnt + 1; - end if; - -- READ Key Hash 3/4 - when 9 => - inst_ready_out <= '1'; - - -- Memory Flow Control Guard - if (inst_valid_out = '1') then - inst_data_next.key_hash(2) <= inst_read_data; - inst_cnt_next <= inst_cnt + 1; - end if; - -- READ Key Hash 4/4 - when 10 => - inst_ready_out <= '1'; - - -- Memory Flow Control Guard - if (inst_valid_out = '1') then - inst_data_next.key_hash(3) <= inst_read_data; - inst_data_next.field_flags <= inst_data.field_flags or IMF_KEY_HASH_FLAG; - - if check_mask(inst_latch_data.field_flags,IMF_STATUS_FLAG) then - inst_cnt_next <= 11; - elsif check_mask(inst_latch_data.field_flags,IMF_SAMPLE_CNT_FLAG) then - inst_cnt_next <= 12; - elsif check_mask(inst_latch_data.field_flags,IMF_ACK_CNT_FLAG) then - inst_cnt_next <= 13; - else - -- DONE - inst_stage_next <= IDLE; - end if; - end if; - -- READ Status Info - when 11 => - inst_ready_out <= '1'; - - -- Memory Flow Control Guard - if (inst_valid_out = '1') then - inst_data_next.status_info <= inst_read_data; - inst_data_next.field_flags <= inst_data.field_flags or IMF_STATUS_FLAG; - - if check_mask(inst_latch_data.field_flags,IMF_SAMPLE_CNT_FLAG) then - inst_cnt_next <= 12; - elsif check_mask(inst_latch_data.field_flags,IMF_ACK_CNT_FLAG) then - inst_cnt_next <= 13; - else - -- DONE - inst_stage_next <= IDLE; - end if; - end if; - -- READ Sample Count - when 12 => - inst_ready_out <= '1'; - - -- Memory Flow Control Guard - if (inst_valid_out = '1') then - inst_data_next.sample_cnt <= unsigned(inst_read_data); - inst_data_next.field_flags <= inst_data.field_flags or IMF_SAMPLE_CNT_FLAG; - - if check_mask(inst_latch_data.field_flags,IMF_ACK_CNT_FLAG) then - inst_cnt_next <= 13; - else - -- DONE - inst_stage_next <= IDLE; - end if; - end if; - -- READ ACK Count - when 13 => - inst_ready_out <= '1'; - - -- Memory Flow Control Guard - if (inst_valid_out = '1') then - inst_data_next.ack_cnt <= unsigned(inst_read_data); - inst_data_next.field_flags <= inst_data.field_flags or IMF_ACK_CNT_FLAG; - - -- DONE - inst_stage_next <= IDLE; - end if; - end case; - when INSERT_INSTANCE => - case (inst_cnt) is - -- GET Next Instance - when 0 => - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_NEXT_ADDR_OFFSET; - inst_read <= '1'; - - -- Memory Flow Control Guard - if (inst_ready_in = '1') then - inst_cnt_next <= inst_cnt + 1; - end if; - -- SET Key Hash 1/4 - when 1 => - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_KEY_HASH_OFFSET; - inst_write_data <= inst_latch_data.key_hash(0); - - -- Memory Flow Control Guard - if (inst_ready_in = '1') then - inst_cnt_next <= inst_cnt + 1; - end if; - -- SET Key Hash 2/4 - when 2 => - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_KEY_HASH_OFFSET + 1; - inst_write_data <= inst_latch_data.key_hash(1); - - -- Memory Flow Control Guard - if (inst_ready_in = '1') then - inst_cnt_next <= inst_cnt + 1; - end if; - -- SET Key Hash 3/4 - when 3 => - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_KEY_HASH_OFFSET + 2; - inst_write_data <= inst_latch_data.key_hash(2); - - -- Memory Flow Control Guard - if (inst_ready_in = '1') then - inst_cnt_next <= inst_cnt + 1; - end if; - -- SET Key Hash 4/4 - when 4 => - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_KEY_HASH_OFFSET + 3; - inst_write_data <= inst_latch_data.key_hash(3); - inst_data_next.field_flags <= inst_data.field_flags or IMF_KEY_HASH_FLAG; - - -- Memory Flow Control Guard - if (inst_ready_in = '1') then - inst_cnt_next <= inst_cnt + 1; - end if; - -- SET Status Info - when 5 => - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_STATUS_INFO_OFFSET; - inst_write_data <= inst_latch_data.status_info; - inst_data_next.field_flags <= inst_data.field_flags or IMF_STATUS_FLAG; - - -- Memory Flow Control Guard - if (inst_ready_in = '1') then - inst_cnt_next <= inst_cnt + 1; - end if; - -- SET Sample Count - when 6 => - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_SAMPLE_CNT_OFFSET; - inst_write_data <= std_logic_vector(inst_latch_data.sample_cnt); - inst_data_next.field_flags <= inst_data.field_flags or IMF_SAMPLE_CNT_FLAG; - - -- Memory Flow Control Guard - if (inst_ready_in = '1') then - inst_cnt_next <= inst_cnt + 1; - end if; - -- SET ACK Count - when 7 => - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_ACK_CNT_OFFSET; - inst_write_data <= std_logic_vector(inst_latch_data.ack_cnt); - inst_data_next.field_flags <= inst_data.field_flags or IMF_ACK_CNT_FLAG; - - -- Memory Flow Control Guard - if (inst_ready_in = '1') then - inst_cnt_next <= inst_cnt + 1; - end if; - -- SET Next Addr - when 8 => - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_NEXT_ADDR_OFFSET; - inst_write_data <= std_logic_vector(resize(inst_occupied_head,WORD_WIDTH)); - - -- Memory Flow Control Guard - if (inst_ready_in = '1') then - inst_cnt_next <= inst_cnt + 1; - end if; - -- SET Prev Addr - when 9 => - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_PREV_ADDR_OFFSET; - inst_write_data <= std_logic_vector(resize(INSTANCE_MEMORY_MAX_ADDRESS,WORD_WIDTH)); - - -- Memory Flow Control Guard - if (inst_ready_in = '1') then - if (inst_occupied_head = INSTANCE_MEMORY_MAX_ADDRESS) then - inst_cnt_next <= inst_cnt + 2; -- Skip Next Step - else - inst_cnt_next <= inst_cnt + 1; - end if; - end if; - -- SET Prev Addr (Occupied Head) - when 10 => - inst_valid_in <= '1'; - inst_addr <= inst_occupied_head + IMF_PREV_ADDR_OFFSET; - inst_write_data <= std_logic_vector(resize(inst_addr_base,WORD_WIDTH)); - - -- Memory Flow Control Guard - if (inst_ready_in = '1') then - inst_cnt_next <= inst_cnt + 1; - end if; - -- READ Next Addr - when 11 => - inst_ready_out <= '1'; - -- Memory Flow Control Guard - if (inst_valid_out = '1') then - - -- Update List Heads - inst_empty_head_next <= resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH); - inst_occupied_head_next <= inst_addr_base; - - -- DONE - inst_stage_next <= IDLE; - end if; - when others => - null; - end case; - when UPDATE_INSTANCE => - case (inst_cnt) is - -- Status Info - when 0 => - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_STATUS_INFO_OFFSET; - inst_write_data <= inst_latch_data.status_info; - inst_data_next.status_info <= inst_latch_data.status_info; - inst_data_next.field_flags <= inst_data.field_flags or IMF_STATUS_FLAG; - -- Memory Flow Control Guard - if (inst_ready_in = '1') then - if check_mask(inst_latch_data.field_flags,IMF_SAMPLE_CNT_FLAG) then - inst_cnt_next <= 1; - elsif check_mask(inst_latch_data.field_flags,IMF_ACK_CNT_FLAG) then - inst_cnt_next <= 2; - else - -- DONE - inst_stage_next <= IDLE; - end if; - end if; - -- Sample Count - when 1 => - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_SAMPLE_CNT_OFFSET; - inst_write_data <= std_logic_vector(inst_latch_data.sample_cnt); - inst_data_next.sample_cnt <= inst_latch_data.sample_cnt; - inst_data_next.field_flags <= inst_data.field_flags or IMF_SAMPLE_CNT_FLAG; - -- Memory Flow Control Guard - if (inst_ready_in = '1') then - if check_mask(inst_latch_data.field_flags,IMF_ACK_CNT_FLAG) then - inst_cnt_next <= 2; - else - -- DONE - inst_stage_next <= IDLE; - end if; - end if; - -- ACK Count - when 2 => - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_ACK_CNT_OFFSET; - inst_write_data <= std_logic_vector(inst_latch_data.ack_cnt); - inst_data_next.ack_cnt <= inst_latch_data.ack_cnt; - inst_data_next.field_flags <= inst_data.field_flags or IMF_ACK_CNT_FLAG; - -- Memory Flow Control Guard - if (inst_ready_in = '1') then - -- DONE - inst_stage_next <= IDLE; - end if; - when others => - null; - end case; - when REMOVE_INSTANCE => - case (inst_cnt) is - -- GET Next Addr - when 0 => - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_NEXT_ADDR_OFFSET; - inst_read <= '1'; - -- Memory Flow Control Guard - if (inst_ready_in = '1') then - inst_cnt_next <= inst_cnt + 1; - end if; - -- GET Prev Addr - when 1 => - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_PREV_ADDR_OFFSET; - inst_read <= '1'; - -- Memory Flow Control Guard - if (inst_ready_in = '1') then - inst_cnt_next <= inst_cnt + 1; - end if; - -- SET Next Addr - when 2 => - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_NEXT_ADDR_OFFSET; - inst_write_data <= std_logic_vector(resize(inst_empty_head,WORD_WIDTH)); - - if (inst_ready_in = '1') then - -- Set New Empty Head - inst_empty_head_next <= inst_addr_base; - - inst_cnt_next <= inst_cnt + 1; - end if; - -- READ Next Addr - when 3 => - inst_ready_out <= '1'; - -- Memory Flow Control Guard - if (inst_valid_out = '1') then - inst_addr_latch_next <= resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH); - inst_cnt_next <= inst_cnt + 1; - end if; - -- READ Prev Addr - when 4 => - inst_ready_out <= '1'; - -- Memory Flow Control Guard - if (inst_valid_out = '1') then - if (inst_addr_latch = INSTANCE_MEMORY_MAX_ADDRESS) then - if (resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH) = INSTANCE_MEMORY_MAX_ADDRESS) then - -- RESET Occupied List Head - inst_occupied_head_next <= INSTANCE_MEMORY_MAX_ADDRESS; - - inst_data_next.addr <= INSTANCE_MEMORY_MAX_ADDRESS; - -- DONE - inst_stage_next <= IDLE; - else - inst_addr_base_next <= resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH); - inst_cnt_next <= inst_cnt + 2; -- Skip Next Step - end if; - else - inst_addr_base_next <= inst_addr_latch; - inst_addr_latch_next <= resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH); - inst_cnt_next <= inst_cnt + 1; - end if; - end if; - -- SET Prev Addr (Next Slot) - when 5 => - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_PREV_ADDR_OFFSET; - inst_write_data <= std_logic_vector(resize(inst_addr_latch,WORD_WIDTH)); - - if (inst_ready_in = '1') then - if (inst_addr_latch = INSTANCE_MEMORY_MAX_ADDRESS) then - -- Set New Occupied List Head - inst_occupied_head_next <= inst_addr_base; - - inst_data_next.addr <= inst_addr_base; - -- DONE - inst_stage_next <= IDLE; - else - inst_addr_base_next <= inst_addr_latch; - inst_addr_latch_next <= inst_addr_base; - inst_cnt_next <= inst_cnt + 1; - end if; - end if; - -- SET Next Addr (Previous Slot) - when 6 => - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_NEXT_ADDR_OFFSET; - inst_write_data <= std_logic_vector(resize(inst_addr_latch,WORD_WIDTH)); - - if (inst_ready_in = '1') then - inst_data_next.addr <= inst_addr_latch; - -- DONE - inst_stage_next <= IDLE; - end if; - when others => - null; - end case; - when RESET_MEMORY => - case (inst_cnt) is - -- SET Next Pointer - when 0 => - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_NEXT_ADDR_OFFSET; - if (inst_addr_base = MAX_INSTANCE_ADDRESS) then - inst_write_data <= std_logic_vector(resize(INSTANCE_MEMORY_MAX_ADDRESS,WORD_WIDTH)); - else - inst_write_data <= std_logic_vector(resize(inst_addr_base + INSTANCE_FRAME_SIZE,WORD_WIDTH)); - end if; - - -- Memory Flow Control Guard - if (inst_ready_in = '1') then - inst_cnt_next <= inst_cnt + 1; - end if; - -- SET Previous Pointer - when 1 => - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_PREV_ADDR_OFFSET; - inst_write_data <= std_logic_vector(resize(inst_addr_latch,WORD_WIDTH)); - - -- Memory Flow Control Guard - if (inst_ready_in = '1') then - if (inst_addr_base = MAX_INSTANCE_ADDRESS) then - -- Initialize Empty and Occupied Heads - inst_empty_head_next <= FIRST_INSTANCE_ADDRESS; - inst_occupied_head_next <= INSTANCE_MEMORY_MAX_ADDRESS; - - -- DONE - inst_stage_next <= IDLE; - else - inst_addr_latch_next <= inst_addr_base; - inst_addr_base_next <= inst_addr_base + INSTANCE_FRAME_SIZE; - inst_cnt_next <= 0; - end if; - end if; - when others => - null; - end case; - end case; - end process; - end generate; - sync_prc : process(clk) begin if rising_edge(clk) then @@ -4431,30 +4683,33 @@ begin instance_handle <= HANDLE_NIL; cc_instance_handle_sig <= HANDLE_NIL; sample_rej_last_inst <= HANDLE_NIL; - deadline_miss_last_inst <= HANDLE_NIL; + deadline_miss_last_inst <= (others => HANDLE_NIL); key_hash <= KEY_HASH_NIL; - deadline_time <= time + DEADLINE_QOS; + deadline_check_time <= TIME_ZERO; + for i in 0 to NUM_WRITERS-1 loop + deadline_time(i) <= time + CONFIG_ARRAY_T(i).DEADLINE_QOS; + lease_deadline(i) <= time + CONFIG_ARRAY_T(i).LEASE_DURATION; + end loop; lifespan_time <= TIME_INFINITE; source_ts <= TIME_INVALID; - timeout_time <= TIME_INVALID; - lease_deadline <= time + LEASE_DURATION; + timeout_check_time <= TIME_INVALID; + timeout_time <= (others => TIME_INVALID); + lease_check_time <= TIME_ZERO; cc_source_timestamp_sig <= TIME_INVALID; lifespan <= DURATION_INFINITE; - global_seq_nr <= FIRST_SEQUENCENUMBER; + global_seq_nr <= (others => FIRST_SEQUENCENUMBER); seq_nr <= SEQUENCENUMBER_UNKNOWN; cc_seq_nr_sig <= SEQUENCENUMBER_UNKNOWN; cc_kind_sig <= ALIVE; inst_data <= ZERO_INSTANCE_DATA; - if (not WITH_KEY) then - inst_data.field_flags <= (others => '1'); - end if; inst_latch_data <= ZERO_INSTANCE_DATA; + ind <= 0; cnt <= 0; cnt2 <= 0; cnt3 <= 0; - global_sample_cnt <= 0; - global_ack_cnt <= 0; - stale_inst_cnt <= 0; + global_sample_cnt <= (others => 0); + global_ack_cnt <= (others => 0); + stale_inst_cnt <= (others => 0); inst_cnt <= 0; remove_oldest_sample <= '0'; remove_oldest_inst_sample <= '0'; @@ -4462,22 +4717,23 @@ begin is_lifespan_check <= '0'; register_op <= '0'; lookup_op <= '0'; - ack_wait <= '0'; + ack_wait <= (others => '0'); + ack_wait_check <= '0'; is_ack <= '0'; is_rtps <= '0'; - data_available_sig <= '0'; + data_available_sig <= (others => '0'); orphan_samples <= '0'; - newest_sample <= SAMPLE_MEMORY_MAX_ADDRESS; - oldest_sample <= SAMPLE_MEMORY_MAX_ADDRESS; - empty_payload_list_head <= PAYLOAD_MEMORY_MAX_ADDRESS; - empty_sample_list_head <= SAMPLE_MEMORY_MAX_ADDRESS; - empty_sample_list_tail <= SAMPLE_MEMORY_MAX_ADDRESS; + newest_sample <= (others => SAMPLE_MEMORY_MAX_ADDRESS); + oldest_sample <= (others => SAMPLE_MEMORY_MAX_ADDRESS); + empty_payload_list_head <= (others => PAYLOAD_MEMORY_MAX_ADDRESS); + empty_sample_list_head <= (others => SAMPLE_MEMORY_MAX_ADDRESS); + empty_sample_list_tail <= (others => SAMPLE_MEMORY_MAX_ADDRESS); payload_addr_latch_1 <= (others => '0'); payload_addr_latch_2 <= (others => '0'); long_latch <= (others => '0'); - sample_addr_latch_1 <= (others => '0'); + sample_addr_latch_1 <= SAMPLE_MEMORY_MAX_ADDRESS; sample_addr_latch_2 <= (others => '0'); - sample_addr_latch_3 <= (others => '0'); + sample_addr_latch_3 <= FIRST_SAMPLE_ADDRESS; sample_addr_latch_4 <= (others => '0'); inst_addr_latch_1 <= (others => '0'); inst_addr_latch_2 <= (others => '0'); @@ -4485,14 +4741,14 @@ begin sample_rej_cnt <= (others => '0'); sample_rej_cnt_change <= (others => '0'); sample_rej_last_reason <= (others => '0'); - deadline_miss_cnt <= (others => '0'); - deadline_miss_cnt_change <= (others => '0'); - liveliness_lost_cnt <= (others => '0'); - liveliness_lost_cnt_change <= (others => '0'); - status_sig <= (others => '0'); + deadline_miss_cnt <= (others => (others => '0')); + deadline_miss_cnt_change <= (others => (others => '0')); + liveliness_lost_cnt <= (others => (others => '0')); + liveliness_lost_cnt_change <= (others => (others => '0')); + status_sig <= (others => (others => '0')); inst_addr_base <= FIRST_INSTANCE_ADDRESS; - inst_empty_head <= INSTANCE_MEMORY_MAX_ADDRESS; - inst_occupied_head <= INSTANCE_MEMORY_MAX_ADDRESS; + inst_empty_head <= (others => INSTANCE_MEMORY_MAX_ADDRESS); + inst_occupied_head <= (others => INSTANCE_MEMORY_MAX_ADDRESS); inst_addr_latch <= INSTANCE_MEMORY_MAX_ADDRESS; inst_long_latch <= (others => '0'); return_code_latch <= RETCODE_UNSUPPORTED; @@ -4505,10 +4761,13 @@ begin sample_rej_last_inst <= sample_rej_last_inst_next; deadline_miss_last_inst <= deadline_miss_last_inst_next; key_hash <= key_hash_next; + deadline_check_time <= deadline_check_time_next; deadline_time <= deadline_time_next; lifespan_time <= lifespan_time_next; source_ts <= source_ts_next; + timeout_check_time <= timeout_check_time_next; timeout_time <= timeout_time_next; + lease_check_time <= lease_check_time_next; lease_deadline <= lease_deadline_next; cc_source_timestamp_sig <= cc_source_timestamp_sig_next; lifespan <= lifespan_next; @@ -4516,12 +4775,9 @@ begin seq_nr <= seq_nr_next; cc_seq_nr_sig <= cc_seq_nr_sig_next; cc_kind_sig <= cc_kind_sig_next; - if (WITH_KEY) then - inst_data <= inst_data_next; - else - inst_data <= inst_data_next2; - end if; + inst_data <= inst_data_next; inst_latch_data <= inst_latch_data_next; + ind <= ind_next; cnt <= cnt_next; cnt2 <= cnt2_next; cnt3 <= cnt3_next; @@ -4536,6 +4792,7 @@ begin register_op <= register_op_next; lookup_op <= lookup_op_next; ack_wait <= ack_wait_next; + ack_wait_check <= ack_wait_check_next; is_ack <= is_ack_next; is_rtps <= is_rtps_next; data_available_sig <= data_available_sig_next; diff --git a/src/ros2/Tests/Level_2/L2_Testbench_ROS_Lib2.vhd b/src/ros2/Tests/Level_2/L2_Testbench_ROS_Lib2.vhd index e4612a0..8e75b53 100644 --- a/src/ros2/Tests/Level_2/L2_Testbench_ROS_Lib2.vhd +++ b/src/ros2/Tests/Level_2/L2_Testbench_ROS_Lib2.vhd @@ -358,122 +358,114 @@ begin ); end generate; - dds_endpoint_gen : for i in 0 to NUM_ENDPOINTS-2 generate - dds_endpoint_if : if (i < NUM_READERS) generate - dds_reader_inst : entity work.dds_reader(arch) - generic map ( - TIME_BASED_FILTER_QOS => ENDPOINT_CONFIG(i).TIME_BASED_FILTER_QOS, - DEADLINE_QOS => ENDPOINT_CONFIG(i).DEADLINE_QOS, - MAX_INSTANCES => ENDPOINT_CONFIG(i).MAX_INSTANCES, - MAX_SAMPLES_PER_INSTANCE => ENDPOINT_CONFIG(i).MAX_SAMPLES_PER_INSTANCE, - MAX_SAMPLES => ENDPOINT_CONFIG(i).MAX_SAMPLES, - HISTORY_QOS => ENDPOINT_CONFIG(i).HISTORY_QOS, - RELIABILITY_QOS => ENDPOINT_CONFIG(i).RELIABILITY_QOS, - PRESENTATION_QOS => ENDPOINT_CONFIG(i).PRESENTATION_QOS, - DESTINATION_ORDER_QOS => ENDPOINT_CONFIG(i).DESTINATION_ORDER_QOS, - COHERENT_ACCESS => ENDPOINT_CONFIG(i).COHERENT_ACCESS, - ORDERED_ACCESS => ENDPOINT_CONFIG(i).ORDERED_ACCESS, - WITH_KEY => ENDPOINT_CONFIG(i).WITH_KEY, - PAYLOAD_FRAME_SIZE => ENDPOINT_CONFIG(i).MAX_PAYLOAD_SIZE, - MAX_REMOTE_ENDPOINTS => MAX_REMOTE_ENDPOINTS - ) - port map ( - -- SYSTEM - clk => clk, - reset => reset, - time => time, - -- FROM RTPS ENDPOINT - start_rtps => start_rr_dr(i), - opcode_rtps => opcode_rr_dr(i), - ack_rtps => ack_dr_rr(i), - done_rtps => done_dr_rr(i), - ret_rtps => ret_dr_rr(i), - valid_in_rtps => valid_rr_dr(i), - ready_in_rtps => ready_dr_rr(i), - data_in_rtps => data_rr_dr(i), - last_word_in_rtps => last_word_rr_dr(i), - -- TO USER ENTITY - start_dds => start_ri_dr(i), - ack_dds => ack_dr_ri(i), - opcode_dds => opcode_ri_dr(i), - instance_state_dds => instance_state_ri_dr(i), - view_state_dds => view_state_ri_dr(i), - sample_state_dds => sample_state_ri_dr(i), - instance_handle_dds => instance_handle_ri_dr(i), - max_samples_dds => max_samples_ri_dr(i), - get_data_dds => get_data_ri_dr(i), - done_dds => done_dr_ri(i), - return_code_dds => return_code_dr_ri(i), - valid_out_dds => valid_dr_ri(i), - ready_out_dds => ready_ri_dr(i), - data_out_dds => data_dr_ri(i), - last_word_out_dds => last_word_dr_ri(i), - sample_info => sample_info_dr_ri(i), - sample_info_valid => sample_info_valid_dr_ri(i), - sample_info_ack => sample_info_ack_ri_dr(i), - eoc => eoc_dr_ri(i), - -- Communication Status - status => status_dr_ri(i) - ); - else generate - dds_writer_inst : entity work.dds_writer(arch) - generic map ( - HISTORY_QOS => ENDPOINT_CONFIG(i).HISTORY_QOS, - DEADLINE_QOS => ENDPOINT_CONFIG(i).DEADLINE_QOS, - LIFESPAN_QOS => ENDPOINT_CONFIG(i).LIFESPAN_QOS, - LEASE_DURATION => ENDPOINT_CONFIG(i).LEASE_DURATION, - WITH_KEY => ENDPOINT_CONFIG(i).WITH_KEY, - MAX_SAMPLES => ENDPOINT_CONFIG(i).MAX_SAMPLES, - MAX_INSTANCES => ENDPOINT_CONFIG(i).MAX_INSTANCES, - MAX_SAMPLES_PER_INSTANCE => ENDPOINT_CONFIG(i).MAX_SAMPLES_PER_INSTANCE, - PAYLOAD_FRAME_SIZE => ENDPOINT_CONFIG(i).MAX_PAYLOAD_SIZE - ) - port map ( - -- SYSTEM - clk => clk, - reset => reset, - time => time, - -- TO/FROM RTPS ENDPOINT - start_rtps => start_rw_dw(i-NUM_READERS), - opcode_rtps => opcode_rw_dw(i-NUM_READERS), - ack_rtps => ack_dw_rw(i-NUM_READERS), - done_rtps => done_rw_dw(i-NUM_READERS), - ret_rtps => ret_dw_rw(i-NUM_READERS), - seq_nr_rtps => seq_nr_rw_dw(i-NUM_READERS), - get_data_rtps => get_data_rw_dw(i-NUM_READERS), - valid_out_rtps => valid_dw_rw(i-NUM_READERS), - ready_out_rtps => ready_rw_dw(i-NUM_READERS), - data_out_rtps => data_dw_rw(i-NUM_READERS), - last_word_out_rtps => last_word_dw_rw(i-NUM_READERS), - liveliness_assertion => liveliness_assertion_dw_rw(i-NUM_READERS), - data_available => data_available_dw_rw(i-NUM_READERS), - -- Cache Change - cc_instance_handle => cc_instance_handle_dw_rw(i-NUM_READERS), - cc_kind => cc_kind_dw_rw(i-NUM_READERS), - cc_source_timestamp => cc_source_timestamp_dw_rw(i-NUM_READERS), - cc_seq_nr => cc_seq_nr_dw_rw(i-NUM_READERS), - -- TO/FROM USER ENTITY - start_dds => start_wi_dw(i-NUM_READERS), - ack_dds => ack_dw_wi(i-NUM_READERS), - opcode_dds => opcode_wi_dw(i-NUM_READERS), - instance_handle_in_dds => instance_handle_wi_dw(i-NUM_READERS), - source_ts_dds => source_ts_wi_dw(i-NUM_READERS), - max_wait_dds => max_wait_wi_dw(i-NUM_READERS), - done_dds => done_dw_wi(i-NUM_READERS), - return_code_dds => return_code_dw_wi(i-NUM_READERS), - instance_handle_out_dds => instance_handle_dw_wi(i-NUM_READERS), - valid_in_dds => valid_wi_dw(i-NUM_READERS), - ready_in_dds => ready_dw_wi(i-NUM_READERS), - data_in_dds => data_wi_dw(i-NUM_READERS), - last_word_in_dds => last_word_wi_dw(i-NUM_READERS), - valid_out_dds => valid_dw_wi(i-NUM_READERS), - ready_out_dds => ready_wi_dw(i-NUM_READERS), - data_out_dds => data_dw_wi(i-NUM_READERS), - last_word_out_dds => last_word_dw_wi(i-NUM_READERS), - -- Communication Status - status => status_dw_wi(i-NUM_READERS) - ); - end generate; + dds_endpoint_w_if : if (NUM_WRITERS > 1) generate + dds_writer_inst : entity work.dds_writer(arch) + generic map ( + NUM_WRITERS => NUM_WRITERS-1, + CONFIG_ARRAY => to_QUARTUS_CONFIG_ARRAY_TYPE(ENDPOINT_CONFIG(NUM_READERS to NUM_ENDPOINTS-2)) + ) + port map ( + -- SYSTEM + clk => clk, + reset => reset, + time => time, + -- TO/FROM RTPS ENDPOINT + start_rtps => start_rw_dw(0 to NUM_WRITERS-2), + opcode_rtps => opcode_rw_dw(0 to NUM_WRITERS-2), + ack_rtps => ack_dw_rw(0 to NUM_WRITERS-2), + done_rtps => done_rw_dw(0 to NUM_WRITERS-2), + ret_rtps => ret_dw_rw(0 to NUM_WRITERS-2), + seq_nr_rtps => seq_nr_rw_dw(0 to NUM_WRITERS-2), + get_data_rtps => get_data_rw_dw(0 to NUM_WRITERS-2), + valid_out_rtps => valid_dw_rw(0 to NUM_WRITERS-2), + ready_out_rtps => ready_rw_dw(0 to NUM_WRITERS-2), + data_out_rtps => data_dw_rw(0 to NUM_WRITERS-2), + last_word_out_rtps => last_word_dw_rw(0 to NUM_WRITERS-2), + liveliness_assertion => liveliness_assertion_dw_rw(0 to NUM_WRITERS-2), + data_available => data_available_dw_rw(0 to NUM_WRITERS-2), + -- Cache Change + cc_instance_handle => cc_instance_handle_dw_rw(0 to NUM_WRITERS-2), + cc_kind => cc_kind_dw_rw(0 to NUM_WRITERS-2), + cc_source_timestamp => cc_source_timestamp_dw_rw(0 to NUM_WRITERS-2), + cc_seq_nr => cc_seq_nr_dw_rw(0 to NUM_WRITERS-2), + -- TO/FROM USER ENTITY + start_dds => start_wi_dw(0 to NUM_WRITERS-2), + ack_dds => ack_dw_wi(0 to NUM_WRITERS-2), + opcode_dds => opcode_wi_dw(0 to NUM_WRITERS-2), + instance_handle_in_dds => instance_handle_wi_dw(0 to NUM_WRITERS-2), + source_ts_dds => source_ts_wi_dw(0 to NUM_WRITERS-2), + max_wait_dds => max_wait_wi_dw(0 to NUM_WRITERS-2), + done_dds => done_dw_wi(0 to NUM_WRITERS-2), + return_code_dds => return_code_dw_wi(0 to NUM_WRITERS-2), + instance_handle_out_dds => instance_handle_dw_wi(0 to NUM_WRITERS-2), + valid_in_dds => valid_wi_dw(0 to NUM_WRITERS-2), + ready_in_dds => ready_dw_wi(0 to NUM_WRITERS-2), + data_in_dds => data_wi_dw(0 to NUM_WRITERS-2), + last_word_in_dds => last_word_wi_dw(0 to NUM_WRITERS-2), + valid_out_dds => valid_dw_wi(0 to NUM_WRITERS-2), + ready_out_dds => ready_wi_dw(0 to NUM_WRITERS-2), + data_out_dds => data_dw_wi(0 to NUM_WRITERS-2), + last_word_out_dds => last_word_dw_wi(0 to NUM_WRITERS-2), + -- Communication Status + status => status_dw_wi(0 to NUM_WRITERS-2) + ); + end generate; + dds_endpoint_gen : for i in 0 to NUM_READERS-1 generate + dds_reader_inst : entity work.dds_reader(arch) + generic map ( + TIME_BASED_FILTER_QOS => ENDPOINT_CONFIG(i).TIME_BASED_FILTER_QOS, + DEADLINE_QOS => ENDPOINT_CONFIG(i).DEADLINE_QOS, + MAX_INSTANCES => ENDPOINT_CONFIG(i).MAX_INSTANCES, + MAX_SAMPLES_PER_INSTANCE => ENDPOINT_CONFIG(i).MAX_SAMPLES_PER_INSTANCE, + MAX_SAMPLES => ENDPOINT_CONFIG(i).MAX_SAMPLES, + HISTORY_QOS => ENDPOINT_CONFIG(i).HISTORY_QOS, + RELIABILITY_QOS => ENDPOINT_CONFIG(i).RELIABILITY_QOS, + PRESENTATION_QOS => ENDPOINT_CONFIG(i).PRESENTATION_QOS, + DESTINATION_ORDER_QOS => ENDPOINT_CONFIG(i).DESTINATION_ORDER_QOS, + COHERENT_ACCESS => ENDPOINT_CONFIG(i).COHERENT_ACCESS, + ORDERED_ACCESS => ENDPOINT_CONFIG(i).ORDERED_ACCESS, + WITH_KEY => ENDPOINT_CONFIG(i).WITH_KEY, + PAYLOAD_FRAME_SIZE => ENDPOINT_CONFIG(i).MAX_PAYLOAD_SIZE, + MAX_REMOTE_ENDPOINTS => MAX_REMOTE_ENDPOINTS + ) + port map ( + -- SYSTEM + clk => clk, + reset => reset, + time => time, + -- FROM RTPS ENDPOINT + start_rtps => start_rr_dr(i), + opcode_rtps => opcode_rr_dr(i), + ack_rtps => ack_dr_rr(i), + done_rtps => done_dr_rr(i), + ret_rtps => ret_dr_rr(i), + valid_in_rtps => valid_rr_dr(i), + ready_in_rtps => ready_dr_rr(i), + data_in_rtps => data_rr_dr(i), + last_word_in_rtps => last_word_rr_dr(i), + -- TO USER ENTITY + start_dds => start_ri_dr(i), + ack_dds => ack_dr_ri(i), + opcode_dds => opcode_ri_dr(i), + instance_state_dds => instance_state_ri_dr(i), + view_state_dds => view_state_ri_dr(i), + sample_state_dds => sample_state_ri_dr(i), + instance_handle_dds => instance_handle_ri_dr(i), + max_samples_dds => max_samples_ri_dr(i), + get_data_dds => get_data_ri_dr(i), + done_dds => done_dr_ri(i), + return_code_dds => return_code_dr_ri(i), + valid_out_dds => valid_dr_ri(i), + ready_out_dds => ready_ri_dr(i), + data_out_dds => data_dr_ri(i), + last_word_out_dds => last_word_dr_ri(i), + sample_info => sample_info_dr_ri(i), + sample_info_valid => sample_info_valid_dr_ri(i), + sample_info_ack => sample_info_ack_ri_dr(i), + eoc => eoc_dr_ri(i), + -- Communication Status + status => status_dr_ri(i) + ); end generate; diff --git a/src/ros2/Tests/Level_2/L2_Testbench_ROS_Lib3.vhd b/src/ros2/Tests/Level_2/L2_Testbench_ROS_Lib3.vhd index 9129e92..9401c67 100644 --- a/src/ros2/Tests/Level_2/L2_Testbench_ROS_Lib3.vhd +++ b/src/ros2/Tests/Level_2/L2_Testbench_ROS_Lib3.vhd @@ -366,122 +366,114 @@ begin ); end generate; - dds_endpoint_gen : for i in 0 to NUM_ENDPOINTS-2 generate - dds_endpoint_if : if (i < NUM_READERS) generate - dds_reader_inst : entity work.dds_reader(arch) - generic map ( - TIME_BASED_FILTER_QOS => ENDPOINT_CONFIG(i).TIME_BASED_FILTER_QOS, - DEADLINE_QOS => ENDPOINT_CONFIG(i).DEADLINE_QOS, - MAX_INSTANCES => ENDPOINT_CONFIG(i).MAX_INSTANCES, - MAX_SAMPLES_PER_INSTANCE => ENDPOINT_CONFIG(i).MAX_SAMPLES_PER_INSTANCE, - MAX_SAMPLES => ENDPOINT_CONFIG(i).MAX_SAMPLES, - HISTORY_QOS => ENDPOINT_CONFIG(i).HISTORY_QOS, - RELIABILITY_QOS => ENDPOINT_CONFIG(i).RELIABILITY_QOS, - PRESENTATION_QOS => ENDPOINT_CONFIG(i).PRESENTATION_QOS, - DESTINATION_ORDER_QOS => ENDPOINT_CONFIG(i).DESTINATION_ORDER_QOS, - COHERENT_ACCESS => ENDPOINT_CONFIG(i).COHERENT_ACCESS, - ORDERED_ACCESS => ENDPOINT_CONFIG(i).ORDERED_ACCESS, - WITH_KEY => ENDPOINT_CONFIG(i).WITH_KEY, - PAYLOAD_FRAME_SIZE => ENDPOINT_CONFIG(i).MAX_PAYLOAD_SIZE, - MAX_REMOTE_ENDPOINTS => MAX_REMOTE_ENDPOINTS - ) - port map ( - -- SYSTEM - clk => clk, - reset => reset, - time => time, - -- FROM RTPS ENDPOINT - start_rtps => start_rr_dr(i), - opcode_rtps => opcode_rr_dr(i), - ack_rtps => ack_dr_rr(i), - done_rtps => done_dr_rr(i), - ret_rtps => ret_dr_rr(i), - valid_in_rtps => valid_rr_dr(i), - ready_in_rtps => ready_dr_rr(i), - data_in_rtps => data_rr_dr(i), - last_word_in_rtps => last_word_rr_dr(i), - -- TO USER ENTITY - start_dds => start_ri_dr(i), - ack_dds => ack_dr_ri(i), - opcode_dds => opcode_ri_dr(i), - instance_state_dds => instance_state_ri_dr(i), - view_state_dds => view_state_ri_dr(i), - sample_state_dds => sample_state_ri_dr(i), - instance_handle_dds => instance_handle_ri_dr(i), - max_samples_dds => max_samples_ri_dr(i), - get_data_dds => get_data_ri_dr(i), - done_dds => done_dr_ri(i), - return_code_dds => return_code_dr_ri(i), - valid_out_dds => valid_dr_ri(i), - ready_out_dds => ready_ri_dr(i), - data_out_dds => data_dr_ri(i), - last_word_out_dds => last_word_dr_ri(i), - sample_info => sample_info_dr_ri(i), - sample_info_valid => sample_info_valid_dr_ri(i), - sample_info_ack => sample_info_ack_ri_dr(i), - eoc => eoc_dr_ri(i), - -- Communication Status - status => status_dr_ri(i) - ); - else generate - dds_writer_inst : entity work.dds_writer(arch) - generic map ( - HISTORY_QOS => ENDPOINT_CONFIG(i).HISTORY_QOS, - DEADLINE_QOS => ENDPOINT_CONFIG(i).DEADLINE_QOS, - LIFESPAN_QOS => ENDPOINT_CONFIG(i).LIFESPAN_QOS, - LEASE_DURATION => ENDPOINT_CONFIG(i).LEASE_DURATION, - WITH_KEY => ENDPOINT_CONFIG(i).WITH_KEY, - MAX_SAMPLES => ENDPOINT_CONFIG(i).MAX_SAMPLES, - MAX_INSTANCES => ENDPOINT_CONFIG(i).MAX_INSTANCES, - MAX_SAMPLES_PER_INSTANCE => ENDPOINT_CONFIG(i).MAX_SAMPLES_PER_INSTANCE, - PAYLOAD_FRAME_SIZE => ENDPOINT_CONFIG(i).MAX_PAYLOAD_SIZE - ) - port map ( - -- SYSTEM - clk => clk, - reset => reset, - time => time, - -- TO/FROM RTPS ENDPOINT - start_rtps => start_rw_dw(i-NUM_READERS), - opcode_rtps => opcode_rw_dw(i-NUM_READERS), - ack_rtps => ack_dw_rw(i-NUM_READERS), - done_rtps => done_rw_dw(i-NUM_READERS), - ret_rtps => ret_dw_rw(i-NUM_READERS), - seq_nr_rtps => seq_nr_rw_dw(i-NUM_READERS), - get_data_rtps => get_data_rw_dw(i-NUM_READERS), - valid_out_rtps => valid_dw_rw(i-NUM_READERS), - ready_out_rtps => ready_rw_dw(i-NUM_READERS), - data_out_rtps => data_dw_rw(i-NUM_READERS), - last_word_out_rtps => last_word_dw_rw(i-NUM_READERS), - liveliness_assertion => liveliness_assertion_dw_rw(i-NUM_READERS), - data_available => data_available_dw_rw(i-NUM_READERS), - -- Cache Change - cc_instance_handle => cc_instance_handle_dw_rw(i-NUM_READERS), - cc_kind => cc_kind_dw_rw(i-NUM_READERS), - cc_source_timestamp => cc_source_timestamp_dw_rw(i-NUM_READERS), - cc_seq_nr => cc_seq_nr_dw_rw(i-NUM_READERS), - -- TO/FROM USER ENTITY - start_dds => start_wi_dw(i-NUM_READERS), - ack_dds => ack_dw_wi(i-NUM_READERS), - opcode_dds => opcode_wi_dw(i-NUM_READERS), - instance_handle_in_dds => instance_handle_wi_dw(i-NUM_READERS), - source_ts_dds => source_ts_wi_dw(i-NUM_READERS), - max_wait_dds => max_wait_wi_dw(i-NUM_READERS), - done_dds => done_dw_wi(i-NUM_READERS), - return_code_dds => return_code_dw_wi(i-NUM_READERS), - instance_handle_out_dds => instance_handle_dw_wi(i-NUM_READERS), - valid_in_dds => valid_wi_dw(i-NUM_READERS), - ready_in_dds => ready_dw_wi(i-NUM_READERS), - data_in_dds => data_wi_dw(i-NUM_READERS), - last_word_in_dds => last_word_wi_dw(i-NUM_READERS), - valid_out_dds => valid_dw_wi(i-NUM_READERS), - ready_out_dds => ready_wi_dw(i-NUM_READERS), - data_out_dds => data_dw_wi(i-NUM_READERS), - last_word_out_dds => last_word_dw_wi(i-NUM_READERS), - -- Communication Status - status => status_dw_wi(i-NUM_READERS) - ); - end generate; + dds_endpoint_w_if : if (NUM_WRITERS > 1) generate + dds_writer_inst : entity work.dds_writer(arch) + generic map ( + NUM_WRITERS => NUM_WRITERS-1, + CONFIG_ARRAY => to_QUARTUS_CONFIG_ARRAY_TYPE(ENDPOINT_CONFIG(NUM_READERS to NUM_ENDPOINTS-2)) + ) + port map ( + -- SYSTEM + clk => clk, + reset => reset, + time => time, + -- TO/FROM RTPS ENDPOINT + start_rtps => start_rw_dw(0 to NUM_WRITERS-2), + opcode_rtps => opcode_rw_dw(0 to NUM_WRITERS-2), + ack_rtps => ack_dw_rw(0 to NUM_WRITERS-2), + done_rtps => done_rw_dw(0 to NUM_WRITERS-2), + ret_rtps => ret_dw_rw(0 to NUM_WRITERS-2), + seq_nr_rtps => seq_nr_rw_dw(0 to NUM_WRITERS-2), + get_data_rtps => get_data_rw_dw(0 to NUM_WRITERS-2), + valid_out_rtps => valid_dw_rw(0 to NUM_WRITERS-2), + ready_out_rtps => ready_rw_dw(0 to NUM_WRITERS-2), + data_out_rtps => data_dw_rw(0 to NUM_WRITERS-2), + last_word_out_rtps => last_word_dw_rw(0 to NUM_WRITERS-2), + liveliness_assertion => liveliness_assertion_dw_rw(0 to NUM_WRITERS-2), + data_available => data_available_dw_rw(0 to NUM_WRITERS-2), + -- Cache Change + cc_instance_handle => cc_instance_handle_dw_rw(0 to NUM_WRITERS-2), + cc_kind => cc_kind_dw_rw(0 to NUM_WRITERS-2), + cc_source_timestamp => cc_source_timestamp_dw_rw(0 to NUM_WRITERS-2), + cc_seq_nr => cc_seq_nr_dw_rw(0 to NUM_WRITERS-2), + -- TO/FROM USER ENTITY + start_dds => start_wi_dw(0 to NUM_WRITERS-2), + ack_dds => ack_dw_wi(0 to NUM_WRITERS-2), + opcode_dds => opcode_wi_dw(0 to NUM_WRITERS-2), + instance_handle_in_dds => instance_handle_wi_dw(0 to NUM_WRITERS-2), + source_ts_dds => source_ts_wi_dw(0 to NUM_WRITERS-2), + max_wait_dds => max_wait_wi_dw(0 to NUM_WRITERS-2), + done_dds => done_dw_wi(0 to NUM_WRITERS-2), + return_code_dds => return_code_dw_wi(0 to NUM_WRITERS-2), + instance_handle_out_dds => instance_handle_dw_wi(0 to NUM_WRITERS-2), + valid_in_dds => valid_wi_dw(0 to NUM_WRITERS-2), + ready_in_dds => ready_dw_wi(0 to NUM_WRITERS-2), + data_in_dds => data_wi_dw(0 to NUM_WRITERS-2), + last_word_in_dds => last_word_wi_dw(0 to NUM_WRITERS-2), + valid_out_dds => valid_dw_wi(0 to NUM_WRITERS-2), + ready_out_dds => ready_wi_dw(0 to NUM_WRITERS-2), + data_out_dds => data_dw_wi(0 to NUM_WRITERS-2), + last_word_out_dds => last_word_dw_wi(0 to NUM_WRITERS-2), + -- Communication Status + status => status_dw_wi(0 to NUM_WRITERS-2) + ); + end generate; + dds_endpoint_gen : for i in 0 to NUM_READERS-1 generate + dds_reader_inst : entity work.dds_reader(arch) + generic map ( + TIME_BASED_FILTER_QOS => ENDPOINT_CONFIG(i).TIME_BASED_FILTER_QOS, + DEADLINE_QOS => ENDPOINT_CONFIG(i).DEADLINE_QOS, + MAX_INSTANCES => ENDPOINT_CONFIG(i).MAX_INSTANCES, + MAX_SAMPLES_PER_INSTANCE => ENDPOINT_CONFIG(i).MAX_SAMPLES_PER_INSTANCE, + MAX_SAMPLES => ENDPOINT_CONFIG(i).MAX_SAMPLES, + HISTORY_QOS => ENDPOINT_CONFIG(i).HISTORY_QOS, + RELIABILITY_QOS => ENDPOINT_CONFIG(i).RELIABILITY_QOS, + PRESENTATION_QOS => ENDPOINT_CONFIG(i).PRESENTATION_QOS, + DESTINATION_ORDER_QOS => ENDPOINT_CONFIG(i).DESTINATION_ORDER_QOS, + COHERENT_ACCESS => ENDPOINT_CONFIG(i).COHERENT_ACCESS, + ORDERED_ACCESS => ENDPOINT_CONFIG(i).ORDERED_ACCESS, + WITH_KEY => ENDPOINT_CONFIG(i).WITH_KEY, + PAYLOAD_FRAME_SIZE => ENDPOINT_CONFIG(i).MAX_PAYLOAD_SIZE, + MAX_REMOTE_ENDPOINTS => MAX_REMOTE_ENDPOINTS + ) + port map ( + -- SYSTEM + clk => clk, + reset => reset, + time => time, + -- FROM RTPS ENDPOINT + start_rtps => start_rr_dr(i), + opcode_rtps => opcode_rr_dr(i), + ack_rtps => ack_dr_rr(i), + done_rtps => done_dr_rr(i), + ret_rtps => ret_dr_rr(i), + valid_in_rtps => valid_rr_dr(i), + ready_in_rtps => ready_dr_rr(i), + data_in_rtps => data_rr_dr(i), + last_word_in_rtps => last_word_rr_dr(i), + -- TO USER ENTITY + start_dds => start_ri_dr(i), + ack_dds => ack_dr_ri(i), + opcode_dds => opcode_ri_dr(i), + instance_state_dds => instance_state_ri_dr(i), + view_state_dds => view_state_ri_dr(i), + sample_state_dds => sample_state_ri_dr(i), + instance_handle_dds => instance_handle_ri_dr(i), + max_samples_dds => max_samples_ri_dr(i), + get_data_dds => get_data_ri_dr(i), + done_dds => done_dr_ri(i), + return_code_dds => return_code_dr_ri(i), + valid_out_dds => valid_dr_ri(i), + ready_out_dds => ready_ri_dr(i), + data_out_dds => data_dr_ri(i), + last_word_out_dds => last_word_dr_ri(i), + sample_info => sample_info_dr_ri(i), + sample_info_valid => sample_info_valid_dr_ri(i), + sample_info_ack => sample_info_ack_ri_dr(i), + eoc => eoc_dr_ri(i), + -- Communication Status + status => status_dr_ri(i) + ); end generate; diff --git a/src/ros2/Tests/Level_2/L2_Testbench_ROS_Lib4.vhd b/src/ros2/Tests/Level_2/L2_Testbench_ROS_Lib4.vhd index 382752a..5012da4 100644 --- a/src/ros2/Tests/Level_2/L2_Testbench_ROS_Lib4.vhd +++ b/src/ros2/Tests/Level_2/L2_Testbench_ROS_Lib4.vhd @@ -369,122 +369,114 @@ begin ); end generate; - dds_endpoint_gen : for i in 0 to NUM_ENDPOINTS-2 generate - dds_endpoint_if : if (i < NUM_READERS) generate - dds_reader_inst : entity work.dds_reader(arch) - generic map ( - TIME_BASED_FILTER_QOS => ENDPOINT_CONFIG(i).TIME_BASED_FILTER_QOS, - DEADLINE_QOS => ENDPOINT_CONFIG(i).DEADLINE_QOS, - MAX_INSTANCES => ENDPOINT_CONFIG(i).MAX_INSTANCES, - MAX_SAMPLES_PER_INSTANCE => ENDPOINT_CONFIG(i).MAX_SAMPLES_PER_INSTANCE, - MAX_SAMPLES => ENDPOINT_CONFIG(i).MAX_SAMPLES, - HISTORY_QOS => ENDPOINT_CONFIG(i).HISTORY_QOS, - RELIABILITY_QOS => ENDPOINT_CONFIG(i).RELIABILITY_QOS, - PRESENTATION_QOS => ENDPOINT_CONFIG(i).PRESENTATION_QOS, - DESTINATION_ORDER_QOS => ENDPOINT_CONFIG(i).DESTINATION_ORDER_QOS, - COHERENT_ACCESS => ENDPOINT_CONFIG(i).COHERENT_ACCESS, - ORDERED_ACCESS => ENDPOINT_CONFIG(i).ORDERED_ACCESS, - WITH_KEY => ENDPOINT_CONFIG(i).WITH_KEY, - PAYLOAD_FRAME_SIZE => ENDPOINT_CONFIG(i).MAX_PAYLOAD_SIZE, - MAX_REMOTE_ENDPOINTS => MAX_REMOTE_ENDPOINTS - ) - port map ( - -- SYSTEM - clk => clk, - reset => reset, - time => time, - -- FROM RTPS ENDPOINT - start_rtps => start_rr_dr(i), - opcode_rtps => opcode_rr_dr(i), - ack_rtps => ack_dr_rr(i), - done_rtps => done_dr_rr(i), - ret_rtps => ret_dr_rr(i), - valid_in_rtps => valid_rr_dr(i), - ready_in_rtps => ready_dr_rr(i), - data_in_rtps => data_rr_dr(i), - last_word_in_rtps => last_word_rr_dr(i), - -- TO USER ENTITY - start_dds => start_ri_dr(i), - ack_dds => ack_dr_ri(i), - opcode_dds => opcode_ri_dr(i), - instance_state_dds => instance_state_ri_dr(i), - view_state_dds => view_state_ri_dr(i), - sample_state_dds => sample_state_ri_dr(i), - instance_handle_dds => instance_handle_ri_dr(i), - max_samples_dds => max_samples_ri_dr(i), - get_data_dds => get_data_ri_dr(i), - done_dds => done_dr_ri(i), - return_code_dds => return_code_dr_ri(i), - valid_out_dds => valid_dr_ri(i), - ready_out_dds => ready_ri_dr(i), - data_out_dds => data_dr_ri(i), - last_word_out_dds => last_word_dr_ri(i), - sample_info => sample_info_dr_ri(i), - sample_info_valid => sample_info_valid_dr_ri(i), - sample_info_ack => sample_info_ack_ri_dr(i), - eoc => eoc_dr_ri(i), - -- Communication Status - status => status_dr_ri(i) - ); - else generate - dds_writer_inst : entity work.dds_writer(arch) - generic map ( - HISTORY_QOS => ENDPOINT_CONFIG(i).HISTORY_QOS, - DEADLINE_QOS => ENDPOINT_CONFIG(i).DEADLINE_QOS, - LIFESPAN_QOS => ENDPOINT_CONFIG(i).LIFESPAN_QOS, - LEASE_DURATION => ENDPOINT_CONFIG(i).LEASE_DURATION, - WITH_KEY => ENDPOINT_CONFIG(i).WITH_KEY, - MAX_SAMPLES => ENDPOINT_CONFIG(i).MAX_SAMPLES, - MAX_INSTANCES => ENDPOINT_CONFIG(i).MAX_INSTANCES, - MAX_SAMPLES_PER_INSTANCE => ENDPOINT_CONFIG(i).MAX_SAMPLES_PER_INSTANCE, - PAYLOAD_FRAME_SIZE => ENDPOINT_CONFIG(i).MAX_PAYLOAD_SIZE - ) - port map ( - -- SYSTEM - clk => clk, - reset => reset, - time => time, - -- TO/FROM RTPS ENDPOINT - start_rtps => start_rw_dw(i-NUM_READERS), - opcode_rtps => opcode_rw_dw(i-NUM_READERS), - ack_rtps => ack_dw_rw(i-NUM_READERS), - done_rtps => done_rw_dw(i-NUM_READERS), - ret_rtps => ret_dw_rw(i-NUM_READERS), - seq_nr_rtps => seq_nr_rw_dw(i-NUM_READERS), - get_data_rtps => get_data_rw_dw(i-NUM_READERS), - valid_out_rtps => valid_dw_rw(i-NUM_READERS), - ready_out_rtps => ready_rw_dw(i-NUM_READERS), - data_out_rtps => data_dw_rw(i-NUM_READERS), - last_word_out_rtps => last_word_dw_rw(i-NUM_READERS), - liveliness_assertion => liveliness_assertion_dw_rw(i-NUM_READERS), - data_available => data_available_dw_rw(i-NUM_READERS), - -- Cache Change - cc_instance_handle => cc_instance_handle_dw_rw(i-NUM_READERS), - cc_kind => cc_kind_dw_rw(i-NUM_READERS), - cc_source_timestamp => cc_source_timestamp_dw_rw(i-NUM_READERS), - cc_seq_nr => cc_seq_nr_dw_rw(i-NUM_READERS), - -- TO/FROM USER ENTITY - start_dds => start_wi_dw(i-NUM_READERS), - ack_dds => ack_dw_wi(i-NUM_READERS), - opcode_dds => opcode_wi_dw(i-NUM_READERS), - instance_handle_in_dds => instance_handle_wi_dw(i-NUM_READERS), - source_ts_dds => source_ts_wi_dw(i-NUM_READERS), - max_wait_dds => max_wait_wi_dw(i-NUM_READERS), - done_dds => done_dw_wi(i-NUM_READERS), - return_code_dds => return_code_dw_wi(i-NUM_READERS), - instance_handle_out_dds => instance_handle_dw_wi(i-NUM_READERS), - valid_in_dds => valid_wi_dw(i-NUM_READERS), - ready_in_dds => ready_dw_wi(i-NUM_READERS), - data_in_dds => data_wi_dw(i-NUM_READERS), - last_word_in_dds => last_word_wi_dw(i-NUM_READERS), - valid_out_dds => valid_dw_wi(i-NUM_READERS), - ready_out_dds => ready_wi_dw(i-NUM_READERS), - data_out_dds => data_dw_wi(i-NUM_READERS), - last_word_out_dds => last_word_dw_wi(i-NUM_READERS), - -- Communication Status - status => status_dw_wi(i-NUM_READERS) - ); - end generate; + dds_endpoint_w_if : if (NUM_WRITERS > 1) generate + dds_writer_inst : entity work.dds_writer(arch) + generic map ( + NUM_WRITERS => NUM_WRITERS-1, + CONFIG_ARRAY => to_QUARTUS_CONFIG_ARRAY_TYPE(ENDPOINT_CONFIG(NUM_READERS to NUM_ENDPOINTS-2)) + ) + port map ( + -- SYSTEM + clk => clk, + reset => reset, + time => time, + -- TO/FROM RTPS ENDPOINT + start_rtps => start_rw_dw(0 to NUM_WRITERS-2), + opcode_rtps => opcode_rw_dw(0 to NUM_WRITERS-2), + ack_rtps => ack_dw_rw(0 to NUM_WRITERS-2), + done_rtps => done_rw_dw(0 to NUM_WRITERS-2), + ret_rtps => ret_dw_rw(0 to NUM_WRITERS-2), + seq_nr_rtps => seq_nr_rw_dw(0 to NUM_WRITERS-2), + get_data_rtps => get_data_rw_dw(0 to NUM_WRITERS-2), + valid_out_rtps => valid_dw_rw(0 to NUM_WRITERS-2), + ready_out_rtps => ready_rw_dw(0 to NUM_WRITERS-2), + data_out_rtps => data_dw_rw(0 to NUM_WRITERS-2), + last_word_out_rtps => last_word_dw_rw(0 to NUM_WRITERS-2), + liveliness_assertion => liveliness_assertion_dw_rw(0 to NUM_WRITERS-2), + data_available => data_available_dw_rw(0 to NUM_WRITERS-2), + -- Cache Change + cc_instance_handle => cc_instance_handle_dw_rw(0 to NUM_WRITERS-2), + cc_kind => cc_kind_dw_rw(0 to NUM_WRITERS-2), + cc_source_timestamp => cc_source_timestamp_dw_rw(0 to NUM_WRITERS-2), + cc_seq_nr => cc_seq_nr_dw_rw(0 to NUM_WRITERS-2), + -- TO/FROM USER ENTITY + start_dds => start_wi_dw(0 to NUM_WRITERS-2), + ack_dds => ack_dw_wi(0 to NUM_WRITERS-2), + opcode_dds => opcode_wi_dw(0 to NUM_WRITERS-2), + instance_handle_in_dds => instance_handle_wi_dw(0 to NUM_WRITERS-2), + source_ts_dds => source_ts_wi_dw(0 to NUM_WRITERS-2), + max_wait_dds => max_wait_wi_dw(0 to NUM_WRITERS-2), + done_dds => done_dw_wi(0 to NUM_WRITERS-2), + return_code_dds => return_code_dw_wi(0 to NUM_WRITERS-2), + instance_handle_out_dds => instance_handle_dw_wi(0 to NUM_WRITERS-2), + valid_in_dds => valid_wi_dw(0 to NUM_WRITERS-2), + ready_in_dds => ready_dw_wi(0 to NUM_WRITERS-2), + data_in_dds => data_wi_dw(0 to NUM_WRITERS-2), + last_word_in_dds => last_word_wi_dw(0 to NUM_WRITERS-2), + valid_out_dds => valid_dw_wi(0 to NUM_WRITERS-2), + ready_out_dds => ready_wi_dw(0 to NUM_WRITERS-2), + data_out_dds => data_dw_wi(0 to NUM_WRITERS-2), + last_word_out_dds => last_word_dw_wi(0 to NUM_WRITERS-2), + -- Communication Status + status => status_dw_wi(0 to NUM_WRITERS-2) + ); + end generate; + dds_endpoint_gen : for i in 0 to NUM_READERS-1 generate + dds_reader_inst : entity work.dds_reader(arch) + generic map ( + TIME_BASED_FILTER_QOS => ENDPOINT_CONFIG(i).TIME_BASED_FILTER_QOS, + DEADLINE_QOS => ENDPOINT_CONFIG(i).DEADLINE_QOS, + MAX_INSTANCES => ENDPOINT_CONFIG(i).MAX_INSTANCES, + MAX_SAMPLES_PER_INSTANCE => ENDPOINT_CONFIG(i).MAX_SAMPLES_PER_INSTANCE, + MAX_SAMPLES => ENDPOINT_CONFIG(i).MAX_SAMPLES, + HISTORY_QOS => ENDPOINT_CONFIG(i).HISTORY_QOS, + RELIABILITY_QOS => ENDPOINT_CONFIG(i).RELIABILITY_QOS, + PRESENTATION_QOS => ENDPOINT_CONFIG(i).PRESENTATION_QOS, + DESTINATION_ORDER_QOS => ENDPOINT_CONFIG(i).DESTINATION_ORDER_QOS, + COHERENT_ACCESS => ENDPOINT_CONFIG(i).COHERENT_ACCESS, + ORDERED_ACCESS => ENDPOINT_CONFIG(i).ORDERED_ACCESS, + WITH_KEY => ENDPOINT_CONFIG(i).WITH_KEY, + PAYLOAD_FRAME_SIZE => ENDPOINT_CONFIG(i).MAX_PAYLOAD_SIZE, + MAX_REMOTE_ENDPOINTS => MAX_REMOTE_ENDPOINTS + ) + port map ( + -- SYSTEM + clk => clk, + reset => reset, + time => time, + -- FROM RTPS ENDPOINT + start_rtps => start_rr_dr(i), + opcode_rtps => opcode_rr_dr(i), + ack_rtps => ack_dr_rr(i), + done_rtps => done_dr_rr(i), + ret_rtps => ret_dr_rr(i), + valid_in_rtps => valid_rr_dr(i), + ready_in_rtps => ready_dr_rr(i), + data_in_rtps => data_rr_dr(i), + last_word_in_rtps => last_word_rr_dr(i), + -- TO USER ENTITY + start_dds => start_ri_dr(i), + ack_dds => ack_dr_ri(i), + opcode_dds => opcode_ri_dr(i), + instance_state_dds => instance_state_ri_dr(i), + view_state_dds => view_state_ri_dr(i), + sample_state_dds => sample_state_ri_dr(i), + instance_handle_dds => instance_handle_ri_dr(i), + max_samples_dds => max_samples_ri_dr(i), + get_data_dds => get_data_ri_dr(i), + done_dds => done_dr_ri(i), + return_code_dds => return_code_dr_ri(i), + valid_out_dds => valid_dr_ri(i), + ready_out_dds => ready_ri_dr(i), + data_out_dds => data_dr_ri(i), + last_word_out_dds => last_word_dr_ri(i), + sample_info => sample_info_dr_ri(i), + sample_info_valid => sample_info_valid_dr_ri(i), + sample_info_ack => sample_info_ack_ri_dr(i), + eoc => eoc_dr_ri(i), + -- Communication Status + status => status_dr_ri(i) + ); end generate; diff --git a/src/ros2/Tests/Level_2/L2_Testbench_ROS_Lib5.vhd b/src/ros2/Tests/Level_2/L2_Testbench_ROS_Lib5.vhd index 845a667..07450bb 100644 --- a/src/ros2/Tests/Level_2/L2_Testbench_ROS_Lib5.vhd +++ b/src/ros2/Tests/Level_2/L2_Testbench_ROS_Lib5.vhd @@ -399,122 +399,114 @@ begin ); end generate; - dds_endpoint_gen : for i in 0 to NUM_ENDPOINTS-2 generate - dds_endpoint_if : if (i < NUM_READERS) generate - dds_reader_inst : entity work.dds_reader(arch) - generic map ( - TIME_BASED_FILTER_QOS => ENDPOINT_CONFIG(i).TIME_BASED_FILTER_QOS, - DEADLINE_QOS => ENDPOINT_CONFIG(i).DEADLINE_QOS, - MAX_INSTANCES => ENDPOINT_CONFIG(i).MAX_INSTANCES, - MAX_SAMPLES_PER_INSTANCE => ENDPOINT_CONFIG(i).MAX_SAMPLES_PER_INSTANCE, - MAX_SAMPLES => ENDPOINT_CONFIG(i).MAX_SAMPLES, - HISTORY_QOS => ENDPOINT_CONFIG(i).HISTORY_QOS, - RELIABILITY_QOS => ENDPOINT_CONFIG(i).RELIABILITY_QOS, - PRESENTATION_QOS => ENDPOINT_CONFIG(i).PRESENTATION_QOS, - DESTINATION_ORDER_QOS => ENDPOINT_CONFIG(i).DESTINATION_ORDER_QOS, - COHERENT_ACCESS => ENDPOINT_CONFIG(i).COHERENT_ACCESS, - ORDERED_ACCESS => ENDPOINT_CONFIG(i).ORDERED_ACCESS, - WITH_KEY => ENDPOINT_CONFIG(i).WITH_KEY, - PAYLOAD_FRAME_SIZE => ENDPOINT_CONFIG(i).MAX_PAYLOAD_SIZE, - MAX_REMOTE_ENDPOINTS => MAX_REMOTE_ENDPOINTS - ) - port map ( - -- SYSTEM - clk => clk, - reset => reset, - time => time, - -- FROM RTPS ENDPOINT - start_rtps => start_rr_dr(i), - opcode_rtps => opcode_rr_dr(i), - ack_rtps => ack_dr_rr(i), - done_rtps => done_dr_rr(i), - ret_rtps => ret_dr_rr(i), - valid_in_rtps => valid_rr_dr(i), - ready_in_rtps => ready_dr_rr(i), - data_in_rtps => data_rr_dr(i), - last_word_in_rtps => last_word_rr_dr(i), - -- TO USER ENTITY - start_dds => start_ri_dr(i), - ack_dds => ack_dr_ri(i), - opcode_dds => opcode_ri_dr(i), - instance_state_dds => instance_state_ri_dr(i), - view_state_dds => view_state_ri_dr(i), - sample_state_dds => sample_state_ri_dr(i), - instance_handle_dds => instance_handle_ri_dr(i), - max_samples_dds => max_samples_ri_dr(i), - get_data_dds => get_data_ri_dr(i), - done_dds => done_dr_ri(i), - return_code_dds => return_code_dr_ri(i), - valid_out_dds => valid_dr_ri(i), - ready_out_dds => ready_ri_dr(i), - data_out_dds => data_dr_ri(i), - last_word_out_dds => last_word_dr_ri(i), - sample_info => sample_info_dr_ri(i), - sample_info_valid => sample_info_valid_dr_ri(i), - sample_info_ack => sample_info_ack_ri_dr(i), - eoc => eoc_dr_ri(i), - -- Communication Status - status => status_dr_ri(i) - ); - else generate - dds_writer_inst : entity work.dds_writer(arch) - generic map ( - HISTORY_QOS => ENDPOINT_CONFIG(i).HISTORY_QOS, - DEADLINE_QOS => ENDPOINT_CONFIG(i).DEADLINE_QOS, - LIFESPAN_QOS => ENDPOINT_CONFIG(i).LIFESPAN_QOS, - LEASE_DURATION => ENDPOINT_CONFIG(i).LEASE_DURATION, - WITH_KEY => ENDPOINT_CONFIG(i).WITH_KEY, - MAX_SAMPLES => ENDPOINT_CONFIG(i).MAX_SAMPLES, - MAX_INSTANCES => ENDPOINT_CONFIG(i).MAX_INSTANCES, - MAX_SAMPLES_PER_INSTANCE => ENDPOINT_CONFIG(i).MAX_SAMPLES_PER_INSTANCE, - PAYLOAD_FRAME_SIZE => ENDPOINT_CONFIG(i).MAX_PAYLOAD_SIZE - ) - port map ( - -- SYSTEM - clk => clk, - reset => reset, - time => time, - -- TO/FROM RTPS ENDPOINT - start_rtps => start_rw_dw(i-NUM_READERS), - opcode_rtps => opcode_rw_dw(i-NUM_READERS), - ack_rtps => ack_dw_rw(i-NUM_READERS), - done_rtps => done_rw_dw(i-NUM_READERS), - ret_rtps => ret_dw_rw(i-NUM_READERS), - seq_nr_rtps => seq_nr_rw_dw(i-NUM_READERS), - get_data_rtps => get_data_rw_dw(i-NUM_READERS), - valid_out_rtps => valid_dw_rw(i-NUM_READERS), - ready_out_rtps => ready_rw_dw(i-NUM_READERS), - data_out_rtps => data_dw_rw(i-NUM_READERS), - last_word_out_rtps => last_word_dw_rw(i-NUM_READERS), - liveliness_assertion => liveliness_assertion_dw_rw(i-NUM_READERS), - data_available => data_available_dw_rw(i-NUM_READERS), - -- Cache Change - cc_instance_handle => cc_instance_handle_dw_rw(i-NUM_READERS), - cc_kind => cc_kind_dw_rw(i-NUM_READERS), - cc_source_timestamp => cc_source_timestamp_dw_rw(i-NUM_READERS), - cc_seq_nr => cc_seq_nr_dw_rw(i-NUM_READERS), - -- TO/FROM USER ENTITY - start_dds => start_wi_dw(i-NUM_READERS), - ack_dds => ack_dw_wi(i-NUM_READERS), - opcode_dds => opcode_wi_dw(i-NUM_READERS), - instance_handle_in_dds => instance_handle_wi_dw(i-NUM_READERS), - source_ts_dds => source_ts_wi_dw(i-NUM_READERS), - max_wait_dds => max_wait_wi_dw(i-NUM_READERS), - done_dds => done_dw_wi(i-NUM_READERS), - return_code_dds => return_code_dw_wi(i-NUM_READERS), - instance_handle_out_dds => instance_handle_dw_wi(i-NUM_READERS), - valid_in_dds => valid_wi_dw(i-NUM_READERS), - ready_in_dds => ready_dw_wi(i-NUM_READERS), - data_in_dds => data_wi_dw(i-NUM_READERS), - last_word_in_dds => last_word_wi_dw(i-NUM_READERS), - valid_out_dds => valid_dw_wi(i-NUM_READERS), - ready_out_dds => ready_wi_dw(i-NUM_READERS), - data_out_dds => data_dw_wi(i-NUM_READERS), - last_word_out_dds => last_word_dw_wi(i-NUM_READERS), - -- Communication Status - status => status_dw_wi(i-NUM_READERS) - ); - end generate; + dds_endpoint_w_if : if (NUM_WRITERS > 1) generate + dds_writer_inst : entity work.dds_writer(arch) + generic map ( + NUM_WRITERS => NUM_WRITERS-1, + CONFIG_ARRAY => to_QUARTUS_CONFIG_ARRAY_TYPE(ENDPOINT_CONFIG(NUM_READERS to NUM_ENDPOINTS-2)) + ) + port map ( + -- SYSTEM + clk => clk, + reset => reset, + time => time, + -- TO/FROM RTPS ENDPOINT + start_rtps => start_rw_dw(0 to NUM_WRITERS-2), + opcode_rtps => opcode_rw_dw(0 to NUM_WRITERS-2), + ack_rtps => ack_dw_rw(0 to NUM_WRITERS-2), + done_rtps => done_rw_dw(0 to NUM_WRITERS-2), + ret_rtps => ret_dw_rw(0 to NUM_WRITERS-2), + seq_nr_rtps => seq_nr_rw_dw(0 to NUM_WRITERS-2), + get_data_rtps => get_data_rw_dw(0 to NUM_WRITERS-2), + valid_out_rtps => valid_dw_rw(0 to NUM_WRITERS-2), + ready_out_rtps => ready_rw_dw(0 to NUM_WRITERS-2), + data_out_rtps => data_dw_rw(0 to NUM_WRITERS-2), + last_word_out_rtps => last_word_dw_rw(0 to NUM_WRITERS-2), + liveliness_assertion => liveliness_assertion_dw_rw(0 to NUM_WRITERS-2), + data_available => data_available_dw_rw(0 to NUM_WRITERS-2), + -- Cache Change + cc_instance_handle => cc_instance_handle_dw_rw(0 to NUM_WRITERS-2), + cc_kind => cc_kind_dw_rw(0 to NUM_WRITERS-2), + cc_source_timestamp => cc_source_timestamp_dw_rw(0 to NUM_WRITERS-2), + cc_seq_nr => cc_seq_nr_dw_rw(0 to NUM_WRITERS-2), + -- TO/FROM USER ENTITY + start_dds => start_wi_dw(0 to NUM_WRITERS-2), + ack_dds => ack_dw_wi(0 to NUM_WRITERS-2), + opcode_dds => opcode_wi_dw(0 to NUM_WRITERS-2), + instance_handle_in_dds => instance_handle_wi_dw(0 to NUM_WRITERS-2), + source_ts_dds => source_ts_wi_dw(0 to NUM_WRITERS-2), + max_wait_dds => max_wait_wi_dw(0 to NUM_WRITERS-2), + done_dds => done_dw_wi(0 to NUM_WRITERS-2), + return_code_dds => return_code_dw_wi(0 to NUM_WRITERS-2), + instance_handle_out_dds => instance_handle_dw_wi(0 to NUM_WRITERS-2), + valid_in_dds => valid_wi_dw(0 to NUM_WRITERS-2), + ready_in_dds => ready_dw_wi(0 to NUM_WRITERS-2), + data_in_dds => data_wi_dw(0 to NUM_WRITERS-2), + last_word_in_dds => last_word_wi_dw(0 to NUM_WRITERS-2), + valid_out_dds => valid_dw_wi(0 to NUM_WRITERS-2), + ready_out_dds => ready_wi_dw(0 to NUM_WRITERS-2), + data_out_dds => data_dw_wi(0 to NUM_WRITERS-2), + last_word_out_dds => last_word_dw_wi(0 to NUM_WRITERS-2), + -- Communication Status + status => status_dw_wi(0 to NUM_WRITERS-2) + ); + end generate; + dds_endpoint_gen : for i in 0 to NUM_READERS-1 generate + dds_reader_inst : entity work.dds_reader(arch) + generic map ( + TIME_BASED_FILTER_QOS => ENDPOINT_CONFIG(i).TIME_BASED_FILTER_QOS, + DEADLINE_QOS => ENDPOINT_CONFIG(i).DEADLINE_QOS, + MAX_INSTANCES => ENDPOINT_CONFIG(i).MAX_INSTANCES, + MAX_SAMPLES_PER_INSTANCE => ENDPOINT_CONFIG(i).MAX_SAMPLES_PER_INSTANCE, + MAX_SAMPLES => ENDPOINT_CONFIG(i).MAX_SAMPLES, + HISTORY_QOS => ENDPOINT_CONFIG(i).HISTORY_QOS, + RELIABILITY_QOS => ENDPOINT_CONFIG(i).RELIABILITY_QOS, + PRESENTATION_QOS => ENDPOINT_CONFIG(i).PRESENTATION_QOS, + DESTINATION_ORDER_QOS => ENDPOINT_CONFIG(i).DESTINATION_ORDER_QOS, + COHERENT_ACCESS => ENDPOINT_CONFIG(i).COHERENT_ACCESS, + ORDERED_ACCESS => ENDPOINT_CONFIG(i).ORDERED_ACCESS, + WITH_KEY => ENDPOINT_CONFIG(i).WITH_KEY, + PAYLOAD_FRAME_SIZE => ENDPOINT_CONFIG(i).MAX_PAYLOAD_SIZE, + MAX_REMOTE_ENDPOINTS => MAX_REMOTE_ENDPOINTS + ) + port map ( + -- SYSTEM + clk => clk, + reset => reset, + time => time, + -- FROM RTPS ENDPOINT + start_rtps => start_rr_dr(i), + opcode_rtps => opcode_rr_dr(i), + ack_rtps => ack_dr_rr(i), + done_rtps => done_dr_rr(i), + ret_rtps => ret_dr_rr(i), + valid_in_rtps => valid_rr_dr(i), + ready_in_rtps => ready_dr_rr(i), + data_in_rtps => data_rr_dr(i), + last_word_in_rtps => last_word_rr_dr(i), + -- TO USER ENTITY + start_dds => start_ri_dr(i), + ack_dds => ack_dr_ri(i), + opcode_dds => opcode_ri_dr(i), + instance_state_dds => instance_state_ri_dr(i), + view_state_dds => view_state_ri_dr(i), + sample_state_dds => sample_state_ri_dr(i), + instance_handle_dds => instance_handle_ri_dr(i), + max_samples_dds => max_samples_ri_dr(i), + get_data_dds => get_data_ri_dr(i), + done_dds => done_dr_ri(i), + return_code_dds => return_code_dr_ri(i), + valid_out_dds => valid_dr_ri(i), + ready_out_dds => ready_ri_dr(i), + data_out_dds => data_dr_ri(i), + last_word_out_dds => last_word_dr_ri(i), + sample_info => sample_info_dr_ri(i), + sample_info_valid => sample_info_valid_dr_ri(i), + sample_info_ack => sample_info_ack_ri_dr(i), + eoc => eoc_dr_ri(i), + -- Communication Status + status => status_dr_ri(i) + ); end generate; diff --git a/src/rtps_package.vhd b/src/rtps_package.vhd index 6277f4c..cf1f0ed 100644 --- a/src/rtps_package.vhd +++ b/src/rtps_package.vhd @@ -79,9 +79,12 @@ package rtps_package is constant SAMPLE_LOST_STATUS_COUNT_WIDTH : natural := CDR_LONG_WIDTH; constant SAMPLE_REJECTED_STATUS_COUNT_WIDTH : natural := CDR_LONG_WIDTH; constant LIVELINESS_LOST_STATUS_COUNT_WIDTH : natural := CDR_LONG_WIDTH; + type LIVELINESS_LOST_STATUS_COUNT_ARRAY_TYPE is array (natural range <>) of std_logic_vector(LIVELINESS_LOST_STATUS_COUNT_WIDTH-1 downto 0); constant LIVELINESS_CHANGED_STATUS_COUNT_WIDTH : natural := CDR_LONG_WIDTH; constant OFFERED_DEADLINE_MISSED_STATUS_COUNT_WIDTH : natural := CDR_LONG_WIDTH; + type OFFERED_DEADLINE_MISSED_STATUS_COUNT_ARRAY_TYPE is array (natural range <>) of std_logic_vector(OFFERED_DEADLINE_MISSED_STATUS_COUNT_WIDTH-1 downto 0); constant REQUESTED_DEADLINE_MISSED_STATUS_COUNT_WIDTH : natural := CDR_LONG_WIDTH; + type REQUESTED_DEADLINE_MISSED_STATUS_COUNT_ARRAY_TYPE is array (natural range <>) of std_logic_vector(REQUESTED_DEADLINE_MISSED_STATUS_COUNT_WIDTH-1 downto 0); constant OFFERED_INCOMPATIBLE_QOS_STATUS_COUNT_WIDTH : natural := CDR_LONG_WIDTH; constant REQUESTED_INCOMPATIBLE_QOS_STATUS_COUNT_WIDTH : natural := CDR_LONG_WIDTH; constant PUBLICATION_MATCHED_STATUS_COUNT_WIDTH : natural := CDR_LONG_WIDTH; @@ -492,6 +495,7 @@ package rtps_package is type HISTORY_CACHE_OPCODE_TYPE is (NOP, ADD_CACHE_CHANGE, GET_CACHE_CHANGE, ACK_CACHE_CHANGE, NACK_CACHE_CHANGE, REMOVE_CACHE_CHANGE, REMOVE_WRITER, GET_MIN_SN, GET_MAX_SN); type HISTORY_CACHE_OPCODE_ARRAY_TYPE is array (natural range <>) of HISTORY_CACHE_OPCODE_TYPE; type KEY_HOLDER_OPCODE_TYPE is (NOP, PUSH_DATA, PUSH_SERIALIZED_KEY, READ_KEY_HASH, READ_SERIALIZED_KEY); + type KEY_HOLDER_OPCODE_ARRAY_TYPE is array (natural range <>) of KEY_HOLDER_OPCODE_TYPE; type HISTORY_CACHE_RESPONSE_TYPE is (OK, REJECTED, INVALID, ERROR); type HISTORY_CACHE_RESPONSE_ARRAY_TYPE is array (natural range <>) of HISTORY_CACHE_RESPONSE_TYPE; type DDS_WRITER_OPCODE_TYPE is (NOP, REGISTER_INSTANCE, WRITE, DISPOSE, UNREGISTER_INSTANCE, LOOKUP_INSTANCE, WAIT_FOR_ACKNOWLEDGEMENTS, GET_OFFERED_DEADLINE_MISSED_STATUS, ASSERT_LIVELINESS, GET_LIVELINESS_LOST_STATUS); diff --git a/syn/DE10-Nano/top.qsf b/syn/DE10-Nano/top.qsf index d6a3ac7..21af300 100644 --- a/syn/DE10-Nano/top.qsf +++ b/syn/DE10-Nano/top.qsf @@ -39,7 +39,7 @@ set_global_assignment -name FAMILY "Cyclone V" set_global_assignment -name DEVICE 5CSEBA6U23I7 -set_global_assignment -name TOP_LEVEL_ENTITY test_top +set_global_assignment -name TOP_LEVEL_ENTITY dds_writer_syn set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.0 set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:33:09 NOVEMBER 02, 2020" set_global_assignment -name LAST_QUARTUS_VERSION "21.1.0 Lite Edition" @@ -49,9 +49,6 @@ set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008 set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF -set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top -set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top -set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top set_global_assignment -name SDC_FILE ../top.sdc set_global_assignment -name VHDL_FILE ../test_top.vhd -hdl_version VHDL_2008 set_global_assignment -name VHDL_FILE ../../src/ros2/Tests/Level_2/L2_Testbench_ROS_Lib4.vhd -hdl_version VHDL_2008 @@ -134,4 +131,7 @@ set_global_assignment -name VHDL_FILE ../../src/ros2/rcl_interfaces/action_msgs/ set_global_assignment -name VHDL_FILE ../../src/ros2/ros_package.vhd -hdl_version VHDL_2008 set_global_assignment -name VHDL_FILE ../../src/rtps_package.vhd -hdl_version VHDL_2008 set_global_assignment -name VHDL_FILE ../../src/math_pkg.vhd -hdl_version VHDL_2008 +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/syn/dds_writer_syn.vhd b/syn/dds_writer_syn.vhd index 8592fce..570c37d 100644 --- a/syn/dds_writer_syn.vhd +++ b/syn/dds_writer_syn.vhd @@ -18,44 +18,44 @@ entity dds_writer_syn is reset : in std_logic; time : in TIME_TYPE; -- TO/FROM RTPS ENDPOINT - start_rtps : in std_logic; - opcode_rtps : in HISTORY_CACHE_OPCODE_TYPE; - ack_rtps : out std_logic; - done_rtps : out std_logic; - ret_rtps : out HISTORY_CACHE_RESPONSE_TYPE; - seq_nr_rtps : in SEQUENCENUMBER_TYPE; - get_data_rtps : in std_logic; - data_out_rtps : out std_logic_vector(WORD_WIDTH-1 downto 0); - valid_out_rtps : out std_logic; - ready_out_rtps : in std_logic; - last_word_out_rtps : out std_logic; - liveliness_assertion : out std_logic; - data_available : out std_logic; + start_rtps : in std_logic_vector(0 to 0); + opcode_rtps : in HISTORY_CACHE_OPCODE_ARRAY_TYPE(0 to 0); + ack_rtps : out std_logic_vector(0 to 0); + done_rtps : out std_logic_vector(0 to 0); + ret_rtps : out HISTORY_CACHE_RESPONSE_ARRAY_TYPE(0 to 0); + seq_nr_rtps : in SEQUENCENUMBER_ARRAY_TYPE(0 to 0); + get_data_rtps : in std_logic_vector(0 to 0); + data_out_rtps : out WORD_ARRAY_TYPE(0 to 0); + valid_out_rtps : out std_logic_vector(0 to 0); + ready_out_rtps : in std_logic_vector(0 to 0); + last_word_out_rtps : out std_logic_vector(0 to 0); + liveliness_assertion : out std_logic_vector(0 to 0); + data_available : out std_logic_vector(0 to 0); -- Cache Change - cc_instance_handle : out INSTANCE_HANDLE_TYPE; - cc_kind : out CACHE_CHANGE_KIND_TYPE; - cc_source_timestamp : out TIME_TYPE; - cc_seq_nr : out SEQUENCENUMBER_TYPE; + cc_instance_handle : out INSTANCE_HANDLE_ARRAY_TYPE(0 to 0); + cc_kind : out CACHE_CHANGE_KIND_ARRAY_TYPE(0 to 0); + cc_source_timestamp : out TIME_ARRAY_TYPE(0 to 0); + cc_seq_nr : out SEQUENCENUMBER_ARRAY_TYPE(0 to 0); -- TO/FROM USER ENTITY - start_dds : in std_logic; - ack_dds : out std_logic; - opcode_dds : in DDS_WRITER_OPCODE_TYPE; - instance_handle_in_dds : in INSTANCE_HANDLE_TYPE; - source_ts_dds : in TIME_TYPE; - max_wait_dds : in DURATION_TYPE; - done_dds : out std_logic; - return_code_dds : out std_logic_vector(RETURN_CODE_WIDTH-1 downto 0); - instance_handle_out_dds : out INSTANCE_HANDLE_TYPE; - ready_in_dds : out std_logic; - valid_in_dds : in std_logic; - data_in_dds : in std_logic_vector(WORD_WIDTH-1 downto 0); - last_word_in_dds : in std_logic; - ready_out_dds : in std_logic; - valid_out_dds : out std_logic; - data_out_dds : out std_logic_vector(WORD_WIDTH-1 downto 0); - last_word_out_dds : out std_logic; + start_dds : in std_logic_vector(0 to 0); + ack_dds : out std_logic_vector(0 to 0); + opcode_dds : in DDS_WRITER_OPCODE_ARRAY_TYPE(0 to 0); + instance_handle_in_dds : in INSTANCE_HANDLE_ARRAY_TYPE(0 to 0); + source_ts_dds : in TIME_ARRAY_TYPE(0 to 0); + max_wait_dds : in DURATION_ARRAY_TYPE(0 to 0); + done_dds : out std_logic_vector(0 to 0); + return_code_dds : out RETURN_CODE_ARRAY_TYPE(0 to 0); + instance_handle_out_dds : out INSTANCE_HANDLE_ARRAY_TYPE(0 to 0); + valid_in_dds : in std_logic_vector(0 to 0); + ready_in_dds : out std_logic_vector(0 to 0); + data_in_dds : in WORD_ARRAY_TYPE(0 to 0); + last_word_in_dds : in std_logic_vector(0 to 0); + valid_out_dds : out std_logic_vector(0 to 0); + ready_out_dds : in std_logic_vector(0 to 0); + data_out_dds : out WORD_ARRAY_TYPE(0 to 0); + last_word_out_dds : out std_logic_vector(0 to 0); -- Communication Status - status : out std_logic_vector(STATUS_KIND_WIDTH-1 downto 0) + status : out STATUS_KIND_ARRAY_TYPE(0 to 0) ); end entity; @@ -65,15 +65,8 @@ begin if_gen : if (NUM_WRITERS > 0) generate syn_inst : entity work.dds_writer(arch) generic map ( - HISTORY_QOS => ENDPOINT_CONFIG(NUM_READERS).HISTORY_QOS, - DEADLINE_QOS => ENDPOINT_CONFIG(NUM_READERS).DEADLINE_QOS, - LIFESPAN_QOS => ENDPOINT_CONFIG(NUM_READERS).LIFESPAN_QOS, - LEASE_DURATION => ENDPOINT_CONFIG(NUM_READERS).LEASE_DURATION, - WITH_KEY => ENDPOINT_CONFIG(NUM_READERS).WITH_KEY, - MAX_SAMPLES => ENDPOINT_CONFIG(NUM_READERS).MAX_SAMPLES, - MAX_INSTANCES => ENDPOINT_CONFIG(NUM_READERS).MAX_INSTANCES, - MAX_SAMPLES_PER_INSTANCE => ENDPOINT_CONFIG(NUM_READERS).MAX_SAMPLES_PER_INSTANCE, - PAYLOAD_FRAME_SIZE => MAX_TYPE1_SIZE + NUM_WRITERS => 1, + CONFIG_ARRAY => to_QUARTUS_CONFIG_ARRAY_TYPE(ENDPOINT_CONFIG(NUM_READERS to NUM_READERS)) ) port map ( clk => clk,