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Code refactoring

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This commit is contained in:
John Ring 2022-03-08 13:09:00 +01:00
parent e4e702ebc4
commit 5f01a94b31
5 changed files with 26 additions and 36 deletions
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4
sim/modelsim.ini
View File

@ -26,6 +26,8 @@ Testbench_Lib1 = W:/HDL-SIM/OSVVM-Scripts/../sim/VHDL_LIBS/ModelSim-2020.02/Test
Testbench_ROS_Lib1 = W:/HDL-SIM/OSVVM-Scripts/../sim/VHDL_LIBS/ModelSim-2020.02/Testbench_ROS_Lib1.lib
Testbench_ROS_Lib2 = W:/HDL-SIM/OSVVM-Scripts/../sim/VHDL_LIBS/ModelSim-2020.02/Testbench_ROS_Lib2.lib
Testbench_ROS_Lib3 = W:/HDL-SIM/OSVVM-Scripts/../sim/VHDL_LIBS/ModelSim-2020.02/Testbench_ROS_Lib3.lib
Testbench_ROS_Lib4 = W:/HDL-SIM/OSVVM-Scripts/../sim/VHDL_LIBS/ModelSim-2020.02/Testbench_ROS_Lib4.lib
Testbench_ROS_Lib5 = W:/HDL-SIM/OSVVM-Scripts/../sim/VHDL_LIBS/ModelSim-2020.02/Testbench_ROS_Lib5.lib
[vcom]
; VHDL93 variable selects language version as the default.
; Default is VHDL-2002.
@ -172,7 +174,7 @@ IterationLimit = 5000
; Stop the simulator after a VHDL/Verilog assertion message
; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal
BreakOnAssertion = 3
BreakOnAssertion = 2
; Assertion Message Format
; %S - Severity Level

4
src/TODO.txt
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@ -432,9 +432,9 @@ DESIGN DECISIONS
use a 64-bit unsigned nanosecond representation, and ROS sends time (defined in
rcl_interfaces/builtin_interfaces) in 32-bit second and 32-bit nanosecond respresentation.
An internal representation of a 64-bit nanosecond counter seems like the most sensible, but conversions
between are quite resource and latency heavy.
between the representations are quite resource and latency heavy.
Since the ros action server directly interfaces ros services with the builtin_interfaces definition,
it was decided that the entire server works on this representation to avoid costly converions. This in
it was decided that the entire server works on this representation to avoid costly conversions. This in
effect mitigates the converion problem to the instantiating entity, but a single conversion point could
be defined that can be used throughout the system.

14
src/math_pkg.vhd
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@ -19,8 +19,7 @@ end package;
package body math_pkg is
--*****FUNCTION DEFINITION*****
function log2c(constant value : in integer) return integer is
function log2(constant value : in integer) return integer is
variable ret_value : integer;
variable cur_value : integer;
begin
@ -34,6 +33,17 @@ package body math_pkg is
return ret_value;
end function;
function log2c(constant value : in integer) return integer is
variable ret : natural;
begin
ret := log2(value);
if (ret = 0) then
return 1;
else
return ret;
end if;
end function;
function max(constant value1, value2 : in integer) return integer is
variable ret_value : integer;
begin

2
src/ros2/example_interfaces/Fibonacci_package.vhd
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@ -14,7 +14,7 @@ package Fibonacci_package is
constant G_RQ_MAX_GOAL_ID_SIZE : natural := GoalInfo_package.MAX_GOAL_ID_SIZE;
constant G_RQ_MAX_ORDER_SIZE : natural := 4;
constant G_RQ_FIBONACCI_SIZE : natural := G_RQ_MAX_GOAL_ID_SIZE + G_RQ_MAX_ORDER_SIZE;
constant G_RQ_MAX_FIBONACCI_SIZE : natural := G_RQ_MAX_GOAL_ID_SIZE + G_RQ_MAX_ORDER_SIZE;
constant G_RR_MAX_ACCEPTED : natural := 1;
constant G_RR_MAX_STAMP_SEC_SIZE : natural := GoalInfo_package.MAX_STAMP_SEC_SIZE;

34
syn/dds_reader_syn.vhd
View File

@ -44,20 +44,9 @@ entity dds_reader_syn is
data_out_dds : out std_logic_vector(WORD_WIDTH-1 downto 0);
last_word_out_dds : out std_logic;
-- Sample Info
si_sample_state : out std_logic_vector(SAMPLE_STATE_KIND_WIDTH-1 downto 0);
si_view_state : out std_logic_vector(VIEW_STATE_KIND_WIDTH-1 downto 0);
si_instance_state : out std_logic_vector(INSTANCE_STATE_KIND_WIDTH-1 downto 0);
si_source_timestamp : out TIME_TYPE;
si_instance_handle : out INSTANCE_HANDLE_TYPE;
si_publication_handle : out INSTANCE_HANDLE_TYPE;
si_disposed_generation_count : out std_logic_vector(DISPOSED_GENERATION_COUNT_WIDTH-1 downto 0);
si_no_writers_generation_count : out std_logic_vector(NO_WRITERS_GENERATION_COUNT_WIDTH-1 downto 0);
si_sample_rank : out std_logic_vector(SAMPLE_RANK_WIDTH-1 downto 0);
si_generation_rank : out std_logic_vector(GENERATION_RANK_WIDTH-1 downto 0);
si_absolute_generation_rank : out std_logic_vector(ABSOLUTE_GENERATION_COUNT_WIDTH-1 downto 0);
si_valid_data : out std_logic;
si_valid : out std_logic;
si_ack : in std_logic;
sample_info : out SAMPLE_INFO_TYPE;
sample_info_valid : out std_logic;
sample_info_ack : in std_logic;
eoc : out std_logic;
-- Communication Status
status : out std_logic_vector(STATUS_KIND_WIDTH-1 downto 0)
@ -112,20 +101,9 @@ begin
valid_out_dds => valid_out_dds,
data_out_dds => data_out_dds,
last_word_out_dds => last_word_out_dds,
si_sample_state => si_sample_state,
si_view_state => si_view_state,
si_instance_state => si_instance_state,
si_source_timestamp => si_source_timestamp,
si_instance_handle => si_instance_handle,
si_publication_handle => si_publication_handle,
si_disposed_generation_count => si_disposed_generation_count,
si_no_writers_generation_count => si_no_writers_generation_count,
si_sample_rank => si_sample_rank,
si_generation_rank => si_generation_rank,
si_absolute_generation_rank => si_absolute_generation_rank,
si_valid_data => si_valid_data,
si_valid => si_valid,
si_ack => si_ack,
sample_info => sample_info,
sample_info_valid => sample_info_valid,
sample_info_ack => sample_info_ack,
eoc => eoc,
status => status
);