diff --git a/sim/modelsim.ini b/sim/modelsim.ini
index dd3d443..cd6d7bd 100644
--- a/sim/modelsim.ini
+++ b/sim/modelsim.ini
@@ -16,18 +16,18 @@ others = $MODEL_TECH/../modelsim.ini
 ;
 ; Verilog Section
 ;
-default = W:/HDL-SIM/OSVVM-Scripts/../sim/VHDL_LIBS/ModelSim-2020.02/default.lib
-osvvm = W:/HDL-SIM/OSVVM-Scripts/../sim/VHDL_LIBS/ModelSim-2020.02/osvvm.lib
-Testbench_Lib2 = W:/HDL-SIM/OSVVM-Scripts/../sim/VHDL_LIBS/ModelSim-2020.02/Testbench_Lib2.lib
-Testbench_Lib3 = W:/HDL-SIM/OSVVM-Scripts/../sim/VHDL_LIBS/ModelSim-2020.02/Testbench_Lib3.lib
-Testbench_Lib4 = W:/HDL-SIM/OSVVM-Scripts/../sim/VHDL_LIBS/ModelSim-2020.02/Testbench_Lib4.lib
-Testbench_Lib5 = W:/HDL-SIM/OSVVM-Scripts/../sim/VHDL_LIBS/ModelSim-2020.02/Testbench_Lib5.lib
-Testbench_Lib1 = W:/HDL-SIM/OSVVM-Scripts/../sim/VHDL_LIBS/ModelSim-2020.02/Testbench_Lib1.lib
-Testbench_ROS_Lib1 = W:/HDL-SIM/OSVVM-Scripts/../sim/VHDL_LIBS/ModelSim-2020.02/Testbench_ROS_Lib1.lib
-Testbench_ROS_Lib2 = W:/HDL-SIM/OSVVM-Scripts/../sim/VHDL_LIBS/ModelSim-2020.02/Testbench_ROS_Lib2.lib
-Testbench_ROS_Lib3 = W:/HDL-SIM/OSVVM-Scripts/../sim/VHDL_LIBS/ModelSim-2020.02/Testbench_ROS_Lib3.lib
-Testbench_ROS_Lib4 = W:/HDL-SIM/OSVVM-Scripts/../sim/VHDL_LIBS/ModelSim-2020.02/Testbench_ROS_Lib4.lib
-Testbench_ROS_Lib5 = W:/HDL-SIM/OSVVM-Scripts/../sim/VHDL_LIBS/ModelSim-2020.02/Testbench_ROS_Lib5.lib
+default = /tmp/sim_temp/VHDL_LIBS/ModelSim-2020.02/default.lib
+osvvm = /tmp/sim_temp/VHDL_LIBS/ModelSim-2020.02/osvvm.lib
+Testbench_Lib2 = /tmp/sim_temp/VHDL_LIBS/ModelSim-2020.02/Testbench_Lib2.lib
+Testbench_Lib3 = /tmp/sim_temp/VHDL_LIBS/ModelSim-2020.02/Testbench_Lib3.lib
+Testbench_Lib4 = /tmp/sim_temp/VHDL_LIBS/ModelSim-2020.02/Testbench_Lib4.lib
+Testbench_Lib5 = /tmp/sim_temp/VHDL_LIBS/ModelSim-2020.02/Testbench_Lib5.lib
+Testbench_Lib1 = /tmp/sim_temp/VHDL_LIBS/ModelSim-2020.02/Testbench_Lib1.lib
+Testbench_ROS_Lib1 = /tmp/sim_temp/VHDL_LIBS/ModelSim-2020.02/Testbench_ROS_Lib1.lib
+Testbench_ROS_Lib2 = /tmp/sim_temp/VHDL_LIBS/ModelSim-2020.02/Testbench_ROS_Lib2.lib
+Testbench_ROS_Lib3 = /tmp/sim_temp/VHDL_LIBS/ModelSim-2020.02/Testbench_ROS_Lib3.lib
+Testbench_ROS_Lib4 = /tmp/sim_temp/VHDL_LIBS/ModelSim-2020.02/Testbench_ROS_Lib4.lib
+Testbench_ROS_Lib5 = /tmp/sim_temp/VHDL_LIBS/ModelSim-2020.02/Testbench_ROS_Lib5.lib
 [vcom]
 ; VHDL93 variable selects language version as the default. 
 ; Default is VHDL-2002.
diff --git a/src/Tests/Level_2/L2_testbench_Lib4.vhd b/src/Tests/Level_2/L2_Testbench_Lib4.vhd
similarity index 100%
rename from src/Tests/Level_2/L2_testbench_Lib4.vhd
rename to src/Tests/Level_2/L2_Testbench_Lib4.vhd
diff --git a/src/Tests/Level_2/L2_testbench_Lib4_config.vhd b/src/Tests/Level_2/L2_Testbench_Lib4_config.vhd
similarity index 100%
rename from src/Tests/Level_2/L2_testbench_Lib4_config.vhd
rename to src/Tests/Level_2/L2_Testbench_Lib4_config.vhd
diff --git a/src/Tests/Level_2/L2_testbench_Lib5.vhd b/src/Tests/Level_2/L2_Testbench_Lib5.vhd
similarity index 100%
rename from src/Tests/Level_2/L2_testbench_Lib5.vhd
rename to src/Tests/Level_2/L2_Testbench_Lib5.vhd
diff --git a/src/Tests/Level_2/L2_testbench_Lib5_config.vhd b/src/Tests/Level_2/L2_Testbench_Lib5_config.vhd
similarity index 100%
rename from src/Tests/Level_2/L2_testbench_Lib5_config.vhd
rename to src/Tests/Level_2/L2_Testbench_Lib5_config.vhd