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Refactor some TEMPLATE VHDL files

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This commit is contained in:
John Ring 2023-07-21 17:01:53 +02:00
parent 41814f6bcc
commit 5f7f2685c2
6 changed files with 53 additions and 53 deletions
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30
src/TEMPLATE_reader_interface.vhd
View File

@ -240,21 +240,6 @@ begin
stage_next <= FETCH;
end if;
end if;
when SKIP_PAYLOAD =>
if (last_word_in_latch = '0') then
-- Skip Read
ready_in_dds_sig <= '1';
else
stage_next <= IDLE;
-- If no Decode Error, mark output as valid
if (decode_error_latch = '0') then
valid_latch_next <= '1';
end if;
-- Reset
last_word_in_latch_next <= '0';
end if;
when DECODE_PAYLOAD =>
case (decode_stage) is
-- ###GENERATED START###
@ -313,6 +298,21 @@ begin
when others =>
null;
end case;
when SKIP_PAYLOAD =>
if (last_word_in_latch = '0') then
-- Skip Read
ready_in_dds_sig <= '1';
else
stage_next <= IDLE;
-- If no Decode Error, mark output as valid
if (decode_error_latch = '0') then
valid_latch_next <= '1';
end if;
-- Reset
last_word_in_latch_next <= '0';
end if;
when others =>
null;
end case;

30
src/Tests/Type1_reader_interface.vhd
View File

@ -237,21 +237,6 @@ begin
stage_next <= FETCH;
end if;
end if;
when SKIP_PAYLOAD =>
if (last_word_in_latch = '0') then
-- Skip Read
ready_in_dds_sig <= '1';
else
stage_next <= IDLE;
-- If no Decode Error, mark output as valid
if (decode_error_latch = '0') then
valid_latch_next <= '1';
end if;
-- Reset
last_word_in_latch_next <= '0';
end if;
when DECODE_PAYLOAD =>
case (decode_stage) is
-- ###GENERATED START###
@ -333,6 +318,21 @@ begin
when others =>
null;
end case;
when SKIP_PAYLOAD =>
if (last_word_in_latch = '0') then
-- Skip Read
ready_in_dds_sig <= '1';
else
stage_next <= IDLE;
-- If no Decode Error, mark output as valid
if (decode_error_latch = '0') then
valid_latch_next <= '1';
end if;
-- Reset
last_word_in_latch_next <= '0';
end if;
when others =>
null;
end case;

2
src/Tests/Type1_writer_interface.vhd
View File

@ -162,7 +162,7 @@ begin
-- Output Guard
if (ready_out_dds = '1') then
stage_next <= ENCODE_PAYLOAD;
-- Reset
-- Reset
align_offset_next <= (others => '0');
data_out_latch_next <= (others => '0');
-- ###GENERATED START###

30
src/Tests/Type2_reader_interface.vhd
View File

@ -604,21 +604,6 @@ begin
stage_next <= FETCH;
end if;
end if;
when SKIP_PAYLOAD =>
if (last_word_in_latch = '0') then
-- Skip Read
ready_in_dds_sig <= '1';
else
stage_next <= IDLE;
-- If no Decode Error, mark output as valid
if (decode_error_latch = '0') then
valid_latch_next <= '1';
end if;
-- Reset
last_word_in_latch_next <= '0';
end if;
when DECODE_PAYLOAD =>
case (decode_stage) is
-- ###GENERATED START###
@ -1102,6 +1087,21 @@ begin
when others =>
null;
end case;
when SKIP_PAYLOAD =>
if (last_word_in_latch = '0') then
-- Skip Read
ready_in_dds_sig <= '1';
else
stage_next <= IDLE;
-- If no Decode Error, mark output as valid
if (decode_error_latch = '0') then
valid_latch_next <= '1';
end if;
-- Reset
last_word_in_latch_next <= '0';
end if;
when others =>
null;
end case;

10
src/ros2/TEMPLATE_ros_pub.vhd
View File

@ -9,7 +9,7 @@ use work.rtps_package.all;
use work.rtps_config_package.all;
use work.ros_package.all;
entity TEMPLATE_pub is
entity TEMPLATE_ros_pub is
generic (
LITTLE_ENDIAN : std_logic := '0'
);
@ -52,7 +52,7 @@ entity TEMPLATE_pub is
);
end entity;
architecture arch of TEMPLATE_pub is
architecture arch of TEMPLATE_ros_pub is
--*****TYPE DECLARATION*****
-- FSM states. Explained below in detail
@ -109,7 +109,7 @@ begin
opcode_dds <= NOP;
valid_out_dds <= '0';
last_word_out_dds <= '0';
ack_user <= '0';
ack_user <= '0';
done_user <= '0';
return_code_user <= ROS_RET_OK;
data_out_dds <= (others => '0');
@ -159,7 +159,7 @@ begin
-- Output Guard
if (ready_out_dds = '1') then
stage_next <= ENCODE_PAYLOAD;
-- Reset
-- Reset
align_offset_next <= (others => '0');
data_out_latch_next <= (others => '0');
-- ###GENERATED START###
@ -253,7 +253,7 @@ begin
align_offset <= align_offset_next;
data_out_latch <= data_out_latch_next;
-- ###GENERATED START###
-- SYNC SIGNALS
-- SYNC SIGNALS
-- ###GENERATED END###
end if;
end if;

4
src/ros2/TEMPLATE_ros_sub.vhd
View File

@ -9,7 +9,7 @@ use work.rtps_package.all;
use work.rtps_config_package.all;
use work.ros_package.all;
entity TEMPLATE_sub is
entity TEMPLATE_ros_sub is
port (
-- SYSTEM
clk : in std_logic;
@ -55,7 +55,7 @@ entity TEMPLATE_sub is
);
end entity;
architecture arch of TEMPLATE_sub is
architecture arch of TEMPLATE_ros_sub is
--*****TYPE DECLARATION*****
-- FSM states. Explained below in detail