From 63465e8e304100ca3cff6e3ae8f93f191c49268d Mon Sep 17 00:00:00 2001 From: Greek Date: Fri, 19 Nov 2021 18:50:18 +0100 Subject: [PATCH] Remove default signal initialization from entire codebase --- src/FWFT_FIFO.vhd | 4 +- src/TEMPLATE_key_holder.vhd | 50 ++-- src/TEMPLATE_reader_wrapper.vhd | 32 +-- src/TEMPLATE_writer_wrapper.vhd | 19 +- .../Level_1/L1_Type1_key_holder_test1.vhd | 9 +- .../Level_1/L1_Type1_key_holder_test2.vhd | 9 +- src/Tests/Level_1/L1_Type1_wrapper_test1.vhd | 8 +- src/Tests/Level_1/L1_Type1_wrapper_test2.vhd | 8 +- .../Level_1/L1_Type2_key_holder_test1.vhd | 9 +- .../Level_1/L1_Type2_key_holder_test2.vhd | 9 +- src/Tests/Level_1/L1_Type2_wrapper_test1.vhd | 9 +- src/Tests/Level_1/L1_Type2_wrapper_test2.vhd | 8 +- src/Tests/Level_2/L2_Testbench_Lib2.vhd | 58 ++--- src/Tests/Level_2/L2_Testbench_Lib3.vhd | 66 ++--- src/Tests/Type1_key_holder.vhd | 52 ++-- src/Tests/Type1_reader_wrapper.vhd | 36 +-- src/Tests/Type1_writer_wrapper.vhd | 19 +- src/Tests/Type2_key_holder.vhd | 66 ++--- src/Tests/Type2_reader_wrapper.vhd | 114 ++++---- src/Tests/Type2_writer_wrapper.vhd | 77 +++--- src/Tests/test_key_hash_generator.vhd | 6 +- src/Tests/test_key_holder.vhd | 6 +- src/addsub.vhd | 4 +- src/checksum.vhd | 4 +- src/dds_reader.vhd | 246 +++++++++--------- src/dds_writer.vhd | 206 +++++++-------- src/history_cache.vhd | 134 +++++----- src/ipv4_in_handler.vhd | 68 ++--- src/mem_ctrl.vhd | 10 +- src/rtps_builtin_endpoint.vhd | 178 ++++++------- src/rtps_handler.vhd | 88 +++---- src/rtps_out.vhd | 24 +- src/rtps_reader.vhd | 120 ++++----- src/rtps_writer.vhd | 126 ++++----- 34 files changed, 954 insertions(+), 928 deletions(-) diff --git a/src/FWFT_FIFO.vhd b/src/FWFT_FIFO.vhd index 781bf96..2120fa6 100644 --- a/src/FWFT_FIFO.vhd +++ b/src/FWFT_FIFO.vhd @@ -29,8 +29,8 @@ architecture arch of FWFT_FIFO is type FIFO_DATA_ARRAY is array (FIFO_DEPTH-1 downto 0) of std_logic_vector(DATA_WIDTH-1 downto 0); -- *SIGNAL DECLARATIONS* - signal fifo_data : FIFO_DATA_ARRAY := (others => (others => '0')); - signal free_sig : natural range 0 to FIFO_DEPTH := FIFO_DEPTH; + signal fifo_data : FIFO_DATA_ARRAY; + signal free_sig : natural range 0 to FIFO_DEPTH; begin data_out <= fifo_data(0); diff --git a/src/TEMPLATE_key_holder.vhd b/src/TEMPLATE_key_holder.vhd index b7841b7..e88d288 100644 --- a/src/TEMPLATE_key_holder.vhd +++ b/src/TEMPLATE_key_holder.vhd @@ -37,30 +37,30 @@ architecture TYPENAME of key_holder is -- ###GENERATED END### -- *MAIN PROCESS* - signal stage, stage_next : STAGE_TYPE := IDLE; - signal cnt, cnt_next : natural range 0 to 5 := 0; - signal endian_flag, endian_flag_next : std_logic := '0'; - signal last_word_in_latch, last_word_in_latch_next : std_logic := '0'; - signal decode_error_latch, decode_error_latch_next : std_logic := '0'; - signal align_offset, align_offset_next : unsigned(MAX_ALIGN_OFFSET_WIDTH-1 downto 0) := (others => '0'); - signal target_align, target_align_next : ALIGN_TYPE := ALIGN_1; - signal data_in_latch, data_in_latch_next : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); - signal data_out_latch, data_out_latch_next : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); - signal optional, optional_next : std_logic := '0'; - signal abort_mem : std_logic := '0'; - signal opcode_latch, opcode_latch_next : KEY_HOLDER_OPCODE_TYPE := NOP; - signal cnt_2, cnt_2_next : natural range 0 to (WORD_WIDTH/BYTE_WIDTH)-1 := 0; - signal align_op, align_op_next : std_logic := '0'; - signal finalize_payload, finalize_payload_next : std_logic := '0'; - signal ready_in_sig : std_logic := '0'; - signal start_kh, ack_kh, done_kh : std_logic := '0'; - signal data_in_kh : std_logic_vector(BYTE_WIDTH-1 downto 0) := (others => '0'); - signal valid_in_kh, ready_in_kh, last_word_in_kh : std_logic := '0'; - signal key_hash_kh : std_logic_vector(KEY_HASH_WIDTH-1 downto 0) := (others => '0'); - signal key_hash, key_hash_next : KEY_HASH_TYPE := HANDLE_NIL; - signal decode_stage, decode_stage_next : DECODE_STAGE_TYPE := TODO; - signal encode_stage, encode_stage_next : ENCODE_STAGE_TYPE := TODO; - signal return_stage, return_stage_next : DECODE_STAGE_TYPE := TODO; + signal stage, stage_next : STAGE_TYPE; + signal cnt, cnt_next : natural range 0 to 5; + signal endian_flag, endian_flag_next : std_logic; + signal last_word_in_latch, last_word_in_latch_next : std_logic; + signal decode_error_latch, decode_error_latch_next : std_logic; + signal align_offset, align_offset_next : unsigned(MAX_ALIGN_OFFSET_WIDTH-1 downto 0); + signal target_align, target_align_next : ALIGN_TYPE; + signal data_in_latch, data_in_latch_next : std_logic_vector(WORD_WIDTH-1 downto 0); + signal data_out_latch, data_out_latch_next : std_logic_vector(WORD_WIDTH-1 downto 0); + signal optional, optional_next : std_logic; + signal abort_mem : std_logic; + signal opcode_latch, opcode_latch_next : KEY_HOLDER_OPCODE_TYPE; + signal cnt_2, cnt_2_next : natural range 0 to (WORD_WIDTH/BYTE_WIDTH)-1; + signal align_op, align_op_next : std_logic; + signal finalize_payload, finalize_payload_next : std_logic + signal ready_in_sig : std_logic; + signal start_kh, ack_kh, done_kh : std_logic; + signal data_in_kh : std_logic_vector(BYTE_WIDTH-1 downto 0); + signal valid_in_kh, ready_in_kh, last_word_in_kh : std_logic; + signal key_hash_kh : std_logic_vector(KEY_HASH_WIDTH-1 downto 0); + signal key_hash, key_hash_next : KEY_HASH_TYPE; + signal decode_stage, decode_stage_next : DECODE_STAGE_TYPE; + signal encode_stage, encode_stage_next : ENCODE_STAGE_TYPE; + signal return_stage, return_stage_next : DECODE_STAGE_TYPE; -- ###GENERATED START### -- SIGNAL DECLARATION -- ###GENERATED END### @@ -96,7 +96,7 @@ begin ready_in <= ready_in_sig; main_prc : process (all) - variable tmp_length : unsigned(WORD_WIDTH-1 downto 0) := (others => '0'); + variable tmp_length : unsigned(WORD_WIDTH-1 downto 0); begin -- DEFAULT stage_next <= stage; diff --git a/src/TEMPLATE_reader_wrapper.vhd b/src/TEMPLATE_reader_wrapper.vhd index b1c15e7..596f879 100644 --- a/src/TEMPLATE_reader_wrapper.vhd +++ b/src/TEMPLATE_reader_wrapper.vhd @@ -96,21 +96,21 @@ architecture arch of Type2_reader_wrapper is -- ###GENERATED END### -- *MAIN PROCESS* - signal stage, stage_next : STAGE_TYPE := IDLE; - signal cnt, cnt_next : natural range 0 to 5 := 0; - signal endian_flag, endian_flag_next : std_logic := '0'; - signal last_word_in_latch, last_word_in_latch_next : std_logic := '0'; - signal decode_error_latch, decode_error_latch_next : std_logic := '0'; - signal align_offset, align_offset_next : unsigned(MAX_ALIGN_OFFSET_WIDTH-1 downto 0) := (others => '0'); - signal align_op, align_op_next : std_logic := '0'; - signal target_align, target_align_next : ALIGN_TYPE := ALIGN_1; - signal data_in_latch, data_in_latch_next : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); - signal optional, optional_next : std_logic := '0'; - signal abort_mem : std_logic := '0'; - signal ready_in_dds_sig : std_logic := '0'; - signal valid_latch, valid_latch_next : std_logic := '0'; - signal decode_stage, decode_stage_next : DECODE_STAGE_TYPE := TODO; - signal return_stage, return_stage_next : DECODE_STAGE_TYPE := TODO; + signal stage, stage_next : STAGE_TYPE; + signal cnt, cnt_next : natural range 0 to 5; + signal endian_flag, endian_flag_next : std_logic; + signal last_word_in_latch, last_word_in_latch_next : std_logic; + signal decode_error_latch, decode_error_latch_next : std_logic; + signal align_offset, align_offset_next : unsigned(MAX_ALIGN_OFFSET_WIDTH-1 downto 0); + signal align_op, align_op_next : std_logic; + signal target_align, target_align_next : ALIGN_TYPE; + signal data_in_latch, data_in_latch_next : std_logic_vector(WORD_WIDTH-1 downto 0); + signal optional, optional_next : std_logic; + signal abort_mem : std_logic; + signal ready_in_dds_sig : std_logic; + signal valid_latch, valid_latch_next : std_logic; + signal decode_stage, decode_stage_next : DECODE_STAGE_TYPE; + signal return_stage, return_stage_next : DECODE_STAGE_TYPE; -- ###GENERATED START### -- SIGNAL DECLARATIONS -- ###GENERATED END### @@ -166,7 +166,7 @@ begin -- ###GENERATED END### main_prc : process (all) - variable tmp_length : unsigned(WORD_WIDTH-1 downto 0) := (others => '0'); + variable tmp_length : unsigned(WORD_WIDTH-1 downto 0); begin -- DEFAULT stage_next <= stage; diff --git a/src/TEMPLATE_writer_wrapper.vhd b/src/TEMPLATE_writer_wrapper.vhd index 9b1e008..6aebeb2 100644 --- a/src/TEMPLATE_writer_wrapper.vhd +++ b/src/TEMPLATE_writer_wrapper.vhd @@ -69,15 +69,15 @@ architecture arch of Type2_writer_wrapper is -- ###GENERATED END### -- *MAIN PROCESS* - signal stage, stage_next : STAGE_TYPE := IDLE; - signal cnt, cnt_next : natural range 0 to 5 := 0; - signal align_offset, align_offset_next : unsigned(MAX_ALIGN_OFFSET_WIDTH-1 downto 0) := (others => '0'); - signal align_op, align_op_next : std_logic := '0'; - signal target_align, target_align_next : ALIGN_TYPE := ALIGN_1; - signal data_out_latch, data_out_latch_next : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); - signal abort_mem : std_logic := '0'; - signal finalize_payload, finalize_payload_next : std_logic := '0'; - signal encode_stage, encode_stage_next : ENCODE_STAGE_TYPE := TODO; + signal stage, stage_next : STAGE_TYPE; + signal cnt, cnt_next : natural range 0 to 5; + signal align_offset, align_offset_next : unsigned(MAX_ALIGN_OFFSET_WIDTH-1 downto 0); + signal align_op, align_op_next : std_logic; + signal target_align, target_align_next : ALIGN_TYPE; + signal data_out_latch, data_out_latch_next : std_logic_vector(WORD_WIDTH-1 downto 0); + signal abort_mem : std_logic; + signal finalize_payload, finalize_payload_next : std_logic; + signal encode_stage, encode_stage_next : ENCODE_STAGE_TYPE; -- ###GENERATED START### -- SIGNAL DECLARATION -- ###GENERATED END### @@ -109,7 +109,6 @@ begin -- ###GENERATED END### main_prc : process (all) - variable tmp_length : unsigned(WORD_WIDTH-1 downto 0) := (others => '0'); begin -- DEFAULT stage_next <= stage; diff --git a/src/Tests/Level_1/L1_Type1_key_holder_test1.vhd b/src/Tests/Level_1/L1_Type1_key_holder_test1.vhd index 7163b1b..96bfecf 100644 --- a/src/Tests/Level_1/L1_Type1_key_holder_test1.vhd +++ b/src/Tests/Level_1/L1_Type1_key_holder_test1.vhd @@ -125,11 +125,14 @@ begin SK := GetAlertLogID("SerializedKey", ALERTLOG_BASE_ID); KH := GetAlertLogID("KeyHash", ALERTLOG_BASE_ID); - Log("Setting Data in Writer Side", INFO); - - start_w <= '0'; + Log("Initial Reset", INFO); + start_w <= '0'; + reset <= '1'; wait until rising_edge(clk); + wait until rising_edge(clk); + reset <= '0'; + Log("Setting Data in Writer Side", INFO); -- Static id_in <= RV.RandSlv(id_in'length); a_in <= RV.RandSlv(a_in'length); diff --git a/src/Tests/Level_1/L1_Type1_key_holder_test2.vhd b/src/Tests/Level_1/L1_Type1_key_holder_test2.vhd index ada7bd0..27df847 100644 --- a/src/Tests/Level_1/L1_Type1_key_holder_test2.vhd +++ b/src/Tests/Level_1/L1_Type1_key_holder_test2.vhd @@ -128,11 +128,14 @@ begin SK := GetAlertLogID("SerializedKey", ALERTLOG_BASE_ID); KH := GetAlertLogID("KeyHash", ALERTLOG_BASE_ID); - Log("Setting Data in Writer Side", INFO); - - start_w <= '0'; + Log("Initial Reset", INFO); + start_w <= '0'; + reset <= '1'; wait until rising_edge(clk); + wait until rising_edge(clk); + reset <= '0'; + Log("Setting Data in Writer Side", INFO); -- Static id_in <= RV.RandSlv(id_in'length); a_in <= RV.RandSlv(a_in'length); diff --git a/src/Tests/Level_1/L1_Type1_wrapper_test1.vhd b/src/Tests/Level_1/L1_Type1_wrapper_test1.vhd index 0384de7..88bd089 100644 --- a/src/Tests/Level_1/L1_Type1_wrapper_test1.vhd +++ b/src/Tests/Level_1/L1_Type1_wrapper_test1.vhd @@ -159,11 +159,15 @@ begin ID := GetAlertLogID("ID", ALERTLOG_BASE_ID); A := GetAlertLogID("A", ALERTLOG_BASE_ID); - Log("Setting Data in Writer Side", INFO); - + Log("Initial Reset", INFO); start_w <= '0'; get_data_r <= '0'; + reset <= '1'; + wait until rising_edge(clk); + wait until rising_edge(clk); + reset <= '0'; + Log("Setting Data in Writer Side", INFO); -- Static id_in <= RV.RandSlv(id_in'length); a_in <= RV.RandSlv(a_in'length); diff --git a/src/Tests/Level_1/L1_Type1_wrapper_test2.vhd b/src/Tests/Level_1/L1_Type1_wrapper_test2.vhd index 7a87572..10ac9b7 100644 --- a/src/Tests/Level_1/L1_Type1_wrapper_test2.vhd +++ b/src/Tests/Level_1/L1_Type1_wrapper_test2.vhd @@ -162,11 +162,15 @@ begin ID := GetAlertLogID("ID", ALERTLOG_BASE_ID); A := GetAlertLogID("A", ALERTLOG_BASE_ID); - Log("Setting Data in Writer Side", INFO); - + Log("Initial Reset", INFO); start_w <= '0'; get_data_r <= '0'; + reset <= '1'; + wait until rising_edge(clk); + wait until rising_edge(clk); + reset <= '0'; + Log("Setting Data in Writer Side", INFO); -- Static id_in <= RV.RandSlv(id_in'length); a_in <= RV.RandSlv(a_in'length); diff --git a/src/Tests/Level_1/L1_Type2_key_holder_test1.vhd b/src/Tests/Level_1/L1_Type2_key_holder_test1.vhd index 9fabe94..27e474b 100644 --- a/src/Tests/Level_1/L1_Type2_key_holder_test1.vhd +++ b/src/Tests/Level_1/L1_Type2_key_holder_test1.vhd @@ -197,11 +197,14 @@ begin SK := GetAlertLogID("SerializedKey", ALERTLOG_BASE_ID); KH := GetAlertLogID("KeyHash", ALERTLOG_BASE_ID); - Log("Setting Data in Writer Side", INFO); - - start_w <= '0'; + Log("Initial Reset", INFO); + start_w <= '0'; + reset <= '1'; wait until rising_edge(clk); + wait until rising_edge(clk); + reset <= '0'; + Log("Setting Data in Writer Side", INFO); -- Static id_in <= RV.RandSlv(id_in'length); TestEnum_in <= RV.RandSlv(TestEnum_in'length); diff --git a/src/Tests/Level_1/L1_Type2_key_holder_test2.vhd b/src/Tests/Level_1/L1_Type2_key_holder_test2.vhd index f525fa6..e8e65de 100644 --- a/src/Tests/Level_1/L1_Type2_key_holder_test2.vhd +++ b/src/Tests/Level_1/L1_Type2_key_holder_test2.vhd @@ -200,11 +200,14 @@ begin SK := GetAlertLogID("SerializedKey", ALERTLOG_BASE_ID); KH := GetAlertLogID("KeyHash", ALERTLOG_BASE_ID); - Log("Setting Data in Writer Side", INFO); - - start_w <= '0'; + Log("Initial Reset", INFO); + start_w <= '0'; + reset <= '1'; wait until rising_edge(clk); + wait until rising_edge(clk); + reset <= '0'; + Log("Setting Data in Writer Side", INFO); -- Static id_in <= RV.RandSlv(id_in'length); TestEnum_in <= RV.RandSlv(TestEnum_in'length); diff --git a/src/Tests/Level_1/L1_Type2_wrapper_test1.vhd b/src/Tests/Level_1/L1_Type2_wrapper_test1.vhd index 5ff5b9e..689daf1 100644 --- a/src/Tests/Level_1/L1_Type2_wrapper_test1.vhd +++ b/src/Tests/Level_1/L1_Type2_wrapper_test1.vhd @@ -277,10 +277,15 @@ begin TB := GetAlertLogID("TestBitmask", ALERTLOG_BASE_ID); TS := GetAlertLogID("TestString", ALERTLOG_BASE_ID); - Log("Setting Data in Writer Side", INFO); - + Log("Initial Reset", INFO); start_w <= '0'; get_data_r <= '0'; + reset <= '1'; + wait until rising_edge(clk); + wait until rising_edge(clk); + reset <= '0'; + + Log("Setting Data in Writer Side", INFO); -- Static id_in <= RV.RandSlv(id_in'length); diff --git a/src/Tests/Level_1/L1_Type2_wrapper_test2.vhd b/src/Tests/Level_1/L1_Type2_wrapper_test2.vhd index ce4aef1..1b4591b 100644 --- a/src/Tests/Level_1/L1_Type2_wrapper_test2.vhd +++ b/src/Tests/Level_1/L1_Type2_wrapper_test2.vhd @@ -280,11 +280,15 @@ begin TB := GetAlertLogID("TestBitmask", ALERTLOG_BASE_ID); TS := GetAlertLogID("TestString", ALERTLOG_BASE_ID); - Log("Setting Data in Writer Side", INFO); - + Log("Initial Reset", INFO); start_w <= '0'; get_data_r <= '0'; + reset <= '1'; + wait until rising_edge(clk); + wait until rising_edge(clk); + reset <= '0'; + Log("Setting Data in Writer Side", INFO); -- Static id_in <= RV.RandSlv(id_in'length); TestEnum_in <= RV.RandSlv(TestEnum_in'length); diff --git a/src/Tests/Level_2/L2_Testbench_Lib2.vhd b/src/Tests/Level_2/L2_Testbench_Lib2.vhd index ce8fc49..2a311f3 100644 --- a/src/Tests/Level_2/L2_Testbench_Lib2.vhd +++ b/src/Tests/Level_2/L2_Testbench_Lib2.vhd @@ -52,39 +52,39 @@ architecture arch of L2_Testbench_Lib2 is type ENDPOINT_DATA_TYPE is array (0 to NUM_ENDPOINTS) of std_logic_vector(WORD_WIDTH downto 0); -- INTERCONNECT - signal start_wr_dds, ack_wr_dds, done_wr_dds, ready_out_wr_dds, valid_out_wr_dds, last_word_out_wr_dds, ready_in_wr_dds, valid_in_wr_dds, last_word_in_wr_dds : std_logic := '0'; - signal opcode_wr_dds : DDS_WRITER_OPCODE_TYPE := NOP; - signal instance_handle_wr_dds : INSTANCE_HANDLE_TYPE := HANDLE_NIL; - signal source_ts_wr_dds : TIME_TYPE := TIME_ZERO; - signal max_wait_wr_dds : DURATION_TYPE := DURATION_ZERO; - signal return_code_wr_dds : std_logic_vector(RETURN_CODE_WIDTH-1 downto 0) := RETCODE_OK; - signal data_in_wr_dds, data_out_wr_dds : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); - signal status_wr_dds : std_logic_vector(STATUS_KIND_WIDTH-1 downto 0) := (others => '0'); - signal start_dds_rtps, ack_dds_rtps, done_dds_rtps, get_data_dds_rtps, valid_out_dds_rtps, ready_out_dds_rtps, last_word_out_dds_rtps, liveliness_assertion_dds_rtps, data_available_dds_rtps : std_logic := '0'; - signal data_out_dds_rtps : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); - signal opcode_dds_rtps : HISTORY_CACHE_OPCODE_TYPE := NOP; - signal ret_dds_rtps : HISTORY_CACHE_RESPONSE_TYPE := OK; - signal seq_nr_dds_rtps : SEQUENCENUMBER_TYPE := SEQUENCENUMBER_UNKNOWN; - signal cc_instance_handle_dds_rtps : INSTANCE_HANDLE_TYPE := HANDLE_NIL; - signal cc_kind_dds_rtps : CACHE_CHANGE_KIND_TYPE := ALIVE; - signal cc_source_timestamp_dds_rtps : TIME_TYPE := TIME_ZERO; - signal cc_seq_nr_dds_rtps : SEQUENCENUMBER_TYPE := SEQUENCENUMBER_UNKNOWN; + signal start_wr_dds, ack_wr_dds, done_wr_dds, ready_out_wr_dds, valid_out_wr_dds, last_word_out_wr_dds, ready_in_wr_dds, valid_in_wr_dds, last_word_in_wr_dds : std_logic; + signal opcode_wr_dds : DDS_WRITER_OPCODE_TYPE; + signal instance_handle_wr_dds : INSTANCE_HANDLE_TYPE; + signal source_ts_wr_dds : TIME_TYPE; + signal max_wait_wr_dds : DURATION_TYPE; + signal return_code_wr_dds : std_logic_vector(RETURN_CODE_WIDTH-1 downto 0); + signal data_in_wr_dds, data_out_wr_dds : std_logic_vector(WORD_WIDTH-1 downto 0); + signal status_wr_dds : std_logic_vector(STATUS_KIND_WIDTH-1 downto 0); + signal start_dds_rtps, ack_dds_rtps, done_dds_rtps, get_data_dds_rtps, valid_out_dds_rtps, ready_out_dds_rtps, last_word_out_dds_rtps, liveliness_assertion_dds_rtps, data_available_dds_rtps : std_logic; + signal data_out_dds_rtps : std_logic_vector(WORD_WIDTH-1 downto 0); + signal opcode_dds_rtps : HISTORY_CACHE_OPCODE_TYPE; + signal ret_dds_rtps : HISTORY_CACHE_RESPONSE_TYPE; + signal seq_nr_dds_rtps : SEQUENCENUMBER_TYPE; + signal cc_instance_handle_dds_rtps : INSTANCE_HANDLE_TYPE; + signal cc_kind_dds_rtps : CACHE_CHANGE_KIND_TYPE; + signal cc_source_timestamp_dds_rtps : TIME_TYPE; + signal cc_seq_nr_dds_rtps : SEQUENCENUMBER_TYPE; - signal empty_rh, full_rh, rd_rh, wr_rh : std_logic_vector(0 to NUM_ENDPOINTS) := (others => '0'); - signal data_in_rh, data_out_rh : ENDPOINT_DATA_TYPE := (others => (others => '0')); + signal empty_rh, full_rh, rd_rh, wr_rh : std_logic_vector(0 to NUM_ENDPOINTS); + signal data_in_rh, data_out_rh : ENDPOINT_DATA_TYPE; - signal empty_rtps, full_rtps, rd_rtps, wr_rtps, alive_sig_rtps : std_logic_vector(0 to NUM_ENDPOINTS) := (others => '0'); - signal data_in_rtps, data_out_rtps : ENDPOINT_DATA_TYPE := (others => (others => '0')); + signal empty_rtps, full_rtps, rd_rtps, wr_rtps, alive_sig_rtps : std_logic_vector(0 to NUM_ENDPOINTS); + signal data_in_rtps, data_out_rtps : ENDPOINT_DATA_TYPE; - signal wr_rtps_out, rd_rtps_out, full_rtps_out, empty_rtps_out : std_logic_vector(0 to NUM_ENDPOINTS) := (others => '0'); - signal data_out_rtps_out, data_in_rtps_out : ENDPOINT_DATA_TYPE := (others => (others => '0')); + signal wr_rtps_out, rd_rtps_out, full_rtps_out, empty_rtps_out : std_logic_vector(0 to NUM_ENDPOINTS); + signal data_out_rtps_out, data_in_rtps_out : ENDPOINT_DATA_TYPE; - signal last_word_out_rbe : std_logic := '0'; - signal data_out_rbe : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); - signal last_word_out_rh_be_s, last_word_out_rh_ue_s : std_logic := '0'; - signal data_out_rh_be_s, data_out_rh_ue_s : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); - signal data_rtps_out_s : RTPS_OUT_DATA_TYPE := (others => (others => '0')); - signal last_word_rtps_out_s : std_logic_vector(0 to NUM_ENDPOINTS) := (others => '0'); + signal last_word_out_rbe : std_logic; + signal data_out_rbe : std_logic_vector(WORD_WIDTH-1 downto 0); + signal last_word_out_rh_be_s, last_word_out_rh_ue_s : std_logic; + signal data_out_rh_be_s, data_out_rh_ue_s : std_logic_vector(WORD_WIDTH-1 downto 0); + signal data_rtps_out_s : RTPS_OUT_DATA_TYPE; + signal last_word_rtps_out_s : std_logic_vector(0 to NUM_ENDPOINTS); begin diff --git a/src/Tests/Level_2/L2_Testbench_Lib3.vhd b/src/Tests/Level_2/L2_Testbench_Lib3.vhd index 627a4c6..772e4ad 100644 --- a/src/Tests/Level_2/L2_Testbench_Lib3.vhd +++ b/src/Tests/Level_2/L2_Testbench_Lib3.vhd @@ -70,44 +70,44 @@ architecture arch of L2_Testbench_Lib3 is type ENDPOINT_DATA_TYPE is array (0 to NUM_ENDPOINTS) of std_logic_vector(WORD_WIDTH downto 0); -- INTERCONNECT - signal start_wr_dds, ack_wr_dds, get_data_wr_dds, done_wr_dds, ready_in_wr_dds, valid_in_wr_dds, last_word_in_wr_dds, si_valid_data_wr_dds, si_valid_wr_dds, si_ack_wr_dds, eoc_wr_dds : std_logic := '0'; - signal opcode_wr_dds : DDS_READER_OPCODE_TYPE := NOP; - signal instance_state_wr_dds, si_instance_state_wr_dds : std_logic_vector(INSTANCE_STATE_KIND_WIDTH-1 downto 0) := ANY_INSTANCE_STATE; - signal view_state_wr_dds, si_view_state_wr_dds : std_logic_vector(VIEW_STATE_KIND_WIDTH-1 downto 0) := ANY_VIEW_STATE; - signal sample_state_wr_dds, si_sample_state_wr_dds : std_logic_vector(SAMPLE_STATE_KIND_WIDTH-1 downto 0) := ANY_SAMPLE_STATE; - signal instance_handle_wr_dds, si_instance_handle_wr_dds : INSTANCE_HANDLE_TYPE := HANDLE_NIL; - signal max_samples_wr_dds : std_logic_vector(MAX_SAMPLES_WIDTH-1 downto 0) := (others => '0'); - signal return_code_wr_dds : std_logic_vector(RETURN_CODE_WIDTH-1 downto 0) := RETCODE_OK; - signal data_in_wr_dds : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); - signal si_source_timestamp_wr_dds : TIME_TYPE := TIME_ZERO; - signal si_publication_handle_wr_dds : PUBLICATION_HANDLE_TYPE := GUID_UNKNOWN; - signal si_disposed_generation_count_wr_dds : std_logic_vector(DISPOSED_GENERATION_COUNT_WIDTH-1 downto 0) := (others => '0'); - signal si_no_writers_generation_count_wr_dds : std_logic_vector(NO_WRITERS_GENERATION_COUNT_WIDTH-1 downto 0) := (others => '0'); - signal si_sample_rank_wr_dds : std_logic_vector(SAMPLE_RANK_WIDTH-1 downto 0) := (others => '0'); - signal si_generation_rank_wr_dds : std_logic_vector(GENERATION_RANK_WIDTH-1 downto 0) := (others => '0'); - signal si_absolute_generation_rank_wr_dds : std_logic_vector(ABSOLUTE_GENERATION_COUNT_WIDTH-1 downto 0) := (others => '0'); - signal status_wr_dds : std_logic_vector(STATUS_KIND_WIDTH-1 downto 0) := (others => '0'); + signal start_wr_dds, ack_wr_dds, get_data_wr_dds, done_wr_dds, ready_in_wr_dds, valid_in_wr_dds, last_word_in_wr_dds, si_valid_data_wr_dds, si_valid_wr_dds, si_ack_wr_dds, eoc_wr_dds : std_logic; + signal opcode_wr_dds : DDS_READER_OPCODE_TYPE; + signal instance_state_wr_dds, si_instance_state_wr_dds : std_logic_vector(INSTANCE_STATE_KIND_WIDTH-1 downto 0); + signal view_state_wr_dds, si_view_state_wr_dds : std_logic_vector(VIEW_STATE_KIND_WIDTH-1 downto 0); + signal sample_state_wr_dds, si_sample_state_wr_dds : std_logic_vector(SAMPLE_STATE_KIND_WIDTH-1 downto 0); + signal instance_handle_wr_dds, si_instance_handle_wr_dds : INSTANCE_HANDLE_TYPE; + signal max_samples_wr_dds : std_logic_vector(MAX_SAMPLES_WIDTH-1 downto 0); + signal return_code_wr_dds : std_logic_vector(RETURN_CODE_WIDTH-1 downto 0); + signal data_in_wr_dds : std_logic_vector(WORD_WIDTH-1 downto 0); + signal si_source_timestamp_wr_dds : TIME_TYPE; + signal si_publication_handle_wr_dds : PUBLICATION_HANDLE_TYPE; + signal si_disposed_generation_count_wr_dds : std_logic_vector(DISPOSED_GENERATION_COUNT_WIDTH-1 downto 0); + signal si_no_writers_generation_count_wr_dds : std_logic_vector(NO_WRITERS_GENERATION_COUNT_WIDTH-1 downto 0); + signal si_sample_rank_wr_dds : std_logic_vector(SAMPLE_RANK_WIDTH-1 downto 0); + signal si_generation_rank_wr_dds : std_logic_vector(GENERATION_RANK_WIDTH-1 downto 0); + signal si_absolute_generation_rank_wr_dds : std_logic_vector(ABSOLUTE_GENERATION_COUNT_WIDTH-1 downto 0); + signal status_wr_dds : std_logic_vector(STATUS_KIND_WIDTH-1 downto 0); - signal start_dds_rtps, ack_dds_rtps, done_dds_rtps, valid_in_dds_rtps, ready_in_dds_rtps, last_word_in_dds_rtps : std_logic := '0'; - signal opcode_dds_rtps : HISTORY_CACHE_OPCODE_TYPE := NOP; - signal ret_dds_rtps : HISTORY_CACHE_RESPONSE_TYPE := OK; - signal data_in_dds_rtps : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); + signal start_dds_rtps, ack_dds_rtps, done_dds_rtps, valid_in_dds_rtps, ready_in_dds_rtps, last_word_in_dds_rtps : std_logic; + signal opcode_dds_rtps : HISTORY_CACHE_OPCODE_TYPE; + signal ret_dds_rtps : HISTORY_CACHE_RESPONSE_TYPE; + signal data_in_dds_rtps : std_logic_vector(WORD_WIDTH-1 downto 0); - signal empty_rh, full_rh, rd_rh, wr_rh : std_logic_vector(0 to NUM_ENDPOINTS) := (others => '0'); - signal data_in_rh, data_out_rh : ENDPOINT_DATA_TYPE := (others => (others => '0')); + signal empty_rh, full_rh, rd_rh, wr_rh : std_logic_vector(0 to NUM_ENDPOINTS); + signal data_in_rh, data_out_rh : ENDPOINT_DATA_TYPE; - signal empty_rtps, full_rtps, rd_rtps, wr_rtps, alive_sig_rtps : std_logic_vector(0 to NUM_ENDPOINTS) := (others => '0'); - signal data_in_rtps, data_out_rtps : ENDPOINT_DATA_TYPE := (others => (others => '0')); + signal empty_rtps, full_rtps, rd_rtps, wr_rtps, alive_sig_rtps : std_logic_vector(0 to NUM_ENDPOINTS); + signal data_in_rtps, data_out_rtps : ENDPOINT_DATA_TYPE; - signal wr_rtps_out, rd_rtps_out, full_rtps_out, empty_rtps_out : std_logic_vector(0 to NUM_ENDPOINTS) := (others => '0'); - signal data_out_rtps_out, data_in_rtps_out : ENDPOINT_DATA_TYPE := (others => (others => '0')); + signal wr_rtps_out, rd_rtps_out, full_rtps_out, empty_rtps_out : std_logic_vector(0 to NUM_ENDPOINTS); + signal data_out_rtps_out, data_in_rtps_out : ENDPOINT_DATA_TYPE; - signal last_word_out_rbe : std_logic := '0'; - signal data_out_rbe : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); - signal last_word_out_rh_be_s, last_word_out_rh_ue_s : std_logic := '0'; - signal data_out_rh_be_s, data_out_rh_ue_s : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); - signal data_rtps_out_s : RTPS_OUT_DATA_TYPE := (others => (others => '0')); - signal last_word_rtps_out_s : std_logic_vector(0 to NUM_ENDPOINTS) := (others => '0'); + signal last_word_out_rbe : std_logic; + signal data_out_rbe : std_logic_vector(WORD_WIDTH-1 downto 0); + signal last_word_out_rh_be_s, last_word_out_rh_ue_s : std_logic; + signal data_out_rh_be_s, data_out_rh_ue_s : std_logic_vector(WORD_WIDTH-1 downto 0); + signal data_rtps_out_s : RTPS_OUT_DATA_TYPE; + signal last_word_rtps_out_s : std_logic_vector(0 to NUM_ENDPOINTS); diff --git a/src/Tests/Type1_key_holder.vhd b/src/Tests/Type1_key_holder.vhd index 9122763..fb110c7 100644 --- a/src/Tests/Type1_key_holder.vhd +++ b/src/Tests/Type1_key_holder.vhd @@ -36,32 +36,32 @@ architecture TYPE1 of key_holder is -- ###GENERATED END### -- *MAIN PROCESS* - signal stage, stage_next : STAGE_TYPE := IDLE; - signal cnt, cnt_next : natural range 0 to 5 := 0; - signal endian_flag, endian_flag_next : std_logic := '0'; - signal last_word_in_latch, last_word_in_latch_next : std_logic := '0'; - signal decode_error_latch, decode_error_latch_next : std_logic := '0'; - signal align_offset, align_offset_next : unsigned(MAX_ALIGN_OFFSET_WIDTH-1 downto 0) := (others => '0'); - signal target_align, target_align_next : ALIGN_TYPE := ALIGN_1; - signal data_in_latch, data_in_latch_next : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); - signal data_out_latch, data_out_latch_next : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); - signal optional, optional_next : std_logic := '0'; - signal abort_mem : std_logic := '0'; - signal opcode_latch, opcode_latch_next : KEY_HOLDER_OPCODE_TYPE := NOP; - signal cnt_2, cnt_2_next : natural range 0 to (WORD_WIDTH/BYTE_WIDTH)-1 := 0; - signal align_op, align_op_next : std_logic := '0'; - signal finalize_payload, finalize_payload_next : std_logic := '0'; - signal ready_in_sig : std_logic := '0'; - signal start_kh, ack_kh, done_kh : std_logic := '0'; - signal data_in_kh : std_logic_vector(BYTE_WIDTH-1 downto 0) := (others => '0'); - signal valid_in_kh, ready_in_kh, last_word_in_kh : std_logic := '0'; - signal key_hash_kh : std_logic_vector(KEY_HASH_WIDTH-1 downto 0) := (others => '0'); - signal key_hash, key_hash_next : KEY_HASH_TYPE := HANDLE_NIL; - signal decode_stage, decode_stage_next : DECODE_STAGE_TYPE := GET_ID; - signal encode_stage, encode_stage_next : ENCODE_STAGE_TYPE := WRITE_ID; - signal return_stage, return_stage_next : DECODE_STAGE_TYPE := GET_ID; + signal stage, stage_next : STAGE_TYPE; + signal cnt, cnt_next : natural range 0 to 5; + signal endian_flag, endian_flag_next : std_logic; + signal last_word_in_latch, last_word_in_latch_next : std_logic; + signal decode_error_latch, decode_error_latch_next : std_logic; + signal align_offset, align_offset_next : unsigned(MAX_ALIGN_OFFSET_WIDTH-1 downto 0); + signal target_align, target_align_next : ALIGN_TYPE; + signal data_in_latch, data_in_latch_next : std_logic_vector(WORD_WIDTH-1 downto 0); + signal data_out_latch, data_out_latch_next : std_logic_vector(WORD_WIDTH-1 downto 0); + signal optional, optional_next : std_logic; + signal abort_mem : std_logic; + signal opcode_latch, opcode_latch_next : KEY_HOLDER_OPCODE_TYPE; + signal cnt_2, cnt_2_next : natural range 0 to (WORD_WIDTH/BYTE_WIDTH)-1; + signal align_op, align_op_next : std_logic; + signal finalize_payload, finalize_payload_next : std_logic; + signal ready_in_sig : std_logic; + signal start_kh, ack_kh, done_kh : std_logic; + signal data_in_kh : std_logic_vector(BYTE_WIDTH-1 downto 0); + signal valid_in_kh, ready_in_kh, last_word_in_kh : std_logic; + signal key_hash_kh : std_logic_vector(KEY_HASH_WIDTH-1 downto 0); + signal key_hash, key_hash_next : KEY_HASH_TYPE; + signal decode_stage, decode_stage_next : DECODE_STAGE_TYPE; + signal encode_stage, encode_stage_next : ENCODE_STAGE_TYPE; + signal return_stage, return_stage_next : DECODE_STAGE_TYPE; -- ###GENERATED START### - signal id_latch, id_latch_next : std_logic_vector(CDR_LONG_WIDTH-1 downto 0) := (others => '0'); + signal id_latch, id_latch_next : std_logic_vector(CDR_LONG_WIDTH-1 downto 0); -- ###GENERATED END### --*****ALIAS DECLARATION***** @@ -91,7 +91,7 @@ begin ready_in <= ready_in_sig; main_prc : process (all) - variable tmp_length : unsigned(WORD_WIDTH-1 downto 0) := (others => '0'); + variable tmp_length : unsigned(WORD_WIDTH-1 downto 0); begin -- DEFAULT stage_next <= stage; diff --git a/src/Tests/Type1_reader_wrapper.vhd b/src/Tests/Type1_reader_wrapper.vhd index 07e487f..cfea6d1 100644 --- a/src/Tests/Type1_reader_wrapper.vhd +++ b/src/Tests/Type1_reader_wrapper.vhd @@ -96,24 +96,24 @@ architecture arch of Type1_reader_wrapper is -- ###GENERATED END### -- *MAIN PROCESS* - signal stage, stage_next : STAGE_TYPE := IDLE; - signal cnt, cnt_next : natural range 0 to 5 := 0; - signal endian_flag, endian_flag_next : std_logic := '0'; - signal last_word_in_latch, last_word_in_latch_next : std_logic := '0'; - signal decode_error_latch, decode_error_latch_next : std_logic := '0'; - signal align_offset, align_offset_next : unsigned(MAX_ALIGN_OFFSET_WIDTH-1 downto 0) := (others => '0'); - signal align_op, align_op_next : std_logic := '0'; - signal target_align, target_align_next : ALIGN_TYPE := ALIGN_1; - signal data_in_latch, data_in_latch_next : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); - signal optional, optional_next : std_logic := '0'; - signal abort_mem : std_logic := '0'; - signal ready_in_dds_sig : std_logic := '0'; - signal valid_latch, valid_latch_next : std_logic := '0'; - signal decode_stage, decode_stage_next : DECODE_STAGE_TYPE := GET_ID; - signal return_stage, return_stage_next : DECODE_STAGE_TYPE := GET_ID; + signal stage, stage_next : STAGE_TYPE; + signal cnt, cnt_next : natural range 0 to 5; + signal endian_flag, endian_flag_next : std_logic; + signal last_word_in_latch, last_word_in_latch_next : std_logic; + signal decode_error_latch, decode_error_latch_next : std_logic; + signal align_offset, align_offset_next : unsigned(MAX_ALIGN_OFFSET_WIDTH-1 downto 0); + signal align_op, align_op_next : std_logic; + signal target_align, target_align_next : ALIGN_TYPE; + signal data_in_latch, data_in_latch_next : std_logic_vector(WORD_WIDTH-1 downto 0); + signal optional, optional_next : std_logic; + signal abort_mem : std_logic; + signal ready_in_dds_sig : std_logic; + signal valid_latch, valid_latch_next : std_logic; + signal decode_stage, decode_stage_next : DECODE_STAGE_TYPE; + signal return_stage, return_stage_next : DECODE_STAGE_TYPE; -- ###GENERATED START### - signal id_latch, id_latch_next : std_logic_vector(CDR_LONG_WIDTH-1 downto 0) := (others => '0'); - signal a_latch, a_latch_next : std_logic_vector(CDR_LONG_WIDTH-1 downto 0) := (others => '0'); + signal id_latch, id_latch_next : std_logic_vector(CDR_LONG_WIDTH-1 downto 0); + signal a_latch, a_latch_next : std_logic_vector(CDR_LONG_WIDTH-1 downto 0); -- ###GENERATED END### --*****ALIAS DECLARATION***** @@ -164,7 +164,7 @@ begin -- ###GENERATED END### main_prc : process (all) - variable tmp_length : unsigned(WORD_WIDTH-1 downto 0) := (others => '0'); + variable tmp_length : unsigned(WORD_WIDTH-1 downto 0); begin -- DEFAULT stage_next <= stage; diff --git a/src/Tests/Type1_writer_wrapper.vhd b/src/Tests/Type1_writer_wrapper.vhd index 96a3656..f6abc0e 100644 --- a/src/Tests/Type1_writer_wrapper.vhd +++ b/src/Tests/Type1_writer_wrapper.vhd @@ -70,15 +70,15 @@ architecture arch of Type1_writer_wrapper is -- ###GENERATED END### -- *MAIN PROCESS* - signal stage, stage_next : STAGE_TYPE := IDLE; - signal cnt, cnt_next : natural range 0 to 5 := 0; - signal align_offset, align_offset_next : unsigned(MAX_ALIGN_OFFSET_WIDTH-1 downto 0) := (others => '0'); - signal align_op, align_op_next : std_logic := '0'; - signal target_align, target_align_next : ALIGN_TYPE := ALIGN_1; - signal data_out_latch, data_out_latch_next : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); - signal abort_mem : std_logic := '0'; - signal finalize_payload, finalize_payload_next : std_logic := '0'; - signal encode_stage, encode_stage_next : ENCODE_STAGE_TYPE := WRITE_ID; + signal stage, stage_next : STAGE_TYPE; + signal cnt, cnt_next : natural range 0 to 5; + signal align_offset, align_offset_next : unsigned(MAX_ALIGN_OFFSET_WIDTH-1 downto 0); + signal align_op, align_op_next : std_logic; + signal target_align, target_align_next : ALIGN_TYPE; + signal data_out_latch, data_out_latch_next : std_logic_vector(WORD_WIDTH-1 downto 0); + signal abort_mem : std_logic; + signal finalize_payload, finalize_payload_next : std_logic; + signal encode_stage, encode_stage_next : ENCODE_STAGE_TYPE; begin @@ -99,7 +99,6 @@ begin status_user <= status_dds; main_prc : process (all) - variable tmp_length : unsigned(WORD_WIDTH-1 downto 0) := (others => '0'); begin -- DEFAULT stage_next <= stage; diff --git a/src/Tests/Type2_key_holder.vhd b/src/Tests/Type2_key_holder.vhd index b0a781d..ea9c008 100644 --- a/src/Tests/Type2_key_holder.vhd +++ b/src/Tests/Type2_key_holder.vhd @@ -38,40 +38,40 @@ architecture TYPE2 of key_holder is -- ###GENERATED END### -- *MAIN PROCESS* - signal stage, stage_next : STAGE_TYPE := IDLE; - signal cnt, cnt_next : natural range 0 to 5 := 0; - signal endian_flag, endian_flag_next : std_logic := '0'; - signal last_word_in_latch, last_word_in_latch_next : std_logic := '0'; - signal decode_error_latch, decode_error_latch_next : std_logic := '0'; - signal align_offset, align_offset_next : unsigned(MAX_ALIGN_OFFSET_WIDTH-1 downto 0) := (others => '0'); - signal target_align, target_align_next : ALIGN_TYPE := ALIGN_1; - signal data_in_latch, data_in_latch_next : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); - signal data_out_latch, data_out_latch_next : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); - signal optional, optional_next : std_logic := '0'; - signal abort_mem : std_logic := '0'; - signal opcode_latch, opcode_latch_next : KEY_HOLDER_OPCODE_TYPE := NOP; - signal cnt_2, cnt_2_next : natural range 0 to (WORD_WIDTH/BYTE_WIDTH)-1 := 0; - signal align_op, align_op_next : std_logic := '0'; - signal finalize_payload, finalize_payload_next : std_logic := '0'; - signal ready_in_sig : std_logic := '0'; - signal start_kh, ack_kh, done_kh : std_logic := '0'; - signal data_in_kh : std_logic_vector(BYTE_WIDTH-1 downto 0) := (others => '0'); - signal valid_in_kh, ready_in_kh, last_word_in_kh : std_logic := '0'; - signal key_hash_kh : std_logic_vector(KEY_HASH_WIDTH-1 downto 0) := (others => '0'); - signal key_hash, key_hash_next : KEY_HASH_TYPE := HANDLE_NIL; - signal decode_stage, decode_stage_next : DECODE_STAGE_TYPE := GET_ID; - signal encode_stage, encode_stage_next : ENCODE_STAGE_TYPE := WRITE_ID; - signal return_stage, return_stage_next : DECODE_STAGE_TYPE := GET_ID; + signal stage, stage_next : STAGE_TYPE; + signal cnt, cnt_next : natural range 0 to 5; + signal endian_flag, endian_flag_next : std_logic; + signal last_word_in_latch, last_word_in_latch_next : std_logic; + signal decode_error_latch, decode_error_latch_next : std_logic; + signal align_offset, align_offset_next : unsigned(MAX_ALIGN_OFFSET_WIDTH-1 downto 0); + signal target_align, target_align_next : ALIGN_TYPE; + signal data_in_latch, data_in_latch_next : std_logic_vector(WORD_WIDTH-1 downto 0); + signal data_out_latch, data_out_latch_next : std_logic_vector(WORD_WIDTH-1 downto 0); + signal optional, optional_next : std_logic; + signal abort_mem : std_logic; + signal opcode_latch, opcode_latch_next : KEY_HOLDER_OPCODE_TYPE; + signal cnt_2, cnt_2_next : natural range 0 to (WORD_WIDTH/BYTE_WIDTH)-1; + signal align_op, align_op_next : std_logic; + signal finalize_payload, finalize_payload_next : std_logic; + signal ready_in_sig : std_logic; + signal start_kh, ack_kh, done_kh : std_logic; + signal data_in_kh : std_logic_vector(BYTE_WIDTH-1 downto 0); + signal valid_in_kh, ready_in_kh, last_word_in_kh : std_logic; + signal key_hash_kh : std_logic_vector(KEY_HASH_WIDTH-1 downto 0); + signal key_hash, key_hash_next : KEY_HASH_TYPE; + signal decode_stage, decode_stage_next : DECODE_STAGE_TYPE; + signal encode_stage, encode_stage_next : ENCODE_STAGE_TYPE; + signal return_stage, return_stage_next : DECODE_STAGE_TYPE; -- ###GENERATED START### - signal id_latch, id_latch_next : std_logic_vector(CDR_LONG_WIDTH-1 downto 0) := (others => '0'); - signal TestSequence_cnt, TestSequence_cnt_next : natural range 0 to TESTSEQUENCE_MAX_DEPTH-1 := 0; - signal TestSequence_len_latch, TestSequence_len_latch_next : unsigned(TESTSEQUENCE_ADDR_WIDTH-1 downto 0) := (others => '0'); - signal TestSequence_addr_latch, TestSequence_addr_latch_next : std_logic_vector(TESTSEQUENCE_ADDR_WIDTH-1 downto 0) := (others => '0'); - signal TestSequence_TestArray_cnt, TestSequence_TestArray_cnt_next : natural range 0 to TESTSEQUENCE_TESTARRAY_MAX_DEPTH-1 := 0; + signal id_latch, id_latch_next : std_logic_vector(CDR_LONG_WIDTH-1 downto 0); + signal TestSequence_cnt, TestSequence_cnt_next : natural range 0 to TESTSEQUENCE_MAX_DEPTH-1; + signal TestSequence_len_latch, TestSequence_len_latch_next : unsigned(TESTSEQUENCE_ADDR_WIDTH-1 downto 0); + signal TestSequence_addr_latch, TestSequence_addr_latch_next : std_logic_vector(TESTSEQUENCE_ADDR_WIDTH-1 downto 0); + signal TestSequence_TestArray_cnt, TestSequence_TestArray_cnt_next : natural range 0 to TESTSEQUENCE_TESTARRAY_MAX_DEPTH-1; -- TestSequence_TestArray_mem SIGNALS - signal TestSequence_TestArray_mem_addr : TESTSEQUENCE_TESTARRAY_ADDR_TYPE := (others => (others => '0')); - signal TestSequence_TestArray_mem_read, TestSequence_TestArray_mem_ready_in, TestSequence_TestArray_mem_ready_out, TestSequence_TestArray_mem_valid_in, TestSequence_TestArray_mem_valid_out : std_logic_vector(0 to TESTSEQUENCE_TESTARRAY_MAX_DEPTH-1) := (others => '0'); - signal TestSequence_TestArray_mem_data_in, TestSequence_TestArray_mem_data_out : TESTSEQUENCE_TESTARRAY_DATA_TYPE := (others => (others => '0')); + signal TestSequence_TestArray_mem_addr : TESTSEQUENCE_TESTARRAY_ADDR_TYPE; + signal TestSequence_TestArray_mem_read, TestSequence_TestArray_mem_ready_in, TestSequence_TestArray_mem_ready_out, TestSequence_TestArray_mem_valid_in, TestSequence_TestArray_mem_valid_out : std_logic_vector(0 to TESTSEQUENCE_TESTARRAY_MAX_DEPTH-1); + signal TestSequence_TestArray_mem_data_in, TestSequence_TestArray_mem_data_out : TESTSEQUENCE_TESTARRAY_DATA_TYPE; -- ###GENERATED END### --*****ALIAS DECLARATION***** @@ -126,7 +126,7 @@ begin ready_in <= ready_in_sig; main_prc : process (all) - variable tmp_length : unsigned(WORD_WIDTH-1 downto 0) := (others => '0'); + variable tmp_length : unsigned(WORD_WIDTH-1 downto 0); begin -- DEFAULT stage_next <= stage; diff --git a/src/Tests/Type2_reader_wrapper.vhd b/src/Tests/Type2_reader_wrapper.vhd index a3d2b23..37aad59 100644 --- a/src/Tests/Type2_reader_wrapper.vhd +++ b/src/Tests/Type2_reader_wrapper.vhd @@ -134,71 +134,71 @@ architecture arch of Type2_reader_wrapper is -- ###GENERATED END### -- *MAIN PROCESS* - signal stage, stage_next : STAGE_TYPE := IDLE; - signal cnt, cnt_next : natural range 0 to 5 := 0; - signal endian_flag, endian_flag_next : std_logic := '0'; - signal last_word_in_latch, last_word_in_latch_next : std_logic := '0'; - signal decode_error_latch, decode_error_latch_next : std_logic := '0'; - signal align_offset, align_offset_next : unsigned(MAX_ALIGN_OFFSET_WIDTH-1 downto 0) := (others => '0'); - signal align_op, align_op_next : std_logic := '0'; - signal target_align, target_align_next : ALIGN_TYPE := ALIGN_1; - signal data_in_latch, data_in_latch_next : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); - signal optional, optional_next : std_logic := '0'; - signal abort_mem : std_logic := '0'; - signal ready_in_dds_sig : std_logic := '0'; + signal stage, stage_next : STAGE_TYPE; + signal cnt, cnt_next : natural range 0 to 5; + signal endian_flag, endian_flag_next : std_logic; + signal last_word_in_latch, last_word_in_latch_next : std_logic; + signal decode_error_latch, decode_error_latch_next : std_logic; + signal align_offset, align_offset_next : unsigned(MAX_ALIGN_OFFSET_WIDTH-1 downto 0); + signal align_op, align_op_next : std_logic; + signal target_align, target_align_next : ALIGN_TYPE; + signal data_in_latch, data_in_latch_next : std_logic_vector(WORD_WIDTH-1 downto 0); + signal optional, optional_next : std_logic; + signal abort_mem : std_logic; + signal ready_in_dds_sig : std_logic; -- ###GENERATED START### - signal decode_stage, decode_stage_next : DECODE_STAGE_TYPE := GET_ID; - signal valid_latch, valid_latch_next : std_logic := '0'; - signal return_stage, return_stage_next : DECODE_STAGE_TYPE := GET_ID; - signal dw_latch, dw_latch_next : std_logic_vector(CDR_LONG_LONG_WIDTH-1 downto 0) := (others => '0'); - signal qw_latch, qw_latch_next : std_logic_vector(CDR_LONG_DOUBLE_WIDTH-1 downto 0) := (others => '0'); - signal id_latch, id_latch_next : std_logic_vector(CDR_LONG_WIDTH-1 downto 0) := (others => '0'); - signal TestSequence_cnt, TestSequence_cnt_next : natural range 0 to TESTSEQUENCE_MAX_DEPTH-1 := 0; - signal TestSequence_len_latch, TestSequence_len_latch_next : unsigned(TESTSEQUENCE_ADDR_WIDTH-1 downto 0) := (others => '0'); - signal TestSequence_addr_latch, TestSequence_addr_latch_next : std_logic_vector(TESTSEQUENCE_ADDR_WIDTH-1 downto 0) := (others => '0'); - signal TestSequence_TestArray_cnt, TestSequence_TestArray_cnt_next : natural range 0 to TESTSEQUENCE_TESTARRAY_MAX_DEPTH-1 := 0; - signal TestMap_cnt, TestMap_cnt_next : natural range 0 to TESTMAP_MAX_DEPTH-1 := 0; - signal TestMap_len_latch, TestMap_len_latch_next : unsigned(TESTMAP_ADDR_WIDTH-1 downto 0) := (others => '0'); - signal TestString_cnt, TestString_cnt_next : natural range 0 to TESTSTRING_MAX_DEPTH-1 := 0; - signal TestString_len_latch, TestString_len_latch_next : unsigned(TESTSTRING_ADDR_WIDTH-1 downto 0) := (others => '0'); - signal TestEnum_latch, TestEnum_latch_next : std_logic_vector(TESTENUM_WIDTH-1 downto 0) := (others => '0'); - signal TestUnion_opt_latch, TestUnion_opt_latch_next : std_logic := '0'; - signal TestUnion_d_latch, TestUnion_d_latch_next : std_logic_vector(CDR_CHAR_WIDTH-1 downto 0) := (others => '0'); - signal TestUnion_LongU_latch, TestUnion_LongU_latch_next : std_logic_vector(CDR_LONG_WIDTH-1 downto 0) := (others => '0'); - signal TestUnion_OctetU_latch, TestUnion_OctetU_latch_next : std_logic_vector(CDR_OCTET_WIDTH-1 downto 0) := (others => '0'); - signal TestBitmask_latch, TestBitmask_latch_next : std_logic_vector(TESTBITMASK_WIDTH-1 downto 0) := (others => '0'); + signal decode_stage, decode_stage_next : DECODE_STAGE_TYPE; + signal valid_latch, valid_latch_next : std_logic; + signal return_stage, return_stage_next : DECODE_STAGE_TYPE; + signal dw_latch, dw_latch_next : std_logic_vector(CDR_LONG_LONG_WIDTH-1 downto 0); + signal qw_latch, qw_latch_next : std_logic_vector(CDR_LONG_DOUBLE_WIDTH-1 downto 0); + signal id_latch, id_latch_next : std_logic_vector(CDR_LONG_WIDTH-1 downto 0); + signal TestSequence_cnt, TestSequence_cnt_next : natural range 0 to TESTSEQUENCE_MAX_DEPTH-1; + signal TestSequence_len_latch, TestSequence_len_latch_next : unsigned(TESTSEQUENCE_ADDR_WIDTH-1 downto 0); + signal TestSequence_addr_latch, TestSequence_addr_latch_next : std_logic_vector(TESTSEQUENCE_ADDR_WIDTH-1 downto 0); + signal TestSequence_TestArray_cnt, TestSequence_TestArray_cnt_next : natural range 0 to TESTSEQUENCE_TESTARRAY_MAX_DEPTH-1; + signal TestMap_cnt, TestMap_cnt_next : natural range 0 to TESTMAP_MAX_DEPTH-1; + signal TestMap_len_latch, TestMap_len_latch_next : unsigned(TESTMAP_ADDR_WIDTH-1 downto 0); + signal TestString_cnt, TestString_cnt_next : natural range 0 to TESTSTRING_MAX_DEPTH-1; + signal TestString_len_latch, TestString_len_latch_next : unsigned(TESTSTRING_ADDR_WIDTH-1 downto 0); + signal TestEnum_latch, TestEnum_latch_next : std_logic_vector(TESTENUM_WIDTH-1 downto 0); + signal TestUnion_opt_latch, TestUnion_opt_latch_next : std_logic; + signal TestUnion_d_latch, TestUnion_d_latch_next : std_logic_vector(CDR_CHAR_WIDTH-1 downto 0); + signal TestUnion_LongU_latch, TestUnion_LongU_latch_next : std_logic_vector(CDR_LONG_WIDTH-1 downto 0); + signal TestUnion_OctetU_latch, TestUnion_OctetU_latch_next : std_logic_vector(CDR_OCTET_WIDTH-1 downto 0); + signal TestBitmask_latch, TestBitmask_latch_next : std_logic_vector(TESTBITMASK_WIDTH-1 downto 0); -- TestSequence_TestChar_mem SIGNALS - signal TestSequence_TestChar_mem_addr : std_logic_vector(TESTSEQUENCE_ADDR_WIDTH-1 downto 0) := (others => '0'); - signal TestSequence_TestChar_mem_read, TestSequence_TestChar_mem_ready_in, TestSequence_TestChar_mem_ready_out, TestSequence_TestChar_mem_valid_in, TestSequence_TestChar_mem_valid_out : std_logic := '0'; - signal TestSequence_TestChar_mem_data_in, TestSequence_TestChar_mem_data_out : std_logic_vector(CDR_CHAR_WIDTH-1 downto 0) := (others => '0'); + signal TestSequence_TestChar_mem_addr : std_logic_vector(TESTSEQUENCE_ADDR_WIDTH-1 downto 0); + signal TestSequence_TestChar_mem_read, TestSequence_TestChar_mem_ready_in, TestSequence_TestChar_mem_ready_out, TestSequence_TestChar_mem_valid_in, TestSequence_TestChar_mem_valid_out : std_logic; + signal TestSequence_TestChar_mem_data_in, TestSequence_TestChar_mem_data_out : std_logic_vector(CDR_CHAR_WIDTH-1 downto 0); -- TestSequence_TestWChar_mem SIGNALS - signal TestSequence_TestWChar_mem_addr : std_logic_vector(TESTSEQUENCE_ADDR_WIDTH-1 downto 0) := (others => '0'); - signal TestSequence_TestWChar_mem_read, TestSequence_TestWChar_mem_ready_in, TestSequence_TestWChar_mem_ready_out, TestSequence_TestWChar_mem_valid_in, TestSequence_TestWChar_mem_valid_out : std_logic := '0'; - signal TestSequence_TestWChar_mem_data_in, TestSequence_TestWChar_mem_data_out : std_logic_vector(CDR_WCHAR_WIDTH-1 downto 0) := (others => '0'); + signal TestSequence_TestWChar_mem_addr : std_logic_vector(TESTSEQUENCE_ADDR_WIDTH-1 downto 0); + signal TestSequence_TestWChar_mem_read, TestSequence_TestWChar_mem_ready_in, TestSequence_TestWChar_mem_ready_out, TestSequence_TestWChar_mem_valid_in, TestSequence_TestWChar_mem_valid_out : std_logic; + signal TestSequence_TestWChar_mem_data_in, TestSequence_TestWChar_mem_data_out : std_logic_vector(CDR_WCHAR_WIDTH-1 downto 0); -- TestSequence_TestLongLong_mem SIGNALS - signal TestSequence_TestLongLong_mem_addr : std_logic_vector(TESTSEQUENCE_ADDR_WIDTH-1 downto 0) := (others => '0'); - signal TestSequence_TestLongLong_mem_read, TestSequence_TestLongLong_mem_ready_in, TestSequence_TestLongLong_mem_ready_out, TestSequence_TestLongLong_mem_valid_in, TestSequence_TestLongLong_mem_valid_out : std_logic := '0'; - signal TestSequence_TestLongLong_mem_data_in, TestSequence_TestLongLong_mem_data_out : std_logic_vector(CDR_LONG_LONG_WIDTH-1 downto 0) := (others => '0'); + signal TestSequence_TestLongLong_mem_addr : std_logic_vector(TESTSEQUENCE_ADDR_WIDTH-1 downto 0); + signal TestSequence_TestLongLong_mem_read, TestSequence_TestLongLong_mem_ready_in, TestSequence_TestLongLong_mem_ready_out, TestSequence_TestLongLong_mem_valid_in, TestSequence_TestLongLong_mem_valid_out : std_logic; + signal TestSequence_TestLongLong_mem_data_in, TestSequence_TestLongLong_mem_data_out : std_logic_vector(CDR_LONG_LONG_WIDTH-1 downto 0); -- TestSequence_TestLongDouble_mem SIGNALS - signal TestSequence_TestLongDouble_mem_addr : std_logic_vector(TESTSEQUENCE_ADDR_WIDTH-1 downto 0) := (others => '0'); - signal TestSequence_TestLongDouble_mem_read, TestSequence_TestLongDouble_mem_ready_in, TestSequence_TestLongDouble_mem_ready_out, TestSequence_TestLongDouble_mem_valid_in, TestSequence_TestLongDouble_mem_valid_out : std_logic := '0'; - signal TestSequence_TestLongDouble_mem_data_in, TestSequence_TestLongDouble_mem_data_out : std_logic_vector(CDR_LONG_DOUBLE_WIDTH+1-1 downto 0) := (others => '0'); + signal TestSequence_TestLongDouble_mem_addr : std_logic_vector(TESTSEQUENCE_ADDR_WIDTH-1 downto 0); + signal TestSequence_TestLongDouble_mem_read, TestSequence_TestLongDouble_mem_ready_in, TestSequence_TestLongDouble_mem_ready_out, TestSequence_TestLongDouble_mem_valid_in, TestSequence_TestLongDouble_mem_valid_out : std_logic; + signal TestSequence_TestLongDouble_mem_data_in, TestSequence_TestLongDouble_mem_data_out : std_logic_vector(CDR_LONG_DOUBLE_WIDTH+1-1 downto 0); -- TestSequence_TestArray_mem SIGNALS - signal TestSequence_TestArray_mem_addr : TESTSEQUENCE_TESTARRAY_ADDR_TYPE := (others => (others => '0')); - signal TestSequence_TestArray_mem_read, TestSequence_TestArray_mem_ready_in, TestSequence_TestArray_mem_ready_out, TestSequence_TestArray_mem_valid_in, TestSequence_TestArray_mem_valid_out : std_logic_vector(0 to TESTSEQUENCE_TESTARRAY_MAX_DEPTH-1) := (others => '0'); - signal TestSequence_TestArray_mem_data_in, TestSequence_TestArray_mem_data_out : TESTSEQUENCE_TESTARRAY_DATA_TYPE := (others => (others => '0')); + signal TestSequence_TestArray_mem_addr : TESTSEQUENCE_TESTARRAY_ADDR_TYPE; + signal TestSequence_TestArray_mem_read, TestSequence_TestArray_mem_ready_in, TestSequence_TestArray_mem_ready_out, TestSequence_TestArray_mem_valid_in, TestSequence_TestArray_mem_valid_out : std_logic_vector(0 to TESTSEQUENCE_TESTARRAY_MAX_DEPTH-1); + signal TestSequence_TestArray_mem_data_in, TestSequence_TestArray_mem_data_out : TESTSEQUENCE_TESTARRAY_DATA_TYPE; -- TestMap_key_mem SIGNALS - signal TestMap_key_mem_addr : std_logic_vector(TESTMAP_ADDR_WIDTH-1 downto 0) := (others => '0'); - signal TestMap_key_mem_read, TestMap_key_mem_ready_in, TestMap_key_mem_ready_out, TestMap_key_mem_valid_in, TestMap_key_mem_valid_out : std_logic := '0'; - signal TestMap_key_mem_data_in, TestMap_key_mem_data_out : std_logic_vector(CDR_OCTET_WIDTH-1 downto 0) := (others => '0'); + signal TestMap_key_mem_addr : std_logic_vector(TESTMAP_ADDR_WIDTH-1 downto 0); + signal TestMap_key_mem_read, TestMap_key_mem_ready_in, TestMap_key_mem_ready_out, TestMap_key_mem_valid_in, TestMap_key_mem_valid_out : std_logic; + signal TestMap_key_mem_data_in, TestMap_key_mem_data_out : std_logic_vector(CDR_OCTET_WIDTH-1 downto 0); -- TestMap_value_mem SIGNALS - signal TestMap_value_mem_addr : std_logic_vector(TESTMAP_ADDR_WIDTH-1 downto 0) := (others => '0'); - signal TestMap_value_mem_read, TestMap_value_mem_ready_in, TestMap_value_mem_ready_out, TestMap_value_mem_valid_in, TestMap_value_mem_valid_out : std_logic := '0'; - signal TestMap_value_mem_data_in, TestMap_value_mem_data_out : std_logic_vector(CDR_SHORT_WIDTH-1 downto 0) := (others => '0'); + signal TestMap_value_mem_addr : std_logic_vector(TESTMAP_ADDR_WIDTH-1 downto 0); + signal TestMap_value_mem_read, TestMap_value_mem_ready_in, TestMap_value_mem_ready_out, TestMap_value_mem_valid_in, TestMap_value_mem_valid_out : std_logic; + signal TestMap_value_mem_data_in, TestMap_value_mem_data_out : std_logic_vector(CDR_SHORT_WIDTH-1 downto 0); -- TestString_mem SIGNALS - signal TestString_mem_addr : std_logic_vector(TESTSTRING_ADDR_WIDTH-1 downto 0) := (others => '0'); - signal TestString_mem_read, TestString_mem_ready_in, TestString_mem_ready_out, TestString_mem_valid_in, TestString_mem_valid_out : std_logic := '0'; - signal TestString_mem_data_in, TestString_mem_data_out : std_logic_vector(CDR_CHAR_WIDTH-1 downto 0) := (others => '0'); + signal TestString_mem_addr : std_logic_vector(TESTSTRING_ADDR_WIDTH-1 downto 0); + signal TestString_mem_read, TestString_mem_ready_in, TestString_mem_ready_out, TestString_mem_valid_in, TestString_mem_valid_out : std_logic; + signal TestString_mem_data_in, TestString_mem_data_out : std_logic_vector(CDR_CHAR_WIDTH-1 downto 0); -- ###GENERATED END### --*****ALIAS DECLARATION***** @@ -437,7 +437,7 @@ begin -- ###GENERATED END### main_prc : process (all) - variable tmp_length : unsigned(WORD_WIDTH-1 downto 0) := (others => '0'); + variable tmp_length : unsigned(WORD_WIDTH-1 downto 0); begin -- DEFAULT stage_next <= stage; diff --git a/src/Tests/Type2_writer_wrapper.vhd b/src/Tests/Type2_writer_wrapper.vhd index e808e63..a002539 100644 --- a/src/Tests/Type2_writer_wrapper.vhd +++ b/src/Tests/Type2_writer_wrapper.vhd @@ -119,53 +119,53 @@ architecture arch of Type2_writer_wrapper is -- ###GENERATED END### -- *MAIN PROCESS* - signal stage, stage_next : STAGE_TYPE := IDLE; - signal cnt, cnt_next : natural range 0 to 5 := 0; - signal align_offset, align_offset_next : unsigned(MAX_ALIGN_OFFSET_WIDTH-1 downto 0) := (others => '0'); - signal align_op, align_op_next : std_logic := '0'; - signal target_align, target_align_next : ALIGN_TYPE := ALIGN_1; - signal data_out_latch, data_out_latch_next : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); - signal abort_mem : std_logic := '0'; - signal finalize_payload, finalize_payload_next : std_logic := '0'; + signal stage, stage_next : STAGE_TYPE; + signal cnt, cnt_next : natural range 0 to 5; + signal align_offset, align_offset_next : unsigned(MAX_ALIGN_OFFSET_WIDTH-1 downto 0); + signal align_op, align_op_next : std_logic; + signal target_align, target_align_next : ALIGN_TYPE; + signal data_out_latch, data_out_latch_next : std_logic_vector(WORD_WIDTH-1 downto 0); + signal abort_mem : std_logic; + signal finalize_payload, finalize_payload_next : std_logic; -- ###GENERATED START### - signal encode_stage, encode_stage_next : ENCODE_STAGE_TYPE := WRITE_ID; - signal TestSequence_cnt, TestSequence_cnt_next : natural range 0 to TESTSEQUENCE_MAX_DEPTH-1 := 0; - signal TestSequence_addr_latch, TestSequence_addr_latch_next : std_logic_vector(TESTSEQUENCE_ADDR_WIDTH-1 downto 0) := (others => '0'); - signal TestSequence_TestArray_cnt, TestSequence_TestArray_cnt_next : natural range 0 to TESTSEQUENCE_TESTARRAY_MAX_DEPTH-1 := 0; - signal TestMap_cnt, TestMap_cnt_next : natural range 0 to TESTMAP_MAX_DEPTH-1 := 0; - signal TestString_cnt, TestString_cnt_next : natural range 0 to TESTSTRING_MAX_DEPTH-1 := 0; + signal encode_stage, encode_stage_next : ENCODE_STAGE_TYPE; + signal TestSequence_cnt, TestSequence_cnt_next : natural range 0 to TESTSEQUENCE_MAX_DEPTH-1; + signal TestSequence_addr_latch, TestSequence_addr_latch_next : std_logic_vector(TESTSEQUENCE_ADDR_WIDTH-1 downto 0); + signal TestSequence_TestArray_cnt, TestSequence_TestArray_cnt_next : natural range 0 to TESTSEQUENCE_TESTARRAY_MAX_DEPTH-1; + signal TestMap_cnt, TestMap_cnt_next : natural range 0 to TESTMAP_MAX_DEPTH-1; + signal TestString_cnt, TestString_cnt_next : natural range 0 to TESTSTRING_MAX_DEPTH-1; -- TestSequence_TestChar_mem SIGNALS - signal TestSequence_TestChar_mem_addr : std_logic_vector(TESTSEQUENCE_ADDR_WIDTH-1 downto 0) := (others => '0'); - signal TestSequence_TestChar_mem_read, TestSequence_TestChar_mem_ready_in, TestSequence_TestChar_mem_ready_out, TestSequence_TestChar_mem_valid_in, TestSequence_TestChar_mem_valid_out : std_logic := '0'; - signal TestSequence_TestChar_mem_data_in, TestSequence_TestChar_mem_data_out : std_logic_vector(CDR_CHAR_WIDTH-1 downto 0) := (others => '0'); + signal TestSequence_TestChar_mem_addr : std_logic_vector(TESTSEQUENCE_ADDR_WIDTH-1 downto 0); + signal TestSequence_TestChar_mem_read, TestSequence_TestChar_mem_ready_in, TestSequence_TestChar_mem_ready_out, TestSequence_TestChar_mem_valid_in, TestSequence_TestChar_mem_valid_out : std_logic; + signal TestSequence_TestChar_mem_data_in, TestSequence_TestChar_mem_data_out : std_logic_vector(CDR_CHAR_WIDTH-1 downto 0); -- TestSequence_TestWChar_mem SIGNALS - signal TestSequence_TestWChar_mem_addr : std_logic_vector(TESTSEQUENCE_ADDR_WIDTH-1 downto 0) := (others => '0'); - signal TestSequence_TestWChar_mem_read, TestSequence_TestWChar_mem_ready_in, TestSequence_TestWChar_mem_ready_out, TestSequence_TestWChar_mem_valid_in, TestSequence_TestWChar_mem_valid_out : std_logic := '0'; - signal TestSequence_TestWChar_mem_data_in, TestSequence_TestWChar_mem_data_out : std_logic_vector(CDR_WCHAR_WIDTH-1 downto 0) := (others => '0'); + signal TestSequence_TestWChar_mem_addr : std_logic_vector(TESTSEQUENCE_ADDR_WIDTH-1 downto 0); + signal TestSequence_TestWChar_mem_read, TestSequence_TestWChar_mem_ready_in, TestSequence_TestWChar_mem_ready_out, TestSequence_TestWChar_mem_valid_in, TestSequence_TestWChar_mem_valid_out : std_logic; + signal TestSequence_TestWChar_mem_data_in, TestSequence_TestWChar_mem_data_out : std_logic_vector(CDR_WCHAR_WIDTH-1 downto 0); -- TestSequence_TestLongLong_mem SIGNALS - signal TestSequence_TestLongLong_mem_addr : std_logic_vector(TESTSEQUENCE_ADDR_WIDTH-1 downto 0) := (others => '0'); - signal TestSequence_TestLongLong_mem_read, TestSequence_TestLongLong_mem_ready_in, TestSequence_TestLongLong_mem_ready_out, TestSequence_TestLongLong_mem_valid_in, TestSequence_TestLongLong_mem_valid_out : std_logic := '0'; - signal TestSequence_TestLongLong_mem_data_in, TestSequence_TestLongLong_mem_data_out : std_logic_vector(CDR_LONG_LONG_WIDTH-1 downto 0) := (others => '0'); + signal TestSequence_TestLongLong_mem_addr : std_logic_vector(TESTSEQUENCE_ADDR_WIDTH-1 downto 0); + signal TestSequence_TestLongLong_mem_read, TestSequence_TestLongLong_mem_ready_in, TestSequence_TestLongLong_mem_ready_out, TestSequence_TestLongLong_mem_valid_in, TestSequence_TestLongLong_mem_valid_out : std_logic; + signal TestSequence_TestLongLong_mem_data_in, TestSequence_TestLongLong_mem_data_out : std_logic_vector(CDR_LONG_LONG_WIDTH-1 downto 0); -- TestSequence_TestLongDouble_mem SIGNALS - signal TestSequence_TestLongDouble_mem_addr : std_logic_vector(TESTSEQUENCE_ADDR_WIDTH-1 downto 0) := (others => '0'); - signal TestSequence_TestLongDouble_mem_read, TestSequence_TestLongDouble_mem_ready_in, TestSequence_TestLongDouble_mem_ready_out, TestSequence_TestLongDouble_mem_valid_in, TestSequence_TestLongDouble_mem_valid_out : std_logic := '0'; - signal TestSequence_TestLongDouble_mem_data_in, TestSequence_TestLongDouble_mem_data_out : std_logic_vector(CDR_LONG_DOUBLE_WIDTH+1-1 downto 0) := (others => '0'); + signal TestSequence_TestLongDouble_mem_addr : std_logic_vector(TESTSEQUENCE_ADDR_WIDTH-1 downto 0); + signal TestSequence_TestLongDouble_mem_read, TestSequence_TestLongDouble_mem_ready_in, TestSequence_TestLongDouble_mem_ready_out, TestSequence_TestLongDouble_mem_valid_in, TestSequence_TestLongDouble_mem_valid_out : std_logic; + signal TestSequence_TestLongDouble_mem_data_in, TestSequence_TestLongDouble_mem_data_out : std_logic_vector(CDR_LONG_DOUBLE_WIDTH+1-1 downto 0); -- TestSequence_TestArray_mem SIGNALS - signal TestSequence_TestArray_mem_addr : TESTSEQUENCE_TESTARRAY_ADDR_TYPE := (others => (others => '0')); - signal TestSequence_TestArray_mem_read, TestSequence_TestArray_mem_ready_in, TestSequence_TestArray_mem_ready_out, TestSequence_TestArray_mem_valid_in, TestSequence_TestArray_mem_valid_out : std_logic_vector(0 to TESTSEQUENCE_TESTARRAY_MAX_DEPTH-1) := (others => '0'); - signal TestSequence_TestArray_mem_data_in, TestSequence_TestArray_mem_data_out : TESTSEQUENCE_TESTARRAY_DATA_TYPE := (others => (others => '0')); + signal TestSequence_TestArray_mem_addr : TESTSEQUENCE_TESTARRAY_ADDR_TYPE; + signal TestSequence_TestArray_mem_read, TestSequence_TestArray_mem_ready_in, TestSequence_TestArray_mem_ready_out, TestSequence_TestArray_mem_valid_in, TestSequence_TestArray_mem_valid_out : std_logic_vector(0 to TESTSEQUENCE_TESTARRAY_MAX_DEPTH-1); + signal TestSequence_TestArray_mem_data_in, TestSequence_TestArray_mem_data_out : TESTSEQUENCE_TESTARRAY_DATA_TYPE; -- TestMap_key_mem SIGNALS - signal TestMap_key_mem_addr : std_logic_vector(TESTMAP_ADDR_WIDTH-1 downto 0) := (others => '0'); - signal TestMap_key_mem_read, TestMap_key_mem_ready_in, TestMap_key_mem_ready_out, TestMap_key_mem_valid_in, TestMap_key_mem_valid_out : std_logic := '0'; - signal TestMap_key_mem_data_in, TestMap_key_mem_data_out : std_logic_vector(CDR_OCTET_WIDTH-1 downto 0) := (others => '0'); + signal TestMap_key_mem_addr : std_logic_vector(TESTMAP_ADDR_WIDTH-1 downto 0); + signal TestMap_key_mem_read, TestMap_key_mem_ready_in, TestMap_key_mem_ready_out, TestMap_key_mem_valid_in, TestMap_key_mem_valid_out : std_logic; + signal TestMap_key_mem_data_in, TestMap_key_mem_data_out : std_logic_vector(CDR_OCTET_WIDTH-1 downto 0); -- TestMap_value_mem SIGNALS - signal TestMap_value_mem_addr : std_logic_vector(TESTMAP_ADDR_WIDTH-1 downto 0) := (others => '0'); - signal TestMap_value_mem_read, TestMap_value_mem_ready_in, TestMap_value_mem_ready_out, TestMap_value_mem_valid_in, TestMap_value_mem_valid_out : std_logic := '0'; - signal TestMap_value_mem_data_in, TestMap_value_mem_data_out : std_logic_vector(CDR_SHORT_WIDTH-1 downto 0) := (others => '0'); + signal TestMap_value_mem_addr : std_logic_vector(TESTMAP_ADDR_WIDTH-1 downto 0); + signal TestMap_value_mem_read, TestMap_value_mem_ready_in, TestMap_value_mem_ready_out, TestMap_value_mem_valid_in, TestMap_value_mem_valid_out : std_logic; + signal TestMap_value_mem_data_in, TestMap_value_mem_data_out : std_logic_vector(CDR_SHORT_WIDTH-1 downto 0); -- TestString_mem SIGNALS - signal TestString_mem_addr : std_logic_vector(TESTSTRING_ADDR_WIDTH-1 downto 0) := (others => '0'); - signal TestString_mem_read, TestString_mem_ready_in, TestString_mem_ready_out, TestString_mem_valid_in, TestString_mem_valid_out : std_logic := '0'; - signal TestString_mem_data_in, TestString_mem_data_out : std_logic_vector(CDR_CHAR_WIDTH-1 downto 0) := (others => '0'); + signal TestString_mem_addr : std_logic_vector(TESTSTRING_ADDR_WIDTH-1 downto 0); + signal TestString_mem_read, TestString_mem_ready_in, TestString_mem_ready_out, TestString_mem_valid_in, TestString_mem_valid_out : std_logic; + signal TestString_mem_data_in, TestString_mem_data_out : std_logic_vector(CDR_CHAR_WIDTH-1 downto 0); -- ###GENERATED END### @@ -378,7 +378,6 @@ begin -- ###GENERATED END### main_prc : process (all) - variable tmp_length : unsigned(WORD_WIDTH-1 downto 0) := (others => '0'); begin -- DEFAULT stage_next <= stage; diff --git a/src/Tests/test_key_hash_generator.vhd b/src/Tests/test_key_hash_generator.vhd index 65ded1e..e631f21 100644 --- a/src/Tests/test_key_hash_generator.vhd +++ b/src/Tests/test_key_hash_generator.vhd @@ -6,9 +6,9 @@ architecture arch of key_hash_generator is type STAGE_TYPE is (IDLE, GEN_CHECKSUM, FINALIZE); - signal stage, stage_next : STAGE_TYPE := IDLE; - signal checksum, checksum_next : std_logic_vector(127 downto 0) := (others => '0'); - signal done_sig, done_sig_next : std_logic := '0'; + signal stage, stage_next : STAGE_TYPE; + signal checksum, checksum_next : std_logic_vector(127 downto 0); + signal done_sig, done_sig_next : std_logic; begin diff --git a/src/Tests/test_key_holder.vhd b/src/Tests/test_key_holder.vhd index 719ecc4..bb68053 100644 --- a/src/Tests/test_key_holder.vhd +++ b/src/Tests/test_key_holder.vhd @@ -13,9 +13,9 @@ architecture test of key_holder is -- ###GENERATED END### -- *MAIN PROCESS* - signal stage, stage_next : STAGE_TYPE := IDLE; - signal cnt, cnt_next : natural range 0 to 5 := 0; - signal key_hash, key_hash_next : KEY_HASH_TYPE := HANDLE_NIL; + signal stage, stage_next : STAGE_TYPE; + signal cnt, cnt_next : natural range 0 to 5; + signal key_hash, key_hash_next : KEY_HASH_TYPE; begin diff --git a/src/addsub.vhd b/src/addsub.vhd index 0c7595a..43967c1 100644 --- a/src/addsub.vhd +++ b/src/addsub.vhd @@ -31,8 +31,8 @@ end entity; architecture arch of addsub is --*****SIGNAl DECLARATION - signal result : std_logic_vector(DATA_WIDTH-1 downto 0) := (others => '0'); - signal carry : std_logic := '0'; + signal result : std_logic_vector(DATA_WIDTH-1 downto 0); + signal carry : std_logic; begin diff --git a/src/checksum.vhd b/src/checksum.vhd index c5130e3..59ad562 100644 --- a/src/checksum.vhd +++ b/src/checksum.vhd @@ -38,8 +38,8 @@ architecture arch of addsub is end entity; --*****SIGNAl DECLARATION - signal result : std_logic_vector(DATA_WIDTH-1 downto 0) := (others => '0'); - signal carry : std_logic := '0'; + signal result : std_logic_vector(DATA_WIDTH-1 downto 0); + signal carry : std_logic; begin diff --git a/src/dds_reader.vhd b/src/dds_reader.vhd index f64da08..19823b9 100644 --- a/src/dds_reader.vhd +++ b/src/dds_reader.vhd @@ -298,220 +298,220 @@ architecture arch of dds_reader is --*****SIGNAL DECLARATION***** -- *SAMPLE MEMORY CONNECTION SIGNALS* - signal sample_addr : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); - signal sample_read : std_logic := '0'; - signal sample_read_data, sample_write_data : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); - signal sample_ready_in, sample_valid_in : std_logic := '0'; - signal sample_ready_out, sample_valid_out : std_logic := '0'; - signal sample_abort_read : std_logic := '0'; + signal sample_addr : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0); + signal sample_read : std_logic; + signal sample_read_data, sample_write_data : std_logic_vector(WORD_WIDTH-1 downto 0); + signal sample_ready_in, sample_valid_in : std_logic; + signal sample_ready_out, sample_valid_out : std_logic; + signal sample_abort_read : std_logic; -- *PAYLOAD MEMORY CONNECTION SIGNALS* - signal payload_addr : unsigned(PAYLOAD_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); - signal payload_read : std_logic := '0'; - signal payload_read_data, payload_write_data : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); - signal payload_ready_in, payload_valid_in : std_logic := '0'; - signal payload_ready_out, payload_valid_out : std_logic := '0'; - signal payload_abort_read : std_logic := '0'; + signal payload_addr : unsigned(PAYLOAD_MEMORY_ADDR_WIDTH-1 downto 0); + signal payload_read : std_logic; + signal payload_read_data, payload_write_data : std_logic_vector(WORD_WIDTH-1 downto 0); + signal payload_ready_in, payload_valid_in : std_logic; + signal payload_ready_out, payload_valid_out : std_logic; + signal payload_abort_read : std_logic; -- *INSTANCE MEMORY CONNECTION SIGNALS* - signal inst_addr : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); - signal inst_read : std_logic := '0'; - signal inst_read_data, inst_write_data : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); - signal inst_ready_in, inst_valid_in : std_logic := '0'; - signal inst_ready_out, inst_valid_out : std_logic := '0'; - signal inst_abort_read : std_logic := '0'; + signal inst_addr : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0); + signal inst_read : std_logic; + signal inst_read_data, inst_write_data : std_logic_vector(WORD_WIDTH-1 downto 0); + signal inst_ready_in, inst_valid_in : std_logic; + signal inst_ready_out, inst_valid_out : std_logic; + signal inst_abort_read : std_logic; -- *KEY HOLDER CONNECTION SIGNALS* - signal start_kh, ack_kh, valid_in_kh, ready_in_kh, last_word_in_kh, valid_out_kh, ready_out_kh, last_word_out_kh, abort_kh : std_logic := '0'; - signal opcode_kh : KEY_HOLDER_OPCODE_TYPE := NOP; - signal data_in_kh, data_out_kh : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); + signal start_kh, ack_kh, valid_in_kh, ready_in_kh, last_word_in_kh, valid_out_kh, ready_out_kh, last_word_out_kh, abort_kh : std_logic; + signal opcode_kh : KEY_HOLDER_OPCODE_TYPE; + signal data_in_kh, data_out_kh : std_logic_vector(WORD_WIDTH-1 downto 0); -- *MAIN PROCESS* -- FSM state - signal stage, stage_next : STAGE_TYPE := IDLE; + signal stage, stage_next : STAGE_TYPE; -- General Purpose Counter - signal cnt, cnt_next : natural range 0 to 18 := 0; + signal cnt, cnt_next : natural range 0 to 18; -- Counter used to read/write Payload Fames - signal cnt2, cnt2_next : natural range 0 to PAYLOAD_FRAME_SIZE := 0; + signal cnt2, cnt2_next : natural range 0 to PAYLOAD_FRAME_SIZE; -- Counter used to read/write Payload Fames - signal cnt3, cnt3_next : natural range 0 to PAYLOAD_FRAME_SIZE := 0; + signal cnt3, cnt3_next : natural range 0 to PAYLOAD_FRAME_SIZE; -- Head of Empty Sample List - signal empty_sample_list_head, empty_sample_list_head_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); + signal empty_sample_list_head, empty_sample_list_head_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0); -- Tail of Empty Sample List - signal empty_sample_list_tail, empty_sample_list_tail_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); + signal empty_sample_list_tail, empty_sample_list_tail_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0); -- Head of Empty Payload List - signal empty_payload_list_head, empty_payload_list_head_next : unsigned(PAYLOAD_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); + signal empty_payload_list_head, empty_payload_list_head_next : unsigned(PAYLOAD_MEMORY_ADDR_WIDTH-1 downto 0); -- Oldest Sample (Head of Occupied Sample List) - signal oldest_sample, oldest_sample_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); + signal oldest_sample, oldest_sample_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0); -- Newest Sample (Tail of Occupied Sample List) - signal newest_sample, newest_sample_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); + signal newest_sample, newest_sample_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0); -- Highest Timestamp of all READ Samples - signal last_read_ts, last_read_ts_next : TIME_TYPE := TIME_INVALID; + signal last_read_ts, last_read_ts_next : TIME_TYPE; -- Denotes if the oldest Sample should be removed - signal remove_oldest_sample, remove_oldest_sample_next : std_logic := '0'; + signal remove_oldest_sample, remove_oldest_sample_next : std_logic; -- Denotes if the oldest sample of the Instance with 'key_hash' should be removed - signal remove_oldest_inst_sample, remove_oldest_inst_sample_next : std_logic := '0'; + signal remove_oldest_inst_sample, remove_oldest_inst_sample_next : std_logic; -- Remote Writer ID - signal writer_id, writer_id_next : natural range 0 to MAX_REMOTE_ENDPOINTS-1 := 0; + signal writer_id, writer_id_next : natural range 0 to MAX_REMOTE_ENDPOINTS-1; -- Key Hash Latch - signal key_hash, key_hash_next : KEY_HASH_TYPE := HANDLE_NIL; + signal key_hash, key_hash_next : KEY_HASH_TYPE; -- RTPS Return Code Latch - signal rtps_return_code_latch, rtps_return_code_latch_next : HISTORY_CACHE_RESPONSE_TYPE := ERROR; + signal rtps_return_code_latch, rtps_return_code_latch_next : HISTORY_CACHE_RESPONSE_TYPE; -- DDS Return Code Latch - signal dds_return_code_latch, dds_return_code_latch_next : std_logic_vector(RETURN_CODE_WIDTH-1 downto 0) := RETCODE_ERROR; + signal dds_return_code_latch, dds_return_code_latch_next : std_logic_vector(RETURN_CODE_WIDTH-1 downto 0); -- Source Timestamp Latch - signal ts_latch, ts_latch_next : TIME_TYPE := TIME_INVALID; + signal ts_latch, ts_latch_next : TIME_TYPE; -- Lifespan Latch - signal lifespan, lifespan_next : TIME_TYPE := TIME_INVALID; + signal lifespan, lifespan_next : TIME_TYPE; -- Sample Status Info Latch - signal sample_status_info, sample_status_info_next : std_logic_vector(CDR_LONG_WIDTH-1 downto 0) := (others => '0'); + signal sample_status_info, sample_status_info_next : std_logic_vector(CDR_LONG_WIDTH-1 downto 0); -- General Purpose Payload Pointer - signal payload_addr_latch_1, payload_addr_latch_1_next : unsigned(PAYLOAD_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); + signal payload_addr_latch_1, payload_addr_latch_1_next : unsigned(PAYLOAD_MEMORY_ADDR_WIDTH-1 downto 0); -- General Purpose Payload Pointer - signal payload_addr_latch_2, payload_addr_latch_2_next : unsigned(PAYLOAD_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); + signal payload_addr_latch_2, payload_addr_latch_2_next : unsigned(PAYLOAD_MEMORY_ADDR_WIDTH-1 downto 0); -- General Purpose Sample Pointer - signal sample_addr_latch_1, sample_addr_latch_1_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); + signal sample_addr_latch_1, sample_addr_latch_1_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0); -- General Purpose Sample Pointer - signal sample_addr_latch_2, sample_addr_latch_2_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); + signal sample_addr_latch_2, sample_addr_latch_2_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0); -- General Purpose Sample Pointer - signal sample_addr_latch_3, sample_addr_latch_3_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); + signal sample_addr_latch_3, sample_addr_latch_3_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0); -- General Purpose Sample Pointer - signal sample_addr_latch_4, sample_addr_latch_4_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); + signal sample_addr_latch_4, sample_addr_latch_4_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0); -- General Purpose Sample Pointer - signal sample_addr_latch_5, sample_addr_latch_5_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); + signal sample_addr_latch_5, sample_addr_latch_5_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0); -- General Purpose Instance Pointer - signal inst_addr_latch_1, inst_addr_latch_1_next : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); + signal inst_addr_latch_1, inst_addr_latch_1_next : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0); -- General Purpose Instance Pointer - signal inst_addr_latch_2, inst_addr_latch_2_next : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); + signal inst_addr_latch_2, inst_addr_latch_2_next : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0); -- General Purpose Long Latch - signal long_latch, long_latch_next : std_logic_vector(CDR_LONG_WIDTH-1 downto 0) := (others => '0'); + signal long_latch, long_latch_next : std_logic_vector(CDR_LONG_WIDTH-1 downto 0); -- Signal used to pass Writer Bitmaps to Instance Memory Process - signal writer_bitmap : WRITER_BITMAP_ARRAY_TYPE := ZERO_WRITER_BITMAP_ARRAY; + signal writer_bitmap : WRITER_BITMAP_ARRAY_TYPE; -- Signal used to pass Sample Status Infos to Instance Memory Process - signal status_info_update : std_logic_vector(CDR_LONG_WIDTH-1 downto 0) := (others => '0'); + signal status_info_update : std_logic_vector(CDR_LONG_WIDTH-1 downto 0); -- Signal used to pass Generation Counters to the Instance Memory Process - signal gen_cnt : unsigned(CDR_LONG_WIDTH-1 downto 0) := (others => '0'); + signal gen_cnt : unsigned(CDR_LONG_WIDTH-1 downto 0); -- Signal used to pass TIMEs to the Instance Memory Process - signal deadline : TIME_TYPE := TIME_INVALID; + signal deadline : TIME_TYPE; -- Signal containing the relevant Instance Memory Frame Fields of the Instance Memory Operation - signal inst_mem_fields : std_logic_vector(0 to IMF_FLAG_WIDTH-1) := (others => '0'); + signal inst_mem_fields : std_logic_vector(0 to IMF_FLAG_WIDTH-1); -- Signal used to pass Instance Pointers to the Instance Memory Process - signal inst_addr_update : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); + signal inst_addr_update : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0); -- Signal used to pass Sample Counts to the Instance Memory Process - signal sample_cnt : unsigned(CDR_LONG_WIDTH-1 downto 0) := (others => '0'); + signal sample_cnt : unsigned(CDR_LONG_WIDTH-1 downto 0); -- Signals start of Instance Memory Operation - signal inst_op_start : std_logic := '0'; + signal inst_op_start : std_logic; -- Opcode of Instance Memory Operation (Valid only when inst_op_start is high) - signal inst_opcode : INSTANCE_OPCODE_TYPE := NOP; + signal inst_opcode : INSTANCE_OPCODE_TYPE; -- Signals the end of an Instance Memory Operation - signal inst_op_done : std_logic := '0'; + signal inst_op_done : std_logic; -- Time of next Sample Lifespan Check - signal lifespan_time, lifespan_time_next : TIME_TYPE := TIME_ZERO; + signal lifespan_time, lifespan_time_next : TIME_TYPE; -- Signifies if a Lifespan Check is in progress - signal is_lifespan_check, is_lifespan_check_next : std_logic := '0'; + signal is_lifespan_check, is_lifespan_check_next : std_logic; -- Sample State Latch - signal sample_state, sample_state_next : std_logic_vector(SAMPLE_STATE_KIND_WIDTH-1 downto 0) := (others => '0'); + signal sample_state, sample_state_next : std_logic_vector(SAMPLE_STATE_KIND_WIDTH-1 downto 0); -- View State Latch - signal view_state, view_state_next : std_logic_vector(VIEW_STATE_KIND_WIDTH-1 downto 0) := (others => '0'); + signal view_state, view_state_next : std_logic_vector(VIEW_STATE_KIND_WIDTH-1 downto 0); -- Instance State Latch - signal instance_state, instance_state_next : std_logic_vector(INSTANCE_STATE_KIND_WIDTH-1 downto 0) := (others => '0'); + signal instance_state, instance_state_next : std_logic_vector(INSTANCE_STATE_KIND_WIDTH-1 downto 0); -- Instance Handle Latch - signal instance_handle, instance_handle_next : INSTANCE_HANDLE_TYPE := HANDLE_NIL; + signal instance_handle, instance_handle_next : INSTANCE_HANDLE_TYPE; -- Max Samples Latch - signal max_samples_latch, max_samples_latch_next : unsigned(MAX_SAMPLES_WIDTH-1 downto 0) := (others => '0'); + signal max_samples_latch, max_samples_latch_next : unsigned(MAX_SAMPLES_WIDTH-1 downto 0); -- Denotes the current length of the Collection - signal collection_cnt, collection_cnt_next : unsigned(MAX_SAMPLES_WIDTH-1 downto 0) := (others => '0'); + signal collection_cnt, collection_cnt_next : unsigned(MAX_SAMPLES_WIDTH-1 downto 0); -- Denotes the current pre-calculated length of the Collection - signal collection_cnt_max, collection_cnt_max_next : unsigned(MAX_SAMPLES_WIDTH-1 downto 0) := (others => '0'); + signal collection_cnt_max, collection_cnt_max_next : unsigned(MAX_SAMPLES_WIDTH-1 downto 0); -- Denotes the Generation Rank (For a collection of length collection_cnt_max) - signal collection_generation_rank, collection_generation_rank_next : unsigned(GENERATION_RANK_WIDTH-1 downto 0) := (others => '0'); + signal collection_generation_rank, collection_generation_rank_next : unsigned(GENERATION_RANK_WIDTH-1 downto 0); -- Number of NOT_ALIVE->ALIVE Transitions during reception of selected Sample - signal cur_generation_rank, cur_generation_rank_next : unsigned(GENERATION_RANK_WIDTH-1 downto 0) := (others => '0'); + signal cur_generation_rank, cur_generation_rank_next : unsigned(GENERATION_RANK_WIDTH-1 downto 0); -- Denotes if a TAKE operation is in progress - signal is_take, is_take_next : std_logic := '0'; + signal is_take, is_take_next : std_logic; -- NOTE: We use this signal to prevent the costly Instance Marking in the case that we only need to ouptput samples of one Instance. -- Denotes if the READ/TAKE operation applies to a single Instance - signal single_instance, single_instance_next : std_logic := '0'; + signal single_instance, single_instance_next : std_logic; -- Denotes if the marks on Instances should be reset - signal unmark_instances_flag, unmark_instances_flag_next : std_logic := '0'; + signal unmark_instances_flag, unmark_instances_flag_next : std_logic; -- Denotes if the READ/TAKE operation does not apply to a specific Instance - signal dynamic_next_instance, dynamic_next_instance_next : std_logic := '0'; + signal dynamic_next_instance, dynamic_next_instance_next : std_logic; -- Signal containing the number of currently stale Instances - signal stale_inst_cnt, stale_inst_cnt_next : natural range 0 to to_integer(unsigned(MAX_INSTANCES))-1 := 0; + signal stale_inst_cnt, stale_inst_cnt_next : natural range 0 to to_integer(unsigned(MAX_INSTANCES))-1; -- Test signal used for testbench synchronisation - signal idle_sig : std_logic := '0'; + signal idle_sig : std_logic; -- Signal denoting if the PRE_CALCULATE stage was run for the current instance - signal pre_calculated, pre_calculated_next : std_logic := '0'; + signal pre_calculated, pre_calculated_next : std_logic; -- Disposed Generation Count Latch - signal dis_gen_cnt_latch, dis_gen_cnt_latch_next : unsigned(WORD_WIDTH-1 downto 0) := (others => '0'); + signal dis_gen_cnt_latch, dis_gen_cnt_latch_next : unsigned(WORD_WIDTH-1 downto 0); -- No Writers Generation Count Latch - signal no_w_gen_cnt_latch, no_w_gen_cnt_latch_next : unsigned(WORD_WIDTH-1 downto 0) := (others => '0'); + signal no_w_gen_cnt_latch, no_w_gen_cnt_latch_next : unsigned(WORD_WIDTH-1 downto 0); -- Denotes if a newer sample of the same Instance exists - signal newer_inst_sample, newer_inst_sample_next : std_logic := '0'; + signal newer_inst_sample, newer_inst_sample_next : std_logic; -- Denotes if a new Instance is added - signal new_inst, new_inst_next : std_logic := '0'; + signal new_inst, new_inst_next : std_logic; -- Triggers Sample Generation - signal trigger_sample_gen, trigger_sample_gen_next : std_logic := '0'; + signal trigger_sample_gen, trigger_sample_gen_next : std_logic; -- Waits for Sample Removal (MAX_SAMPLES Limit lift) to trigger Sample Generation - signal wait_for_sample_removal, wait_for_sample_removal_next : std_logic := '0'; + signal wait_for_sample_removal, wait_for_sample_removal_next : std_logic; -- *COMMUNICATION STATUS* - signal status_sig, status_sig_next : std_logic_vector(STATUS_KIND_WIDTH-1 downto 0) := (others => '0'); + signal status_sig, status_sig_next : std_logic_vector(STATUS_KIND_WIDTH-1 downto 0); -- SAMPLE REJECT STATUS - signal sample_rej_cnt, sample_rej_cnt_next : unsigned(SAMPLE_REJECTED_STATUS_COUNT_WIDTH-1 downto 0) := (others => '0'); - signal sample_rej_cnt_change, sample_rej_cnt_change_next : unsigned(SAMPLE_REJECTED_STATUS_COUNT_WIDTH-1 downto 0) := (others => '0'); - signal sample_rej_last_reason, sample_rej_last_reason_next : std_logic_vector(CDR_ENUMERATION_WIDTH-1 downto 0) := (others =>'0'); - signal sample_rej_last_inst, sample_rej_last_inst_next : INSTANCE_HANDLE_TYPE := (others => (others => '0')); + signal sample_rej_cnt, sample_rej_cnt_next : unsigned(SAMPLE_REJECTED_STATUS_COUNT_WIDTH-1 downto 0); + signal sample_rej_cnt_change, sample_rej_cnt_change_next : unsigned(SAMPLE_REJECTED_STATUS_COUNT_WIDTH-1 downto 0); + signal sample_rej_last_reason, sample_rej_last_reason_next : std_logic_vector(CDR_ENUMERATION_WIDTH-1 downto 0); + signal sample_rej_last_inst, sample_rej_last_inst_next : INSTANCE_HANDLE_TYPE; -- REQUESTED DEADLINE MISSED STATUS -- Time of next Deadline Miss Check - signal deadline_time, deadline_time_next : TIME_TYPE := TIME_ZERO; - signal deadline_miss_cnt, deadline_miss_cnt_next : unsigned(REQUESTED_DEADLINE_MISSED_STATUS_COUNT_WIDTH-1 downto 0) := (others => '0'); - signal deadline_miss_cnt_change, deadline_miss_cnt_change_next : unsigned(REQUESTED_DEADLINE_MISSED_STATUS_COUNT_WIDTH-1 downto 0) := (others => '0'); - signal deadline_miss_last_inst, deadline_miss_last_inst_next : INSTANCE_HANDLE_TYPE := (others => (others => '0')); + signal deadline_time, deadline_time_next : TIME_TYPE; + signal deadline_miss_cnt, deadline_miss_cnt_next : unsigned(REQUESTED_DEADLINE_MISSED_STATUS_COUNT_WIDTH-1 downto 0); + signal deadline_miss_cnt_change, deadline_miss_cnt_change_next : unsigned(REQUESTED_DEADLINE_MISSED_STATUS_COUNT_WIDTH-1 downto 0); + signal deadline_miss_last_inst, deadline_miss_last_inst_next : INSTANCE_HANDLE_TYPE; -- *SAMPLE INFO* - signal si_sample_state_sig, si_sample_state_sig_next : std_logic_vector(SAMPLE_STATE_KIND_WIDTH-1 downto 0) := (others => '0'); - signal si_view_state_sig, si_view_state_sig_next : std_logic_vector(VIEW_STATE_KIND_WIDTH-1 downto 0) := (others => '0'); - signal si_instance_state_sig, si_instance_state_sig_next : std_logic_vector(INSTANCE_STATE_KIND_WIDTH-1 downto 0) := (others => '0'); - signal si_source_timestamp_sig, si_source_timestamp_sig_next : TIME_TYPE := TIME_INVALID; - signal si_instance_handle_sig, si_instance_handle_sig_next : INSTANCE_HANDLE_TYPE := HANDLE_NIL; - signal si_publication_handle_sig, si_publication_handle_sig_next : PUBLICATION_HANDLE_TYPE := (others => (others => '0')); - signal si_disposed_generation_count_sig, si_disposed_generation_count_sig_next : std_logic_vector(DISPOSED_GENERATION_COUNT_WIDTH-1 downto 0) := (others => '0'); - signal si_no_writers_generation_count_sig, si_no_writers_generation_count_sig_next : std_logic_vector(NO_WRITERS_GENERATION_COUNT_WIDTH-1 downto 0) := (others => '0'); - signal si_sample_rank_sig, si_sample_rank_sig_next : unsigned(SAMPLE_RANK_WIDTH-1 downto 0) := (others => '0'); - signal si_generation_rank_sig, si_generation_rank_sig_next : unsigned(GENERATION_RANK_WIDTH-1 downto 0) := (others => '0'); - signal si_absolute_generation_rank_sig, si_absolute_generation_rank_sig_next : unsigned(ABSOLUTE_GENERATION_COUNT_WIDTH-1 downto 0) := (others => '0'); - signal si_valid_data_sig, si_valid_data_sig_next : std_logic := '0'; - signal si_valid_sig, si_valid_sig_next : std_logic := '0'; - signal eoc_sig, eoc_sig_next : std_logic := '0'; + signal si_sample_state_sig, si_sample_state_sig_next : std_logic_vector(SAMPLE_STATE_KIND_WIDTH-1 downto 0); + signal si_view_state_sig, si_view_state_sig_next : std_logic_vector(VIEW_STATE_KIND_WIDTH-1 downto 0); + signal si_instance_state_sig, si_instance_state_sig_next : std_logic_vector(INSTANCE_STATE_KIND_WIDTH-1 downto 0); + signal si_source_timestamp_sig, si_source_timestamp_sig_next : TIME_TYPE; + signal si_instance_handle_sig, si_instance_handle_sig_next : INSTANCE_HANDLE_TYPE; + signal si_publication_handle_sig, si_publication_handle_sig_next : PUBLICATION_HANDLE_TYPE; + signal si_disposed_generation_count_sig, si_disposed_generation_count_sig_next : std_logic_vector(DISPOSED_GENERATION_COUNT_WIDTH-1 downto 0); + signal si_no_writers_generation_count_sig, si_no_writers_generation_count_sig_next : std_logic_vector(NO_WRITERS_GENERATION_COUNT_WIDTH-1 downto 0); + signal si_sample_rank_sig, si_sample_rank_sig_next : unsigned(SAMPLE_RANK_WIDTH-1 downto 0); + signal si_generation_rank_sig, si_generation_rank_sig_next : unsigned(GENERATION_RANK_WIDTH-1 downto 0); + signal si_absolute_generation_rank_sig, si_absolute_generation_rank_sig_next : unsigned(ABSOLUTE_GENERATION_COUNT_WIDTH-1 downto 0); + signal si_valid_data_sig, si_valid_data_sig_next : std_logic; + signal si_valid_sig, si_valid_sig_next : std_logic; + signal eoc_sig, eoc_sig_next : std_logic; -- *INSTANCE MEMORY PROCESS* -- Instance Memory FSM state - signal inst_stage, inst_stage_next : INST_STAGE_TYPE := IDLE; + signal inst_stage, inst_stage_next : INST_STAGE_TYPE; -- Pointer to current relevant Instance Memory Frame Address - signal inst_addr_base, inst_addr_base_next : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); + signal inst_addr_base, inst_addr_base_next : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0); -- Pointer to next Instance Memory Frame Address - signal inst_next_addr_base, inst_next_addr_base_next : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); + signal inst_next_addr_base, inst_next_addr_base_next : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0); -- Pointer to previous Instacne Memory Address - signal inst_prev_addr_base, inst_prev_addr_base_next : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); + signal inst_prev_addr_base, inst_prev_addr_base_next : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0); -- Head of Empty Instance List - signal inst_empty_head, inst_empty_head_next : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); + signal inst_empty_head, inst_empty_head_next : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0); -- Head of Occupied Instance List - signal inst_occupied_head, inst_occupied_head_next : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); + signal inst_occupied_head, inst_occupied_head_next : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0); -- Latch for Instance Data from main process - signal inst_latch_data, inst_latch_data_next : INST_LATCH_DATA_TYPE := ZERO_INST_LATCH_DATA; + signal inst_latch_data, inst_latch_data_next : INST_LATCH_DATA_TYPE; -- NOTE: The next signal is driven by the inst_ctrl_prc. In case WITH_KEY is FALSE, no inst_ctrl_prc is generated and the inst_data is -- set by the main process directly by drivng the next2 signal. The sync_prc is responsible for latching the corrct next signal. -- Latch for Instance Data from memory - signal inst_data, inst_data_next, inst_data_next2 : INSTANCE_DATA_TYPE := ZERO_INSTANCE_DATA; + signal inst_data, inst_data_next, inst_data_next2 : INSTANCE_DATA_TYPE; -- General Purpose Counter - signal inst_cnt, inst_cnt_next : natural range 0 to 21 := 0; + signal inst_cnt, inst_cnt_next : natural range 0 to 21; -- Counter used to read/write the Writer Bitmap - signal inst_cnt2, inst_cnt2_next : natural range 0 to WRITER_BITMAP_ARRAY_TYPE'length := 0; + signal inst_cnt2, inst_cnt2_next : natural range 0 to WRITER_BITMAP_ARRAY_TYPE'length; -- General Purpose Long Latch - signal inst_long_latch, inst_long_latch_next : std_logic_vector(CDR_LONG_WIDTH-1 downto 0) := (others => '0'); + signal inst_long_latch, inst_long_latch_next : std_logic_vector(CDR_LONG_WIDTH-1 downto 0); -- Instance Memory Flag Array denoting which inst_data Fields are up-to-date with the respective fields of the Instance (Pointed by inst_addr_base) - signal current_imf, current_imf_next : std_logic_vector(0 to IMF_FLAG_WIDTH-1) := (others => '0'); + signal current_imf, current_imf_next : std_logic_vector(0 to IMF_FLAG_WIDTH-1); --*****ALIAS DECLARATION***** alias prev_sample : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) is sample_addr_latch_1; @@ -719,10 +719,10 @@ begin -- RESET_SAMPLE_MEMORY Reset Sample Memory to Empty State -- RESET_PAYLOAD_MEMORY Reset Payload Memory to Empty State parse_a_prc : process (all) - variable tmp_dw : DOUBLE_WORD_ARRAY := (others => (others => '0')); - variable tmp_bitmap : std_logic_vector(0 to WRITER_BITMAP_WIDTH-1) := (others => '0'); - variable tmp_update : std_logic_vector(0 to IMF_FLAG_WIDTH-1) := (others => '0'); - variable tmp_bool : boolean := FALSE; + variable tmp_dw : DOUBLE_WORD_ARRAY; + variable tmp_bitmap : std_logic_vector(0 to WRITER_BITMAP_WIDTH-1); + variable tmp_update : std_logic_vector(0 to IMF_FLAG_WIDTH-1); + variable tmp_bool : boolean; begin -- DEFAULT Registered stage_next <= stage; diff --git a/src/dds_writer.vhd b/src/dds_writer.vhd index 4c94dcb..f53a279 100644 --- a/src/dds_writer.vhd +++ b/src/dds_writer.vhd @@ -257,194 +257,194 @@ architecture arch of dds_writer is --*****SIGNAL DECLARATION***** -- *SAMPLE MEMORY CONNECTION SIGNALS* - signal sample_addr : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); - signal sample_read : std_logic := '0'; - signal sample_read_data, sample_write_data : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); - signal sample_ready_in, sample_valid_in : std_logic := '0'; - signal sample_ready_out, sample_valid_out : std_logic := '0'; - signal sample_abort_read : std_logic := '0'; + signal sample_addr : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0); + signal sample_read : std_logic; + signal sample_read_data, sample_write_data : std_logic_vector(WORD_WIDTH-1 downto 0); + signal sample_ready_in, sample_valid_in : std_logic; + signal sample_ready_out, sample_valid_out : std_logic; + signal sample_abort_read : std_logic; -- *PAYLOAD MEMORY CONNECTION SIGNALS* - signal payload_addr : unsigned(PAYLOAD_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); - signal payload_read : std_logic := '0'; - signal payload_read_data, payload_write_data : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); - signal payload_ready_in, payload_valid_in : std_logic := '0'; - signal payload_ready_out, payload_valid_out : std_logic := '0'; - signal payload_abort_read : std_logic := '0'; + signal payload_addr : unsigned(PAYLOAD_MEMORY_ADDR_WIDTH-1 downto 0); + signal payload_read : std_logic; + signal payload_read_data, payload_write_data : std_logic_vector(WORD_WIDTH-1 downto 0); + signal payload_ready_in, payload_valid_in : std_logic; + signal payload_ready_out, payload_valid_out : std_logic; + signal payload_abort_read : std_logic; -- *INSTANCE MEMORY CONNECTION SIGNALS* - signal inst_addr : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); - signal inst_read : std_logic := '0'; - signal inst_read_data, inst_write_data : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); - signal inst_ready_in, inst_valid_in : std_logic := '0'; - signal inst_ready_out, inst_valid_out : std_logic := '0'; - signal inst_abort_read : std_logic := '0'; + signal inst_addr : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0); + signal inst_read : std_logic; + signal inst_read_data, inst_write_data : std_logic_vector(WORD_WIDTH-1 downto 0); + signal inst_ready_in, inst_valid_in : std_logic; + signal inst_ready_out, inst_valid_out : std_logic; + signal inst_abort_read : std_logic; -- *KEY HOLDER CONNECTION SIGNALS* - signal start_kh, ack_kh, valid_in_kh, ready_in_kh, last_word_in_kh, valid_out_kh, ready_out_kh, last_word_out_kh, abort_kh : std_logic := '0'; - signal opcode_kh : KEY_HOLDER_OPCODE_TYPE := NOP; - signal data_in_kh, data_out_kh : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); + signal start_kh, ack_kh, valid_in_kh, ready_in_kh, last_word_in_kh, valid_out_kh, ready_out_kh, last_word_out_kh, abort_kh : std_logic; + signal opcode_kh : KEY_HOLDER_OPCODE_TYPE; + signal data_in_kh, data_out_kh : std_logic_vector(WORD_WIDTH-1 downto 0); -- *MAIN PROCESS* -- FSM state - signal stage, stage_next : STAGE_TYPE := IDLE; + signal stage, stage_next : STAGE_TYPE; -- FSM state latch. Used to transition dynamically to different states from the same state. - signal return_stage, return_stage_next : STAGE_TYPE := IDLE; + signal return_stage, return_stage_next : STAGE_TYPE; -- General Purpose Counter - signal cnt, cnt_next : natural range 0 to 14 := 0; + signal cnt, cnt_next : natural range 0 to 14; -- Counter used to read/write Payload Fames - signal cnt2, cnt2_next : natural range 0 to max(PAYLOAD_FRAME_SIZE, INSTANCE_HANDLE_TYPE'length-1) := 0; + signal cnt2, cnt2_next : natural range 0 to max(PAYLOAD_FRAME_SIZE, INSTANCE_HANDLE_TYPE'length-1); -- Counter used to read/write Payload Fames - signal cnt3, cnt3_next : natural range 0 to PAYLOAD_FRAME_SIZE := 0; + signal cnt3, cnt3_next : natural range 0 to PAYLOAD_FRAME_SIZE; -- Head of Empty Sample List - signal empty_sample_list_head, empty_sample_list_head_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); + signal empty_sample_list_head, empty_sample_list_head_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0); -- Tail of Empty Sample List - signal empty_sample_list_tail, empty_sample_list_tail_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); + signal empty_sample_list_tail, empty_sample_list_tail_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0); -- Head of Empty Payload List - signal empty_payload_list_head, empty_payload_list_head_next : unsigned(PAYLOAD_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); + signal empty_payload_list_head, empty_payload_list_head_next : unsigned(PAYLOAD_MEMORY_ADDR_WIDTH-1 downto 0); -- Oldest Sample (Head of Occupied Sample List) - signal oldest_sample, oldest_sample_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); + signal oldest_sample, oldest_sample_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0); -- Newest Sample (Tail of Occupied Sample List) - signal newest_sample, newest_sample_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); + signal newest_sample, newest_sample_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0); -- Denotes if the oldest Sample should be removed - signal remove_oldest_sample, remove_oldest_sample_next : std_logic := '0'; + signal remove_oldest_sample, remove_oldest_sample_next : std_logic; -- Denotes if the oldest sample of the Instance with 'key_hash' should be removed - signal remove_oldest_inst_sample, remove_oldest_inst_sample_next : std_logic := '0'; + signal remove_oldest_inst_sample, remove_oldest_inst_sample_next : std_logic; -- Denotes if the Sample tobe removed should be ACKed - signal remove_ack_sample, remove_ack_sample_next : std_logic := '0'; + signal remove_ack_sample, remove_ack_sample_next : std_logic; -- Lifespan Latch - signal lifespan, lifespan_next : TIME_TYPE := TIME_INVALID; + signal lifespan, lifespan_next : TIME_TYPE; -- Key hash Latch - signal key_hash, key_hash_next : KEY_HASH_TYPE := (others => (others => '0')); + signal key_hash, key_hash_next : KEY_HASH_TYPE; -- Return Code Latch - signal return_code_latch, return_code_latch_next : std_logic_vector(RETURN_CODE_WIDTH-1 downto 0) := (others => '0'); + signal return_code_latch, return_code_latch_next : std_logic_vector(RETURN_CODE_WIDTH-1 downto 0); -- Instance Handle Latch - signal instance_handle, instance_handle_next : INSTANCE_HANDLE_TYPE := HANDLE_NIL; + signal instance_handle, instance_handle_next : INSTANCE_HANDLE_TYPE; -- Source Timestamp Latch - signal source_ts, source_ts_next : TIME_TYPE := TIME_INVALID; + signal source_ts, source_ts_next : TIME_TYPE; -- Sequence Number Latch - signal seq_nr, seq_nr_next : SEQUENCENUMBER_TYPE := SEQUENCENUMBER_UNKNOWN; + signal seq_nr, seq_nr_next : SEQUENCENUMBER_TYPE; -- Sample Status Info Latch - signal sample_status_info, sample_status_info_next : std_logic_vector(CDR_LONG_WIDTH-1 downto 0) := (others => '0'); + signal sample_status_info, sample_status_info_next : std_logic_vector(CDR_LONG_WIDTH-1 downto 0); -- General Purpose Payload Pointer - signal payload_addr_latch_1, payload_addr_latch_1_next : unsigned(PAYLOAD_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); + signal payload_addr_latch_1, payload_addr_latch_1_next : unsigned(PAYLOAD_MEMORY_ADDR_WIDTH-1 downto 0); -- General Purpose Payload Pointer - signal payload_addr_latch_2, payload_addr_latch_2_next : unsigned(PAYLOAD_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); + signal payload_addr_latch_2, payload_addr_latch_2_next : unsigned(PAYLOAD_MEMORY_ADDR_WIDTH-1 downto 0); -- General Purpose Sample Pointer - signal sample_addr_latch_1, sample_addr_latch_1_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); + signal sample_addr_latch_1, sample_addr_latch_1_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0); -- General Purpose Sample Pointer - signal sample_addr_latch_2, sample_addr_latch_2_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); + signal sample_addr_latch_2, sample_addr_latch_2_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0); -- General Purpose Sample Pointer - signal sample_addr_latch_3, sample_addr_latch_3_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); + signal sample_addr_latch_3, sample_addr_latch_3_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0); -- General Purpose Sample Pointer - signal sample_addr_latch_4, sample_addr_latch_4_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); + signal sample_addr_latch_4, sample_addr_latch_4_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0); -- General Purpose Instance Pointer - signal inst_addr_latch_1, inst_addr_latch_1_next : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); + signal inst_addr_latch_1, inst_addr_latch_1_next : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0); -- General Purpose Instance Pointer - signal inst_addr_latch_2, inst_addr_latch_2_next : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); + signal inst_addr_latch_2, inst_addr_latch_2_next : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0); -- General Purpose Long Latch - signal long_latch, long_latch_next : std_logic_vector(CDR_LONG_WIDTH-1 downto 0) := (others => '0'); + signal long_latch, long_latch_next : std_logic_vector(CDR_LONG_WIDTH-1 downto 0); -- Signal used to pass Sample Status Infos to Instance Memory Process - signal status_info_update : std_logic_vector(CDR_LONG_WIDTH-1 downto 0) := (others => '0'); + signal status_info_update : std_logic_vector(CDR_LONG_WIDTH-1 downto 0); -- Signal used to pass TIMEs to the Instance Memory Process - signal deadline : TIME_TYPE := TIME_INVALID; + signal deadline : TIME_TYPE; -- Signal containing the relevant Instance Memory Frame Fields of the Instance Memory Operation - signal inst_mem_fields : std_logic_vector(0 to IMF_FLAG_WIDTH-1) := (others => '0'); + signal inst_mem_fields : std_logic_vector(0 to IMF_FLAG_WIDTH-1); -- Signal used to pass Instance Pointers to the Instance Memory Process - signal inst_addr_update : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); + signal inst_addr_update : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0); -- Signal used to pass Sample Counts to the Instance Memory Process - signal sample_cnt : unsigned(CDR_LONG_WIDTH-1 downto 0) := (others => '0'); + signal sample_cnt : unsigned(CDR_LONG_WIDTH-1 downto 0); -- Signal used to pass ACK Counts to the Instance Memory Process - signal ack_cnt : unsigned(CDR_LONG_WIDTH-1 downto 0) := (others => '0'); + signal ack_cnt : unsigned(CDR_LONG_WIDTH-1 downto 0); -- Signals start of Instance Memory Operation - signal inst_op_start : std_logic := '0'; + signal inst_op_start : std_logic; -- Opcode of Instance Memory Operation (Valid only when inst_op_start is high) - signal inst_opcode : INSTANCE_OPCODE_TYPE := NOP; + signal inst_opcode : INSTANCE_OPCODE_TYPE; -- Signals the end of an Instance Memory Operation - signal inst_op_done : std_logic := '0'; + signal inst_op_done : std_logic; -- Time of next Sample Lifespan Check - signal lifespan_time, lifespan_time_next : TIME_TYPE := TIME_ZERO; + signal lifespan_time, lifespan_time_next : TIME_TYPE; -- Signifies if a Lifespan Check is in progress - signal is_lifespan_check, is_lifespan_check_next : std_logic := '0'; + signal is_lifespan_check, is_lifespan_check_next : std_logic; -- Signal used to generate the monotonically rising Sequence Numbers -- It contains the next applicable Sequence Number - signal global_seq_nr, global_seq_nr_next : SEQUENCENUMBER_TYPE := SEQUENCENUMBER_UNKNOWN; + signal global_seq_nr, global_seq_nr_next : SEQUENCENUMBER_TYPE; -- Signal containing the current number of stored samples - signal global_sample_cnt, global_sample_cnt_next : natural range 0 to to_integer(unsigned(MAX_SAMPLES)+1) := 0; + signal global_sample_cnt, global_sample_cnt_next : natural range 0 to to_integer(unsigned(MAX_SAMPLES)+1); -- Signal containing the current number of ACKed stored samples - signal global_ack_cnt, global_ack_cnt_next : natural range 0 to to_integer(unsigned(MAX_SAMPLES)+1) := 0; + signal global_ack_cnt, global_ack_cnt_next : natural range 0 to to_integer(unsigned(MAX_SAMPLES)+1); -- Signal containing the number of currently stale Instances - signal stale_inst_cnt, stale_inst_cnt_next : natural range 0 to to_integer(unsigned(MAX_INSTANCES)) := 0; + signal stale_inst_cnt, stale_inst_cnt_next : natural range 0 to to_integer(unsigned(MAX_INSTANCES)); -- Signifies if a Instance Register Operation is in progress - signal register_op, register_op_next : std_logic := '0'; + signal register_op, register_op_next : std_logic; -- Signifies if a Instance Lookup Operation is in progress - signal lookup_op, lookup_op_next : std_logic := '0'; + signal lookup_op, lookup_op_next : std_logic; -- Signifies if a WAIT_FOR_ACKNOWLEDGEMENT Operation is in progress - signal ack_wait, ack_wait_next : std_logic := '0'; + signal ack_wait, ack_wait_next : std_logic; -- Timout time for DDS Operation - signal timeout_time, timeout_time_next : TIME_TYPE := TIME_INVALID; + signal timeout_time, timeout_time_next : TIME_TYPE; -- Signal used to differentiate between ACK and NACK Operations - signal is_ack, is_ack_next : std_logic := '0'; + signal is_ack, is_ack_next : std_logic; -- Signal used to differentiate between RTPS and DDS Operations - signal is_rtps, is_rtps_next : std_logic := '0'; + signal is_rtps, is_rtps_next : std_logic; -- Signifies if new Samples are available for RTPS Writer - signal data_available_sig, data_available_sig_next : std_logic := '0'; + signal data_available_sig, data_available_sig_next : std_logic; -- Denotes if Orphan Samples (of an removed stale instance) need to be removed - signal orphan_samples, orphan_samples_next : std_logic := '0'; + signal orphan_samples, orphan_samples_next : std_logic; -- Test signal used for testbench synchronisation - signal idle_sig : std_logic := '0'; + signal idle_sig : std_logic; -- *COMMUNICATION STATUS* - signal status_sig, status_sig_next : std_logic_vector(STATUS_KIND_WIDTH-1 downto 0) := (others => '0'); + signal status_sig, status_sig_next : std_logic_vector(STATUS_KIND_WIDTH-1 downto 0); -- LIVELINESS LOST STATUS -- Time of next Liveliness Deadline - signal lease_deadline, lease_deadline_next : TIME_TYPE := TIME_INVALID; - signal liveliness_lost_cnt, liveliness_lost_cnt_next : unsigned(LIVELINESS_LOST_STATUS_COUNT_WIDTH-1 downto 0) := (others => '0'); - signal liveliness_lost_cnt_change, liveliness_lost_cnt_change_next : unsigned(LIVELINESS_LOST_STATUS_COUNT_WIDTH-1 downto 0) := (others => '0'); + signal lease_deadline, lease_deadline_next : TIME_TYPE; + signal liveliness_lost_cnt, liveliness_lost_cnt_next : unsigned(LIVELINESS_LOST_STATUS_COUNT_WIDTH-1 downto 0); + signal liveliness_lost_cnt_change, liveliness_lost_cnt_change_next : unsigned(LIVELINESS_LOST_STATUS_COUNT_WIDTH-1 downto 0); -- SAMPLE REJECT STATUS - signal sample_rej_cnt, sample_rej_cnt_next : unsigned(SAMPLE_REJECTED_STATUS_COUNT_WIDTH-1 downto 0) := (others => '0'); - signal sample_rej_cnt_change, sample_rej_cnt_change_next : unsigned(SAMPLE_REJECTED_STATUS_COUNT_WIDTH-1 downto 0) := (others => '0'); - signal sample_rej_last_reason, sample_rej_last_reason_next : std_logic_vector(CDR_ENUMERATION_WIDTH-1 downto 0) := (others =>'0'); - signal sample_rej_last_inst, sample_rej_last_inst_next : INSTANCE_HANDLE_TYPE := (others => (others => '0')); + signal sample_rej_cnt, sample_rej_cnt_next : unsigned(SAMPLE_REJECTED_STATUS_COUNT_WIDTH-1 downto 0); + signal sample_rej_cnt_change, sample_rej_cnt_change_next : unsigned(SAMPLE_REJECTED_STATUS_COUNT_WIDTH-1 downto 0); + signal sample_rej_last_reason, sample_rej_last_reason_next : std_logic_vector(CDR_ENUMERATION_WIDTH-1 downto 0); + signal sample_rej_last_inst, sample_rej_last_inst_next : INSTANCE_HANDLE_TYPE; -- OFFERED DEADLINE MISSED STATUS -- Time of next Deadline Miss Check - signal deadline_time, deadline_time_next : TIME_TYPE := TIME_ZERO; - signal deadline_miss_cnt, deadline_miss_cnt_next : unsigned(REQUESTED_DEADLINE_MISSED_STATUS_COUNT_WIDTH-1 downto 0) := (others => '0'); - signal deadline_miss_cnt_change, deadline_miss_cnt_change_next : unsigned(REQUESTED_DEADLINE_MISSED_STATUS_COUNT_WIDTH-1 downto 0) := (others => '0'); - signal deadline_miss_last_inst, deadline_miss_last_inst_next : INSTANCE_HANDLE_TYPE := (others => (others => '0')); + signal deadline_time, deadline_time_next : TIME_TYPE; + signal deadline_miss_cnt, deadline_miss_cnt_next : unsigned(REQUESTED_DEADLINE_MISSED_STATUS_COUNT_WIDTH-1 downto 0); + signal deadline_miss_cnt_change, deadline_miss_cnt_change_next : unsigned(REQUESTED_DEADLINE_MISSED_STATUS_COUNT_WIDTH-1 downto 0); + signal deadline_miss_last_inst, deadline_miss_last_inst_next : INSTANCE_HANDLE_TYPE; -- *CACHE CHANGE* - signal cc_instance_handle_sig, cc_instance_handle_sig_next : INSTANCE_HANDLE_TYPE := HANDLE_NIL; - signal cc_kind_sig, cc_kind_sig_next : CACHE_CHANGE_KIND_TYPE := ALIVE; - signal cc_source_timestamp_sig, cc_source_timestamp_sig_next : TIME_TYPE := TIME_INVALID; - signal cc_seq_nr_sig, cc_seq_nr_sig_next : SEQUENCENUMBER_TYPE := SEQUENCENUMBER_UNKNOWN; + signal cc_instance_handle_sig, cc_instance_handle_sig_next : INSTANCE_HANDLE_TYPE; + signal cc_kind_sig, cc_kind_sig_next : CACHE_CHANGE_KIND_TYPE; + signal cc_source_timestamp_sig, cc_source_timestamp_sig_next : TIME_TYPE; + signal cc_seq_nr_sig, cc_seq_nr_sig_next : SEQUENCENUMBER_TYPE; -- *INSTANCE MEMORY PROCESS* -- Instance Memory FSM state - signal inst_stage, inst_stage_next : INST_STAGE_TYPE := IDLE; + signal inst_stage, inst_stage_next : INST_STAGE_TYPE; -- Pointer to current relevant Instance Memory Frame Address - signal inst_addr_base, inst_addr_base_next : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); + signal inst_addr_base, inst_addr_base_next : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0); -- Pointer to next Instance Memory Frame Address - signal inst_next_addr_base, inst_next_addr_base_next : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); + signal inst_next_addr_base, inst_next_addr_base_next : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0); -- Pointer to previous Instacne Memory Address - signal inst_prev_addr_base, inst_prev_addr_base_next : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); + signal inst_prev_addr_base, inst_prev_addr_base_next : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0); -- Head of Empty Instance List - signal inst_empty_head, inst_empty_head_next : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); + signal inst_empty_head, inst_empty_head_next : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0); -- Head of Occupied Instance List - signal inst_occupied_head, inst_occupied_head_next : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); + signal inst_occupied_head, inst_occupied_head_next : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0); -- Latch for Instance Data from main process - signal inst_latch_data, inst_latch_data_next : INST_LATCH_DATA_TYPE := ZERO_INST_LATCH_DATA; + signal inst_latch_data, inst_latch_data_next : INST_LATCH_DATA_TYPE; -- NOTE: The next signal is driven by the inst_ctrl_prc. In case WITH_KEY is FALSE, no inst_ctrl_prc is generated and the inst_data is -- set by the main process directly by drivng the next2 signal. The sync_prc is responsible for latching the corrct next signal. -- Latch for Instance Data from memory - signal inst_data, inst_data_next, inst_data_next2 : INSTANCE_DATA_TYPE := ZERO_INSTANCE_DATA; + signal inst_data, inst_data_next, inst_data_next2 : INSTANCE_DATA_TYPE; -- General Purpose Counter - signal inst_cnt, inst_cnt_next : natural range 0 to 13 := 0; + signal inst_cnt, inst_cnt_next : natural range 0 to 13; -- General Purpose Long Latch - signal inst_long_latch, inst_long_latch_next : std_logic_vector(CDR_LONG_WIDTH-1 downto 0) := (others => '0'); + signal inst_long_latch, inst_long_latch_next : std_logic_vector(CDR_LONG_WIDTH-1 downto 0); -- Instance Memory Flag Array denoting which inst_data Fields are up-to-date with the respective fields of the Instance (Pointed by inst_addr_base) - signal current_imf, current_imf_next : std_logic_vector(0 to IMF_FLAG_WIDTH-1) := (others => '0'); + signal current_imf, current_imf_next : std_logic_vector(0 to IMF_FLAG_WIDTH-1); --*****ALIAS DECLARATION***** alias prev_sample : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) is sample_addr_latch_1; @@ -616,8 +616,8 @@ begin -- RESET_SAMPLE_MEMORY Reset Sample Memory to Empty State -- RESET_PAYLOAD_MEMORY Reset Payload Memory to Empty State parse_a_prc : process (all) - variable tmp_dw : DOUBLE_WORD_ARRAY := (others => (others => '0')); - variable tmp_bool : boolean := FALSE; + variable tmp_dw : DOUBLE_WORD_ARRAY; + variable tmp_bool : boolean; begin -- DEFAULT Registered stage_next <= stage; diff --git a/src/history_cache.vhd b/src/history_cache.vhd index db8a78a..8f19dc4 100644 --- a/src/history_cache.vhd +++ b/src/history_cache.vhd @@ -139,78 +139,78 @@ architecture arch of history_cache is ); --*****SIGNAL DECLARATION - signal sample_addr_a, sample_addr_a_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); - signal sample_addr_b, sample_addr_b_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); - signal sample_wen_a, sample_wen_b : std_logic := '0'; - signal sample_ren_a, sample_ren_b : std_logic := '0'; - signal sample_read_data_a, sample_read_data_b : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); - signal sample_write_data_a, sample_write_data_b : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); + signal sample_addr_a, sample_addr_a_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0); + signal sample_addr_b, sample_addr_b_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0); + signal sample_wen_a, sample_wen_b : std_logic; + signal sample_ren_a, sample_ren_b : std_logic; + signal sample_read_data_a, sample_read_data_b : std_logic_vector(WORD_WIDTH-1 downto 0); + signal sample_write_data_a, sample_write_data_b : std_logic_vector(WORD_WIDTH-1 downto 0); - signal payload_addr_a, payload_addr_a_next : unsigned(PAYLOAD_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); - signal payload_addr_b, payload_addr_b_next : unsigned(PAYLOAD_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); - signal payload_wen_a, payload_wen_b : std_logic := '0'; - signal payload_ren_a, payload_ren_b : std_logic := '0'; - signal payload_read_data_a, payload_read_data_b : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); - signal payload_write_data_a, payload_write_data_b : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); + signal payload_addr_a, payload_addr_a_next : unsigned(PAYLOAD_MEMORY_ADDR_WIDTH-1 downto 0); + signal payload_addr_b, payload_addr_b_next : unsigned(PAYLOAD_MEMORY_ADDR_WIDTH-1 downto 0); + signal payload_wen_a, payload_wen_b : std_logic; + signal payload_ren_a, payload_ren_b : std_logic; + signal payload_read_data_a, payload_read_data_b : std_logic_vector(WORD_WIDTH-1 downto 0); + signal payload_write_data_a, payload_write_data_b : std_logic_vector(WORD_WIDTH-1 downto 0); - signal inst_addr_a, inst_addr_a_next : unsigned(PAYLOAD_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); - signal inst_addr_b, inst_addr_b_next : unsigned(PAYLOAD_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); - signal inst_wen_a, inst_wen_b : std_logic := '0'; - signal inst_ren_a, inst_ren_b : std_logic := '0'; - signal inst_read_data_a, inst_read_data_b : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); - signal inst_write_data_a, inst_write_data_b : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); + signal inst_addr_a, inst_addr_a_next : unsigned(PAYLOAD_MEMORY_ADDR_WIDTH-1 downto 0); + signal inst_addr_b, inst_addr_b_next : unsigned(PAYLOAD_MEMORY_ADDR_WIDTH-1 downto 0); + signal inst_wen_a, inst_wen_b : std_logic; + signal inst_ren_a, inst_ren_b : std_logic; + signal inst_read_data_a, inst_read_data_b : std_logic_vector(WORD_WIDTH-1 downto 0); + signal inst_write_data_a, inst_write_data_b : std_logic_vector(WORD_WIDTH-1 downto 0); - signal khg_valid_in, khg_ready_in, khg_last_word_in, khg_valid_out, khg_ready_out, khg_last_word_out : std_logic := '0'; - signal khg_data_in, khg_data_out : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); + signal khg_valid_in, khg_ready_in, khg_last_word_in, khg_valid_out, khg_ready_out, khg_last_word_out : std_logic; + signal khg_data_in, khg_data_out : std_logic_vector(WORD_WIDTH-1 downto 0); - signal stage_a, stage_a_next : STAGE_TYPE := IDLE; - signal cnt_a, cnt_a_next : natural range TODO := 0; - signal empty_sample_list_head, empty_sample_list_head_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); - signal empty_sample_list_tail, empty_sample_list_tail_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); - signal empty_payload_list_head, empty_payload_list_head_next : unsigned(PAYLOAD_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); - signal empty_payload_list_tail, empty_payload_list_tail_next : unsigned(PAYLOAD_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); - signal oldest_sample, oldest_sample_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); - signal newest_sample, newest_sample_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); - signal first_unread_sample, first_unread_sample_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); - signal payload_addr_latch_1, payload_addr_latch_1_next : unsigned(PAYLOAD_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); - signal payload_addr_latch_2, payload_addr_latch_2_next : unsigned(PAYLOAD_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); - signal sample_addr_latch_1, sample_addr_latch_1_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); - signal sample_addr_latch_2, sample_addr_latch_2_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); - signal ts_latch, ts_latch_next : TIME_TYPE := TIME_INVALID; - signal long_latch, long_latch_next : std_logic_vector(CDR_LONG_WIDTH-1 downto 0) := (others => '0'); - signal payload_mem_full, payload_mem_full_next : std_logic := '0'; - signal sample_mem_full, sample_mem_full_next : std_logic := '0'; - signal writer_pos, writer_pos_next : natural range TODO := 0; + signal stage_a, stage_a_next : STAGE_TYPE; + signal cnt_a, cnt_a_next : natural range TODO; + signal empty_sample_list_head, empty_sample_list_head_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0); + signal empty_sample_list_tail, empty_sample_list_tail_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0); + signal empty_payload_list_head, empty_payload_list_head_next : unsigned(PAYLOAD_MEMORY_ADDR_WIDTH-1 downto 0); + signal empty_payload_list_tail, empty_payload_list_tail_next : unsigned(PAYLOAD_MEMORY_ADDR_WIDTH-1 downto 0); + signal oldest_sample, oldest_sample_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0); + signal newest_sample, newest_sample_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0); + signal first_unread_sample, first_unread_sample_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0); + signal payload_addr_latch_1, payload_addr_latch_1_next : unsigned(PAYLOAD_MEMORY_ADDR_WIDTH-1 downto 0); + signal payload_addr_latch_2, payload_addr_latch_2_next : unsigned(PAYLOAD_MEMORY_ADDR_WIDTH-1 downto 0); + signal sample_addr_latch_1, sample_addr_latch_1_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0); + signal sample_addr_latch_2, sample_addr_latch_2_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0); + signal ts_latch, ts_latch_next : TIME_TYPE; + signal long_latch, long_latch_next : std_logic_vector(CDR_LONG_WIDTH-1 downto 0); + signal payload_mem_full, payload_mem_full_next : std_logic; + signal sample_mem_full, sample_mem_full_next : std_logic; + signal writer_pos, writer_pos_next : natural range TODO; signal writer_bitmap : ENDPOINT_BITMAP_ARRAY_TYPE; - signal instance_state : INSTANCE_STATE_TYPE := ALIVE; - signal key_hash, key_hash_next : KEY_HASH_TYPE := (others => (others => '0')); - signal od_instance_sample_removal : std_logic := '0'; - signal od_oldest_sample_removal : std_logic := '0'; - signal od_sample_removal_done : std_logic := '0'; - signal sample_status_info, sample_status_info_next : std_logic_vector(CDR_LONG_WIDTH-1 downto 0) := (others => '0'); - signal gen_cnt : unsigned(CDR_LONG_WIDTH-1 downto 0) := (others => '0'); - signal deadline : TIME_TYPE := TIME_INVALID; - signal release_inst_lock : std_logic := '0'; + signal instance_state : INSTANCE_STATE_TYPE; + signal key_hash, key_hash_next : KEY_HASH_TYPE; + signal od_instance_sample_removal : std_logic; + signal od_oldest_sample_removal : std_logic; + signal od_sample_removal_done : std_logic; + signal sample_status_info, sample_status_info_next : std_logic_vector(CDR_LONG_WIDTH-1 downto 0); + signal gen_cnt : unsigned(CDR_LONG_WIDTH-1 downto 0); + signal deadline : TIME_TYPE; + signal release_inst_lock : std_logic; - signal inst_op_start_a : std_logic := '0'; - signal inst_op_done_a : std_logic := '0'; - signal inst_opcode_a : INSTANCE_OPCODE_TYPE := NOP; - signal inst_stage_a, inst_stage_a_next : INST_STAGE_TYPE := IDLE; - signal inst_addr_base_a, inst_addr_base_a_next : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); - signal inst_addr_base_a, inst_addr_base_a_next : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); - signal inst_next_addr_base_a, inst_next_addr_base_a_next : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); - signal inst_prev_addr_base_a, inst_prev_addr_base_a_next : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); - signal inst_empty_head, inst_empty_head_next : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); - signal inst_occupied_tail, inst_occupied_tail_next : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); - signal inst_latch_data, inst_latch_data_next : INST_LATCH_DATA_TYPE := ZERO_INST_LATCH_DATA; - signal update_inst_flags_a : std_logic_vector(0 to UPDATE_INSTANCE_FLAG_WIDTH-1) := (others => '0'); - signal inst_cnt_a, inst_cnt_a_next : natural range TODO := 0; - signal inst_mem_full, inst_mem_full_next : std_logic := '0'; - signal inst_delete_lock_a, inst_delete_lock_a_next : std_logic := '0'; - signal inst_atomic_lock_a : std_logic := '0'; - signal inst_long_latch_a, inst_long_latch_a_next : std_logic_vector(CDR_LONG_WIDTH-1 downto 0) := (others => '0'); + signal inst_op_start_a : std_logic; + signal inst_op_done_a : std_logic; + signal inst_opcode_a : INSTANCE_OPCODE_TYPE; + signal inst_stage_a, inst_stage_a_next : INST_STAGE_TYPE; + signal inst_addr_base_a, inst_addr_base_a_next : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0); + signal inst_addr_base_a, inst_addr_base_a_next : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0); + signal inst_next_addr_base_a, inst_next_addr_base_a_next : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0); + signal inst_prev_addr_base_a, inst_prev_addr_base_a_next : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0); + signal inst_empty_head, inst_empty_head_next : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0); + signal inst_occupied_tail, inst_occupied_tail_next : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0); + signal inst_latch_data, inst_latch_data_next : INST_LATCH_DATA_TYPE; + signal update_inst_flags_a : std_logic_vector(0 to UPDATE_INSTANCE_FLAG_WIDTH-1); + signal inst_cnt_a, inst_cnt_a_next : natural range TODO; + signal inst_mem_full, inst_mem_full_next : std_logic; + signal inst_delete_lock_a, inst_delete_lock_a_next : std_logic; + signal inst_atomic_lock_a : std_logic; + signal inst_long_latch_a, inst_long_latch_a_next : std_logic_vector(CDR_LONG_WIDTH-1 downto 0); --*****ALIAS DECLARATION***** alias prev_sample : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) is sample_addr_latch_1; @@ -301,9 +301,9 @@ begin ); parse_a_prc : process (all) - variable tmp_dw : DOUBLE_WORD_ARRAY := (others => (others => '0')); - variable tmp_bitmap : std_logic_vector(0 to ENDPOINT_BITMAP_WIDTH-1) := (others => '0'); - variable tmp_update : std_logic_vector(0 to UPDATE_INSTANCE_FLAG_WIDTH-1) := (others => '0'); + variable tmp_dw : DOUBLE_WORD_ARRAY; + variable tmp_bitmap : std_logic_vector(0 to ENDPOINT_BITMAP_WIDTH-1); + variable tmp_update : std_logic_vector(0 to UPDATE_INSTANCE_FLAG_WIDTH-1); begin -- Default stage_a_next <= stage_a; diff --git a/src/ipv4_in_handler.vhd b/src/ipv4_in_handler.vhd index 827979b..a562a3a 100644 --- a/src/ipv4_in_handler.vhd +++ b/src/ipv4_in_handler.vhd @@ -123,49 +123,49 @@ architecture with_frag of ipv4_in_handler is --*****SIGNAL DECLARATION***** -- FSM state - signal stage, stage_next : PARSER_STAGE_TYPE := IPv4_INIT; + signal stage, stage_next : PARSER_STAGE_TYPE; -- 32-bit aligned total packet length - signal packet_length, packet_length_next : unsigned(13 downto 0) := (others => '0'); + signal packet_length, packet_length_next : unsigned(13 downto 0); -- 32-bit aligned header length - signal header_length, header_length_next : unsigned(3 downto 0) := (others => '0'); + signal header_length, header_length_next : unsigned(3 downto 0); -- 32-bit word counter (Counts words read from input fifo) - signal read_cnt : unsigned(13 downto 0) := (others => '0'); + signal read_cnt : unsigned(13 downto 0); -- Intermediate input read signal. (Read from output port not allowed) - signal rd_sig : std_logic := '0'; + signal rd_sig : std_logic; -- States if the current processed packet is a fragment - signal is_fragment, is_fragment_next : std_logic := '0'; + signal is_fragment, is_fragment_next : std_logic; -- States if the current processed packet is the last fragment (Needed to determine total payload size) - signal is_last_fragment, is_last_fragment_next : std_logic := '0'; + signal is_last_fragment, is_last_fragment_next : std_logic; -- Clock with 1 Hz Frequency - signal sec_clk : std_logic := '0'; + signal sec_clk : std_logic; -- Counter used to generate 'sec_clk' - signal sec_cnt : integer range 0 to (CLK_FREQ/2)-1 := 0; + signal sec_cnt : integer range 0 to (CLK_FREQ/2)-1; -- ID of current output fifo (Used to MUX output FIFOs) - signal output_id, output_id_next : integer range 0 to LAYER3_PROTOCOL_NUM-1 := 0; + signal output_id, output_id_next : integer range 0 to LAYER3_PROTOCOL_NUM-1; -- Buffer Identifiers for each buffer. See 'BUFFER_ID_ARRAY' - signal buffer_id, buffer_id_next : BUFFER_ID_ARRAY := (others => (others => '0')); + signal buffer_id, buffer_id_next : BUFFER_ID_ARRAY; -- Used as Constant. See 'BUFFER_ADDR_OFFSET_TYPE' - signal buffer_addr_offset : BUFFER_ADDR_OFFSET_TYPE := (others => (others => '0')); + signal buffer_addr_offset : BUFFER_ADDR_OFFSET_TYPE; -- Bitmap array. See 'BUFFER_BITMAP_ARRAY' - signal buffer_bitmap, buffer_bitmap_next : BUFFER_BITMAP_ARRAY := (others => (others => '0')); + signal buffer_bitmap, buffer_bitmap_next : BUFFER_BITMAP_ARRAY; -- 32-bit word aligned fragment offset - signal frag_offset, frag_offset_next : unsigned(13 downto 0) := (others => '0'); + signal frag_offset, frag_offset_next : unsigned(13 downto 0); -- Packet size array. See 'FRAG_SIZE_ARRAY' - signal frag_size, frag_size_next : FRAG_SIZE_ARRAY := (others => (others => '0')); + signal frag_size, frag_size_next : FRAG_SIZE_ARRAY; -- TimeToLive temporary storage signal ttl, ttl_next : std_logic_vector(7 downto 0); -- Buffer Timers. See 'BUFFER_TIMER_ARRAY' - signal buffer_timer : BUFFER_TIMER_ARRAY := (others => (others => '0')); + signal buffer_timer : BUFFER_TIMER_ARRAY; -- Received fragment word counters. See BUFFER_WORD_COUNTER_ARRAY - signal buffer_word_cnt, buffer_word_cnt_next : BUFFER_WORD_COUNTER_ARRAY := (others => 0); + signal buffer_word_cnt, buffer_word_cnt_next : BUFFER_WORD_COUNTER_ARRAY; -- Timeout values of buffer timers - signal max_buffer_timer, max_buffer_timer_next : BUFFER_TIMER_ARRAY := (others => (others => '0')); + signal max_buffer_timer, max_buffer_timer_next : BUFFER_TIMER_ARRAY; -- Signal used to reset buffer timers - signal reset_buffer_timer : std_logic := '0'; + signal reset_buffer_timer : std_logic; -- ID of buffer timer to be reset - signal reset_buffer_timer_id : integer range 0 to MAX_PARALLEL_FRAG-1 := 0; + signal reset_buffer_timer_id : integer range 0 to MAX_PARALLEL_FRAG-1; -- ID of current buffer - signal cur_buffer_id, cur_buffer_id_next : integer range 0 to MAX_PARALLEL_FRAG-1 := 0; + signal cur_buffer_id, cur_buffer_id_next : integer range 0 to MAX_PARALLEL_FRAG-1; -- Signal used to reset the word counter signal reset_read_cnt : std_logic; -- Intermediate output signal @@ -173,11 +173,11 @@ architecture with_frag of ipv4_in_handler is -- Intermediate output signal, and its 1 clk cycle delayed variant signal wr_sig, wr_sig_del : std_logic; -- RAM Signals - signal buffer_addr, buffer_addr_next : unsigned(RAM_ADDR_WIDTH-1 downto 0) := (others => '0'); - signal buffer_wen, buffer_ren : std_logic := '0'; - signal buffer_wr_data, buffer_rd_data : std_logic_vector(31 downto 0) := (others => '0'); + signal buffer_addr, buffer_addr_next : unsigned(RAM_ADDR_WIDTH-1 downto 0); + signal buffer_wen, buffer_ren : std_logic; + signal buffer_wr_data, buffer_rd_data : std_logic_vector(31 downto 0); -- Old RAM Address (Used to reset address on read error) - signal buffer_addr_old, buffer_addr_old_next : unsigned(RAM_ADDR_WIDTH-1 downto 0) := (others => '0'); + signal buffer_addr_old, buffer_addr_old_next : unsigned(RAM_ADDR_WIDTH-1 downto 0); --*****ALIAS DEFINATION***** @@ -308,8 +308,8 @@ begin -- SKIP_HEADER Skip to beginning of Payload in input FIFO -- SKIP_PACKET Skip to end of packet in input FIFO parser_prc : process(all) - variable tmp : integer range 0 to max(MAX_PARALLEL_FRAG,LAYER3_PROTOCOL_NUM) := 0; - variable tmp_frag_offset : unsigned(buffer_addr'length-1 downto 0) := (others => '0'); + variable tmp : integer range 0 to max(MAX_PARALLEL_FRAG,LAYER3_PROTOCOL_NUM); + variable tmp_frag_offset : unsigned(buffer_addr'length-1 downto 0); begin --DEFAULT Registered stage_next <= stage; @@ -782,17 +782,17 @@ architecture no_frag of ipv4_in_handler is --*****SIGNAL DECLARATION***** -- FSM state - signal stage, stage_next : PARSER_STAGE_TYPE := IPv4_INIT; + signal stage, stage_next : PARSER_STAGE_TYPE; -- 32-bit aligned total packet length - signal packet_length, packet_length_next : unsigned(13 downto 0) := (others => '0'); + signal packet_length, packet_length_next : unsigned(13 downto 0); -- 32-bit aligned header length - signal header_length, header_length_next : unsigned(3 downto 0) := (others => '0'); + signal header_length, header_length_next : unsigned(3 downto 0); -- 32-bit word counter (Counts words read from input fifo) - signal read_cnt : unsigned(13 downto 0) := (others => '0'); + signal read_cnt : unsigned(13 downto 0); -- Intermediate input read signal. (Read from output port not allowed) - signal rd_sig : std_logic := '0'; + signal rd_sig : std_logic; -- ID of current output fifo (Used to MUX output FIFOs) - signal output_id, output_id_next : integer range 0 to LAYER3_PROTOCOL_NUM-1 := 0; + signal output_id, output_id_next : integer range 0 to LAYER3_PROTOCOL_NUM-1; -- Signal used to reset the word counter signal reset_read_cnt : std_logic; -- Intermediate output signal @@ -853,7 +853,7 @@ begin -- SKIP_HEADER Skip to beginning of Payload in input FIFO -- SKIP_PACKET Skip to end of packet in input FIFO parser_prc : process(all) - variable tmp : integer range 0 to max(MAX_PARALLEL_FRAG,LAYER3_PROTOCOL_NUM) := 0; + variable tmp : integer range 0 to max(MAX_PARALLEL_FRAG,LAYER3_PROTOCOL_NUM); begin --DEFAULT Registered stage_next <= stage; diff --git a/src/mem_ctrl.vhd b/src/mem_ctrl.vhd index 64c7de2..d04fd19 100644 --- a/src/mem_ctrl.vhd +++ b/src/mem_ctrl.vhd @@ -34,11 +34,11 @@ architecture arch of mem_ctrl is -- *SIGNAL DECLARATION* signal mem_read_data : std_logic_vector(DATA_WIDTH-1 downto 0); - signal delay_line : std_logic_vector(READ_LATENCY-1 downto 0) := (others => '0'); - signal fifo_empty : std_logic := '0'; - signal fifo_cnt : natural range 0 to MAX_BURST_LENGTH := 0; - signal delay_cnt : natural range 0 to READ_LATENCY := 0; - signal ready_in_sig, valid_out_sig : std_logic := '0'; + signal delay_line : std_logic_vector(READ_LATENCY-1 downto 0); + signal fifo_empty : std_logic; + signal fifo_cnt : natural range 0 to MAX_BURST_LENGTH; + signal delay_cnt : natural range 0 to READ_LATENCY; + signal ready_in_sig, valid_out_sig : std_logic; begin diff --git a/src/rtps_builtin_endpoint.vhd b/src/rtps_builtin_endpoint.vhd index 5ac0208..be2f57d 100644 --- a/src/rtps_builtin_endpoint.vhd +++ b/src/rtps_builtin_endpoint.vhd @@ -228,177 +228,177 @@ architecture arch of rtps_builtin_endpoint is --*****SIGNAL DECLARATION***** -- FSM state - signal stage, stage_next : STAGE_TYPE := IDLE; + signal stage, stage_next : STAGE_TYPE; -- FSM state latch. Used to transition dynamically to different states from the same state. - signal return_stage, return_stage_next : STAGE_TYPE := IDLE; + signal return_stage, return_stage_next : STAGE_TYPE; -- Intermediate input read signal. (Read from output port not allowed) - signal rd_sig : std_logic := '0'; + signal rd_sig : std_logic; -- Signal used to reset the word counter signal reset_read_cnt : std_logic; -- Word (4-Byte) counter (Counts words read from input fifo) - signal read_cnt : unsigned(SUBMESSAGE_LENGTH_WIDTH-3 downto 0) := (others => '0'); + signal read_cnt : unsigned(SUBMESSAGE_LENGTH_WIDTH-3 downto 0); -- RTPS Submessage ID Latch - signal opcode, opcode_next : std_logic_vector(SUBMESSAGE_ID_WIDTH-1 downto 0) := (others => '0'); + signal opcode, opcode_next : std_logic_vector(SUBMESSAGE_ID_WIDTH-1 downto 0); -- RTPS Submessage Flags Latch - signal flags, flags_next : std_logic_vector(SUBMESSAGE_FLAGS_WIDTH-1 downto 0) := (others => '0'); + signal flags, flags_next : std_logic_vector(SUBMESSAGE_FLAGS_WIDTH-1 downto 0); -- UDPv4 Source Port Latch - signal src_port, src_port_next : std_logic_vector(UDP_PORT_WIDTH-1 downto 0) := (others => '0'); + signal src_port, src_port_next : std_logic_vector(UDP_PORT_WIDTH-1 downto 0); -- IPv4 Source Address Latch - signal src_addr, src_addr_next : std_logic_vector(IPv4_ADDRESS_WIDTH-1 downto 0) := (others => '0'); + signal src_addr, src_addr_next : std_logic_vector(IPv4_ADDRESS_WIDTH-1 downto 0); -- Source Entity ID Latch - signal src_entityid, src_entityid_next : std_logic_vector(ENTITYID_WIDTH-1 downto 0) := (others => '0'); + signal src_entityid, src_entityid_next : std_logic_vector(ENTITYID_WIDTH-1 downto 0); -- Destination Entity ID Latch - signal dest_entityid, dest_entityid_next : std_logic_vector(ENTITYID_WIDTH-1 downto 0) := (others => '0'); + signal dest_entityid, dest_entityid_next : std_logic_vector(ENTITYID_WIDTH-1 downto 0); -- Source GUID Latch - signal guid, guid_next : GUID_TYPE := (others => (others => '0')); + signal guid, guid_next : GUID_TYPE; -- RTPS DATA Submessage Sequence Number Latch - signal seq_nr, seq_nr_next : SEQUENCENUMBER_TYPE := (others => (others => '0')); + signal seq_nr, seq_nr_next : SEQUENCENUMBER_TYPE; -- Word aligned End of Parameter - signal parameter_end, parameter_end_next : unsigned(PARAMETER_LENGTH_WIDTH-1 downto 0) := (others => '0'); + signal parameter_end, parameter_end_next : unsigned(PARAMETER_LENGTH_WIDTH-1 downto 0); -- RTPS DATA Submessage Content Type - signal message_type, message_type_next : MESSAGE_TYPE_TYPE := NONE; + signal message_type, message_type_next : MESSAGE_TYPE_TYPE; -- Data in represented in Big Endian - signal data_in_swapped : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); + signal data_in_swapped : std_logic_vector(WORD_WIDTH-1 downto 0); -- Byte Length of string - signal string_length, string_length_next : unsigned(WORD_WIDTH-1 downto 0) := (others => '0'); + signal string_length, string_length_next : unsigned(WORD_WIDTH-1 downto 0); -- Counter of compared string words (4-Byte) - signal compare_length, compare_length_next : unsigned(WORD_WIDTH-3 downto 0) := (others => '0'); + signal compare_length, compare_length_next : unsigned(WORD_WIDTH-3 downto 0); -- Bitmask of local Endpoint Matches - signal endpoint_mask, endpoint_mask_next : std_logic_vector(0 to NUM_ENDPOINTS-1) := (others => '0'); + signal endpoint_mask, endpoint_mask_next : std_logic_vector(0 to NUM_ENDPOINTS-1); -- Signifies if the source of the Participant Data is compatible with our Participant - signal participant_match, participant_match_next : std_logic := '0'; + signal participant_match, participant_match_next : std_logic; -- Signifies if the Packet is comming from a Subscriber Endpoint - signal is_subscriber, is_subscriber_next : std_logic := '0'; + signal is_subscriber, is_subscriber_next : std_logic; -- Signifies that the read Locator is a Metatraffic Locator - signal is_meta_addr, is_meta_addr_next : std_logic := '0'; + signal is_meta_addr, is_meta_addr_next : std_logic; -- General Purpose counter - signal cnt, cnt_next : natural range 0 to max(23, STRING_WORD_ARRAY_TYPE'length) := 0; + signal cnt, cnt_next : natural range 0 to max(23, STRING_WORD_ARRAY_TYPE'length); -- NOTE: In order to avoid synthesizing indexing for the full range of the OUTPUT_DATA_TYPE, we explicitly use counters constrained to the actual size -- Counter used to index the Participant Data - signal participant_data_cnt, participant_data_cnt_next : natural range 0 to LOCAL_PARTICIPANT_DATA.length-1 := 0; + signal participant_data_cnt, participant_data_cnt_next : natural range 0 to LOCAL_PARTICIPANT_DATA.length-1; -- Counter used to index the Publisher Data - signal publisher_data_cnt, publisher_data_cnt_next : natural range 0 to work.math_pkg.max(WRITER_ENDPOINT_DATA.length-1, 0) := 0; + signal publisher_data_cnt, publisher_data_cnt_next : natural range 0 to work.math_pkg.max(WRITER_ENDPOINT_DATA.length-1, 0); -- Counter used to index the Subscriber Data - signal subscriber_data_cnt, subscriber_data_cnt_next : natural range 0 to work.math_pkg.max(READER_ENDPOINT_DATA.length-1, 0) := 0; + signal subscriber_data_cnt, subscriber_data_cnt_next : natural range 0 to work.math_pkg.max(READER_ENDPOINT_DATA.length-1, 0); -- Signifies the next expected Sequence Number of the current relevant Message Type (Participant/Publisher/Subscriber/Message Data) - signal next_seq_nr, next_seq_nr_next : SEQUENCENUMBER_TYPE := SEQUENCENUMBER_UNKNOWN; + signal next_seq_nr, next_seq_nr_next : SEQUENCENUMBER_TYPE; -- Generic Sequence Number Latch - signal sn_latch_1, sn_latch_1_next : SEQUENCENUMBER_TYPE := SEQUENCENUMBER_UNKNOWN; + signal sn_latch_1, sn_latch_1_next : SEQUENCENUMBER_TYPE; -- Generic Sequence Number Latch - signal sn_latch_2, sn_latch_2_next : SEQUENCENUMBER_TYPE := SEQUENCENUMBER_UNKNOWN; + signal sn_latch_2, sn_latch_2_next : SEQUENCENUMBER_TYPE; -- Generic Sequence Number Latch - signal sn_latch_3, sn_latch_3_next : SEQUENCENUMBER_TYPE := SEQUENCENUMBER_UNKNOWN; + signal sn_latch_3, sn_latch_3_next : SEQUENCENUMBER_TYPE; -- Intermediate write enable signal. - signal wr_sig : std_logic := '0'; + signal wr_sig : std_logic; -- Signifies if a Stale Endpoint Check is in progress - signal stale_check, stale_check_next : std_logic := '0'; + signal stale_check, stale_check_next : std_logic; -- Time of next Stale Endpoint Check - signal check_time, check_time_next : TIME_TYPE := TIME_INVALID; + signal check_time, check_time_next : TIME_TYPE; -- Toggle latching the "last_word_in" signal until reset - signal last_word_in_latch, last_word_in_latch_next : std_logic := '0'; + signal last_word_in_latch, last_word_in_latch_next : std_logic; -- Signal containing the HEARTBEAT/ACKNACK count of all built-in Endpoints - signal count, count_next : unsigned(COUNT_WIDTH-1 downto 0) := (others => '0'); + signal count, count_next : unsigned(COUNT_WIDTH-1 downto 0); -- Toggle set when at least one Endpoint has asserted the "alive" signal, until reset - signal endpoint_alive : std_logic := '0'; + signal endpoint_alive : std_logic; -- Resets the "endpoint_alive" signal - signal reset_endpoint_alive : std_logic := '0'; + signal reset_endpoint_alive : std_logic; -- NOTE: The "auto_live_seq_nr" is always higher than "man_live_seq_nr" -- Contains the highest Sequence Number for automatic liveliness updates - signal auto_live_seq_nr, auto_live_seq_nr_next : SEQUENCENUMBER_TYPE := (others => (others => '0')); + signal auto_live_seq_nr, auto_live_seq_nr_next : SEQUENCENUMBER_TYPE; -- Contains the highest Sequence Number for manual by participant liveliness updates - signal man_live_seq_nr, man_live_seq_nr_next : SEQUENCENUMBER_TYPE := (others => (others => '0')); + signal man_live_seq_nr, man_live_seq_nr_next : SEQUENCENUMBER_TYPE; -- Points to the first Sequence Number after "man_live_seq_nr" (Signifies the start of the GAP between "man_live_seq_nr" and "auto_live_seq_nr") - signal live_gap_start, live_gap_start_next : SEQUENCENUMBER_TYPE := (others => (others => '0')); + signal live_gap_start, live_gap_start_next : SEQUENCENUMBER_TYPE; -- Points to the first Sequence Number before "auto_live_seq_nr" (Signifies the end of the GAP between "man_live_seq_nr" and "auto_live_seq_nr") - signal live_gap_end, live_gap_end_next : SEQUENCENUMBER_TYPE := (others => (others => '0')); + signal live_gap_end, live_gap_end_next : SEQUENCENUMBER_TYPE; -- Denotes the number of valid Bitmap longs (4-Byte words) - signal bitmap_cnt, bitmap_cnt_next : unsigned(log2c(MAX_BITMAP_WIDTH/CDR_LONG_WIDTH)-1 downto 0) := (others => '0'); + signal bitmap_cnt, bitmap_cnt_next : unsigned(log2c(MAX_BITMAP_WIDTH/CDR_LONG_WIDTH)-1 downto 0); -- NumberSet Bitmap Latch - signal bitmap_latch, bitmap_latch_next : BITMAP_TYPE := (others => (others => '0')); + signal bitmap_latch, bitmap_latch_next : BITMAP_TYPE; -- Counter used to read out Bitmaps - signal cnt2, cnt2_next : natural range 0 to BITMAP_TYPE'length := 0; + signal cnt2, cnt2_next : natural range 0 to BITMAP_TYPE'length; -- Signal used to iterate through Bitmaps - signal bitmap_pos, bitmap_pos_next : natural range 0 to MAX_BITMAP_WIDTH-1 := 0; + signal bitmap_pos, bitmap_pos_next : natural range 0 to MAX_BITMAP_WIDTH-1; -- Participant Announcement Timeout Time - signal announcement_time, announcement_time_next : TIME_TYPE := (others => (others => '0')); + signal announcement_time, announcement_time_next : TIME_TYPE; -- Heartbeat/Liveliness Assertion Timeout Time - signal heartbeat_time, heartbeat_time_next : TIME_TYPE := (others => (others => '0')); + signal heartbeat_time, heartbeat_time_next : TIME_TYPE; -- Signifies if we are currently in a Liveliness Assertion - signal is_live_assert, is_live_assert_next : std_logic := '0'; + signal is_live_assert, is_live_assert_next : std_logic; -- Signifies the content of the string read from input - signal string_content, string_content_next : STRING_CONTENT_TYPE := TOPIC_NAME_TYPE; + signal string_content, string_content_next : STRING_CONTENT_TYPE; -- Reader Flags of remote Reader - signal reader_flags, reader_flags_next : std_logic_vector(READER_FLAGS_WIDTH-1 downto 0) := (others => '0'); + signal reader_flags, reader_flags_next : std_logic_vector(READER_FLAGS_WIDTH-1 downto 0); -- Endpoint Locator IPv4 Address Latch - signal def_addr, def_addr_next : std_logic_vector(IPv4_ADDRESS_WIDTH-1 downto 0) := (others => '0'); + signal def_addr, def_addr_next : std_logic_vector(IPv4_ADDRESS_WIDTH-1 downto 0); -- Metatraffic Locator IPv4 Address Latch - signal meta_addr, meta_addr_next : std_logic_vector(IPv4_ADDRESS_WIDTH-1 downto 0) := (others => '0'); + signal meta_addr, meta_addr_next : std_logic_vector(IPv4_ADDRESS_WIDTH-1 downto 0); -- Endpoint UDPv4 Port Latch - signal def_port, def_port_next : std_logic_vector(UDP_PORT_WIDTH-1 downto 0) := (others => '0'); + signal def_port, def_port_next : std_logic_vector(UDP_PORT_WIDTH-1 downto 0); -- Metatraffic UDPv4 Port Latch - signal meta_port, meta_port_next : std_logic_vector(UDP_PORT_WIDTH-1 downto 0) := (others => '0'); + signal meta_port, meta_port_next : std_logic_vector(UDP_PORT_WIDTH-1 downto 0); -- Participant Lease Duration Latch - signal lease_duration, lease_duration_next : DURATION_TYPE := (others => (others => '0')); + signal lease_duration, lease_duration_next : DURATION_TYPE; -- General Purpose Long latch - signal long_latch, long_latch_next : std_logic_vector(CDR_LONG_WIDTH-1 downto 0) := (others => '0'); + signal long_latch, long_latch_next : std_logic_vector(CDR_LONG_WIDTH-1 downto 0); -- Contains flags that signify which PIDs where received. This is done in order to use the default value for -- not received elements. - signal rcvd, rcvd_next : std_logic_vector(RCVD_FLAG_WIDTH-1 downto 0) := (others => '0'); + signal rcvd, rcvd_next : std_logic_vector(RCVD_FLAG_WIDTH-1 downto 0); -- Signal containing the relevant Participant Memory Frame Fields of the Memory Operation signal mem_field_flags : std_logic_vector(0 to PMF_FLAG_WIDTH-1) := (others => '0'); -- Signal used to pass deadlines to the Memory FSM - signal deadline : TIME_TYPE := TIME_INVALID; + signal deadline : TIME_TYPE; -- Signal used to pass extra flags to the Memory FSM - signal extra_flags : std_logic_vector(0 to EF_FLAG_WIDTH-1) := (others => '0'); + signal extra_flags : std_logic_vector(0 to EF_FLAG_WIDTH-1); -- Signal used to pass Participant Pointers to the Memory Process - signal mem_addr_update : unsigned(PARTICIPANT_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); + signal mem_addr_update : unsigned(PARTICIPANT_MEMORY_ADDR_WIDTH-1 downto 0); -- Signal used to be pass Response Times to the Memory FSM - signal res_time : TIME_TYPE := TIME_INVALID; + signal res_time : TIME_TYPE; -- Test signal used for testbench synchronisation - signal idle_sig : std_logic := '0'; + signal idle_sig : std_logic; -- Signifies that we received an Unregister/Dispose Status Info - signal ud_status, ud_status_next : std_logic := '0'; + signal ud_status, ud_status_next : std_logic; -- Internal Signal for data_out - signal data_out_sig : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); + signal data_out_sig : std_logic_vector(WORD_WIDTH-1 downto 0); -- Internal Signal for last_word_out - signal last_word_out_sig : std_logic := '0'; + signal last_word_out_sig : std_logic; -- *MEMORY PROCESS* -- Memory FSM State - signal mem_stage, mem_stage_next : MEM_STAGE_TYPE := IDLE; + signal mem_stage, mem_stage_next : MEM_STAGE_TYPE; -- General Purpose Counter (Memory FSM) - signal mem_cnt, mem_cnt_next : natural range 0 to 46 := 0; + signal mem_cnt, mem_cnt_next : natural range 0 to 46; -- Signals the start of a Memory Operation (Should be pulled high only when mem_op_done is high) - signal mem_op_start : std_logic := '0'; + signal mem_op_start : std_logic; -- Signals the end of a Memory Operation - signal mem_op_done : std_logic := '0'; + signal mem_op_done : std_logic; -- Opcode of the Memory Operation (Valid only when mem_op_start is high) - signal mem_opcode : MEM_OPCODE_TYPE := NOP; + signal mem_opcode : MEM_OPCODE_TYPE; -- Base Memory Address of current Participant Frame - signal mem_addr_base, mem_addr_base_next : unsigned(PARTICIPANT_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); + signal mem_addr_base, mem_addr_base_next : unsigned(PARTICIPANT_MEMORY_ADDR_WIDTH-1 downto 0); -- Pointer to previous Participant Memory Frame Address - signal mem_prev_addr_base, mem_prev_addr_base_next : unsigned(PARTICIPANT_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); + signal mem_prev_addr_base, mem_prev_addr_base_next : unsigned(PARTICIPANT_MEMORY_ADDR_WIDTH-1 downto 0); -- Pointer to next Participant Memory Frame Address - signal mem_next_addr_base, mem_next_addr_base_next : unsigned(PARTICIPANT_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); + signal mem_next_addr_base, mem_next_addr_base_next : unsigned(PARTICIPANT_MEMORY_ADDR_WIDTH-1 downto 0); -- Head of Empty Participant List - signal mem_empty_head, mem_empty_head_next : unsigned(PARTICIPANT_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); + signal mem_empty_head, mem_empty_head_next : unsigned(PARTICIPANT_MEMORY_ADDR_WIDTH-1 downto 0); -- Head of Occupied Participant List - signal mem_occupied_head, mem_occupied_head_next : unsigned(PARTICIPANT_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); + signal mem_occupied_head, mem_occupied_head_next : unsigned(PARTICIPANT_MEMORY_ADDR_WIDTH-1 downto 0); -- Latch for the Participant Data stored in memory - signal participant_data, participant_data_next : PARTICIPANT_DATA_TYPE := ZERO_PARTICIPANT_DATA; + signal participant_data, participant_data_next : PARTICIPANT_DATA_TYPE; -- Latch for Participant Data from main FSM - signal participant_latch_data, participant_latch_data_next : PARTICIPANT_LATCH_DATA_TYPE := ZERO_PARTICIPANT_LATCH_DATA; + signal participant_latch_data, participant_latch_data_next : PARTICIPANT_LATCH_DATA_TYPE; -- Participant Memory Flag Array denoting which participant_data Fields are up-to-date with the respective fields of the Participant (Pointed by mem_addr_base) - signal current_pmf, current_pmf_next : std_logic_vector(0 to PMF_FLAG_WIDTH-1) := (others => '0'); + signal current_pmf, current_pmf_next : std_logic_vector(0 to PMF_FLAG_WIDTH-1); -- *MEMORY CONTROL CONNECTION SIGNALS* - signal mem_addr : unsigned(PARTICIPANT_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); - signal mem_read_data, mem_write_data : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); - signal mem_ready_in, mem_valid_in : std_logic := '0'; - signal mem_ready_out, mem_valid_out : std_logic := '0'; - signal mem_read : std_logic := '0'; - signal mem_abort_read : std_logic := '0'; + signal mem_addr : unsigned(PARTICIPANT_MEMORY_ADDR_WIDTH-1 downto 0); + signal mem_read_data, mem_write_data : std_logic_vector(WORD_WIDTH-1 downto 0); + signal mem_ready_in, mem_valid_in : std_logic; + signal mem_ready_out, mem_valid_out : std_logic; + signal mem_read : std_logic; + signal mem_abort_read : std_logic; --*****ALIAS DEFINATION***** -- ENDPOINT FRAME HEADER @@ -615,13 +615,13 @@ begin -- SKIP_PARAMETER Skip rest of Parameter -- SKIP_PACKET Skip rest of Packet parse_prc: process(all) - variable tmp_endpoint_mask : std_logic_vector(0 to NUM_ENDPOINTS-1) := (others => '0'); - variable rd_guard : std_logic := '0'; - variable tmp_default_qos_match : DEFAULT_QOS_MATCH_TYPE := READER_DEFAULT_QOS_MATCH; - variable tmp_dw : DOUBLE_WORD_ARRAY := (others => (others => '0')); - variable mem_seq_nr : SEQUENCENUMBER_TYPE := SEQUENCENUMBER_UNKNOWN; + variable tmp_endpoint_mask : std_logic_vector(0 to NUM_ENDPOINTS-1); + variable rd_guard : std_logic; + variable tmp_default_qos_match : DEFAULT_QOS_MATCH_TYPE; + variable tmp_dw : DOUBLE_WORD_ARRAY; + variable mem_seq_nr : SEQUENCENUMBER_TYPE; -- NOTE: We convert the bitamp to a slv to make operations easier (The tool should handle both cases equally) - variable tmp_bitmap : std_logic_vector(0 to MAX_BITMAP_WIDTH-1) := (others => '0'); + variable tmp_bitmap : std_logic_vector(0 to MAX_BITMAP_WIDTH-1); begin --DEFAULT Registered stage_next <= stage; diff --git a/src/rtps_handler.vhd b/src/rtps_handler.vhd index 047c1f7..5c237f7 100644 --- a/src/rtps_handler.vhd +++ b/src/rtps_handler.vhd @@ -42,92 +42,92 @@ architecture arch of rtps_handler is --*****SIGNAL DECLARATION***** -- FSM state - signal stage, stage_next : STAGE_TYPE := SRC_ADDR_HEADER; + signal stage, stage_next : STAGE_TYPE; -- Intermediate input read signal. (Read from output port not allowed) - signal rd_sig : std_logic := '0'; + signal rd_sig : std_logic; -- Signal used to reset the 4-Byte Word counter signal reset_read_cnt : std_logic; -- 4-Byte Word counter (Counts words read from input FIFO) - signal read_cnt : unsigned(UDP_HEADER_LENGTH_WIDTH-3 downto 0) := (others => '0'); + signal read_cnt : unsigned(UDP_HEADER_LENGTH_WIDTH-3 downto 0); -- read_cnt + 1 -- NOTE: Because the Submessage Length does not include the Submessage Header, we need a to add +1 to find the end of the Submessage -- In order to prevent two serial additions in the same clock cycle, we use this pre-incremented signal instead - signal read_cnt_plus : unsigned(UDP_HEADER_LENGTH_WIDTH-3 downto 0) := (others => '0'); + signal read_cnt_plus : unsigned(UDP_HEADER_LENGTH_WIDTH-3 downto 0); -- Total packet length (4-Byte Words) - signal packet_length, packet_length_next : unsigned(UDP_HEADER_LENGTH_WIDTH-3 downto 0) := (others => '0'); + signal packet_length, packet_length_next : unsigned(UDP_HEADER_LENGTH_WIDTH-3 downto 0); -- End of Submessage from the beginning of the UDP Packet in 4-Byte Words -- NOTE: We count this in 4-Byte Words, because Submessages always begin in a 4-Byte boundary (DDSI-RTPS 2.3 Section 9.4.1), -- and thus the "sub_end" is always a multiple of four. - signal sub_end, sub_end_next : unsigned(SUBMESSAGE_LENGTH_WIDTH-3 downto 0) := (others => '0'); + signal sub_end, sub_end_next : unsigned(SUBMESSAGE_LENGTH_WIDTH-3 downto 0); -- End of DATA Submessage Sub-Header (Beginning of inlineQoS/Payload) from the beginning of the UDP Packet in Bytes - signal data_header_end, data_header_end_next : unsigned(SUBMESSAGE_LENGTH_WIDTH-1 downto 0) := (others => '0'); + signal data_header_end, data_header_end_next : unsigned(SUBMESSAGE_LENGTH_WIDTH-1 downto 0); -- Input Signal Latch. Used to read 4-Byte aligned from input (see align_prc) - signal align_sig, align_sig_next : std_logic_vector((3*BYTE_WIDTH)-1 downto 0) := (others => '0'); + signal align_sig, align_sig_next : std_logic_vector((3*BYTE_WIDTH)-1 downto 0); -- 4-Byte Aligned Input (see align_prc) signal data_in_aligned : std_logic_vector(WORD_WIDTH-1 downto 0); -- 4-Byte Alignement offset (see align_prc) - signal align_offset, align_offset_next : std_logic_vector(1 downto 0) := (others => '0'); + signal align_offset, align_offset_next : std_logic_vector(1 downto 0); -- 4-Byte Alignement offset latch - signal offset_latch, offset_latch_next : std_logic_vector(1 downto 0) := (others => '0'); + signal offset_latch, offset_latch_next : std_logic_vector(1 downto 0); -- IPv4 Source Address latch - signal src_addr, src_addr_next : std_logic_vector(IPv4_ADDRESS_WIDTH-1 downto 0) := (others => '0'); + signal src_addr, src_addr_next : std_logic_vector(IPv4_ADDRESS_WIDTH-1 downto 0); -- UDP Source Port latch - signal src_port, src_port_next : std_logic_vector(UDP_PORT_WIDTH-1 downto 0) := (others => '0'); + signal src_port, src_port_next : std_logic_vector(UDP_PORT_WIDTH-1 downto 0); -- Denotes if processed Message is Metatraffic - signal is_metatraffic, is_metatraffic_next : std_logic := '0'; + signal is_metatraffic, is_metatraffic_next : std_logic; -- RTPS Submessage Flag latch - signal flags, flags_next : std_logic_vector(SUBMESSAGE_FLAGS_WIDTH-1 downto 0) := (others => '0'); + signal flags, flags_next : std_logic_vector(SUBMESSAGE_FLAGS_WIDTH-1 downto 0); -- Source Entity ID latch - signal src_entityid, src_entityid_next : std_logic_vector(ENTITYID_WIDTH-1 downto 0) := (others => '0'); + signal src_entityid, src_entityid_next : std_logic_vector(ENTITYID_WIDTH-1 downto 0); -- Destination Entity ID latch - signal dest_entityid, dest_entityid_next : std_logic_vector(ENTITYID_WIDTH-1 downto 0) := (others => '0'); + signal dest_entityid, dest_entityid_next : std_logic_vector(ENTITYID_WIDTH-1 downto 0); -- Source GUID Prefix latch - signal src_guidprefix, src_guidprefix_next : GUIDPREFIX_TYPE := (others => (others => '0')); + signal src_guidprefix, src_guidprefix_next : GUIDPREFIX_TYPE; -- Vector denoting the Destination User Endpoints of the Submessage - signal user_endpoints, user_endpoints_next : std_logic_vector(0 to NUM_ENDPOINTS-1) := (others => '0'); + signal user_endpoints, user_endpoints_next : std_logic_vector(0 to NUM_ENDPOINTS-1); -- Denotes if the Message is destined for the Built-in Endpoints - signal builtin_endpoint, builtin_endpoint_next : std_logic := '0'; + signal builtin_endpoint, builtin_endpoint_next : std_logic; -- LocatorList NumLocator latch -- NOTE: Since Submessages are limited to 2^16 Bytes, we can limit this also to 16 bits - signal numlocators, numlocators_next : unsigned(SUBMESSAGE_LENGTH_WIDTH-1 downto 0) := (others => '0'); + signal numlocators, numlocators_next : unsigned(SUBMESSAGE_LENGTH_WIDTH-1 downto 0); -- Denotes if a suitable and valid Locator has been found - signal locator_match, locator_match_next : std_logic := '0'; + signal locator_match, locator_match_next : std_logic; -- Denotes if the Source of the Message is a Reader Endpoint - signal src_is_reader, src_is_reader_next : std_logic := '0'; + signal src_is_reader, src_is_reader_next : std_logic; -- Intermediate Write Enable Signal - signal wr_sig : std_logic := '0'; + signal wr_sig : std_logic; -- Submessage ID latch (Used as OPCODE by Endpoints) - signal opcode, opcode_next : std_logic_vector(SUBMESSAGE_ID_WIDTH-1 downto 0) := (others => '0'); + signal opcode, opcode_next : std_logic_vector(SUBMESSAGE_ID_WIDTH-1 downto 0); -- General Purpose counter - signal cnt, cnt_next : natural range 0 to 10 := 0; + signal cnt, cnt_next : natural range 0 to 10; -- Input in Big Endian representation - signal data_in_swapped : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); + signal data_in_swapped : std_logic_vector(WORD_WIDTH-1 downto 0); -- Sequence Number latch - signal sn_latch_1, sn_latch_1_next : SEQUENCENUMBER_TYPE := (others => (others => '0')); + signal sn_latch_1, sn_latch_1_next : SEQUENCENUMBER_TYPE; -- Sequence Number latch - signal sn_latch_2, sn_latch_2_next : SEQUENCENUMBER_TYPE := (others => (others => '0')); + signal sn_latch_2, sn_latch_2_next : SEQUENCENUMBER_TYPE; -- Sequence Number latch - signal sn_latch_3, sn_latch_3_next : SEQUENCENUMBER_TYPE := (others => (others => '0')); + signal sn_latch_3, sn_latch_3_next : SEQUENCENUMBER_TYPE; -- Long atch - signal long_latch, long_latch_next : std_logic_vector(CDR_LONG_WIDTH-1 downto 0) := (others => '0'); + signal long_latch, long_latch_next : std_logic_vector(CDR_LONG_WIDTH-1 downto 0); -- Unsigned long latch - signal ulong_latch, ulong_latch_next : unsigned(CDR_LONG_WIDTH-1 downto 0) := (others => '0'); + signal ulong_latch, ulong_latch_next : unsigned(CDR_LONG_WIDTH-1 downto 0); -- NumberSet Bitmap latch - signal bitmap_latch, bitmap_latch_next : BITMAP_TYPE := (others => (others => '0')); + signal bitmap_latch, bitmap_latch_next : BITMAP_TYPE; -- Counter used to read out Bitmaps - signal cnt2, cnt2_next : natural range 0 to BITMAP_TYPE'length := 0; + signal cnt2, cnt2_next : natural range 0 to BITMAP_TYPE'length; -- Denotes the number of valid Bitmap longs (4-Byte words) - signal bitmap_cnt, bitmap_cnt_next : unsigned(log2c(MAX_BITMAP_WIDTH/CDR_LONG_WIDTH)-1 downto 0) := (others => '0'); + signal bitmap_cnt, bitmap_cnt_next : unsigned(log2c(MAX_BITMAP_WIDTH/CDR_LONG_WIDTH)-1 downto 0); -- Source Timestamp latch - signal src_ts, src_ts_next : TIME_TYPE := TIME_INVALID; + signal src_ts, src_ts_next : TIME_TYPE; -- Indicates the Destination IP Address - signal ip_addr_type, ip_addr_type_next : IPv4_ADDRESS_TYPE := INVALID; + signal ip_addr_type, ip_addr_type_next : IPv4_ADDRESS_TYPE; -- Alias "substitution" - signal rtps_sub_length, rtps_sub_data_length : unsigned(SUBMESSAGE_LENGTH_WIDTH-1 downto 0) := (others => '0'); + signal rtps_sub_length, rtps_sub_data_length : unsigned(SUBMESSAGE_LENGTH_WIDTH-1 downto 0); -- Internal Signal for data_out - signal data_out_sig : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); + signal data_out_sig : std_logic_vector(WORD_WIDTH-1 downto 0); -- Internal Signal for last_word_out - signal last_word_out_sig : std_logic := '0'; + signal last_word_out_sig : std_logic; --*****ALIAS DEFINATION***** -- UDP HEADER @@ -183,7 +183,7 @@ begin -- We store the lower 2 bits of the octet length (Which denotes the 4-Byte alignment offset), and together -- with the "align_sig" which stores 3 Bytes from the previous input word, we generate our aligned signal. align_prc : process(all) - variable input : std_logic_vector(55 downto 0) := (others => '0'); + variable input : std_logic_vector(55 downto 0); begin input := align_sig & data_in; case(align_offset) is @@ -225,11 +225,11 @@ begin -- SKIP_SUB Skip rest of Submessage -- SKIP_PACKET Skip rest of UDP Packet parse_prc: process(all) - variable tmp : std_logic_vector(0 to NUM_ENDPOINTS-1) := (others => '0'); - variable dest : std_logic_vector(ENTITYID_WIDTH-1 downto 0) := (others => '0'); - variable tmp_sn : SEQUENCENUMBER_TYPE := SEQUENCENUMBER_UNKNOWN; + variable tmp : std_logic_vector(0 to NUM_ENDPOINTS-1); + variable dest : std_logic_vector(ENTITYID_WIDTH-1 downto 0); + variable tmp_sn : SEQUENCENUMBER_TYPE; -- This variable is used to allow the Overread Guard to control the rd Signal - variable rd_guard : std_logic := '0'; + variable rd_guard : std_logic; begin --DEFAULT Registered stage_next <= stage; diff --git a/src/rtps_out.vhd b/src/rtps_out.vhd index 5d73d84..ed6aa6e 100644 --- a/src/rtps_out.vhd +++ b/src/rtps_out.vhd @@ -35,18 +35,18 @@ architecture arch of rtps_out is type OUTPUT_STAGE_TYPE is (IDLE, SRC_ADDR_HEADER, DEST_ADDR_HEADER, PORT_HEADER, PACKET_LENGTH, WRITE); -- *SIGNAL DECLARATION* - signal selector, selector_next : natural range 0 to NUM_ENDPOINTS := 0; - signal buff, buff_next : BUFFER_TYPE := (others => (others => '0')); - signal in_pntr, in_pntr_next : natural range 0 to MAX_BUFFER_SIZE := MAX_BUFFER_SIZE; - signal out_pntr, out_pntr_next : natural range 0 to MAX_BUFFER_SIZE := MAX_BUFFER_SIZE; - signal length, length_next : unsigned(WORD_WIDTH-1 downto 0) := (others => '0'); - signal packet_end, packet_end_next : unsigned(WORD_WIDTH-1 downto 0) := (others => '0'); - signal input_stage, input_stage_next : INPUT_STAGE_TYPE := IDLE; - signal output_stage, output_stage_next : OUTPUT_STAGE_TYPE := IDLE; - signal filled ,reset_filled, set_filled: std_logic := '0'; - signal src_addr, src_addr_next : std_logic_vector(WORD_WIDTH-1 downto 0 ) := (others => '0'); - signal dest_addr, dest_addr_next : std_logic_vector(WORD_WIDTH-1 downto 0 ) := (others => '0'); - signal ports, ports_next : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); + signal selector, selector_next : natural range 0 to NUM_ENDPOINTS; + signal buff, buff_next : BUFFER_TYPE; + signal in_pntr, in_pntr_next : natural range 0 to MAX_BUFFER_SIZE; + signal out_pntr, out_pntr_next : natural range 0 to MAX_BUFFER_SIZE; + signal length, length_next : unsigned(WORD_WIDTH-1 downto 0); + signal packet_end, packet_end_next : unsigned(WORD_WIDTH-1 downto 0); + signal input_stage, input_stage_next : INPUT_STAGE_TYPE; + signal output_stage, output_stage_next : OUTPUT_STAGE_TYPE; + signal filled ,reset_filled, set_filled: std_logic; + signal src_addr, src_addr_next : std_logic_vector(WORD_WIDTH-1 downto 0); + signal dest_addr, dest_addr_next : std_logic_vector(WORD_WIDTH-1 downto 0); + signal ports, ports_next : std_logic_vector(WORD_WIDTH-1 downto 0); begin diff --git a/src/rtps_reader.vhd b/src/rtps_reader.vhd index 756be43..5b110d8 100644 --- a/src/rtps_reader.vhd +++ b/src/rtps_reader.vhd @@ -175,117 +175,117 @@ architecture arch of rtps_reader is --*****SIGNAL DECLARATION***** -- *MAIN PROCESS* -- FSM state - signal stage, stage_next : STAGE_TYPE := IDLE; + signal stage, stage_next : STAGE_TYPE; -- FSM state latch. Used to transition dynamically to different states from the same state. - signal return_stage, return_stage_next : STAGE_TYPE := IDLE; + signal return_stage, return_stage_next : STAGE_TYPE; -- Intermediate input read signal. (Read from output port not allowed) - signal rd_sig : std_logic := '0'; + signal rd_sig : std_logic; -- Signal used to reset the word counter signal reset_read_cnt : std_logic; -- Word (4-Byte) counter (Counts words read from input fifo) - signal read_cnt : unsigned(SUBMESSAGE_LENGTH_WIDTH-3 downto 0) := (others => '0'); + signal read_cnt : unsigned(SUBMESSAGE_LENGTH_WIDTH-3 downto 0); -- Word aligned End of Parameter - signal parameter_end, parameter_end_next : unsigned(PARAMETER_LENGTH_WIDTH-1 downto 0) := (others => '0'); + signal parameter_end, parameter_end_next : unsigned(PARAMETER_LENGTH_WIDTH-1 downto 0); -- General Purpose Counter - signal cnt, cnt_next : natural range 0 to 9 := 0; + signal cnt, cnt_next : natural range 0 to 9; -- Packet Opcode Latch (RTPS Message ID) - signal opcode, opcode_next : std_logic_vector(SUBMESSAGE_ID_WIDTH-1 downto 0) := (others => '0'); + signal opcode, opcode_next : std_logic_vector(SUBMESSAGE_ID_WIDTH-1 downto 0); -- Metatraffic Opcode Latch - signal meta_opcode, meta_opcode_next : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); + signal meta_opcode, meta_opcode_next : std_logic_vector(WORD_WIDTH-1 downto 0); -- Signifies if the received packet is a metatraffic operation - signal is_meta, is_meta_next : std_logic := '0'; + signal is_meta, is_meta_next : std_logic; -- Source GUID Latch - signal guid, guid_next : GUID_TYPE := (others => (others => '0')); + signal guid, guid_next : GUID_TYPE; -- Source IPv4 Address Latch - signal addr, addr_next : std_logic_vector(IPv4_ADDRESS_WIDTH-1 downto 0) := (others => '0'); + signal addr, addr_next : std_logic_vector(IPv4_ADDRESS_WIDTH-1 downto 0); -- UDP Port Latch - signal portn, portn_next : std_logic_vector(UDP_PORT_WIDTH-1 downto 0) := (others => '0'); + signal portn, portn_next : std_logic_vector(UDP_PORT_WIDTH-1 downto 0); -- RTPS Header Flags Latch - signal flags, flags_next : std_logic_vector(SUBMESSAGE_FLAGS_WIDTH-1 downto 0) := (others => '0'); + signal flags, flags_next : std_logic_vector(SUBMESSAGE_FLAGS_WIDTH-1 downto 0); -- Source Timestamp Latch - signal ts, ts_next : TIME_TYPE := TIME_INVALID; + signal ts, ts_next : TIME_TYPE; -- Key Hash Latch - signal key_hash, key_hash_next : KEY_HASH_TYPE := (others => (others => '0')); + signal key_hash, key_hash_next : KEY_HASH_TYPE; -- Signifies if a Key Hash was received - signal key_hash_rcvd, key_hash_rcvd_next : std_logic := '0'; + signal key_hash_rcvd, key_hash_rcvd_next : std_logic; -- Status Info Latch - signal status_info, status_info_next : std_logic_vector(STATUS_INFO_WIDTH-1 downto 0) := (others => '0'); + signal status_info, status_info_next : std_logic_vector(STATUS_INFO_WIDTH-1 downto 0); -- Lifespan Latch - signal lifespan, lifespan_next : TIME_TYPE := TIME_INVALID; + signal lifespan, lifespan_next : TIME_TYPE; -- RTPS Sequence Number Latch - signal seq_nr, seq_nr_next : SEQUENCENUMBER_TYPE := SEQUENCENUMBER_UNKNOWN; + signal seq_nr, seq_nr_next : SEQUENCENUMBER_TYPE; -- Signifies the next expected Sequence Number - signal next_seq_nr, next_seq_nr_next : SEQUENCENUMBER_TYPE := SEQUENCENUMBER_UNKNOWN; + signal next_seq_nr, next_seq_nr_next : SEQUENCENUMBER_TYPE; -- Generic Sequence Number Latch - signal sn_latch_1, sn_latch_1_next : SEQUENCENUMBER_TYPE := SEQUENCENUMBER_UNKNOWN; + signal sn_latch_1, sn_latch_1_next : SEQUENCENUMBER_TYPE; -- Generic Sequence Number Latch - signal sn_latch_2, sn_latch_2_next : SEQUENCENUMBER_TYPE := SEQUENCENUMBER_UNKNOWN; + signal sn_latch_2, sn_latch_2_next : SEQUENCENUMBER_TYPE; -- Generic Sequence Number Latch - signal sn_latch_3, sn_latch_3_next : SEQUENCENUMBER_TYPE := SEQUENCENUMBER_UNKNOWN; + signal sn_latch_3, sn_latch_3_next : SEQUENCENUMBER_TYPE; -- Toggle latching the "last_word_in_user" signal until reset - signal last_word_in_latch, last_word_in_latch_next : std_logic := '0'; + signal last_word_in_latch, last_word_in_latch_next : std_logic; -- Time of next Stale Endpoint Check - signal check_time, check_time_next : TIME_TYPE := TIME_INVALID; + signal check_time, check_time_next : TIME_TYPE; -- Signifies if a Stale Endpoint Check is in progress - signal stale_check, stale_check_next : std_logic := '0'; + signal stale_check, stale_check_next : std_logic; -- Signal containing the RTPS ACKNACK Count Field - signal count, count_next : unsigned(COUNT_WIDTH-1 downto 0) := (others => '0'); + signal count, count_next : unsigned(COUNT_WIDTH-1 downto 0); -- Data in represented in Big Endian - signal data_in_swapped : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); + signal data_in_swapped : std_logic_vector(WORD_WIDTH-1 downto 0); -- Denotes the number of valid Bitmap longs (4-Byte words) - signal bitmap_cnt, bitmap_cnt_next : unsigned(log2c(MAX_BITMAP_WIDTH/CDR_LONG_WIDTH)-1 downto 0) := (others => '0'); + signal bitmap_cnt, bitmap_cnt_next : unsigned(log2c(MAX_BITMAP_WIDTH/CDR_LONG_WIDTH)-1 downto 0); -- NumberSet Bitmap Latch - signal bitmap_latch, bitmap_latch_next : BITMAP_TYPE := (others => (others => '0')); + signal bitmap_latch, bitmap_latch_next : BITMAP_TYPE; -- Counter used to read out Bitmaps - signal cnt2, cnt2_next : natural range 0 to BITMAP_TYPE'length := 0; + signal cnt2, cnt2_next : natural range 0 to BITMAP_TYPE'length; -- Signal used to iterate through Bitmaps - signal bitmap_pos, bitmap_pos_next : natural range 0 to MAX_BITMAP_WIDTH-1 := 0; + signal bitmap_pos, bitmap_pos_next : natural range 0 to MAX_BITMAP_WIDTH-1; -- Signals the start of a Memory Operation - signal mem_op_start : std_logic := '0'; + signal mem_op_start : std_logic; -- Opcode of the Memory Operation (Valid only when mem_op_start is high) - signal mem_opcode : MEM_OPCODE_TYPE := NOP; + signal mem_opcode : MEM_OPCODE_TYPE; -- Signals the end of a Memory Operation - signal mem_op_done : std_logic := '0'; + signal mem_op_done : std_logic; -- Signal containing the relevant Endpoint Memory Format Fields of the Memory Operation - signal mem_field_flags : std_logic_vector(0 to EMF_FLAG_WIDTH-1) := (others => '0'); + signal mem_field_flags : std_logic_vector(0 to EMF_FLAG_WIDTH-1); -- Signal used to pass Lease Deadlines from main to memory process - signal lease_deadline : TIME_TYPE := TIME_INVALID; + signal lease_deadline : TIME_TYPE; -- Signal used to pass Response Deadlines from main to memory process - signal res_time : TIME_TYPE := TIME_INVALID; + signal res_time : TIME_TYPE; -- Test signal used for testbench synchronisation - signal idle_sig : std_logic := '0'; + signal idle_sig : std_logic; -- Signal used to pass Endpoint Pointers to the Endpoint Memory Process - signal mem_addr_update : unsigned(ENDPOINT_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); + signal mem_addr_update : unsigned(ENDPOINT_MEMORY_ADDR_WIDTH-1 downto 0); -- *MEMORY PROCESS* -- Memory FSM state - signal mem_stage, mem_stage_next : MEM_STAGE_TYPE := IDLE; + signal mem_stage, mem_stage_next : MEM_STAGE_TYPE; -- Pointer to current relevant Endpoint Address - signal mem_addr_base, mem_addr_base_next : unsigned(ENDPOINT_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); + signal mem_addr_base, mem_addr_base_next : unsigned(ENDPOINT_MEMORY_ADDR_WIDTH-1 downto 0); -- Help signal used to reset the MAX Endpoint Memory Pointer - signal last_addr, last_addr_next : unsigned(ENDPOINT_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); + signal last_addr, last_addr_next : unsigned(ENDPOINT_MEMORY_ADDR_WIDTH-1 downto 0); -- General Memory Address Latch - signal mem_addr_latch, mem_addr_latch_next : unsigned(ENDPOINT_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); + signal mem_addr_latch, mem_addr_latch_next : unsigned(ENDPOINT_MEMORY_ADDR_WIDTH-1 downto 0); -- Highest Endpoint Memory Address (Points to first Address of last occupied Endpoint Frame) - signal max_endpoint_addr, max_endpoint_addr_next : unsigned(ENDPOINT_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); + signal max_endpoint_addr, max_endpoint_addr_next : unsigned(ENDPOINT_MEMORY_ADDR_WIDTH-1 downto 0); -- General Purpose Couter - signal mem_cnt, mem_cnt_next : natural range 0 to 23 := 0; + signal mem_cnt, mem_cnt_next : natural range 0 to 23; -- Latch for Endpoint Data from Memory - signal mem_endpoint_data, mem_endpoint_data_next : ENDPOINT_DATA_TYPE := ZERO_ENDPOINT_DATA; + signal mem_endpoint_data, mem_endpoint_data_next : ENDPOINT_DATA_TYPE; -- Latch for Endpoint Data from main process - signal mem_endpoint_latch_data, mem_endpoint_latch_data_next : ENDPOINT_LATCH_DATA_TYPE := ZERO_ENDPOINT_LATCH_DATA; + signal mem_endpoint_latch_data, mem_endpoint_latch_data_next : ENDPOINT_LATCH_DATA_TYPE; -- Position (In Endpoint Memory Frame Granularity) of current relevant Endpoint - signal mem_pos, mem_pos_next : natural range 0 to MAX_REMOTE_ENDPOINTS-1 := 0; + signal mem_pos, mem_pos_next : natural range 0 to MAX_REMOTE_ENDPOINTS-1; -- Endpoint Memory Flag Array denoting which mem_endpoint_data Fields are up-to-date with the respective fields of the Endpoint (Pointed by mem_addr_base) - signal current_emf, current_emf_next : std_logic_vector(0 to EMF_FLAG_WIDTH-1) := (others => '0'); + signal current_emf, current_emf_next : std_logic_vector(0 to EMF_FLAG_WIDTH-1); -- *MEMORY CONTROL CONNECTION SIGNALS* - signal mem_addr : unsigned(ENDPOINT_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); - signal mem_read_data, mem_write_data : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); - signal mem_ready_in, mem_valid_in : std_logic := '0'; - signal mem_ready_out, mem_valid_out : std_logic := '0'; - signal mem_read : std_logic := '0'; - signal abort_read : std_logic := '0'; + signal mem_addr : unsigned(ENDPOINT_MEMORY_ADDR_WIDTH-1 downto 0); + signal mem_read_data, mem_write_data : std_logic_vector(WORD_WIDTH-1 downto 0); + signal mem_ready_in, mem_valid_in : std_logic; + signal mem_ready_out, mem_valid_out : std_logic; + signal mem_read : std_logic; + signal abort_read : std_logic; --*****ALIAS DECLARATION***** -- ENDPOINT FRAME HEADER @@ -388,11 +388,11 @@ begin -- SKIP_PACKET Skip rest of Packet -- SKIP_META_OPERATION Skip Metatraffic Operation parse_prc : process(all) - variable tmp_dw : DOUBLE_WORD_ARRAY := (others => (others => '0')); + variable tmp_dw : DOUBLE_WORD_ARRAY; -- NOTE: We convert the bitamp to a slv to make operations easier (The tool should handle both cases equally) - variable tmp_bitmap : std_logic_vector(0 to MAX_BITMAP_WIDTH-1) := (others => '0'); - variable rd_guard : std_logic := '0'; - variable tmp_flags : std_logic_vector(0 to EMF_FLAG_WIDTH-1) := (others => '0'); + variable tmp_bitmap : std_logic_vector(0 to MAX_BITMAP_WIDTH-1); + variable rd_guard : std_logic; + variable tmp_flags : std_logic_vector(0 to EMF_FLAG_WIDTH-1); begin -- DEFAULT Registered stage_next <= stage; diff --git a/src/rtps_writer.vhd b/src/rtps_writer.vhd index 5971aa4..7fc2999 100644 --- a/src/rtps_writer.vhd +++ b/src/rtps_writer.vhd @@ -199,123 +199,123 @@ architecture arch of rtps_writer is --*****SIGNAL DECLARATION***** -- *MAIN PROCESS* -- FSM state - signal stage, stage_next : STAGE_TYPE := IDLE; + signal stage, stage_next : STAGE_TYPE; -- FSM state latch. Used to transition dynamically to different states from the same state. - signal return_stage, return_stage_next : STAGE_TYPE := IDLE; + signal return_stage, return_stage_next : STAGE_TYPE; -- General Purpose Counter - signal cnt, cnt_next : natural range 0 to 13 := 0; + signal cnt, cnt_next : natural range 0 to 13; -- Counter Latch. Used to transition dynamically to different sub-states from the same state. - signal return_cnt, return_cnt_next : natural range 0 to 13 := 0; + signal return_cnt, return_cnt_next : natural range 0 to 13; -- Packet Opcode Latch (RTPS Message ID) - signal opcode, opcode_next : std_logic_vector(SUBMESSAGE_ID_WIDTH-1 downto 0) := (others => '0'); + signal opcode, opcode_next : std_logic_vector(SUBMESSAGE_ID_WIDTH-1 downto 0); -- Metatraffic Opcode Latch - signal meta_opcode, meta_opcode_next : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); + signal meta_opcode, meta_opcode_next : std_logic_vector(WORD_WIDTH-1 downto 0); -- Signifies if the received packet is a metatraffic operation - signal is_meta, is_meta_next : std_logic := '0'; + signal is_meta, is_meta_next : std_logic; -- Source GUID Latch - signal guid, guid_next : GUID_TYPE := (others => (others => '0')); + signal guid, guid_next : GUID_TYPE; -- Source IPv4 Address Latch - signal addr, addr_next : std_logic_vector(IPv4_ADDRESS_WIDTH-1 downto 0) := (others => '0'); + signal addr, addr_next : std_logic_vector(IPv4_ADDRESS_WIDTH-1 downto 0); -- UDP Port Latch - signal portn, portn_next : std_logic_vector(UDP_PORT_WIDTH-1 downto 0) := (others => '0'); + signal portn, portn_next : std_logic_vector(UDP_PORT_WIDTH-1 downto 0); -- RTPS Header Flags Latch - signal rtps_flags, rtps_flags_next : std_logic_vector(SUBMESSAGE_FLAGS_WIDTH-1 downto 0) := (others => '0'); + signal rtps_flags, rtps_flags_next : std_logic_vector(SUBMESSAGE_FLAGS_WIDTH-1 downto 0); -- Remote Endpoint Reader Flags Latch - signal reader_flags, reader_flags_next : std_logic_vector(CDR_SHORT_WIDTH-1 downto 0) := (others => '0'); + signal reader_flags, reader_flags_next : std_logic_vector(CDR_SHORT_WIDTH-1 downto 0); -- Generic Sequence Number Latch - signal sn_latch_1, sn_latch_1_next : SEQUENCENUMBER_TYPE := SEQUENCENUMBER_UNKNOWN; + signal sn_latch_1, sn_latch_1_next : SEQUENCENUMBER_TYPE; -- Generic Sequence Number Latch - signal sn_latch_2, sn_latch_2_next : SEQUENCENUMBER_TYPE := SEQUENCENUMBER_UNKNOWN; + signal sn_latch_2, sn_latch_2_next : SEQUENCENUMBER_TYPE; -- Generic Sequence Number Latch - signal sn_latch_3, sn_latch_3_next : SEQUENCENUMBER_TYPE := SEQUENCENUMBER_UNKNOWN; + signal sn_latch_3, sn_latch_3_next : SEQUENCENUMBER_TYPE; -- General Purpose Long Latch - signal long_latch, long_latch_next : std_logic_vector(CDR_LONG_WIDTH-1 downto 0) := (others => '0'); + signal long_latch, long_latch_next : std_logic_vector(CDR_LONG_WIDTH-1 downto 0); -- Toggle latching the "last_word_in_user" signal until reset - signal last_word_in_latch, last_word_in_latch_next : std_logic := '0'; + signal last_word_in_latch, last_word_in_latch_next : std_logic; -- Toggle latch for Liveliness Assertion - signal assert_liveliness_latch, assert_liveliness_latch_next : std_logic := '0'; + signal assert_liveliness_latch, assert_liveliness_latch_next : std_logic; -- Time of next Stale Endpoint Check - signal check_time, check_time_next : TIME_TYPE := TIME_INVALID; + signal check_time, check_time_next : TIME_TYPE; -- Time of next Heartbeat sending - signal heartbeat_time, heartbeat_time_next : TIME_TYPE := TIME_INVALID; + signal heartbeat_time, heartbeat_time_next : TIME_TYPE; -- Signifies if a Stale Endpoint Check is in progress - signal stale_check, stale_check_next : std_logic := '0'; + signal stale_check, stale_check_next : std_logic; -- Signifies the new Cache Changes are currently being send out - signal new_push, new_push_next : std_logic := '0'; + signal new_push, new_push_next : std_logic; -- Signifies that Historical Cache Changes are currently being sent out - signal historical_push, historical_push_next : std_logic := '0'; + signal historical_push, historical_push_next : std_logic; -- Signifies that the first half of a GAP Message has been written, and needs to be "closed" - signal gap_in_progress, gap_in_progress_next : std_logic := '0'; + signal gap_in_progress, gap_in_progress_next : std_logic; -- Signifies that the GAP is the Last Submessage - signal gap_is_last, gap_is_last_next : std_logic := '0'; + signal gap_is_last, gap_is_last_next : std_logic; -- Signal containing the RTPS Heartbeat Count Field - signal count, count_next : unsigned(COUNT_WIDTH-1 downto 0) := (others => '0'); + signal count, count_next : unsigned(COUNT_WIDTH-1 downto 0); -- Signal containing the lowest common Sequence Number ACKed by ALL remote Readers - signal global_ack_seq_nr_base, global_ack_seq_nr_base_next : SEQUENCENUMBER_TYPE := SEQUENCENUMBER_UNKNOWN; + signal global_ack_seq_nr_base, global_ack_seq_nr_base_next : SEQUENCENUMBER_TYPE; -- Signal containing the highest Sequence Number sent out by the writer - signal last_seq_nr, last_seq_nr_next : SEQUENCENUMBER_TYPE := SEQUENCENUMBER_UNKNOWN; + signal last_seq_nr, last_seq_nr_next : SEQUENCENUMBER_TYPE; -- Denotes the number of valid Bitmap longs (4-Byte words) - signal bitmap_cnt, bitmap_cnt_next : unsigned(log2c(MAX_BITMAP_WIDTH/CDR_LONG_WIDTH)-1 downto 0) := (others => '0'); + signal bitmap_cnt, bitmap_cnt_next : unsigned(log2c(MAX_BITMAP_WIDTH/CDR_LONG_WIDTH)-1 downto 0); -- NumberSet Bitmap Latch - signal bitmap_latch, bitmap_latch_next : BITMAP_TYPE := (others => (others => '0')); + signal bitmap_latch, bitmap_latch_next : BITMAP_TYPE; -- Counter used to read out Bitmaps - signal cnt2, cnt2_next : natural range 0 to BITMAP_TYPE'length := 0; + signal cnt2, cnt2_next : natural range 0 to BITMAP_TYPE'length; -- Counter used to read out the In-Line QoS - signal cnt3, cnt3_next : natural range 0 to INLINE_QOS.length-1 := 0; + signal cnt3, cnt3_next : natural range 0 to INLINE_QOS.length-1; -- Signal used to iterate through NACK Bitmaps - signal nack_bitmap_pos, nack_bitmap_pos_next : natural range 0 to MAX_BITMAP_WIDTH-1 := 0; + signal nack_bitmap_pos, nack_bitmap_pos_next : natural range 0 to MAX_BITMAP_WIDTH-1; -- Signals the start of a Memory Operation - signal mem_op_start : std_logic := '0'; + signal mem_op_start : std_logic; -- Opcode of the Memory Operation (Valid only when mem_op_start is high) - signal mem_opcode : MEM_OPCODE_TYPE := NOP; + signal mem_opcode : MEM_OPCODE_TYPE; -- Signals the end of a Memory Operation - signal mem_op_done : std_logic := '0'; + signal mem_op_done : std_logic; -- Signal containing the relevant Endpoint Memory Format Fields of the Memory Operation - signal mem_field_flags : std_logic_vector(0 to EMF_FLAG_WIDTH-1) := (others => '0'); + signal mem_field_flags : std_logic_vector(0 to EMF_FLAG_WIDTH-1); -- Signal used to pass Lease Deadlines from main to memory process - signal lease_deadline : TIME_TYPE := TIME_INVALID; + signal lease_deadline : TIME_TYPE; -- Signal used to pass Response Deadlines from main to memory process - signal res_time : TIME_TYPE := TIME_INVALID; + signal res_time : TIME_TYPE; -- Signal used to pass Sequence Numbers from main to memory process - signal seq_nr : SEQUENCENUMBER_TYPE := SEQUENCENUMBER_UNKNOWN; + signal seq_nr : SEQUENCENUMBER_TYPE; -- Signal used to pass the Request Sequence Number Bitmap from main to memory process - signal req_seq_nr_bitmap, req_seq_nr_bitmap_next : std_logic_vector(0 to WORD_WIDTH-1) := (others => '0'); + signal req_seq_nr_bitmap, req_seq_nr_bitmap_next : std_logic_vector(0 to WORD_WIDTH-1); -- Signal used to iterate through Request Bitmaps - signal req_bitmap_pos, req_bitmap_pos_next : natural range 0 to req_seq_nr_bitmap'length-1 := 0; + signal req_bitmap_pos, req_bitmap_pos_next : natural range 0 to req_seq_nr_bitmap'length-1; -- Test signal used for testbench synchronisation - signal idle_sig : std_logic := '0'; + signal idle_sig : std_logic; -- Signal used to pass Endpoint Pointers to the Endpoint Memory Process - signal mem_addr_update : unsigned(ENDPOINT_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); + signal mem_addr_update : unsigned(ENDPOINT_MEMORY_ADDR_WIDTH-1 downto 0); -- *MEMORY PROCESS* -- Memory FSM state - signal mem_stage, mem_stage_next : MEM_STAGE_TYPE := IDLE; + signal mem_stage, mem_stage_next : MEM_STAGE_TYPE; -- Pointer to current relevant Endpoint Address - signal mem_addr_base, mem_addr_base_next : unsigned(ENDPOINT_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); + signal mem_addr_base, mem_addr_base_next : unsigned(ENDPOINT_MEMORY_ADDR_WIDTH-1 downto 0); -- Help signal used to reset the MAX Endpoint Memory Pointer - signal last_addr, last_addr_next : unsigned(ENDPOINT_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); + signal last_addr, last_addr_next : unsigned(ENDPOINT_MEMORY_ADDR_WIDTH-1 downto 0); -- General Memory Address Latch - signal mem_addr_latch, mem_addr_latch_next : unsigned(ENDPOINT_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); + signal mem_addr_latch, mem_addr_latch_next : unsigned(ENDPOINT_MEMORY_ADDR_WIDTH-1 downto 0); -- Highest Endpoint Memory Address (Points to first Address of last occupied Endpoint Frame) - signal max_endpoint_addr, max_endpoint_addr_next : unsigned(ENDPOINT_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); + signal max_endpoint_addr, max_endpoint_addr_next : unsigned(ENDPOINT_MEMORY_ADDR_WIDTH-1 downto 0); -- General Purpose Couter - signal mem_cnt, mem_cnt_next : natural range 0 to 29 := 0; + signal mem_cnt, mem_cnt_next : natural range 0 to 29; -- Latch for Endpoint Data from Memory - signal mem_endpoint_data, mem_endpoint_data_next : ENDPOINT_DATA_TYPE := ZERO_ENDPOINT_DATA; + signal mem_endpoint_data, mem_endpoint_data_next : ENDPOINT_DATA_TYPE; -- Latch for Endpoint Data from main process - signal mem_endpoint_latch_data, mem_endpoint_latch_data_next : ENDPOINT_LATCH_DATA_TYPE := ZERO_ENDPOINT_LATCH_DATA; + signal mem_endpoint_latch_data, mem_endpoint_latch_data_next : ENDPOINT_LATCH_DATA_TYPE; -- Position (In Endpoint Memory Frame Granularity) of current relevant Endpoint - signal mem_pos, mem_pos_next : natural range 0 to MAX_REMOTE_ENDPOINTS-1 := 0; + signal mem_pos, mem_pos_next : natural range 0 to MAX_REMOTE_ENDPOINTS-1; -- Endpoint Memory Flag Array denoting which mem_endpoint_data Fields are up-to-date with the respective fields of the Endpoint (Pointed by mem_addr_base) - signal current_emf, current_emf_next : std_logic_vector(0 to EMF_FLAG_WIDTH-1) := (others => '0'); + signal current_emf, current_emf_next : std_logic_vector(0 to EMF_FLAG_WIDTH-1); -- *MEMORY CONTROL CONNECTION SIGNALS* - signal mem_addr : unsigned(ENDPOINT_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); - signal mem_read_data, mem_write_data : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); - signal mem_ready_in, mem_valid_in : std_logic := '0'; - signal mem_ready_out, mem_valid_out : std_logic := '0'; - signal mem_read : std_logic := '0'; - signal abort_read : std_logic := '0'; + signal mem_addr : unsigned(ENDPOINT_MEMORY_ADDR_WIDTH-1 downto 0); + signal mem_read_data, mem_write_data : std_logic_vector(WORD_WIDTH-1 downto 0); + signal mem_ready_in, mem_valid_in : std_logic; + signal mem_ready_out, mem_valid_out : std_logic; + signal mem_read : std_logic; + signal abort_read : std_logic; --*****ALIAS DECLARATION***** @@ -414,10 +414,10 @@ begin -- SKIP_PACKET Skip rest of Packet -- SKIP_META_OPERATION Skip Metatraffic Operation parse_prc : process(all) - variable tmp_dw : DOUBLE_WORD_ARRAY := (others => (others => '0')); + variable tmp_dw : DOUBLE_WORD_ARRAY; -- NOTE: We convert the bitamp to a slv to make operations easier (The tool should handle both cases equally) - variable tmp_bitmap : std_logic_vector(0 to MAX_BITMAP_WIDTH-1) := (others => '0'); - variable tmp_flags : std_logic_vector(0 to EMF_FLAG_WIDTH-1) := (others => '0'); + variable tmp_bitmap : std_logic_vector(0 to MAX_BITMAP_WIDTH-1); + variable tmp_flags : std_logic_vector(0 to EMF_FLAG_WIDTH-1); begin -- DEFAULT Registered stage_next <= stage;