* Restructure, cleaning and final documentation in builtin_endpoint

VHDL-2008.txt

@@ -0,0 +1,5 @@
+Quartus 18.1 Unsupported
+========================
+* Unconstrained arrays in records (Supported in Pro)
+* Vectors in aggregate statements
+    e.g. V := ("0000", others => '1');

src/math_pkg.vhd

@@ -8,6 +8,8 @@ package math_pkg is
     function max(constant value1, value2, value3 : in integer) return integer;
     -- returns the minimum of the two operands
     function min(constant value1, value2 : in integer) return integer;
+	 
+	 function round_div(constant divident, divisor : in integer) return integer;
 end package;
 
 

src/rtps_package.vhd

@@ -343,7 +343,7 @@ package rtps_package is
     constant PARTICIPANT_MESSAGE_DATA_KIND_MANUAL_LIVELINESS_UPDATE     : std_logic_vector(PARTICIPANT_MESSAGE_KIND_WIDTH-1 downto 0) := x"00000002";
     
     --*****CUSTOM*****
-    constant PARTICIPANT_FRAME_SIZE     : natural := 19;
+    constant PARTICIPANT_FRAME_SIZE     : natural := 23;
     constant ENDPOINT_BITMASK_SIZE      : natural := round_div(MAX_ENDPOINTS, 32);
     constant ENDPOINT_FRAME_SIZE        : natural := 4 + ENDPOINT_BITMASK_SIZE;
     -- Limit Buffer to 32 bit Addresses

src/test.vhd

@@ -4,6 +4,7 @@ use ieee.numeric_std.all;
 
 use work.math_pkg.all;
 use work.test_package.all;
+use work.rtps_package.all;
 
 -- TODO: Remove alignment logic for RTPS Submessages, since all Submessages are 32-bit aligned
 -- Checksum has to be checked before
@@ -12,26 +13,43 @@ entity test is
     port (
         clk             : in std_logic;                                     -- Input Clock
         reset           : in std_logic;                                     -- Synchronous Reset
-        cnt             : in natural;
+        input           : in std_logic_vector(1 downto 0);
-        output			: out unsigned(31 downto 0)
+        cnt             : in natural range 0 to 12;
+        output			: out unsigned(5 downto 0)
     );
 end entity;
 
 architecture arch of test is
 
+    constant BUILD : std_logic := '0';
     
-    signal output_sig : unsigned(31 downto 0) := (others => '0');
+    signal output_sig : unsigned(5 downto 0) := (others => '0');
     
 begin
 	output <= output_sig;
     
-    bitmap: process(all)
+    process(all)
     begin
         output_sig  <= (others => '0');
         
-        for i in 0 to cnt loop
+        if (cnt < PARTICIPANT_DATA.length) then
-            output_sig(i)   <= '1';
+            output_sig  <= unsigned(PARTICIPANT_DATA.data(cnt))(5 downto 0);
-        end loop;
+        end if;
+        
+--        case (input) is
+--            when "00" =>
+--                output_sig  <= to_unsigned(1,6);
+--            when "01" =>
+--                output_sig  <= to_unsigned(2,6);
+--            when "10" =>
+--                output_sig  <= to_unsigned(3,6);
+--            when "11" =>
+--                if (BUILD = '1') then
+--                    output_sig  <= to_unsigned(1,6) + cnt;
+--                end if;
+--        end case;
     end process;
     
+    
+
 end architecture;

syn/DE10-Nano/top.qsf

@@ -51,6 +51,7 @@ set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
 set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
 set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
 set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name VHDL_FILE ../../src/rtps_package.vhd -hdl_version VHDL_2008
 set_global_assignment -name VHDL_FILE ../../src/test_package.vhd -hdl_version VHDL_2008
 set_global_assignment -name VHDL_FILE ../../src/test.vhd -hdl_version VHDL_2008
 set_global_assignment -name VHDL_FILE ../../src/math_pkg.vhd -hdl_version VHDL_2008