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Fix Port Name Convention and RTPS/DDS Handshacking

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Greek 2021-02-03 20:22:43 +01:00
parent dc8746c463
commit 6488918ede
2 changed files with 303 additions and 262 deletions
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102
src/dds_reader.vhd
View File

@ -36,13 +36,12 @@ entity dds_reader is
start_dds : in std_logic; start_dds : in std_logic;
ack_dds : out std_logic; ack_dds : out std_logic;
opcode_dds : in HISTORY_CACHE_OPCODE_TYPE; opcode_dds : in HISTORY_CACHE_OPCODE_TYPE;
instance_state_in : in std_logic_vector(INSTANCE_STATE_KIND_WIDTH-1 downto 0); instance_state_dds : in std_logic_vector(INSTANCE_STATE_KIND_WIDTH-1 downto 0);
view_state_in : in std_logic_vector(VIEW_STATE_KIND_WIDTH-1 downto 0); view_state_dds : in std_logic_vector(VIEW_STATE_KIND_WIDTH-1 downto 0);
sample_state_in : in std_logic_vector(SAMPLE_STATE_KIND_WIDTH-1 downto 0); sample_state_dds : in std_logic_vector(SAMPLE_STATE_KIND_WIDTH-1 downto 0);
instance_handle_in : in INSTANCE_HANDLE_TYPE; instance_handle_dds : in INSTANCE_HANDLE_TYPE;
max_samples_in : in std_logic_vector(MAX_SAMPLES_WIDTH-1 downto 0); max_samples_dds : in std_logic_vector(MAX_SAMPLES_WIDTH-1 downto 0);
next_sample : in std_logic; get_data_dds : in std_logic;
get_data : in std_logic;
done_dds : out std_logic; done_dds : out std_logic;
return_code_dds : out std_logic_vector(RETURN_CODE_WIDTH-1 downto 0); return_code_dds : out std_logic_vector(RETURN_CODE_WIDTH-1 downto 0);
ready_out_dds : in std_logic; ready_out_dds : in std_logic;
@ -510,6 +509,21 @@ begin
); );
end generate; end generate;
si_sample_state <= si_sample_state_sig;
si_view_state <= si_view_state_sig;
si_instance_state <= si_instance_handle_sig;
si_source_timestamp <= si_source_timestamp_sig;
si_instance_handle <= si_instance_handle_sig;
si_publication_handle <= si_publication_handle_sig;
si_disposed_generation_count <= si_disposed_generation_count_sig;
si_no_writers_generation_count <= si_no_writers_generation_count_sig;
si_sample_rank <= si_sample_rank_sig;
si_generation_rank <= si_generation_rank_sig;
si_absolute_generation_count <= si_absolute_generation_count_sig;
si_valid_data <= si_valid_data_sig;
si_valid <= si_valid_sig;
status <= status_sig;
-- *Main State Machine* -- *Main State Machine*
-- STATE DESCRIPTION -- STATE DESCRIPTION
-- IDLE Idle State. Initiates Deadline Miss Checks, Lifespan Expiry Checks, RTPS Operation handling, and DDS Operation handling, in that priority order. -- IDLE Idle State. Initiates Deadline Miss Checks, Lifespan Expiry Checks, RTPS Operation handling, and DDS Operation handling, in that priority order.
@ -647,9 +661,6 @@ begin
case (stage) is case (stage) is
when IDLE => when IDLE =>
-- DEFAULT
ready_in_rtps <= '1';
-- Reset -- Reset
remove_oldest_inst_sample_next <= '0'; remove_oldest_inst_sample_next <= '0';
remove_oldest_sample_next <= '0'; remove_oldest_sample_next <= '0';
@ -692,8 +703,6 @@ begin
elsif (start_rtps = '1') then elsif (start_rtps = '1') then
case (opcode_rtps) is case (opcode_rtps) is
when ADD_CHANGE => when ADD_CHANGE =>
-- This Operation does not accept input at this time
ready_in_rtps <= '0';
res_rtps <= ACK; res_rtps <= ACK;
stage_next <= ADD_SAMPLE_INFO; stage_next <= ADD_SAMPLE_INFO;
@ -701,30 +710,27 @@ begin
cnt_next <= 0; cnt_next <= 0;
end if; end if;
when REMOVE_WRITER => when REMOVE_WRITER =>
-- Input and Memory Gurad res_rtps <= ACK;
if (valid_in_rtps = '1') then
res_rtps <= ACK; -- Synthesis Guard
if (WITH_KEY) then
-- Latch Writer Pos
writer_pos_next <= to_integer(unsigned(data_in_rtps));
stage_next <= REMOVE_WRITER;
cnt_next <= 2;
else
-- Convert Writer Bitmap to SLV
tmp_bitmap := to_endpoint_bitmap(inst_data.writer_bitmap);
-- Synthesis Guard -- Remove Writer
if (WITH_KEY) then tmp_bitmap(to_integer(unsigned(data_in_rtps))) := '0';
-- Latch Writer Pos
writer_pos_next <= to_integer(unsigned(data_in_rtps)); -- Convert Back
stage_next <= REMOVE_WRITER; inst_data_next.writer_bitmap <= from_endpoint_bitmap(tmp_bitmap);
cnt_next <= 2;
else -- NOT_ALIVE_NO_WRITERS Transition
-- Convert Writer Bitmap to SLV if (tmp_bitmap = (tmp_bitmap'range => '0') and inst_data.status_info(NOT_ALIVE_DISPOSED_FLAG) = '0') then
tmp_bitmap := to_endpoint_bitmap(inst_data.writer_bitmap); inst_data_next.status_info(NOT_ALIVE_NO_WRITERS_FLAG) <= '1';
-- Remove Writer
tmp_bitmap(to_integer(unsigned(data_in_rtps))) := '0';
-- Convert Back
inst_data_next.writer_bitmap <= from_endpoint_bitmap(tmp_bitmap);
-- NOT_ALIVE_NO_WRITERS Transition
if (tmp_bitmap = (tmp_bitmap'range => '0') and inst_data.status_info(NOT_ALIVE_DISPOSED_FLAG) = '0') then
inst_data_next.status_info(NOT_ALIVE_NO_WRITERS_FLAG) <= '1';
end if;
end if; end if;
end if; end if;
when others => when others =>
@ -741,10 +747,10 @@ begin
-- DDS Operation -- DDS Operation
elsif (start_dds = '1') then elsif (start_dds = '1') then
-- Latch Input Signals -- Latch Input Signals
sample_state_next <= sample_state_in; sample_state_next <= sample_state_dds;
view_state_next <= view_state_in; view_state_next <= view_state_dds;
instance_state_next <= instance_state; instance_state_next <= instance_state;
max_samples_next <= unsigned(max_samples_in); max_samples_next <= unsigned(max_samples_dds);
-- Reset -- Reset
single_sample_next <= '0'; single_sample_next <= '0';
@ -809,7 +815,7 @@ begin
ack_dds <= '1'; ack_dds <= '1';
single_instance_next <= '1'; single_instance_next <= '1';
cur_sample_next <= oldest_sample; cur_sample_next <= oldest_sample;
key_hash_next <= instance_handle_in; key_hash_next <= instance_handle_dds;
stage_next <= CHECK_INSTANCE; stage_next <= CHECK_INSTANCE;
cnt_next <= 0; cnt_next <= 0;
else else
@ -823,7 +829,7 @@ begin
is_take_next <= '1'; is_take_next <= '1';
single_instance_next <= '1'; single_instance_next <= '1';
cur_sample_next <= oldest_sample; cur_sample_next <= oldest_sample;
key_hash_next <= instance_handle_in; key_hash_next <= instance_handle_dds;
stage_next <= CHECK_INSTANCE; stage_next <= CHECK_INSTANCE;
cnt_next <= 0; cnt_next <= 0;
else else
@ -837,7 +843,7 @@ begin
single_instance_next <= '1'; single_instance_next <= '1';
dynamic_next_instance_next <= '1'; dynamic_next_instance_next <= '1';
cur_sample_next <= oldest_sample; cur_sample_next <= oldest_sample;
key_hash_next <= instance_handle_in; key_hash_next <= instance_handle_dds;
stage_next <= FIND_NEXT_INSTANCE; stage_next <= FIND_NEXT_INSTANCE;
cnt_next <= 0; cnt_next <= 0;
else else
@ -852,7 +858,7 @@ begin
single_instance_next <= '1'; single_instance_next <= '1';
dynamic_next_instance_next <= '1'; dynamic_next_instance_next <= '1';
cur_sample_next <= oldest_sample; cur_sample_next <= oldest_sample;
key_hash_next <= instance_handle_in; key_hash_next <= instance_handle_dds;
stage_next <= FIND_NEXT_INSTANCE; stage_next <= FIND_NEXT_INSTANCE;
cnt_next <= 0; cnt_next <= 0;
else else
@ -1368,7 +1374,7 @@ begin
-- Synthesis Guard -- Synthesis Guard
if (WITH_KEY) then if (WITH_KEY) then
tmp_update <= tmp_update or IMF_STATUS_FLAG; tmp_update <= tmp_update or IMF_STATUS_FLAG;
status_info_update <= inst_data.status; status_info_update <= inst_data.status_info;
status_info_update(NOT_ALIVE_DISPOSED_FLAG) <= '1'; status_info_update(NOT_ALIVE_DISPOSED_FLAG) <= '1';
status_info_update(LIVELINESS_FLAG) <= '1'; status_info_update(LIVELINESS_FLAG) <= '1';
else else
@ -1399,7 +1405,7 @@ begin
-- Synthesis Guard -- Synthesis Guard
if (WITH_KEY) then if (WITH_KEY) then
tmp_update <= tmp_update or IMF_STATUS_FLAG; tmp_update <= tmp_update or IMF_STATUS_FLAG;
status_info_update <= inst_data.status; status_info_update <= inst_data.status_info;
status_info_update(NOT_ALIVE_NO_WRITERS_FLAG) <= '1'; status_info_update(NOT_ALIVE_NO_WRITERS_FLAG) <= '1';
status_info_update(LIVELINESS_FLAG) <= '1'; status_info_update(LIVELINESS_FLAG) <= '1';
else else
@ -1413,7 +1419,7 @@ begin
-- Synthesis Guard -- Synthesis Guard
if (WITH_KEY) then if (WITH_KEY) then
tmp_update <= tmp_update or IMF_STATUS_FLAG; tmp_update <= tmp_update or IMF_STATUS_FLAG;
status_info_update <= inst_data.status; status_info_update <= inst_data.status_info;
status_info_update(NOT_ALIVE_DISPOSED_FLAG) <= '0'; status_info_update(NOT_ALIVE_DISPOSED_FLAG) <= '0';
status_info_update(NOT_ALIVE_NO_WRITERS_FLAG) <= '0'; status_info_update(NOT_ALIVE_NO_WRITERS_FLAG) <= '0';
status_info_update(LIVELINESS_FLAG) <= '1'; status_info_update(LIVELINESS_FLAG) <= '1';
@ -2212,8 +2218,8 @@ begin
writer_bitmap <= from_endpoint_bitmap(tmp_bitmap); writer_bitmap <= from_endpoint_bitmap(tmp_bitmap);
-- NOT_ALIVE_NO_WRITERS Transition -- NOT_ALIVE_NO_WRITERS Transition
if (tmp_bitmap = (tmp_bitmap'range => '0') and inst_data.status(NOT_ALIVE_DISPOSED_FLAG) = '0') then if (tmp_bitmap = (tmp_bitmap'range => '0') and inst_data.status_info(NOT_ALIVE_DISPOSED_FLAG) = '0') then
status_info_update <= inst_data.status; status_info_update <= inst_data.status_info;
status_info_update(NOT_ALIVE_NO_WRITERS_FLAG) <= '1'; status_info_update(NOT_ALIVE_NO_WRITERS_FLAG) <= '1';
inst_op_start <= '1'; inst_op_start <= '1';
inst_opcode <= UPDATE_INSTANCE; inst_opcode <= UPDATE_INSTANCE;
@ -2987,7 +2993,7 @@ begin
status_sig_next(DATA_AVAILABLE_STATUS) <= '0'; status_sig_next(DATA_AVAILABLE_STATUS) <= '0';
-- Sample Data Request -- Sample Data Request
if (get_data = '1') then if (get_data_dds = '1') then
stage_next <= GET_PAYLOAD; stage_next <= GET_PAYLOAD;
cnt_next <= 0; cnt_next <= 0;
else else

463
src/rtps_reader.vhd
View File

@ -28,28 +28,28 @@ entity rtps_reader is
clk : in std_logic; clk : in std_logic;
reset : in std_logic; reset : in std_logic;
time : in TIME_TYPE; time : in TIME_TYPE;
-- FROM RTPS_HANDLER -- FROM RTPS_HANDLER (USER TRAFFIC)
empty : in std_logic; empty_user : in std_logic;
rd : out std_logic; rd_user : out std_logic;
last_word_in : in std_logic; last_word_in_user : in std_logic;
data_in : in std_logic_vector(WORD_WIDTH-1 downto 0); data_in_user : in std_logic_vector(WORD_WIDTH-1 downto 0);
-- FROM RTPS_BUILTIN_ENDPOINT -- FROM RTPS_BUILTIN_ENDPOINT (META TRAFFIC)
meta_empty : in std_logic; empty_meta : in std_logic;
meta_data_in : in std_logic_vector(WORD_WIDTH-1 downto 0); data_in_meta : in std_logic_vector(WORD_WIDTH-1 downto 0);
meta_rd : out std_logic; rd_meta : out std_logic;
-- RTPS OUTPUT -- RTPS OUTPUT
rtps_wr : out std_logic; wr_rtps : out std_logic;
rtps_full : in std_logic; full_rtps : in std_logic;
last_word_out : out std_logic; last_word_out_rtps : out std_logic;
data_out : out std_logic_vector(WORD_WIDTH-1 downto 0); data_out_rtps : out std_logic_vector(WORD_WIDTH-1 downto 0);
-- TO DDS READER -- TO DDS READER
dds_start : out std_logic; start_dds : out std_logic;
dds_opcode : out HISTORY_CACHE_OPCODE_TYPE; opcode_dds : out HISTORY_CACHE_OPCODE_TYPE;
dds_res : in HISTORY_CACHE_RESPOSNE_TYPE; res_dds : in HISTORY_CACHE_RESPOSNE_TYPE;
dds_data_out : in std_logic_vector(WORD_WIDTH-1 downto 0); data_out_dds : out std_logic_vector(WORD_WIDTH-1 downto 0);
dds_valid_out : in std_logic; valid_out_dds : out std_logic;
dds_ready_out : out std_logic; ready_out_dds : in std_logic;
dds_last_word_out : in std_logic last_word_out_dds : out std_logic
); );
end entity; end entity;
@ -102,7 +102,7 @@ architecture arch of rtps_reader is
-- *Memory FSM Opcodes* -- *Memory FSM Opcodes*
-- OPCODE DESCRIPTION -- OPCODE DESCRIPTION
-- SEARCH_ENDPOINT Find Endpoint with specified GUID in memory -- SEARCH_ENDPOINT Find Endpoint with specified GUID in memory
-- INSERT_ENDPOINT Insert Endpoint to first available empty slot in memory -- INSERT_ENDPOINT Insert Endpoint to first available empty_user slot in memory
-- UPDATE_ENDPOINT Update Endpoint pointed by mem_addr_base. (mem_field_flags specifies which Fields to update) -- UPDATE_ENDPOINT Update Endpoint pointed by mem_addr_base. (mem_field_flags specifies which Fields to update)
-- REMOVE_ENDPOINT Remove Endpoint pointed by mem_addr_base -- REMOVE_ENDPOINT Remove Endpoint pointed by mem_addr_base
-- GET_FIRST_ENDPOINT Get Endpoint Data of first Endpoint stored in Memory. (mem_field_flags specifies which Fields to get) -- GET_FIRST_ENDPOINT Get Endpoint Data of first Endpoint stored in Memory. (mem_field_flags specifies which Fields to get)
@ -198,7 +198,7 @@ architecture arch of rtps_reader is
signal sn_latch_2, sn_latch_2_next : SEQUENCENUMBER_TYPE := SEQUENCENUMBER_UNKNOWN; signal sn_latch_2, sn_latch_2_next : SEQUENCENUMBER_TYPE := SEQUENCENUMBER_UNKNOWN;
-- Generic Sequence Number Latch -- Generic Sequence Number Latch
signal sn_latch_3, sn_latch_3_next : SEQUENCENUMBER_TYPE := SEQUENCENUMBER_UNKNOWN; signal sn_latch_3, sn_latch_3_next : SEQUENCENUMBER_TYPE := SEQUENCENUMBER_UNKNOWN;
-- Toggle latching the "last_word_in" signal until reset -- Toggle latching the "last_word_in_user" signal until reset
signal last_word_in_latch, last_word_in_latch_next : std_logic := '0'; signal last_word_in_latch, last_word_in_latch_next : std_logic := '0';
-- Time of next Stale Endpoint Check -- Time of next Stale Endpoint Check
signal check_time, check_time_next : TIME_TYPE := TIME_INVALID; signal check_time, check_time_next : TIME_TYPE := TIME_INVALID;
@ -261,16 +261,16 @@ architecture arch of rtps_reader is
--*****ALIAS DECLARATION***** --*****ALIAS DECLARATION*****
-- ENDPOINT FRAME HEADER -- ENDPOINT FRAME HEADER
alias header_opcode : std_logic_vector(7 downto 0) is data_in(31 downto 24); alias header_opcode : std_logic_vector(7 downto 0) is data_in_user(31 downto 24);
alias header_flags : std_logic_vector(7 downto 0) is data_in(23 downto 16); alias header_flags : std_logic_vector(7 downto 0) is data_in_user(23 downto 16);
alias header_udp_port : std_logic_vector(15 downto 0) is data_in(15 downto 0); alias header_udp_port : std_logic_vector(15 downto 0) is data_in_user(15 downto 0);
-- RTPS PARAMETER LIST HEADER -- RTPS PARAMETER LIST HEADER
alias parameter_id : std_logic_vector(15 downto 0) is data_in(31 downto 16); alias parameter_id : std_logic_vector(15 downto 0) is data_in_user(31 downto 16);
alias parameter_length : std_logic_vector(15 downto 0) is data_in(15 downto 0); alias parameter_length : std_logic_vector(15 downto 0) is data_in_user(15 downto 0);
alias must_understand : std_logic is parameter_id(14); alias must_understand : std_logic is parameter_id(14);
-- RTPS DATA PAYLOAD HEADER -- RTPS DATA PAYLOAD HEADER
alias representation_id : std_logic_vector(15 downto 0) is data_in(31 downto 16); alias representation_id : std_logic_vector(15 downto 0) is data_in_user(31 downto 16);
alias representation_options : std_logic_vector(15 downto 0) is data_in(15 downto 0); alias representation_options : std_logic_vector(15 downto 0) is data_in_user(15 downto 0);
-- RTPS SUBMESSAGE FLAGS -- RTPS SUBMESSAGE FLAGS
alias endian_flag : std_logic is flags(0); alias endian_flag : std_logic is flags(0);
alias qos_flag : std_logic is flags(1); alias qos_flag : std_logic is flags(1);
@ -320,14 +320,14 @@ begin
read => mem_read, read => mem_read,
ready_in => mem_ready_in, ready_in => mem_ready_in,
valid_in => mem_valid_in, valid_in => mem_valid_in,
data_in => mem_write_data, data_in_user => mem_write_data,
ready_out => mem_ready_out, ready_out => mem_ready_out,
valid_out => mem_valid_out, valid_out => mem_valid_out,
data_out => mem_read_data data_out_rtps => mem_read_data
); );
-- Big Endian Representation -- Big Endian Representation
data_in_swapped <= endian_swap(endian_flag, data_in); data_in_swapped <= endian_swap(endian_flag, data_in_user);
-- *Main State Machine* -- *Main State Machine*
-- STATE DESCRIPTION -- STATE DESCRIPTION
@ -392,24 +392,24 @@ begin
lifespan_next <= lifespan; lifespan_next <= lifespan;
-- DEFAULT Unregistered -- DEFAULT Unregistered
mem_opcode <= NOP; mem_opcode <= NOP;
dds_opcode <= ADD_CACHE_CHANGE; opcode_dds <= ADD_CACHE_CHANGE;
lease_deadline <= TIME_INVALID; lease_deadline <= TIME_INVALID;
res_time <= TIME_INVALID; res_time <= TIME_INVALID;
meta_rd <= '0'; rd_meta <= '0';
rd <= '0'; rd_user <= '0';
mem_op_start <= '0'; mem_op_start <= '0';
dds_start <= '0'; start_dds <= '0';
dds_ready_out <= '0'; ready_out_dds <= '0';
dds_valid_in <= '0'; valid_out_dds <= '0';
dds_last_word_in <= '0'; last_word_out_dds <= '0';
rd_guard := '0'; rd_guard := '0';
mem_field_flags <= (others => '0'); mem_field_flags <= (others => '0');
dds_data_in <= (others => '0'); data_out_dds <= (others => '0');
-- Last Word Latch Setter -- Last Word Latch Setter
if (last_word_in = '1') then if (last_word_in_user = '1') then
last_word_in_latch_next <= '1'; last_word_in_latch_next <= '1';
end if; end if;
@ -437,19 +437,19 @@ begin
check_time_next <= TIME_INFINITE; check_time_next <= TIME_INFINITE;
end if; end if;
-- Input FIFO Guard -- Input FIFO Guard
elsif (meta_empty = '0') then elsif (empty_meta = '0') then
meta_rd <= '1'; rd_meta <= '1';
-- Mark as METATRAFFIC -- Mark as METATRAFFIC
is_meta_next <= '1'; is_meta_next <= '1';
-- Latch Endpoint Metatraffic Opcode -- Latch Endpoint Metatraffic Opcode
meta_opcode_next <= meta_data_in; meta_opcode_next <= data_in_meta;
stage_next <= LATCH_GUIDPREFIX; stage_next <= LATCH_GUIDPREFIX;
cnt_next <= 0; cnt_next <= 0;
-- Input FIFO Guard -- Input FIFO Guard
elsif (empty = '0') then elsif (empty_user = '0') then
rd_guard := '1'; rd_guard := '1';
-- Latch Opcode -- Latch Opcode
@ -467,9 +467,9 @@ begin
end if; end if;
when LATCH_GUIDPREFIX => when LATCH_GUIDPREFIX =>
-- Input FIFO Guard -- Input FIFO Guard
if ((is_meta = '1' and meta_empty = '0') or (is_meta = '0' and empty = '0')) then if ((is_meta = '1' and empty_meta = '0') or (is_meta = '0' and empty_user = '0')) then
if (is_meta = '1') then if (is_meta = '1') then
meta_rd <= '1'; rd_meta <= '1';
else else
rd_guard := '1'; rd_guard := '1';
end if; end if;
@ -479,23 +479,23 @@ begin
-- GUID Prefix 1/3 -- GUID Prefix 1/3
when 0 => when 0 =>
if (is_meta = '1') then if (is_meta = '1') then
guid_next(0) <= meta_data_in; guid_next(0) <= data_in_meta;
else else
guid_next(0) <= data_in; guid_next(0) <= data_in_user;
end if; end if;
-- GUID Prefix 2/3 -- GUID Prefix 2/3
when 1 => when 1 =>
if (is_meta = '1') then if (is_meta = '1') then
guid_next(1) <= meta_data_in; guid_next(1) <= data_in_meta;
else else
guid_next(1) <= data_in; guid_next(1) <= data_in_user;
end if; end if;
-- GUID Prefix 3/3 -- GUID Prefix 3/3
when 2 => when 2 =>
if (is_meta = '1') then if (is_meta = '1') then
guid_next(2) <= meta_data_in; guid_next(2) <= data_in_meta;
else else
guid_next(2) <= data_in; guid_next(2) <= data_in_user;
end if; end if;
if (is_meta = '1' and (meta_opcode = OPCODE_PARTICIPANT_UNMATCH or meta_opcode = OPCODE_LIVELINESS_UPDATE)) then if (is_meta = '1' and (meta_opcode = OPCODE_PARTICIPANT_UNMATCH or meta_opcode = OPCODE_LIVELINESS_UPDATE)) then
@ -508,14 +508,14 @@ begin
end if; end if;
when LATCH_ENTITYID => when LATCH_ENTITYID =>
-- Input FIFO Guard -- Input FIFO Guard
if ((is_meta = '1' and meta_empty = '0') or (is_meta = '0' and empty = '0')) then if ((is_meta = '1' and empty_meta = '0') or (is_meta = '0' and empty_user = '0')) then
if (is_meta = '1') then if (is_meta = '1') then
meta_rd <= '1'; rd_meta <= '1';
guid_next(3) <= meta_data_in; guid_next(3) <= data_in_meta;
-- Memory Operation Guard -- Memory Operation Guard
else else
rd_guard := '1'; rd_guard := '1';
guid_next(3) <= data_in; guid_next(3) <= data_in_user;
end if; end if;
stage_next <= INITIATE_ENDPOINT_SEARCH; stage_next <= INITIATE_ENDPOINT_SEARCH;
end if; end if;
@ -584,17 +584,17 @@ begin
-- Synthesis Guard -- Synthesis Guard
if (RELIABILTY_QOS = RELIABLE_RELIABILITY_QOS) then if (RELIABILTY_QOS = RELIABLE_RELIABILITY_QOS) then
-- Input FIFO Guard -- Input FIFO Guard
if (meta_empty = '0') then if (empty_meta = '0') then
meta_rd <= '1'; rd_meta <= '1';
cnt_next <= cnt + 1; cnt_next <= cnt + 1;
case (cnt) is case (cnt) is
-- IPv4 Address -- IPv4 Address
when 0 => when 0 =>
addr_next <= meta_data_in; addr_next <= data_in_meta;
-- UDP Port -- UDP Port
when 1 => when 1 =>
portn_next <= meta_data_in(WORD_WIDTH-1 downto WORD_WIDTH-UDP_PORT_WIDTH-1); portn_next <= data_in_meta(WORD_WIDTH-1 downto WORD_WIDTH-UDP_PORT_WIDTH-1);
stage_next <= METATRAFFIC_OPERATION; stage_next <= METATRAFFIC_OPERATION;
when others => when others =>
@ -643,21 +643,17 @@ begin
-- Ignore -- Ignore
stage_next <= IDLE; stage_next <= IDLE;
else else
-- Output Guard -- Propagate Removal
if (dds_ready_in = '1') then start_dds <= '1';
-- Propagate Removal opcode_dds <= REMOVE_WRITER;
dds_start <= '1'; data_out_dds <= std_logic_vector(to_unsigned(mem_pos, WORD_WIDTH));
dds_opcode <= REMOVE_WRITER; -- Wait for Operation Acknowledgement
dds_valid_in <= '1'; if (res_dds = ACK) then
dds_data_in <= std_logic_vector(to_unsigned(mem_pos, WORD_WIDTH)); -- Remove Unmatched Remote Endpoint
-- Wait for Operation Acknowledgement mem_op_start <= '1';
if (dds_res = ACK) then mem_opcode <= REMOVE_ENDPOINT;
-- Remove Unmatched Remote Endpoint -- DONE
mem_op_start <= '1'; stage_next <= IDLE;
mem_opcode <= REMOVE_ENDPOINT;
-- DONE
stage_next <= IDLE;
end if;
end if; end if;
end if; end if;
when OPCODE_PARTICIPANT_UNMATCH => when OPCODE_PARTICIPANT_UNMATCH =>
@ -670,19 +666,15 @@ begin
else else
-- Participant Match -- Participant Match
if (guid(0) = mem_endpoint_data.guid(0) and guid(1) = mem_endpoint_data.guid(1) and guid(2) = mem_endpoint_data.guid(2)) then if (guid(0) = mem_endpoint_data.guid(0) and guid(1) = mem_endpoint_data.guid(1) and guid(2) = mem_endpoint_data.guid(2)) then
-- Output Guard -- Propagate Removal
if (dds_ready_in = '1') then start_dds <= '1';
-- Propagate Removal opcode_dds <= REMOVE_WRITER;
dds_start <= '1'; data_out_dds <= std_logic_vector(to_unsigned(mem_pos, WORD_WIDTH));
dds_opcode <= REMOVE_WRITER; -- Wait for Operation Acknowledgement
dds_valid_in <= '1'; if (res_dds = ACK) then
dds_data_in <= std_logic_vector(to_unsigned(mem_pos, WORD_WIDTH)); -- Remove Unmatched Remote Endpoint
-- Wait for Operation Acknowledgement mem_op_start <= '1';
if (dds_res = ACK) then mem_opcode <= REMOVE_ENDPOINT;
-- Remove Unmatched Remote Endpoint
mem_op_start <= '1';
mem_opcode <= REMOVE_ENDPOINT;
end if;
end if; end if;
end if; end if;
cnt_next <= 1; cnt_next <= 1;
@ -738,37 +730,37 @@ begin
end if; end if;
when LATCH_SRC_ADDR => when LATCH_SRC_ADDR =>
-- Input FIFO Guard -- Input FIFO Guard
if (empty = '0') then if (empty_user = '0') then
rd_guard := '1'; rd_guard := '1';
-- Latch Source IP Address -- Latch Source IP Address
addr_next <= data_in; addr_next <= data_in_user;
stage_next <= LATCH_GUIDPREFIX; stage_next <= LATCH_GUIDPREFIX;
cnt_next <= 0; cnt_next <= 0;
end if; end if;
when LATCH_EXTRA_DATA => when LATCH_EXTRA_DATA =>
-- Input FIFO Guard -- Input FIFO Guard
if (empty = '0') then if (empty_user = '0') then
rd_guard := '1'; rd_guard := '1';
cnt_next <= cnt + 1; cnt_next <= cnt + 1;
case (cnt) is case (cnt) is
-- Sequence Number 1/2 -- Sequence Number 1/2
when 0 => when 0 =>
seq_nr_next(0) <= unsigned(data_in); seq_nr_next(0) <= unsigned(data_in_user);
-- Sequence Number 2/2 -- Sequence Number 2/2
when 1 => when 1 =>
seq_nr_next(1) <= unsigned(data_in); seq_nr_next(1) <= unsigned(data_in_user);
-- Store Next Sequence Number -- Store Next Sequence Number
tmp_dw := (0 => seq_nr(0), 1 => unsigned(data_in)); tmp_dw := (0 => seq_nr(0), 1 => unsigned(data_in_user));
next_seq_nr_next <= tmp_dw + 1; next_seq_nr_next <= tmp_dw + 1;
-- Timestamp 1/2 -- Timestamp 1/2
when 2 => when 2 =>
ts_next(0) <= unsigned(data_in); ts_next(0) <= unsigned(data_in_user);
-- Timestamp 2/2 -- Timestamp 2/2
when 3 => when 3 =>
ts_next(1) <= unsigned(data_in); ts_next(1) <= unsigned(data_in_user);
if (qos_flag = '1') then if (qos_flag = '1') then
stage_next <= PROCESS_INLINE_QOS; stage_next <= PROCESS_INLINE_QOS;
@ -781,23 +773,23 @@ begin
end if; end if;
when LATCH_HEARTBEAT => when LATCH_HEARTBEAT =>
-- Input FIFO Guard -- Input FIFO Guard
if (empty = '0') then if (empty_user = '0') then
rd_guard := '1'; rd_guard := '1';
cnt_next <= cnt + 1; cnt_next <= cnt + 1;
case (cnt) is case (cnt) is
-- First Sequence Number 1/2 -- First Sequence Number 1/2
when 0 => when 0 =>
first_seq_nr_next(0) <= unsigned(data_in); first_seq_nr_next(0) <= unsigned(data_in_user);
-- First Sequence Number 2/2 -- First Sequence Number 2/2
when 1 => when 1 =>
first_seq_nr_next(1) <= unsigned(data_in); first_seq_nr_next(1) <= unsigned(data_in_user);
-- Last Sequence Number 1/2 -- Last Sequence Number 1/2
when 2 => when 2 =>
last_seq_nr_next(0) <= unsigned(data_in); last_seq_nr_next(0) <= unsigned(data_in_user);
-- Last Sequence Number 2/2 -- Last Sequence Number 2/2
when 3 => when 3 =>
last_seq_nr_next(1) <= unsigned(data_in); last_seq_nr_next(1) <= unsigned(data_in_user);
stage_next <= PROCESS_HEARTBEAT; stage_next <= PROCESS_HEARTBEAT;
when others => when others =>
@ -885,27 +877,27 @@ begin
end if; end if;
when LATCH_GAP => when LATCH_GAP =>
-- Input FIFO Guard -- Input FIFO Guard
if (empty = '0') then if (empty_user = '0') then
rd_guard := '1'; rd_guard := '1';
cnt_next <= cnt + 1; cnt_next <= cnt + 1;
case (cnt) is case (cnt) is
-- GapStart Sequence Number 1/2 -- GapStart Sequence Number 1/2
when 0 => when 0 =>
gap_start_next(0) <= unsigned(data_in); gap_start_next(0) <= unsigned(data_in_user);
-- GapStart Sequence Number 2/2 -- GapStart Sequence Number 2/2
when 1 => when 1 =>
gap_start_next(1) <= unsigned(data_in); gap_start_next(1) <= unsigned(data_in_user);
-- GapList.Base 1/2 -- GapList.Base 1/2
when 2 => when 2 =>
gap_list_base_next(0) <= unsigned(data_in); gap_list_base_next(0) <= unsigned(data_in_user);
-- GapList.Base 2/2 -- GapList.Base 2/2
when 3 => when 3 =>
gap_list_base_next(1) <= unsigned(data_in); gap_list_base_next(1) <= unsigned(data_in_user);
-- ReaderSNState.NumBits -- ReaderSNState.NumBits
when 4 => when 4 =>
gap_list_end_next <= gap_list_base + to_integer(unsigned(data_in)); gap_list_end_next <= gap_list_base + to_integer(unsigned(data_in_user));
bitmap_cnt_next <= unsigned(round_slv(data_in(log2c(MAX_BITMAP_WIDTH)-1 downto 0),bitmap_cnt'length)); bitmap_cnt_next <= unsigned(round_slv(data_in_user(log2c(MAX_BITMAP_WIDTH)-1 downto 0),bitmap_cnt'length));
cnt2_next <= 0; cnt2_next <= 0;
-- ReaderSNState.Bitmap -- ReaderSNState.Bitmap
when 5 => when 5 =>
@ -971,7 +963,7 @@ begin
end if; end if;
when PROCESS_INLINE_QOS => when PROCESS_INLINE_QOS =>
-- input FIFO Guard -- input FIFO Guard
if (empty = '0') then if (empty_user = '0') then
rd_guard := '1'; rd_guard := '1';
-- Reset Word Counter -- Reset Word Counter
reset_read_cnt <= '1'; reset_read_cnt <= '1';
@ -1068,7 +1060,7 @@ begin
end if; end if;
when LATCH_LIFESPAN => when LATCH_LIFESPAN =>
-- Input FIFO Guard -- Input FIFO Guard
if (empty = '0') then if (empty_user = '0') then
rd_guard := '1'; rd_guard := '1';
cnt_next <= cnt + 1; cnt_next <= cnt + 1;
@ -1093,23 +1085,23 @@ begin
end if; end if;
when LATCH_KEY_HASH => when LATCH_KEY_HASH =>
-- Input FIFO Guard -- Input FIFO Guard
if (empty = '0') then if (empty_user = '0') then
rd_guard := '1'; rd_guard := '1';
cnt_next <= cnt + 1; cnt_next <= cnt + 1;
case (cnt) is case (cnt) is
-- Key Hash 1/4 -- Key Hash 1/4
when 0 => when 0 =>
key_hash_next(0) <= data_in; key_hash_next(0) <= data_in_user;
-- Key Hash 2/4 -- Key Hash 2/4
when 1 => when 1 =>
key_hash_next(1) <= data_in; key_hash_next(1) <= data_in_user;
-- Key Hash 3/4 -- Key Hash 3/4
when 2 => when 2 =>
key_hash_next(2) <= data_in; key_hash_next(2) <= data_in_user;
-- Key Hash 4/4 -- Key Hash 4/4
when 3 => when 3 =>
key_hash_next(3) <= data_in; key_hash_next(3) <= data_in_user;
-- DONE -- DONE
stage_next <= SKIP_PARAMETER; stage_next <= SKIP_PARAMETER;
@ -1119,106 +1111,149 @@ begin
end if; end if;
when LATCH_STATUS_INFO => when LATCH_STATUS_INFO =>
-- Input FIFO Guard -- Input FIFO Guard
if (empty = '0') then if (empty_user = '0') then
rd_guard := '1'; rd_guard := '1';
status_info_next <= data_in; status_info_next <= data_in_user;
-- DONE -- DONE
stage_next <= SKIP_PARAMETER; stage_next <= SKIP_PARAMETER;
end if; end if;
when INITIATE_ADD_CACHE_CHANGE_REQUEST => when INITIATE_ADD_CACHE_CHANGE_REQUEST =>
dds_start <= '1'; start_dds <= '1';
dds_opcode <= ADD_CACHE_CHANGE; opcode_dds <= ADD_CACHE_CHANGE;
-- Wait until History Cache acknowledges request -- Wait until History Cache acknowledges request
if (dds_res = ACK) then if (res_dds = ACK) then
stage_next <= ADD_CACHE_CHANGE; stage_next <= ADD_CACHE_CHANGE;
cnt_next <= 0; cnt_next <= 0;
end if; end if;
when ADD_CACHE_CHANGE => when ADD_CACHE_CHANGE =>
if (dds_ready_in = '1') then case (cnt) is
dds_valid_in <= '1'; -- Status Info
cnt_next <= cnt + 1; when 0 =>
valid_out_dds <= '1';
case (cnt) is data_out_dds <= status_info;
-- Status Info data_out_dds(KEY_HASH_FLAG) <= key_hash_rcvd;
when 0 => data_out_dds(PAYLOAD_FLAG) <= data_flag;
dds_data_in <= status_info; -- Output Guard
dds_data_in(KEY_HASH_FLAG) <= key_hash_rcvd; if (ready_out_dds = '1') then
dds_data_in(PAYLOAD_FLAG) <= data_flag; cnt_next <= cnt + 1;
-- Timestamp 1/2 end if;
when 1 => -- Timestamp 1/2
dds_data_in <= ts(0); when 1 =>
-- Timestamp 2/2 valid_out_dds <= '1';
when 2 => data_out_dds <= ts(0);
dds_data_in <= ts(1); -- Output Guard
-- Lifespan Deadline 1/2 if (ready_out_dds = '1') then
when 3 => cnt_next <= cnt + 1;
dds_data_in <= lifespan(0); end if;
-- Lifespan Deadline 2/2 -- Timestamp 2/2
when 4 => when 2 =>
dds_data_in <= lifespan(1); valid_out_dds <= '1';
data_out_dds <= ts(1);
-- Output Guard
if (ready_out_dds = '1') then
cnt_next <= cnt + 1;
end if;
-- Lifespan Deadline 1/2
when 3 =>
valid_out_dds <= '1';
data_out_dds <= lifespan(0);
-- Output Guard
if (ready_out_dds = '1') then
cnt_next <= cnt + 1;
end if;
-- Lifespan Deadline 2/2
when 4 =>
valid_out_dds <= '1';
data_out_dds <= lifespan(1);
-- Output Guard
if (ready_out_dds = '1') then
-- Skip Key Hash, if not received -- Skip Key Hash, if not received
if (not WITH_KEY or key_hash_rcvd = '0') then if (not WITH_KEY or key_hash_rcvd = '0') then
cnt_next <= 9; cnt_next <= cnt + 5;
else
cnt_next <= cnt + 1;
end if; end if;
-- Key hash 1/4 end if;
when 5 => -- Key hash 1/4
dds_data_in <= key_hash(0); when 5 =>
-- Key Hash 2/4 valid_out_dds <= '1';
when 6 => data_out_dds <= key_hash(0);
dds_data_in <= key_hash(1); -- Output Guard
-- Key Hash 3/4 if (ready_out_dds = '1') then
when 7 => cnt_next <= cnt + 1;
dds_data_in <= key_hash(2); end if;
-- Key hash 4/4 -- Key Hash 2/4
when 8 => when 6 =>
dds_data_in <= key_hash(3); valid_out_dds <= '1';
-- Endpoint Memory Position data_out_dds <= key_hash(1);
when 9 => -- Output Guard
-- Wait for Endpoint Search if (ready_out_dds = '1') then
if (mem_op_done = '1') then cnt_next <= cnt + 1;
end if;
-- TODO: Assert mem_pos range fits in CDR_LONG -- Key Hash 3/4
dds_data_in <= std_logic_vector(to_unsigned(mem_pos, CDR_LONG_WIDTH)); when 7 =>
valid_out_dds <= '1';
data_out_dds <= key_hash(2);
-- Output Guard
if (ready_out_dds = '1') then
cnt_next <= cnt + 1;
end if;
-- Key hash 4/4
when 8 =>
valid_out_dds <= '1';
data_out_dds <= key_hash(3);
-- Output Guard
if (ready_out_dds = '1') then
cnt_next <= cnt + 1;
end if;
-- Endpoint Memory Position
when 9 =>
-- Wait for Endpoint Search
if (mem_op_done = '1') then
valid_out_dds <= '1';
-- TODO: Assert mem_pos range fits in CDR_LONG
data_out_dds <= std_logic_vector(to_unsigned(mem_pos, CDR_LONG_WIDTH));
-- Output Guard
if (ready_out_dds = '1') then
-- Payload exists -- Payload exists
if (data_flag = '1' or (WITH_KEY and key_flag = '1')) then if (data_flag = '1' or (WITH_KEY and key_flag = '1')) then
stage_next <= PUSH_PAYLOAD; stage_next <= PUSH_PAYLOAD;
else else
-- DONE -- DONE
dds_last_word_in <= '1'; last_word_out_dds <= '1';
stage_next <= FINALIZE_ADD_CACHE_CHANGE_REQUEST; stage_next <= FINALIZE_ADD_CACHE_CHANGE_REQUEST;
end if; end if;
else
-- Keep State
dds_valid_in <= '0';
cnt_next <= cnt;
end if; end if;
when others => end if;
null; when others =>
end case; null;
end if; end case;
when PUSH_PAYLOAD => when PUSH_PAYLOAD =>
-- Input/Output Guard -- Input Guard
if (empty = '0' and dds_ready_in = '1') then if (empty_user = '0') then
rd_guard := '1'; valid_out_dds <= '1';
dds_valid_in <= '1';
-- Push Payload to History Cache -- Push Payload to History Cache
dds_data_in <= data_in; data_out_dds <= data_in_user;
last_word_out_dds <= last_word_in_user;
-- Exit Condition -- Output Guard
if (last_word_in = '1') then if (ready_out_dds = '1') then
dds_last_word_in <= '1'; rd_guard := '1';
stage_next <= FINALIZE_ADD_CACHE_CHANGE_REQUEST;
-- Exit Condition
if (last_word_in_user = '1') then
stage_next <= FINALIZE_ADD_CACHE_CHANGE_REQUEST;
end if;
end if; end if;
end if; end if;
when FINALIZE_ADD_CACHE_CHANGE_REQUEST => when FINALIZE_ADD_CACHE_CHANGE_REQUEST =>
-- NOTE: Memory is already in done state from previous state (ADD_CACHE_CHANGE) -- NOTE: Memory is already in done state from previous state (ADD_CACHE_CHANGE)
assert (mem_op_done = '1') report "FINALIZE_ADD_CACHE_CHANGE_REQUEST precondition not met. mem_op_done /= '1'" severity FAILURE; assert (mem_op_done = '1') report "FINALIZE_ADD_CACHE_CHANGE_REQUEST precondition not met. mem_op_done /= '1'" severity FAILURE;
-- Wait for History Cache Response -- Wait for History Cache Response
if (dds_res /= UNDEFINED) then if (res_dds /= UNDEFINED) then
-- NOTE: The Lease Duration is also updated if the Cache Change is not accepted. This in effect "skews" the -- NOTE: The Lease Duration is also updated if the Cache Change is not accepted. This in effect "skews" the
-- "correctness" of the Writer Liveliness Protocol until the reader has no pending request from the Writer. -- "correctness" of the Writer Liveliness Protocol until the reader has no pending request from the Writer.
@ -1242,7 +1277,7 @@ begin
-- NOTE: In case the operation was unsucessfull (e.g. reached Resource Limits), the Sequence Number is not updated -- NOTE: In case the operation was unsucessfull (e.g. reached Resource Limits), the Sequence Number is not updated
-- and thus not "acknowledged". -- and thus not "acknowledged".
-- Operation was Accepted -- Operation was Accepted
if (dds_res = ACCEPTED) then if (res_dds = ACCEPTED) then
-- Update also next sequence number -- Update also next sequence number
mem_field_flags <= NEXT_SEQ_NR_FLAG or LEASE_DEADLINE_FLAG; mem_field_flags <= NEXT_SEQ_NR_FLAG or LEASE_DEADLINE_FLAG;
end if; end if;
@ -1348,7 +1383,7 @@ begin
-- Synthesis Guard -- Synthesis Guard
if (RELIABILTY_QOS = RELIABLE_RELIABILITY_QOS) then if (RELIABILTY_QOS = RELIABLE_RELIABILITY_QOS) then
-- Output FIFO Guard -- Output FIFO Guard
if (rtps_full = '0') then if (full_rtps = '0') then
wr_sig <= '1'; wr_sig <= '1';
cnt_next <= cnt + 1; cnt_next <= cnt + 1;
@ -1356,24 +1391,24 @@ begin
-- OUTPUT HEADER -- OUTPUT HEADER
-- Src IPv4 Address -- Src IPv4 Address
when 0 => when 0 =>
data_out <= DEFAULT_IPv4_ADDRESS; data_out_rtps <= DEFAULT_IPv4_ADDRESS;
-- Dest IPv4 Address -- Dest IPv4 Address
when 1 => when 1 =>
data_out <= mem_endpoint_data.addr; data_out_rtps <= mem_endpoint_data.addr;
-- Src and Dest UDPv4 Ports -- Src and Dest UDPv4 Ports
when 2 => when 2 =>
data_out <= USER_IPv4_UNICAST_PORT & mem_endpoint_data.portn; data_out_rtps <= USER_IPv4_UNICAST_PORT & mem_endpoint_data.portn;
-- RTPS MESSAGE HEADER -- RTPS MESSAGE HEADER
when 3 => when 3 =>
data_out <= PROTOCOL_RTPS; data_out_rtps <= PROTOCOL_RTPS;
when 4 => when 4 =>
data_out <= PROTOCOLVERSION_2_4 & VENDORID; data_out_rtps <= PROTOCOLVERSION_2_4 & VENDORID;
when 5 => when 5 =>
data_out <= GUIDPREFIX(0); data_out_rtps <= GUIDPREFIX(0);
when 6 => when 6 =>
data_out <= GUIDPREFIX(1); data_out_rtps <= GUIDPREFIX(1);
when 7 => when 7 =>
data_out <= GUIDPREFIX(2); data_out_rtps <= GUIDPREFIX(2);
-- Continue with respective RTPS Submessage -- Continue with respective RTPS Submessage
stage_next <= return_stage; stage_next <= return_stage;
cnt_next <= 0; cnt_next <= 0;
@ -1386,7 +1421,7 @@ begin
-- Synthesis Guard -- Synthesis Guard
if (RELIABILTY_QOS = RELIABLE_RELIABILITY_QOS) then if (RELIABILTY_QOS = RELIABLE_RELIABILITY_QOS) then
-- Output FIFO Guard -- Output FIFO Guard
if (rtps_full = '0') then if (full_rtps = '0') then
wr_sig <= '1'; wr_sig <= '1';
cnt_next <= cnt + 1; cnt_next <= cnt + 1;
@ -1394,31 +1429,31 @@ begin
-- ACKNACK RTPS SUBMESSAGE -- ACKNACK RTPS SUBMESSAGE
-- RTPS Submessage Header -- RTPS Submessage Header
when 0 => when 0 =>
data_out <= SID_ACKNACK & "00000010" & std_logic_vector(to_unsigned(28, SUBMESSAGE_LENGTH_WIDTH)); data_out_rtps <= SID_ACKNACK & "00000010" & std_logic_vector(to_unsigned(28, SUBMESSAGE_LENGTH_WIDTH));
-- Reader Entity ID -- Reader Entity ID
when 1 => when 1 =>
data_out <= ENTITYID; data_out_rtps <= ENTITYID;
-- Writer Entity ID -- Writer Entity ID
when 2 => when 2 =>
data_out <= ENTITYID_UNKNOWN; data_out_rtps <= ENTITYID_UNKNOWN;
-- Sequence Number Set (Bitmap Base 1/2) -- Sequence Number Set (Bitmap Base 1/2)
when 3 => when 3 =>
data_out <= std_logic_vector(mem_endpoint_data.next_seq_nr(0)); data_out_rtps <= std_logic_vector(mem_endpoint_data.next_seq_nr(0));
-- Sequence Number Set (Bitmap Base 2/2) -- Sequence Number Set (Bitmap Base 2/2)
when 4 => when 4 =>
data_out <= std_logic_vector(mem_endpoint_data.next_seq_nr(1)); data_out_rtps <= std_logic_vector(mem_endpoint_data.next_seq_nr(1));
-- Sequence Number Set (NumBits) -- Sequence Number Set (NumBits)
when 5 => when 5 =>
data_out <= std_logic_vector(to_unsigned(CDR_LONG_WIDTH, CDR_LONG_WIDTH)); data_out_rtps <= std_logic_vector(to_unsigned(CDR_LONG_WIDTH, CDR_LONG_WIDTH));
-- Sequence Number Set (Bitmap) -- Sequence Number Set (Bitmap)
when 6 => when 6 =>
-- NOTE: In order to avoid having to generate a variable sized bitmap, we always request the next 32 sequence numbers, even if they do not exist (yet) -- NOTE: In order to avoid having to generate a variable sized bitmap, we always request the next 32 sequence numbers, even if they do not exist (yet)
-- XXX: Assumes correct implementation of the RTPS Protocol (i.e. Writer ignores requested SNs that do not exist) -- XXX: Assumes correct implementation of the RTPS Protocol (i.e. Writer ignores requested SNs that do not exist)
data_out <= (others => '1'); data_out_rtps <= (others => '1');
-- Count -- Count
when 7 => when 7 =>
data_out <= std_logic_vector(count); data_out_rtps <= std_logic_vector(count);
last_word_out <= '1'; last_word_out_rtps <= '1';
-- Stale Check in Progress -- Stale Check in Progress
if (stale_check = '1') then if (stale_check = '1') then
@ -1436,7 +1471,7 @@ begin
end if; end if;
when SKIP_PARAMETER => when SKIP_PARAMETER =>
-- Consumed last word of Packet -- Consumed last word of Packet
if (last_word_in_latch = '1' and last_word_in = '0') then if (last_word_in_latch = '1' and last_word_in_user = '0') then
-- Reset Last Word In Latch -- Reset Last Word In Latch
last_word_in_latch_next <= '0'; last_word_in_latch_next <= '0';
-- Continue parsing next Packet -- Continue parsing next Packet
@ -1446,12 +1481,12 @@ begin
-- End of Parameter -- End of Parameter
elsif ((read_cnt & "00" ) >= parameter_end) then elsif ((read_cnt & "00" ) >= parameter_end) then
-- Parse Next Parameter -- Parse Next Parameter
-- NOTE: data_in is already showing the next parameter -- NOTE: data_in_user is already showing the next parameter
stage_next <= PROCESS_PL; stage_next <= PROCESS_PL;
-- Reset Parameter End -- Reset Parameter End
parameter_end_next <= (others => '1'); parameter_end_next <= (others => '1');
-- Input FIFO Guard -- Input FIFO Guard
elsif (empty = '0') then elsif (empty_user = '0') then
-- Skip-Read -- Skip-Read
rd_guard := '1'; rd_guard := '1';
end if; end if;
@ -1465,13 +1500,13 @@ begin
-- DONE -- DONE
stage_next <= IDLE; stage_next <= IDLE;
-- Consumed last word of Packet -- Consumed last word of Packet
elsif (last_word_in_latch = '1' and last_word_in = '0') then elsif (last_word_in_latch = '1' and last_word_in_user = '0') then
-- Reset Last Word In Latch -- Reset Last Word In Latch
last_word_in_latch_next <= '0'; last_word_in_latch_next <= '0';
-- DONE -- DONE
stage_next <= IDLE; stage_next <= IDLE;
-- Input FIFO Guard -- Input FIFO Guard
elsif (empty = '0') then elsif (empty_user = '0') then
-- Skip-Read -- Skip-Read
rd_guard := '1'; rd_guard := '1';
end if; end if;
@ -1484,7 +1519,7 @@ begin
-- NOTE: If the Packet Length is smaller than expected there will be a read from input FIFO while -- NOTE: If the Packet Length is smaller than expected there will be a read from input FIFO while
-- the Packet Length has been reached and will be caught by this clause. -- the Packet Length has been reached and will be caught by this clause.
-- The SKIP_PACKET clause prevents a read signal from occuring in this situation, and thus prevents from entering this state. -- The SKIP_PACKET clause prevents a read signal from occuring in this situation, and thus prevents from entering this state.
if ((last_word_in_latch = '1' and last_word_in = '0') and rd_guard = '1') then if ((last_word_in_latch = '1' and last_word_in_user = '0') and rd_guard = '1') then
-- Force rd_sig low -- Force rd_sig low
rd_sig <= '0'; rd_sig <= '0';
-- Continue parsing next Packet -- Continue parsing next Packet
@ -1518,7 +1553,7 @@ begin
-- INSERT_ENDPOINT See Memory OPCODE Description -- INSERT_ENDPOINT See Memory OPCODE Description
-- UPDATE_ENDPOINT See Memory OPCODE Description -- UPDATE_ENDPOINT See Memory OPCODE Description
-- REMOVE_ENDPOINT See Memory OPCODE Description -- REMOVE_ENDPOINT See Memory OPCODE Description
-- FIND_EMPTY_SLOT Find first empty slot in memory. -- FIND_EMPTY_SLOT Find first empty_user slot in memory.
-- RESET_MAX_POINTER Reset the max_endpoint_addr pointer to last occupied slot in memory. -- RESET_MAX_POINTER Reset the max_endpoint_addr pointer to last occupied slot in memory.
-- GET_NEXT_ENDPOINT See Memory OPCODE Description -- GET_NEXT_ENDPOINT See Memory OPCODE Description
mem_ctrl_prc : process(all) mem_ctrl_prc : process(all)
@ -2452,7 +2487,7 @@ begin
null; null;
end case; end case;
when REMOVE_ENDPOINT => when REMOVE_ENDPOINT =>
-- Mark with ENTITYID_UNKNOWN to mark slot empty -- Mark with ENTITYID_UNKNOWN to mark slot empty_user
mem_valid_in <= '1'; mem_valid_in <= '1';
mem_addr <= mem_addr_base + EMF_ENTITYID_OFFSET; mem_addr <= mem_addr_base + EMF_ENTITYID_OFFSET;
mem_write_data <= ENTITYID_UNKNOWN; mem_write_data <= ENTITYID_UNKNOWN;
@ -2655,7 +2690,7 @@ begin
-- Reset Read counter -- Reset Read counter
if (reset = '1' or reset_read_cnt = '1') then if (reset = '1' or reset_read_cnt = '1') then
read_cnt <= (others => '0'); read_cnt <= (others => '0');
-- Increment read counter each time rd is high -- Increment read counter each time rd_user is high
elsif (rd_sig = '1') then elsif (rd_sig = '1') then
read_cnt <= read_cnt + 1; read_cnt <= read_cnt + 1;
end if; end if;