diff --git a/ros_action_Fibonacci_with_feedback.txt b/ros_action_Fibonacci_with_feedback.txt index 8bf760e..73eced3 100644 --- a/ros_action_Fibonacci_with_feedback.txt +++ b/ros_action_Fibonacci_with_feedback.txt @@ -73,4 +73,16 @@ ; |dds_writer:\dds_endpoint_w_if:dds_writer_inst| ; 6798 (4926) ; 4149 (1812) ; 428928 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst ; dds_writer ; work ; ; |rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst| ; 5381 (5249) ; 2360 (2279) ; 84672 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst ; rtps_reader ; work ; ; |rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst| ; 6872 (6612) ; 3150 (2988) ; 169344 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst ; rtps_writer ; work ; ++------------------------------------------------------------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------+--------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Resource Utilization by Entity ; ++------------------------------------------------------------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------+--------------+ +; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ; ++------------------------------------------------------------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------+--------------+ +; |test_top ; 41730 (64) ; 20866 (63) ; 2377339 ; 4 ; 71 ; 0 ; |test_top ; test_top ; work ; +; |dds_reader:\dds_endpoint_r_if:dds_reader_inst| ; 6437 (5369) ; 2872 (1512) ; 29184 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst ; dds_reader ; work ; +; |dds_writer:\dds_endpoint_w_if:dds_writer_inst| ; 6775 (4904) ; 4152 (1815) ; 428928 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst ; dds_writer ; work ; +; |rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst| ; 5594 (5424) ; 2398 (2282) ; 85024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst ; rtps_reader ; work ; +; |rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst| ; 6869 (6609) ; 3154 (2992) ; 169344 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst ; rtps_writer ; work ; +------------------------------------------------------------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------+--------------+ \ No newline at end of file diff --git a/ros_action_Fibonacci_with_feedback6.rpt b/ros_action_Fibonacci_with_feedback6.rpt new file mode 100644 index 0000000..1c0e518 --- /dev/null +++ b/ros_action_Fibonacci_with_feedback6.rpt @@ -0,0 +1,731 @@ +Resource Utilization by Entity report for top +Thu Apr 14 14:21:46 2022 +Quartus Prime Version 21.1.0 Build 842 10/21/2021 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Analysis & Synthesis Resource Utilization by Entity + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2021 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. + + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Resource Utilization by Entity ; ++------------------------------------------------------------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------+--------------+ +; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ; ++------------------------------------------------------------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------+--------------+ +; |test_top ; 41730 (64) ; 20866 (63) ; 2377339 ; 4 ; 71 ; 0 ; |test_top ; test_top ; work ; +; |Avalon_MM_wrapper:Avalon_MM_wrapper_inst| ; 67 (67) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |test_top|Avalon_MM_wrapper:Avalon_MM_wrapper_inst ; Avalon_MM_wrapper ; work ; +; |FWFT_FIFO:FIFO_IN_inst| ; 122 (0) ; 62 (0) ; 524288 ; 0 ; 0 ; 0 ; |test_top|FWFT_FIFO:FIFO_IN_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 122 (0) ; 62 (0) ; 524288 ; 0 ; 0 ; 0 ; |test_top|FWFT_FIFO:FIFO_IN_inst|scfifo:scfifo_component ; scfifo ; work ; +; |scfifo_ink1:auto_generated| ; 122 (0) ; 62 (0) ; 524288 ; 0 ; 0 ; 0 ; |test_top|FWFT_FIFO:FIFO_IN_inst|scfifo:scfifo_component|scfifo_ink1:auto_generated ; scfifo_ink1 ; work ; +; |a_dpfifo_ojb1:dpfifo| ; 122 (44) ; 62 (20) ; 524288 ; 0 ; 0 ; 0 ; |test_top|FWFT_FIFO:FIFO_IN_inst|scfifo:scfifo_component|scfifo_ink1:auto_generated|a_dpfifo_ojb1:dpfifo ; a_dpfifo_ojb1 ; work ; +; |altsyncram_eek1:FIFOram| ; 34 (0) ; 1 (1) ; 524288 ; 0 ; 0 ; 0 ; |test_top|FWFT_FIFO:FIFO_IN_inst|scfifo:scfifo_component|scfifo_ink1:auto_generated|a_dpfifo_ojb1:dpfifo|altsyncram_eek1:FIFOram ; altsyncram_eek1 ; work ; +; |decode_s07:decode2| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |test_top|FWFT_FIFO:FIFO_IN_inst|scfifo:scfifo_component|scfifo_ink1:auto_generated|a_dpfifo_ojb1:dpfifo|altsyncram_eek1:FIFOram|decode_s07:decode2 ; decode_s07 ; work ; +; |mux_ps7:mux3| ; 32 (32) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |test_top|FWFT_FIFO:FIFO_IN_inst|scfifo:scfifo_component|scfifo_ink1:auto_generated|a_dpfifo_ojb1:dpfifo|altsyncram_eek1:FIFOram|mux_ps7:mux3 ; mux_ps7 ; work ; +; |cntr_04b:wr_ptr| ; 15 (15) ; 14 (14) ; 0 ; 0 ; 0 ; 0 ; |test_top|FWFT_FIFO:FIFO_IN_inst|scfifo:scfifo_component|scfifo_ink1:auto_generated|a_dpfifo_ojb1:dpfifo|cntr_04b:wr_ptr ; cntr_04b ; work ; +; |cntr_c47:usedw_counter| ; 15 (15) ; 14 (14) ; 0 ; 0 ; 0 ; 0 ; |test_top|FWFT_FIFO:FIFO_IN_inst|scfifo:scfifo_component|scfifo_ink1:auto_generated|a_dpfifo_ojb1:dpfifo|cntr_c47:usedw_counter ; cntr_c47 ; work ; +; |cntr_v3b:rd_ptr_msb| ; 14 (14) ; 13 (13) ; 0 ; 0 ; 0 ; 0 ; |test_top|FWFT_FIFO:FIFO_IN_inst|scfifo:scfifo_component|scfifo_ink1:auto_generated|a_dpfifo_ojb1:dpfifo|cntr_v3b:rd_ptr_msb ; cntr_v3b ; work ; +; |FWFT_FIFO:FIFO_OUT_inst| ; 93 (0) ; 62 (0) ; 524288 ; 0 ; 0 ; 0 ; |test_top|FWFT_FIFO:FIFO_OUT_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 93 (0) ; 62 (0) ; 524288 ; 0 ; 0 ; 0 ; |test_top|FWFT_FIFO:FIFO_OUT_inst|scfifo:scfifo_component ; scfifo ; work ; +; |scfifo_ink1:auto_generated| ; 93 (0) ; 62 (0) ; 524288 ; 0 ; 0 ; 0 ; |test_top|FWFT_FIFO:FIFO_OUT_inst|scfifo:scfifo_component|scfifo_ink1:auto_generated ; scfifo_ink1 ; work ; +; |a_dpfifo_ojb1:dpfifo| ; 93 (47) ; 62 (20) ; 524288 ; 0 ; 0 ; 0 ; |test_top|FWFT_FIFO:FIFO_OUT_inst|scfifo:scfifo_component|scfifo_ink1:auto_generated|a_dpfifo_ojb1:dpfifo ; a_dpfifo_ojb1 ; work ; +; |altsyncram_eek1:FIFOram| ; 2 (0) ; 1 (1) ; 524288 ; 0 ; 0 ; 0 ; |test_top|FWFT_FIFO:FIFO_OUT_inst|scfifo:scfifo_component|scfifo_ink1:auto_generated|a_dpfifo_ojb1:dpfifo|altsyncram_eek1:FIFOram ; altsyncram_eek1 ; work ; +; |decode_s07:wren_decode_a| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |test_top|FWFT_FIFO:FIFO_OUT_inst|scfifo:scfifo_component|scfifo_ink1:auto_generated|a_dpfifo_ojb1:dpfifo|altsyncram_eek1:FIFOram|decode_s07:wren_decode_a ; decode_s07 ; work ; +; |cntr_04b:wr_ptr| ; 15 (15) ; 14 (14) ; 0 ; 0 ; 0 ; 0 ; |test_top|FWFT_FIFO:FIFO_OUT_inst|scfifo:scfifo_component|scfifo_ink1:auto_generated|a_dpfifo_ojb1:dpfifo|cntr_04b:wr_ptr ; cntr_04b ; work ; +; |cntr_c47:usedw_counter| ; 15 (15) ; 14 (14) ; 0 ; 0 ; 0 ; 0 ; |test_top|FWFT_FIFO:FIFO_OUT_inst|scfifo:scfifo_component|scfifo_ink1:auto_generated|a_dpfifo_ojb1:dpfifo|cntr_c47:usedw_counter ; cntr_c47 ; work ; +; |cntr_v3b:rd_ptr_msb| ; 14 (14) ; 13 (13) ; 0 ; 0 ; 0 ; 0 ; |test_top|FWFT_FIFO:FIFO_OUT_inst|scfifo:scfifo_component|scfifo_ink1:auto_generated|a_dpfifo_ojb1:dpfifo|cntr_v3b:rd_ptr_msb ; cntr_v3b ; work ; +; |L2_Testbench_ROS_Lib4:ros_action_inst| ; 41384 (0) ; 20679 (0) ; 1328763 ; 4 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst ; L2_Testbench_ROS_Lib4 ; work ; +; |FWFT_FIFO:\fifo_in_ro_gen:0:fifo_in_ro_if:fifo_in_ro_inst| ; 16 (0) ; 9 (0) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|FWFT_FIFO:\fifo_in_ro_gen:0:fifo_in_ro_if:fifo_in_ro_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 16 (0) ; 9 (0) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|FWFT_FIFO:\fifo_in_ro_gen:0:fifo_in_ro_if:fifo_in_ro_inst|scfifo:scfifo_component ; scfifo ; work ; +; |scfifo_bfk1:auto_generated| ; 16 (0) ; 9 (0) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|FWFT_FIFO:\fifo_in_ro_gen:0:fifo_in_ro_if:fifo_in_ro_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated ; scfifo_bfk1 ; work ; +; |a_dpfifo_hbb1:dpfifo| ; 16 (12) ; 9 (7) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|FWFT_FIFO:\fifo_in_ro_gen:0:fifo_in_ro_if:fifo_in_ro_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated|a_dpfifo_hbb1:dpfifo ; a_dpfifo_hbb1 ; work ; +; |altsyncram_0uj1:FIFOram| ; 0 (0) ; 0 (0) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|FWFT_FIFO:\fifo_in_ro_gen:0:fifo_in_ro_if:fifo_in_ro_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated|a_dpfifo_hbb1:dpfifo|altsyncram_0uj1:FIFOram ; altsyncram_0uj1 ; work ; +; |cntr_c2b:wr_ptr| ; 2 (2) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|FWFT_FIFO:\fifo_in_ro_gen:0:fifo_in_ro_if:fifo_in_ro_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated|a_dpfifo_hbb1:dpfifo|cntr_c2b:wr_ptr ; cntr_c2b ; work ; +; |cntr_o27:usedw_counter| ; 2 (2) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|FWFT_FIFO:\fifo_in_ro_gen:0:fifo_in_ro_if:fifo_in_ro_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated|a_dpfifo_hbb1:dpfifo|cntr_o27:usedw_counter ; cntr_o27 ; work ; +; |FWFT_FIFO:\fifo_in_ro_gen:1:fifo_in_ro_if:fifo_in_ro_inst| ; 17 (0) ; 9 (0) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|FWFT_FIFO:\fifo_in_ro_gen:1:fifo_in_ro_if:fifo_in_ro_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 17 (0) ; 9 (0) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|FWFT_FIFO:\fifo_in_ro_gen:1:fifo_in_ro_if:fifo_in_ro_inst|scfifo:scfifo_component ; scfifo ; work ; +; |scfifo_bfk1:auto_generated| ; 17 (0) ; 9 (0) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|FWFT_FIFO:\fifo_in_ro_gen:1:fifo_in_ro_if:fifo_in_ro_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated ; scfifo_bfk1 ; work ; +; |a_dpfifo_hbb1:dpfifo| ; 17 (13) ; 9 (7) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|FWFT_FIFO:\fifo_in_ro_gen:1:fifo_in_ro_if:fifo_in_ro_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated|a_dpfifo_hbb1:dpfifo ; a_dpfifo_hbb1 ; work ; +; |altsyncram_0uj1:FIFOram| ; 0 (0) ; 0 (0) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|FWFT_FIFO:\fifo_in_ro_gen:1:fifo_in_ro_if:fifo_in_ro_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated|a_dpfifo_hbb1:dpfifo|altsyncram_0uj1:FIFOram ; altsyncram_0uj1 ; work ; +; |cntr_c2b:wr_ptr| ; 2 (2) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|FWFT_FIFO:\fifo_in_ro_gen:1:fifo_in_ro_if:fifo_in_ro_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated|a_dpfifo_hbb1:dpfifo|cntr_c2b:wr_ptr ; cntr_c2b ; work ; +; |cntr_o27:usedw_counter| ; 2 (2) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|FWFT_FIFO:\fifo_in_ro_gen:1:fifo_in_ro_if:fifo_in_ro_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated|a_dpfifo_hbb1:dpfifo|cntr_o27:usedw_counter ; cntr_o27 ; work ; +; |FWFT_FIFO:\fifo_in_ro_gen:2:fifo_in_ro_if:fifo_in_ro_inst| ; 15 (0) ; 9 (0) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|FWFT_FIFO:\fifo_in_ro_gen:2:fifo_in_ro_if:fifo_in_ro_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 15 (0) ; 9 (0) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|FWFT_FIFO:\fifo_in_ro_gen:2:fifo_in_ro_if:fifo_in_ro_inst|scfifo:scfifo_component ; scfifo ; work ; +; |scfifo_bfk1:auto_generated| ; 15 (0) ; 9 (0) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|FWFT_FIFO:\fifo_in_ro_gen:2:fifo_in_ro_if:fifo_in_ro_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated ; scfifo_bfk1 ; work ; +; |a_dpfifo_hbb1:dpfifo| ; 15 (11) ; 9 (7) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|FWFT_FIFO:\fifo_in_ro_gen:2:fifo_in_ro_if:fifo_in_ro_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated|a_dpfifo_hbb1:dpfifo ; a_dpfifo_hbb1 ; work ; +; |altsyncram_0uj1:FIFOram| ; 0 (0) ; 0 (0) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|FWFT_FIFO:\fifo_in_ro_gen:2:fifo_in_ro_if:fifo_in_ro_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated|a_dpfifo_hbb1:dpfifo|altsyncram_0uj1:FIFOram ; altsyncram_0uj1 ; work ; +; |cntr_c2b:wr_ptr| ; 2 (2) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|FWFT_FIFO:\fifo_in_ro_gen:2:fifo_in_ro_if:fifo_in_ro_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated|a_dpfifo_hbb1:dpfifo|cntr_c2b:wr_ptr ; cntr_c2b ; work ; +; |cntr_o27:usedw_counter| ; 2 (2) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|FWFT_FIFO:\fifo_in_ro_gen:2:fifo_in_ro_if:fifo_in_ro_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated|a_dpfifo_hbb1:dpfifo|cntr_o27:usedw_counter ; cntr_o27 ; work ; +; |FWFT_FIFO:fifo_in_rb_inst| ; 16 (0) ; 9 (0) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|FWFT_FIFO:fifo_in_rb_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 16 (0) ; 9 (0) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|FWFT_FIFO:fifo_in_rb_inst|scfifo:scfifo_component ; scfifo ; work ; +; |scfifo_bfk1:auto_generated| ; 16 (0) ; 9 (0) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|FWFT_FIFO:fifo_in_rb_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated ; scfifo_bfk1 ; work ; +; |a_dpfifo_hbb1:dpfifo| ; 16 (12) ; 9 (7) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|FWFT_FIFO:fifo_in_rb_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated|a_dpfifo_hbb1:dpfifo ; a_dpfifo_hbb1 ; work ; +; |altsyncram_0uj1:FIFOram| ; 0 (0) ; 0 (0) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|FWFT_FIFO:fifo_in_rb_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated|a_dpfifo_hbb1:dpfifo|altsyncram_0uj1:FIFOram ; altsyncram_0uj1 ; work ; +; |cntr_c2b:wr_ptr| ; 2 (2) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|FWFT_FIFO:fifo_in_rb_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated|a_dpfifo_hbb1:dpfifo|cntr_c2b:wr_ptr ; cntr_c2b ; work ; +; |cntr_o27:usedw_counter| ; 2 (2) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|FWFT_FIFO:fifo_in_rb_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated|a_dpfifo_hbb1:dpfifo|cntr_o27:usedw_counter ; cntr_o27 ; work ; +; |Fibonacci:Fibonacci_inst| ; 291 (291) ; 183 (183) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci:Fibonacci_inst ; Fibonacci ; work ; +; |Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst| ; 4263 (128) ; 3171 (13) ; 50439 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst ; Fibonacci_ros_action_server ; work ; +; |CancelGoal_ros_srv_server:cancel_srv_server_inst| ; 596 (581) ; 699 (501) ; 19200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|CancelGoal_ros_srv_server:cancel_srv_server_inst ; CancelGoal_ros_srv_server ; work ; +; |mem_ctrl:goals_canceling_goal_id_mem| ; 9 (6) ; 131 (2) ; 12800 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|CancelGoal_ros_srv_server:cancel_srv_server_inst|mem_ctrl:goals_canceling_goal_id_mem ; mem_ctrl ; work ; +; |FWFT_FIFO:burst_fifo_inst| ; 3 (0) ; 129 (0) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|CancelGoal_ros_srv_server:cancel_srv_server_inst|mem_ctrl:goals_canceling_goal_id_mem|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 3 (0) ; 129 (0) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|CancelGoal_ros_srv_server:cancel_srv_server_inst|mem_ctrl:goals_canceling_goal_id_mem|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ; +; |a_regfifo:subfifo| ; 3 (3) ; 129 (129) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|CancelGoal_ros_srv_server:cancel_srv_server_inst|mem_ctrl:goals_canceling_goal_id_mem|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|a_regfifo:subfifo ; a_regfifo ; work ; +; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 12800 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|CancelGoal_ros_srv_server:cancel_srv_server_inst|mem_ctrl:goals_canceling_goal_id_mem|single_port_ram:ram_inst ; single_port_ram ; work ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 12800 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|CancelGoal_ros_srv_server:cancel_srv_server_inst|mem_ctrl:goals_canceling_goal_id_mem|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ; +; |altsyncram_hpv3:auto_generated| ; 0 (0) ; 0 (0) ; 12800 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|CancelGoal_ros_srv_server:cancel_srv_server_inst|mem_ctrl:goals_canceling_goal_id_mem|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_hpv3:auto_generated ; altsyncram_hpv3 ; work ; +; |mem_ctrl:goals_canceling_stamp_mem| ; 6 (4) ; 67 (2) ; 6400 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|CancelGoal_ros_srv_server:cancel_srv_server_inst|mem_ctrl:goals_canceling_stamp_mem ; mem_ctrl ; work ; +; |FWFT_FIFO:burst_fifo_inst| ; 2 (0) ; 65 (0) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|CancelGoal_ros_srv_server:cancel_srv_server_inst|mem_ctrl:goals_canceling_stamp_mem|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 2 (0) ; 65 (0) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|CancelGoal_ros_srv_server:cancel_srv_server_inst|mem_ctrl:goals_canceling_stamp_mem|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ; +; |a_regfifo:subfifo| ; 2 (2) ; 65 (65) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|CancelGoal_ros_srv_server:cancel_srv_server_inst|mem_ctrl:goals_canceling_stamp_mem|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|a_regfifo:subfifo ; a_regfifo ; work ; +; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 6400 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|CancelGoal_ros_srv_server:cancel_srv_server_inst|mem_ctrl:goals_canceling_stamp_mem|single_port_ram:ram_inst ; single_port_ram ; work ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 6400 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|CancelGoal_ros_srv_server:cancel_srv_server_inst|mem_ctrl:goals_canceling_stamp_mem|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ; +; |altsyncram_vnv3:auto_generated| ; 0 (0) ; 0 (0) ; 6400 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|CancelGoal_ros_srv_server:cancel_srv_server_inst|mem_ctrl:goals_canceling_stamp_mem|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_vnv3:auto_generated ; altsyncram_vnv3 ; work ; +; |Fibonacci_ros_action_feedback_pub:\feedback_gen:feedback_pub_inst| ; 193 (154) ; 95 (60) ; 3200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|Fibonacci_ros_action_feedback_pub:\feedback_gen:feedback_pub_inst ; Fibonacci_ros_action_feedback_pub ; work ; +; |mem_ctrl:seq_mem| ; 39 (4) ; 35 (2) ; 3200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|Fibonacci_ros_action_feedback_pub:\feedback_gen:feedback_pub_inst|mem_ctrl:seq_mem ; mem_ctrl ; work ; +; |FWFT_FIFO:burst_fifo_inst| ; 35 (0) ; 33 (0) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|Fibonacci_ros_action_feedback_pub:\feedback_gen:feedback_pub_inst|mem_ctrl:seq_mem|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 35 (0) ; 33 (0) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|Fibonacci_ros_action_feedback_pub:\feedback_gen:feedback_pub_inst|mem_ctrl:seq_mem|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ; +; |a_regfifo:subfifo| ; 35 (35) ; 33 (33) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|Fibonacci_ros_action_feedback_pub:\feedback_gen:feedback_pub_inst|mem_ctrl:seq_mem|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|a_regfifo:subfifo ; a_regfifo ; work ; +; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 3200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|Fibonacci_ros_action_feedback_pub:\feedback_gen:feedback_pub_inst|mem_ctrl:seq_mem|single_port_ram:ram_inst ; single_port_ram ; work ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 3200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|Fibonacci_ros_action_feedback_pub:\feedback_gen:feedback_pub_inst|mem_ctrl:seq_mem|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ; +; |altsyncram_qnv3:auto_generated| ; 0 (0) ; 0 (0) ; 3200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|Fibonacci_ros_action_feedback_pub:\feedback_gen:feedback_pub_inst|mem_ctrl:seq_mem|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_qnv3:auto_generated ; altsyncram_qnv3 ; work ; +; |Fibonacci_ros_action_goal_srv_server:goal_srv_server_inst| ; 366 (366) ; 460 (460) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|Fibonacci_ros_action_goal_srv_server:goal_srv_server_inst ; Fibonacci_ros_action_goal_srv_server ; work ; +; |Fibonacci_ros_action_result_srv_server:result_srv_server_inst| ; 459 (420) ; 470 (435) ; 3200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|Fibonacci_ros_action_result_srv_server:result_srv_server_inst ; Fibonacci_ros_action_result_srv_server ; work ; +; |mem_ctrl:seq_mem| ; 39 (5) ; 35 (2) ; 3200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|Fibonacci_ros_action_result_srv_server:result_srv_server_inst|mem_ctrl:seq_mem ; mem_ctrl ; work ; +; |FWFT_FIFO:burst_fifo_inst| ; 34 (0) ; 33 (0) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|Fibonacci_ros_action_result_srv_server:result_srv_server_inst|mem_ctrl:seq_mem|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 34 (0) ; 33 (0) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|Fibonacci_ros_action_result_srv_server:result_srv_server_inst|mem_ctrl:seq_mem|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ; +; |a_regfifo:subfifo| ; 34 (34) ; 33 (33) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|Fibonacci_ros_action_result_srv_server:result_srv_server_inst|mem_ctrl:seq_mem|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|a_regfifo:subfifo ; a_regfifo ; work ; +; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 3200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|Fibonacci_ros_action_result_srv_server:result_srv_server_inst|mem_ctrl:seq_mem|single_port_ram:ram_inst ; single_port_ram ; work ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 3200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|Fibonacci_ros_action_result_srv_server:result_srv_server_inst|mem_ctrl:seq_mem|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ; +; |altsyncram_qnv3:auto_generated| ; 0 (0) ; 0 (0) ; 3200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|Fibonacci_ros_action_result_srv_server:result_srv_server_inst|mem_ctrl:seq_mem|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_qnv3:auto_generated ; altsyncram_qnv3 ; work ; +; |GoalStatusArray_ros_pub:status_pub_inst| ; 253 (225) ; 271 (62) ; 20000 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|GoalStatusArray_ros_pub:status_pub_inst ; GoalStatusArray_ros_pub ; work ; +; |mem_ctrl:status_list_goal_info_goal_id_mem| ; 7 (4) ; 131 (2) ; 12800 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|GoalStatusArray_ros_pub:status_pub_inst|mem_ctrl:status_list_goal_info_goal_id_mem ; mem_ctrl ; work ; +; |FWFT_FIFO:burst_fifo_inst| ; 3 (0) ; 129 (0) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|GoalStatusArray_ros_pub:status_pub_inst|mem_ctrl:status_list_goal_info_goal_id_mem|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 3 (0) ; 129 (0) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|GoalStatusArray_ros_pub:status_pub_inst|mem_ctrl:status_list_goal_info_goal_id_mem|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ; +; |a_regfifo:subfifo| ; 3 (3) ; 129 (129) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|GoalStatusArray_ros_pub:status_pub_inst|mem_ctrl:status_list_goal_info_goal_id_mem|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|a_regfifo:subfifo ; a_regfifo ; work ; +; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 12800 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|GoalStatusArray_ros_pub:status_pub_inst|mem_ctrl:status_list_goal_info_goal_id_mem|single_port_ram:ram_inst ; single_port_ram ; work ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 12800 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|GoalStatusArray_ros_pub:status_pub_inst|mem_ctrl:status_list_goal_info_goal_id_mem|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ; +; |altsyncram_hpv3:auto_generated| ; 0 (0) ; 0 (0) ; 12800 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|GoalStatusArray_ros_pub:status_pub_inst|mem_ctrl:status_list_goal_info_goal_id_mem|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_hpv3:auto_generated ; altsyncram_hpv3 ; work ; +; |mem_ctrl:status_list_goal_info_stamp_mem| ; 6 (4) ; 67 (2) ; 6400 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|GoalStatusArray_ros_pub:status_pub_inst|mem_ctrl:status_list_goal_info_stamp_mem ; mem_ctrl ; work ; +; |FWFT_FIFO:burst_fifo_inst| ; 2 (0) ; 65 (0) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|GoalStatusArray_ros_pub:status_pub_inst|mem_ctrl:status_list_goal_info_stamp_mem|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 2 (0) ; 65 (0) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|GoalStatusArray_ros_pub:status_pub_inst|mem_ctrl:status_list_goal_info_stamp_mem|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ; +; |a_regfifo:subfifo| ; 2 (2) ; 65 (65) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|GoalStatusArray_ros_pub:status_pub_inst|mem_ctrl:status_list_goal_info_stamp_mem|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|a_regfifo:subfifo ; a_regfifo ; work ; +; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 6400 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|GoalStatusArray_ros_pub:status_pub_inst|mem_ctrl:status_list_goal_info_stamp_mem|single_port_ram:ram_inst ; single_port_ram ; work ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 6400 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|GoalStatusArray_ros_pub:status_pub_inst|mem_ctrl:status_list_goal_info_stamp_mem|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ; +; |altsyncram_vnv3:auto_generated| ; 0 (0) ; 0 (0) ; 6400 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|GoalStatusArray_ros_pub:status_pub_inst|mem_ctrl:status_list_goal_info_stamp_mem|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_vnv3:auto_generated ; altsyncram_vnv3 ; work ; +; |mem_ctrl:status_list_status_mem| ; 15 (4) ; 11 (2) ; 800 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|GoalStatusArray_ros_pub:status_pub_inst|mem_ctrl:status_list_status_mem ; mem_ctrl ; work ; +; |FWFT_FIFO:burst_fifo_inst| ; 11 (0) ; 9 (0) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|GoalStatusArray_ros_pub:status_pub_inst|mem_ctrl:status_list_status_mem|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 11 (0) ; 9 (0) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|GoalStatusArray_ros_pub:status_pub_inst|mem_ctrl:status_list_status_mem|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ; +; |a_regfifo:subfifo| ; 11 (11) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|GoalStatusArray_ros_pub:status_pub_inst|mem_ctrl:status_list_status_mem|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|a_regfifo:subfifo ; a_regfifo ; work ; +; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 800 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|GoalStatusArray_ros_pub:status_pub_inst|mem_ctrl:status_list_status_mem|single_port_ram:ram_inst ; single_port_ram ; work ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 800 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|GoalStatusArray_ros_pub:status_pub_inst|mem_ctrl:status_list_status_mem|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ; +; |altsyncram_emv3:auto_generated| ; 0 (0) ; 0 (0) ; 800 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|GoalStatusArray_ros_pub:status_pub_inst|mem_ctrl:status_list_status_mem|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_emv3:auto_generated ; altsyncram_emv3 ; work ; +; |mem_ctrl:\r_seq_gen:0:r_seq_mem| ; 38 (4) ; 35 (2) ; 3200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|mem_ctrl:\r_seq_gen:0:r_seq_mem ; mem_ctrl ; work ; +; |FWFT_FIFO:burst_fifo_inst| ; 34 (0) ; 33 (0) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|mem_ctrl:\r_seq_gen:0:r_seq_mem|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 34 (0) ; 33 (0) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|mem_ctrl:\r_seq_gen:0:r_seq_mem|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ; +; |a_regfifo:subfifo| ; 34 (34) ; 33 (33) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|mem_ctrl:\r_seq_gen:0:r_seq_mem|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|a_regfifo:subfifo ; a_regfifo ; work ; +; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 3200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|mem_ctrl:\r_seq_gen:0:r_seq_mem|single_port_ram:ram_inst ; single_port_ram ; work ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 3200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|mem_ctrl:\r_seq_gen:0:r_seq_mem|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ; +; |altsyncram_qnv3:auto_generated| ; 0 (0) ; 0 (0) ; 3200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|mem_ctrl:\r_seq_gen:0:r_seq_mem|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_qnv3:auto_generated ; altsyncram_qnv3 ; work ; +; |mem_ctrl:r_seq_len_mem| ; 14 (5) ; 10 (2) ; 7 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|mem_ctrl:r_seq_len_mem ; mem_ctrl ; work ; +; |FWFT_FIFO:burst_fifo_inst| ; 9 (0) ; 8 (0) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|mem_ctrl:r_seq_len_mem|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 9 (0) ; 8 (0) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|mem_ctrl:r_seq_len_mem|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ; +; |a_regfifo:subfifo| ; 9 (9) ; 8 (8) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|mem_ctrl:r_seq_len_mem|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|a_regfifo:subfifo ; a_regfifo ; work ; +; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 7 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|mem_ctrl:r_seq_len_mem|single_port_ram:ram_inst ; single_port_ram ; work ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 7 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|mem_ctrl:r_seq_len_mem|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ; +; |altsyncram_6jv3:auto_generated| ; 0 (0) ; 0 (0) ; 7 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|mem_ctrl:r_seq_len_mem|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_6jv3:auto_generated ; altsyncram_6jv3 ; work ; +; |ros_action_server:action_server_inst| ; 2216 (2133) ; 1118 (1072) ; 1632 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|ros_action_server:action_server_inst ; ros_action_server ; work ; +; |mem_ctrl:goal_mem_ctrl_inst| ; 42 (6) ; 23 (2) ; 832 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|ros_action_server:action_server_inst|mem_ctrl:goal_mem_ctrl_inst ; mem_ctrl ; work ; +; |FWFT_FIFO:burst_fifo_inst| ; 36 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|ros_action_server:action_server_inst|mem_ctrl:goal_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 36 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|ros_action_server:action_server_inst|mem_ctrl:goal_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ; +; |scfifo_sgk1:auto_generated| ; 36 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|ros_action_server:action_server_inst|mem_ctrl:goal_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_sgk1:auto_generated ; scfifo_sgk1 ; work ; +; |a_dpfifo_2db1:dpfifo| ; 36 (22) ; 21 (10) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|ros_action_server:action_server_inst|mem_ctrl:goal_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_sgk1:auto_generated|a_dpfifo_2db1:dpfifo ; a_dpfifo_2db1 ; work ; +; |altsyncram_e1k1:FIFOram| ; 0 (0) ; 0 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|ros_action_server:action_server_inst|mem_ctrl:goal_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_sgk1:auto_generated|a_dpfifo_2db1:dpfifo|altsyncram_e1k1:FIFOram ; altsyncram_e1k1 ; work ; +; |cntr_e2b:rd_ptr_msb| ; 4 (4) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|ros_action_server:action_server_inst|mem_ctrl:goal_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_sgk1:auto_generated|a_dpfifo_2db1:dpfifo|cntr_e2b:rd_ptr_msb ; cntr_e2b ; work ; +; |cntr_f2b:wr_ptr| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|ros_action_server:action_server_inst|mem_ctrl:goal_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_sgk1:auto_generated|a_dpfifo_2db1:dpfifo|cntr_f2b:wr_ptr ; cntr_f2b ; work ; +; |cntr_r27:usedw_counter| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|ros_action_server:action_server_inst|mem_ctrl:goal_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_sgk1:auto_generated|a_dpfifo_2db1:dpfifo|cntr_r27:usedw_counter ; cntr_r27 ; work ; +; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 320 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|ros_action_server:action_server_inst|mem_ctrl:goal_mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 320 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|ros_action_server:action_server_inst|mem_ctrl:goal_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ; +; |altsyncram_7mv3:auto_generated| ; 0 (0) ; 0 (0) ; 320 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|ros_action_server:action_server_inst|mem_ctrl:goal_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_7mv3:auto_generated ; altsyncram_7mv3 ; work ; +; |mem_ctrl:rrq_mem_ctrl_inst| ; 41 (6) ; 23 (2) ; 800 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|ros_action_server:action_server_inst|mem_ctrl:rrq_mem_ctrl_inst ; mem_ctrl ; work ; +; |FWFT_FIFO:burst_fifo_inst| ; 35 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|ros_action_server:action_server_inst|mem_ctrl:rrq_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 35 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|ros_action_server:action_server_inst|mem_ctrl:rrq_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ; +; |scfifo_kfk1:auto_generated| ; 35 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|ros_action_server:action_server_inst|mem_ctrl:rrq_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated ; scfifo_kfk1 ; work ; +; |a_dpfifo_qbb1:dpfifo| ; 35 (21) ; 21 (10) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|ros_action_server:action_server_inst|mem_ctrl:rrq_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo ; a_dpfifo_qbb1 ; work ; +; |altsyncram_e1k1:FIFOram| ; 0 (0) ; 0 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|ros_action_server:action_server_inst|mem_ctrl:rrq_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo|altsyncram_e1k1:FIFOram ; altsyncram_e1k1 ; work ; +; |cntr_e2b:rd_ptr_msb| ; 4 (4) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|ros_action_server:action_server_inst|mem_ctrl:rrq_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo|cntr_e2b:rd_ptr_msb ; cntr_e2b ; work ; +; |cntr_f2b:wr_ptr| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|ros_action_server:action_server_inst|mem_ctrl:rrq_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo|cntr_f2b:wr_ptr ; cntr_f2b ; work ; +; |cntr_r27:usedw_counter| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|ros_action_server:action_server_inst|mem_ctrl:rrq_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo|cntr_r27:usedw_counter ; cntr_r27 ; work ; +; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 288 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|ros_action_server:action_server_inst|mem_ctrl:rrq_mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 288 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|ros_action_server:action_server_inst|mem_ctrl:rrq_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ; +; |altsyncram_vkv3:auto_generated| ; 0 (0) ; 0 (0) ; 288 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|ros_action_server:action_server_inst|mem_ctrl:rrq_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_vkv3:auto_generated ; altsyncram_vkv3 ; work ; +; |dds_reader:\dds_endpoint_r_if:dds_reader_inst| ; 6437 (5369) ; 2872 (1512) ; 29184 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst ; dds_reader ; work ; +; |key_holder:\key_holder_gen:0:key_holder_inst| ; 228 (186) ; 385 (250) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|key_holder:\key_holder_gen:0:key_holder_inst ; key_holder ; work ; +; |key_hash_generator:key_hash_generator_inst| ; 42 (42) ; 135 (135) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|key_holder:\key_holder_gen:0:key_holder_inst|key_hash_generator:key_hash_generator_inst ; key_hash_generator ; work ; +; |key_holder:\key_holder_gen:1:key_holder_inst| ; 229 (187) ; 384 (249) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|key_holder:\key_holder_gen:1:key_holder_inst ; key_holder ; work ; +; |key_hash_generator:key_hash_generator_inst| ; 42 (42) ; 135 (135) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|key_holder:\key_holder_gen:1:key_holder_inst|key_hash_generator:key_hash_generator_inst ; key_hash_generator ; work ; +; |key_holder:\key_holder_gen:2:key_holder_inst| ; 225 (183) ; 384 (249) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|key_holder:\key_holder_gen:2:key_holder_inst ; key_holder ; work ; +; |key_hash_generator:key_hash_generator_inst| ; 42 (42) ; 135 (135) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|key_holder:\key_holder_gen:2:key_holder_inst|key_hash_generator:key_hash_generator_inst ; key_hash_generator ; work ; +; |mem_ctrl:\instance_mem_ctrl_gen:0:instance_mem_ctrl_inst| ; 46 (8) ; 23 (2) ; 960 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\instance_mem_ctrl_gen:0:instance_mem_ctrl_inst ; mem_ctrl ; work ; +; |FWFT_FIFO:burst_fifo_inst| ; 38 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\instance_mem_ctrl_gen:0:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 38 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\instance_mem_ctrl_gen:0:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ; +; |scfifo_0hk1:auto_generated| ; 38 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\instance_mem_ctrl_gen:0:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_0hk1:auto_generated ; scfifo_0hk1 ; work ; +; |a_dpfifo_6db1:dpfifo| ; 38 (24) ; 21 (10) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\instance_mem_ctrl_gen:0:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_0hk1:auto_generated|a_dpfifo_6db1:dpfifo ; a_dpfifo_6db1 ; work ; +; |altsyncram_e1k1:FIFOram| ; 0 (0) ; 0 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\instance_mem_ctrl_gen:0:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_0hk1:auto_generated|a_dpfifo_6db1:dpfifo|altsyncram_e1k1:FIFOram ; altsyncram_e1k1 ; work ; +; |cntr_e2b:rd_ptr_msb| ; 4 (4) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\instance_mem_ctrl_gen:0:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_0hk1:auto_generated|a_dpfifo_6db1:dpfifo|cntr_e2b:rd_ptr_msb ; cntr_e2b ; work ; +; |cntr_f2b:wr_ptr| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\instance_mem_ctrl_gen:0:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_0hk1:auto_generated|a_dpfifo_6db1:dpfifo|cntr_f2b:wr_ptr ; cntr_f2b ; work ; +; |cntr_r27:usedw_counter| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\instance_mem_ctrl_gen:0:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_0hk1:auto_generated|a_dpfifo_6db1:dpfifo|cntr_r27:usedw_counter ; cntr_r27 ; work ; +; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 448 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\instance_mem_ctrl_gen:0:instance_mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 448 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\instance_mem_ctrl_gen:0:instance_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ; +; |altsyncram_bmv3:auto_generated| ; 0 (0) ; 0 (0) ; 448 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\instance_mem_ctrl_gen:0:instance_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_bmv3:auto_generated ; altsyncram_bmv3 ; work ; +; |mem_ctrl:\instance_mem_ctrl_gen:1:instance_mem_ctrl_inst| ; 46 (8) ; 23 (2) ; 960 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\instance_mem_ctrl_gen:1:instance_mem_ctrl_inst ; mem_ctrl ; work ; +; |FWFT_FIFO:burst_fifo_inst| ; 38 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\instance_mem_ctrl_gen:1:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 38 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\instance_mem_ctrl_gen:1:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ; +; |scfifo_0hk1:auto_generated| ; 38 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\instance_mem_ctrl_gen:1:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_0hk1:auto_generated ; scfifo_0hk1 ; work ; +; |a_dpfifo_6db1:dpfifo| ; 38 (24) ; 21 (10) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\instance_mem_ctrl_gen:1:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_0hk1:auto_generated|a_dpfifo_6db1:dpfifo ; a_dpfifo_6db1 ; work ; +; |altsyncram_e1k1:FIFOram| ; 0 (0) ; 0 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\instance_mem_ctrl_gen:1:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_0hk1:auto_generated|a_dpfifo_6db1:dpfifo|altsyncram_e1k1:FIFOram ; altsyncram_e1k1 ; work ; +; |cntr_e2b:rd_ptr_msb| ; 4 (4) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\instance_mem_ctrl_gen:1:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_0hk1:auto_generated|a_dpfifo_6db1:dpfifo|cntr_e2b:rd_ptr_msb ; cntr_e2b ; work ; +; |cntr_f2b:wr_ptr| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\instance_mem_ctrl_gen:1:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_0hk1:auto_generated|a_dpfifo_6db1:dpfifo|cntr_f2b:wr_ptr ; cntr_f2b ; work ; +; |cntr_r27:usedw_counter| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\instance_mem_ctrl_gen:1:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_0hk1:auto_generated|a_dpfifo_6db1:dpfifo|cntr_r27:usedw_counter ; cntr_r27 ; work ; +; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 448 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\instance_mem_ctrl_gen:1:instance_mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 448 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\instance_mem_ctrl_gen:1:instance_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ; +; |altsyncram_bmv3:auto_generated| ; 0 (0) ; 0 (0) ; 448 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\instance_mem_ctrl_gen:1:instance_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_bmv3:auto_generated ; altsyncram_bmv3 ; work ; +; |mem_ctrl:\instance_mem_ctrl_gen:2:instance_mem_ctrl_inst| ; 46 (8) ; 23 (2) ; 960 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\instance_mem_ctrl_gen:2:instance_mem_ctrl_inst ; mem_ctrl ; work ; +; |FWFT_FIFO:burst_fifo_inst| ; 38 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\instance_mem_ctrl_gen:2:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 38 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\instance_mem_ctrl_gen:2:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ; +; |scfifo_0hk1:auto_generated| ; 38 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\instance_mem_ctrl_gen:2:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_0hk1:auto_generated ; scfifo_0hk1 ; work ; +; |a_dpfifo_6db1:dpfifo| ; 38 (24) ; 21 (10) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\instance_mem_ctrl_gen:2:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_0hk1:auto_generated|a_dpfifo_6db1:dpfifo ; a_dpfifo_6db1 ; work ; +; |altsyncram_e1k1:FIFOram| ; 0 (0) ; 0 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\instance_mem_ctrl_gen:2:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_0hk1:auto_generated|a_dpfifo_6db1:dpfifo|altsyncram_e1k1:FIFOram ; altsyncram_e1k1 ; work ; +; |cntr_e2b:rd_ptr_msb| ; 4 (4) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\instance_mem_ctrl_gen:2:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_0hk1:auto_generated|a_dpfifo_6db1:dpfifo|cntr_e2b:rd_ptr_msb ; cntr_e2b ; work ; +; |cntr_f2b:wr_ptr| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\instance_mem_ctrl_gen:2:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_0hk1:auto_generated|a_dpfifo_6db1:dpfifo|cntr_f2b:wr_ptr ; cntr_f2b ; work ; +; |cntr_r27:usedw_counter| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\instance_mem_ctrl_gen:2:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_0hk1:auto_generated|a_dpfifo_6db1:dpfifo|cntr_r27:usedw_counter ; cntr_r27 ; work ; +; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 448 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\instance_mem_ctrl_gen:2:instance_mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 448 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\instance_mem_ctrl_gen:2:instance_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ; +; |altsyncram_bmv3:auto_generated| ; 0 (0) ; 0 (0) ; 448 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\instance_mem_ctrl_gen:2:instance_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_bmv3:auto_generated ; altsyncram_bmv3 ; work ; +; |mem_ctrl:\payload_mem_ctrl_gen:0:payload_mem_ctrl_inst| ; 38 (5) ; 23 (2) ; 4384 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\payload_mem_ctrl_gen:0:payload_mem_ctrl_inst ; mem_ctrl ; work ; +; |FWFT_FIFO:burst_fifo_inst| ; 33 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\payload_mem_ctrl_gen:0:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 33 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\payload_mem_ctrl_gen:0:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ; +; |scfifo_tgk1:auto_generated| ; 33 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\payload_mem_ctrl_gen:0:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated ; scfifo_tgk1 ; work ; +; |a_dpfifo_3db1:dpfifo| ; 33 (19) ; 21 (10) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\payload_mem_ctrl_gen:0:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated|a_dpfifo_3db1:dpfifo ; a_dpfifo_3db1 ; work ; +; |altsyncram_e1k1:FIFOram| ; 0 (0) ; 0 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\payload_mem_ctrl_gen:0:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated|a_dpfifo_3db1:dpfifo|altsyncram_e1k1:FIFOram ; altsyncram_e1k1 ; work ; +; |cntr_e2b:rd_ptr_msb| ; 4 (4) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\payload_mem_ctrl_gen:0:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated|a_dpfifo_3db1:dpfifo|cntr_e2b:rd_ptr_msb ; cntr_e2b ; work ; +; |cntr_f2b:wr_ptr| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\payload_mem_ctrl_gen:0:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated|a_dpfifo_3db1:dpfifo|cntr_f2b:wr_ptr ; cntr_f2b ; work ; +; |cntr_r27:usedw_counter| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\payload_mem_ctrl_gen:0:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated|a_dpfifo_3db1:dpfifo|cntr_r27:usedw_counter ; cntr_r27 ; work ; +; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 3872 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\payload_mem_ctrl_gen:0:payload_mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 3872 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\payload_mem_ctrl_gen:0:payload_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ; +; |altsyncram_0ov3:auto_generated| ; 0 (0) ; 0 (0) ; 3872 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\payload_mem_ctrl_gen:0:payload_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_0ov3:auto_generated ; altsyncram_0ov3 ; work ; +; |mem_ctrl:\payload_mem_ctrl_gen:1:payload_mem_ctrl_inst| ; 38 (5) ; 23 (2) ; 4032 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\payload_mem_ctrl_gen:1:payload_mem_ctrl_inst ; mem_ctrl ; work ; +; |FWFT_FIFO:burst_fifo_inst| ; 33 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\payload_mem_ctrl_gen:1:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 33 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\payload_mem_ctrl_gen:1:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ; +; |scfifo_sgk1:auto_generated| ; 33 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\payload_mem_ctrl_gen:1:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_sgk1:auto_generated ; scfifo_sgk1 ; work ; +; |a_dpfifo_2db1:dpfifo| ; 33 (19) ; 21 (10) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\payload_mem_ctrl_gen:1:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_sgk1:auto_generated|a_dpfifo_2db1:dpfifo ; a_dpfifo_2db1 ; work ; +; |altsyncram_e1k1:FIFOram| ; 0 (0) ; 0 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\payload_mem_ctrl_gen:1:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_sgk1:auto_generated|a_dpfifo_2db1:dpfifo|altsyncram_e1k1:FIFOram ; altsyncram_e1k1 ; work ; +; |cntr_e2b:rd_ptr_msb| ; 4 (4) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\payload_mem_ctrl_gen:1:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_sgk1:auto_generated|a_dpfifo_2db1:dpfifo|cntr_e2b:rd_ptr_msb ; cntr_e2b ; work ; +; |cntr_f2b:wr_ptr| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\payload_mem_ctrl_gen:1:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_sgk1:auto_generated|a_dpfifo_2db1:dpfifo|cntr_f2b:wr_ptr ; cntr_f2b ; work ; +; |cntr_r27:usedw_counter| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\payload_mem_ctrl_gen:1:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_sgk1:auto_generated|a_dpfifo_2db1:dpfifo|cntr_r27:usedw_counter ; cntr_r27 ; work ; +; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 3520 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\payload_mem_ctrl_gen:1:payload_mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 3520 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\payload_mem_ctrl_gen:1:payload_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ; +; |altsyncram_snv3:auto_generated| ; 0 (0) ; 0 (0) ; 3520 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\payload_mem_ctrl_gen:1:payload_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_snv3:auto_generated ; altsyncram_snv3 ; work ; +; |mem_ctrl:\payload_mem_ctrl_gen:2:payload_mem_ctrl_inst| ; 37 (5) ; 23 (2) ; 4736 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\payload_mem_ctrl_gen:2:payload_mem_ctrl_inst ; mem_ctrl ; work ; +; |FWFT_FIFO:burst_fifo_inst| ; 32 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\payload_mem_ctrl_gen:2:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 32 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\payload_mem_ctrl_gen:2:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ; +; |scfifo_vgk1:auto_generated| ; 32 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\payload_mem_ctrl_gen:2:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_vgk1:auto_generated ; scfifo_vgk1 ; work ; +; |a_dpfifo_5db1:dpfifo| ; 32 (18) ; 21 (10) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\payload_mem_ctrl_gen:2:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_vgk1:auto_generated|a_dpfifo_5db1:dpfifo ; a_dpfifo_5db1 ; work ; +; |altsyncram_e1k1:FIFOram| ; 0 (0) ; 0 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\payload_mem_ctrl_gen:2:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_vgk1:auto_generated|a_dpfifo_5db1:dpfifo|altsyncram_e1k1:FIFOram ; altsyncram_e1k1 ; work ; +; |cntr_e2b:rd_ptr_msb| ; 4 (4) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\payload_mem_ctrl_gen:2:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_vgk1:auto_generated|a_dpfifo_5db1:dpfifo|cntr_e2b:rd_ptr_msb ; cntr_e2b ; work ; +; |cntr_f2b:wr_ptr| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\payload_mem_ctrl_gen:2:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_vgk1:auto_generated|a_dpfifo_5db1:dpfifo|cntr_f2b:wr_ptr ; cntr_f2b ; work ; +; |cntr_r27:usedw_counter| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\payload_mem_ctrl_gen:2:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_vgk1:auto_generated|a_dpfifo_5db1:dpfifo|cntr_r27:usedw_counter ; cntr_r27 ; work ; +; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 4224 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\payload_mem_ctrl_gen:2:payload_mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 4224 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\payload_mem_ctrl_gen:2:payload_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ; +; |altsyncram_1ov3:auto_generated| ; 0 (0) ; 0 (0) ; 4224 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\payload_mem_ctrl_gen:2:payload_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_1ov3:auto_generated ; altsyncram_1ov3 ; work ; +; |mem_ctrl:\sample_mem_ctrl_gen:0:sample_mem_ctrl_inst| ; 45 (6) ; 23 (2) ; 4384 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\sample_mem_ctrl_gen:0:sample_mem_ctrl_inst ; mem_ctrl ; work ; +; |FWFT_FIFO:burst_fifo_inst| ; 39 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\sample_mem_ctrl_gen:0:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 39 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\sample_mem_ctrl_gen:0:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ; +; |scfifo_tgk1:auto_generated| ; 39 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\sample_mem_ctrl_gen:0:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated ; scfifo_tgk1 ; work ; +; |a_dpfifo_3db1:dpfifo| ; 39 (22) ; 21 (10) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\sample_mem_ctrl_gen:0:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated|a_dpfifo_3db1:dpfifo ; a_dpfifo_3db1 ; work ; +; |altsyncram_e1k1:FIFOram| ; 0 (0) ; 0 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\sample_mem_ctrl_gen:0:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated|a_dpfifo_3db1:dpfifo|altsyncram_e1k1:FIFOram ; altsyncram_e1k1 ; work ; +; |cntr_e2b:rd_ptr_msb| ; 5 (5) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\sample_mem_ctrl_gen:0:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated|a_dpfifo_3db1:dpfifo|cntr_e2b:rd_ptr_msb ; cntr_e2b ; work ; +; |cntr_f2b:wr_ptr| ; 6 (6) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\sample_mem_ctrl_gen:0:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated|a_dpfifo_3db1:dpfifo|cntr_f2b:wr_ptr ; cntr_f2b ; work ; +; |cntr_r27:usedw_counter| ; 6 (6) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\sample_mem_ctrl_gen:0:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated|a_dpfifo_3db1:dpfifo|cntr_r27:usedw_counter ; cntr_r27 ; work ; +; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 3872 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\sample_mem_ctrl_gen:0:sample_mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 3872 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\sample_mem_ctrl_gen:0:sample_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ; +; |altsyncram_tnv3:auto_generated| ; 0 (0) ; 0 (0) ; 3872 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\sample_mem_ctrl_gen:0:sample_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_tnv3:auto_generated ; altsyncram_tnv3 ; work ; +; |mem_ctrl:\sample_mem_ctrl_gen:1:sample_mem_ctrl_inst| ; 45 (6) ; 23 (2) ; 4384 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\sample_mem_ctrl_gen:1:sample_mem_ctrl_inst ; mem_ctrl ; work ; +; |FWFT_FIFO:burst_fifo_inst| ; 39 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\sample_mem_ctrl_gen:1:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 39 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\sample_mem_ctrl_gen:1:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ; +; |scfifo_tgk1:auto_generated| ; 39 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\sample_mem_ctrl_gen:1:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated ; scfifo_tgk1 ; work ; +; |a_dpfifo_3db1:dpfifo| ; 39 (22) ; 21 (10) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\sample_mem_ctrl_gen:1:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated|a_dpfifo_3db1:dpfifo ; a_dpfifo_3db1 ; work ; +; |altsyncram_e1k1:FIFOram| ; 0 (0) ; 0 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\sample_mem_ctrl_gen:1:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated|a_dpfifo_3db1:dpfifo|altsyncram_e1k1:FIFOram ; altsyncram_e1k1 ; work ; +; |cntr_e2b:rd_ptr_msb| ; 5 (5) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\sample_mem_ctrl_gen:1:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated|a_dpfifo_3db1:dpfifo|cntr_e2b:rd_ptr_msb ; cntr_e2b ; work ; +; |cntr_f2b:wr_ptr| ; 6 (6) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\sample_mem_ctrl_gen:1:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated|a_dpfifo_3db1:dpfifo|cntr_f2b:wr_ptr ; cntr_f2b ; work ; +; |cntr_r27:usedw_counter| ; 6 (6) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\sample_mem_ctrl_gen:1:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated|a_dpfifo_3db1:dpfifo|cntr_r27:usedw_counter ; cntr_r27 ; work ; +; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 3872 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\sample_mem_ctrl_gen:1:sample_mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 3872 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\sample_mem_ctrl_gen:1:sample_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ; +; |altsyncram_tnv3:auto_generated| ; 0 (0) ; 0 (0) ; 3872 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\sample_mem_ctrl_gen:1:sample_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_tnv3:auto_generated ; altsyncram_tnv3 ; work ; +; |mem_ctrl:\sample_mem_ctrl_gen:2:sample_mem_ctrl_inst| ; 45 (6) ; 23 (2) ; 4384 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\sample_mem_ctrl_gen:2:sample_mem_ctrl_inst ; mem_ctrl ; work ; +; |FWFT_FIFO:burst_fifo_inst| ; 39 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\sample_mem_ctrl_gen:2:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 39 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\sample_mem_ctrl_gen:2:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ; +; |scfifo_tgk1:auto_generated| ; 39 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\sample_mem_ctrl_gen:2:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated ; scfifo_tgk1 ; work ; +; |a_dpfifo_3db1:dpfifo| ; 39 (22) ; 21 (10) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\sample_mem_ctrl_gen:2:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated|a_dpfifo_3db1:dpfifo ; a_dpfifo_3db1 ; work ; +; |altsyncram_e1k1:FIFOram| ; 0 (0) ; 0 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\sample_mem_ctrl_gen:2:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated|a_dpfifo_3db1:dpfifo|altsyncram_e1k1:FIFOram ; altsyncram_e1k1 ; work ; +; |cntr_e2b:rd_ptr_msb| ; 5 (5) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\sample_mem_ctrl_gen:2:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated|a_dpfifo_3db1:dpfifo|cntr_e2b:rd_ptr_msb ; cntr_e2b ; work ; +; |cntr_f2b:wr_ptr| ; 6 (6) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\sample_mem_ctrl_gen:2:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated|a_dpfifo_3db1:dpfifo|cntr_f2b:wr_ptr ; cntr_f2b ; work ; +; |cntr_r27:usedw_counter| ; 6 (6) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\sample_mem_ctrl_gen:2:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated|a_dpfifo_3db1:dpfifo|cntr_r27:usedw_counter ; cntr_r27 ; work ; +; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 3872 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\sample_mem_ctrl_gen:2:sample_mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 3872 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\sample_mem_ctrl_gen:2:sample_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ; +; |altsyncram_tnv3:auto_generated| ; 0 (0) ; 0 (0) ; 3872 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_r_if:dds_reader_inst|mem_ctrl:\sample_mem_ctrl_gen:2:sample_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_tnv3:auto_generated ; altsyncram_tnv3 ; work ; +; |dds_writer:\dds_endpoint_w_if:dds_writer_inst| ; 6775 (4904) ; 4152 (1815) ; 428928 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst ; dds_writer ; work ; +; |key_holder:\key_holder_gen:0:key_holder_inst| ; 222 (182) ; 384 (249) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|key_holder:\key_holder_gen:0:key_holder_inst ; key_holder ; work ; +; |key_hash_generator:key_hash_generator_inst| ; 40 (40) ; 135 (135) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|key_holder:\key_holder_gen:0:key_holder_inst|key_hash_generator:key_hash_generator_inst ; key_hash_generator ; work ; +; |key_holder:\key_holder_gen:1:key_holder_inst| ; 224 (183) ; 384 (249) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|key_holder:\key_holder_gen:1:key_holder_inst ; key_holder ; work ; +; |key_hash_generator:key_hash_generator_inst| ; 41 (41) ; 135 (135) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|key_holder:\key_holder_gen:1:key_holder_inst|key_hash_generator:key_hash_generator_inst ; key_hash_generator ; work ; +; |key_holder:\key_holder_gen:2:key_holder_inst| ; 218 (185) ; 384 (249) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|key_holder:\key_holder_gen:2:key_holder_inst ; key_holder ; work ; +; |key_hash_generator:key_hash_generator_inst| ; 33 (33) ; 135 (135) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|key_holder:\key_holder_gen:2:key_holder_inst|key_hash_generator:key_hash_generator_inst ; key_hash_generator ; work ; +; |key_holder:\key_holder_gen:3:key_holder_inst| ; 227 (182) ; 384 (249) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|key_holder:\key_holder_gen:3:key_holder_inst ; key_holder ; work ; +; |key_hash_generator:key_hash_generator_inst| ; 45 (45) ; 135 (135) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|key_holder:\key_holder_gen:3:key_holder_inst|key_hash_generator:key_hash_generator_inst ; key_hash_generator ; work ; +; |key_holder:\key_holder_gen:4:key_holder_inst| ; 219 (180) ; 384 (249) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|key_holder:\key_holder_gen:4:key_holder_inst ; key_holder ; work ; +; |key_hash_generator:key_hash_generator_inst| ; 39 (39) ; 135 (135) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|key_holder:\key_holder_gen:4:key_holder_inst|key_hash_generator:key_hash_generator_inst ; key_hash_generator ; work ; +; |mem_ctrl:\instance_mem_ctrl_gen:0:instance_mem_ctrl_inst| ; 40 (7) ; 23 (2) ; 800 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:0:instance_mem_ctrl_inst ; mem_ctrl ; work ; +; |FWFT_FIFO:burst_fifo_inst| ; 33 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:0:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 33 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:0:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ; +; |scfifo_kfk1:auto_generated| ; 33 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:0:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated ; scfifo_kfk1 ; work ; +; |a_dpfifo_qbb1:dpfifo| ; 33 (19) ; 21 (10) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:0:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo ; a_dpfifo_qbb1 ; work ; +; |altsyncram_e1k1:FIFOram| ; 0 (0) ; 0 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:0:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo|altsyncram_e1k1:FIFOram ; altsyncram_e1k1 ; work ; +; |cntr_e2b:rd_ptr_msb| ; 4 (4) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:0:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo|cntr_e2b:rd_ptr_msb ; cntr_e2b ; work ; +; |cntr_f2b:wr_ptr| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:0:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo|cntr_f2b:wr_ptr ; cntr_f2b ; work ; +; |cntr_r27:usedw_counter| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:0:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo|cntr_r27:usedw_counter ; cntr_r27 ; work ; +; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 288 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:0:instance_mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 288 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:0:instance_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ; +; |altsyncram_vkv3:auto_generated| ; 0 (0) ; 0 (0) ; 288 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:0:instance_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_vkv3:auto_generated ; altsyncram_vkv3 ; work ; +; |mem_ctrl:\instance_mem_ctrl_gen:1:instance_mem_ctrl_inst| ; 38 (5) ; 23 (2) ; 800 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:1:instance_mem_ctrl_inst ; mem_ctrl ; work ; +; |FWFT_FIFO:burst_fifo_inst| ; 33 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:1:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 33 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:1:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ; +; |scfifo_kfk1:auto_generated| ; 33 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:1:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated ; scfifo_kfk1 ; work ; +; |a_dpfifo_qbb1:dpfifo| ; 33 (19) ; 21 (10) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:1:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo ; a_dpfifo_qbb1 ; work ; +; |altsyncram_e1k1:FIFOram| ; 0 (0) ; 0 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:1:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo|altsyncram_e1k1:FIFOram ; altsyncram_e1k1 ; work ; +; |cntr_e2b:rd_ptr_msb| ; 4 (4) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:1:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo|cntr_e2b:rd_ptr_msb ; cntr_e2b ; work ; +; |cntr_f2b:wr_ptr| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:1:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo|cntr_f2b:wr_ptr ; cntr_f2b ; work ; +; |cntr_r27:usedw_counter| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:1:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo|cntr_r27:usedw_counter ; cntr_r27 ; work ; +; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 288 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:1:instance_mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 288 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:1:instance_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ; +; |altsyncram_vkv3:auto_generated| ; 0 (0) ; 0 (0) ; 288 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:1:instance_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_vkv3:auto_generated ; altsyncram_vkv3 ; work ; +; |mem_ctrl:\instance_mem_ctrl_gen:2:instance_mem_ctrl_inst| ; 38 (5) ; 23 (2) ; 800 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:2:instance_mem_ctrl_inst ; mem_ctrl ; work ; +; |FWFT_FIFO:burst_fifo_inst| ; 33 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:2:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 33 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:2:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ; +; |scfifo_kfk1:auto_generated| ; 33 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:2:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated ; scfifo_kfk1 ; work ; +; |a_dpfifo_qbb1:dpfifo| ; 33 (19) ; 21 (10) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:2:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo ; a_dpfifo_qbb1 ; work ; +; |altsyncram_e1k1:FIFOram| ; 0 (0) ; 0 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:2:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo|altsyncram_e1k1:FIFOram ; altsyncram_e1k1 ; work ; +; |cntr_e2b:rd_ptr_msb| ; 4 (4) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:2:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo|cntr_e2b:rd_ptr_msb ; cntr_e2b ; work ; +; |cntr_f2b:wr_ptr| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:2:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo|cntr_f2b:wr_ptr ; cntr_f2b ; work ; +; |cntr_r27:usedw_counter| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:2:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo|cntr_r27:usedw_counter ; cntr_r27 ; work ; +; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 288 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:2:instance_mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 288 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:2:instance_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ; +; |altsyncram_vkv3:auto_generated| ; 0 (0) ; 0 (0) ; 288 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:2:instance_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_vkv3:auto_generated ; altsyncram_vkv3 ; work ; +; |mem_ctrl:\instance_mem_ctrl_gen:3:instance_mem_ctrl_inst| ; 38 (5) ; 23 (2) ; 800 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:3:instance_mem_ctrl_inst ; mem_ctrl ; work ; +; |FWFT_FIFO:burst_fifo_inst| ; 33 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:3:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 33 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:3:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ; +; |scfifo_kfk1:auto_generated| ; 33 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:3:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated ; scfifo_kfk1 ; work ; +; |a_dpfifo_qbb1:dpfifo| ; 33 (19) ; 21 (10) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:3:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo ; a_dpfifo_qbb1 ; work ; +; |altsyncram_e1k1:FIFOram| ; 0 (0) ; 0 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:3:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo|altsyncram_e1k1:FIFOram ; altsyncram_e1k1 ; work ; +; |cntr_e2b:rd_ptr_msb| ; 4 (4) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:3:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo|cntr_e2b:rd_ptr_msb ; cntr_e2b ; work ; +; |cntr_f2b:wr_ptr| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:3:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo|cntr_f2b:wr_ptr ; cntr_f2b ; work ; +; |cntr_r27:usedw_counter| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:3:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo|cntr_r27:usedw_counter ; cntr_r27 ; work ; +; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 288 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:3:instance_mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 288 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:3:instance_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ; +; |altsyncram_vkv3:auto_generated| ; 0 (0) ; 0 (0) ; 288 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:3:instance_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_vkv3:auto_generated ; altsyncram_vkv3 ; work ; +; |mem_ctrl:\instance_mem_ctrl_gen:4:instance_mem_ctrl_inst| ; 38 (5) ; 23 (2) ; 800 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:4:instance_mem_ctrl_inst ; mem_ctrl ; work ; +; |FWFT_FIFO:burst_fifo_inst| ; 33 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:4:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 33 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:4:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ; +; |scfifo_kfk1:auto_generated| ; 33 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:4:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated ; scfifo_kfk1 ; work ; +; |a_dpfifo_qbb1:dpfifo| ; 33 (19) ; 21 (10) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:4:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo ; a_dpfifo_qbb1 ; work ; +; |altsyncram_e1k1:FIFOram| ; 0 (0) ; 0 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:4:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo|altsyncram_e1k1:FIFOram ; altsyncram_e1k1 ; work ; +; |cntr_e2b:rd_ptr_msb| ; 4 (4) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:4:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo|cntr_e2b:rd_ptr_msb ; cntr_e2b ; work ; +; |cntr_f2b:wr_ptr| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:4:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo|cntr_f2b:wr_ptr ; cntr_f2b ; work ; +; |cntr_r27:usedw_counter| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:4:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo|cntr_r27:usedw_counter ; cntr_r27 ; work ; +; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 288 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:4:instance_mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 288 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:4:instance_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ; +; |altsyncram_vkv3:auto_generated| ; 0 (0) ; 0 (0) ; 288 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:4:instance_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_vkv3:auto_generated ; altsyncram_vkv3 ; work ; +; |mem_ctrl:\payload_mem_ctrl_gen:0:payload_mem_ctrl_inst| ; 39 (6) ; 23 (2) ; 3680 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:0:payload_mem_ctrl_inst ; mem_ctrl ; work ; +; |FWFT_FIFO:burst_fifo_inst| ; 33 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:0:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 33 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:0:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ; +; |scfifo_kfk1:auto_generated| ; 33 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:0:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated ; scfifo_kfk1 ; work ; +; |a_dpfifo_qbb1:dpfifo| ; 33 (19) ; 21 (10) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:0:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo ; a_dpfifo_qbb1 ; work ; +; |altsyncram_e1k1:FIFOram| ; 0 (0) ; 0 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:0:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo|altsyncram_e1k1:FIFOram ; altsyncram_e1k1 ; work ; +; |cntr_e2b:rd_ptr_msb| ; 4 (4) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:0:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo|cntr_e2b:rd_ptr_msb ; cntr_e2b ; work ; +; |cntr_f2b:wr_ptr| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:0:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo|cntr_f2b:wr_ptr ; cntr_f2b ; work ; +; |cntr_r27:usedw_counter| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:0:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo|cntr_r27:usedw_counter ; cntr_r27 ; work ; +; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 3168 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:0:payload_mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 3168 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:0:payload_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ; +; |altsyncram_aov3:auto_generated| ; 0 (0) ; 0 (0) ; 3168 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:0:payload_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_aov3:auto_generated ; altsyncram_aov3 ; work ; +; |mem_ctrl:\payload_mem_ctrl_gen:1:payload_mem_ctrl_inst| ; 69 (15) ; 35 (2) ; 41760 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:1:payload_mem_ctrl_inst ; mem_ctrl ; work ; +; |FWFT_FIFO:burst_fifo_inst| ; 54 (5) ; 33 (0) ; 4096 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:1:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 49 (0) ; 33 (0) ; 4096 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:1:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ; +; |scfifo_oik1:auto_generated| ; 49 (0) ; 33 (0) ; 4096 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:1:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_oik1:auto_generated ; scfifo_oik1 ; work ; +; |a_dpfifo_ueb1:dpfifo| ; 49 (26) ; 33 (13) ; 4096 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:1:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_oik1:auto_generated|a_dpfifo_ueb1:dpfifo ; a_dpfifo_ueb1 ; work ; +; |altsyncram_s4k1:FIFOram| ; 0 (0) ; 0 (0) ; 4096 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:1:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_oik1:auto_generated|a_dpfifo_ueb1:dpfifo|altsyncram_s4k1:FIFOram ; altsyncram_s4k1 ; work ; +; |cntr_h2b:rd_ptr_msb| ; 7 (7) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:1:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_oik1:auto_generated|a_dpfifo_ueb1:dpfifo|cntr_h2b:rd_ptr_msb ; cntr_h2b ; work ; +; |cntr_i2b:wr_ptr| ; 8 (8) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:1:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_oik1:auto_generated|a_dpfifo_ueb1:dpfifo|cntr_i2b:wr_ptr ; cntr_i2b ; work ; +; |cntr_u27:usedw_counter| ; 8 (8) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:1:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_oik1:auto_generated|a_dpfifo_ueb1:dpfifo|cntr_u27:usedw_counter ; cntr_u27 ; work ; +; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 37664 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:1:payload_mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 37664 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:1:payload_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ; +; |altsyncram_6rv3:auto_generated| ; 0 (0) ; 0 (0) ; 37664 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:1:payload_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_6rv3:auto_generated ; altsyncram_6rv3 ; work ; +; |mem_ctrl:\payload_mem_ctrl_gen:2:payload_mem_ctrl_inst| ; 88 (18) ; 47 (2) ; 246432 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:2:payload_mem_ctrl_inst ; mem_ctrl ; work ; +; |FWFT_FIFO:burst_fifo_inst| ; 70 (5) ; 45 (0) ; 32768 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:2:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 65 (0) ; 45 (0) ; 32768 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:2:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ; +; |scfifo_5kk1:auto_generated| ; 65 (0) ; 45 (0) ; 32768 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:2:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_5kk1:auto_generated ; scfifo_5kk1 ; work ; +; |a_dpfifo_bgb1:dpfifo| ; 65 (33) ; 45 (16) ; 32768 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:2:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_5kk1:auto_generated|a_dpfifo_bgb1:dpfifo ; a_dpfifo_bgb1 ; work ; +; |altsyncram_8ak1:FIFOram| ; 0 (0) ; 0 (0) ; 32768 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:2:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_5kk1:auto_generated|a_dpfifo_bgb1:dpfifo|altsyncram_8ak1:FIFOram ; altsyncram_8ak1 ; work ; +; |cntr_847:usedw_counter| ; 11 (11) ; 10 (10) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:2:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_5kk1:auto_generated|a_dpfifo_bgb1:dpfifo|cntr_847:usedw_counter ; cntr_847 ; work ; +; |cntr_k2b:rd_ptr_msb| ; 10 (10) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:2:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_5kk1:auto_generated|a_dpfifo_bgb1:dpfifo|cntr_k2b:rd_ptr_msb ; cntr_k2b ; work ; +; |cntr_s3b:wr_ptr| ; 11 (11) ; 10 (10) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:2:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_5kk1:auto_generated|a_dpfifo_bgb1:dpfifo|cntr_s3b:wr_ptr ; cntr_s3b ; work ; +; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 213664 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:2:payload_mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 213664 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:2:payload_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ; +; |altsyncram_grv3:auto_generated| ; 0 (0) ; 0 (0) ; 213664 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:2:payload_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_grv3:auto_generated ; altsyncram_grv3 ; work ; +; |mem_ctrl:\payload_mem_ctrl_gen:3:payload_mem_ctrl_inst| ; 72 (16) ; 35 (2) ; 41408 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:3:payload_mem_ctrl_inst ; mem_ctrl ; work ; +; |FWFT_FIFO:burst_fifo_inst| ; 56 (7) ; 33 (0) ; 4096 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:3:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 49 (0) ; 33 (0) ; 4096 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:3:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ; +; |scfifo_pik1:auto_generated| ; 49 (0) ; 33 (0) ; 4096 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:3:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_pik1:auto_generated ; scfifo_pik1 ; work ; +; |a_dpfifo_veb1:dpfifo| ; 49 (26) ; 33 (13) ; 4096 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:3:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_pik1:auto_generated|a_dpfifo_veb1:dpfifo ; a_dpfifo_veb1 ; work ; +; |altsyncram_s4k1:FIFOram| ; 0 (0) ; 0 (0) ; 4096 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:3:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_pik1:auto_generated|a_dpfifo_veb1:dpfifo|altsyncram_s4k1:FIFOram ; altsyncram_s4k1 ; work ; +; |cntr_h2b:rd_ptr_msb| ; 7 (7) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:3:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_pik1:auto_generated|a_dpfifo_veb1:dpfifo|cntr_h2b:rd_ptr_msb ; cntr_h2b ; work ; +; |cntr_i2b:wr_ptr| ; 8 (8) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:3:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_pik1:auto_generated|a_dpfifo_veb1:dpfifo|cntr_i2b:wr_ptr ; cntr_i2b ; work ; +; |cntr_u27:usedw_counter| ; 8 (8) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:3:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_pik1:auto_generated|a_dpfifo_veb1:dpfifo|cntr_u27:usedw_counter ; cntr_u27 ; work ; +; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 37312 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:3:payload_mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 37312 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:3:payload_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ; +; |altsyncram_5rv3:auto_generated| ; 0 (0) ; 0 (0) ; 37312 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:3:payload_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_5rv3:auto_generated ; altsyncram_5rv3 ; work ; +; |mem_ctrl:\payload_mem_ctrl_gen:4:payload_mem_ctrl_inst| ; 90 (18) ; 47 (2) ; 72896 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:4:payload_mem_ctrl_inst ; mem_ctrl ; work ; +; |FWFT_FIFO:burst_fifo_inst| ; 72 (8) ; 45 (0) ; 32768 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:4:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 64 (0) ; 45 (0) ; 32768 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:4:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ; +; |scfifo_7kk1:auto_generated| ; 64 (0) ; 45 (0) ; 32768 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:4:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_7kk1:auto_generated ; scfifo_7kk1 ; work ; +; |a_dpfifo_dgb1:dpfifo| ; 64 (32) ; 45 (16) ; 32768 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:4:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_7kk1:auto_generated|a_dpfifo_dgb1:dpfifo ; a_dpfifo_dgb1 ; work ; +; |altsyncram_8ak1:FIFOram| ; 0 (0) ; 0 (0) ; 32768 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:4:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_7kk1:auto_generated|a_dpfifo_dgb1:dpfifo|altsyncram_8ak1:FIFOram ; altsyncram_8ak1 ; work ; +; |cntr_847:usedw_counter| ; 11 (11) ; 10 (10) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:4:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_7kk1:auto_generated|a_dpfifo_dgb1:dpfifo|cntr_847:usedw_counter ; cntr_847 ; work ; +; |cntr_k2b:rd_ptr_msb| ; 10 (10) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:4:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_7kk1:auto_generated|a_dpfifo_dgb1:dpfifo|cntr_k2b:rd_ptr_msb ; cntr_k2b ; work ; +; |cntr_s3b:wr_ptr| ; 11 (11) ; 10 (10) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:4:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_7kk1:auto_generated|a_dpfifo_dgb1:dpfifo|cntr_s3b:wr_ptr ; cntr_s3b ; work ; +; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 40128 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:4:payload_mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 40128 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:4:payload_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ; +; |altsyncram_7rv3:auto_generated| ; 0 (0) ; 0 (0) ; 40128 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:4:payload_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_7rv3:auto_generated ; altsyncram_7rv3 ; work ; +; |mem_ctrl:\sample_mem_ctrl_gen:0:sample_mem_ctrl_inst| ; 44 (7) ; 23 (2) ; 4384 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:0:sample_mem_ctrl_inst ; mem_ctrl ; work ; +; |FWFT_FIFO:burst_fifo_inst| ; 37 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:0:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 37 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:0:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ; +; |scfifo_tgk1:auto_generated| ; 37 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:0:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated ; scfifo_tgk1 ; work ; +; |a_dpfifo_3db1:dpfifo| ; 37 (23) ; 21 (10) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:0:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated|a_dpfifo_3db1:dpfifo ; a_dpfifo_3db1 ; work ; +; |altsyncram_e1k1:FIFOram| ; 0 (0) ; 0 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:0:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated|a_dpfifo_3db1:dpfifo|altsyncram_e1k1:FIFOram ; altsyncram_e1k1 ; work ; +; |cntr_e2b:rd_ptr_msb| ; 4 (4) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:0:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated|a_dpfifo_3db1:dpfifo|cntr_e2b:rd_ptr_msb ; cntr_e2b ; work ; +; |cntr_f2b:wr_ptr| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:0:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated|a_dpfifo_3db1:dpfifo|cntr_f2b:wr_ptr ; cntr_f2b ; work ; +; |cntr_r27:usedw_counter| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:0:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated|a_dpfifo_3db1:dpfifo|cntr_r27:usedw_counter ; cntr_r27 ; work ; +; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 3872 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:0:sample_mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 3872 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:0:sample_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ; +; |altsyncram_tnv3:auto_generated| ; 0 (0) ; 0 (0) ; 3872 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:0:sample_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_tnv3:auto_generated ; altsyncram_tnv3 ; work ; +; |mem_ctrl:\sample_mem_ctrl_gen:1:sample_mem_ctrl_inst| ; 42 (5) ; 23 (2) ; 4384 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:1:sample_mem_ctrl_inst ; mem_ctrl ; work ; +; |FWFT_FIFO:burst_fifo_inst| ; 37 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:1:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 37 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:1:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ; +; |scfifo_tgk1:auto_generated| ; 37 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:1:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated ; scfifo_tgk1 ; work ; +; |a_dpfifo_3db1:dpfifo| ; 37 (23) ; 21 (10) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:1:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated|a_dpfifo_3db1:dpfifo ; a_dpfifo_3db1 ; work ; +; |altsyncram_e1k1:FIFOram| ; 0 (0) ; 0 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:1:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated|a_dpfifo_3db1:dpfifo|altsyncram_e1k1:FIFOram ; altsyncram_e1k1 ; work ; +; |cntr_e2b:rd_ptr_msb| ; 4 (4) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:1:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated|a_dpfifo_3db1:dpfifo|cntr_e2b:rd_ptr_msb ; cntr_e2b ; work ; +; |cntr_f2b:wr_ptr| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:1:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated|a_dpfifo_3db1:dpfifo|cntr_f2b:wr_ptr ; cntr_f2b ; work ; +; |cntr_r27:usedw_counter| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:1:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated|a_dpfifo_3db1:dpfifo|cntr_r27:usedw_counter ; cntr_r27 ; work ; +; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 3872 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:1:sample_mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 3872 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:1:sample_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ; +; |altsyncram_tnv3:auto_generated| ; 0 (0) ; 0 (0) ; 3872 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:1:sample_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_tnv3:auto_generated ; altsyncram_tnv3 ; work ; +; |mem_ctrl:\sample_mem_ctrl_gen:2:sample_mem_ctrl_inst| ; 41 (5) ; 23 (2) ; 4384 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:2:sample_mem_ctrl_inst ; mem_ctrl ; work ; +; |FWFT_FIFO:burst_fifo_inst| ; 36 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:2:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 36 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:2:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ; +; |scfifo_tgk1:auto_generated| ; 36 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:2:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated ; scfifo_tgk1 ; work ; +; |a_dpfifo_3db1:dpfifo| ; 36 (22) ; 21 (10) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:2:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated|a_dpfifo_3db1:dpfifo ; a_dpfifo_3db1 ; work ; +; |altsyncram_e1k1:FIFOram| ; 0 (0) ; 0 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:2:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated|a_dpfifo_3db1:dpfifo|altsyncram_e1k1:FIFOram ; altsyncram_e1k1 ; work ; +; |cntr_e2b:rd_ptr_msb| ; 4 (4) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:2:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated|a_dpfifo_3db1:dpfifo|cntr_e2b:rd_ptr_msb ; cntr_e2b ; work ; +; |cntr_f2b:wr_ptr| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:2:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated|a_dpfifo_3db1:dpfifo|cntr_f2b:wr_ptr ; cntr_f2b ; work ; +; |cntr_r27:usedw_counter| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:2:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated|a_dpfifo_3db1:dpfifo|cntr_r27:usedw_counter ; cntr_r27 ; work ; +; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 3872 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:2:sample_mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 3872 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:2:sample_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ; +; |altsyncram_tnv3:auto_generated| ; 0 (0) ; 0 (0) ; 3872 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:2:sample_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_tnv3:auto_generated ; altsyncram_tnv3 ; work ; +; |mem_ctrl:\sample_mem_ctrl_gen:3:sample_mem_ctrl_inst| ; 42 (5) ; 23 (2) ; 4384 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:3:sample_mem_ctrl_inst ; mem_ctrl ; work ; +; |FWFT_FIFO:burst_fifo_inst| ; 37 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:3:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 37 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:3:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ; +; |scfifo_tgk1:auto_generated| ; 37 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:3:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated ; scfifo_tgk1 ; work ; +; |a_dpfifo_3db1:dpfifo| ; 37 (23) ; 21 (10) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:3:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated|a_dpfifo_3db1:dpfifo ; a_dpfifo_3db1 ; work ; +; |altsyncram_e1k1:FIFOram| ; 0 (0) ; 0 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:3:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated|a_dpfifo_3db1:dpfifo|altsyncram_e1k1:FIFOram ; altsyncram_e1k1 ; work ; +; |cntr_e2b:rd_ptr_msb| ; 4 (4) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:3:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated|a_dpfifo_3db1:dpfifo|cntr_e2b:rd_ptr_msb ; cntr_e2b ; work ; +; |cntr_f2b:wr_ptr| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:3:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated|a_dpfifo_3db1:dpfifo|cntr_f2b:wr_ptr ; cntr_f2b ; work ; +; |cntr_r27:usedw_counter| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:3:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated|a_dpfifo_3db1:dpfifo|cntr_r27:usedw_counter ; cntr_r27 ; work ; +; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 3872 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:3:sample_mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 3872 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:3:sample_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ; +; |altsyncram_tnv3:auto_generated| ; 0 (0) ; 0 (0) ; 3872 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:3:sample_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_tnv3:auto_generated ; altsyncram_tnv3 ; work ; +; |mem_ctrl:\sample_mem_ctrl_gen:4:sample_mem_ctrl_inst| ; 42 (5) ; 23 (2) ; 1216 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:4:sample_mem_ctrl_inst ; mem_ctrl ; work ; +; |FWFT_FIFO:burst_fifo_inst| ; 37 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:4:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 37 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:4:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ; +; |scfifo_tgk1:auto_generated| ; 37 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:4:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated ; scfifo_tgk1 ; work ; +; |a_dpfifo_3db1:dpfifo| ; 37 (23) ; 21 (10) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:4:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated|a_dpfifo_3db1:dpfifo ; a_dpfifo_3db1 ; work ; +; |altsyncram_e1k1:FIFOram| ; 0 (0) ; 0 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:4:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated|a_dpfifo_3db1:dpfifo|altsyncram_e1k1:FIFOram ; altsyncram_e1k1 ; work ; +; |cntr_e2b:rd_ptr_msb| ; 4 (4) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:4:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated|a_dpfifo_3db1:dpfifo|cntr_e2b:rd_ptr_msb ; cntr_e2b ; work ; +; |cntr_f2b:wr_ptr| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:4:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated|a_dpfifo_3db1:dpfifo|cntr_f2b:wr_ptr ; cntr_f2b ; work ; +; |cntr_r27:usedw_counter| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:4:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated|a_dpfifo_3db1:dpfifo|cntr_r27:usedw_counter ; cntr_r27 ; work ; +; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 704 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:4:sample_mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 704 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:4:sample_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ; +; |altsyncram_fmv3:auto_generated| ; 0 (0) ; 0 (0) ; 704 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:4:sample_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_fmv3:auto_generated ; altsyncram_fmv3 ; work ; +; |ros_static_discovery_writer:ros_discovery_writer_inst| ; 51 (51) ; 12 (12) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|ros_static_discovery_writer:ros_discovery_writer_inst ; ros_static_discovery_writer ; work ; +; |ros_time_converter:ros_time_converter_inst| ; 122 (63) ; 240 (95) ; 0 ; 4 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|ros_time_converter:ros_time_converter_inst ; ros_time_converter ; work ; +; |mult:mult_inst| ; 59 (0) ; 145 (0) ; 0 ; 4 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|ros_time_converter:ros_time_converter_inst|mult:mult_inst ; mult ; work ; +; |lpm_mult:lpm_mult_component| ; 59 (0) ; 145 (0) ; 0 ; 4 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|ros_time_converter:ros_time_converter_inst|mult:mult_inst|lpm_mult:lpm_mult_component ; lpm_mult ; work ; +; |mult_ilr:auto_generated| ; 59 (59) ; 145 (145) ; 0 ; 4 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|ros_time_converter:ros_time_converter_inst|mult:mult_inst|lpm_mult:lpm_mult_component|mult_ilr:auto_generated ; mult_ilr ; work ; +; |rtps_discovery_module:rtps_discovery_module_inst| ; 8752 (8705) ; 3240 (3213) ; 41024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_discovery_module:rtps_discovery_module_inst ; rtps_discovery_module ; work ; +; |mem_ctrl:mem_ctrl_inst| ; 47 (6) ; 27 (2) ; 41024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_discovery_module:rtps_discovery_module_inst|mem_ctrl:mem_ctrl_inst ; mem_ctrl ; work ; +; |FWFT_FIFO:burst_fifo_inst| ; 41 (0) ; 25 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_discovery_module:rtps_discovery_module_inst|mem_ctrl:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 41 (0) ; 25 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_discovery_module:rtps_discovery_module_inst|mem_ctrl:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ; +; |scfifo_3hk1:auto_generated| ; 41 (0) ; 25 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_discovery_module:rtps_discovery_module_inst|mem_ctrl:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_3hk1:auto_generated ; scfifo_3hk1 ; work ; +; |a_dpfifo_9db1:dpfifo| ; 41 (24) ; 25 (11) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_discovery_module:rtps_discovery_module_inst|mem_ctrl:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_3hk1:auto_generated|a_dpfifo_9db1:dpfifo ; a_dpfifo_9db1 ; work ; +; |altsyncram_c1k1:FIFOram| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_discovery_module:rtps_discovery_module_inst|mem_ctrl:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_3hk1:auto_generated|a_dpfifo_9db1:dpfifo|altsyncram_c1k1:FIFOram ; altsyncram_c1k1 ; work ; +; |cntr_f2b:rd_ptr_msb| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_discovery_module:rtps_discovery_module_inst|mem_ctrl:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_3hk1:auto_generated|a_dpfifo_9db1:dpfifo|cntr_f2b:rd_ptr_msb ; cntr_f2b ; work ; +; |cntr_g2b:wr_ptr| ; 6 (6) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_discovery_module:rtps_discovery_module_inst|mem_ctrl:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_3hk1:auto_generated|a_dpfifo_9db1:dpfifo|cntr_g2b:wr_ptr ; cntr_g2b ; work ; +; |cntr_s27:usedw_counter| ; 6 (6) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_discovery_module:rtps_discovery_module_inst|mem_ctrl:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_3hk1:auto_generated|a_dpfifo_9db1:dpfifo|cntr_s27:usedw_counter ; cntr_s27 ; work ; +; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 40000 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_discovery_module:rtps_discovery_module_inst|mem_ctrl:mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 40000 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_discovery_module:rtps_discovery_module_inst|mem_ctrl:mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ; +; |altsyncram_sqv3:auto_generated| ; 0 (0) ; 0 (0) ; 40000 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_discovery_module:rtps_discovery_module_inst|mem_ctrl:mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_sqv3:auto_generated ; altsyncram_sqv3 ; work ; +; |rtps_handler:rtps_handler_inst| ; 1670 (1670) ; 964 (964) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_handler:rtps_handler_inst ; rtps_handler ; work ; +; |rtps_out:rtps_out_inst| ; 364 (310) ; 185 (173) ; 524256 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_out:rtps_out_inst ; rtps_out ; work ; +; |dp_mem_ctrl:buffer_inst| ; 54 (3) ; 12 (2) ; 524256 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_out:rtps_out_inst|dp_mem_ctrl:buffer_inst ; dp_mem_ctrl ; work ; +; |FWFT_FIFO:burst_fifo_inst| ; 15 (0) ; 9 (0) ; 64 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_out:rtps_out_inst|dp_mem_ctrl:buffer_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 15 (0) ; 9 (0) ; 64 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_out:rtps_out_inst|dp_mem_ctrl:buffer_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ; +; |scfifo_afk1:auto_generated| ; 15 (0) ; 9 (0) ; 64 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_out:rtps_out_inst|dp_mem_ctrl:buffer_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_afk1:auto_generated ; scfifo_afk1 ; work ; +; |a_dpfifo_gbb1:dpfifo| ; 15 (11) ; 9 (7) ; 64 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_out:rtps_out_inst|dp_mem_ctrl:buffer_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_afk1:auto_generated|a_dpfifo_gbb1:dpfifo ; a_dpfifo_gbb1 ; work ; +; |altsyncram_utj1:FIFOram| ; 0 (0) ; 0 (0) ; 64 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_out:rtps_out_inst|dp_mem_ctrl:buffer_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_afk1:auto_generated|a_dpfifo_gbb1:dpfifo|altsyncram_utj1:FIFOram ; altsyncram_utj1 ; work ; +; |cntr_c2b:wr_ptr| ; 2 (2) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_out:rtps_out_inst|dp_mem_ctrl:buffer_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_afk1:auto_generated|a_dpfifo_gbb1:dpfifo|cntr_c2b:wr_ptr ; cntr_c2b ; work ; +; |cntr_o27:usedw_counter| ; 2 (2) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_out:rtps_out_inst|dp_mem_ctrl:buffer_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_afk1:auto_generated|a_dpfifo_gbb1:dpfifo|cntr_o27:usedw_counter ; cntr_o27 ; work ; +; |dual_port_ram:ram_inst| ; 36 (0) ; 1 (0) ; 524192 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_out:rtps_out_inst|dp_mem_ctrl:buffer_inst|dual_port_ram:ram_inst ; dual_port_ram ; work ; +; |altsyncram:altsyncram_component| ; 36 (0) ; 1 (0) ; 524192 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_out:rtps_out_inst|dp_mem_ctrl:buffer_inst|dual_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ; +; |altsyncram_1qv3:auto_generated| ; 36 (0) ; 1 (1) ; 524192 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_out:rtps_out_inst|dp_mem_ctrl:buffer_inst|dual_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_1qv3:auto_generated ; altsyncram_1qv3 ; work ; +; |decode_5la:rden_decode_b| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_out:rtps_out_inst|dp_mem_ctrl:buffer_inst|dual_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_1qv3:auto_generated|decode_5la:rden_decode_b ; decode_5la ; work ; +; |decode_5la:wren_decode_a| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_out:rtps_out_inst|dp_mem_ctrl:buffer_inst|dual_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_1qv3:auto_generated|decode_5la:wren_decode_a ; decode_5la ; work ; +; |mux_2hb:mux3| ; 32 (32) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_out:rtps_out_inst|dp_mem_ctrl:buffer_inst|dual_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_1qv3:auto_generated|mux_2hb:mux3 ; mux_2hb ; work ; +; |rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst| ; 5594 (5424) ; 2398 (2282) ; 85024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst ; rtps_reader ; work ; +; |mem_ctrl:\mem_ctrl_gen:0:mem_ctrl_inst| ; 44 (6) ; 27 (2) ; 28224 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:0:mem_ctrl_inst ; mem_ctrl ; work ; +; |FWFT_FIFO:burst_fifo_inst| ; 38 (0) ; 25 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:0:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 38 (0) ; 25 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:0:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ; +; |scfifo_4hk1:auto_generated| ; 38 (0) ; 25 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:0:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated ; scfifo_4hk1 ; work ; +; |a_dpfifo_adb1:dpfifo| ; 38 (21) ; 25 (11) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:0:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo ; a_dpfifo_adb1 ; work ; +; |altsyncram_c1k1:FIFOram| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:0:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|altsyncram_c1k1:FIFOram ; altsyncram_c1k1 ; work ; +; |cntr_f2b:rd_ptr_msb| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:0:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|cntr_f2b:rd_ptr_msb ; cntr_f2b ; work ; +; |cntr_g2b:wr_ptr| ; 6 (6) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:0:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|cntr_g2b:wr_ptr ; cntr_g2b ; work ; +; |cntr_s27:usedw_counter| ; 6 (6) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:0:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|cntr_s27:usedw_counter ; cntr_s27 ; work ; +; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 27200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:0:mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 27200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:0:mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ; +; |altsyncram_gpv3:auto_generated| ; 0 (0) ; 0 (0) ; 27200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:0:mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_gpv3:auto_generated ; altsyncram_gpv3 ; work ; +; |mem_ctrl:\mem_ctrl_gen:1:mem_ctrl_inst| ; 44 (6) ; 27 (2) ; 28224 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:1:mem_ctrl_inst ; mem_ctrl ; work ; +; |FWFT_FIFO:burst_fifo_inst| ; 38 (0) ; 25 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:1:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 38 (0) ; 25 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:1:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ; +; |scfifo_4hk1:auto_generated| ; 38 (0) ; 25 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:1:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated ; scfifo_4hk1 ; work ; +; |a_dpfifo_adb1:dpfifo| ; 38 (21) ; 25 (11) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:1:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo ; a_dpfifo_adb1 ; work ; +; |altsyncram_c1k1:FIFOram| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:1:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|altsyncram_c1k1:FIFOram ; altsyncram_c1k1 ; work ; +; |cntr_f2b:rd_ptr_msb| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:1:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|cntr_f2b:rd_ptr_msb ; cntr_f2b ; work ; +; |cntr_g2b:wr_ptr| ; 6 (6) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:1:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|cntr_g2b:wr_ptr ; cntr_g2b ; work ; +; |cntr_s27:usedw_counter| ; 6 (6) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:1:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|cntr_s27:usedw_counter ; cntr_s27 ; work ; +; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 27200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:1:mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 27200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:1:mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ; +; |altsyncram_gpv3:auto_generated| ; 0 (0) ; 0 (0) ; 27200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:1:mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_gpv3:auto_generated ; altsyncram_gpv3 ; work ; +; |mem_ctrl:\mem_ctrl_gen:2:mem_ctrl_inst| ; 44 (6) ; 27 (2) ; 28224 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:2:mem_ctrl_inst ; mem_ctrl ; work ; +; |FWFT_FIFO:burst_fifo_inst| ; 38 (0) ; 25 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:2:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 38 (0) ; 25 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:2:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ; +; |scfifo_4hk1:auto_generated| ; 38 (0) ; 25 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:2:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated ; scfifo_4hk1 ; work ; +; |a_dpfifo_adb1:dpfifo| ; 38 (21) ; 25 (11) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:2:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo ; a_dpfifo_adb1 ; work ; +; |altsyncram_c1k1:FIFOram| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:2:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|altsyncram_c1k1:FIFOram ; altsyncram_c1k1 ; work ; +; |cntr_f2b:rd_ptr_msb| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:2:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|cntr_f2b:rd_ptr_msb ; cntr_f2b ; work ; +; |cntr_g2b:wr_ptr| ; 6 (6) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:2:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|cntr_g2b:wr_ptr ; cntr_g2b ; work ; +; |cntr_s27:usedw_counter| ; 6 (6) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:2:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|cntr_s27:usedw_counter ; cntr_s27 ; work ; +; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 27200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:2:mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 27200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:2:mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ; +; |altsyncram_gpv3:auto_generated| ; 0 (0) ; 0 (0) ; 27200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:2:mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_gpv3:auto_generated ; altsyncram_gpv3 ; work ; +; |mem_ctrl:payload_mem_inst| ; 38 (4) ; 35 (2) ; 352 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:payload_mem_inst ; mem_ctrl ; work ; +; |FWFT_FIFO:burst_fifo_inst| ; 34 (0) ; 33 (0) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:payload_mem_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 34 (0) ; 33 (0) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:payload_mem_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ; +; |a_regfifo:subfifo| ; 34 (34) ; 33 (33) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:payload_mem_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|a_regfifo:subfifo ; a_regfifo ; work ; +; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 352 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:payload_mem_inst|single_port_ram:ram_inst ; single_port_ram ; work ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 352 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:payload_mem_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ; +; |altsyncram_8mv3:auto_generated| ; 0 (0) ; 0 (0) ; 352 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:payload_mem_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_8mv3:auto_generated ; altsyncram_8mv3 ; work ; +; |rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst| ; 6869 (6609) ; 3154 (2992) ; 169344 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst ; rtps_writer ; work ; +; |mem_ctrl:\mem_ctrl_gen:0:mem_ctrl_inst| ; 45 (7) ; 27 (2) ; 28224 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:0:mem_ctrl_inst ; mem_ctrl ; work ; +; |FWFT_FIFO:burst_fifo_inst| ; 38 (0) ; 25 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:0:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 38 (0) ; 25 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:0:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ; +; |scfifo_4hk1:auto_generated| ; 38 (0) ; 25 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:0:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated ; scfifo_4hk1 ; work ; +; |a_dpfifo_adb1:dpfifo| ; 38 (21) ; 25 (11) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:0:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo ; a_dpfifo_adb1 ; work ; +; |altsyncram_c1k1:FIFOram| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:0:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|altsyncram_c1k1:FIFOram ; altsyncram_c1k1 ; work ; +; |cntr_f2b:rd_ptr_msb| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:0:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|cntr_f2b:rd_ptr_msb ; cntr_f2b ; work ; +; |cntr_g2b:wr_ptr| ; 6 (6) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:0:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|cntr_g2b:wr_ptr ; cntr_g2b ; work ; +; |cntr_s27:usedw_counter| ; 6 (6) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:0:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|cntr_s27:usedw_counter ; cntr_s27 ; work ; +; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 27200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:0:mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 27200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:0:mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ; +; |altsyncram_gpv3:auto_generated| ; 0 (0) ; 0 (0) ; 27200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:0:mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_gpv3:auto_generated ; altsyncram_gpv3 ; work ; +; |mem_ctrl:\mem_ctrl_gen:1:mem_ctrl_inst| ; 43 (5) ; 27 (2) ; 28224 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:1:mem_ctrl_inst ; mem_ctrl ; work ; +; |FWFT_FIFO:burst_fifo_inst| ; 38 (0) ; 25 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:1:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 38 (0) ; 25 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:1:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ; +; |scfifo_4hk1:auto_generated| ; 38 (0) ; 25 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:1:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated ; scfifo_4hk1 ; work ; +; |a_dpfifo_adb1:dpfifo| ; 38 (21) ; 25 (11) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:1:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo ; a_dpfifo_adb1 ; work ; +; |altsyncram_c1k1:FIFOram| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:1:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|altsyncram_c1k1:FIFOram ; altsyncram_c1k1 ; work ; +; |cntr_f2b:rd_ptr_msb| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:1:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|cntr_f2b:rd_ptr_msb ; cntr_f2b ; work ; +; |cntr_g2b:wr_ptr| ; 6 (6) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:1:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|cntr_g2b:wr_ptr ; cntr_g2b ; work ; +; |cntr_s27:usedw_counter| ; 6 (6) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:1:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|cntr_s27:usedw_counter ; cntr_s27 ; work ; +; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 27200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:1:mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 27200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:1:mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ; +; |altsyncram_gpv3:auto_generated| ; 0 (0) ; 0 (0) ; 27200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:1:mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_gpv3:auto_generated ; altsyncram_gpv3 ; work ; +; |mem_ctrl:\mem_ctrl_gen:2:mem_ctrl_inst| ; 43 (5) ; 27 (2) ; 28224 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:2:mem_ctrl_inst ; mem_ctrl ; work ; +; |FWFT_FIFO:burst_fifo_inst| ; 38 (0) ; 25 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:2:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 38 (0) ; 25 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:2:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ; +; |scfifo_4hk1:auto_generated| ; 38 (0) ; 25 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:2:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated ; scfifo_4hk1 ; work ; +; |a_dpfifo_adb1:dpfifo| ; 38 (21) ; 25 (11) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:2:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo ; a_dpfifo_adb1 ; work ; +; |altsyncram_c1k1:FIFOram| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:2:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|altsyncram_c1k1:FIFOram ; altsyncram_c1k1 ; work ; +; |cntr_f2b:rd_ptr_msb| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:2:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|cntr_f2b:rd_ptr_msb ; cntr_f2b ; work ; +; |cntr_g2b:wr_ptr| ; 6 (6) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:2:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|cntr_g2b:wr_ptr ; cntr_g2b ; work ; +; |cntr_s27:usedw_counter| ; 6 (6) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:2:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|cntr_s27:usedw_counter ; cntr_s27 ; work ; +; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 27200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:2:mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 27200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:2:mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ; +; |altsyncram_gpv3:auto_generated| ; 0 (0) ; 0 (0) ; 27200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:2:mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_gpv3:auto_generated ; altsyncram_gpv3 ; work ; +; |mem_ctrl:\mem_ctrl_gen:3:mem_ctrl_inst| ; 43 (5) ; 27 (2) ; 28224 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:3:mem_ctrl_inst ; mem_ctrl ; work ; +; |FWFT_FIFO:burst_fifo_inst| ; 38 (0) ; 25 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:3:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 38 (0) ; 25 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:3:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ; +; |scfifo_4hk1:auto_generated| ; 38 (0) ; 25 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:3:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated ; scfifo_4hk1 ; work ; +; |a_dpfifo_adb1:dpfifo| ; 38 (21) ; 25 (11) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:3:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo ; a_dpfifo_adb1 ; work ; +; |altsyncram_c1k1:FIFOram| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:3:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|altsyncram_c1k1:FIFOram ; altsyncram_c1k1 ; work ; +; |cntr_f2b:rd_ptr_msb| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:3:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|cntr_f2b:rd_ptr_msb ; cntr_f2b ; work ; +; |cntr_g2b:wr_ptr| ; 6 (6) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:3:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|cntr_g2b:wr_ptr ; cntr_g2b ; work ; +; |cntr_s27:usedw_counter| ; 6 (6) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:3:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|cntr_s27:usedw_counter ; cntr_s27 ; work ; +; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 27200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:3:mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 27200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:3:mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ; +; |altsyncram_gpv3:auto_generated| ; 0 (0) ; 0 (0) ; 27200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:3:mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_gpv3:auto_generated ; altsyncram_gpv3 ; work ; +; |mem_ctrl:\mem_ctrl_gen:4:mem_ctrl_inst| ; 43 (5) ; 27 (2) ; 28224 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:4:mem_ctrl_inst ; mem_ctrl ; work ; +; |FWFT_FIFO:burst_fifo_inst| ; 38 (0) ; 25 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:4:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 38 (0) ; 25 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:4:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ; +; |scfifo_4hk1:auto_generated| ; 38 (0) ; 25 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:4:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated ; scfifo_4hk1 ; work ; +; |a_dpfifo_adb1:dpfifo| ; 38 (21) ; 25 (11) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:4:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo ; a_dpfifo_adb1 ; work ; +; |altsyncram_c1k1:FIFOram| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:4:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|altsyncram_c1k1:FIFOram ; altsyncram_c1k1 ; work ; +; |cntr_f2b:rd_ptr_msb| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:4:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|cntr_f2b:rd_ptr_msb ; cntr_f2b ; work ; +; |cntr_g2b:wr_ptr| ; 6 (6) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:4:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|cntr_g2b:wr_ptr ; cntr_g2b ; work ; +; |cntr_s27:usedw_counter| ; 6 (6) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:4:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|cntr_s27:usedw_counter ; cntr_s27 ; work ; +; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 27200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:4:mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 27200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:4:mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ; +; |altsyncram_gpv3:auto_generated| ; 0 (0) ; 0 (0) ; 27200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:4:mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_gpv3:auto_generated ; altsyncram_gpv3 ; work ; +; |mem_ctrl:\mem_ctrl_gen:5:mem_ctrl_inst| ; 43 (5) ; 27 (2) ; 28224 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:5:mem_ctrl_inst ; mem_ctrl ; work ; +; |FWFT_FIFO:burst_fifo_inst| ; 38 (0) ; 25 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:5:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 38 (0) ; 25 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:5:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ; +; |scfifo_4hk1:auto_generated| ; 38 (0) ; 25 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:5:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated ; scfifo_4hk1 ; work ; +; |a_dpfifo_adb1:dpfifo| ; 38 (21) ; 25 (11) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:5:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo ; a_dpfifo_adb1 ; work ; +; |altsyncram_c1k1:FIFOram| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:5:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|altsyncram_c1k1:FIFOram ; altsyncram_c1k1 ; work ; +; |cntr_f2b:rd_ptr_msb| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:5:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|cntr_f2b:rd_ptr_msb ; cntr_f2b ; work ; +; |cntr_g2b:wr_ptr| ; 6 (6) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:5:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|cntr_g2b:wr_ptr ; cntr_g2b ; work ; +; |cntr_s27:usedw_counter| ; 6 (6) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:5:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|cntr_s27:usedw_counter ; cntr_s27 ; work ; +; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 27200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:5:mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 27200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:5:mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ; +; |altsyncram_gpv3:auto_generated| ; 0 (0) ; 0 (0) ; 27200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:5:mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_gpv3:auto_generated ; altsyncram_gpv3 ; work ; +; |vector_FIFO:\fifo_in_re_r_if:fifo_in_re_inst| ; 31 (2) ; 18 (0) ; 72 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_in_re_r_if:fifo_in_re_inst ; vector_FIFO ; work ; +; |FWFT_FIFO:fifo_main_inst| ; 15 (0) ; 9 (0) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_in_re_r_if:fifo_in_re_inst|FWFT_FIFO:fifo_main_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 15 (0) ; 9 (0) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_in_re_r_if:fifo_in_re_inst|FWFT_FIFO:fifo_main_inst|scfifo:scfifo_component ; scfifo ; work ; +; |scfifo_bfk1:auto_generated| ; 15 (0) ; 9 (0) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_in_re_r_if:fifo_in_re_inst|FWFT_FIFO:fifo_main_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated ; scfifo_bfk1 ; work ; +; |a_dpfifo_hbb1:dpfifo| ; 15 (11) ; 9 (7) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_in_re_r_if:fifo_in_re_inst|FWFT_FIFO:fifo_main_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated|a_dpfifo_hbb1:dpfifo ; a_dpfifo_hbb1 ; work ; +; |altsyncram_0uj1:FIFOram| ; 0 (0) ; 0 (0) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_in_re_r_if:fifo_in_re_inst|FWFT_FIFO:fifo_main_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated|a_dpfifo_hbb1:dpfifo|altsyncram_0uj1:FIFOram ; altsyncram_0uj1 ; work ; +; |cntr_c2b:wr_ptr| ; 2 (2) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_in_re_r_if:fifo_in_re_inst|FWFT_FIFO:fifo_main_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated|a_dpfifo_hbb1:dpfifo|cntr_c2b:wr_ptr ; cntr_c2b ; work ; +; |cntr_o27:usedw_counter| ; 2 (2) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_in_re_r_if:fifo_in_re_inst|FWFT_FIFO:fifo_main_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated|a_dpfifo_hbb1:dpfifo|cntr_o27:usedw_counter ; cntr_o27 ; work ; +; |FWFT_FIFO:fifo_sup_inst| ; 14 (0) ; 9 (0) ; 6 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_in_re_r_if:fifo_in_re_inst|FWFT_FIFO:fifo_sup_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 14 (0) ; 9 (0) ; 6 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_in_re_r_if:fifo_in_re_inst|FWFT_FIFO:fifo_sup_inst|scfifo:scfifo_component ; scfifo ; work ; +; |scfifo_odk1:auto_generated| ; 14 (0) ; 9 (0) ; 6 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_in_re_r_if:fifo_in_re_inst|FWFT_FIFO:fifo_sup_inst|scfifo:scfifo_component|scfifo_odk1:auto_generated ; scfifo_odk1 ; work ; +; |a_dpfifo_u9b1:dpfifo| ; 14 (10) ; 9 (7) ; 6 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_in_re_r_if:fifo_in_re_inst|FWFT_FIFO:fifo_sup_inst|scfifo:scfifo_component|scfifo_odk1:auto_generated|a_dpfifo_u9b1:dpfifo ; a_dpfifo_u9b1 ; work ; +; |altsyncram_qqj1:FIFOram| ; 0 (0) ; 0 (0) ; 6 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_in_re_r_if:fifo_in_re_inst|FWFT_FIFO:fifo_sup_inst|scfifo:scfifo_component|scfifo_odk1:auto_generated|a_dpfifo_u9b1:dpfifo|altsyncram_qqj1:FIFOram ; altsyncram_qqj1 ; work ; +; |cntr_c2b:wr_ptr| ; 2 (2) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_in_re_r_if:fifo_in_re_inst|FWFT_FIFO:fifo_sup_inst|scfifo:scfifo_component|scfifo_odk1:auto_generated|a_dpfifo_u9b1:dpfifo|cntr_c2b:wr_ptr ; cntr_c2b ; work ; +; |cntr_o27:usedw_counter| ; 2 (2) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_in_re_r_if:fifo_in_re_inst|FWFT_FIFO:fifo_sup_inst|scfifo:scfifo_component|scfifo_odk1:auto_generated|a_dpfifo_u9b1:dpfifo|cntr_o27:usedw_counter ; cntr_o27 ; work ; +; |vector_FIFO:\fifo_in_re_w_if:fifo_in_re_inst| ; 37 (7) ; 18 (0) ; 78 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_in_re_w_if:fifo_in_re_inst ; vector_FIFO ; work ; +; |FWFT_FIFO:fifo_main_inst| ; 15 (0) ; 9 (0) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_in_re_w_if:fifo_in_re_inst|FWFT_FIFO:fifo_main_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 15 (0) ; 9 (0) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_in_re_w_if:fifo_in_re_inst|FWFT_FIFO:fifo_main_inst|scfifo:scfifo_component ; scfifo ; work ; +; |scfifo_bfk1:auto_generated| ; 15 (0) ; 9 (0) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_in_re_w_if:fifo_in_re_inst|FWFT_FIFO:fifo_main_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated ; scfifo_bfk1 ; work ; +; |a_dpfifo_hbb1:dpfifo| ; 15 (11) ; 9 (7) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_in_re_w_if:fifo_in_re_inst|FWFT_FIFO:fifo_main_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated|a_dpfifo_hbb1:dpfifo ; a_dpfifo_hbb1 ; work ; +; |altsyncram_0uj1:FIFOram| ; 0 (0) ; 0 (0) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_in_re_w_if:fifo_in_re_inst|FWFT_FIFO:fifo_main_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated|a_dpfifo_hbb1:dpfifo|altsyncram_0uj1:FIFOram ; altsyncram_0uj1 ; work ; +; |cntr_c2b:wr_ptr| ; 2 (2) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_in_re_w_if:fifo_in_re_inst|FWFT_FIFO:fifo_main_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated|a_dpfifo_hbb1:dpfifo|cntr_c2b:wr_ptr ; cntr_c2b ; work ; +; |cntr_o27:usedw_counter| ; 2 (2) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_in_re_w_if:fifo_in_re_inst|FWFT_FIFO:fifo_main_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated|a_dpfifo_hbb1:dpfifo|cntr_o27:usedw_counter ; cntr_o27 ; work ; +; |FWFT_FIFO:fifo_sup_inst| ; 15 (0) ; 9 (0) ; 12 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_in_re_w_if:fifo_in_re_inst|FWFT_FIFO:fifo_sup_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 15 (0) ; 9 (0) ; 12 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_in_re_w_if:fifo_in_re_inst|FWFT_FIFO:fifo_sup_inst|scfifo:scfifo_component ; scfifo ; work ; +; |scfifo_rdk1:auto_generated| ; 15 (0) ; 9 (0) ; 12 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_in_re_w_if:fifo_in_re_inst|FWFT_FIFO:fifo_sup_inst|scfifo:scfifo_component|scfifo_rdk1:auto_generated ; scfifo_rdk1 ; work ; +; |a_dpfifo_1ab1:dpfifo| ; 15 (11) ; 9 (7) ; 12 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_in_re_w_if:fifo_in_re_inst|FWFT_FIFO:fifo_sup_inst|scfifo:scfifo_component|scfifo_rdk1:auto_generated|a_dpfifo_1ab1:dpfifo ; a_dpfifo_1ab1 ; work ; +; |altsyncram_0rj1:FIFOram| ; 0 (0) ; 0 (0) ; 12 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_in_re_w_if:fifo_in_re_inst|FWFT_FIFO:fifo_sup_inst|scfifo:scfifo_component|scfifo_rdk1:auto_generated|a_dpfifo_1ab1:dpfifo|altsyncram_0rj1:FIFOram ; altsyncram_0rj1 ; work ; +; |cntr_c2b:wr_ptr| ; 2 (2) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_in_re_w_if:fifo_in_re_inst|FWFT_FIFO:fifo_sup_inst|scfifo:scfifo_component|scfifo_rdk1:auto_generated|a_dpfifo_1ab1:dpfifo|cntr_c2b:wr_ptr ; cntr_c2b ; work ; +; |cntr_o27:usedw_counter| ; 2 (2) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_in_re_w_if:fifo_in_re_inst|FWFT_FIFO:fifo_sup_inst|scfifo:scfifo_component|scfifo_rdk1:auto_generated|a_dpfifo_1ab1:dpfifo|cntr_o27:usedw_counter ; cntr_o27 ; work ; +; |vector_FIFO:\fifo_rb_re_r_if:fifo_rb_re_inst| ; 29 (0) ; 18 (0) ; 72 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_rb_re_r_if:fifo_rb_re_inst ; vector_FIFO ; work ; +; |FWFT_FIFO:fifo_main_inst| ; 15 (0) ; 9 (0) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_rb_re_r_if:fifo_rb_re_inst|FWFT_FIFO:fifo_main_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 15 (0) ; 9 (0) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_rb_re_r_if:fifo_rb_re_inst|FWFT_FIFO:fifo_main_inst|scfifo:scfifo_component ; scfifo ; work ; +; |scfifo_bfk1:auto_generated| ; 15 (0) ; 9 (0) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_rb_re_r_if:fifo_rb_re_inst|FWFT_FIFO:fifo_main_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated ; scfifo_bfk1 ; work ; +; |a_dpfifo_hbb1:dpfifo| ; 15 (11) ; 9 (7) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_rb_re_r_if:fifo_rb_re_inst|FWFT_FIFO:fifo_main_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated|a_dpfifo_hbb1:dpfifo ; a_dpfifo_hbb1 ; work ; +; |altsyncram_0uj1:FIFOram| ; 0 (0) ; 0 (0) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_rb_re_r_if:fifo_rb_re_inst|FWFT_FIFO:fifo_main_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated|a_dpfifo_hbb1:dpfifo|altsyncram_0uj1:FIFOram ; altsyncram_0uj1 ; work ; +; |cntr_c2b:wr_ptr| ; 2 (2) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_rb_re_r_if:fifo_rb_re_inst|FWFT_FIFO:fifo_main_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated|a_dpfifo_hbb1:dpfifo|cntr_c2b:wr_ptr ; cntr_c2b ; work ; +; |cntr_o27:usedw_counter| ; 2 (2) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_rb_re_r_if:fifo_rb_re_inst|FWFT_FIFO:fifo_main_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated|a_dpfifo_hbb1:dpfifo|cntr_o27:usedw_counter ; cntr_o27 ; work ; +; |FWFT_FIFO:fifo_sup_inst| ; 14 (0) ; 9 (0) ; 6 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_rb_re_r_if:fifo_rb_re_inst|FWFT_FIFO:fifo_sup_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 14 (0) ; 9 (0) ; 6 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_rb_re_r_if:fifo_rb_re_inst|FWFT_FIFO:fifo_sup_inst|scfifo:scfifo_component ; scfifo ; work ; +; |scfifo_odk1:auto_generated| ; 14 (0) ; 9 (0) ; 6 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_rb_re_r_if:fifo_rb_re_inst|FWFT_FIFO:fifo_sup_inst|scfifo:scfifo_component|scfifo_odk1:auto_generated ; scfifo_odk1 ; work ; +; |a_dpfifo_u9b1:dpfifo| ; 14 (10) ; 9 (7) ; 6 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_rb_re_r_if:fifo_rb_re_inst|FWFT_FIFO:fifo_sup_inst|scfifo:scfifo_component|scfifo_odk1:auto_generated|a_dpfifo_u9b1:dpfifo ; a_dpfifo_u9b1 ; work ; +; |altsyncram_qqj1:FIFOram| ; 0 (0) ; 0 (0) ; 6 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_rb_re_r_if:fifo_rb_re_inst|FWFT_FIFO:fifo_sup_inst|scfifo:scfifo_component|scfifo_odk1:auto_generated|a_dpfifo_u9b1:dpfifo|altsyncram_qqj1:FIFOram ; altsyncram_qqj1 ; work ; +; |cntr_c2b:wr_ptr| ; 2 (2) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_rb_re_r_if:fifo_rb_re_inst|FWFT_FIFO:fifo_sup_inst|scfifo:scfifo_component|scfifo_odk1:auto_generated|a_dpfifo_u9b1:dpfifo|cntr_c2b:wr_ptr ; cntr_c2b ; work ; +; |cntr_o27:usedw_counter| ; 2 (2) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_rb_re_r_if:fifo_rb_re_inst|FWFT_FIFO:fifo_sup_inst|scfifo:scfifo_component|scfifo_odk1:auto_generated|a_dpfifo_u9b1:dpfifo|cntr_o27:usedw_counter ; cntr_o27 ; work ; +; |vector_FIFO:\fifo_rb_re_w_if:fifo_rb_re_inst| ; 35 (7) ; 18 (0) ; 78 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_rb_re_w_if:fifo_rb_re_inst ; vector_FIFO ; work ; +; |FWFT_FIFO:fifo_main_inst| ; 14 (0) ; 9 (0) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_rb_re_w_if:fifo_rb_re_inst|FWFT_FIFO:fifo_main_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 14 (0) ; 9 (0) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_rb_re_w_if:fifo_rb_re_inst|FWFT_FIFO:fifo_main_inst|scfifo:scfifo_component ; scfifo ; work ; +; |scfifo_bfk1:auto_generated| ; 14 (0) ; 9 (0) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_rb_re_w_if:fifo_rb_re_inst|FWFT_FIFO:fifo_main_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated ; scfifo_bfk1 ; work ; +; |a_dpfifo_hbb1:dpfifo| ; 14 (10) ; 9 (7) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_rb_re_w_if:fifo_rb_re_inst|FWFT_FIFO:fifo_main_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated|a_dpfifo_hbb1:dpfifo ; a_dpfifo_hbb1 ; work ; +; |altsyncram_0uj1:FIFOram| ; 0 (0) ; 0 (0) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_rb_re_w_if:fifo_rb_re_inst|FWFT_FIFO:fifo_main_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated|a_dpfifo_hbb1:dpfifo|altsyncram_0uj1:FIFOram ; altsyncram_0uj1 ; work ; +; |cntr_c2b:wr_ptr| ; 2 (2) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_rb_re_w_if:fifo_rb_re_inst|FWFT_FIFO:fifo_main_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated|a_dpfifo_hbb1:dpfifo|cntr_c2b:wr_ptr ; cntr_c2b ; work ; +; |cntr_o27:usedw_counter| ; 2 (2) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_rb_re_w_if:fifo_rb_re_inst|FWFT_FIFO:fifo_main_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated|a_dpfifo_hbb1:dpfifo|cntr_o27:usedw_counter ; cntr_o27 ; work ; +; |FWFT_FIFO:fifo_sup_inst| ; 14 (0) ; 9 (0) ; 12 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_rb_re_w_if:fifo_rb_re_inst|FWFT_FIFO:fifo_sup_inst ; FWFT_FIFO ; work ; +; |scfifo:scfifo_component| ; 14 (0) ; 9 (0) ; 12 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_rb_re_w_if:fifo_rb_re_inst|FWFT_FIFO:fifo_sup_inst|scfifo:scfifo_component ; scfifo ; work ; +; |scfifo_rdk1:auto_generated| ; 14 (0) ; 9 (0) ; 12 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_rb_re_w_if:fifo_rb_re_inst|FWFT_FIFO:fifo_sup_inst|scfifo:scfifo_component|scfifo_rdk1:auto_generated ; scfifo_rdk1 ; work ; +; |a_dpfifo_1ab1:dpfifo| ; 14 (10) ; 9 (7) ; 12 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_rb_re_w_if:fifo_rb_re_inst|FWFT_FIFO:fifo_sup_inst|scfifo:scfifo_component|scfifo_rdk1:auto_generated|a_dpfifo_1ab1:dpfifo ; a_dpfifo_1ab1 ; work ; +; |altsyncram_0rj1:FIFOram| ; 0 (0) ; 0 (0) ; 12 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_rb_re_w_if:fifo_rb_re_inst|FWFT_FIFO:fifo_sup_inst|scfifo:scfifo_component|scfifo_rdk1:auto_generated|a_dpfifo_1ab1:dpfifo|altsyncram_0rj1:FIFOram ; altsyncram_0rj1 ; work ; +; |cntr_c2b:wr_ptr| ; 2 (2) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_rb_re_w_if:fifo_rb_re_inst|FWFT_FIFO:fifo_sup_inst|scfifo:scfifo_component|scfifo_rdk1:auto_generated|a_dpfifo_1ab1:dpfifo|cntr_c2b:wr_ptr ; cntr_c2b ; work ; +; |cntr_o27:usedw_counter| ; 2 (2) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_rb_re_w_if:fifo_rb_re_inst|FWFT_FIFO:fifo_sup_inst|scfifo:scfifo_component|scfifo_rdk1:auto_generated|a_dpfifo_1ab1:dpfifo|cntr_o27:usedw_counter ; cntr_o27 ; work ; ++------------------------------------------------------------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++---------------------------------------------------------+ +; Analysis & Synthesis Resource Usage Summary ; ++---------------------------------------------+-----------+ +; Resource ; Usage ; ++---------------------------------------------+-----------+ +; Estimate of Logic utilization (ALMs needed) ; 27435 ; +; ; ; +; Combinational ALUT usage for logic ; 41730 ; +; -- 7 input functions ; 734 ; +; -- 6 input functions ; 8427 ; +; -- 5 input functions ; 9988 ; +; -- 4 input functions ; 9332 ; +; -- <=3 input functions ; 13249 ; +; ; ; +; Dedicated logic registers ; 20866 ; +; ; ; +; I/O pins ; 71 ; +; Total MLAB memory bits ; 0 ; +; Total block memory bits ; 2377339 ; +; ; ; +; Total DSP Blocks ; 4 ; +; ; ; +; Maximum fan-out node ; clk~input ; +; Maximum fan-out ; 24203 ; +; Total fan-out ; 297731 ; +; Average fan-out ; 4.51 ; ++---------------------------------------------+-----------+ diff --git a/src/dds_reader.vhd b/src/dds_reader.vhd index ef336f5..722d705 100644 --- a/src/dds_reader.vhd +++ b/src/dds_reader.vhd @@ -319,9 +319,9 @@ architecture arch of dds_reader is -- FSM states. Explained below in detail type STAGE_TYPE is (IDLE, RETURN_DDS, RETURN_RTPS, ADD_SAMPLE_INFO, ADD_PAYLOAD, NEXT_PAYLOAD_SLOT, ALIGN_PAYLOAD, GET_KEY_HASH, INITIATE_INSTANCE_SEARCH, FILTER_STAGE, UPDATE_INSTANCE, FINALIZE_PAYLOAD, PRE_SAMPLE_FINALIZE, FIND_POS, FIX_POINTERS, FINALIZE_SAMPLE, GENERATE_SAMPLE, GET_OLDEST_SAMPLE_INSTANCE, - FIND_OLDEST_INST_SAMPLE, REMOVE_SAMPLE, POST_SAMPLE_REMOVE, SKIP_AND_RETURN, REMOVE_WRITER, REMOVE_STALE_INSTANCE, GET_NEXT_SAMPLE, PRE_CALCULATE, FINALIZE_SAMPLE_INFO, - GET_PAYLOAD, FIND_NEXT_INSTANCE, CHECK_INSTANCE, CHECK_LIFESPAN, PROCESS_PENDING_SAMPLE_GENERATION, GET_SAMPLE_REJECTED_STATUS, GET_REQUESTED_DEADLINE_MISSED_STATUS, - CHECK_DEADLINE, RESET_SAMPLE_MEMORY, RESET_PAYLOAD_MEMORY); + FIND_OLDEST_INST_SAMPLE, REMOVE_SAMPLE, POST_SAMPLE_REMOVE, SKIP_AND_RETURN, REMOVE_WRITER, REMOVE_STALE_INSTANCE, WAIT_READ, GET_PAYLOAD, CHECK_LIFESPAN, + PROCESS_PENDING_SAMPLE_GENERATION, GET_SAMPLE_REJECTED_STATUS, GET_REQUESTED_DEADLINE_MISSED_STATUS, CHECK_DEADLINE, RESET_SAMPLE_MEMORY, RESET_PAYLOAD_MEMORY); + type READ_STAGE_TYPE is (IDLE, GET_NEXT_SAMPLE, PRE_CALCULATE, FINALIZE_SAMPLE_INFO, FIND_NEXT_INSTANCE, CHECK_INSTANCE, WAIT_PAYLOAD, WAIT_REMOVE, DONE); -- Instance Memory FSM states. Explained below in detail type INST_STAGE_TYPE is (IDLE, SEARCH_INSTANCE, GET_NEXT_INSTANCE, GET_INSTANCE_DATA, FIND_POS, INSERT_INSTANCE, UPDATE_INSTANCE, REMOVE_INSTANCE, UNMARK_INSTANCES, RESET_MEMORY); @@ -373,12 +373,12 @@ architecture arch of dds_reader is --*****SIGNAL DECLARATION***** -- *SAMPLE MEMORY CONNECTION SIGNALS* - signal sample_addr : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0); - signal sample_read : std_logic; - signal sample_read_data, sample_write_data : std_logic_vector(WORD_WIDTH-1 downto 0); - signal sample_ready_in, sample_valid_in : std_logic; - signal sample_ready_out, sample_valid_out : std_logic; - signal sample_abort_read : std_logic; + signal sample_addr1, sample_addr2 : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0); + signal sample_read1, sample_read2 : std_logic; + signal sample_read_data, sample_write_data1, sample_write_data2 : std_logic_vector(WORD_WIDTH-1 downto 0); + signal sample_ready_in, sample_valid_in1, sample_valid_in2 : std_logic; + signal sample_ready_out1, sample_ready_out2, sample_valid_out : std_logic; + signal sample_abort_read1, sample_abort_read2 : std_logic; signal sample_addr_i : SAMPLE_MEMORY_ADDR_ARRAY_TYPE; signal sample_read_i : std_logic_vector(0 to NUM_READERS-1); signal sample_read_data_i, sample_write_data_i : WORD_ARRAY_TYPE(0 to NUM_READERS-1); @@ -423,11 +423,11 @@ architecture arch of dds_reader is -- FSM state signal stage, stage_next : STAGE_TYPE; -- General Purpose Counter - signal cnt, cnt_next : natural range 0 to 18; + signal cnt, cnt_next : natural range 0 to 13; -- Counter used to read/write Payload Fames - signal cnt2, cnt2_next : natural range 0 to get_max_payload_memory_size(PAYLOAD_FRAME_SIZE); + signal payload_cnt, payload_cnt_next : natural range 0 to get_max_payload_memory_size(PAYLOAD_FRAME_SIZE); -- Counter used to read/write Payload Fames - signal cnt3, cnt3_next : natural range 0 to get_max_payload_memory_size(PAYLOAD_FRAME_SIZE); + signal payload_cnt2, payload_cnt2_next : natural range 0 to get_max_payload_memory_size(PAYLOAD_FRAME_SIZE); -- Head of Empty Sample List signal empty_sample_list_head, empty_sample_list_head_next : SAMPLE_MEMORY_ADDR_ARRAY_TYPE; -- Tail of Empty Sample List @@ -438,8 +438,6 @@ architecture arch of dds_reader is signal oldest_sample, oldest_sample_next : SAMPLE_MEMORY_ADDR_ARRAY_TYPE; -- Newest Sample (Tail of Occupied Sample List) signal newest_sample, newest_sample_next : SAMPLE_MEMORY_ADDR_ARRAY_TYPE; - -- Highest Timestamp of all READ Samples - signal last_read_ts, last_read_ts_next : TIME_ARRAY_TYPE(0 to NUM_READERS-1); -- Denotes if the oldest Sample should be removed signal remove_oldest_sample, remove_oldest_sample_next : std_logic; -- Denotes if the oldest sample of the Instance with 'key_hash' should be removed @@ -468,10 +466,6 @@ architecture arch of dds_reader is signal sample_addr_latch_2, sample_addr_latch_2_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0); -- General Purpose Sample Pointer signal sample_addr_latch_3, sample_addr_latch_3_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0); - -- General Purpose Sample Pointer - signal sample_addr_latch_4, sample_addr_latch_4_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0); - -- General Purpose Sample Pointer - signal sample_addr_latch_5, sample_addr_latch_5_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0); -- General Purpose Instance Pointer signal inst_addr_latch_1, inst_addr_latch_1_next : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0); -- General Purpose Instance Pointer @@ -479,17 +473,67 @@ architecture arch of dds_reader is -- General Purpose Long Latch signal long_latch, long_latch_next : std_logic_vector(CDR_LONG_WIDTH-1 downto 0); -- Signals start of Instance Memory Operation - signal inst_op_start : std_logic; - -- Opcode of Instance Memory Operation (Valid only when inst_op_start is high) - signal inst_opcode : INSTANCE_OPCODE_TYPE; - -- Signals the end of an Instance Memory Operation - signal inst_op_done : std_logic; + signal inst_op_start1 : std_logic; + -- Opcode of Instance Memory Operation (Valid only when inst_op_start1 is high) + signal inst_opcode1 : INSTANCE_OPCODE_TYPE; -- Signal used to pass data to instance memory process - signal inst_r : INSTANCE_DATA_TYPE; + signal inst_r1 : INSTANCE_DATA_TYPE; -- Time of next Sample Lifespan Check signal lifespan_time, lifespan_time_next : TIME_TYPE; -- Signifies if a Lifespan Check is in progress signal is_lifespan_check, is_lifespan_check_next : std_logic; + -- Denotes if the marks on Instances should be reset + signal unmark_instances_flag, unmark_instances_flag_next : std_logic; + -- Signal containing the number of currently stale Instances + signal stale_inst_cnt, stale_inst_cnt_next : MAX_INSTANCES_NATURAL_ARRAY_TYPE; + -- Disposed Generation Count Latch + signal dis_gen_cnt_latch, dis_gen_cnt_latch_next : unsigned(WORD_WIDTH-1 downto 0); + -- No Writers Generation Count Latch + signal no_w_gen_cnt_latch, no_w_gen_cnt_latch_next : unsigned(WORD_WIDTH-1 downto 0); + -- Denotes if a newer sample of the same Instance exists + signal newer_inst_sample, newer_inst_sample_next : std_logic; + -- Denotes if a new Instance is added + signal new_inst, new_inst_next : std_logic; + -- Triggers Sample Generation + signal trigger_sample_gen, trigger_sample_gen_next : std_logic; + -- Waits for Sample Removal (MAX_SAMPLES Limit lift) to trigger Sample Generation + signal wait_for_sample_removal, wait_for_sample_removal_next : std_logic; + -- Signal used to index the readers + signal ind, ind_next : natural range 0 to NUM_READERS-1; + -- Communication Signals between READ and MAIN FSM + signal start_read : std_logic; + signal get_payload_done : std_logic; + -- Test signals used in testbenches + signal idle_sig : std_logic; + signal empty_inst_head_sig : NATURAL_ARRAY_TYPE; + signal empty_sample_head_sig : NATURAL_ARRAY_TYPE; + signal empty_payload_head_sig : NATURAL_ARRAY_TYPE; + + -- *READ PROCESS* + -- FSM state + signal read_stage, read_stage_next : READ_STAGE_TYPE; + -- General Purpose Counter + signal cnt2, cnt2_next : natural range 0 to 18; + -- Signals start of Instance Memory Operation + signal inst_op_start2 : std_logic; + -- Opcode of Instance Memory Operation (Valid only when inst_op_start1 is high) + signal inst_opcode2 : INSTANCE_OPCODE_TYPE; + -- Signal used to pass data to instance memory process + signal inst_r2 : INSTANCE_DATA_TYPE; + -- General Purpose Sample Pointer + signal sample_addr_latch_4, sample_addr_latch_4_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0); + -- General Purpose Sample Pointer + signal sample_addr_latch_5, sample_addr_latch_5_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0); + -- General Purpose Sample Pointer + signal sample_addr_latch_6, sample_addr_latch_6_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0); + -- General Purpose Sample Pointer + signal sample_addr_latch_7, sample_addr_latch_7_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0); + -- General Purpose Sample Pointer + signal sample_addr_latch_8, sample_addr_latch_8_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0); + -- General Purpose Instance Pointer + signal inst_addr_latch_3, inst_addr_latch_3_next : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0); + -- General Purpose Instance Pointer + signal inst_addr_latch_4, inst_addr_latch_4_next : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0); -- Sample State Latch signal sample_state, sample_state_next : std_logic_vector(SAMPLE_STATE_KIND_WIDTH-1 downto 0); -- View State Latch @@ -513,33 +557,27 @@ architecture arch of dds_reader is -- NOTE: We use this signal to prevent the costly Instance Marking in the case that we only need to ouptput samples of one Instance. -- Denotes if the READ/TAKE operation applies to a single Instance signal single_instance, single_instance_next : std_logic; - -- Denotes if the marks on Instances should be reset - signal unmark_instances_flag, unmark_instances_flag_next : std_logic; -- Denotes if the READ/TAKE operation does not apply to a specific Instance signal dynamic_next_instance, dynamic_next_instance_next : std_logic; - -- Signal containing the number of currently stale Instances - signal stale_inst_cnt, stale_inst_cnt_next : MAX_INSTANCES_NATURAL_ARRAY_TYPE; + -- DDS Return Code Latch + signal dds_return_code_latch2, dds_return_code_latch2_next : std_logic_vector(RETURN_CODE_WIDTH-1 downto 0); + -- Sample Status Info Latch + signal sample_status_info2, sample_status_info2_next : std_logic_vector(CDR_LONG_WIDTH-1 downto 0); + -- Highest Timestamp of all READ Samples + signal last_read_ts, last_read_ts_next : TIME_ARRAY_TYPE(0 to NUM_READERS-1); -- Signal denoting if the PRE_CALCULATE stage was run for the current instance signal pre_calculated, pre_calculated_next : std_logic; - -- Disposed Generation Count Latch - signal dis_gen_cnt_latch, dis_gen_cnt_latch_next : unsigned(WORD_WIDTH-1 downto 0); - -- No Writers Generation Count Latch - signal no_w_gen_cnt_latch, no_w_gen_cnt_latch_next : unsigned(WORD_WIDTH-1 downto 0); - -- Denotes if a newer sample of the same Instance exists - signal newer_inst_sample, newer_inst_sample_next : std_logic; - -- Denotes if a new Instance is added - signal new_inst, new_inst_next : std_logic; - -- Triggers Sample Generation - signal trigger_sample_gen, trigger_sample_gen_next : std_logic; - -- Waits for Sample Removal (MAX_SAMPLES Limit lift) to trigger Sample Generation - signal wait_for_sample_removal, wait_for_sample_removal_next : std_logic; - -- Signal used to index the readers - signal ind, ind_next : natural range 0 to NUM_READERS-1; - -- Test signals used in testbenches - signal idle_sig : std_logic; - signal empty_inst_head_sig : NATURAL_ARRAY_TYPE; - signal empty_sample_head_sig : NATURAL_ARRAY_TYPE; - signal empty_payload_head_sig : NATURAL_ARRAY_TYPE; + -- General Purpose Payload Pointer + signal payload_addr_latch_3, payload_addr_latch_3_next : unsigned(PAYLOAD_MEMORY_ADDR_WIDTH-1 downto 0); + -- Signals the main process to reset the Instances Marks + signal unmark_instances_trigger : std_logic; + -- Communication Signals between READ and MAIN FSM + signal ack_read : std_logic; + signal done_read_error : std_logic; + signal done_read_success : std_logic; + signal get_payload_trigger : std_logic; + signal remove_sample_trigger : std_logic; + -- *COMMUNICATION STATUS* signal status_sig, status_sig_next : STATUS_KIND_ARRAY_TYPE(0 to NUM_READERS-1); @@ -576,6 +614,14 @@ architecture arch of dds_reader is -- *INSTANCE MEMORY PROCESS* -- Instance Memory FSM state signal inst_stage, inst_stage_next : INST_STAGE_TYPE; + -- Signals start of Instance Memory Operation + signal inst_op_start : std_logic; + -- Opcode of Instance Memory Operation (Valid only when inst_op_start1 is high) + signal inst_opcode : INSTANCE_OPCODE_TYPE; + -- Signal used to pass data to instance memory process + signal inst_r : INSTANCE_DATA_TYPE; + -- Signals the end of an Instance Memory Operation + signal inst_op_done : std_logic; -- Pointer to current relevant Instance Memory Frame Address signal inst_addr_base, inst_addr_base_next : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0); -- General Purpose Instance Memory Address Latch @@ -596,30 +642,16 @@ architecture arch of dds_reader is signal inst_long_latch, inst_long_latch_next : std_logic_vector(CDR_LONG_WIDTH-1 downto 0); --*****ALIAS DECLARATION***** - alias prev_sample : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) is sample_addr_latch_1; - alias prev_sample_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) is sample_addr_latch_1_next; - alias sel_sample : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) is sample_addr_latch_1; - alias sel_sample_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) is sample_addr_latch_1_next; - alias next_sample : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) is sample_addr_latch_2; - alias next_sample_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) is sample_addr_latch_2_next; - alias cur_sample : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) is sample_addr_latch_3; - alias cur_sample_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) is sample_addr_latch_3_next; - alias sample_p1 : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) is sample_addr_latch_4; - alias sample_p1_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) is sample_addr_latch_4_next; - alias sample_p2 : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) is sample_addr_latch_5; - alias sample_p2_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) is sample_addr_latch_5_next; + alias has_data : std_logic is sample_status_info(SSI_DATA_FLAG); + alias has_key_hash : std_logic is sample_status_info(SSI_KEY_HASH_FLAG); alias cur_payload : unsigned(PAYLOAD_MEMORY_ADDR_WIDTH-1 downto 0) is payload_addr_latch_1; alias cur_payload_next : unsigned(PAYLOAD_MEMORY_ADDR_WIDTH-1 downto 0) is payload_addr_latch_1_next; alias next_payload : unsigned(PAYLOAD_MEMORY_ADDR_WIDTH-1 downto 0) is payload_addr_latch_2; - alias next_payload_next : unsigned(PAYLOAD_MEMORY_ADDR_WIDTH-1 downto 0) is payload_addr_latch_2_next; - alias cur_inst : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0) is inst_addr_latch_1; - alias cur_inst_next : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0) is inst_addr_latch_1_next; - alias next_inst : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0) is inst_addr_latch_2; - alias next_inst_next : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0) is inst_addr_latch_2_next; + alias next_payload_next : unsigned(PAYLOAD_MEMORY_ADDR_WIDTH-1 downto 0) is payload_addr_latch_2_next; alias first_payload : unsigned(PAYLOAD_MEMORY_ADDR_WIDTH-1 downto 0) is payload_addr_latch_2; alias first_payload_next : unsigned(PAYLOAD_MEMORY_ADDR_WIDTH-1 downto 0) is payload_addr_latch_2_next; - alias has_data : std_logic is sample_status_info(SSI_DATA_FLAG); - alias has_key_hash : std_logic is sample_status_info(SSI_KEY_HASH_FLAG); + alias sel_payload : unsigned(PAYLOAD_MEMORY_ADDR_WIDTH-1 downto 0) is payload_addr_latch_3; + alias sel_payload_next : unsigned(PAYLOAD_MEMORY_ADDR_WIDTH-1 downto 0) is payload_addr_latch_3_next; -- *FUNCTION DECLARATION* @@ -782,6 +814,20 @@ begin inst_read_data <= inst_read_data_i(inst_latch_data.i); end process; + inst_mux_prc : process (all) + begin + -- MUX between FSMs + if (stage = WAIT_READ) then + inst_op_start <= inst_op_start2; + inst_opcode <= inst_opcode2; + inst_r <= inst_r2; + else + inst_op_start <= inst_op_start1; + inst_opcode <= inst_opcode1; + inst_r <= inst_r1; + end if; + end process; + sample_memory_mux : process (all) begin sample_abort_read_i <= (others => '0'); @@ -791,12 +837,22 @@ begin sample_write_data_i <= (others => (others => '0')); sample_ready_out_i <= (others => '0'); - sample_abort_read_i(ind) <= sample_abort_read; - sample_addr_i(ind) <= sample_addr; - sample_read_i(ind) <= sample_read; - sample_valid_in_i(ind) <= sample_valid_in; - sample_write_data_i(ind) <= sample_write_data; - sample_ready_out_i(ind) <= sample_ready_out; + -- MUX between FSMs + if (stage = WAIT_READ) then + sample_abort_read_i(ind) <= sample_abort_read2; + sample_addr_i(ind) <= sample_addr2; + sample_read_i(ind) <= sample_read2; + sample_valid_in_i(ind) <= sample_valid_in2; + sample_write_data_i(ind) <= sample_write_data2; + sample_ready_out_i(ind) <= sample_ready_out2; + else + sample_abort_read_i(ind) <= sample_abort_read1; + sample_addr_i(ind) <= sample_addr1; + sample_read_i(ind) <= sample_read1; + sample_valid_in_i(ind) <= sample_valid_in1; + sample_write_data_i(ind) <= sample_write_data1; + sample_ready_out_i(ind) <= sample_ready_out1; + end if; sample_ready_in <= sample_ready_in_i(ind); sample_valid_out <= sample_valid_out_i(ind); @@ -881,11 +937,21 @@ begin -- CHECK_DEADLINE Check and Mark Instances with missed Deadlines -- RESET_SAMPLE_MEMORY Reset Sample Memory to Empty State -- RESET_PAYLOAD_MEMORY Reset Payload Memory to Empty State - parse_a_prc : process (all) + parse_prc : process (all) variable tmp_dw : DOUBLE_WORD_ARRAY; variable tmp_bitmap : std_logic_vector(0 to WRITER_BITMAP_WIDTH-1); variable tmp_update : std_logic_vector(0 to IMF_FLAG_WIDTH-1); variable tmp_bool : boolean; + alias prev_sample : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) is sample_addr_latch_1; + alias prev_sample_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) is sample_addr_latch_1_next; + alias next_sample : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) is sample_addr_latch_2; + alias next_sample_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) is sample_addr_latch_2_next; + alias cur_sample : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) is sample_addr_latch_3; + alias cur_sample_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) is sample_addr_latch_3_next; + alias cur_inst : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0) is inst_addr_latch_1; + alias cur_inst_next : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0) is inst_addr_latch_1_next; + alias next_inst : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0) is inst_addr_latch_2; + alias next_inst_next : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0) is inst_addr_latch_2_next; begin -- DEFAULT Registered stage_next <= stage; @@ -900,43 +966,13 @@ begin sample_addr_latch_1_next <= sample_addr_latch_1; sample_addr_latch_2_next <= sample_addr_latch_2; sample_addr_latch_3_next <= sample_addr_latch_3; - sample_addr_latch_4_next <= sample_addr_latch_4; - sample_addr_latch_5_next <= sample_addr_latch_5; writer_id_next <= writer_id; key_hash_next <= key_hash; sample_status_info_next <= sample_status_info; remove_oldest_sample_next <= remove_oldest_sample; remove_oldest_inst_sample_next <= remove_oldest_inst_sample; - si_sample_state_sig_next <= si_sample_state_sig; - si_view_state_sig_next <= si_view_state_sig; - si_instance_state_sig_next <= si_instance_state_sig; - si_source_timestamp_sig_next <= si_source_timestamp_sig; - si_instance_handle_sig_next <= si_instance_handle_sig; - si_publication_handle_sig_next <= si_publication_handle_sig; - si_disposed_generation_count_sig_next <= si_disposed_generation_count_sig; - si_no_writers_generation_count_sig_next <= si_no_writers_generation_count_sig; - si_sample_rank_sig_next <= si_sample_rank_sig; - si_generation_rank_sig_next <= si_generation_rank_sig; - si_absolute_generation_rank_sig_next <= si_absolute_generation_rank_sig; - si_valid_data_sig_next <= si_valid_data_sig; - si_valid_sig_next <= si_valid_sig; - eoc_sig_next <= eoc_sig; - sample_state_next <= sample_state; - view_state_next <= view_state; - instance_state_next <= instance_state; - instance_handle_next <= instance_handle; - max_samples_latch_next <= max_samples_latch; inst_addr_latch_1_next <= inst_addr_latch_1; inst_addr_latch_2_next <= inst_addr_latch_2; - collection_cnt_next <= collection_cnt; - collection_cnt_max_next <= collection_cnt_max; - collection_generation_rank_next <= collection_generation_rank; - cur_generation_rank_next <= cur_generation_rank; - is_take_next <= is_take; - single_instance_next <= single_instance; - unmark_instances_flag_next <= unmark_instances_flag; - dynamic_next_instance_next <= dynamic_next_instance; - last_read_ts_next <= last_read_ts; sample_rej_cnt_next <= sample_rej_cnt; sample_rej_cnt_change_next <= sample_rej_cnt_change; sample_rej_last_reason_next <= sample_rej_last_reason; @@ -948,16 +984,16 @@ begin deadline_miss_last_inst_next <= deadline_miss_last_inst; lifespan_time_next <= lifespan_time; is_lifespan_check_next <= is_lifespan_check; + unmark_instances_flag_next <= unmark_instances_flag; status_sig_next <= status_sig; cnt_next <= cnt; - cnt2_next <= cnt2; - cnt3_next <= cnt3; + payload_cnt_next <= payload_cnt; + payload_cnt2_next <= payload_cnt2; lifespan_next <= lifespan; stale_inst_cnt_next <= stale_inst_cnt; oldest_sample_next <= oldest_sample; rtps_return_code_latch_next <= rtps_return_code_latch; dds_return_code_latch_next <= dds_return_code_latch; - pre_calculated_next <= pre_calculated; dis_gen_cnt_latch_next <= dis_gen_cnt_latch; no_w_gen_cnt_latch_next <= no_w_gen_cnt_latch; newer_inst_sample_next <= newer_inst_sample; @@ -966,7 +1002,7 @@ begin wait_for_sample_removal_next <= wait_for_sample_removal; ind_next <= ind; -- DEFAULT Unregistered - inst_opcode <= NOP; + inst_opcode1 <= NOP; opcode_kh <= (others => NOP); ret_rtps <= (others => ERROR); return_code_dds <= (others => RETCODE_UNSUPPORTED); @@ -974,15 +1010,17 @@ begin done_dds <= (others => '0'); ack_rtps <= (others => '0'); done_rtps <= (others => '0'); - inst_op_start <= '0'; - sample_read <= '0'; - sample_ready_out <= '0'; - sample_valid_in <= '0'; - sample_abort_read <= '0'; + inst_op_start1 <= '0'; + sample_read1 <= '0'; + sample_ready_out1 <= '0'; + sample_valid_in1 <= '0'; + sample_abort_read1 <= '0'; payload_read <= '0'; payload_ready_out <= '0'; payload_valid_in <= '0'; payload_abort_read <= '0'; + start_read <= '0'; + get_payload_done <= '0'; ready_in_rtps <= (others => '0'); start_kh <= (others => '0'); abort_kh <= (others => '0'); @@ -994,11 +1032,11 @@ begin idle_sig <= '0'; data_out_dds <= (others => (others => '0')); data_out_kh <= (others => (others => '0')); - sample_addr <= (others => '0'); - sample_write_data <= (others => '0'); + sample_addr1 <= (others => '0'); + sample_write_data1 <= (others => '0'); payload_addr <= (others => '0'); payload_write_data <= (others => '0'); - inst_r <= ZERO_INSTANCE_DATA; + inst_r1 <= ZERO_INSTANCE_DATA; @@ -1010,7 +1048,6 @@ begin newer_inst_sample_next <= '0'; remove_oldest_inst_sample_next <= '0'; remove_oldest_sample_next <= '0'; - is_take_next <= '0'; key_hash_next <= KEY_HASH_NIL; @@ -1094,9 +1131,9 @@ begin elsif (unmark_instances_flag = '1') then -- Memory Operation Guard if (inst_op_done = '1') then - inst_op_start <= '1'; - inst_opcode <= UNMARK_INSTANCES; - inst_r.i <= ind; + inst_op_start1 <= '1'; + inst_opcode1 <= UNMARK_INSTANCES; + inst_r1.i <= ind; unmark_instances_flag_next <= '0'; end if; -- DDS Operation @@ -1108,182 +1145,54 @@ begin ind_next <= ind + 1; end if; else - -- Latch Input Signals - sample_state_next <= sample_state_dds(ind); - view_state_next <= view_state_dds(ind); - instance_state_next <= instance_state_dds(ind); - max_samples_latch_next <= unsigned(max_samples_dds(ind)); - - -- Reset - sel_sample_next <= SAMPLE_MEMORY_MAX_ADDRESS; - sample_p1_next <= SAMPLE_MEMORY_MAX_ADDRESS; - sample_p2_next <= SAMPLE_MEMORY_MAX_ADDRESS; - pre_calculated_next <= '0'; - single_instance_next <= '0'; - dynamic_next_instance_next <= '0'; - collection_cnt_next <= (others => '0'); - collection_cnt_max_next <= (others => '0'); - si_sample_state_sig_next <= (others => '0'); - si_view_state_sig_next <= (others => '0'); - si_instance_state_sig_next <= (others => '0'); - si_source_timestamp_sig_next <= TIME_ZERO; - si_instance_handle_sig_next <= HANDLE_NIL; - si_publication_handle_sig_next <= HANDLE_NIL; - si_sample_rank_sig_next <= (others => '0'); - si_generation_rank_sig_next <= (others => '0'); - si_valid_data_sig_next <= '0'; - si_valid_sig_next <= '0'; - eoc_sig_next <= '0'; - si_absolute_generation_rank_sig_next <= (others => '0'); - si_disposed_generation_count_sig_next <= (others => '0'); - si_no_writers_generation_count_sig_next <= (others => '0'); - case (opcode_dds(ind)) is when READ => - ack_dds(ind) <= '1'; - -- No Samples Available - if (oldest_sample(ind) = SAMPLE_MEMORY_MAX_ADDRESS) then - stage_next <= RETURN_DDS; - dds_return_code_latch_next <= RETCODE_NO_DATA; - else - cur_sample_next <= oldest_sample(ind); - cur_inst_next <= INSTANCE_MEMORY_MAX_ADDRESS; - stage_next <= GET_NEXT_SAMPLE; - cnt_next <= 0; - if (unsigned(max_samples_dds(ind)) = 1) then - single_instance_next <= '1'; - end if; + start_read <= '1'; + if (ack_read = '1') then + ack_dds(ind) <= '1'; + stage_next <= WAIT_READ; end if; when TAKE => - ack_dds(ind) <= '1'; - -- No Samples Available - if (oldest_sample(ind) = SAMPLE_MEMORY_MAX_ADDRESS) then - stage_next <= RETURN_DDS; - dds_return_code_latch_next <= RETCODE_NO_DATA; - else - is_take_next <= '1'; - cur_sample_next <= oldest_sample(ind); - cur_inst_next <= INSTANCE_MEMORY_MAX_ADDRESS; - stage_next <= GET_NEXT_SAMPLE; - cnt_next <= 0; - if (unsigned(max_samples_dds(ind)) = 1) then - single_instance_next <= '1'; - end if; + start_read <= '1'; + if (ack_read = '1') then + ack_dds(ind) <= '1'; + stage_next <= WAIT_READ; end if; when READ_NEXT_SAMPLE => - ack_dds(ind) <= '1'; - -- No Samples Available - if (oldest_sample(ind) = SAMPLE_MEMORY_MAX_ADDRESS) then - stage_next <= RETURN_DDS; - dds_return_code_latch_next <= RETCODE_NO_DATA; - else - single_instance_next <= '1'; - cur_sample_next <= oldest_sample(ind); - cur_inst_next <= INSTANCE_MEMORY_MAX_ADDRESS; - sample_state_next <= NOT_READ_SAMPLE_STATE; - view_state_next <= ANY_VIEW_STATE; - instance_state_next <= ANY_INSTANCE_STATE; - max_samples_latch_next <= to_unsigned(1, max_samples_latch'length); - stage_next <= GET_NEXT_SAMPLE; - cnt_next <= 0; + start_read <= '1'; + if (ack_read = '1') then + ack_dds(ind) <= '1'; + stage_next <= WAIT_READ; end if; when TAKE_NEXT_SAMPLE => - ack_dds(ind) <= '1'; - -- No Samples Available - if (oldest_sample(ind) = SAMPLE_MEMORY_MAX_ADDRESS) then - stage_next <= RETURN_DDS; - dds_return_code_latch_next <= RETCODE_NO_DATA; - else - is_take_next <= '1'; - single_instance_next <= '1'; - cur_sample_next <= oldest_sample(ind); - cur_inst_next <= INSTANCE_MEMORY_MAX_ADDRESS; - sample_state_next <= NOT_READ_SAMPLE_STATE; - view_state_next <= ANY_VIEW_STATE; - instance_state_next <= ANY_INSTANCE_STATE; - max_samples_latch_next <= to_unsigned(1, max_samples_latch'length); - stage_next <= GET_NEXT_SAMPLE; - cnt_next <= 0; + start_read <= '1'; + if (ack_read = '1') then + ack_dds(ind) <= '1'; + stage_next <= WAIT_READ; end if; when READ_INSTANCE => - ack_dds(ind) <= '1'; - -- Synthesis Guard - if (CONFIG_ARRAY_T(ind).WITH_KEY) then - -- No Samples Available - if (oldest_sample(ind) = SAMPLE_MEMORY_MAX_ADDRESS) then - stage_next <= RETURN_DDS; - dds_return_code_latch_next <= RETCODE_NO_DATA; - else - single_instance_next <= '1'; - cur_sample_next <= oldest_sample(ind); - key_hash_next <= instance_handle_dds(ind); - stage_next <= CHECK_INSTANCE; - cnt_next <= 0; - end if; - else - stage_next <= RETURN_DDS; - dds_return_code_latch_next <= RETCODE_ILLEGAL_OPERATION; + start_read <= '1'; + if (ack_read = '1') then + ack_dds(ind) <= '1'; + stage_next <= WAIT_READ; end if; when TAKE_INSTANCE => - ack_dds(ind) <= '1'; - -- Synthesis Guard - if (CONFIG_ARRAY_T(ind).WITH_KEY) then - -- No Samples Available - if (oldest_sample(ind) = SAMPLE_MEMORY_MAX_ADDRESS) then - stage_next <= RETURN_DDS; - dds_return_code_latch_next <= RETCODE_NO_DATA; - else - is_take_next <= '1'; - single_instance_next <= '1'; - cur_sample_next <= oldest_sample(ind); - key_hash_next <= instance_handle_dds(ind); - stage_next <= CHECK_INSTANCE; - cnt_next <= 0; - end if; - else - stage_next <= RETURN_DDS; - dds_return_code_latch_next <= RETCODE_ILLEGAL_OPERATION; + start_read <= '1'; + if (ack_read = '1') then + ack_dds(ind) <= '1'; + stage_next <= WAIT_READ; end if; when READ_NEXT_INSTANCE => - ack_dds(ind) <= '1'; - -- Synthesis Guard - if (CONFIG_ARRAY_T(ind).WITH_KEY) then - -- No Samples Available - if (oldest_sample(ind) = SAMPLE_MEMORY_MAX_ADDRESS) then - stage_next <= RETURN_DDS; - dds_return_code_latch_next <= RETCODE_NO_DATA; - else - single_instance_next <= '1'; - dynamic_next_instance_next <= '1'; - cur_sample_next <= oldest_sample(ind); - key_hash_next <= instance_handle_dds(ind); - stage_next <= FIND_NEXT_INSTANCE; - cnt_next <= 0; -- GET FIRST INSTANCE - end if; - else - stage_next <= RETURN_DDS; - dds_return_code_latch_next <= RETCODE_ILLEGAL_OPERATION; + start_read <= '1'; + if (ack_read = '1') then + ack_dds(ind) <= '1'; + stage_next <= WAIT_READ; end if; when TAKE_NEXT_INSTANCE => - ack_dds(ind) <= '1'; - -- Synthesis Guard - if (CONFIG_ARRAY_T(ind).WITH_KEY) then - -- No Samples Available - if (oldest_sample(ind) = SAMPLE_MEMORY_MAX_ADDRESS) then - stage_next <= RETURN_DDS; - dds_return_code_latch_next <= RETCODE_NO_DATA; - else - is_take_next <= '1'; - single_instance_next <= '1'; - dynamic_next_instance_next <= '1'; - cur_sample_next <= oldest_sample(ind); - key_hash_next <= instance_handle_dds(ind); - stage_next <= FIND_NEXT_INSTANCE; - cnt_next <= 0; -- GET FIRST INSTANCE - end if; - else - stage_next <= RETURN_DDS; - dds_return_code_latch_next <= RETCODE_ILLEGAL_OPERATION; + start_read <= '1'; + if (ack_read = '1') then + ack_dds(ind) <= '1'; + stage_next <= WAIT_READ; end if; when GET_SAMPLE_REJECTED_STATUS => ack_dds(ind) <= '1'; @@ -1322,12 +1231,12 @@ begin if (valid_in_rtps(ind) = '1') then -- NOTE: The PAYLOAD_FLAG and KEY_HASH_FLAG are set by the RTPS Reader -- NOTE: The ALIGNED_FLAG is set by default. if actual Payload is not aligned, need to reset. - sample_valid_in <= '1'; - sample_addr <= cur_sample + SMF_STATUS_INFO_OFFSET; - sample_write_data <= data_in_rtps(ind); - sample_write_data(SSI_KEY_HASH_FLAG) <= '0'; -- Key Hash Flag is not stored - sample_write_data(SSI_READ_FLAG) <= '0'; - sample_write_data(SSI_ALIGNED_FLAG) <= data_in_rtps(ind)(SSI_DATA_FLAG); + sample_valid_in1 <= '1'; + sample_addr1 <= cur_sample + SMF_STATUS_INFO_OFFSET; + sample_write_data1 <= data_in_rtps(ind); + sample_write_data1(SSI_KEY_HASH_FLAG) <= '0'; -- Key Hash Flag is not stored + sample_write_data1(SSI_READ_FLAG) <= '0'; + sample_write_data1(SSI_ALIGNED_FLAG) <= data_in_rtps(ind)(SSI_DATA_FLAG); -- Latch Status Info sample_status_info_next <= data_in_rtps(ind); sample_status_info_next(SSI_READ_FLAG) <= '0'; @@ -1345,9 +1254,9 @@ begin when 1 => -- Input Guard if (valid_in_rtps(ind) = '1') then - sample_valid_in <= '1'; - sample_addr <= cur_sample + SMF_TIMESTAMP_OFFSET; - sample_write_data <= data_in_rtps(ind); + sample_valid_in1 <= '1'; + sample_addr1 <= cur_sample + SMF_TIMESTAMP_OFFSET; + sample_write_data1 <= data_in_rtps(ind); -- Latch Timestamp ts_latch_next(0) <= unsigned(data_in_rtps(ind)); -- Memory Flow Control Guard @@ -1360,9 +1269,9 @@ begin when 2 => -- Input Guard if (valid_in_rtps(ind) = '1') then - sample_valid_in <= '1'; - sample_addr <= cur_sample + SMF_TIMESTAMP_OFFSET + 1; - sample_write_data <= data_in_rtps(ind); + sample_valid_in1 <= '1'; + sample_addr1 <= cur_sample + SMF_TIMESTAMP_OFFSET + 1; + sample_write_data1 <= data_in_rtps(ind); -- Latch Timestamp ts_latch_next(1) <= unsigned(data_in_rtps(ind)); -- Memory Flow Control Guard @@ -1391,9 +1300,9 @@ begin when 3 => -- Input Guard if (valid_in_rtps(ind) = '1') then - sample_valid_in <= '1'; - sample_addr <= cur_sample + SMF_LIFESPAN_DEADLINE_OFFSET; - sample_write_data <= data_in_rtps(ind); + sample_valid_in1 <= '1'; + sample_addr1 <= cur_sample + SMF_LIFESPAN_DEADLINE_OFFSET; + sample_write_data1 <= data_in_rtps(ind); -- Latch Lifespan lifespan_next(0) <= unsigned(data_in_rtps(ind)); -- Memory Flow Control Guard @@ -1406,9 +1315,9 @@ begin when 4 => -- Input Guard if (valid_in_rtps(ind) = '1') then - sample_valid_in <= '1'; - sample_addr <= cur_sample + SMF_LIFESPAN_DEADLINE_OFFSET + 1; - sample_write_data <= data_in_rtps(ind); + sample_valid_in1 <= '1'; + sample_addr1 <= cur_sample + SMF_LIFESPAN_DEADLINE_OFFSET + 1; + sample_write_data1 <= data_in_rtps(ind); -- Latch Lifespan lifespan_next(1) <= unsigned(data_in_rtps(ind)); -- Memory Flow Control Guard @@ -1474,16 +1383,16 @@ begin -- SET Payload Address when 10 => assert (empty_payload_list_head(ind) /= PAYLOAD_MEMORY_MAX_ADDRESS) severity FAILURE; - sample_valid_in <= '1'; - sample_addr <= cur_sample + SMF_PAYLOAD_ADDR_OFFSET; + sample_valid_in1 <= '1'; + sample_addr1 <= cur_sample + SMF_PAYLOAD_ADDR_OFFSET; if (has_data = '1') then -- Store Payload Address - sample_write_data <= std_logic_vector(resize(empty_payload_list_head(ind), WORD_WIDTH)); + sample_write_data1 <= std_logic_vector(resize(empty_payload_list_head(ind), WORD_WIDTH)); cur_payload_next <= empty_payload_list_head(ind); else -- Mark Sample with no Payload - sample_write_data <= std_logic_vector(resize(PAYLOAD_MEMORY_MAX_ADDRESS, WORD_WIDTH)); + sample_write_data1 <= std_logic_vector(resize(PAYLOAD_MEMORY_MAX_ADDRESS, WORD_WIDTH)); end if; -- Memory Flow Control Guard @@ -1494,7 +1403,7 @@ begin elsif (has_data = '1') then stage_next <= ADD_PAYLOAD; cnt_next <= 0; - cnt2_next <= 1; + payload_cnt_next <= 1; else assert (has_data = '0' and has_key_hash = '1') severity FAILURE; stage_next <= INITIATE_INSTANCE_SEARCH; @@ -1520,7 +1429,7 @@ begin else stage_next <= ADD_PAYLOAD; cnt_next <= 0; - cnt2_next <= 1; + payload_cnt_next <= 1; end if; end if; when others => @@ -1542,7 +1451,7 @@ begin -- Input Guard if (valid_in_rtps(ind) = '1') then payload_valid_in <= '1'; - payload_addr <= cur_payload + cnt2; + payload_addr <= cur_payload + payload_cnt; payload_write_data <= data_in_rtps(ind); -- Memory Control Flow Guard if (payload_ready_in = '1') then @@ -1554,7 +1463,7 @@ begin -- End of Payload if (last_word_in_rtps(ind) = '1') then -- End of Payload Slot - if (cnt2 = PAYLOAD_FRAME_SIZE(ind)-1) then + if (payload_cnt = PAYLOAD_FRAME_SIZE(ind)-1) then stage_next <= INITIATE_INSTANCE_SEARCH; else stage_next <= ALIGN_PAYLOAD; @@ -1562,12 +1471,12 @@ begin end if; else -- End of Payload Slot - if (cnt2 = PAYLOAD_FRAME_SIZE(ind)-1) then + if (payload_cnt = PAYLOAD_FRAME_SIZE(ind)-1) then stage_next <= NEXT_PAYLOAD_SLOT; cnt_next <= 0; else -- Next Word - cnt2_next <= cnt2 + 1; + payload_cnt_next <= payload_cnt + 1; end if; end if; end if; @@ -1591,24 +1500,24 @@ begin if (last_word_in_rtps(ind) = '1') then last_word_out_kh(ind) <= '1'; -- End of Payload Slot - if (cnt2 = PAYLOAD_FRAME_SIZE(ind)-1) then + if (payload_cnt = PAYLOAD_FRAME_SIZE(ind)-1) then -- Fetch the Key Hash stage_next <= GET_KEY_HASH; cnt_next <= 0; - cnt2_next <= 0; + payload_cnt_next <= 0; else stage_next <= ALIGN_PAYLOAD; cnt_next <= 0; end if; else -- End of Payload Slot - if (cnt2 = PAYLOAD_FRAME_SIZE(ind)-1) then + if (payload_cnt = PAYLOAD_FRAME_SIZE(ind)-1) then stage_next <= NEXT_PAYLOAD_SLOT; cnt_next <= 0; else -- Next Word cnt_next <= 0; -- PUSH TO MEMORY - cnt2_next <= cnt2 + 1; + payload_cnt_next <= payload_cnt + 1; end if; end if; else @@ -1618,7 +1527,7 @@ begin -- Fetch the Key Hash stage_next <= GET_KEY_HASH; cnt_next <= 0; - cnt2_next <= 0; + payload_cnt_next <= 0; else -- Next Word cnt_next <= 1; -- Same Sub-state @@ -1668,7 +1577,7 @@ begin cur_payload_next <= resize(unsigned(payload_read_data),PAYLOAD_MEMORY_ADDR_WIDTH); stage_next <= ADD_PAYLOAD; cnt_next <= 0; - cnt2_next <= 1; + payload_cnt_next <= 1; end if; end if; when others => @@ -1678,10 +1587,10 @@ begin case (cnt) is -- Mark Payload as unaligned when 0 => - sample_valid_in <= '1'; - sample_addr <= cur_sample + SMF_STATUS_INFO_OFFSET; - sample_write_data <= sample_status_info; - sample_write_data(SSI_ALIGNED_FLAG) <= '0'; + sample_valid_in1 <= '1'; + sample_addr1 <= cur_sample + SMF_STATUS_INFO_OFFSET; + sample_write_data1 <= sample_status_info; + sample_write_data1(SSI_ALIGNED_FLAG) <= '0'; -- Memory Control Flow Guard if (sample_ready_in = '1') then @@ -1691,14 +1600,14 @@ begin when 1 => payload_valid_in <= '1'; payload_addr <= cur_payload + PAYLOAD_FRAME_SIZE(ind)-1; - payload_write_data <= std_logic_vector(to_unsigned(cnt2, WORD_WIDTH)); + payload_write_data <= std_logic_vector(to_unsigned(payload_cnt, WORD_WIDTH)); -- Memory Control Flow Guard if (payload_ready_in = '1') then if (has_key_hash = '0') then stage_next <= GET_KEY_HASH; cnt_next <= 0; - cnt2_next <= 0; + payload_cnt_next <= 0; else stage_next <= INITIATE_INSTANCE_SEARCH; end if; @@ -1723,10 +1632,10 @@ begin ready_in_kh(ind) <= '1'; if (valid_in_kh(ind) = '1') then - cnt2_next <= cnt2 + 1; + payload_cnt_next <= payload_cnt + 1; -- Latch Key Hash - key_hash_next(cnt2) <= data_in_kh(ind); + key_hash_next(payload_cnt) <= data_in_kh(ind); -- Exit Condition if (last_word_in_kh(ind) = '1') then @@ -1740,11 +1649,11 @@ begin when INITIATE_INSTANCE_SEARCH => -- Memory Operation Guard if (inst_op_done = '1') then - inst_op_start <= '1'; - inst_opcode <= SEARCH_INSTANCE; - inst_r.i <= ind; - inst_r.key_hash <= key_hash; - inst_r.field_flags <= IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_DISPOSED_CNT_FLAG or IMF_NO_WRITERS_CNT_FLAG or IMF_IGNORE_DEADLINE_FLAG or IMF_WRITER_BITMAP_FLAG; + inst_op_start1 <= '1'; + inst_opcode1 <= SEARCH_INSTANCE; + inst_r1.i <= ind; + inst_r1.key_hash <= key_hash; + inst_r1.field_flags <= IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_DISPOSED_CNT_FLAG or IMF_NO_WRITERS_CNT_FLAG or IMF_IGNORE_DEADLINE_FLAG or IMF_WRITER_BITMAP_FLAG; stage_next <= FILTER_STAGE; @@ -1904,11 +1813,11 @@ begin ret_rtps(ind) <= OK; -- Remove Stale Instance and Insert Instance - inst_op_start <= '1'; - inst_opcode <= GET_INSTANCE; - inst_r.i <= ind; - inst_r.addr <= inst_occupied_head(ind); - inst_r.field_flags <= IMF_SAMPLE_CNT_FLAG or IMF_WRITER_BITMAP_FLAG; + inst_op_start1 <= '1'; + inst_opcode1 <= GET_INSTANCE; + inst_r1.i <= ind; + inst_r1.addr <= inst_occupied_head(ind); + inst_r1.field_flags <= IMF_SAMPLE_CNT_FLAG or IMF_WRITER_BITMAP_FLAG; stage_next <= REMOVE_STALE_INSTANCE; cnt_next <= 0; end if; @@ -1917,11 +1826,11 @@ begin ret_rtps(ind) <= OK; -- Remove Stale Instance and Insert Instance - inst_op_start <= '1'; - inst_opcode <= GET_INSTANCE; - inst_r.addr <= inst_occupied_head(ind); - inst_r.i <= ind; - inst_r.field_flags <= IMF_SAMPLE_CNT_FLAG or IMF_WRITER_BITMAP_FLAG; + inst_op_start1 <= '1'; + inst_opcode1 <= GET_INSTANCE; + inst_r1.addr <= inst_occupied_head(ind); + inst_r1.i <= ind; + inst_r1.field_flags <= IMF_SAMPLE_CNT_FLAG or IMF_WRITER_BITMAP_FLAG; stage_next <= REMOVE_STALE_INSTANCE; cnt_next <= 0; end if; @@ -1947,20 +1856,20 @@ begin ret_rtps(ind) <= OK; -- Insert New Instance - inst_op_start <= '1'; - inst_opcode <= INSERT_INSTANCE; - inst_r.i <= ind; - inst_r.key_hash <= key_hash; - inst_r.status_info <= (ISI_LIVELINESS_FLAG => '1', ISI_NOT_ALIVE_DISPOSED_FLAG => sample_status_info(SSI_DISPOSED_FLAG), others => '0'); - inst_r.sample_cnt <= to_unsigned(1, WORD_WIDTH); + inst_op_start1 <= '1'; + inst_opcode1 <= INSERT_INSTANCE; + inst_r1.i <= ind; + inst_r1.key_hash <= key_hash; + inst_r1.status_info <= (ISI_LIVELINESS_FLAG => '1', ISI_NOT_ALIVE_DISPOSED_FLAG => sample_status_info(SSI_DISPOSED_FLAG), others => '0'); + inst_r1.sample_cnt <= to_unsigned(1, WORD_WIDTH); if (CONFIG_ARRAY_T(ind).TIME_BASED_FILTER_QOS /= DURATION_ZERO) then - inst_r.ignore_deadline <= time + CONFIG_ARRAY_T(ind).TIME_BASED_FILTER_QOS; + inst_r1.ignore_deadline <= time + CONFIG_ARRAY_T(ind).TIME_BASED_FILTER_QOS; else - inst_r.ignore_deadline <= TIME_INVALID; + inst_r1.ignore_deadline <= TIME_INVALID; end if; tmp_bitmap := (others => '0'); tmp_bitmap(writer_id) := '1'; - inst_r.writer_bitmap <= to_writer_bitmap_array(tmp_bitmap); + inst_r1.writer_bitmap <= to_writer_bitmap_array(tmp_bitmap); if (CONFIG_ARRAY_T(ind).DESTINATION_ORDER_QOS = BY_SOURCE_TIMESTAMP_DESTINATION_ORDER_QOS and newest_sample(ind) /= SAMPLE_MEMORY_MAX_ADDRESS) then stage_next <= FIND_POS; @@ -1984,20 +1893,20 @@ begin ret_rtps(ind) <= OK; -- Insert New Instance - inst_op_start <= '1'; - inst_opcode <= INSERT_INSTANCE; - inst_r.i <= ind; - inst_r.key_hash <= key_hash; - inst_r.status_info <= (ISI_LIVELINESS_FLAG => '1', ISI_NOT_ALIVE_DISPOSED_FLAG => sample_status_info(SSI_DISPOSED_FLAG), others => '0'); - inst_r.sample_cnt <= to_unsigned(1, WORD_WIDTH); + inst_op_start1 <= '1'; + inst_opcode1 <= INSERT_INSTANCE; + inst_r1.i <= ind; + inst_r1.key_hash <= key_hash; + inst_r1.status_info <= (ISI_LIVELINESS_FLAG => '1', ISI_NOT_ALIVE_DISPOSED_FLAG => sample_status_info(SSI_DISPOSED_FLAG), others => '0'); + inst_r1.sample_cnt <= to_unsigned(1, WORD_WIDTH); if (CONFIG_ARRAY_T(ind).TIME_BASED_FILTER_QOS /= DURATION_ZERO) then - inst_r.ignore_deadline <= time + CONFIG_ARRAY_T(ind).TIME_BASED_FILTER_QOS; + inst_r1.ignore_deadline <= time + CONFIG_ARRAY_T(ind).TIME_BASED_FILTER_QOS; else - inst_r.ignore_deadline <= TIME_INVALID; + inst_r1.ignore_deadline <= TIME_INVALID; end if; tmp_bitmap := (others => '0'); tmp_bitmap(writer_id) := '1'; - inst_r.writer_bitmap <= to_writer_bitmap_array(tmp_bitmap); + inst_r1.writer_bitmap <= to_writer_bitmap_array(tmp_bitmap); if (CONFIG_ARRAY_T(ind).DESTINATION_ORDER_QOS = BY_SOURCE_TIMESTAMP_DESTINATION_ORDER_QOS and newest_sample(ind) /= SAMPLE_MEMORY_MAX_ADDRESS) then stage_next <= FIND_POS; @@ -2025,9 +1934,9 @@ begin case (cnt) is -- GET Timestamp 1/2 when 0 => - sample_valid_in <= '1'; - sample_addr <= cur_sample + SMF_TIMESTAMP_OFFSET; - sample_read <= '1'; + sample_valid_in1 <= '1'; + sample_addr1 <= cur_sample + SMF_TIMESTAMP_OFFSET; + sample_read1 <= '1'; -- Memory Flow Control Guard if (sample_ready_in = '1') then @@ -2035,9 +1944,9 @@ begin end if; -- GET Timestamp 2/2 when 1 => - sample_valid_in <= '1'; - sample_addr <= cur_sample + SMF_TIMESTAMP_OFFSET + 1; - sample_read <= '1'; + sample_valid_in1 <= '1'; + sample_addr1 <= cur_sample + SMF_TIMESTAMP_OFFSET + 1; + sample_read1 <= '1'; -- Memory Flow Control Guard if (sample_ready_in = '1') then @@ -2045,9 +1954,9 @@ begin end if; -- GET Previous Sample when 2 => - sample_valid_in <= '1'; - sample_addr <= cur_sample + SMF_PREV_ADDR_OFFSET; - sample_read <= '1'; + sample_valid_in1 <= '1'; + sample_addr1 <= cur_sample + SMF_PREV_ADDR_OFFSET; + sample_read1 <= '1'; -- Memory Flow Control Guard if (sample_ready_in = '1') then @@ -2055,9 +1964,9 @@ begin end if; -- GET Instance Pointer when 3 => - sample_valid_in <= '1'; - sample_addr <= cur_sample + SMF_INSTANCE_ADDR_OFFSET; - sample_read <= '1'; + sample_valid_in1 <= '1'; + sample_addr1 <= cur_sample + SMF_INSTANCE_ADDR_OFFSET; + sample_read1 <= '1'; -- Memory Flow Control Guard if (sample_ready_in = '1') then @@ -2065,7 +1974,7 @@ begin end if; -- READ Timestamp 1/2 when 4 => - sample_ready_out <= '1'; + sample_ready_out1 <= '1'; -- Memory Flow Control Guard if (sample_valid_out = '1') then @@ -2074,7 +1983,7 @@ begin end if; -- READ Timestamp 2/2 when 5 => - sample_ready_out <= '1'; + sample_ready_out1 <= '1'; -- Memory Flow Control Guard if (sample_valid_out = '1') then @@ -2082,7 +1991,7 @@ begin -- Found position (After current slot) if (ts_latch >= tmp_dw) then - sample_abort_read <= '1'; + sample_abort_read1 <= '1'; prev_sample_next <= cur_sample; cur_sample_next <= empty_sample_list_head(ind); if (new_inst = '1') then @@ -2102,7 +2011,7 @@ begin end if; -- READ Previous Sample Pointer when 6 => - sample_ready_out <= '1'; + sample_ready_out1 <= '1'; -- Memory Flow Control Guard if (sample_valid_out = '1') then @@ -2111,7 +2020,7 @@ begin end if; -- READ Instance Poiner when 7 => - sample_ready_out <= '1'; + sample_ready_out1 <= '1'; -- Memory Flow Control Guard if (sample_valid_out = '1') then @@ -2157,9 +2066,9 @@ begin end if; -- GET Disposed Generation Count when 8 => - sample_valid_in <= '1'; - sample_addr <= cur_sample + SMF_DISPOSED_GEN_CNT_OFFSET; - sample_read <= '1'; + sample_valid_in1 <= '1'; + sample_addr1 <= cur_sample + SMF_DISPOSED_GEN_CNT_OFFSET; + sample_read1 <= '1'; -- Memory Flow Control Guard if (sample_ready_in = '1') then @@ -2167,9 +2076,9 @@ begin end if; -- GET No Writers Generation Count when 9 => - sample_valid_in <= '1'; - sample_addr <= cur_sample + SMF_NO_WRITERS_GEN_CNT_OFFSET; - sample_read <= '1'; + sample_valid_in1 <= '1'; + sample_addr1 <= cur_sample + SMF_NO_WRITERS_GEN_CNT_OFFSET; + sample_read1 <= '1'; -- Memory Flow Control Guard if (sample_ready_in = '1') then @@ -2177,7 +2086,7 @@ begin end if; -- READ Disposed Generation Count when 10 => - sample_ready_out <= '1'; + sample_ready_out1 <= '1'; -- Memory Flow Control Guard if (sample_valid_out = '1') then @@ -2188,7 +2097,7 @@ begin end if; -- READ No Writers Generation Count when 11 => - sample_ready_out <= '1'; + sample_ready_out1 <= '1'; -- Memory Flow Control Guard if (sample_valid_out = '1') then @@ -2216,8 +2125,8 @@ begin -- DEFAULT STATUS INFO (LIVELINESS) tmp_update := IMF_STATUS_FLAG; - inst_r.status_info <= inst_data.status_info; - inst_r.status_info(ISI_LIVELINESS_FLAG) <= '1'; + inst_r1.status_info <= inst_data.status_info; + inst_r1.status_info(ISI_LIVELINESS_FLAG) <= '1'; -- *WRITER BITMAP* -- Convert Writer Bitmap to SLV @@ -2229,7 +2138,7 @@ begin -- Insert Writer tmp_bitmap(writer_id) := '1'; -- Convert Back - inst_r.writer_bitmap <= to_writer_bitmap_array(tmp_bitmap); + inst_r1.writer_bitmap <= to_writer_bitmap_array(tmp_bitmap); tmp_update := tmp_update or IMF_WRITER_BITMAP_FLAG; end if; else @@ -2238,7 +2147,7 @@ begin -- Insert Writer tmp_bitmap(writer_id) := '0'; -- Convert Back - inst_r.writer_bitmap <= to_writer_bitmap_array(tmp_bitmap); + inst_r1.writer_bitmap <= to_writer_bitmap_array(tmp_bitmap); tmp_update := tmp_update or IMF_WRITER_BITMAP_FLAG; end if; end if; @@ -2249,13 +2158,13 @@ begin -- NOT_ALIVE_DISPOSED -> ALIVE Transition if (sample_status_info(SSI_DISPOSED_FLAG) = '0' and sample_status_info(SSI_UNREGISTERED_FLAG) = '0' and inst_data.status_info(ISI_NOT_ALIVE_DISPOSED_FLAG) = '1') then tmp_update := tmp_update or IMF_DISPOSED_CNT_FLAG; - inst_r.disposed_gen_cnt <= inst_data.disposed_gen_cnt + 1; - inst_r.status_info(ISI_VIEW_FLAG) <= '0'; + inst_r1.disposed_gen_cnt <= inst_data.disposed_gen_cnt + 1; + inst_r1.status_info(ISI_VIEW_FLAG) <= '0'; -- NOT_ALIVE_NO_WRITERS -> ALIVE Transition OR NOT_ALIVE_NO_WRITERS -> NOT_ALIVE_DISPOSED Transition elsif (sample_status_info(SSI_UNREGISTERED_FLAG) = '0' and inst_data.status_info(ISI_NOT_ALIVE_NO_WRITERS_FLAG) = '1') then tmp_update := tmp_update or IMF_NO_WRITERS_CNT_FLAG; - inst_r.no_writers_gen_cnt <= inst_data.no_writers_gen_cnt + 1; - inst_r.status_info(ISI_VIEW_FLAG) <= '0'; + inst_r1.no_writers_gen_cnt <= inst_data.no_writers_gen_cnt + 1; + inst_r1.status_info(ISI_VIEW_FLAG) <= '0'; end if; end if; @@ -2267,8 +2176,8 @@ begin tmp_bool := FALSE; -- Only Update Instance State if Sample if newest elsif (newer_inst_sample = '0') then - inst_r.status_info(ISI_NOT_ALIVE_DISPOSED_FLAG) <= '1'; - inst_r.status_info(ISI_NOT_ALIVE_NO_WRITERS_FLAG) <= '0'; + inst_r1.status_info(ISI_NOT_ALIVE_DISPOSED_FLAG) <= '1'; + inst_r1.status_info(ISI_NOT_ALIVE_NO_WRITERS_FLAG) <= '0'; end if; -- * -> NOT_ALIVE_NO_WRITERS Transition elsif (sample_status_info(SSI_UNREGISTERED_FLAG) = '1' and tmp_bitmap = (tmp_bitmap'reverse_range => '0')) then @@ -2277,8 +2186,8 @@ begin tmp_bool := FALSE; -- Only Update Instance State if Sample if newest elsif (newer_inst_sample = '0') then - inst_r.status_info(ISI_NOT_ALIVE_DISPOSED_FLAG) <= '0'; - inst_r.status_info(ISI_NOT_ALIVE_NO_WRITERS_FLAG) <= '1'; + inst_r1.status_info(ISI_NOT_ALIVE_DISPOSED_FLAG) <= '0'; + inst_r1.status_info(ISI_NOT_ALIVE_NO_WRITERS_FLAG) <= '1'; end if; -- * -> ALIVE Transition elsif (sample_status_info(SSI_UNREGISTERED_FLAG) = '0' and sample_status_info(SSI_DISPOSED_FLAG) = '0') then @@ -2292,8 +2201,8 @@ begin end if; -- Only Update Instance State if Sample if newest elsif (newer_inst_sample = '0') then - inst_r.status_info(ISI_NOT_ALIVE_DISPOSED_FLAG) <= '0'; - inst_r.status_info(ISI_NOT_ALIVE_NO_WRITERS_FLAG) <= '0'; + inst_r1.status_info(ISI_NOT_ALIVE_DISPOSED_FLAG) <= '0'; + inst_r1.status_info(ISI_NOT_ALIVE_NO_WRITERS_FLAG) <= '0'; end if; else tmp_bool := FALSE; @@ -2302,13 +2211,13 @@ begin -- *INSTANCE SAMPLE COUNT* if (tmp_bool) then tmp_update := tmp_update or IMF_SAMPLE_CNT_FLAG; - inst_r.sample_cnt <= inst_data.sample_cnt + 1; + inst_r1.sample_cnt <= inst_data.sample_cnt + 1; end if; -- *IGNORE DEADLINE* if (CONFIG_ARRAY_T(ind).TIME_BASED_FILTER_QOS /= DURATION_ZERO) then tmp_update := tmp_update or IMF_IGNORE_DEADLINE_FLAG; - inst_r.ignore_deadline <= time + CONFIG_ARRAY_T(ind).TIME_BASED_FILTER_QOS; + inst_r1.ignore_deadline <= time + CONFIG_ARRAY_T(ind).TIME_BASED_FILTER_QOS; end if; -- *STALE INSTANCE COUNT* @@ -2328,11 +2237,11 @@ begin end if; -- UPDATE Instance - inst_op_start <= '1'; - inst_opcode <= UPDATE_INSTANCE; - inst_r.i <= ind; - inst_r.addr <= inst_data.addr; - inst_r.field_flags <= tmp_update; + inst_op_start1 <= '1'; + inst_opcode1 <= UPDATE_INSTANCE; + inst_r1.i <= ind; + inst_r1.addr <= inst_data.addr; + inst_r1.field_flags <= tmp_update; if (not tmp_bool) then -- DONE (Drop Sample) @@ -2396,13 +2305,13 @@ begin case (cnt) is -- SET Disposed Generation Counter when 0 => - sample_valid_in <= '1'; - sample_addr <= cur_sample + SMF_DISPOSED_GEN_CNT_OFFSET; + sample_valid_in1 <= '1'; + sample_addr1 <= cur_sample + SMF_DISPOSED_GEN_CNT_OFFSET; if (newer_inst_sample = '1') then - sample_write_data <= std_logic_vector(dis_gen_cnt_latch); + sample_write_data1 <= std_logic_vector(dis_gen_cnt_latch); else - sample_write_data <= std_logic_vector(inst_data.disposed_gen_cnt); + sample_write_data1 <= std_logic_vector(inst_data.disposed_gen_cnt); end if; -- Memory Flow Control Guard @@ -2411,13 +2320,13 @@ begin end if; -- SET No Writer Generation Counter when 1 => - sample_valid_in <= '1'; - sample_addr <= cur_sample + SMF_NO_WRITERS_GEN_CNT_OFFSET; + sample_valid_in1 <= '1'; + sample_addr1 <= cur_sample + SMF_NO_WRITERS_GEN_CNT_OFFSET; if (newer_inst_sample = '1') then - sample_write_data <= std_logic_vector(no_w_gen_cnt_latch); + sample_write_data1 <= std_logic_vector(no_w_gen_cnt_latch); else - sample_write_data <= std_logic_vector(inst_data.no_writers_gen_cnt); + sample_write_data1 <= std_logic_vector(inst_data.no_writers_gen_cnt); end if; -- Memory Flow Control Guard @@ -2453,9 +2362,9 @@ begin -- Next Pointer (Previous Sample) when 0 => -- Fix Next Pointer - sample_valid_in <= '1'; - sample_addr <= prev_sample + SMF_NEXT_ADDR_OFFSET; - sample_write_data <= std_logic_vector(resize(empty_sample_list_head(ind),WORD_WIDTH)); + sample_valid_in1 <= '1'; + sample_addr1 <= prev_sample + SMF_NEXT_ADDR_OFFSET; + sample_write_data1 <= std_logic_vector(resize(empty_sample_list_head(ind),WORD_WIDTH)); -- Memory Flow Control Guard if (sample_ready_in = '1') then @@ -2473,9 +2382,9 @@ begin -- Previous Pointer (Next Sample) when 1 => -- Fix Previous Pointer - sample_valid_in <= '1'; - sample_addr <= next_sample + SMF_PREV_ADDR_OFFSET; - sample_write_data <= std_logic_vector(resize(empty_sample_list_head(ind),WORD_WIDTH)); + sample_valid_in1 <= '1'; + sample_addr1 <= next_sample + SMF_PREV_ADDR_OFFSET; + sample_write_data1 <= std_logic_vector(resize(empty_sample_list_head(ind),WORD_WIDTH)); -- Memory Flow Control Guard if (sample_ready_in = '1') then @@ -2492,9 +2401,9 @@ begin case (cnt) is -- GET Next (Empty) Sample when 0 => - sample_valid_in <= '1'; - sample_addr <= cur_sample + SMF_NEXT_ADDR_OFFSET; - sample_read <= '1'; + sample_valid_in1 <= '1'; + sample_addr1 <= cur_sample + SMF_NEXT_ADDR_OFFSET; + sample_read1 <= '1'; -- Memory Flow Control Guard if (sample_ready_in = '1') then cnt_next <= cnt + 1; @@ -2502,9 +2411,9 @@ begin -- SET Instance Pointer when 1 => -- Write Instance Pointer - sample_valid_in <= '1'; - sample_addr <= cur_sample + SMF_INSTANCE_ADDR_OFFSET; - sample_write_data <= std_logic_vector(resize(cur_inst,WORD_WIDTH)); + sample_valid_in1 <= '1'; + sample_addr1 <= cur_sample + SMF_INSTANCE_ADDR_OFFSET; + sample_write_data1 <= std_logic_vector(resize(cur_inst,WORD_WIDTH)); -- Memory Flow Control Guard if (sample_ready_in = '1') then @@ -2513,9 +2422,9 @@ begin -- SET Previous Pointer when 2 => -- Write Previous Pointer - sample_valid_in <= '1'; - sample_addr <= cur_sample + SMF_PREV_ADDR_OFFSET; - sample_write_data <= std_logic_vector(resize(prev_sample,WORD_WIDTH)); + sample_valid_in1 <= '1'; + sample_addr1 <= cur_sample + SMF_PREV_ADDR_OFFSET; + sample_write_data1 <= std_logic_vector(resize(prev_sample,WORD_WIDTH)); -- Memory Flow Control Guard if (sample_ready_in = '1') then @@ -2524,9 +2433,9 @@ begin -- SET Next Pointer when 3 => -- Write Next Pointer - sample_valid_in <= '1'; - sample_addr <= cur_sample + SMF_NEXT_ADDR_OFFSET; - sample_write_data <= std_logic_vector(resize(next_sample,WORD_WIDTH)); + sample_valid_in1 <= '1'; + sample_addr1 <= cur_sample + SMF_NEXT_ADDR_OFFSET; + sample_write_data1 <= std_logic_vector(resize(next_sample,WORD_WIDTH)); -- Memory Flow Control Guard if (sample_ready_in = '1') then @@ -2535,7 +2444,7 @@ begin -- READ Next (Empty) Sample when 4 => - sample_ready_out <= '1'; + sample_ready_out1 <= '1'; -- Memory Flow Control Guard if (sample_valid_out = '1') then @@ -2591,9 +2500,9 @@ begin case (cnt) is -- GET Next Sample (Empty List) when 0 => - sample_valid_in <= '1'; - sample_addr <= cur_sample + SMF_NEXT_ADDR_OFFSET; - sample_read <= '1'; + sample_valid_in1 <= '1'; + sample_addr1 <= cur_sample + SMF_NEXT_ADDR_OFFSET; + sample_read1 <= '1'; -- Memory Flow Control Guard if (sample_ready_in = '1') then @@ -2601,9 +2510,9 @@ begin end if; -- SET Sample Status Info when 1 => - sample_valid_in <= '1'; - sample_addr <= cur_sample + SMF_STATUS_INFO_OFFSET; - sample_write_data <= (SSI_UNREGISTERED_FLAG => '1', others => '0'); + sample_valid_in1 <= '1'; + sample_addr1 <= cur_sample + SMF_STATUS_INFO_OFFSET; + sample_write_data1 <= (SSI_UNREGISTERED_FLAG => '1', others => '0'); -- Memory Flow Control Guard if (sample_ready_in = '1') then @@ -2611,9 +2520,9 @@ begin end if; -- SET Timestamp 1/2 when 2 => - sample_valid_in <= '1'; - sample_addr <= cur_sample + SMF_TIMESTAMP_OFFSET; - sample_write_data <= std_logic_vector(time(0)); + sample_valid_in1 <= '1'; + sample_addr1 <= cur_sample + SMF_TIMESTAMP_OFFSET; + sample_write_data1 <= std_logic_vector(time(0)); -- Memory Flow Control Guard if (sample_ready_in = '1') then @@ -2621,9 +2530,9 @@ begin end if; -- SET Timestamp 2/2 when 3 => - sample_valid_in <= '1'; - sample_addr <= cur_sample + SMF_TIMESTAMP_OFFSET + 1; - sample_write_data <= std_logic_vector(time(1)); + sample_valid_in1 <= '1'; + sample_addr1 <= cur_sample + SMF_TIMESTAMP_OFFSET + 1; + sample_write_data1 <= std_logic_vector(time(1)); -- Memory Flow Control Guard if (sample_ready_in = '1') then @@ -2631,9 +2540,9 @@ begin end if; -- SET Lifespan 1/2 when 4 => - sample_valid_in <= '1'; - sample_addr <= cur_sample + SMF_LIFESPAN_DEADLINE_OFFSET; - sample_write_data <= std_logic_vector(TIME_INVALID(0)); + sample_valid_in1 <= '1'; + sample_addr1 <= cur_sample + SMF_LIFESPAN_DEADLINE_OFFSET; + sample_write_data1 <= std_logic_vector(TIME_INVALID(0)); -- Memory Flow Control Guard if (sample_ready_in = '1') then @@ -2641,9 +2550,9 @@ begin end if; -- SET Lifespan 2/2 when 5 => - sample_valid_in <= '1'; - sample_addr <= cur_sample + SMF_LIFESPAN_DEADLINE_OFFSET + 1; - sample_write_data <= std_logic_vector(TIME_INVALID(1)); + sample_valid_in1 <= '1'; + sample_addr1 <= cur_sample + SMF_LIFESPAN_DEADLINE_OFFSET + 1; + sample_write_data1 <= std_logic_vector(TIME_INVALID(1)); -- Memory Flow Control Guard if (sample_ready_in = '1') then @@ -2651,9 +2560,9 @@ begin end if; -- SET Payload Pointer when 6 => - sample_valid_in <= '1'; - sample_addr <= cur_sample + SMF_PAYLOAD_ADDR_OFFSET; - sample_write_data <= std_logic_vector(resize(PAYLOAD_MEMORY_MAX_ADDRESS,WORD_WIDTH)); + sample_valid_in1 <= '1'; + sample_addr1 <= cur_sample + SMF_PAYLOAD_ADDR_OFFSET; + sample_write_data1 <= std_logic_vector(resize(PAYLOAD_MEMORY_MAX_ADDRESS,WORD_WIDTH)); -- Memory Flow Control Guard if (sample_ready_in = '1') then @@ -2661,9 +2570,9 @@ begin end if; -- SET Instance Pointer when 7 => - sample_valid_in <= '1'; - sample_addr <= cur_sample + SMF_INSTANCE_ADDR_OFFSET; - sample_write_data <= std_logic_vector(resize(cur_inst,WORD_WIDTH)); + sample_valid_in1 <= '1'; + sample_addr1 <= cur_sample + SMF_INSTANCE_ADDR_OFFSET; + sample_write_data1 <= std_logic_vector(resize(cur_inst,WORD_WIDTH)); -- Memory Flow Control Guard if (sample_ready_in = '1') then @@ -2671,9 +2580,9 @@ begin end if; -- SET Disposed Generation Count when 8 => - sample_valid_in <= '1'; - sample_addr <= cur_sample + SMF_DISPOSED_GEN_CNT_OFFSET; - sample_write_data <= std_logic_vector(inst_data.disposed_gen_cnt); + sample_valid_in1 <= '1'; + sample_addr1 <= cur_sample + SMF_DISPOSED_GEN_CNT_OFFSET; + sample_write_data1 <= std_logic_vector(inst_data.disposed_gen_cnt); -- Memory Flow Control Guard if (sample_ready_in = '1') then @@ -2681,9 +2590,9 @@ begin end if; -- SET No Writers Generation Count when 9 => - sample_valid_in <= '1'; - sample_addr <= cur_sample + SMF_NO_WRITERS_GEN_CNT_OFFSET; - sample_write_data <= std_logic_vector(inst_data.no_writers_gen_cnt); + sample_valid_in1 <= '1'; + sample_addr1 <= cur_sample + SMF_NO_WRITERS_GEN_CNT_OFFSET; + sample_write_data1 <= std_logic_vector(inst_data.no_writers_gen_cnt); -- Memory Flow Control Guard if (sample_ready_in = '1') then @@ -2691,9 +2600,9 @@ begin end if; -- SET Previous Sample Pointer when 10 => - sample_valid_in <= '1'; - sample_addr <= cur_sample + SMF_PREV_ADDR_OFFSET; - sample_write_data <= std_logic_vector(resize(newest_sample(ind),WORD_WIDTH)); + sample_valid_in1 <= '1'; + sample_addr1 <= cur_sample + SMF_PREV_ADDR_OFFSET; + sample_write_data1 <= std_logic_vector(resize(newest_sample(ind),WORD_WIDTH)); -- Memory Flow Control Guard if (sample_ready_in = '1') then @@ -2701,9 +2610,9 @@ begin end if; -- SET Next Sample Pointer when 11 => - sample_valid_in <= '1'; - sample_addr <= cur_sample + SMF_NEXT_ADDR_OFFSET; - sample_write_data <= std_logic_vector(resize(SAMPLE_MEMORY_MAX_ADDRESS,WORD_WIDTH)); + sample_valid_in1 <= '1'; + sample_addr1 <= cur_sample + SMF_NEXT_ADDR_OFFSET; + sample_write_data1 <= std_logic_vector(resize(SAMPLE_MEMORY_MAX_ADDRESS,WORD_WIDTH)); -- Memory Flow Control Guard if (sample_ready_in = '1') then @@ -2712,9 +2621,9 @@ begin end if; -- SET Next Sample Pointer (Previous Sample) when 12 => - sample_valid_in <= '1'; - sample_addr <= newest_sample(ind) + SMF_NEXT_ADDR_OFFSET; - sample_write_data <= std_logic_vector(resize(empty_sample_list_head(ind),WORD_WIDTH)); + sample_valid_in1 <= '1'; + sample_addr1 <= newest_sample(ind) + SMF_NEXT_ADDR_OFFSET; + sample_write_data1 <= std_logic_vector(resize(empty_sample_list_head(ind),WORD_WIDTH)); -- Memory Flow Control Guard if (sample_ready_in = '1') then @@ -2722,7 +2631,7 @@ begin end if; -- READ Next Address (Empty List) when 13 => - sample_ready_out <= '1'; + sample_ready_out1 <= '1'; -- Memory Flow Control Guard if (sample_valid_out = '1') then @@ -2761,9 +2670,9 @@ begin case (cnt) is -- GET Instance Pointer (Oldest Sample) when 0 => - sample_valid_in <= '1'; - sample_addr <= oldest_sample(ind) + SMF_INSTANCE_ADDR_OFFSET; - sample_read <= '1'; + sample_valid_in1 <= '1'; + sample_addr1 <= oldest_sample(ind) + SMF_INSTANCE_ADDR_OFFSET; + sample_read1 <= '1'; -- Memory Flow Control Guard if (sample_ready_in = '1') then @@ -2773,7 +2682,7 @@ begin when 1 => -- Memory Operation Guard if (inst_op_done = '1') then - sample_ready_out <= '1'; + sample_ready_out1 <= '1'; -- Memory Flow Control Guard if (sample_valid_out = '1') then @@ -2792,9 +2701,9 @@ begin case (cnt) is -- GET Instance Pointer when 0 => - sample_valid_in <= '1'; - sample_addr <= cur_sample + SMF_INSTANCE_ADDR_OFFSET; - sample_read <= '1'; + sample_valid_in1 <= '1'; + sample_addr1 <= cur_sample + SMF_INSTANCE_ADDR_OFFSET; + sample_read1 <= '1'; -- Memory Flow Control Guard if (sample_ready_in = '1') then @@ -2802,9 +2711,9 @@ begin end if; -- GET Next Sample when 1 => - sample_valid_in <= '1'; - sample_addr <= cur_sample + SMF_NEXT_ADDR_OFFSET; - sample_read <= '1'; + sample_valid_in1 <= '1'; + sample_addr1 <= cur_sample + SMF_NEXT_ADDR_OFFSET; + sample_read1 <= '1'; -- Memory Flow Control Guard if (sample_ready_in = '1') then @@ -2812,13 +2721,13 @@ begin end if; -- READ Instance Pointer when 2 => - sample_ready_out <= '1'; + sample_ready_out1 <= '1'; -- Memory Flow Control Guard if (sample_valid_out = '1') then -- Oldest Instance Sample Found if (resize(unsigned(sample_read_data),INSTANCE_MEMORY_ADDR_WIDTH) = cur_inst) then - sample_abort_read <= '1'; + sample_abort_read1 <= '1'; stage_next <= REMOVE_SAMPLE; cnt_next <= 0; else @@ -2827,7 +2736,7 @@ begin end if; -- READ Next Sample when 3 => - sample_ready_out <= '1'; + sample_ready_out1 <= '1'; -- Memory Flow Control Guard if (sample_valid_out = '1') then @@ -2848,19 +2757,19 @@ begin else -- Memory Operation Guard if (inst_op_done = '1') then - inst_op_start <= '1'; - inst_opcode <= GET_INSTANCE; - inst_r.i <= ind; - inst_r.addr <= cur_inst; - inst_r.field_flags <= IMF_SAMPLE_CNT_FLAG or IMF_WRITER_BITMAP_FLAG or IMF_STATUS_FLAG; + inst_op_start1 <= '1'; + inst_opcode1 <= GET_INSTANCE; + inst_r1.i <= ind; + inst_r1.addr <= cur_inst; + inst_r1.field_flags <= IMF_SAMPLE_CNT_FLAG or IMF_WRITER_BITMAP_FLAG or IMF_STATUS_FLAG; cnt_next <= cnt + 1; end if; end if; -- GET Previous Sample when 1 => - sample_valid_in <= '1'; - sample_addr <= cur_sample + SMF_PREV_ADDR_OFFSET; - sample_read <= '1'; + sample_valid_in1 <= '1'; + sample_addr1 <= cur_sample + SMF_PREV_ADDR_OFFSET; + sample_read1 <= '1'; -- Memory Flow Control Guard if (sample_ready_in = '1') then @@ -2868,9 +2777,9 @@ begin end if; -- GET Next Sample when 2 => - sample_valid_in <= '1'; - sample_addr <= cur_sample + SMF_NEXT_ADDR_OFFSET; - sample_read <= '1'; + sample_valid_in1 <= '1'; + sample_addr1 <= cur_sample + SMF_NEXT_ADDR_OFFSET; + sample_read1 <= '1'; -- Memory Flow Control Guard if (sample_ready_in = '1') then @@ -2878,9 +2787,9 @@ begin end if; -- GET Payload Pointer when 3 => - sample_valid_in <= '1'; - sample_addr <= cur_sample + SMF_PAYLOAD_ADDR_OFFSET; - sample_read <= '1'; + sample_valid_in1 <= '1'; + sample_addr1 <= cur_sample + SMF_PAYLOAD_ADDR_OFFSET; + sample_read1 <= '1'; -- Memory Flow Control Guard if (sample_ready_in = '1') then @@ -2888,7 +2797,7 @@ begin end if; -- READ Previous Sample when 4 => - sample_ready_out <= '1'; + sample_ready_out1 <= '1'; -- Memory Flow Control Guard if (sample_valid_out = '1') then prev_sample_next <= resize(unsigned(sample_read_data),SAMPLE_MEMORY_ADDR_WIDTH); @@ -2896,7 +2805,7 @@ begin end if; -- READ Next Sample when 5 => - sample_ready_out <= '1'; + sample_ready_out1 <= '1'; -- Memory Flow Control Guard if (sample_valid_out = '1') then next_sample_next <= resize(unsigned(sample_read_data),SAMPLE_MEMORY_ADDR_WIDTH); @@ -2913,9 +2822,9 @@ begin -- SET Next Pointer (Empty List Tail) when 6 => -- Add Current Sample after Empty List Tail - sample_valid_in <= '1'; - sample_addr <= empty_sample_list_tail(ind) + SMF_NEXT_ADDR_OFFSET; - sample_write_data <= std_logic_vector(resize(cur_sample,WORD_WIDTH)); + sample_valid_in1 <= '1'; + sample_addr1 <= empty_sample_list_tail(ind) + SMF_NEXT_ADDR_OFFSET; + sample_write_data1 <= std_logic_vector(resize(cur_sample,WORD_WIDTH)); -- Memory Flow Control Guard if (sample_ready_in = '1') then @@ -2924,9 +2833,9 @@ begin -- SET Next Pointer (Current Sample) when 7 => -- Make Current Sample Empty List Tail - sample_valid_in <= '1'; - sample_addr <= cur_sample + SMF_NEXT_ADDR_OFFSET; - sample_write_data <= std_logic_vector(resize(SAMPLE_MEMORY_MAX_ADDRESS,WORD_WIDTH)); + sample_valid_in1 <= '1'; + sample_addr1 <= cur_sample + SMF_NEXT_ADDR_OFFSET; + sample_write_data1 <= std_logic_vector(resize(SAMPLE_MEMORY_MAX_ADDRESS,WORD_WIDTH)); -- Memory Flow Control Guard if (sample_ready_in = '1') then @@ -2960,9 +2869,9 @@ begin -- SET Previous Address (Next Sample) when 8 => -- Remove link to cur_sample - sample_valid_in <= '1'; - sample_addr <= next_sample + SMF_PREV_ADDR_OFFSET; - sample_write_data <= std_logic_vector(resize(prev_sample,WORD_WIDTH)); + sample_valid_in1 <= '1'; + sample_addr1 <= next_sample + SMF_PREV_ADDR_OFFSET; + sample_write_data1 <= std_logic_vector(resize(prev_sample,WORD_WIDTH)); -- Memory Flow Control Guard if (sample_ready_in = '1') then @@ -2981,9 +2890,9 @@ begin -- SET Next Address (Previous Sample) when 9 => -- Remove link to cur_sample - sample_valid_in <= '1'; - sample_addr <= prev_sample + SMF_NEXT_ADDR_OFFSET; - sample_write_data <= std_logic_vector(resize(next_sample,WORD_WIDTH)); + sample_valid_in1 <= '1'; + sample_addr1 <= prev_sample + SMF_NEXT_ADDR_OFFSET; + sample_write_data1 <= std_logic_vector(resize(next_sample,WORD_WIDTH)); -- Memory Flow Control Guard if (sample_ready_in = '1') then @@ -2991,7 +2900,7 @@ begin end if; -- READ Payload Pointer when 10 => - sample_ready_out <= '1'; + sample_ready_out1 <= '1'; -- Memory Flow Control Guard if (sample_valid_out = '1') then @@ -3064,12 +2973,12 @@ begin stale_inst_cnt_next(ind) <= stale_inst_cnt(ind) + 1; end if; - inst_op_start <= '1'; - inst_opcode <= UPDATE_INSTANCE; - inst_r.i <= ind; - inst_r.addr <= inst_data.addr; - inst_r.field_flags <= IMF_SAMPLE_CNT_FLAG; - inst_r.sample_cnt <= inst_data.sample_cnt - 1; + inst_op_start1 <= '1'; + inst_opcode1 <= UPDATE_INSTANCE; + inst_r1.i <= ind; + inst_r1.addr <= inst_data.addr; + inst_r1.field_flags <= IMF_SAMPLE_CNT_FLAG; + inst_r1.sample_cnt <= inst_data.sample_cnt - 1; if (wait_for_sample_removal = '1' or inst_data.status_info(ISI_GENERATE_SAMPLE_FLAG) = '1') then trigger_sample_gen_next <= '1'; @@ -3082,25 +2991,7 @@ begin remove_oldest_sample_next <= '0'; if (is_take = '1') then - -- cur_inst has no more samples in collection - if (si_sample_rank_sig = 0) then - -- Skipped Sample available - if (sample_p2 /= SAMPLE_MEMORY_MAX_ADDRESS) then - cur_sample_next <= sample_p2; - else - cur_sample_next <= sample_p1; - end if; - cur_inst_next <= INSTANCE_MEMORY_MAX_ADDRESS; - sample_p2_next <= SAMPLE_MEMORY_MAX_ADDRESS; - pre_calculated_next <= '0'; - else - cur_sample_next <= sample_p1; - end if; - sample_p1_next <= SAMPLE_MEMORY_MAX_ADDRESS; - sel_sample_next <= SAMPLE_MEMORY_MAX_ADDRESS; - -- Continue Processing - stage_next <= GET_NEXT_SAMPLE; - cnt_next <= 0; + stage_next <= WAIT_READ; elsif (is_lifespan_check = '1') then -- Reached End of Samples if (next_sample = SAMPLE_MEMORY_MAX_ADDRESS) then @@ -3166,25 +3057,25 @@ begin -- NOTE: writer_bitmap is not latched, since the memory process is latching it at the -- same clock cycle. -- Convert Back - inst_r.writer_bitmap <= to_writer_bitmap_array(tmp_bitmap); + inst_r1.writer_bitmap <= to_writer_bitmap_array(tmp_bitmap); -- NOT_ALIVE_NO_WRITERS Transition if (tmp_bitmap = (tmp_bitmap'reverse_range => '0') and inst_data.status_info(ISI_NOT_ALIVE_DISPOSED_FLAG) = '0') then trigger_sample_gen_next <= '1'; - inst_r.status_info <= inst_data.status_info; - inst_r.status_info(ISI_NOT_ALIVE_NO_WRITERS_FLAG) <= '1'; - inst_r.status_info(ISI_GENERATE_SAMPLE_FLAG) <= '1'; - inst_op_start <= '1'; - inst_opcode <= UPDATE_INSTANCE; - inst_r.i <= ind; - inst_r.addr <= inst_data.addr; - inst_r.field_flags <= IMF_STATUS_FLAG or IMF_WRITER_BITMAP_FLAG; + inst_r1.status_info <= inst_data.status_info; + inst_r1.status_info(ISI_NOT_ALIVE_NO_WRITERS_FLAG) <= '1'; + inst_r1.status_info(ISI_GENERATE_SAMPLE_FLAG) <= '1'; + inst_op_start1 <= '1'; + inst_opcode1 <= UPDATE_INSTANCE; + inst_r1.i <= ind; + inst_r1.addr <= inst_data.addr; + inst_r1.field_flags <= IMF_STATUS_FLAG or IMF_WRITER_BITMAP_FLAG; else - inst_op_start <= '1'; - inst_opcode <= UPDATE_INSTANCE; - inst_r.i <= ind; - inst_r.addr <= inst_data.addr; - inst_r.field_flags <= IMF_WRITER_BITMAP_FLAG; + inst_op_start1 <= '1'; + inst_opcode1 <= UPDATE_INSTANCE; + inst_r1.i <= ind; + inst_r1.addr <= inst_data.addr; + inst_r1.field_flags <= IMF_WRITER_BITMAP_FLAG; end if; -- Update Stale Instance Count @@ -3197,19 +3088,19 @@ begin end if; -- GET NEXT INSTANCE when 1 => - inst_op_start <= '1'; - inst_opcode <= GET_NEXT_INSTANCE; - inst_r.i <= ind; - inst_r.addr <= inst_data.addr; - inst_r.field_flags <= IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_WRITER_BITMAP_FLAG; + inst_op_start1 <= '1'; + inst_opcode1 <= GET_NEXT_INSTANCE; + inst_r1.i <= ind; + inst_r1.addr <= inst_data.addr; + inst_r1.field_flags <= IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_WRITER_BITMAP_FLAG; cnt_next <= 0; -- UPDATE INSTANCE -- GET FIRST INSTANCE when 2 => - inst_op_start <= '1'; - inst_opcode <= GET_INSTANCE; - inst_r.i <= ind; - inst_r.addr <= inst_occupied_head(ind); - inst_r.field_flags <= IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_WRITER_BITMAP_FLAG; + inst_op_start1 <= '1'; + inst_opcode1 <= GET_INSTANCE; + inst_r1.i <= ind; + inst_r1.addr <= inst_occupied_head(ind); + inst_r1.field_flags <= IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_WRITER_BITMAP_FLAG; cnt_next <= 0; -- UPDATE INSTANCE when others => null; @@ -3235,10 +3126,10 @@ begin -- Found Stale Instance (No Samples and No Active Writers) if (inst_data.sample_cnt = 0 and inst_data.writer_bitmap = ZERO_WRITER_BITMAP_ARRAY) then -- Remove Stale Instance - inst_op_start <= '1'; - inst_opcode <= REMOVE_INSTANCE; - inst_r.i <= ind; - inst_r.addr <= inst_data.addr; + inst_op_start1 <= '1'; + inst_opcode1 <= REMOVE_INSTANCE; + inst_r1.i <= ind; + inst_r1.addr <= inst_data.addr; -- Update Stale Instance Count stale_inst_cnt_next(ind) <= stale_inst_cnt(ind) - 1; @@ -3246,29 +3137,29 @@ begin else -- Continue Search - inst_op_start <= '1'; - inst_opcode <= GET_NEXT_INSTANCE; - inst_r.i <= ind; - inst_r.addr <= inst_data.addr; - inst_r.field_flags <= IMF_SAMPLE_CNT_FLAG or IMF_WRITER_BITMAP_FLAG; + inst_op_start1 <= '1'; + inst_opcode1 <= GET_NEXT_INSTANCE; + inst_r1.i <= ind; + inst_r1.addr <= inst_data.addr; + inst_r1.field_flags <= IMF_SAMPLE_CNT_FLAG or IMF_WRITER_BITMAP_FLAG; end if; end if; -- Insert New Instance when 1 => - inst_op_start <= '1'; - inst_opcode <= INSERT_INSTANCE; - inst_r.i <= ind; - inst_r.key_hash <= key_hash; - inst_r.status_info <= (ISI_LIVELINESS_FLAG => '1', ISI_NOT_ALIVE_DISPOSED_FLAG => sample_status_info(SSI_DISPOSED_FLAG), others => '0'); - inst_r.sample_cnt <= to_unsigned(1, WORD_WIDTH); + inst_op_start1 <= '1'; + inst_opcode1 <= INSERT_INSTANCE; + inst_r1.i <= ind; + inst_r1.key_hash <= key_hash; + inst_r1.status_info <= (ISI_LIVELINESS_FLAG => '1', ISI_NOT_ALIVE_DISPOSED_FLAG => sample_status_info(SSI_DISPOSED_FLAG), others => '0'); + inst_r1.sample_cnt <= to_unsigned(1, WORD_WIDTH); if (CONFIG_ARRAY_T(ind).TIME_BASED_FILTER_QOS /= DURATION_ZERO) then - inst_r.ignore_deadline <= time + CONFIG_ARRAY_T(ind).TIME_BASED_FILTER_QOS; + inst_r1.ignore_deadline <= time + CONFIG_ARRAY_T(ind).TIME_BASED_FILTER_QOS; else - inst_r.ignore_deadline <= TIME_INVALID; + inst_r1.ignore_deadline <= TIME_INVALID; end if; tmp_bitmap := (others => '0'); tmp_bitmap(writer_id) := '1'; - inst_r.writer_bitmap <= to_writer_bitmap_array(tmp_bitmap); + inst_r1.writer_bitmap <= to_writer_bitmap_array(tmp_bitmap); -- Latch Instance Pointer cur_inst_next <= inst_empty_head(ind); @@ -3292,820 +3183,45 @@ begin null; end case; end if; - when GET_NEXT_SAMPLE => - -- Precondition: cur_sample set, cur_inst set, si_sample_rank_sig set + when WAIT_READ => + if (done_read_success = '1') then + done_dds(ind) <= '1'; + return_code_dds(ind) <= RETCODE_OK; + + -- Reset Data Available Status + status_sig_next(ind) <= status_sig(ind) and (not DATA_AVAILABLE_STATUS); + end if; - case (cnt) is - -- GET Next Sample - when 0 => - sample_valid_in <= '1'; - sample_addr <= cur_sample + SMF_NEXT_ADDR_OFFSET; - sample_read <= '1'; - - -- Memory Control Flow Guard - if (sample_ready_in = '1') then - cnt_next <= cnt + 1; - end if; - -- GET Status Info - when 1 => - sample_valid_in <= '1'; - sample_addr <= cur_sample + SMF_STATUS_INFO_OFFSET; - sample_read <= '1'; - - -- Memory Control Flow Guard - if (sample_ready_in = '1') then - cnt_next <= cnt + 1; - end if; - -- GET Instance Pointer - when 2 => - sample_valid_in <= '1'; - sample_addr <= cur_sample + SMF_INSTANCE_ADDR_OFFSET; - sample_read <= '1'; - - -- Memory Control Flow Guard - if (sample_ready_in = '1') then - cnt_next <= cnt + 1; - end if; - -- READ Next Sample - when 3 => - sample_ready_out <= '1'; - - -- Memory Control Flow Guard - if (sample_valid_out = '1') then - next_sample_next <= resize(unsigned(sample_read_data),SAMPLE_MEMORY_ADDR_WIDTH); - cnt_next <= cnt + 1; - end if; - -- READ Status Info - when 4 => - sample_ready_out <= '1'; - - -- Memory Control Flow Guard - if (sample_valid_out = '1') then - tmp_bool := TRUE; - - -- Check Sample State - case (sample_state) is - when READ_SAMPLE_STATE => - if (sample_read_data(SSI_READ_FLAG) /= '1') then - tmp_bool := FALSE; - end if; - when NOT_READ_SAMPLE_STATE => - if (sample_read_data(SSI_READ_FLAG) /= '0') then - tmp_bool := FALSE; - end if; - when ANY_SAMPLE_STATE => - null; - -- Uknown Sample State - when others => - tmp_bool := FALSE; - end case; - - -- Latch Sample Status Info - sample_status_info_next <= sample_read_data; - - if (sample_read_data(SSI_READ_FLAG) = '1') then - si_sample_state_sig_next <= READ_SAMPLE_STATE; - else - si_sample_state_sig_next <= NOT_READ_SAMPLE_STATE; - end if; - - -- Sample Passes Checks - if (tmp_bool) then - cnt_next <= cnt + 1; - else - -- Sample not in collection, Skip Sample - cnt_next <= 18; -- EXIT STATE - sample_abort_read <= '1'; - end if; - end if; - -- READ Instance Pointer - when 5 => - sample_ready_out <= '1'; - - -- Memory Control Flow Guard - if (sample_valid_out = '1') then - -- Instance pre-selected - if (cur_inst /= INSTANCE_MEMORY_MAX_ADDRESS) then - -- Sample has different Instance - if (cur_inst /= resize(unsigned(sample_read_data),INSTANCE_MEMORY_ADDR_WIDTH)) then - -- Consecutive Instance Sample Order - if (not CONFIG_ARRAY_T(ind).ORDERED_ACCESS or CONFIG_ARRAY_T(ind).PRESENTATION_QOS = INSTANCE_PRESENTATION_QOS or single_instance = '1') then - -- Skip Sample - cnt_next <= 18; -- EXIT STATE - sample_abort_read <= '1'; - -- Latch first skipped Sample - if (sample_p2 = SAMPLE_MEMORY_MAX_ADDRESS) then - sample_p2_next <= cur_sample; - end if; - else - -- Get Instance Data - next_inst_next <= resize(unsigned(sample_read_data),INSTANCE_MEMORY_ADDR_WIDTH); - cnt_next <= cnt + 1; - end if; - else - -- Select Sample - collection_cnt_next <= collection_cnt + 1; - sel_sample_next <= cur_sample; - -- Latch Next Sample (For resume purposes) - sample_p1_next <= next_sample; - - -- First Instance Sample - -- NOTE: This state only enters with a sample rank of 0 and cur_inst set, when the - -- first sample of the instance has not yet been selected - if (si_sample_rank_sig = 0) then - -- Reset - collection_cnt_max_next <= collection_cnt + 1; - else - si_sample_rank_sig_next <= si_sample_rank_sig - 1; - end if; - - -- Skip Instance Operation - cnt_next <= cnt + 3; -- GET TIMESTAMP 1/2 - end if; - else - -- Get Instance Data - next_inst_next <= resize(unsigned(sample_read_data),INSTANCE_MEMORY_ADDR_WIDTH); - cnt_next <= cnt + 1; - end if; - end if; - -- Get Instance Data - when 6 => - -- Memory Operation Guard - if (inst_op_done = '1') then - inst_op_start <= '1'; - inst_opcode <= GET_INSTANCE; - inst_r.i <= ind; - inst_r.addr <= next_inst; - inst_r.field_flags <= IMF_STATUS_FLAG; - cnt_next <= cnt + 1; - end if; - -- Check Instance Data - when 7 => - -- Wait for Instance Data - if (inst_op_done = '1') then - assert (stable(clk, inst_data.i = ind and check_mask(inst_data.field_flags, IMF_STATUS_FLAG))) severity FAILURE; - assert (next_inst = inst_data.addr) severity FAILURE; - - -- DEFAULT - tmp_bool := TRUE; - - -- Check Instance State - case (instance_state) is - when ALIVE_INSTANCE_STATE => - if (inst_data.status_info(ISI_NOT_ALIVE_DISPOSED_FLAG) = '1' or inst_data.status_info(ISI_NOT_ALIVE_NO_WRITERS_FLAG) = '1') then - tmp_bool := FALSE; - end if; - when NOT_ALIVE_DISPOSED_INSTANCE_STATE => - if (inst_data.status_info(ISI_NOT_ALIVE_DISPOSED_FLAG) = '0') then - tmp_bool := FALSE; - end if; - when NOT_ALIVE_NO_WRITERS_INSTANCE_STATE => - if (inst_data.status_info(ISI_NOT_ALIVE_NO_WRITERS_FLAG) = '0') then - tmp_bool := FALSE; - end if; - when NOT_ALIVE_INSTANCE_STATE => - if (inst_data.status_info(ISI_NOT_ALIVE_DISPOSED_FLAG) = '0' and inst_data.status_info(ISI_NOT_ALIVE_NO_WRITERS_FLAG) = '0') then - tmp_bool := FALSE; - end if; - when ANY_INSTANCE_STATE => - null; - when others => - tmp_bool := FALSE; - end case; - - -- Check View State - case (view_state) is - when NEW_VIEW_STATE => - if (inst_data.status_info(ISI_VIEW_FLAG) = '1') then - tmp_bool := FALSE; - end if; - when NOT_NEW_VIEW_STATE => - if (inst_data.status_info(ISI_VIEW_FLAG) = '0') then - tmp_bool := FALSE; - end if; - when ANY_VIEW_STATE => - null; - when others => - tmp_bool := FALSE; - end case; - - -- Check Instance Mark - if (inst_data.status_info(ISI_MARK_FLAG) = '1') then - -- Skip Marked Instance - tmp_bool := FALSE; - end if; - - -- Instance Passes Checks - if (tmp_bool) then - -- Select Sample - collection_cnt_next <= collection_cnt + 1; - collection_cnt_max_next <= collection_cnt + 1; - si_sample_rank_sig_next <= (others => '0'); - cur_inst_next <= next_inst; - sel_sample_next <= cur_sample; - -- Latch Next Sample (For resume purposes) - sample_p1_next <= next_sample; - cnt_next <= cnt + 1; - -- Reset - pre_calculated_next <= '0'; - else - if (CONFIG_ARRAY_T(ind).WITH_KEY) then - -- Skip Sample - cnt_next <= 18; -- EXIT STATE - sample_abort_read <= '1'; - else - -- Instance does not pass Checks - done_dds(ind) <= '1'; - return_code_dds(ind) <= RETCODE_NO_DATA; - stage_next <= IDLE; - end if; - end if; - end if; - -- GET Timestamp 1/2 - when 8 => - sample_valid_in <= '1'; - sample_addr <= cur_sample + SMF_TIMESTAMP_OFFSET; - sample_read <= '1'; - - -- Memory Control Flow Guard - if (sample_ready_in = '1') then - cnt_next <= cnt + 1; - end if; - -- GET Timestamp 2/2 - when 9 => - sample_valid_in <= '1'; - sample_addr <= cur_sample + SMF_TIMESTAMP_OFFSET + 1; - sample_read <= '1'; - - -- Memory Control Flow Guard - if (sample_ready_in = '1') then - cnt_next <= cnt + 1; - end if; - -- GET Payload Pointer - when 10 => - sample_valid_in <= '1'; - sample_addr <= cur_sample + SMF_PAYLOAD_ADDR_OFFSET; - sample_read <= '1'; - - -- Memory Control Flow Guard - if (sample_ready_in = '1') then - cnt_next <= cnt + 1; - end if; - -- GET Disposed Generation Count - when 11 => - sample_valid_in <= '1'; - sample_addr <= cur_sample + SMF_DISPOSED_GEN_CNT_OFFSET; - sample_read <= '1'; - - -- Memory Control Flow Guard - if (sample_ready_in = '1') then - cnt_next <= cnt + 1; - end if; - -- GET No Writers Generation Count - when 12 => - sample_valid_in <= '1'; - sample_addr <= cur_sample + SMF_NO_WRITERS_GEN_CNT_OFFSET; - sample_read <= '1'; - - -- Memory Control Flow Guard - if (sample_ready_in = '1') then - cnt_next <= cnt + 1; - end if; - -- READ Timestamp 1/2 - when 13 => - sample_ready_out <= '1'; - - -- Memory Control Flow Guard - if (sample_valid_out = '1') then - si_source_timestamp_sig_next(0) <= unsigned(sample_read_data); - cnt_next <= cnt + 1; - end if; - -- READ Timestamp 2/2 - when 14 => - sample_ready_out <= '1'; - - -- Memory Control Flow Guard - if (sample_valid_out = '1') then - si_source_timestamp_sig_next(1) <= unsigned(sample_read_data); - cnt_next <= cnt + 1; - end if; - -- READ Payload Pointer - when 15 => - sample_ready_out <= '1'; - - -- Memory Control Flow Guard - if (sample_valid_out = '1') then - -- Latch Payload Address - cur_payload_next <= resize(unsigned(sample_read_data),PAYLOAD_MEMORY_ADDR_WIDTH); - cnt_next <= cnt + 1; - end if; - -- READ Disposed Generation Count - when 16 => - sample_ready_out <= '1'; - - -- Memory Control Flow Guard - if (sample_valid_out = '1') then - si_disposed_generation_count_sig_next <= sample_read_data; - cnt_next <= cnt + 1; - end if; - -- READ No Writers Generation Count - when 17 => - sample_ready_out <= '1'; - - -- Memory Control Flow Guard - if (sample_valid_out = '1') then - si_no_writers_generation_count_sig_next <= sample_read_data; - cur_generation_rank_next <= unsigned(si_disposed_generation_count_sig) + unsigned(sample_read_data); - if (pre_calculated = '0') then - -- Reset - collection_generation_rank_next <= unsigned(si_disposed_generation_count_sig) + unsigned(sample_read_data); - end if; - cnt_next <= cnt + 1; - end if; - -- Exit State - when 18 => - -- Exit Condition (Sample Selected) - if (sel_sample /= SAMPLE_MEMORY_MAX_ADDRESS) then - -- Sample not marked as Read - if (sample_status_info(SSI_READ_FLAG) /= '1') then - -- Mark Sample as Read - sample_valid_in <= '1'; - sample_addr <= cur_sample + SMF_STATUS_INFO_OFFSET; - sample_write_data <= sample_status_info; - sample_write_data(SSI_READ_FLAG) <= '1'; - -- Memory Control Flow Guard - if (sample_ready_in = '1') then - -- Pre-Calculation already done for selected Instance (Or not necessary) - if (pre_calculated = '1' or collection_cnt_max = max_samples_latch or next_sample = SAMPLE_MEMORY_MAX_ADDRESS) then - stage_next <= FINALIZE_SAMPLE_INFO; - cnt_next <= 0; - else - -- Calculate Instance Sample Ranks - cur_sample_next <= next_sample; - stage_next <= PRE_CALCULATE; - cnt_next <= 0; - end if; - end if; - else - -- Pre-Calculation already done for selected Instance (Or not necessary) - if (pre_calculated = '1' or collection_cnt_max = max_samples_latch or next_sample = SAMPLE_MEMORY_MAX_ADDRESS) then - stage_next <= FINALIZE_SAMPLE_INFO; - cnt_next <= 0; - else - -- Calculate Instance Sample Ranks - cur_sample_next <= next_sample; - stage_next <= PRE_CALCULATE; - cnt_next <= 0; - end if; - end if; - - -- First Sample Selected - if (collection_cnt = 1) then - done_dds(ind) <= '1'; - return_code_dds(ind) <= RETCODE_OK; - end if; - else - -- End of Samples - if (next_sample = SAMPLE_MEMORY_MAX_ADDRESS) then - -- Collection Empty - if (collection_cnt = 0) then - -- READ_NEXT_INSTANCE/TAKE_NEXT_INSTANCE Operation - if (CONFIG_ARRAY_T(ind).WITH_KEY and dynamic_next_instance = '1') then - -- NOTE: We selected a compatible instance, but the instance has no compatible samples. - -- Find next compatible instance. - stage_next <= FIND_NEXT_INSTANCE; - cnt_next <= 1; -- GET NEXT INSTANCE - else - done_dds(ind) <= '1'; - return_code_dds(ind) <= RETCODE_NO_DATA; - stage_next <= IDLE; - end if; - else - -- Mark End of Collection - eoc_sig_next <= '1'; - stage_next <= IDLE; - -- Consecutive Instance Sample Order of multiple Instances - if ((not CONFIG_ARRAY_T(ind).ORDERED_ACCESS or CONFIG_ARRAY_T(ind).PRESENTATION_QOS = INSTANCE_PRESENTATION_QOS) and single_instance = '0') then - -- Unmark Instances - unmark_instances_flag_next <= '1'; - end if; - end if; - else - -- Continue Searching - cur_sample_next <= next_sample; - cnt_next <= 0; -- GET NEXT SAMPLE - end if; - end if; - when others => - null; - end case; - when PRE_CALCULATE => - -- Precondition: cur_sample set, cur_inst set + if (unmark_instances_trigger = '1') then + -- Unmark Instances + unmark_instances_flag_next <= '1'; + end if; - case (cnt) is - -- GET Next Sample - when 0 => - sample_valid_in <= '1'; - sample_addr <= cur_sample + SMF_NEXT_ADDR_OFFSET; - sample_read <= '1'; - - -- Memory Control Flow Guard - if (sample_ready_in = '1') then - cnt_next <= cnt + 1; - end if; - -- GET Status Info - when 1 => - sample_valid_in <= '1'; - sample_addr <= cur_sample + SMF_STATUS_INFO_OFFSET; - sample_read <= '1'; - - -- Memory Control Flow Guard - if (sample_ready_in = '1') then - cnt_next <= cnt + 1; - end if; - -- GET Instance Pointer - when 2 => - sample_valid_in <= '1'; - sample_addr <= cur_sample + SMF_INSTANCE_ADDR_OFFSET; - sample_read <= '1'; - - -- Memory Control Flow Guard - if (sample_ready_in = '1') then - cnt_next <= cnt + 1; - end if; - -- GET Disposed Generation Count - when 3 => - sample_valid_in <= '1'; - sample_addr <= cur_sample + SMF_DISPOSED_GEN_CNT_OFFSET; - sample_read <= '1'; - - -- Memory Control Flow Guard - if (sample_ready_in = '1') then - cnt_next <= cnt + 1; - end if; - -- GET No Writers Generation Count - when 4 => - sample_valid_in <= '1'; - sample_addr <= cur_sample + SMF_NO_WRITERS_GEN_CNT_OFFSET; - sample_read <= '1'; - - -- Memory Control Flow Guard - if (sample_ready_in = '1') then - cnt_next <= cnt + 1; - end if; - -- READ Next Sample - when 5 => - sample_ready_out <= '1'; - - -- Memory Control Flow Guard - if (sample_valid_out = '1') then - next_sample_next <= resize(unsigned(sample_read_data),SAMPLE_MEMORY_ADDR_WIDTH); - cnt_next <= cnt + 1; - end if; - -- READ Status Info - when 6 => - sample_ready_out <= '1'; - - -- Memory Control Flow Guard - if (sample_valid_out = '1') then - tmp_bool := TRUE; - - -- Check Sample State - case (sample_state) is - when READ_SAMPLE_STATE => - if (sample_read_data(SSI_READ_FLAG) /= '1') then - tmp_bool := FALSE; - end if; - when NOT_READ_SAMPLE_STATE => - if (sample_read_data(SSI_READ_FLAG) /= '0') then - tmp_bool := FALSE; - end if; - when ANY_SAMPLE_STATE => - null; - -- Uknown Sample State - when others => - tmp_bool := FALSE; - end case; - - -- Sample Passes Checks - if (tmp_bool) then - cnt_next <= cnt + 1; - else - -- Skip Sample - cnt_next <= 12; -- EXIT STATE - sample_abort_read <= '1'; - end if; - end if; - -- READ Instance Pointer - when 7 => - sample_ready_out <= '1'; - - -- Memory Control Flow Guard - if (sample_valid_out = '1') then - -- Same Instance - if (resize(unsigned(sample_read_data),INSTANCE_MEMORY_ADDR_WIDTH) = cur_inst) then - -- Count Sample (No need to check Instance) - collection_cnt_max_next <= collection_cnt_max + 1; - si_sample_rank_sig_next <= si_sample_rank_sig + 1; - - cnt_next <= cnt + 1; - else - assert stable(clk, CONFIG_ARRAY_T(ind).WITH_KEY) severity FAILURE; - - -- Consecutive Instance Sample Order - if (not CONFIG_ARRAY_T(ind).ORDERED_ACCESS or CONFIG_ARRAY_T(ind).PRESENTATION_QOS = INSTANCE_PRESENTATION_QOS or single_instance = '1') then - -- Skip Sample - cnt_next <= 12; -- EXIT STATE - sample_abort_read <= '1'; - else - -- Check New Instance - cnt_next <= cnt + 3; -- GET INSTANCE DATA - sample_abort_read <= '1'; - end if; - end if; - end if; - -- READ Disposed Generation Count - when 8 => - sample_ready_out <= '1'; - - -- Memory Control Flow Guard - if (sample_valid_out = '1') then - -- Calculate highest collection generation rank - collection_generation_rank_next <= unsigned(sample_read_data); - cnt_next <= cnt + 1; - end if; - -- READ No Writers Generation Count - when 9 => - sample_ready_out <= '1'; - - -- Memory Control Flow Guard - if (sample_valid_out = '1') then - -- Calculate highest collection generation rank - collection_generation_rank_next <= collection_generation_rank + unsigned(sample_read_data); - -- Skip Instance Check - cnt_next <= cnt + 3; -- EXIT STATE - end if; - -- Get Instance Data - when 10 => - assert (CONFIG_ARRAY_T(ind).WITH_KEY) severity FAILURE; - - -- Memory Operation Guard - if (inst_op_done = '1') then - inst_op_start <= '1'; - inst_opcode <= GET_INSTANCE; - inst_r.i <= ind; - inst_r.addr <= next_inst; - inst_r.field_flags <= IMF_STATUS_FLAG; - cnt_next <= cnt + 1; - end if; - -- Check Instance Data - when 11 => - assert (CONFIG_ARRAY_T(ind).WITH_KEY) severity FAILURE; - - -- Wait for Instance Data - if (inst_op_done = '1') then - assert stable(clk, inst_data.i = ind and check_mask(inst_data.field_flags, IMF_STATUS_FLAG)) severity FAILURE; - assert (next_inst = inst_data.addr) severity FAILURE; - - -- DEFAULT - tmp_bool := TRUE; - - -- Check Instance State - case (instance_state) is - when ALIVE_INSTANCE_STATE => - if (inst_data.status_info(ISI_NOT_ALIVE_DISPOSED_FLAG) = '1' or inst_data.status_info(ISI_NOT_ALIVE_NO_WRITERS_FLAG) = '1') then - tmp_bool := FALSE; - end if; - when NOT_ALIVE_DISPOSED_INSTANCE_STATE => - if (inst_data.status_info(ISI_NOT_ALIVE_DISPOSED_FLAG) = '0') then - tmp_bool := FALSE; - end if; - when NOT_ALIVE_NO_WRITERS_INSTANCE_STATE => - if (inst_data.status_info(ISI_NOT_ALIVE_NO_WRITERS_FLAG) = '0') then - tmp_bool := FALSE; - end if; - when NOT_ALIVE_INSTANCE_STATE => - if (inst_data.status_info(ISI_NOT_ALIVE_DISPOSED_FLAG) = '0' and inst_data.status_info(ISI_NOT_ALIVE_NO_WRITERS_FLAG) = '0') then - tmp_bool := FALSE; - end if; - when ANY_INSTANCE_STATE => - null; - when others => - tmp_bool := FALSE; - end case; - - -- Check View State - case (view_state) is - when NEW_VIEW_STATE => - if (inst_data.status_info(ISI_VIEW_FLAG) = '1') then - tmp_bool := FALSE; - end if; - when NOT_NEW_VIEW_STATE => - if (inst_data.status_info(ISI_VIEW_FLAG) = '0') then - tmp_bool := FALSE; - end if; - when ANY_VIEW_STATE => - null; - when others => - tmp_bool := FALSE; - end case; - - -- Check Instance Mark - if (inst_data.status_info(ISI_MARK_FLAG) = '1') then - -- Skip Marked Instance - tmp_bool := FALSE; - end if; - - -- Instance passes Checks - if (tmp_bool) then - -- Count Sample - collection_cnt_max_next <= collection_cnt_max + 1; - end if; - cnt_next <= cnt + 1; - end if; - -- Exit State - when 12 => - -- Exit Condition (Reached End of Samples or Collection Fully Precalculated) - if (next_sample = SAMPLE_MEMORY_MAX_ADDRESS or collection_cnt_max = max_samples_latch) then - stage_next <= FINALIZE_SAMPLE_INFO; - cnt_next <= 0; - pre_calculated_next <= '1'; - else - -- Continue with next Sample - cur_sample_next <= next_sample; - cnt_next <= 0; -- GET NEXT SAMPLE - end if; - when others => - null; - end case; - when FINALIZE_SAMPLE_INFO => - -- Precondition: cur_inst set - - case (cnt) is - -- Finalize Sample Info Data - when 0 => - -- Wait for Instance Data - if (inst_op_done = '1') then - -- Instance Data valid - if (inst_data.addr = cur_inst and inst_data.i = ind and check_mask(inst_data.field_flags,IMF_STATUS_FLAG or IMF_KEY_HASH_FLAG or IMF_DISPOSED_CNT_FLAG or IMF_NO_WRITERS_CNT_FLAG)) then - - -- Sample Info View State - if (inst_data.status_info(ISI_VIEW_FLAG) = '0') then - si_view_state_sig_next <= NEW_VIEW_STATE; - else - si_view_state_sig_next <= NOT_NEW_VIEW_STATE; - end if; - - -- Sample Info Instance State - if (inst_data.status_info(ISI_NOT_ALIVE_DISPOSED_FLAG) = '1') then - si_instance_state_sig_next <= NOT_ALIVE_DISPOSED_INSTANCE_STATE; - elsif (inst_data.status_info(ISI_NOT_ALIVE_NO_WRITERS_FLAG) = '1') then - si_instance_state_sig_next <= NOT_ALIVE_NO_WRITERS_INSTANCE_STATE; - else - si_instance_state_sig_next <= ALIVE_INSTANCE_STATE; - end if; - - -- Sample Info Instance Handle - si_instance_handle_sig_next <= inst_data.key_hash; - - -- Sample Info Generation Rank - si_generation_rank_sig_next <= collection_generation_rank - cur_generation_rank; - - -- Sample Info Absolut Generation Rank - -- XXX: Possible Worst Case Path (2 32-bit Operations in same clock) - si_absolute_generation_rank_sig_next <= (inst_data.disposed_gen_cnt + inst_data.no_writers_gen_cnt) - cur_generation_rank; - - -- Sample Info Valid Data - if (cur_payload /= PAYLOAD_MEMORY_MAX_ADDRESS) then - si_valid_data_sig_next <= '1'; - else - si_valid_data_sig_next <= '0'; - end if; - - si_valid_sig_next <= '1'; - cnt_next <= 1; - else - -- Get Instance Data - inst_op_start <= '1'; - inst_opcode <= GET_INSTANCE; - inst_r.i <= ind; - inst_r.addr <= cur_inst; - inst_r.field_flags <= IMF_KEY_HASH_FLAG or IMF_STATUS_FLAG or IMF_DISPOSED_CNT_FLAG or IMF_NO_WRITERS_CNT_FLAG; - end if; - end if; - -- Present Data - when 1 => - -- Synthesis Guard - if (CONFIG_ARRAY_T(ind).DESTINATION_ORDER_QOS = BY_SOURCE_TIMESTAMP_DESTINATION_ORDER_QOS) then - -- Update Last Read Timestamp - if (si_source_timestamp_sig > last_read_ts(ind)) then - last_read_ts_next(ind) <= si_source_timestamp_sig; - end if; - end if; - - -- Reset Data Available Status - status_sig_next(ind) <= status_sig(ind) and (not DATA_AVAILABLE_STATUS); - - -- Wait on User - if (sample_info_ack(ind) = '1') then - -- Sample Data Request - if (get_data_dds(ind) = '1') then - stage_next <= GET_PAYLOAD; - cnt_next <= 0; - else - cnt_next <= 2; - -- Invalidate Data - si_valid_sig_next <= '0'; - end if; - end if; - -- Post-Present Data - when 2 => - -- Memory Operation Guard - if (inst_op_done = '1') then - assert (inst_data.addr /= INSTANCE_MEMORY_MAX_ADDRESS) severity FAILURE; - assert (stable(clk, inst_data.i = ind and check_mask(inst_data.field_flags, IMF_STATUS_FLAG))) severity FAILURE; - -- NOTE: If we have a presentation of consecutive same instance samples of multiple instances, we have to - -- mark the instances we have already handled, in order to prevent the GET_NEXT_SAMPLE state to - -- re-process them. - -- Last Sample of Instance in Collection - if (si_sample_rank_sig = 0) then - inst_op_start <= '1'; - inst_opcode <= UPDATE_INSTANCE; - inst_r.i <= ind; - inst_r.addr <= inst_data.addr; - inst_r.field_flags <= IMF_STATUS_FLAG; - inst_r.status_info <= inst_data.status_info; - - -- Consecutive Instance Sample Order of multiple Instances - if ((not CONFIG_ARRAY_T(ind).ORDERED_ACCESS or CONFIG_ARRAY_T(ind).PRESENTATION_QOS = INSTANCE_PRESENTATION_QOS) and single_instance = '0') then - -- Mark Instance - inst_r.status_info(ISI_MARK_FLAG) <= '1'; - end if; - - -- Instance is NOT_VIEWED and sample is from last generation of Instance - if (inst_data.status_info(ISI_VIEW_FLAG) = '0' and si_absolute_generation_rank_sig = 0) then - -- Mark Instance as VIEWED - inst_r.status_info(ISI_VIEW_FLAG) <= '1'; - end if; - end if; - - -- End of Collection - if (collection_cnt = max_samples_latch or (sample_p1 = SAMPLE_MEMORY_MAX_ADDRESS and sample_p2 = SAMPLE_MEMORY_MAX_ADDRESS) or (si_sample_rank_sig = 0 and single_instance = '1')) then - -- Mark End of Collection - eoc_sig_next <= '1'; - -- Consecutive Instance Sample Order of multiple Instances - if ((not CONFIG_ARRAY_T(ind).ORDERED_ACCESS or CONFIG_ARRAY_T(ind).PRESENTATION_QOS = INSTANCE_PRESENTATION_QOS) and single_instance = '0') then - -- Unmark Instances - unmark_instances_flag_next <= '1'; - end if; - - if (is_take = '1') then - cur_sample_next <= sel_sample; - stage_next <= REMOVE_SAMPLE; - cnt_next <= 0; - is_take_next <= '0'; -- Return to IDLE from REMOVE - else - -- DONE - stage_next <= IDLE; - end if; - else - if (is_take = '1') then - -- Remove Sample - cur_sample_next <= sel_sample; - stage_next <= REMOVE_SAMPLE; - cnt_next <= 0; - else - -- cur_inst has no more samples in collection - if (si_sample_rank_sig = 0) then - -- Skipped Sample available - if (sample_p2 /= SAMPLE_MEMORY_MAX_ADDRESS) then - cur_sample_next <= sample_p2; - else - cur_sample_next <= sample_p1; - end if; - cur_inst_next <= INSTANCE_MEMORY_MAX_ADDRESS; - sample_p2_next <= SAMPLE_MEMORY_MAX_ADDRESS; - pre_calculated_next <= '0'; - else - cur_sample_next <= sample_p1; - end if; - sample_p1_next <= SAMPLE_MEMORY_MAX_ADDRESS; - sel_sample_next <= SAMPLE_MEMORY_MAX_ADDRESS; - -- Continue Processing - stage_next <= GET_NEXT_SAMPLE; - cnt_next <= 0; - end if; - end if; - end if; - when others => - null; - end case; + if (get_payload_trigger = '1') then + sample_status_info_next <= sample_status_info2; + cur_payload_next <= sel_payload; + stage_next <= GET_PAYLOAD; + cnt_next <= 0; + elsif (remove_sample_trigger = '1') then + cur_inst_next <= inst_addr_latch_3; -- cur_inst of read_prc + cur_sample_next <= sample_addr_latch_6; -- sel_sample of read_prc + stage_next <= REMOVE_SAMPLE; + cnt_next <= 0; + elsif (eoc_sig = '1') then + -- DONE + stage_next <= IDLE; + elsif (done_read_error = '1') then + -- DONE + done_dds(ind) <= '1'; + return_code_dds(ind) <= dds_return_code_latch2; + stage_next <= IDLE; + end if; when GET_PAYLOAD => -- Precondition: cur_payload set, sample_status_info set -- NOTE: We are using the Burst Capability of the Memory Controller as a FIFO which we -- fill and the output is directly reading. cnt is switching the memory reading states, - -- cnt2 signals the offset of the payload read, and cnt3 signals how many Bytes have been + -- payload_cnt signals the offset of the payload read, and payload_cnt2 signals how many Bytes have been -- requested but not yet claimed (i.e. how many Bytes are in the FIFO). -- DEFAULT @@ -4117,7 +3233,7 @@ begin -- NOTE: We have to make sure that no pending Reads are in the Memory Controler Buffer, -- else the Next Payload Pointer cannot be read. -- No Pending Reads - if (cnt3 = 0) then + if (payload_cnt2 = 0) then payload_valid_in <= '1'; payload_addr <= cur_payload + PMF_NEXT_ADDR_OFFSET; payload_read <= '1'; @@ -4134,7 +3250,7 @@ begin -- Memory Flow Control Guard if (payload_valid_out = '1') then next_payload_next <= resize(unsigned(payload_read_data),PAYLOAD_MEMORY_ADDR_WIDTH); - cnt2_next <= 1; + payload_cnt_next <= 1; -- Last Payload Slot is unaligned if (resize(unsigned(payload_read_data),PAYLOAD_MEMORY_ADDR_WIDTH) = PAYLOAD_MEMORY_MAX_ADDRESS and sample_status_info(SSI_ALIGNED_FLAG) = '0') then @@ -4166,15 +3282,15 @@ begin -- GET PAYLOAD when 4 => payload_valid_in <= '1'; - payload_addr <= cur_payload + cnt2; + payload_addr <= cur_payload + payload_cnt; payload_read <= '1'; -- Memory Flow Control Guard if (payload_ready_in = '1') then - cnt3_next <= cnt3 + 1; - tmp_bool := TRUE; + payload_cnt2_next <= payload_cnt2 + 1; + tmp_bool := TRUE; -- End of Payload Slot - if (cnt2 = unsigned(long_latch)) then + if (payload_cnt = unsigned(long_latch)) then -- End of Payload if (next_payload = PAYLOAD_MEMORY_MAX_ADDRESS) then -- DONE (Wait for Output to finidh reading) @@ -4185,7 +3301,7 @@ begin cnt_next <= 0; end if; else - cnt2_next <= cnt2 + 1; + payload_cnt_next <= payload_cnt + 1; end if; end if; when others => @@ -4193,14 +3309,14 @@ begin end case; -- Data available for Output - if (cnt3 /= 0) then + if (payload_cnt2 /= 0) then -- Memory Flow Control Guard if (payload_valid_out = '1') then valid_out_dds(ind) <= '1'; data_out_dds(ind) <= payload_read_data; -- End of Payload - if (cnt3 = 1 and cnt = 5) then + if (payload_cnt2 = 1 and cnt = 5) then last_word_out_dds(ind) <= '1'; end if; @@ -4211,254 +3327,19 @@ begin -- on the same clock cycle. -- Increment in same clock cycle if (tmp_bool) then - cnt3_next <= cnt3; -- Override increment + payload_cnt2_next <= payload_cnt2; -- Override increment else - cnt3_next <= cnt3 - 1; - -- Exit Condition - if (cnt3 = 1 and cnt = 5) then - -- Exit - stage_next <= FINALIZE_SAMPLE_INFO; - cnt_next <= 2; - -- Invalidate Data - si_valid_sig_next <= '0'; - end if; + payload_cnt2_next <= payload_cnt2 - 1; + end if; + + -- Exit Condition + if (payload_cnt2 = 1 and cnt = 5) then + stage_next <= WAIT_READ; + get_payload_done <= '1'; end if; end if; end if; end if; - when FIND_NEXT_INSTANCE => - assert (CONFIG_ARRAY_T(ind).WITH_KEY) severity FAILURE; - - -- Wait for Instance Data - if (inst_op_done = '1') then - case (cnt) is - -- GET FIRST INSTANCE - when 0 => - -- NOTE: The Generation Counters are not used directly in this state, but will be needed by the FINALIZE_SAMPLE_INFO state. - inst_op_start <= '1'; - inst_opcode <= GET_INSTANCE; - inst_r.i <= ind; - inst_r.addr <= inst_occupied_head(ind); - inst_r.field_flags <= IMF_STATUS_FLAG or IMF_KEY_HASH_FLAG; - cnt_next <= 2; -- EXIT CONDITION - -- GET NEXT INSTANCE - when 1 => - -- NOTE: The Generation Counters are not used directly in this state, but will be needed by the FINALIZE_SAMPLE_INFO state. - inst_op_start <= '1'; - inst_opcode <= GET_NEXT_INSTANCE; - inst_r.i <= ind; - inst_r.addr <= inst_data.addr; - inst_r.field_flags <= IMF_STATUS_FLAG or IMF_KEY_HASH_FLAG; - cnt_next <= 2; -- EXIT CONDITION - -- EXIT CONDITION - when 2 => - -- No More Instances - if (inst_data.addr = INSTANCE_MEMORY_MAX_ADDRESS) then - -- DONE - done_dds(ind) <= '1'; - return_code_dds(ind) <= RETCODE_NO_DATA; - stage_next <= IDLE; - else - -- Check Instance - cnt_next <= cnt + 1; - end if; - -- KEY HASH 1/4 - when 3 => - assert (inst_data.addr /= INSTANCE_MEMORY_MAX_ADDRESS) severity FAILURE; - assert stable(clk, inst_data.i = ind and check_mask(inst_data.field_flags, IMF_KEY_HASH_FLAG)) severity FAILURE; - - if (unsigned(inst_data.key_hash(0)) > unsigned(key_hash(0))) then - cnt_next <= 7; -- INSTANCE STATUS CHECK - elsif (unsigned(inst_data.key_hash(0)) = unsigned(key_hash(0))) then - -- Continue Check - cnt_next <= cnt + 1; - else -- LESS THAN - cnt_next <= 1; -- GET NEXT INSTANCE - end if; - -- KEY HASH 2/4 - when 4 => - assert (inst_data.addr /= INSTANCE_MEMORY_MAX_ADDRESS) severity FAILURE; - assert stable(clk, inst_data.i = ind and check_mask(inst_data.field_flags, IMF_KEY_HASH_FLAG)) severity FAILURE; - - if (unsigned(inst_data.key_hash(1)) > unsigned(key_hash(1))) then - cnt_next <= 7; -- INSTANCE STATUS CHECK - elsif (unsigned(inst_data.key_hash(1)) = unsigned(key_hash(1))) then - -- Continue Check - cnt_next <= cnt + 1; - else -- LESS THAN - cnt_next <= 1; -- GET NEXT INSTANCE - end if; - -- KEY HASH 3/4 - when 5 => - assert (inst_data.addr /= INSTANCE_MEMORY_MAX_ADDRESS) severity FAILURE; - assert stable(clk, inst_data.i = ind and check_mask(inst_data.field_flags, IMF_KEY_HASH_FLAG)) severity FAILURE; - - if (unsigned(inst_data.key_hash(2)) > unsigned(key_hash(2))) then - cnt_next <= 7; -- INSTANCE STATUS CHECK - elsif (unsigned(inst_data.key_hash(2)) = unsigned(key_hash(2))) then - -- Continue Check - cnt_next <= cnt + 1; - else -- LESS THAN - cnt_next <= 1; -- GET NEXT INSTANCE - end if; - -- KEY HASH 4/4 - when 6 => - assert stable(clk, inst_data.i = ind and check_mask(inst_data.field_flags, IMF_KEY_HASH_FLAG)) severity FAILURE; - - if (unsigned(inst_data.key_hash(3)) > unsigned(key_hash(3))) then - cnt_next <= 7; -- INSTANCE STATUS CHECK - else -- LESS THAN EQUAL - cnt_next <= 1; -- GET NEXT INSTANCE - end if; - -- INSTANCE STATUS CHECK - when 7 => - assert (inst_data.addr /= INSTANCE_MEMORY_MAX_ADDRESS) severity FAILURE; - assert stable(clk, inst_data.i = ind and check_mask(inst_data.field_flags, IMF_STATUS_FLAG)) severity FAILURE; - - -- DEFAULT - tmp_bool := TRUE; - - -- Check Instance State - case (instance_state) is - when ALIVE_INSTANCE_STATE => - if (inst_data.status_info(ISI_NOT_ALIVE_DISPOSED_FLAG) = '1' or inst_data.status_info(ISI_NOT_ALIVE_NO_WRITERS_FLAG) = '1') then - tmp_bool := FALSE; - end if; - when NOT_ALIVE_DISPOSED_INSTANCE_STATE => - if (inst_data.status_info(ISI_NOT_ALIVE_DISPOSED_FLAG) = '0') then - tmp_bool := FALSE; - end if; - when NOT_ALIVE_NO_WRITERS_INSTANCE_STATE => - if (inst_data.status_info(ISI_NOT_ALIVE_NO_WRITERS_FLAG) = '0') then - tmp_bool := FALSE; - end if; - when NOT_ALIVE_INSTANCE_STATE => - if (inst_data.status_info(ISI_NOT_ALIVE_DISPOSED_FLAG) = '0' and inst_data.status_info(ISI_NOT_ALIVE_NO_WRITERS_FLAG) = '0') then - tmp_bool := FALSE; - end if; - when ANY_INSTANCE_STATE => - null; - when others => - tmp_bool := FALSE; - end case; - - -- Check View State - case (view_state) is - when NEW_VIEW_STATE => - if (inst_data.status_info(ISI_VIEW_FLAG) = '1') then - tmp_bool := FALSE; - end if; - when NOT_NEW_VIEW_STATE => - if (inst_data.status_info(ISI_VIEW_FLAG) = '0') then - tmp_bool := FALSE; - end if; - when ANY_VIEW_STATE => - null; - when others => - tmp_bool := FALSE; - end case; - - -- Instance Passes Checks - if (tmp_bool) then - cur_inst_next <= inst_data.addr; - stage_next <= GET_NEXT_SAMPLE; - cnt_next <= 0; - -- Reset - sel_sample_next <= SAMPLE_MEMORY_MAX_ADDRESS; - sample_p1_next <= SAMPLE_MEMORY_MAX_ADDRESS; - sample_p2_next <= SAMPLE_MEMORY_MAX_ADDRESS; - else - cnt_next <= 1; -- GET NEXT INSTANCE - end if; - when others => - null; - end case; - end if; - when CHECK_INSTANCE => - assert (CONFIG_ARRAY_T(ind).WITH_KEY) severity FAILURE; - - -- Wait for Instance Data - if (inst_op_done = '1') then - case (cnt) is - when 0 => - -- NOTE: The Generation Counters are not used directly in this state, but will be needed by the FINALIZE_SAMPLE_INFO state. - inst_op_start <= '1'; - inst_opcode <= SEARCH_INSTANCE; - inst_r.i <= ind; - inst_r.key_hash <= key_hash; - inst_r.field_flags <= IMF_STATUS_FLAG; - cnt_next <= cnt + 1; - when 1 => - -- Instance Found - if (inst_data.addr /= INSTANCE_MEMORY_MAX_ADDRESS) then - assert stable(clk, inst_data.i = ind and check_mask(inst_data.field_flags, IMF_STATUS_FLAG)) severity FAILURE; - - -- DEFAULT - tmp_bool := TRUE; - - -- Check Instance State - case (instance_state) is - when ALIVE_INSTANCE_STATE => - if (inst_data.status_info(ISI_NOT_ALIVE_DISPOSED_FLAG) = '1' or inst_data.status_info(ISI_NOT_ALIVE_NO_WRITERS_FLAG) = '1') then - tmp_bool := FALSE; - end if; - when NOT_ALIVE_DISPOSED_INSTANCE_STATE => - if (inst_data.status_info(ISI_NOT_ALIVE_DISPOSED_FLAG) = '0') then - tmp_bool := FALSE; - end if; - when NOT_ALIVE_NO_WRITERS_INSTANCE_STATE => - if (inst_data.status_info(ISI_NOT_ALIVE_NO_WRITERS_FLAG) = '0') then - tmp_bool := FALSE; - end if; - when NOT_ALIVE_INSTANCE_STATE => - if (inst_data.status_info(ISI_NOT_ALIVE_DISPOSED_FLAG) = '0' and inst_data.status_info(ISI_NOT_ALIVE_NO_WRITERS_FLAG) = '0') then - tmp_bool := FALSE; - end if; - when ANY_INSTANCE_STATE => - null; - when others => - tmp_bool := FALSE; - end case; - - -- Check View State - case (view_state) is - when NEW_VIEW_STATE => - if (inst_data.status_info(ISI_VIEW_FLAG) = '1') then - tmp_bool := FALSE; - end if; - when NOT_NEW_VIEW_STATE => - if (inst_data.status_info(ISI_VIEW_FLAG) = '0') then - tmp_bool := FALSE; - end if; - when ANY_VIEW_STATE => - null; - when others => - tmp_bool := FALSE; - end case; - - -- Instance Passes Checks - if (tmp_bool) then - -- Get Instance Samples - cur_inst_next <= inst_data.addr; - stage_next <= GET_NEXT_SAMPLE; - cnt_next <= 0; - else - -- DONE - done_dds(ind) <= '1'; - return_code_dds(ind) <= RETCODE_NO_DATA; - stage_next <= IDLE; - end if; - else - -- Given Instance does not exist - -- DONE - done_dds(ind) <= '1'; - return_code_dds(ind) <= RETCODE_BAD_PARAMETER; - stage_next <= IDLE; - end if; - when others => - null; - end case; - end if; when CHECK_LIFESPAN => -- Precondition: cur_sample set, @@ -4488,9 +3369,9 @@ begin end if; -- GET NEXT Sample when 2 => - sample_valid_in <= '1'; - sample_addr <= cur_sample + SMF_NEXT_ADDR_OFFSET; - sample_read <= '1'; + sample_valid_in1 <= '1'; + sample_addr1 <= cur_sample + SMF_NEXT_ADDR_OFFSET; + sample_read1 <= '1'; -- Memory Control Flow Guard if (sample_ready_in = '1') then @@ -4498,9 +3379,9 @@ begin end if; -- GET Lifespan 1/2 when 3 => - sample_valid_in <= '1'; - sample_addr <= cur_sample + SMF_LIFESPAN_DEADLINE_OFFSET; - sample_read <= '1'; + sample_valid_in1 <= '1'; + sample_addr1 <= cur_sample + SMF_LIFESPAN_DEADLINE_OFFSET; + sample_read1 <= '1'; -- Memory Control Flow Guard if (sample_ready_in = '1') then @@ -4508,9 +3389,9 @@ begin end if; -- GET Lifespan 2/2 when 4 => - sample_valid_in <= '1'; - sample_addr <= cur_sample + SMF_LIFESPAN_DEADLINE_OFFSET + 1; - sample_read <= '1'; + sample_valid_in1 <= '1'; + sample_addr1 <= cur_sample + SMF_LIFESPAN_DEADLINE_OFFSET + 1; + sample_read1 <= '1'; -- Memory Control Flow Guard if (sample_ready_in = '1') then @@ -4518,9 +3399,9 @@ begin end if; -- GET Instance Pointer when 5 => - sample_valid_in <= '1'; - sample_addr <= cur_sample + SMF_INSTANCE_ADDR_OFFSET; - sample_read <= '1'; + sample_valid_in1 <= '1'; + sample_addr1 <= cur_sample + SMF_INSTANCE_ADDR_OFFSET; + sample_read1 <= '1'; -- Memory Control Flow Guard if (sample_ready_in = '1') then @@ -4528,7 +3409,7 @@ begin end if; -- READ Next Sample when 6 => - sample_ready_out <= '1'; + sample_ready_out1 <= '1'; -- Memory Control Flow Guard if (sample_valid_out = '1') then @@ -4537,7 +3418,7 @@ begin end if; -- READ Lifespan 1/2 when 7 => - sample_ready_out <= '1'; + sample_ready_out1 <= '1'; -- Memory Control Flow Guard if (sample_valid_out = '1') then @@ -4546,7 +3427,7 @@ begin end if; -- READ Lifespan 2/2 when 8 => - sample_ready_out <= '1'; + sample_ready_out1 <= '1'; -- Memory Control Flow Guard if (sample_valid_out = '1') then @@ -4556,7 +3437,7 @@ begin if (tmp_dw /= TIME_INVALID and time >= tmp_dw) then cnt_next <= cnt + 1; else - sample_abort_read <= '1'; + sample_abort_read1 <= '1'; -- Update Check Time if (tmp_dw /= TIME_INVALID and tmp_dw < lifespan_time) then @@ -4578,16 +3459,16 @@ begin when 9 => -- Memory Operation Guard if (inst_op_done = '1') then - sample_ready_out <= '1'; + sample_ready_out1 <= '1'; -- Memory Control Flow Guard if (sample_valid_out = '1') then -- Fetch Instance Data - inst_op_start <= '1'; - inst_opcode <= GET_INSTANCE; - inst_r.i <= ind; - inst_r.addr <= resize(unsigned(sample_read_data),INSTANCE_MEMORY_ADDR_WIDTH); - inst_r.field_flags <= IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_WRITER_BITMAP_FLAG; + inst_op_start1 <= '1'; + inst_opcode1 <= GET_INSTANCE; + inst_r1.i <= ind; + inst_r1.addr <= resize(unsigned(sample_read_data),INSTANCE_MEMORY_ADDR_WIDTH); + inst_r1.field_flags <= IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_WRITER_BITMAP_FLAG; -- Remove Sample stage_next <= REMOVE_SAMPLE; @@ -4603,20 +3484,20 @@ begin case (cnt) is -- GET FIRST INSTANCE when 0 => - inst_op_start <= '1'; - inst_opcode <= GET_INSTANCE; - inst_r.i <= ind; - inst_r.addr <= inst_occupied_head(ind); - inst_r.field_flags <= IMF_STATUS_FLAG; + inst_op_start1 <= '1'; + inst_opcode1 <= GET_INSTANCE; + inst_r1.i <= ind; + inst_r1.addr <= inst_occupied_head(ind); + inst_r1.field_flags <= IMF_STATUS_FLAG; cnt_next <= cnt + 2; -- GET NEXT INSTANCE when 1 => -- Continue - inst_op_start <= '1'; - inst_opcode <= GET_NEXT_INSTANCE; - inst_r.i <= ind; - inst_r.addr <= inst_data.addr; - inst_r.field_flags <= IMF_STATUS_FLAG; + inst_op_start1 <= '1'; + inst_opcode1 <= GET_NEXT_INSTANCE; + inst_r1.i <= ind; + inst_r1.addr <= inst_data.addr; + inst_r1.field_flags <= IMF_STATUS_FLAG; cnt_next <= cnt + 1; -- CHECK INSTANCE when 2 => @@ -4627,11 +3508,11 @@ begin -- Sample needs to be Generated if (inst_data.status_info(ISI_GENERATE_SAMPLE_FLAG) = '1') then -- GET Required Instance Data - inst_op_start <= '1'; - inst_opcode <= GET_INSTANCE; - inst_r.i <= ind; - inst_r.addr <= inst_data.addr; - inst_r.field_flags <= IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_DISPOSED_CNT_FLAG or IMF_NO_WRITERS_CNT_FLAG; + inst_op_start1 <= '1'; + inst_opcode1 <= GET_INSTANCE; + inst_r1.i <= ind; + inst_r1.addr <= inst_data.addr; + inst_r1.field_flags <= IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_DISPOSED_CNT_FLAG or IMF_NO_WRITERS_CNT_FLAG; cnt_next <= cnt + 1; else -- Continue @@ -4659,14 +3540,14 @@ begin remove_oldest_inst_sample_next <= '1'; -- Update Instance - inst_op_start <= '1'; - inst_opcode <= UPDATE_INSTANCE; - inst_r.i <= ind; - inst_r.addr <= inst_data.addr; - inst_r.field_flags <= IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG; - inst_r.sample_cnt <= inst_data.sample_cnt + 1; - inst_r.status_info <= inst_data.status_info; - inst_r.status_info(ISI_GENERATE_SAMPLE_FLAG) <= '0'; + inst_op_start1 <= '1'; + inst_opcode1 <= UPDATE_INSTANCE; + inst_r1.i <= ind; + inst_r1.addr <= inst_data.addr; + inst_r1.field_flags <= IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG; + inst_r1.sample_cnt <= inst_data.sample_cnt + 1; + inst_r1.status_info <= inst_data.status_info; + inst_r1.status_info(ISI_GENERATE_SAMPLE_FLAG) <= '0'; cur_sample_next <= empty_sample_list_head(ind); @@ -4685,14 +3566,14 @@ begin remove_oldest_sample_next <= '1'; -- Update Instance - inst_op_start <= '1'; - inst_opcode <= UPDATE_INSTANCE; - inst_r.i <= ind; - inst_r.addr <= inst_data.addr; - inst_r.field_flags <= IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG; - inst_r.sample_cnt <= inst_data.sample_cnt + 1; - inst_r.status_info <= inst_data.status_info; - inst_r.status_info(ISI_GENERATE_SAMPLE_FLAG) <= '0'; + inst_op_start1 <= '1'; + inst_opcode1 <= UPDATE_INSTANCE; + inst_r1.i <= ind; + inst_r1.addr <= inst_data.addr; + inst_r1.field_flags <= IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG; + inst_r1.sample_cnt <= inst_data.sample_cnt + 1; + inst_r1.status_info <= inst_data.status_info; + inst_r1.status_info(ISI_GENERATE_SAMPLE_FLAG) <= '0'; cur_sample_next <= empty_sample_list_head(ind); cur_inst_next <= inst_data.addr; @@ -4701,14 +3582,14 @@ begin end if; else -- Update Instance - inst_op_start <= '1'; - inst_opcode <= UPDATE_INSTANCE; - inst_r.i <= ind; - inst_r.addr <= inst_data.addr; - inst_r.field_flags <= IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG; - inst_r.sample_cnt <= inst_data.sample_cnt + 1; - inst_r.status_info <= inst_data.status_info; - inst_r.status_info(ISI_GENERATE_SAMPLE_FLAG) <= '0'; + inst_op_start1 <= '1'; + inst_opcode1 <= UPDATE_INSTANCE; + inst_r1.i <= ind; + inst_r1.addr <= inst_data.addr; + inst_r1.field_flags <= IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG; + inst_r1.sample_cnt <= inst_data.sample_cnt + 1; + inst_r1.status_info <= inst_data.status_info; + inst_r1.status_info(ISI_GENERATE_SAMPLE_FLAG) <= '0'; cur_sample_next <= empty_sample_list_head(ind); cur_inst_next <= inst_data.addr; @@ -4886,19 +3767,19 @@ begin end if; -- GET FIRST Instance when 2 => - inst_op_start <= '1'; - inst_opcode <= GET_INSTANCE; - inst_r.i <= ind; - inst_r.addr <= inst_occupied_head(ind); - inst_r.field_flags <= IMF_KEY_HASH_FLAG or IMF_STATUS_FLAG; + inst_op_start1 <= '1'; + inst_opcode1 <= GET_INSTANCE; + inst_r1.i <= ind; + inst_r1.addr <= inst_occupied_head(ind); + inst_r1.field_flags <= IMF_KEY_HASH_FLAG or IMF_STATUS_FLAG; cnt_next <= 4; -- CHECK INSTANCE -- GET NEXT Instance when 3 => - inst_op_start <= '1'; - inst_opcode <= GET_NEXT_INSTANCE; - inst_r.i <= ind; - inst_r.addr <= inst_data.addr; - inst_r.field_flags <= IMF_KEY_HASH_FLAG or IMF_STATUS_FLAG; + inst_op_start1 <= '1'; + inst_opcode1 <= GET_NEXT_INSTANCE; + inst_r1.i <= ind; + inst_r1.addr <= inst_data.addr; + inst_r1.field_flags <= IMF_KEY_HASH_FLAG or IMF_STATUS_FLAG; cnt_next <= 4; -- CHECK INSTANCE -- CHECK Instance when 4 => @@ -4912,13 +3793,13 @@ begin -- Instance received Sample if (inst_data.status_info(ISI_LIVELINESS_FLAG) = '1') then -- Reset Liveliness Flag - inst_op_start <= '1'; - inst_opcode <= UPDATE_INSTANCE; - inst_r.i <= ind; - inst_r.addr <= inst_data.addr; - inst_r.field_flags <= IMF_STATUS_FLAG; - inst_r.status_info <= inst_data.status_info; - inst_r.status_info(ISI_LIVELINESS_FLAG) <= '0'; + inst_op_start1 <= '1'; + inst_opcode1 <= UPDATE_INSTANCE; + inst_r1.i <= ind; + inst_r1.addr <= inst_data.addr; + inst_r1.field_flags <= IMF_STATUS_FLAG; + inst_r1.status_info <= inst_data.status_info; + inst_r1.status_info(ISI_LIVELINESS_FLAG) <= '0'; cnt_next <= 3; -- GET NEXT INSTANCE else -- Update Requested Deadline Missed Status @@ -4937,9 +3818,9 @@ begin case (cnt) is -- SET Previous Pointer when 0 => - sample_valid_in <= '1'; - sample_addr <= cur_sample + SMF_PREV_ADDR_OFFSET; - sample_write_data <= std_logic_vector(resize(prev_sample,WORD_WIDTH)); + sample_valid_in1 <= '1'; + sample_addr1 <= cur_sample + SMF_PREV_ADDR_OFFSET; + sample_write_data1 <= std_logic_vector(resize(prev_sample,WORD_WIDTH)); -- Memory Flow Control Guard if (sample_ready_in = '1') then @@ -4947,12 +3828,12 @@ begin end if; -- SET Next Pointer when 1 => - sample_valid_in <= '1'; - sample_addr <= cur_sample + SMF_NEXT_ADDR_OFFSET; + sample_valid_in1 <= '1'; + sample_addr1 <= cur_sample + SMF_NEXT_ADDR_OFFSET; if (cur_sample = MAX_SAMPLE_ADDRESS(ind)) then - sample_write_data <= std_logic_vector(resize(SAMPLE_MEMORY_MAX_ADDRESS,WORD_WIDTH)); + sample_write_data1 <= std_logic_vector(resize(SAMPLE_MEMORY_MAX_ADDRESS,WORD_WIDTH)); else - sample_write_data <= std_logic_vector(resize(cur_sample + SAMPLE_FRAME_SIZE,WORD_WIDTH)); + sample_write_data1 <= std_logic_vector(resize(cur_sample + SAMPLE_FRAME_SIZE,WORD_WIDTH)); end if; -- Memory Flow Control Guard @@ -5006,6 +3887,1335 @@ begin end case; end process; + read_prc : process (all) + variable tmp_bool : boolean; + alias sample_p1 : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) is sample_addr_latch_4; + alias sample_p1_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) is sample_addr_latch_4_next; + alias sample_p2 : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) is sample_addr_latch_5; + alias sample_p2_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) is sample_addr_latch_5_next; + alias sel_sample : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) is sample_addr_latch_6; + alias sel_sample_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) is sample_addr_latch_6_next; + alias next_sample : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) is sample_addr_latch_7; + alias next_sample_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) is sample_addr_latch_7_next; + alias cur_sample : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) is sample_addr_latch_8; + alias cur_sample_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) is sample_addr_latch_8_next; + alias cur_inst : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0) is inst_addr_latch_3; + alias cur_inst_next : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0) is inst_addr_latch_3_next; + alias next_inst : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0) is inst_addr_latch_4; + alias next_inst_next : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0) is inst_addr_latch_4_next; + begin + -- DEFAULT + read_stage_next <= read_stage; + cnt2_next <= cnt2; + sample_addr_latch_4_next <= sample_addr_latch_4; + sample_addr_latch_5_next <= sample_addr_latch_5; + sample_addr_latch_6_next <= sample_addr_latch_6; + sample_addr_latch_7_next <= sample_addr_latch_7; + sample_addr_latch_8_next <= sample_addr_latch_8; + payload_addr_latch_3_next <= payload_addr_latch_3; + inst_addr_latch_3_next <= inst_addr_latch_3; + inst_addr_latch_4_next <= inst_addr_latch_4; + si_sample_state_sig_next <= si_sample_state_sig; + si_view_state_sig_next <= si_view_state_sig; + si_instance_state_sig_next <= si_instance_state_sig; + si_source_timestamp_sig_next <= si_source_timestamp_sig; + si_instance_handle_sig_next <= si_instance_handle_sig; + si_publication_handle_sig_next <= si_publication_handle_sig; + si_disposed_generation_count_sig_next <= si_disposed_generation_count_sig; + si_no_writers_generation_count_sig_next <= si_no_writers_generation_count_sig; + si_sample_rank_sig_next <= si_sample_rank_sig; + si_generation_rank_sig_next <= si_generation_rank_sig; + si_absolute_generation_rank_sig_next <= si_absolute_generation_rank_sig; + si_valid_data_sig_next <= si_valid_data_sig; + si_valid_sig_next <= si_valid_sig; + eoc_sig_next <= eoc_sig; + collection_cnt_next <= collection_cnt; + collection_cnt_max_next <= collection_cnt_max; + collection_generation_rank_next <= collection_generation_rank; + cur_generation_rank_next <= cur_generation_rank; + is_take_next <= is_take; + single_instance_next <= single_instance; + dynamic_next_instance_next <= dynamic_next_instance; + last_read_ts_next <= last_read_ts; + sample_state_next <= sample_state; + view_state_next <= view_state; + instance_state_next <= instance_state; + max_samples_latch_next <= max_samples_latch; + dds_return_code_latch2_next <= dds_return_code_latch2; + sample_status_info2_next <= sample_status_info2; + instance_handle_next <= instance_handle; + pre_calculated_next <= pre_calculated; + -- DEFAULT Unregistered + inst_op_start2 <= '0'; + inst_opcode2 <= NOP; + inst_r2 <= ZERO_INSTANCE_DATA; + sample_addr2 <= (others => '0'); + sample_read2 <= '0'; + sample_write_data2 <= (others => '0'); + sample_valid_in2 <= '0'; + sample_ready_out2 <= '0'; + sample_abort_read2 <= '0'; + ack_read <= '0'; + done_read_error <= '0'; + done_read_success <= '0'; + unmark_instances_trigger <= '0'; + get_payload_trigger <= '0'; + remove_sample_trigger <= '0'; + + + case (read_stage) is + when IDLE => + if (start_read = '1') then + -- Reset + sel_sample_next <= SAMPLE_MEMORY_MAX_ADDRESS; + sample_p1_next <= SAMPLE_MEMORY_MAX_ADDRESS; + sample_p2_next <= SAMPLE_MEMORY_MAX_ADDRESS; + is_take_next <= '0'; + pre_calculated_next <= '0'; + single_instance_next <= '0'; + dynamic_next_instance_next <= '0'; + collection_cnt_next <= (others => '0'); + collection_cnt_max_next <= (others => '0'); + si_sample_state_sig_next <= (others => '0'); + si_view_state_sig_next <= (others => '0'); + si_instance_state_sig_next <= (others => '0'); + si_source_timestamp_sig_next <= TIME_ZERO; + si_instance_handle_sig_next <= HANDLE_NIL; + si_publication_handle_sig_next <= HANDLE_NIL; + si_sample_rank_sig_next <= (others => '0'); + si_generation_rank_sig_next <= (others => '0'); + si_valid_data_sig_next <= '0'; + si_valid_sig_next <= '0'; + eoc_sig_next <= '0'; + si_absolute_generation_rank_sig_next <= (others => '0'); + si_disposed_generation_count_sig_next <= (others => '0'); + si_no_writers_generation_count_sig_next <= (others => '0'); + -- Latch Input Signals + sample_state_next <= sample_state_dds(ind); + view_state_next <= view_state_dds(ind); + instance_state_next <= instance_state_dds(ind); + max_samples_latch_next <= unsigned(max_samples_dds(ind)); + + case (opcode_dds(ind)) is + when READ => + ack_read <= '1'; + -- No Samples Available + if (oldest_sample(ind) = SAMPLE_MEMORY_MAX_ADDRESS) then + read_stage_next <= DONE; + dds_return_code_latch2_next <= RETCODE_NO_DATA; + else + cur_sample_next <= oldest_sample(ind); + cur_inst_next <= INSTANCE_MEMORY_MAX_ADDRESS; + read_stage_next <= GET_NEXT_SAMPLE; + cnt2_next <= 0; + if (unsigned(max_samples_dds(ind)) = 1) then + single_instance_next <= '1'; + end if; + end if; + when TAKE => + ack_read <= '1'; + -- No Samples Available + if (oldest_sample(ind) = SAMPLE_MEMORY_MAX_ADDRESS) then + read_stage_next <= DONE; + dds_return_code_latch2_next <= RETCODE_NO_DATA; + else + is_take_next <= '1'; + cur_sample_next <= oldest_sample(ind); + cur_inst_next <= INSTANCE_MEMORY_MAX_ADDRESS; + read_stage_next <= GET_NEXT_SAMPLE; + cnt2_next <= 0; + if (unsigned(max_samples_dds(ind)) = 1) then + single_instance_next <= '1'; + end if; + end if; + when READ_NEXT_SAMPLE => + ack_read <= '1'; + -- No Samples Available + if (oldest_sample(ind) = SAMPLE_MEMORY_MAX_ADDRESS) then + read_stage_next <= DONE; + dds_return_code_latch2_next <= RETCODE_NO_DATA; + else + single_instance_next <= '1'; + cur_sample_next <= oldest_sample(ind); + cur_inst_next <= INSTANCE_MEMORY_MAX_ADDRESS; + sample_state_next <= NOT_READ_SAMPLE_STATE; + view_state_next <= ANY_VIEW_STATE; + instance_state_next <= ANY_INSTANCE_STATE; + max_samples_latch_next <= to_unsigned(1, max_samples_latch'length); + read_stage_next <= GET_NEXT_SAMPLE; + cnt2_next <= 0; + end if; + when TAKE_NEXT_SAMPLE => + ack_read <= '1'; + -- No Samples Available + if (oldest_sample(ind) = SAMPLE_MEMORY_MAX_ADDRESS) then + read_stage_next <= DONE; + dds_return_code_latch2_next <= RETCODE_NO_DATA; + else + is_take_next <= '1'; + single_instance_next <= '1'; + cur_sample_next <= oldest_sample(ind); + cur_inst_next <= INSTANCE_MEMORY_MAX_ADDRESS; + sample_state_next <= NOT_READ_SAMPLE_STATE; + view_state_next <= ANY_VIEW_STATE; + instance_state_next <= ANY_INSTANCE_STATE; + max_samples_latch_next <= to_unsigned(1, max_samples_latch'length); + read_stage_next <= GET_NEXT_SAMPLE; + cnt2_next <= 0; + end if; + when READ_INSTANCE => + ack_read <= '1'; + -- Synthesis Guard + if (CONFIG_ARRAY_T(ind).WITH_KEY) then + -- No Samples Available + if (oldest_sample(ind) = SAMPLE_MEMORY_MAX_ADDRESS) then + read_stage_next <= DONE; + dds_return_code_latch2_next <= RETCODE_NO_DATA; + else + single_instance_next <= '1'; + cur_sample_next <= oldest_sample(ind); + instance_handle_next <= instance_handle_dds(ind); + read_stage_next <= CHECK_INSTANCE; + cnt2_next <= 0; + end if; + else + read_stage_next <= DONE; + dds_return_code_latch2_next <= RETCODE_ILLEGAL_OPERATION; + end if; + when TAKE_INSTANCE => + ack_read <= '1'; + -- Synthesis Guard + if (CONFIG_ARRAY_T(ind).WITH_KEY) then + -- No Samples Available + if (oldest_sample(ind) = SAMPLE_MEMORY_MAX_ADDRESS) then + read_stage_next <= DONE; + dds_return_code_latch2_next <= RETCODE_NO_DATA; + else + is_take_next <= '1'; + single_instance_next <= '1'; + cur_sample_next <= oldest_sample(ind); + instance_handle_next <= instance_handle_dds(ind); + read_stage_next <= CHECK_INSTANCE; + cnt2_next <= 0; + end if; + else + read_stage_next <= DONE; + dds_return_code_latch2_next <= RETCODE_ILLEGAL_OPERATION; + end if; + when READ_NEXT_INSTANCE => + ack_read <= '1'; + -- Synthesis Guard + if (CONFIG_ARRAY_T(ind).WITH_KEY) then + -- No Samples Available + if (oldest_sample(ind) = SAMPLE_MEMORY_MAX_ADDRESS) then + read_stage_next <= DONE; + dds_return_code_latch2_next <= RETCODE_NO_DATA; + else + single_instance_next <= '1'; + dynamic_next_instance_next <= '1'; + cur_sample_next <= oldest_sample(ind); + instance_handle_next <= instance_handle_dds(ind); + read_stage_next <= FIND_NEXT_INSTANCE; + cnt2_next <= 0; -- GET FIRST INSTANCE + end if; + else + read_stage_next <= DONE; + dds_return_code_latch2_next <= RETCODE_ILLEGAL_OPERATION; + end if; + when TAKE_NEXT_INSTANCE => + ack_read <= '1'; + -- Synthesis Guard + if (CONFIG_ARRAY_T(ind).WITH_KEY) then + -- No Samples Available + if (oldest_sample(ind) = SAMPLE_MEMORY_MAX_ADDRESS) then + read_stage_next <= DONE; + dds_return_code_latch2_next <= RETCODE_NO_DATA; + else + is_take_next <= '1'; + single_instance_next <= '1'; + dynamic_next_instance_next <= '1'; + cur_sample_next <= oldest_sample(ind); + instance_handle_next <= instance_handle_dds(ind); + read_stage_next <= FIND_NEXT_INSTANCE; + cnt2_next <= 0; -- GET FIRST INSTANCE + end if; + else + read_stage_next <= DONE; + dds_return_code_latch2_next <= RETCODE_ILLEGAL_OPERATION; + end if; + when others => + assert FALSE severity FAILURE; + end case; + end if; + when GET_NEXT_SAMPLE => + -- Precondition: cur_sample set, cur_inst set, si_sample_rank_sig set + + case (cnt2) is + -- GET Next Sample + when 0 => + sample_valid_in2 <= '1'; + sample_addr2 <= cur_sample + SMF_NEXT_ADDR_OFFSET; + sample_read2 <= '1'; + + -- Memory Control Flow Guard + if (sample_ready_in = '1') then + cnt2_next <= cnt2 + 1; + end if; + -- GET Status Info + when 1 => + sample_valid_in2 <= '1'; + sample_addr2 <= cur_sample + SMF_STATUS_INFO_OFFSET; + sample_read2 <= '1'; + + -- Memory Control Flow Guard + if (sample_ready_in = '1') then + cnt2_next <= cnt2 + 1; + end if; + -- GET Instance Pointer + when 2 => + sample_valid_in2 <= '1'; + sample_addr2 <= cur_sample + SMF_INSTANCE_ADDR_OFFSET; + sample_read2 <= '1'; + + -- Memory Control Flow Guard + if (sample_ready_in = '1') then + cnt2_next <= cnt2 + 1; + end if; + -- READ Next Sample + when 3 => + sample_ready_out2 <= '1'; + + -- Memory Control Flow Guard + if (sample_valid_out = '1') then + next_sample_next <= resize(unsigned(sample_read_data),SAMPLE_MEMORY_ADDR_WIDTH); + cnt2_next <= cnt2 + 1; + end if; + -- READ Status Info + when 4 => + sample_ready_out2 <= '1'; + + -- Memory Control Flow Guard + if (sample_valid_out = '1') then + tmp_bool := TRUE; + + -- Check Sample State + case (sample_state) is + when READ_SAMPLE_STATE => + if (sample_read_data(SSI_READ_FLAG) /= '1') then + tmp_bool := FALSE; + end if; + when NOT_READ_SAMPLE_STATE => + if (sample_read_data(SSI_READ_FLAG) /= '0') then + tmp_bool := FALSE; + end if; + when ANY_SAMPLE_STATE => + null; + -- Uknown Sample State + when others => + tmp_bool := FALSE; + end case; + + -- Latch Sample Status Info + sample_status_info2_next <= sample_read_data; + + if (sample_read_data(SSI_READ_FLAG) = '1') then + si_sample_state_sig_next <= READ_SAMPLE_STATE; + else + si_sample_state_sig_next <= NOT_READ_SAMPLE_STATE; + end if; + + -- Sample Passes Checks + if (tmp_bool) then + cnt2_next <= cnt2 + 1; + else + -- Sample not in collection, Skip Sample + cnt2_next <= 18; -- EXIT STATE + sample_abort_read2 <= '1'; + end if; + end if; + -- READ Instance Pointer + when 5 => + sample_ready_out2 <= '1'; + + -- Memory Control Flow Guard + if (sample_valid_out = '1') then + -- Instance pre-selected + if (cur_inst /= INSTANCE_MEMORY_MAX_ADDRESS) then + -- Sample has different Instance + if (cur_inst /= resize(unsigned(sample_read_data),INSTANCE_MEMORY_ADDR_WIDTH)) then + -- Consecutive Instance Sample Order + if (not CONFIG_ARRAY_T(ind).ORDERED_ACCESS or CONFIG_ARRAY_T(ind).PRESENTATION_QOS = INSTANCE_PRESENTATION_QOS or single_instance = '1') then + -- Skip Sample + cnt2_next <= 18; -- EXIT STATE + sample_abort_read2 <= '1'; + -- Latch first skipped Sample + if (sample_p2 = SAMPLE_MEMORY_MAX_ADDRESS) then + sample_p2_next <= cur_sample; + end if; + else + -- Get Instance Data + next_inst_next <= resize(unsigned(sample_read_data),INSTANCE_MEMORY_ADDR_WIDTH); + cnt2_next <= cnt2 + 1; + end if; + else + -- Select Sample + collection_cnt_next <= collection_cnt + 1; + sel_sample_next <= cur_sample; + -- Latch Next Sample (For resume purposes) + sample_p1_next <= next_sample; + + -- First Instance Sample + -- NOTE: This state only enters with a sample rank of 0 and cur_inst set, when the + -- first sample of the instance has not yet been selected + if (si_sample_rank_sig = 0) then + -- Reset + collection_cnt_max_next <= collection_cnt + 1; + else + si_sample_rank_sig_next <= si_sample_rank_sig - 1; + end if; + + -- Skip Instance Operation + cnt2_next <= cnt2 + 3; -- GET TIMESTAMP 1/2 + end if; + else + -- Get Instance Data + next_inst_next <= resize(unsigned(sample_read_data),INSTANCE_MEMORY_ADDR_WIDTH); + cnt2_next <= cnt2 + 1; + end if; + end if; + -- Get Instance Data + when 6 => + -- Memory Operation Guard + if (inst_op_done = '1') then + inst_op_start2 <= '1'; + inst_opcode2 <= GET_INSTANCE; + inst_r2.i <= ind; + inst_r2.addr <= next_inst; + inst_r2.field_flags <= IMF_STATUS_FLAG; + cnt2_next <= cnt2 + 1; + end if; + -- Check Instance Data + when 7 => + -- Wait for Instance Data + if (inst_op_done = '1') then + assert (stable(clk, inst_data.i = ind and check_mask(inst_data.field_flags, IMF_STATUS_FLAG))) severity FAILURE; + assert (next_inst = inst_data.addr) severity FAILURE; + + -- DEFAULT + tmp_bool := TRUE; + + -- Check Instance State + case (instance_state) is + when ALIVE_INSTANCE_STATE => + if (inst_data.status_info(ISI_NOT_ALIVE_DISPOSED_FLAG) = '1' or inst_data.status_info(ISI_NOT_ALIVE_NO_WRITERS_FLAG) = '1') then + tmp_bool := FALSE; + end if; + when NOT_ALIVE_DISPOSED_INSTANCE_STATE => + if (inst_data.status_info(ISI_NOT_ALIVE_DISPOSED_FLAG) = '0') then + tmp_bool := FALSE; + end if; + when NOT_ALIVE_NO_WRITERS_INSTANCE_STATE => + if (inst_data.status_info(ISI_NOT_ALIVE_NO_WRITERS_FLAG) = '0') then + tmp_bool := FALSE; + end if; + when NOT_ALIVE_INSTANCE_STATE => + if (inst_data.status_info(ISI_NOT_ALIVE_DISPOSED_FLAG) = '0' and inst_data.status_info(ISI_NOT_ALIVE_NO_WRITERS_FLAG) = '0') then + tmp_bool := FALSE; + end if; + when ANY_INSTANCE_STATE => + null; + when others => + tmp_bool := FALSE; + end case; + + -- Check View State + case (view_state) is + when NEW_VIEW_STATE => + if (inst_data.status_info(ISI_VIEW_FLAG) = '1') then + tmp_bool := FALSE; + end if; + when NOT_NEW_VIEW_STATE => + if (inst_data.status_info(ISI_VIEW_FLAG) = '0') then + tmp_bool := FALSE; + end if; + when ANY_VIEW_STATE => + null; + when others => + tmp_bool := FALSE; + end case; + + -- Check Instance Mark + if (inst_data.status_info(ISI_MARK_FLAG) = '1') then + -- Skip Marked Instance + tmp_bool := FALSE; + end if; + + -- Instance Passes Checks + if (tmp_bool) then + -- Select Sample + collection_cnt_next <= collection_cnt + 1; + collection_cnt_max_next <= collection_cnt + 1; + si_sample_rank_sig_next <= (others => '0'); + cur_inst_next <= next_inst; + sel_sample_next <= cur_sample; + -- Latch Next Sample (For resume purposes) + sample_p1_next <= next_sample; + cnt2_next <= cnt2 + 1; + -- Reset + pre_calculated_next <= '0'; + else + if (CONFIG_ARRAY_T(ind).WITH_KEY) then + -- Skip Sample + cnt2_next <= 18; -- EXIT STATE + sample_abort_read2 <= '1'; + else + -- Instance does not pass Checks + dds_return_code_latch2_next <= RETCODE_NO_DATA; + read_stage_next <= DONE; + end if; + end if; + end if; + -- GET Timestamp 1/2 + when 8 => + sample_valid_in2 <= '1'; + sample_addr2 <= cur_sample + SMF_TIMESTAMP_OFFSET; + sample_read2 <= '1'; + + -- Memory Control Flow Guard + if (sample_ready_in = '1') then + cnt2_next <= cnt2 + 1; + end if; + -- GET Timestamp 2/2 + when 9 => + sample_valid_in2 <= '1'; + sample_addr2 <= cur_sample + SMF_TIMESTAMP_OFFSET + 1; + sample_read2 <= '1'; + + -- Memory Control Flow Guard + if (sample_ready_in = '1') then + cnt2_next <= cnt2 + 1; + end if; + -- GET Payload Pointer + when 10 => + sample_valid_in2 <= '1'; + sample_addr2 <= cur_sample + SMF_PAYLOAD_ADDR_OFFSET; + sample_read2 <= '1'; + + -- Memory Control Flow Guard + if (sample_ready_in = '1') then + cnt2_next <= cnt2 + 1; + end if; + -- GET Disposed Generation Count + when 11 => + sample_valid_in2 <= '1'; + sample_addr2 <= cur_sample + SMF_DISPOSED_GEN_CNT_OFFSET; + sample_read2 <= '1'; + + -- Memory Control Flow Guard + if (sample_ready_in = '1') then + cnt2_next <= cnt2 + 1; + end if; + -- GET No Writers Generation Count + when 12 => + sample_valid_in2 <= '1'; + sample_addr2 <= cur_sample + SMF_NO_WRITERS_GEN_CNT_OFFSET; + sample_read2 <= '1'; + + -- Memory Control Flow Guard + if (sample_ready_in = '1') then + cnt2_next <= cnt2 + 1; + end if; + -- READ Timestamp 1/2 + when 13 => + sample_ready_out2 <= '1'; + + -- Memory Control Flow Guard + if (sample_valid_out = '1') then + si_source_timestamp_sig_next(0) <= unsigned(sample_read_data); + cnt2_next <= cnt2 + 1; + end if; + -- READ Timestamp 2/2 + when 14 => + sample_ready_out2 <= '1'; + + -- Memory Control Flow Guard + if (sample_valid_out = '1') then + si_source_timestamp_sig_next(1) <= unsigned(sample_read_data); + cnt2_next <= cnt2 + 1; + end if; + -- READ Payload Pointer + when 15 => + sample_ready_out2 <= '1'; + + -- Memory Control Flow Guard + if (sample_valid_out = '1') then + -- Latch Payload Address + sel_payload_next <= resize(unsigned(sample_read_data),PAYLOAD_MEMORY_ADDR_WIDTH); + cnt2_next <= cnt2 + 1; + end if; + -- READ Disposed Generation Count + when 16 => + sample_ready_out2 <= '1'; + + -- Memory Control Flow Guard + if (sample_valid_out = '1') then + si_disposed_generation_count_sig_next <= sample_read_data; + cnt2_next <= cnt2 + 1; + end if; + -- READ No Writers Generation Count + when 17 => + sample_ready_out2 <= '1'; + + -- Memory Control Flow Guard + if (sample_valid_out = '1') then + si_no_writers_generation_count_sig_next <= sample_read_data; + cur_generation_rank_next <= unsigned(si_disposed_generation_count_sig) + unsigned(sample_read_data); + if (pre_calculated = '0') then + -- Reset + collection_generation_rank_next <= unsigned(si_disposed_generation_count_sig) + unsigned(sample_read_data); + end if; + cnt2_next <= cnt2 + 1; + end if; + -- Exit State + when 18 => + -- Exit Condition (Sample Selected) + if (sel_sample /= SAMPLE_MEMORY_MAX_ADDRESS) then + -- Sample not marked as Read + if (sample_status_info2(SSI_READ_FLAG) /= '1') then + -- Mark Sample as Read + sample_valid_in2 <= '1'; + sample_addr2 <= cur_sample + SMF_STATUS_INFO_OFFSET; + sample_write_data2 <= sample_status_info2; + sample_write_data2(SSI_READ_FLAG) <= '1'; + -- Memory Control Flow Guard + if (sample_ready_in = '1') then + -- Pre-Calculation already done for selected Instance (Or not necessary) + if (pre_calculated = '1' or collection_cnt_max = max_samples_latch or next_sample = SAMPLE_MEMORY_MAX_ADDRESS) then + read_stage_next <= FINALIZE_SAMPLE_INFO; + cnt2_next <= 0; + else + -- Calculate Instance Sample Ranks + cur_sample_next <= next_sample; + read_stage_next <= PRE_CALCULATE; + cnt2_next <= 0; + end if; + end if; + else + -- Pre-Calculation already done for selected Instance (Or not necessary) + if (pre_calculated = '1' or collection_cnt_max = max_samples_latch or next_sample = SAMPLE_MEMORY_MAX_ADDRESS) then + read_stage_next <= FINALIZE_SAMPLE_INFO; + cnt2_next <= 0; + else + -- Calculate Instance Sample Ranks + cur_sample_next <= next_sample; + read_stage_next <= PRE_CALCULATE; + cnt2_next <= 0; + end if; + end if; + + -- First Sample Selected + if (collection_cnt = 1) then + done_read_success <= '1'; + end if; + else + -- End of Samples + if (next_sample = SAMPLE_MEMORY_MAX_ADDRESS) then + -- Collection Empty + if (collection_cnt = 0) then + -- READ_NEXT_INSTANCE/TAKE_NEXT_INSTANCE Operation + if (CONFIG_ARRAY_T(ind).WITH_KEY and dynamic_next_instance = '1') then + -- NOTE: We selected a compatible instance, but the instance has no compatible samples. + -- Find next compatible instance. + read_stage_next <= FIND_NEXT_INSTANCE; + cnt2_next <= 1; -- GET NEXT INSTANCE + else + dds_return_code_latch2_next <= RETCODE_NO_DATA; + read_stage_next <= DONE; + end if; + else + -- Mark End of Collection + eoc_sig_next <= '1'; + read_stage_next <= IDLE; + -- Consecutive Instance Sample Order of multiple Instances + if ((not CONFIG_ARRAY_T(ind).ORDERED_ACCESS or CONFIG_ARRAY_T(ind).PRESENTATION_QOS = INSTANCE_PRESENTATION_QOS) and single_instance = '0') then + unmark_instances_trigger <= '1'; + end if; + end if; + else + -- Continue Searching + cur_sample_next <= next_sample; + cnt2_next <= 0; -- GET NEXT SAMPLE + end if; + end if; + when others => + null; + end case; + when PRE_CALCULATE => + -- Precondition: cur_sample set, cur_inst set + + case (cnt2) is + -- GET Next Sample + when 0 => + sample_valid_in2 <= '1'; + sample_addr2 <= cur_sample + SMF_NEXT_ADDR_OFFSET; + sample_read2 <= '1'; + + -- Memory Control Flow Guard + if (sample_ready_in = '1') then + cnt2_next <= cnt2 + 1; + end if; + -- GET Status Info + when 1 => + sample_valid_in2 <= '1'; + sample_addr2 <= cur_sample + SMF_STATUS_INFO_OFFSET; + sample_read2 <= '1'; + + -- Memory Control Flow Guard + if (sample_ready_in = '1') then + cnt2_next <= cnt2 + 1; + end if; + -- GET Instance Pointer + when 2 => + sample_valid_in2 <= '1'; + sample_addr2 <= cur_sample + SMF_INSTANCE_ADDR_OFFSET; + sample_read2 <= '1'; + + -- Memory Control Flow Guard + if (sample_ready_in = '1') then + cnt2_next <= cnt2 + 1; + end if; + -- GET Disposed Generation Count + when 3 => + sample_valid_in2 <= '1'; + sample_addr2 <= cur_sample + SMF_DISPOSED_GEN_CNT_OFFSET; + sample_read2 <= '1'; + + -- Memory Control Flow Guard + if (sample_ready_in = '1') then + cnt2_next <= cnt2 + 1; + end if; + -- GET No Writers Generation Count + when 4 => + sample_valid_in2 <= '1'; + sample_addr2 <= cur_sample + SMF_NO_WRITERS_GEN_CNT_OFFSET; + sample_read2 <= '1'; + + -- Memory Control Flow Guard + if (sample_ready_in = '1') then + cnt2_next <= cnt2 + 1; + end if; + -- READ Next Sample + when 5 => + sample_ready_out2 <= '1'; + + -- Memory Control Flow Guard + if (sample_valid_out = '1') then + next_sample_next <= resize(unsigned(sample_read_data),SAMPLE_MEMORY_ADDR_WIDTH); + cnt2_next <= cnt2 + 1; + end if; + -- READ Status Info + when 6 => + sample_ready_out2 <= '1'; + + -- Memory Control Flow Guard + if (sample_valid_out = '1') then + tmp_bool := TRUE; + + -- Check Sample State + case (sample_state) is + when READ_SAMPLE_STATE => + if (sample_read_data(SSI_READ_FLAG) /= '1') then + tmp_bool := FALSE; + end if; + when NOT_READ_SAMPLE_STATE => + if (sample_read_data(SSI_READ_FLAG) /= '0') then + tmp_bool := FALSE; + end if; + when ANY_SAMPLE_STATE => + null; + -- Uknown Sample State + when others => + tmp_bool := FALSE; + end case; + + -- Sample Passes Checks + if (tmp_bool) then + cnt2_next <= cnt2 + 1; + else + -- Skip Sample + cnt2_next <= 12; -- EXIT STATE + sample_abort_read2 <= '1'; + end if; + end if; + -- READ Instance Pointer + when 7 => + sample_ready_out2 <= '1'; + + -- Memory Control Flow Guard + if (sample_valid_out = '1') then + -- Same Instance + if (resize(unsigned(sample_read_data),INSTANCE_MEMORY_ADDR_WIDTH) = cur_inst) then + -- Count Sample (No need to check Instance) + collection_cnt_max_next <= collection_cnt_max + 1; + si_sample_rank_sig_next <= si_sample_rank_sig + 1; + + cnt2_next <= cnt2 + 1; + else + assert stable(clk, CONFIG_ARRAY_T(ind).WITH_KEY) severity FAILURE; + + -- Consecutive Instance Sample Order + if (not CONFIG_ARRAY_T(ind).ORDERED_ACCESS or CONFIG_ARRAY_T(ind).PRESENTATION_QOS = INSTANCE_PRESENTATION_QOS or single_instance = '1') then + -- Skip Sample + cnt2_next <= 12; -- EXIT STATE + sample_abort_read2 <= '1'; + else + -- Check New Instance + cnt2_next <= cnt2 + 3; -- GET INSTANCE DATA + sample_abort_read2 <= '1'; + end if; + end if; + end if; + -- READ Disposed Generation Count + when 8 => + sample_ready_out2 <= '1'; + + -- Memory Control Flow Guard + if (sample_valid_out = '1') then + -- Calculate highest collection generation rank + collection_generation_rank_next <= unsigned(sample_read_data); + cnt2_next <= cnt2 + 1; + end if; + -- READ No Writers Generation Count + when 9 => + sample_ready_out2 <= '1'; + + -- Memory Control Flow Guard + if (sample_valid_out = '1') then + -- Calculate highest collection generation rank + collection_generation_rank_next <= collection_generation_rank + unsigned(sample_read_data); + -- Skip Instance Check + cnt2_next <= cnt2 + 3; -- EXIT STATE + end if; + -- Get Instance Data + when 10 => + assert (CONFIG_ARRAY_T(ind).WITH_KEY) severity FAILURE; + + -- Memory Operation Guard + if (inst_op_done = '1') then + inst_op_start2 <= '1'; + inst_opcode2 <= GET_INSTANCE; + inst_r2.i <= ind; + inst_r2.addr <= next_inst; + inst_r2.field_flags <= IMF_STATUS_FLAG; + cnt2_next <= cnt2 + 1; + end if; + -- Check Instance Data + when 11 => + assert (CONFIG_ARRAY_T(ind).WITH_KEY) severity FAILURE; + + -- Wait for Instance Data + if (inst_op_done = '1') then + assert stable(clk, inst_data.i = ind and check_mask(inst_data.field_flags, IMF_STATUS_FLAG)) severity FAILURE; + assert (next_inst = inst_data.addr) severity FAILURE; + + -- DEFAULT + tmp_bool := TRUE; + + -- Check Instance State + case (instance_state) is + when ALIVE_INSTANCE_STATE => + if (inst_data.status_info(ISI_NOT_ALIVE_DISPOSED_FLAG) = '1' or inst_data.status_info(ISI_NOT_ALIVE_NO_WRITERS_FLAG) = '1') then + tmp_bool := FALSE; + end if; + when NOT_ALIVE_DISPOSED_INSTANCE_STATE => + if (inst_data.status_info(ISI_NOT_ALIVE_DISPOSED_FLAG) = '0') then + tmp_bool := FALSE; + end if; + when NOT_ALIVE_NO_WRITERS_INSTANCE_STATE => + if (inst_data.status_info(ISI_NOT_ALIVE_NO_WRITERS_FLAG) = '0') then + tmp_bool := FALSE; + end if; + when NOT_ALIVE_INSTANCE_STATE => + if (inst_data.status_info(ISI_NOT_ALIVE_DISPOSED_FLAG) = '0' and inst_data.status_info(ISI_NOT_ALIVE_NO_WRITERS_FLAG) = '0') then + tmp_bool := FALSE; + end if; + when ANY_INSTANCE_STATE => + null; + when others => + tmp_bool := FALSE; + end case; + + -- Check View State + case (view_state) is + when NEW_VIEW_STATE => + if (inst_data.status_info(ISI_VIEW_FLAG) = '1') then + tmp_bool := FALSE; + end if; + when NOT_NEW_VIEW_STATE => + if (inst_data.status_info(ISI_VIEW_FLAG) = '0') then + tmp_bool := FALSE; + end if; + when ANY_VIEW_STATE => + null; + when others => + tmp_bool := FALSE; + end case; + + -- Check Instance Mark + if (inst_data.status_info(ISI_MARK_FLAG) = '1') then + -- Skip Marked Instance + tmp_bool := FALSE; + end if; + + -- Instance passes Checks + if (tmp_bool) then + -- Count Sample + collection_cnt_max_next <= collection_cnt_max + 1; + end if; + cnt2_next <= cnt2 + 1; + end if; + -- Exit State + when 12 => + -- Exit Condition (Reached End of Samples or Collection Fully Precalculated) + if (next_sample = SAMPLE_MEMORY_MAX_ADDRESS or collection_cnt_max = max_samples_latch) then + read_stage_next <= FINALIZE_SAMPLE_INFO; + cnt2_next <= 0; + pre_calculated_next <= '1'; + else + -- Continue with next Sample + cur_sample_next <= next_sample; + cnt2_next <= 0; -- GET NEXT SAMPLE + end if; + when others => + null; + end case; + when FINALIZE_SAMPLE_INFO => + -- Precondition: cur_inst set + + case (cnt2) is + -- Finalize Sample Info Data + when 0 => + -- Wait for Instance Data + if (inst_op_done = '1') then + -- Instance Data valid + if (inst_data.addr = cur_inst and inst_data.i = ind and check_mask(inst_data.field_flags,IMF_STATUS_FLAG or IMF_KEY_HASH_FLAG or IMF_DISPOSED_CNT_FLAG or IMF_NO_WRITERS_CNT_FLAG)) then + + -- Sample Info View State + if (inst_data.status_info(ISI_VIEW_FLAG) = '0') then + si_view_state_sig_next <= NEW_VIEW_STATE; + else + si_view_state_sig_next <= NOT_NEW_VIEW_STATE; + end if; + + -- Sample Info Instance State + if (inst_data.status_info(ISI_NOT_ALIVE_DISPOSED_FLAG) = '1') then + si_instance_state_sig_next <= NOT_ALIVE_DISPOSED_INSTANCE_STATE; + elsif (inst_data.status_info(ISI_NOT_ALIVE_NO_WRITERS_FLAG) = '1') then + si_instance_state_sig_next <= NOT_ALIVE_NO_WRITERS_INSTANCE_STATE; + else + si_instance_state_sig_next <= ALIVE_INSTANCE_STATE; + end if; + + -- Sample Info Instance Handle + si_instance_handle_sig_next <= inst_data.key_hash; + + -- Sample Info Generation Rank + si_generation_rank_sig_next <= collection_generation_rank - cur_generation_rank; + + -- Sample Info Absolut Generation Rank + -- XXX: Possible Worst Case Path (2 32-bit Operations in same clock) + si_absolute_generation_rank_sig_next <= (inst_data.disposed_gen_cnt + inst_data.no_writers_gen_cnt) - cur_generation_rank; + + -- Sample Info Valid Data + if (sel_payload /= PAYLOAD_MEMORY_MAX_ADDRESS) then + si_valid_data_sig_next <= '1'; + else + si_valid_data_sig_next <= '0'; + end if; + + si_valid_sig_next <= '1'; + cnt2_next <= 1; + else + -- Get Instance Data + inst_op_start2 <= '1'; + inst_opcode2 <= GET_INSTANCE; + inst_r2.i <= ind; + inst_r2.addr <= cur_inst; + inst_r2.field_flags <= IMF_KEY_HASH_FLAG or IMF_STATUS_FLAG or IMF_DISPOSED_CNT_FLAG or IMF_NO_WRITERS_CNT_FLAG; + end if; + end if; + -- Present Data + when 1 => + -- Synthesis Guard + if (CONFIG_ARRAY_T(ind).DESTINATION_ORDER_QOS = BY_SOURCE_TIMESTAMP_DESTINATION_ORDER_QOS) then + -- Update Last Read Timestamp + if (si_source_timestamp_sig > last_read_ts(ind)) then + last_read_ts_next(ind) <= si_source_timestamp_sig; + end if; + end if; + + -- Wait on User + if (sample_info_ack(ind) = '1') then + -- Sample Data Request + if (si_valid_data_sig = '1' and get_data_dds(ind) = '1') then + get_payload_trigger <= '1'; + read_stage_next <= WAIT_PAYLOAD; + else + cnt2_next <= 2; + -- Invalidate Data + si_valid_sig_next <= '0'; + end if; + end if; + -- Post-Present Data + when 2 => + -- Memory Operation Guard + if (inst_op_done = '1') then + assert (inst_data.addr /= INSTANCE_MEMORY_MAX_ADDRESS) severity FAILURE; + assert (stable(clk, inst_data.i = ind and check_mask(inst_data.field_flags, IMF_STATUS_FLAG))) severity FAILURE; + -- NOTE: If we have a presentation of consecutive same instance samples of multiple instances, we have to + -- mark the instances we have already handled, in order to prevent the GET_NEXT_SAMPLE state to + -- re-process them. + -- Last Sample of Instance in Collection + if (si_sample_rank_sig = 0) then + inst_op_start2 <= '1'; + inst_opcode2 <= UPDATE_INSTANCE; + inst_r2.i <= ind; + inst_r2.addr <= inst_data.addr; + inst_r2.field_flags <= IMF_STATUS_FLAG; + inst_r2.status_info <= inst_data.status_info; + + -- Consecutive Instance Sample Order of multiple Instances + if ((not CONFIG_ARRAY_T(ind).ORDERED_ACCESS or CONFIG_ARRAY_T(ind).PRESENTATION_QOS = INSTANCE_PRESENTATION_QOS) and single_instance = '0') then + -- Mark Instance + inst_r2.status_info(ISI_MARK_FLAG) <= '1'; + end if; + + -- Instance is NOT_VIEWED and sample is from last generation of Instance + if (inst_data.status_info(ISI_VIEW_FLAG) = '0' and si_absolute_generation_rank_sig = 0) then + -- Mark Instance as VIEWED + inst_r2.status_info(ISI_VIEW_FLAG) <= '1'; + end if; + end if; + + -- End of Collection + if (collection_cnt = max_samples_latch or (sample_p1 = SAMPLE_MEMORY_MAX_ADDRESS and sample_p2 = SAMPLE_MEMORY_MAX_ADDRESS) or (si_sample_rank_sig = 0 and single_instance = '1')) then + -- Mark End of Collection + eoc_sig_next <= '1'; + -- Consecutive Instance Sample Order of multiple Instances + if ((not CONFIG_ARRAY_T(ind).ORDERED_ACCESS or CONFIG_ARRAY_T(ind).PRESENTATION_QOS = INSTANCE_PRESENTATION_QOS) and single_instance = '0') then + unmark_instances_trigger <= '1'; + end if; + + if (is_take = '1') then + -- Remove Sample + remove_sample_trigger <= '1'; + read_stage_next <= IDLE; + is_take_next <= '0'; -- Return to IDLE from REMOVE + else + -- DONE + read_stage_next <= IDLE; + end if; + else + if (is_take = '1') then + -- Remove Sample + remove_sample_trigger <= '1'; + read_stage_next <= WAIT_REMOVE; + else + -- cur_inst has no more samples in collection + if (si_sample_rank_sig = 0) then + -- Skipped Sample available + if (sample_p2 /= SAMPLE_MEMORY_MAX_ADDRESS) then + cur_sample_next <= sample_p2; + else + cur_sample_next <= sample_p1; + end if; + cur_inst_next <= INSTANCE_MEMORY_MAX_ADDRESS; + sample_p2_next <= SAMPLE_MEMORY_MAX_ADDRESS; + pre_calculated_next <= '0'; + else + cur_sample_next <= sample_p1; + end if; + sample_p1_next <= SAMPLE_MEMORY_MAX_ADDRESS; + sel_sample_next <= SAMPLE_MEMORY_MAX_ADDRESS; + -- Continue Processing + read_stage_next <= GET_NEXT_SAMPLE; + cnt2_next <= 0; + end if; + end if; + end if; + when others => + null; + end case; + when FIND_NEXT_INSTANCE => + assert (CONFIG_ARRAY_T(ind).WITH_KEY) severity FAILURE; + + -- Wait for Instance Data + if (inst_op_done = '1') then + case (cnt2) is + -- GET FIRST INSTANCE + when 0 => + -- NOTE: The Generation Counters are not used directly in this state, but will be needed by the FINALIZE_SAMPLE_INFO state. + inst_op_start2 <= '1'; + inst_opcode2 <= GET_INSTANCE; + inst_r2.i <= ind; + inst_r2.addr <= inst_occupied_head(ind); + inst_r2.field_flags <= IMF_STATUS_FLAG or IMF_KEY_HASH_FLAG; + cnt2_next <= 2; -- EXIT CONDITION + -- GET NEXT INSTANCE + when 1 => + -- NOTE: The Generation Counters are not used directly in this state, but will be needed by the FINALIZE_SAMPLE_INFO state. + inst_op_start2 <= '1'; + inst_opcode2 <= GET_NEXT_INSTANCE; + inst_r2.i <= ind; + inst_r2.addr <= inst_data.addr; + inst_r2.field_flags <= IMF_STATUS_FLAG or IMF_KEY_HASH_FLAG; + cnt2_next <= 2; -- EXIT CONDITION + -- EXIT CONDITION + when 2 => + -- No More Instances + if (inst_data.addr = INSTANCE_MEMORY_MAX_ADDRESS) then + -- DONE + dds_return_code_latch2_next <= RETCODE_NO_DATA; + read_stage_next <= DONE; + else + -- Check Instance + cnt2_next <= cnt2 + 1; + end if; + -- KEY HASH 1/4 + when 3 => + assert (inst_data.addr /= INSTANCE_MEMORY_MAX_ADDRESS) severity FAILURE; + assert stable(clk, inst_data.i = ind and check_mask(inst_data.field_flags, IMF_KEY_HASH_FLAG)) severity FAILURE; + + if (unsigned(inst_data.key_hash(0)) > unsigned(instance_handle(0))) then + cnt2_next <= 7; -- INSTANCE STATUS CHECK + elsif (unsigned(inst_data.key_hash(0)) = unsigned(instance_handle(0))) then + -- Continue Check + cnt2_next <= cnt2 + 1; + else -- LESS THAN + cnt2_next <= 1; -- GET NEXT INSTANCE + end if; + -- KEY HASH 2/4 + when 4 => + assert (inst_data.addr /= INSTANCE_MEMORY_MAX_ADDRESS) severity FAILURE; + assert stable(clk, inst_data.i = ind and check_mask(inst_data.field_flags, IMF_KEY_HASH_FLAG)) severity FAILURE; + + if (unsigned(inst_data.key_hash(1)) > unsigned(instance_handle(1))) then + cnt2_next <= 7; -- INSTANCE STATUS CHECK + elsif (unsigned(inst_data.key_hash(1)) = unsigned(instance_handle(1))) then + -- Continue Check + cnt2_next <= cnt2 + 1; + else -- LESS THAN + cnt2_next <= 1; -- GET NEXT INSTANCE + end if; + -- KEY HASH 3/4 + when 5 => + assert (inst_data.addr /= INSTANCE_MEMORY_MAX_ADDRESS) severity FAILURE; + assert stable(clk, inst_data.i = ind and check_mask(inst_data.field_flags, IMF_KEY_HASH_FLAG)) severity FAILURE; + + if (unsigned(inst_data.key_hash(2)) > unsigned(instance_handle(2))) then + cnt2_next <= 7; -- INSTANCE STATUS CHECK + elsif (unsigned(inst_data.key_hash(2)) = unsigned(instance_handle(2))) then + -- Continue Check + cnt2_next <= cnt2 + 1; + else -- LESS THAN + cnt2_next <= 1; -- GET NEXT INSTANCE + end if; + -- KEY HASH 4/4 + when 6 => + assert stable(clk, inst_data.i = ind and check_mask(inst_data.field_flags, IMF_KEY_HASH_FLAG)) severity FAILURE; + + if (unsigned(inst_data.key_hash(3)) > unsigned(instance_handle(3))) then + cnt2_next <= 7; -- INSTANCE STATUS CHECK + else -- LESS THAN EQUAL + cnt2_next <= 1; -- GET NEXT INSTANCE + end if; + -- INSTANCE STATUS CHECK + when 7 => + assert (inst_data.addr /= INSTANCE_MEMORY_MAX_ADDRESS) severity FAILURE; + assert stable(clk, inst_data.i = ind and check_mask(inst_data.field_flags, IMF_STATUS_FLAG)) severity FAILURE; + + -- DEFAULT + tmp_bool := TRUE; + + -- Check Instance State + case (instance_state) is + when ALIVE_INSTANCE_STATE => + if (inst_data.status_info(ISI_NOT_ALIVE_DISPOSED_FLAG) = '1' or inst_data.status_info(ISI_NOT_ALIVE_NO_WRITERS_FLAG) = '1') then + tmp_bool := FALSE; + end if; + when NOT_ALIVE_DISPOSED_INSTANCE_STATE => + if (inst_data.status_info(ISI_NOT_ALIVE_DISPOSED_FLAG) = '0') then + tmp_bool := FALSE; + end if; + when NOT_ALIVE_NO_WRITERS_INSTANCE_STATE => + if (inst_data.status_info(ISI_NOT_ALIVE_NO_WRITERS_FLAG) = '0') then + tmp_bool := FALSE; + end if; + when NOT_ALIVE_INSTANCE_STATE => + if (inst_data.status_info(ISI_NOT_ALIVE_DISPOSED_FLAG) = '0' and inst_data.status_info(ISI_NOT_ALIVE_NO_WRITERS_FLAG) = '0') then + tmp_bool := FALSE; + end if; + when ANY_INSTANCE_STATE => + null; + when others => + tmp_bool := FALSE; + end case; + + -- Check View State + case (view_state) is + when NEW_VIEW_STATE => + if (inst_data.status_info(ISI_VIEW_FLAG) = '1') then + tmp_bool := FALSE; + end if; + when NOT_NEW_VIEW_STATE => + if (inst_data.status_info(ISI_VIEW_FLAG) = '0') then + tmp_bool := FALSE; + end if; + when ANY_VIEW_STATE => + null; + when others => + tmp_bool := FALSE; + end case; + + -- Instance Passes Checks + if (tmp_bool) then + cur_inst_next <= inst_data.addr; + read_stage_next <= GET_NEXT_SAMPLE; + cnt2_next <= 0; + -- Reset + sel_sample_next <= SAMPLE_MEMORY_MAX_ADDRESS; + sample_p1_next <= SAMPLE_MEMORY_MAX_ADDRESS; + sample_p2_next <= SAMPLE_MEMORY_MAX_ADDRESS; + else + cnt2_next <= 1; -- GET NEXT INSTANCE + end if; + when others => + null; + end case; + end if; + when CHECK_INSTANCE => + assert (CONFIG_ARRAY_T(ind).WITH_KEY) severity FAILURE; + + -- Wait for Instance Data + if (inst_op_done = '1') then + case (cnt2) is + when 0 => + -- NOTE: The Generation Counters are not used directly in this state, but will be needed by the FINALIZE_SAMPLE_INFO state. + inst_op_start2 <= '1'; + inst_opcode2 <= SEARCH_INSTANCE; + inst_r2.i <= ind; + inst_r2.key_hash <= instance_handle; + inst_r2.field_flags <= IMF_STATUS_FLAG; + cnt2_next <= cnt2 + 1; + when 1 => + -- Instance Found + if (inst_data.addr /= INSTANCE_MEMORY_MAX_ADDRESS) then + assert stable(clk, inst_data.i = ind and check_mask(inst_data.field_flags, IMF_STATUS_FLAG)) severity FAILURE; + + -- DEFAULT + tmp_bool := TRUE; + + -- Check Instance State + case (instance_state) is + when ALIVE_INSTANCE_STATE => + if (inst_data.status_info(ISI_NOT_ALIVE_DISPOSED_FLAG) = '1' or inst_data.status_info(ISI_NOT_ALIVE_NO_WRITERS_FLAG) = '1') then + tmp_bool := FALSE; + end if; + when NOT_ALIVE_DISPOSED_INSTANCE_STATE => + if (inst_data.status_info(ISI_NOT_ALIVE_DISPOSED_FLAG) = '0') then + tmp_bool := FALSE; + end if; + when NOT_ALIVE_NO_WRITERS_INSTANCE_STATE => + if (inst_data.status_info(ISI_NOT_ALIVE_NO_WRITERS_FLAG) = '0') then + tmp_bool := FALSE; + end if; + when NOT_ALIVE_INSTANCE_STATE => + if (inst_data.status_info(ISI_NOT_ALIVE_DISPOSED_FLAG) = '0' and inst_data.status_info(ISI_NOT_ALIVE_NO_WRITERS_FLAG) = '0') then + tmp_bool := FALSE; + end if; + when ANY_INSTANCE_STATE => + null; + when others => + tmp_bool := FALSE; + end case; + + -- Check View State + case (view_state) is + when NEW_VIEW_STATE => + if (inst_data.status_info(ISI_VIEW_FLAG) = '1') then + tmp_bool := FALSE; + end if; + when NOT_NEW_VIEW_STATE => + if (inst_data.status_info(ISI_VIEW_FLAG) = '0') then + tmp_bool := FALSE; + end if; + when ANY_VIEW_STATE => + null; + when others => + tmp_bool := FALSE; + end case; + + -- Instance Passes Checks + if (tmp_bool) then + -- Get Instance Samples + cur_inst_next <= inst_data.addr; + read_stage_next <= GET_NEXT_SAMPLE; + cnt2_next <= 0; + else + -- DONE + dds_return_code_latch2_next <= RETCODE_NO_DATA; + read_stage_next <= DONE; + end if; + else + -- Given Instance does not exist + -- DONE + dds_return_code_latch2_next <= RETCODE_BAD_PARAMETER; + read_stage_next <= DONE; + end if; + when others => + null; + end case; + end if; + when WAIT_PAYLOAD => + -- NOTE: We use a dedicated signal instead of the stage signal, so that the data is invalidated + -- directly after the last payload word. + -- EXIT + if (get_payload_done = '1') then + -- Exit + read_stage_next <= FINALIZE_SAMPLE_INFO; + cnt2_next <= 2; + -- Invalidate Data + si_valid_sig_next <= '0'; + end if; + when WAIT_REMOVE => + -- EXIT + if (stage = WAIT_READ) then + -- cur_inst has no more samples in collection + if (si_sample_rank_sig = 0) then + -- Skipped Sample available + if (sample_p2 /= SAMPLE_MEMORY_MAX_ADDRESS) then + cur_sample_next <= sample_p2; + else + cur_sample_next <= sample_p1; + end if; + cur_inst_next <= INSTANCE_MEMORY_MAX_ADDRESS; + sample_p2_next <= SAMPLE_MEMORY_MAX_ADDRESS; + pre_calculated_next <= '0'; + else + cur_sample_next <= sample_p1; + end if; + sample_p1_next <= SAMPLE_MEMORY_MAX_ADDRESS; + sel_sample_next <= SAMPLE_MEMORY_MAX_ADDRESS; + -- Continue Processing + read_stage_next <= GET_NEXT_SAMPLE; + cnt2_next <= 0; + end if; + when DONE => + done_read_error <= '1'; + read_stage_next <= IDLE; + end case; + end process; + empty_head_sig_prc : process(all) begin for i in 0 to NUM_READERS-1 loop @@ -6568,6 +6778,7 @@ begin if rising_edge(clk) then if (reset = '1') then stage <= RESET_SAMPLE_MEMORY; + read_stage <= IDLE; inst_stage <= RESET_MEMORY; newest_sample <= (others => SAMPLE_MEMORY_MAX_ADDRESS); oldest_sample <= (others => SAMPLE_MEMORY_MAX_ADDRESS); @@ -6603,11 +6814,13 @@ begin sample_rej_last_reason <= (others => NOT_REJECTED); rtps_return_code_latch <= ERROR; dds_return_code_latch <= RETCODE_ERROR; + dds_return_code_latch2 <= RETCODE_ERROR; ind <= 0; writer_id <= 0; cnt <= 0; cnt2 <= 0; - cnt3 <= 0; + payload_cnt <= 0; + payload_cnt2 <= 0; inst_cnt <= 0; inst_cnt2 <= 0; stale_inst_cnt <= (others => 0); @@ -6633,12 +6846,19 @@ begin sample_addr_latch_3 <= FIRST_SAMPLE_ADDRESS; sample_addr_latch_4 <= (others => '0'); sample_addr_latch_5 <= (others => '0'); + sample_addr_latch_6 <= (others => '0'); + sample_addr_latch_7 <= (others => '0'); + sample_addr_latch_8 <= (others => '0'); payload_addr_latch_1 <= (others => '0'); payload_addr_latch_2 <= (others => '0'); + payload_addr_latch_3 <= (others => '0'); inst_addr_latch_1 <= (others => '0'); inst_addr_latch_2 <= (others => '0'); + inst_addr_latch_3 <= (others => '0'); + inst_addr_latch_4 <= (others => '0'); long_latch <= (others => '0'); sample_status_info <= (others => '0'); + sample_status_info2 <= (others => '0'); si_disposed_generation_count_sig <= (others => '0'); si_no_writers_generation_count_sig <= (others => '0'); si_sample_rank_sig <= (others => '0'); @@ -6658,6 +6878,7 @@ begin inst_long_latch <= (others => '0'); else stage <= stage_next; + read_stage <= read_stage_next; inst_stage <= inst_stage_next; newest_sample <= newest_sample_next; oldest_sample <= oldest_sample_next; @@ -6691,11 +6912,13 @@ begin sample_rej_last_reason <= sample_rej_last_reason_next; rtps_return_code_latch <= rtps_return_code_latch_next; dds_return_code_latch <= dds_return_code_latch_next; + dds_return_code_latch2 <= dds_return_code_latch2_next; ind <= ind_next; writer_id <= writer_id_next; cnt <= cnt_next; cnt2 <= cnt2_next; - cnt3 <= cnt3_next; + payload_cnt <= payload_cnt_next; + payload_cnt2 <= payload_cnt2_next; inst_cnt <= inst_cnt_next; inst_cnt2 <= inst_cnt2_next; stale_inst_cnt <= stale_inst_cnt_next; @@ -6721,12 +6944,19 @@ begin sample_addr_latch_3 <= sample_addr_latch_3_next; sample_addr_latch_4 <= sample_addr_latch_4_next; sample_addr_latch_5 <= sample_addr_latch_5_next; + sample_addr_latch_6 <= sample_addr_latch_6_next; + sample_addr_latch_7 <= sample_addr_latch_7_next; + sample_addr_latch_8 <= sample_addr_latch_8_next; payload_addr_latch_1 <= payload_addr_latch_1_next; payload_addr_latch_2 <= payload_addr_latch_2_next; + payload_addr_latch_3 <= payload_addr_latch_3_next; inst_addr_latch_1 <= inst_addr_latch_1_next; inst_addr_latch_2 <= inst_addr_latch_2_next; + inst_addr_latch_3 <= inst_addr_latch_3_next; + inst_addr_latch_4 <= inst_addr_latch_4_next; long_latch <= long_latch_next; sample_status_info <= sample_status_info_next; + sample_status_info2 <= sample_status_info2_next; si_disposed_generation_count_sig <= si_disposed_generation_count_sig_next; si_no_writers_generation_count_sig <= si_no_writers_generation_count_sig_next; si_sample_rank_sig <= si_sample_rank_sig_next; diff --git a/syn/dds_reader_syn.vhd b/syn/dds_reader_syn.vhd index 33be506..1076e0a 100644 --- a/syn/dds_reader_syn.vhd +++ b/syn/dds_reader_syn.vhd @@ -14,52 +14,95 @@ use work.Type1_package.all; entity dds_reader_syn is port ( -- SYSTEM - clk : in std_logic; - reset : in std_logic; - time : in TIME_TYPE; + clk : in std_logic; + reset : in std_logic; -- FROM RTPS ENDPOINT - start_rtps : in std_logic_vector(0 to 0); - opcode_rtps : in HISTORY_CACHE_OPCODE_ARRAY_TYPE(0 to 0); - ack_rtps : out std_logic_vector(0 to 0); - done_rtps : out std_logic_vector(0 to 0); - ret_rtps : out HISTORY_CACHE_RESPONSE_ARRAY_TYPE(0 to 0); - data_in_rtps : in WORD_ARRAY_TYPE(0 to 0); - valid_in_rtps : in std_logic_vector(0 to 0); - ready_in_rtps : out std_logic_vector(0 to 0); - last_word_in_rtps : in std_logic_vector(0 to 0); - -- TO USER ENTITY - start_dds : in std_logic_vector(0 to 0); - ack_dds : out std_logic_vector(0 to 0); - opcode_dds : in DDS_READER_OPCODE_ARRAY_TYPE(0 to 0); - instance_state_dds : in INSTANCE_STATE_ARRAY_TYPE(0 to 0); - view_state_dds : in VIEW_STATE_ARRAY_TYPE(0 to 0); - sample_state_dds : in SAMPLE_STATE_ARRAY_TYPE(0 to 0); - instance_handle_dds : in INSTANCE_HANDLE_ARRAY_TYPE(0 to 0); - max_samples_dds : in MAX_SAMPLES_ARRAY_TYPE(0 to 0); - get_data_dds : in std_logic_vector(0 to 0); - done_dds : out std_logic_vector(0 to 0); - return_code_dds : out RETURN_CODE_ARRAY_TYPE(0 to 0); - valid_out_dds : out std_logic_vector(0 to 0); - ready_out_dds : in std_logic_vector(0 to 0); - data_out_dds : out WORD_ARRAY_TYPE(0 to 0); - last_word_out_dds : out std_logic_vector(0 to 0); - sample_info : out SAMPLE_INFO_ARRAY_TYPE(0 to 0); - sample_info_valid : out std_logic_vector(0 to 0); - sample_info_ack : in std_logic_vector(0 to 0); - eoc : out std_logic_vector(0 to 0); - -- Communication Status - status : out STATUS_KIND_ARRAY_TYPE(0 to 0) + input : in std_logic_vector(13 downto 0); + output : out std_logic_vector(24 downto 0) ); end entity; architecture arch of dds_reader_syn is + + constant NUM_READERS : natural := 1; + begin if_gen : if (NUM_READERS > 0) generate + signal time : TIME_TYPE; + signal start_rtps, ack_rtps, done_rtps, valid_in_rtps, ready_in_rtps, last_word_in_rtps, start_dds, ack_dds, get_data_dds, done_dds, valid_out_dds, ready_out_dds, last_word_out_dds, sample_info_valid, sample_info_ack, eoc : std_logic_vector(0 to NUM_READERS-1); + signal opcode_rtps : HISTORY_CACHE_OPCODE_ARRAY_TYPE(0 to NUM_READERS-1); + signal ret_rtps : HISTORY_CACHE_RESPONSE_ARRAY_TYPE(0 to NUM_READERS-1); + signal data_in_rtps, data_out_dds : WORD_ARRAY_TYPE(0 to NUM_READERS-1); + signal opcode_dds : DDS_READER_OPCODE_ARRAY_TYPE(0 to NUM_READERS-1); + signal instance_state_dds : INSTANCE_STATE_ARRAY_TYPE(0 to NUM_READERS-1); + signal view_state_dds : VIEW_STATE_ARRAY_TYPE(0 to NUM_READERS-1); + signal sample_state_dds : SAMPLE_STATE_ARRAY_TYPE(0 to NUM_READERS-1); + signal instance_handle_dds : INSTANCE_HANDLE_ARRAY_TYPE(0 to NUM_READERS-1); + signal max_samples_dds : MAX_SAMPLES_ARRAY_TYPE(0 to NUM_READERS-1); + signal return_code_dds : RETURN_CODE_ARRAY_TYPE(0 to NUM_READERS-1); + signal sample_info : SAMPLE_INFO_ARRAY_TYPE(0 to NUM_READERS-1); + signal status : STATUS_KIND_ARRAY_TYPE(0 to NUM_READERS-1); + begin + + -- This process is here to reduce the port count (allowing the entity to be synthesized as top level), but still prevent the tool from optimizing any logic away. + dummy_reducer : process (all) + variable tmp : std_logic_vector(127 downto 0); + begin + if rising_edge(clk) then + time <= to_double_word(to_unsigned(time)(62 downto 0) & input(0)); + for i in 0 to NUM_READERS-1 loop + start_rtps(i) <= input(1); + opcode_rtps(i) <= HISTORY_CACHE_OPCODE_TYPE'VAL(to_integer(unsigned(input))); + data_in_rtps(i) <= data_in_rtps(i)(data_in_rtps(i)'length-2 downto 0) & input(2); + valid_in_rtps(i) <= input(3); + last_word_in_rtps(i) <= input(4); + start_dds(i) <= input(5); + opcode_dds(i) <= DDS_READER_OPCODE_TYPE'VAL(to_integer(unsigned(input))); + instance_state_dds(i) <= instance_state_dds(i)(instance_state_dds(i)'length-2 downto 0) & input(6); + view_state_dds(i) <= view_state_dds(i)(view_state_dds(i)'length-2 downto 0) & input(7); + sample_state_dds(i) <= sample_state_dds(i)(sample_state_dds(i)'length-2 downto 0) & input(8); + tmp := std_logic_vector(to_unsigned(instance_handle_dds(i))(126 downto 0) & input(9)); + instance_handle_dds(i) <= to_key_hash(tmp); + max_samples_dds(i) <= max_samples_dds(i)(max_samples_dds(i)'length-2 downto 0) & input(10); + get_data_dds(i) <= input(11); + ready_out_dds(i) <= input(12); + sample_info_ack(i) <= input(13); + end loop; + end if; + for i in 0 to NUM_READERS-1 loop + output(0) <= ack_rtps(i); + output(1) <= done_rtps(i); + output(2) <= to_unsigned(HISTORY_CACHE_RESPONSE_TYPE'POS(ret_rtps(i)),1)(0); + output(3) <= ready_in_rtps(i); + output(4) <= ack_dds(i); + output(5) <= done_dds(i); + output(6) <= return_code_dds(i)(to_integer(unsigned(input))); + output(7) <= valid_out_dds(i); + output(8) <= data_out_dds(i)(to_integer(unsigned(input))); + output(9) <= last_word_out_dds(i); + output(10) <= sample_info(i).sample_state(to_integer(unsigned(input))); + output(11) <= sample_info(i).view_state(to_integer(unsigned(input))); + output(12) <= sample_info(i).instance_state(to_integer(unsigned(input))); + output(13) <= to_unsigned(sample_info(i).source_timestamp)(to_integer(unsigned(input))); + output(14) <= to_unsigned(sample_info(i).instance_handle)(to_integer(unsigned(input))); + output(15) <= to_unsigned(sample_info(i).publication_handle)(to_integer(unsigned(input))); + output(16) <= sample_info(i).disposed_generation_count(to_integer(unsigned(input))); + output(17) <= sample_info(i).no_writers_generation_count(to_integer(unsigned(input))); + output(18) <= sample_info(i).sample_rank(to_integer(unsigned(input))); + output(19) <= sample_info(i).generation_rank(to_integer(unsigned(input))); + output(20) <= sample_info(i).absolute_generation_rank(to_integer(unsigned(input))); + output(21) <= sample_info(i).valid_data; + output(22) <= sample_info_valid(i); + output(23) <= eoc(i); + output(24) <= status(i)(to_integer(unsigned(input))); + end loop; + end process; + syn_inst : entity work.dds_reader(arch) generic map ( - NUM_READERS => 1, - CONFIG_ARRAY => to_QUARTUS_CONFIG_ARRAY_TYPE(ENDPOINT_CONFIG(0 to 0)), + NUM_READERS => NUM_READERS, + CONFIG_ARRAY => to_QUARTUS_CONFIG_ARRAY_TYPE(ENDPOINT_CONFIG(0 to NUM_READERS-1)), MAX_REMOTE_ENDPOINTS => 50 ) port map (