From 6e20b8958dbf682934d55d6aa2ebba94568b6506 Mon Sep 17 00:00:00 2001 From: Greek Date: Sat, 27 Nov 2021 17:05:27 +0100 Subject: [PATCH] Add VHDL configuration for single_port_ram and FWFT_FIFO Allow single_port_ram and FWFT_FIFO to have Altera specific architectures. --- src/FWFT_FIFO_Altera.vhd | 43 ++++++++++ src/FWFT_FIFO_cfg.vhd | 4 + src/Tests/FWFT_FIFO_cfg.vhd | 4 + .../L1_rtps_builtin_endpoint_test1.vhd | 2 +- .../Level_1/L1_rtps_reader_test1_trk.vhd | 2 +- .../Level_1/L1_rtps_reader_test1_vrk.vhd | 2 +- .../Level_1/L1_rtps_writer_test1_tbkdp.vhd | 2 +- .../Level_1/L1_rtps_writer_test1_trkdn.vhd | 2 +- .../Level_1/L1_rtps_writer_test1_trkdp.vhd | 2 +- .../Level_1/L1_rtps_writer_test1_vbkdp.vhd | 2 +- .../Level_1/L1_rtps_writer_test1_vrkdn.vhd | 2 +- .../Level_1/L1_rtps_writer_test1_vrkdp.vhd | 2 +- .../Level_1/L1_rtps_writer_test1_vrksp.vhd | 2 +- .../Level_1/L1_rtps_writer_test1_vrndp.vhd | 2 +- .../Level_1/L1_rtps_writer_test2_vrkdn.vhd | 2 +- src/Tests/Level_2/L2_Testbench_Lib2.vhd | 6 +- src/Tests/Level_2/L2_Testbench_Lib3.vhd | 6 +- src/Tests/Level_2/L2_Type1_test1.vhd | 4 +- src/Tests/single_port_ram_cfg.vhd | 4 + src/Tests/test_ram.vhd | 50 ------------ src/Tests/testbench.pro | 14 +++- src/mem_ctrl.vhd | 4 +- src/single_port_ram.vhd | 78 +++++++++---------- src/single_port_ram_Altera.vhd | 38 +++++++++ src/single_port_ram_cfg.vhd | 4 + 25 files changed, 167 insertions(+), 116 deletions(-) create mode 100644 src/FWFT_FIFO_Altera.vhd create mode 100644 src/FWFT_FIFO_cfg.vhd create mode 100644 src/Tests/FWFT_FIFO_cfg.vhd create mode 100644 src/Tests/single_port_ram_cfg.vhd delete mode 100644 src/Tests/test_ram.vhd create mode 100644 src/single_port_ram_Altera.vhd create mode 100644 src/single_port_ram_cfg.vhd diff --git a/src/FWFT_FIFO_Altera.vhd b/src/FWFT_FIFO_Altera.vhd new file mode 100644 index 0000000..54cd4bd --- /dev/null +++ b/src/FWFT_FIFO_Altera.vhd @@ -0,0 +1,43 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library altera_mf; +use altera_mf.altera_mf_components.all; +use work.math_pkg.all; + +architecture altera of FWFT_FIFO is + + signal used_sig : std_logic_vector(log2c(FIFO_DEPTH)-1 downto 0); + +begin + + -- XXX: Possible Worst Case Path + free <= FIFO_DEPTH - to_integer(unsigned(used_sig)); + + scfifo_component : scfifo + generic map ( + add_ram_output_register => "OFF", + intended_device_family => "Cyclone V", + lpm_numwords => FIFO_DEPTH, + lpm_showahead => "ON", + lpm_type => "scfifo", + lpm_width => DATA_WIDTH, + lpm_widthu => log2c(FIFO_DEPTH), + overflow_checking => "ON", + underflow_checking => "ON", + use_eab => "ON" + ) + port map ( + clock => clk, + sclr => reset, + data => data_in, + rdreq => read, + wrreq => write, + empty => empty, + full => full, + q => data_out, + usedw => used_sig + ); + +end architecture; \ No newline at end of file diff --git a/src/FWFT_FIFO_cfg.vhd b/src/FWFT_FIFO_cfg.vhd new file mode 100644 index 0000000..8583299 --- /dev/null +++ b/src/FWFT_FIFO_cfg.vhd @@ -0,0 +1,4 @@ +configuration FWFT_FIFO_cfg of FWFT_FIFO is + for altera + end for; +end configuration; \ No newline at end of file diff --git a/src/Tests/FWFT_FIFO_cfg.vhd b/src/Tests/FWFT_FIFO_cfg.vhd new file mode 100644 index 0000000..7093e2e --- /dev/null +++ b/src/Tests/FWFT_FIFO_cfg.vhd @@ -0,0 +1,4 @@ +configuration FWFT_FIFO_cfg of FWFT_FIFO is + for arch + end for; +end configuration; \ No newline at end of file diff --git a/src/Tests/Level_1/L1_rtps_builtin_endpoint_test1.vhd b/src/Tests/Level_1/L1_rtps_builtin_endpoint_test1.vhd index 1297ef8..eba4214 100644 --- a/src/Tests/Level_1/L1_rtps_builtin_endpoint_test1.vhd +++ b/src/Tests/Level_1/L1_rtps_builtin_endpoint_test1.vhd @@ -412,7 +412,7 @@ begin last_word_out_ro => fifo_in(WORD_WIDTH) ); - fifo_inst : entity work.FWFT_FIFO(arch) + fifo_inst : configuration work.FWFT_FIFO_cfg generic map ( FIFO_DEPTH => 2, DATA_WIDTH => WORD_WIDTH+1 diff --git a/src/Tests/Level_1/L1_rtps_reader_test1_trk.vhd b/src/Tests/Level_1/L1_rtps_reader_test1_trk.vhd index ae6f63f..7428a45 100644 --- a/src/Tests/Level_1/L1_rtps_reader_test1_trk.vhd +++ b/src/Tests/Level_1/L1_rtps_reader_test1_trk.vhd @@ -120,7 +120,7 @@ begin last_word_out_hc => open ); - fifo_inst : entity work.FWFT_FIFO(arch) + fifo_inst : configuration work.FWFT_FIFO_cfg generic map ( FIFO_DEPTH => 2, DATA_WIDTH => WORD_WIDTH+1 diff --git a/src/Tests/Level_1/L1_rtps_reader_test1_vrk.vhd b/src/Tests/Level_1/L1_rtps_reader_test1_vrk.vhd index 4eeb269..c18b27f 100644 --- a/src/Tests/Level_1/L1_rtps_reader_test1_vrk.vhd +++ b/src/Tests/Level_1/L1_rtps_reader_test1_vrk.vhd @@ -121,7 +121,7 @@ begin last_word_out_hc => open ); - fifo_inst : entity work.FWFT_FIFO(arch) + fifo_inst : configuration work.FWFT_FIFO_cfg generic map ( FIFO_DEPTH => 2, DATA_WIDTH => WORD_WIDTH+1 diff --git a/src/Tests/Level_1/L1_rtps_writer_test1_tbkdp.vhd b/src/Tests/Level_1/L1_rtps_writer_test1_tbkdp.vhd index 9efc596..9306fd3 100644 --- a/src/Tests/Level_1/L1_rtps_writer_test1_tbkdp.vhd +++ b/src/Tests/Level_1/L1_rtps_writer_test1_tbkdp.vhd @@ -127,7 +127,7 @@ begin cc_seq_nr => cc_seq_nr ); - fifo_inst : entity work.FWFT_FIFO(arch) + fifo_inst : configuration work.FWFT_FIFO_cfg generic map ( FIFO_DEPTH => 2, DATA_WIDTH => WORD_WIDTH+1 diff --git a/src/Tests/Level_1/L1_rtps_writer_test1_trkdn.vhd b/src/Tests/Level_1/L1_rtps_writer_test1_trkdn.vhd index 5e7e65d..9c94a69 100644 --- a/src/Tests/Level_1/L1_rtps_writer_test1_trkdn.vhd +++ b/src/Tests/Level_1/L1_rtps_writer_test1_trkdn.vhd @@ -127,7 +127,7 @@ begin cc_seq_nr => cc_seq_nr ); - fifo_inst : entity work.FWFT_FIFO(arch) + fifo_inst : configuration work.FWFT_FIFO_cfg generic map ( FIFO_DEPTH => 2, DATA_WIDTH => WORD_WIDTH+1 diff --git a/src/Tests/Level_1/L1_rtps_writer_test1_trkdp.vhd b/src/Tests/Level_1/L1_rtps_writer_test1_trkdp.vhd index be6d511..08def95 100644 --- a/src/Tests/Level_1/L1_rtps_writer_test1_trkdp.vhd +++ b/src/Tests/Level_1/L1_rtps_writer_test1_trkdp.vhd @@ -127,7 +127,7 @@ begin cc_seq_nr => cc_seq_nr ); - fifo_inst : entity work.FWFT_FIFO(arch) + fifo_inst : configuration work.FWFT_FIFO_cfg generic map ( FIFO_DEPTH => 2, DATA_WIDTH => WORD_WIDTH+1 diff --git a/src/Tests/Level_1/L1_rtps_writer_test1_vbkdp.vhd b/src/Tests/Level_1/L1_rtps_writer_test1_vbkdp.vhd index 3109263..7acdd3c 100644 --- a/src/Tests/Level_1/L1_rtps_writer_test1_vbkdp.vhd +++ b/src/Tests/Level_1/L1_rtps_writer_test1_vbkdp.vhd @@ -127,7 +127,7 @@ begin cc_seq_nr => cc_seq_nr ); - fifo_inst : entity work.FWFT_FIFO(arch) + fifo_inst : configuration work.FWFT_FIFO_cfg generic map ( FIFO_DEPTH => 2, DATA_WIDTH => WORD_WIDTH+1 diff --git a/src/Tests/Level_1/L1_rtps_writer_test1_vrkdn.vhd b/src/Tests/Level_1/L1_rtps_writer_test1_vrkdn.vhd index f4d0fb7..a2dc7bd 100644 --- a/src/Tests/Level_1/L1_rtps_writer_test1_vrkdn.vhd +++ b/src/Tests/Level_1/L1_rtps_writer_test1_vrkdn.vhd @@ -127,7 +127,7 @@ begin cc_seq_nr => cc_seq_nr ); - fifo_inst : entity work.FWFT_FIFO(arch) + fifo_inst : configuration work.FWFT_FIFO_cfg generic map ( FIFO_DEPTH => 2, DATA_WIDTH => WORD_WIDTH+1 diff --git a/src/Tests/Level_1/L1_rtps_writer_test1_vrkdp.vhd b/src/Tests/Level_1/L1_rtps_writer_test1_vrkdp.vhd index ef7d53f..81cb11e 100644 --- a/src/Tests/Level_1/L1_rtps_writer_test1_vrkdp.vhd +++ b/src/Tests/Level_1/L1_rtps_writer_test1_vrkdp.vhd @@ -127,7 +127,7 @@ begin cc_seq_nr => cc_seq_nr ); - fifo_inst : entity work.FWFT_FIFO(arch) + fifo_inst : configuration work.FWFT_FIFO_cfg generic map ( FIFO_DEPTH => 2, DATA_WIDTH => WORD_WIDTH+1 diff --git a/src/Tests/Level_1/L1_rtps_writer_test1_vrksp.vhd b/src/Tests/Level_1/L1_rtps_writer_test1_vrksp.vhd index 8e1891f..28d06b1 100644 --- a/src/Tests/Level_1/L1_rtps_writer_test1_vrksp.vhd +++ b/src/Tests/Level_1/L1_rtps_writer_test1_vrksp.vhd @@ -127,7 +127,7 @@ begin cc_seq_nr => cc_seq_nr ); - fifo_inst : entity work.FWFT_FIFO(arch) + fifo_inst : configuration work.FWFT_FIFO_cfg generic map ( FIFO_DEPTH => 2, DATA_WIDTH => WORD_WIDTH+1 diff --git a/src/Tests/Level_1/L1_rtps_writer_test1_vrndp.vhd b/src/Tests/Level_1/L1_rtps_writer_test1_vrndp.vhd index b3f7e62..5ef8b83 100644 --- a/src/Tests/Level_1/L1_rtps_writer_test1_vrndp.vhd +++ b/src/Tests/Level_1/L1_rtps_writer_test1_vrndp.vhd @@ -127,7 +127,7 @@ begin cc_seq_nr => cc_seq_nr ); - fifo_inst : entity work.FWFT_FIFO(arch) + fifo_inst : configuration work.FWFT_FIFO_cfg generic map ( FIFO_DEPTH => 2, DATA_WIDTH => WORD_WIDTH+1 diff --git a/src/Tests/Level_1/L1_rtps_writer_test2_vrkdn.vhd b/src/Tests/Level_1/L1_rtps_writer_test2_vrkdn.vhd index cc83c0f..40b6919 100644 --- a/src/Tests/Level_1/L1_rtps_writer_test2_vrkdn.vhd +++ b/src/Tests/Level_1/L1_rtps_writer_test2_vrkdn.vhd @@ -126,7 +126,7 @@ begin cc_seq_nr => cc_seq_nr ); - fifo_inst : entity work.FWFT_FIFO(arch) + fifo_inst : configuration work.FWFT_FIFO_cfg generic map ( FIFO_DEPTH => 2, DATA_WIDTH => WORD_WIDTH+1 diff --git a/src/Tests/Level_2/L2_Testbench_Lib2.vhd b/src/Tests/Level_2/L2_Testbench_Lib2.vhd index 9cadec3..8ad1dea 100644 --- a/src/Tests/Level_2/L2_Testbench_Lib2.vhd +++ b/src/Tests/Level_2/L2_Testbench_Lib2.vhd @@ -318,7 +318,7 @@ begin rh_fifo_gen : for i in 0 to NUM_ENDPOINTS generate begin - fifo_inst : entity Testbench_Lib2.FWFT_FIFO(arch) + fifo_inst : configuration Testbench_Lib2.FWFT_FIFO_cfg generic map ( FIFO_DEPTH => 2, DATA_WIDTH => WORD_WIDTH+1 @@ -339,7 +339,7 @@ begin rtps_out_fifo_gen : for i in 0 to NUM_ENDPOINTS generate begin - fifo_inst : entity Testbench_Lib2.FWFT_FIFO(arch) + fifo_inst : configuration Testbench_Lib2.FWFT_FIFO_cfg generic map ( FIFO_DEPTH => 2, DATA_WIDTH => WORD_WIDTH+1 @@ -363,7 +363,7 @@ begin rtps_fifo_gen : for i in 0 to NUM_ENDPOINTS-1 generate begin - fifo_inst : entity Testbench_Lib2.FWFT_FIFO(arch) + fifo_inst : configuration Testbench_Lib2.FWFT_FIFO_cfg generic map ( FIFO_DEPTH => 2, DATA_WIDTH => WORD_WIDTH+1 diff --git a/src/Tests/Level_2/L2_Testbench_Lib3.vhd b/src/Tests/Level_2/L2_Testbench_Lib3.vhd index e838b6f..d72aed6 100644 --- a/src/Tests/Level_2/L2_Testbench_Lib3.vhd +++ b/src/Tests/Level_2/L2_Testbench_Lib3.vhd @@ -371,7 +371,7 @@ begin rh_fifo_gen : for i in 0 to NUM_ENDPOINTS generate begin - fifo_inst : entity Testbench_Lib3.FWFT_FIFO(arch) + fifo_inst : configuration Testbench_Lib3.FWFT_FIFO_cfg generic map ( FIFO_DEPTH => 2, DATA_WIDTH => WORD_WIDTH+1 @@ -392,7 +392,7 @@ begin rtps_out_fifo_gen : for i in 0 to NUM_ENDPOINTS generate begin - fifo_inst : entity Testbench_Lib3.FWFT_FIFO(arch) + fifo_inst : configuration Testbench_Lib3.FWFT_FIFO_cfg generic map ( FIFO_DEPTH => 2, DATA_WIDTH => WORD_WIDTH+1 @@ -416,7 +416,7 @@ begin rtps_fifo_gen : for i in 0 to NUM_ENDPOINTS-1 generate begin - fifo_inst : entity Testbench_Lib3.FWFT_FIFO(arch) + fifo_inst : configuration Testbench_Lib3.FWFT_FIFO_cfg generic map ( FIFO_DEPTH => 2, DATA_WIDTH => WORD_WIDTH+1 diff --git a/src/Tests/Level_2/L2_Type1_test1.vhd b/src/Tests/Level_2/L2_Type1_test1.vhd index 3a3f0f9..d22bc72 100644 --- a/src/Tests/Level_2/L2_Type1_test1.vhd +++ b/src/Tests/Level_2/L2_Type1_test1.vhd @@ -118,7 +118,7 @@ begin encode_done => encode_done_w ); - fifo_r_w_inst : entity work.FWFT_FIFO(arch) + fifo_r_w_inst : configuration work.FWFT_FIFO_cfg generic map ( FIFO_DEPTH => 65536/(WORD_WIDTH/BYTE_WIDTH), DATA_WIDTH => WORD_WIDTH @@ -136,7 +136,7 @@ begin free => open ); - fifo_w_r_inst : entity work.FWFT_FIFO(arch) + fifo_w_r_inst : configuration work.FWFT_FIFO_cfg generic map ( FIFO_DEPTH => 65536/(WORD_WIDTH/BYTE_WIDTH), DATA_WIDTH => WORD_WIDTH diff --git a/src/Tests/single_port_ram_cfg.vhd b/src/Tests/single_port_ram_cfg.vhd new file mode 100644 index 0000000..b38070f --- /dev/null +++ b/src/Tests/single_port_ram_cfg.vhd @@ -0,0 +1,4 @@ +configuration single_port_ram_cfg of single_port_ram is + for arch + end for; +end configuration; \ No newline at end of file diff --git a/src/Tests/test_ram.vhd b/src/Tests/test_ram.vhd deleted file mode 100644 index 4c0d243..0000000 --- a/src/Tests/test_ram.vhd +++ /dev/null @@ -1,50 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -use work.rtps_test_package.all; - -entity single_port_ram is - generic ( - ADDR_WIDTH : natural := 8; - DATA_WIDTH : natural := 12; - MEMORY_DEPTH : natural := 256 - ); - port ( - clk : in std_logic; - addr : in std_logic_vector(ADDR_WIDTH-1 downto 0); - wen : in std_logic; - ren : in std_logic; - wr_data : in std_logic_vector(DATA_WIDTH-1 downto 0); - rd_data : out std_logic_vector(DATA_WIDTH-1 downto 0) - ); -end entity; - -architecture arch of single_port_ram is - - type TEST_RAM_TYPE is array (0 to MEMORY_DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0); - - signal mem : TEST_RAM_TYPE := (others => (others => '0')); - -begin - - ram_prc : process(all) - begin - if rising_edge(clk) then - rd_data <= (others => '0'); - - if (wen = '1') then - mem(to_integer(unsigned(addr))) <= wr_data; - end if; - - if (ren = '1') then - if (wen = '1') then - rd_data <= wr_data; - else - rd_data <= mem(to_integer(unsigned(addr))); - end if; - end if; - end if; - end process; - -end architecture; diff --git a/src/Tests/testbench.pro b/src/Tests/testbench.pro index 04f7c8e..b960253 100644 --- a/src/Tests/testbench.pro +++ b/src/Tests/testbench.pro @@ -7,8 +7,10 @@ analyze ../rtps_package.vhd analyze test_config2.vhd analyze ../rtps_config_package.vhd analyze ../rtps_test_package.vhd -analyze test_ram.vhd +analyze ../single_port_ram.vhd +analyze single_port_ram_cfg.vhd analyze ../FWFT_FIFO.vhd +analyze FWFT_FIFO_cfg.vhd analyze ../mem_ctrl.vhd analyze ../rtps_handler.vhd analyze ../rtps_builtin_endpoint.vhd @@ -33,8 +35,10 @@ analyze ../rtps_package.vhd analyze test_config3.vhd analyze ../rtps_config_package.vhd analyze ../rtps_test_package.vhd -analyze test_ram.vhd +analyze ../single_port_ram.vhd +analyze single_port_ram_cfg.vhd analyze ../FWFT_FIFO.vhd +analyze FWFT_FIFO_cfg.vhd analyze ../mem_ctrl.vhd analyze ../rtps_handler.vhd analyze ../rtps_builtin_endpoint.vhd @@ -61,8 +65,12 @@ analyze ../rtps_package.vhd analyze test_config1.vhd analyze ../rtps_config_package.vhd analyze ../rtps_test_package.vhd -analyze test_ram.vhd +analyze ../single_port_ram.vhd +analyze ../single_port_ram_Altera.vhd +analyze single_port_ram_cfg.vhd analyze ../FWFT_FIFO.vhd +analyze ../FWFT_FIFO_Altera.vhd +analyze FWFT_FIFO_cfg.vhd analyze ../mem_ctrl.vhd analyze ../rtps_handler.vhd analyze ../rtps_builtin_endpoint.vhd diff --git a/src/mem_ctrl.vhd b/src/mem_ctrl.vhd index d04fd19..a5bc100 100644 --- a/src/mem_ctrl.vhd +++ b/src/mem_ctrl.vhd @@ -43,7 +43,7 @@ architecture arch of mem_ctrl is begin --*****COMPONENT INSTANTIATION***** - ram_inst : entity work.single_port_ram(arch) + ram_inst : configuration work.single_port_ram_cfg generic map ( ADDR_WIDTH => ADDR_WIDTH, DATA_WIDTH => DATA_WIDTH, @@ -94,7 +94,7 @@ begin end if; end process; - burst_fifo_inst : entity work.FWFT_FIFO(arch) + burst_fifo_inst : configuration work.FWFT_FIFO_cfg generic map ( FIFO_DEPTH => MAX_BURST_LENGTH, DATA_WIDTH => DATA_WIDTH diff --git a/src/single_port_ram.vhd b/src/single_port_ram.vhd index 54f034a..6a92dcb 100644 --- a/src/single_port_ram.vhd +++ b/src/single_port_ram.vhd @@ -2,53 +2,49 @@ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; -LIBRARY altera_mf; -USE altera_mf.altera_mf_components.all; +use work.rtps_test_package.all; entity single_port_ram is - generic ( - ADDR_WIDTH : natural; - DATA_WIDTH : natural; - MEMORY_DEPTH : natural - ); - port ( - clk : in std_logic; - addr : in std_logic_vector(ADDR_WIDTH-1 downto 0); - wen : in std_logic; - ren : in std_logic; - wr_data : in std_logic_vector(DATA_WIDTH-1 downto 0); - rd_data : out std_logic_vector(DATA_WIDTH-1 downto 0) - ); + generic ( + ADDR_WIDTH : natural := 8; + DATA_WIDTH : natural := 12; + MEMORY_DEPTH : natural := 256 + ); + port ( + clk : in std_logic; + addr : in std_logic_vector(ADDR_WIDTH-1 downto 0); + wen : in std_logic; + ren : in std_logic; + wr_data : in std_logic_vector(DATA_WIDTH-1 downto 0); + rd_data : out std_logic_vector(DATA_WIDTH-1 downto 0) + ); end entity; architecture arch of single_port_ram is + type RAM_TYPE is array (0 to MEMORY_DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0); + + signal mem : RAM_TYPE := (others => (others => '0')); + begin - - altsyncram_component : altsyncram - generic map ( - clock_enable_input_a => "BYPASS", - clock_enable_output_a => "BYPASS", - intended_device_family => "Cyclone V", - lpm_hint => "ENABLE_RUNTIME_MOD=NO", - lpm_type => "altsyncram", - numwords_a => MEMORY_DEPTH, - operation_mode => "SINGLE_PORT", - outdata_aclr_a => "NONE", - outdata_reg_a => "UNREGISTERED", - power_up_uninitialized => "FALSE", - read_during_write_mode_port_a => "DONT_CARE", - widthad_a => ADDR_WIDTH, - width_a => DATA_WIDTH, - width_byteena_a => 1 - ) - port map ( - address_a => addr, - clock0 => clk, - data_a => wr_data, - rden_a => ren, - wren_a => wen, - q_a => rd_data - ); + + ram_prc : process(all) + begin + if rising_edge(clk) then + rd_data <= (others => '0'); + + if (wen = '1') then + mem(to_integer(unsigned(addr))) <= wr_data; + end if; + + if (ren = '1') then + if (wen = '1') then + rd_data <= wr_data; + else + rd_data <= mem(to_integer(unsigned(addr))); + end if; + end if; + end if; + end process; end architecture; diff --git a/src/single_port_ram_Altera.vhd b/src/single_port_ram_Altera.vhd new file mode 100644 index 0000000..3a5b652 --- /dev/null +++ b/src/single_port_ram_Altera.vhd @@ -0,0 +1,38 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +LIBRARY altera_mf; +USE altera_mf.altera_mf_components.all; + +architecture altera of single_port_ram is + +begin + + altsyncram_component : altsyncram + generic map ( + clock_enable_input_a => "BYPASS", + clock_enable_output_a => "BYPASS", + intended_device_family => "Cyclone V", + lpm_hint => "ENABLE_RUNTIME_MOD=NO", + lpm_type => "altsyncram", + numwords_a => MEMORY_DEPTH, + operation_mode => "SINGLE_PORT", + outdata_aclr_a => "NONE", + outdata_reg_a => "UNREGISTERED", + power_up_uninitialized => "FALSE", + read_during_write_mode_port_a => "DONT_CARE", + widthad_a => ADDR_WIDTH, + width_a => DATA_WIDTH, + width_byteena_a => 1 + ) + port map ( + address_a => addr, + clock0 => clk, + data_a => wr_data, + rden_a => ren, + wren_a => wen, + q_a => rd_data + ); + +end architecture; diff --git a/src/single_port_ram_cfg.vhd b/src/single_port_ram_cfg.vhd new file mode 100644 index 0000000..3c417d0 --- /dev/null +++ b/src/single_port_ram_cfg.vhd @@ -0,0 +1,4 @@ +configuration single_port_ram_cfg of single_port_ram is + for altera + end for; +end configuration; \ No newline at end of file