diff --git a/.gitignore b/.gitignore index b5c410c..e781e52 100644 --- a/.gitignore +++ b/.gitignore @@ -8,7 +8,16 @@ !*/ #WHITELIST -#Vivado Project File +#***VIVADO*** +#Project File !*.xpr -#Modelsim Do files -!*.do \ No newline at end of file +#***MODELSIM*** +#Do files +!*.do +#***QUARTUS*** +#Project File +!*.qpf +#Settings File +!*.qsf +#QSYS File +!*.qsys \ No newline at end of file diff --git a/syn/DE10-Nano/rtps-fpga.qpf b/syn/DE10-Nano/rtps-fpga.qpf new file mode 100644 index 0000000..4b71ff7 --- /dev/null +++ b/syn/DE10-Nano/rtps-fpga.qpf @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2018 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition +# Date created = 12:05:11 May 29, 2020 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "18.1" +DATE = "12:05:11 May 29, 2020" + +# Revisions + +PROJECT_REVISION = "top" diff --git a/syn/DE10-Nano/top.qsf b/syn/DE10-Nano/top.qsf new file mode 100644 index 0000000..4f53fb5 --- /dev/null +++ b/syn/DE10-Nano/top.qsf @@ -0,0 +1,55 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2018 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition +# Date created = 12:05:11 May 29, 2020 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# top_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus Prime software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone V" +set_global_assignment -name DEVICE 5CSEBA6U23I7 +set_global_assignment -name TOP_LEVEL_ENTITY rtps_handler +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:05:11 MAY 29, 2020" +set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Lite Edition" +set_global_assignment -name VHDL_FILE ../../src/rtps_package.vhd -hdl_version VHDL_2008 +set_global_assignment -name VHDL_FILE ../../src/rtps_handler.vhd -hdl_version VHDL_2008 +set_global_assignment -name VHDL_FILE ../../src/math_pkg.vhd -hdl_version VHDL_2008 +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40" +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top \ No newline at end of file diff --git a/syn/project_1.xpr b/syn/Zedboard/rtps-fpga.xpr similarity index 94% rename from syn/project_1.xpr rename to syn/Zedboard/rtps-fpga.xpr index 61fce83..fcb009f 100644 --- a/syn/project_1.xpr +++ b/syn/Zedboard/rtps-fpga.xpr @@ -3,10 +3,10 @@ - + -