From 746b273cff8acee6a51d9ff1cbabb8ee23801a15 Mon Sep 17 00:00:00 2001 From: Greek Date: Tue, 30 Nov 2021 12:54:18 +0100 Subject: [PATCH] Fix Avalon_MM_wrapper Byte Ordering According to Avalon MM Interface Specification, the Bus is in Little Endian. --- src/Avalon_MM_wrapper.vhd | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/src/Avalon_MM_wrapper.vhd b/src/Avalon_MM_wrapper.vhd index ebdf46e..37ef7f5 100644 --- a/src/Avalon_MM_wrapper.vhd +++ b/src/Avalon_MM_wrapper.vhd @@ -2,6 +2,8 @@ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; +use work.rtps_config_package.all; + entity Avalon_MM_wrapper is generic ( DATA_WIDTH : integer := 32 @@ -51,7 +53,8 @@ begin if (write = '1') then case (to_integer(unsigned(address))) is when 2 => - data_ri <= writedata; + -- NOTE: Avalon-MM interface specification requires little endian ordering. [Embedded Design Handbook, Chapter 11, ED51012-1.1] + data_ri <= endian_swap('1', writedata); if (full_ri = '1') then -- Stall Avalon MM waitrequest <= '1'; @@ -66,7 +69,8 @@ begin when 0 => readdata(0) <= not empty_ro; when 1 => - readdata <= data_ro; + -- NOTE: Avalon-MM interface specification requires little endian ordering. [Embedded Design Handbook, Chapter 11, ED51012-1.1] + readdata <= endian_swap('1',data_ro); if (empty_ro = '1') then -- Stall Avalon MM waitrequest <= '1';