diff --git a/sim/L0_dds_reader_test1_arzkriu.do b/sim/L0_dds_reader_test1_arzkriu.do index f979273..05c04d0 100644 --- a/sim/L0_dds_reader_test1_arzkriu.do +++ b/sim/L0_dds_reader_test1_arzkriu.do @@ -40,15 +40,15 @@ add wave -noupdate /l0_dds_reader_test1_arzkriu/uut/clk add wave -noupdate /l0_dds_reader_test1_arzkriu/uut/reset add wave -noupdate /l0_dds_reader_test1_arzkriu/uut/time add wave -noupdate -divider RTPS -add wave -noupdate -expand -group RTPS /l0_dds_reader_test1_arzkriu/uut/start_rtps -add wave -noupdate -expand -group RTPS /l0_dds_reader_test1_arzkriu/uut/opcode_rtps -add wave -noupdate -expand -group RTPS /l0_dds_reader_test1_arzkriu/uut/ack_rtps -add wave -noupdate -expand -group RTPS /l0_dds_reader_test1_arzkriu/uut/ret_rtps -add wave -noupdate -expand -group RTPS /l0_dds_reader_test1_arzkriu/uut/done_rtps -add wave -noupdate -expand -group RTPS /l0_dds_reader_test1_arzkriu/uut/ready_in_rtps -add wave -noupdate -expand -group RTPS /l0_dds_reader_test1_arzkriu/uut/valid_in_rtps -add wave -noupdate -expand -group RTPS -radix hexadecimal /l0_dds_reader_test1_arzkriu/uut/data_in_rtps -add wave -noupdate -expand -group RTPS /l0_dds_reader_test1_arzkriu/uut/last_word_in_rtps +add wave -noupdate -group RTPS /l0_dds_reader_test1_arzkriu/uut/start_rtps +add wave -noupdate -group RTPS /l0_dds_reader_test1_arzkriu/uut/opcode_rtps +add wave -noupdate -group RTPS /l0_dds_reader_test1_arzkriu/uut/ack_rtps +add wave -noupdate -group RTPS /l0_dds_reader_test1_arzkriu/uut/ret_rtps +add wave -noupdate -group RTPS /l0_dds_reader_test1_arzkriu/uut/done_rtps +add wave -noupdate -group RTPS /l0_dds_reader_test1_arzkriu/uut/ready_in_rtps +add wave -noupdate -group RTPS /l0_dds_reader_test1_arzkriu/uut/valid_in_rtps +add wave -noupdate -group RTPS -radix hexadecimal /l0_dds_reader_test1_arzkriu/uut/data_in_rtps +add wave -noupdate -group RTPS /l0_dds_reader_test1_arzkriu/uut/last_word_in_rtps add wave -noupdate -divider DDS add wave -noupdate -group DDS /l0_dds_reader_test1_arzkriu/uut/start_dds add wave -noupdate -group DDS /l0_dds_reader_test1_arzkriu/uut/ack_dds @@ -61,19 +61,9 @@ add wave -noupdate -group DDS -radix unsigned /l0_dds_reader_test1_arzkriu/uut/m add wave -noupdate -group DDS -radix DDS_RETCODE /l0_dds_reader_test1_arzkriu/uut/return_code_dds add wave -noupdate -group DDS /l0_dds_reader_test1_arzkriu/uut/done_dds add wave -noupdate -group DDS -divider SI -add wave -noupdate -group DDS -radix SAMPLE_STATE /l0_dds_reader_test1_arzkriu/uut/si_sample_state -add wave -noupdate -group DDS -radix VIEW_STATE /l0_dds_reader_test1_arzkriu/uut/si_view_state -add wave -noupdate -group DDS -radix INSTANCE_STATE /l0_dds_reader_test1_arzkriu/uut/si_instance_state -add wave -noupdate -group DDS -radix unsigned /l0_dds_reader_test1_arzkriu/uut/si_source_timestamp -add wave -noupdate -group DDS -radix hexadecimal /l0_dds_reader_test1_arzkriu/uut/si_instance_handle -add wave -noupdate -group DDS -radix hexadecimal /l0_dds_reader_test1_arzkriu/uut/si_publication_handle -add wave -noupdate -group DDS -radix unsigned /l0_dds_reader_test1_arzkriu/uut/si_disposed_generation_count -add wave -noupdate -group DDS -radix unsigned /l0_dds_reader_test1_arzkriu/uut/si_no_writers_generation_count -add wave -noupdate -group DDS -radix unsigned /l0_dds_reader_test1_arzkriu/uut/si_sample_rank -add wave -noupdate -group DDS -radix unsigned /l0_dds_reader_test1_arzkriu/uut/si_generation_rank -add wave -noupdate -group DDS -radix unsigned /l0_dds_reader_test1_arzkriu/uut/si_absolute_generation_rank -add wave -noupdate -group DDS /l0_dds_reader_test1_arzkriu/uut/si_valid_data -add wave -noupdate -group DDS /l0_dds_reader_test1_arzkriu/uut/si_valid +add wave -noupdate -group DDS -radix hexadecimal -childformat {{/l0_dds_reader_test1_arzkriu/uut/sample_info.sample_state -radix unsigned} {/l0_dds_reader_test1_arzkriu/uut/sample_info.view_state -radix unsigned} {/l0_dds_reader_test1_arzkriu/uut/sample_info.instance_state -radix unsigned} {/l0_dds_reader_test1_arzkriu/uut/sample_info.source_timestamp -radix unsigned} {/l0_dds_reader_test1_arzkriu/uut/sample_info.instance_handle -radix hexadecimal} {/l0_dds_reader_test1_arzkriu/uut/sample_info.publication_handle -radix hexadecimal} {/l0_dds_reader_test1_arzkriu/uut/sample_info.disposed_generation_count -radix unsigned} {/l0_dds_reader_test1_arzkriu/uut/sample_info.no_writers_generation_count -radix unsigned} {/l0_dds_reader_test1_arzkriu/uut/sample_info.sample_rank -radix unsigned} {/l0_dds_reader_test1_arzkriu/uut/sample_info.generation_rank -radix unsigned} {/l0_dds_reader_test1_arzkriu/uut/sample_info.absolute_generation_rank -radix unsigned} {/l0_dds_reader_test1_arzkriu/uut/sample_info.valid_data -radix hexadecimal}} -expand -subitemconfig {/l0_dds_reader_test1_arzkriu/uut/sample_info.sample_state {-height 15 -radix unsigned} /l0_dds_reader_test1_arzkriu/uut/sample_info.view_state {-height 15 -radix unsigned} /l0_dds_reader_test1_arzkriu/uut/sample_info.instance_state {-height 15 -radix unsigned} /l0_dds_reader_test1_arzkriu/uut/sample_info.source_timestamp {-height 15 -radix unsigned} /l0_dds_reader_test1_arzkriu/uut/sample_info.instance_handle {-height 15 -radix hexadecimal} /l0_dds_reader_test1_arzkriu/uut/sample_info.publication_handle {-height 15 -radix hexadecimal} /l0_dds_reader_test1_arzkriu/uut/sample_info.disposed_generation_count {-height 15 -radix unsigned} /l0_dds_reader_test1_arzkriu/uut/sample_info.no_writers_generation_count {-height 15 -radix unsigned} /l0_dds_reader_test1_arzkriu/uut/sample_info.sample_rank {-height 15 -radix unsigned} /l0_dds_reader_test1_arzkriu/uut/sample_info.generation_rank {-height 15 -radix unsigned} /l0_dds_reader_test1_arzkriu/uut/sample_info.absolute_generation_rank {-height 15 -radix unsigned} /l0_dds_reader_test1_arzkriu/uut/sample_info.valid_data {-radix hexadecimal}} /l0_dds_reader_test1_arzkriu/uut/sample_info +add wave -noupdate -group DDS /l0_dds_reader_test1_arzkriu/uut/sample_info_valid +add wave -noupdate -group DDS /l0_dds_reader_test1_arzkriu/uut/sample_info_ack add wave -noupdate -group DDS /l0_dds_reader_test1_arzkriu/uut/eoc add wave -noupdate -group DDS /l0_dds_reader_test1_arzkriu/uut/get_data_dds add wave -noupdate -group DDS -divider OUTPUT @@ -83,9 +73,16 @@ add wave -noupdate -group DDS -radix hexadecimal /l0_dds_reader_test1_arzkriu/uu add wave -noupdate -group DDS /l0_dds_reader_test1_arzkriu/uut/last_word_out_dds add wave -noupdate -divider {MAIN FSM} add wave -noupdate /l0_dds_reader_test1_arzkriu/uut/stage -add wave -noupdate /l0_dds_reader_test1_arzkriu/uut/stage_next add wave -noupdate /l0_dds_reader_test1_arzkriu/uut/cnt add wave -noupdate -divider MEMORY +add wave -noupdate /l0_dds_reader_test1_arzkriu/uut/inst_op_start +add wave -noupdate /l0_dds_reader_test1_arzkriu/uut/inst_opcode +add wave -noupdate /l0_dds_reader_test1_arzkriu/uut/inst_op_done +add wave -noupdate /l0_dds_reader_test1_arzkriu/uut/inst_stage +add wave -noupdate /l0_dds_reader_test1_arzkriu/uut/inst_cnt +add wave -noupdate -radix unsigned /l0_dds_reader_test1_arzkriu/uut/inst_addr_base +add wave -noupdate -childformat {{/l0_dds_reader_test1_arzkriu/uut/inst_data.key_hash -radix hexadecimal} {/l0_dds_reader_test1_arzkriu/uut/inst_data.status_info -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.sample_cnt -radix unsigned} {/l0_dds_reader_test1_arzkriu/uut/inst_data.disposed_gen_cnt -radix unsigned} {/l0_dds_reader_test1_arzkriu/uut/inst_data.no_writers_gen_cnt -radix unsigned} {/l0_dds_reader_test1_arzkriu/uut/inst_data.ignore_deadline -radix unsigned} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap -radix binary -childformat {{/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0) -radix binary -childformat {{/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(0) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(1) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(2) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(3) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(4) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(5) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(6) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(7) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(8) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(9) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(10) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(11) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(12) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(13) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(14) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(15) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(16) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(17) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(18) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(19) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(20) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(21) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(22) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(23) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(24) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(25) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(26) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(27) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(28) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(29) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(30) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(31) -radix binary}}}}}} -subitemconfig {/l0_dds_reader_test1_arzkriu/uut/inst_data.key_hash {-height 15 -radix hexadecimal} /l0_dds_reader_test1_arzkriu/uut/inst_data.status_info {-height 15 -radix binary} /l0_dds_reader_test1_arzkriu/uut/inst_data.sample_cnt {-height 15 -radix unsigned} /l0_dds_reader_test1_arzkriu/uut/inst_data.disposed_gen_cnt {-height 15 -radix unsigned} /l0_dds_reader_test1_arzkriu/uut/inst_data.no_writers_gen_cnt {-height 15 -radix unsigned} /l0_dds_reader_test1_arzkriu/uut/inst_data.ignore_deadline {-height 15 -radix unsigned} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap {-height 15 -radix binary -childformat {{/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0) -radix binary -childformat {{/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(0) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(1) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(2) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(3) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(4) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(5) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(6) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(7) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(8) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(9) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(10) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(11) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(12) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(13) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(14) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(15) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(16) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(17) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(18) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(19) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(20) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(21) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(22) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(23) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(24) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(25) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(26) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(27) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(28) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(29) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(30) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(31) -radix binary}}}}} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0) {-height 15 -radix binary -childformat {{/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(0) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(1) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(2) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(3) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(4) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(5) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(6) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(7) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(8) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(9) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(10) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(11) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(12) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(13) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(14) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(15) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(16) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(17) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(18) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(19) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(20) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(21) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(22) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(23) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(24) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(25) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(26) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(27) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(28) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(29) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(30) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(31) -radix binary}}} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(0) {-height 15 -radix binary} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(1) {-height 15 -radix binary} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(2) {-height 15 -radix binary} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(3) {-height 15 -radix binary} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(4) {-height 15 -radix binary} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(5) {-height 15 -radix binary} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(6) {-height 15 -radix binary} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(7) {-height 15 -radix binary} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(8) {-height 15 -radix binary} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(9) {-height 15 -radix binary} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(10) {-height 15 -radix binary} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(11) {-height 15 -radix binary} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(12) {-height 15 -radix binary} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(13) {-height 15 -radix binary} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(14) {-height 15 -radix binary} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(15) {-height 15 -radix binary} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(16) {-height 15 -radix binary} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(17) {-height 15 -radix binary} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(18) {-height 15 -radix binary} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(19) {-height 15 -radix binary} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(20) {-height 15 -radix binary} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(21) {-height 15 -radix binary} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(22) {-height 15 -radix binary} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(23) {-height 15 -radix binary} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(24) {-height 15 -radix binary} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(25) {-height 15 -radix binary} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(26) {-height 15 -radix binary} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(27) {-height 15 -radix binary} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(28) {-height 15 -radix binary} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(29) {-height 15 -radix binary} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(30) {-height 15 -radix binary} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(31) {-height 15 -radix binary}} /l0_dds_reader_test1_arzkriu/uut/inst_data +add wave -noupdate /l0_dds_reader_test1_arzkriu/uut/stale_inst_cnt add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test1_arzkriu/uut/sample_abort_read add wave -noupdate -group {SAMPLE MEM} -radix unsigned /l0_dds_reader_test1_arzkriu/uut/sample_mem_ctrl_inst/addr add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test1_arzkriu/uut/sample_mem_ctrl_inst/read @@ -113,19 +110,6 @@ add wave -noupdate -group {INSTANCE MEM} -radix hexadecimal /l0_dds_reader_test1 add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test1_arzkriu/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/ready_out add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test1_arzkriu/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/valid_out add wave -noupdate -group {INSTANCE MEM} -radix hexadecimal /l0_dds_reader_test1_arzkriu/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/data_out -add wave -noupdate /l0_dds_reader_test1_arzkriu/uut/inst_op_start -add wave -noupdate /l0_dds_reader_test1_arzkriu/uut/inst_opcode -add wave -noupdate /l0_dds_reader_test1_arzkriu/uut/inst_op_done -add wave -noupdate /l0_dds_reader_test1_arzkriu/uut/inst_stage -add wave -noupdate /l0_dds_reader_test1_arzkriu/uut/inst_stage_next -add wave -noupdate /l0_dds_reader_test1_arzkriu/uut/inst_cnt -add wave -noupdate -radix unsigned /l0_dds_reader_test1_arzkriu/uut/inst_addr_base -add wave -noupdate /l0_dds_reader_test1_arzkriu/uut/inst_mem_fields -add wave -noupdate -childformat {{/l0_dds_reader_test1_arzkriu/uut/inst_data.key_hash -radix hexadecimal} {/l0_dds_reader_test1_arzkriu/uut/inst_data.status_info -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.sample_cnt -radix unsigned} {/l0_dds_reader_test1_arzkriu/uut/inst_data.disposed_gen_cnt -radix unsigned} {/l0_dds_reader_test1_arzkriu/uut/inst_data.no_writers_gen_cnt -radix unsigned} {/l0_dds_reader_test1_arzkriu/uut/inst_data.ignore_deadline -radix unsigned} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap -radix binary -childformat {{/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0) -radix binary -childformat {{/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(0) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(1) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(2) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(3) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(4) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(5) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(6) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(7) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(8) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(9) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(10) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(11) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(12) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(13) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(14) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(15) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(16) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(17) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(18) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(19) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(20) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(21) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(22) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(23) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(24) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(25) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(26) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(27) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(28) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(29) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(30) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(31) -radix binary}}}}}} -expand -subitemconfig {/l0_dds_reader_test1_arzkriu/uut/inst_data.key_hash {-height 15 -radix hexadecimal} /l0_dds_reader_test1_arzkriu/uut/inst_data.status_info {-height 15 -radix binary} /l0_dds_reader_test1_arzkriu/uut/inst_data.sample_cnt {-height 15 -radix unsigned} /l0_dds_reader_test1_arzkriu/uut/inst_data.disposed_gen_cnt {-height 15 -radix unsigned} /l0_dds_reader_test1_arzkriu/uut/inst_data.no_writers_gen_cnt {-height 15 -radix unsigned} /l0_dds_reader_test1_arzkriu/uut/inst_data.ignore_deadline {-height 15 -radix unsigned} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap {-height 15 -radix binary -childformat {{/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0) -radix binary -childformat {{/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(0) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(1) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(2) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(3) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(4) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(5) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(6) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(7) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(8) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(9) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(10) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(11) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(12) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(13) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(14) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(15) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(16) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(17) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(18) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(19) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(20) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(21) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(22) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(23) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(24) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(25) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(26) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(27) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(28) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(29) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(30) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(31) -radix binary}}}}} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0) {-height 15 -radix binary -childformat {{/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(0) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(1) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(2) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(3) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(4) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(5) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(6) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(7) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(8) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(9) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(10) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(11) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(12) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(13) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(14) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(15) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(16) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(17) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(18) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(19) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(20) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(21) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(22) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(23) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(24) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(25) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(26) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(27) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(28) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(29) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(30) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(31) -radix binary}}} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(0) {-height 15 -radix binary} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(1) {-height 15 -radix binary} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(2) {-height 15 -radix binary} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(3) {-height 15 -radix binary} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(4) {-height 15 -radix binary} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(5) {-height 15 -radix binary} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(6) {-height 15 -radix binary} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(7) {-height 15 -radix binary} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(8) {-height 15 -radix binary} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(9) {-height 15 -radix binary} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(10) {-height 15 -radix binary} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(11) {-height 15 -radix binary} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(12) {-height 15 -radix binary} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(13) {-height 15 -radix binary} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(14) {-height 15 -radix binary} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(15) {-height 15 -radix binary} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(16) {-height 15 -radix binary} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(17) {-height 15 -radix binary} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(18) {-height 15 -radix binary} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(19) {-height 15 -radix binary} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(20) {-height 15 -radix binary} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(21) {-height 15 -radix binary} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(22) {-height 15 -radix binary} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(23) {-height 15 -radix binary} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(24) {-height 15 -radix binary} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(25) {-height 15 -radix binary} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(26) {-height 15 -radix binary} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(27) {-height 15 -radix binary} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(28) {-height 15 -radix binary} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(29) {-height 15 -radix binary} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(30) {-height 15 -radix binary} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(31) {-height 15 -radix binary}} /l0_dds_reader_test1_arzkriu/uut/inst_data -add wave -noupdate -radix unsigned /l0_dds_reader_test1_arzkriu/uut/inst_next_addr_base -add wave -noupdate -radix unsigned /l0_dds_reader_test1_arzkriu/uut/inst_prev_addr_base -add wave -noupdate /l0_dds_reader_test1_arzkriu/uut/current_imf -add wave -noupdate /l0_dds_reader_test1_arzkriu/uut/stale_inst_cnt add wave -noupdate -divider POINTERS add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test1_arzkriu/uut/empty_sample_list_head add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test1_arzkriu/uut/empty_sample_list_tail @@ -134,13 +118,13 @@ add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test1_a add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test1_arzkriu/uut/newest_sample add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test1_arzkriu/uut/inst_empty_head add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test1_arzkriu/uut/inst_occupied_head -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test1_arzkriu/uut/cur_sample -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test1_arzkriu/uut/next_sample -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test1_arzkriu/uut/prev_sample -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test1_arzkriu/uut/cur_payload -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test1_arzkriu/uut/next_payload -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test1_arzkriu/uut/cur_inst -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test1_arzkriu/uut/next_inst +add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test1_arzkriu/uut/cur_sample +add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test1_arzkriu/uut/next_sample +add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test1_arzkriu/uut/prev_sample +add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test1_arzkriu/uut/cur_payload +add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test1_arzkriu/uut/next_payload +add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test1_arzkriu/uut/cur_inst +add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test1_arzkriu/uut/next_inst add wave -noupdate -divider MISC add wave -noupdate /l0_dds_reader_test1_arzkriu/uut/trigger_sample_gen add wave -noupdate /l0_dds_reader_test1_arzkriu/uut/wait_for_sample_removal @@ -177,7 +161,7 @@ add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test1_arzkriu/uut/ready_ou add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test1_arzkriu/uut/last_word_out_kh add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test1_arzkriu/uut/abort_kh TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {77695423 ps} 0} {{Cursor 2} {115175000 ps} 1} +WaveRestoreCursors {{Cursor 1} {9775000 ps} 0} quietly wave cursor active 1 configure wave -namecolwidth 187 configure wave -valuecolwidth 206 @@ -193,4 +177,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {76925214 ps} {77858935 ps} +WaveRestoreZoom {6112965 ps} {7046686 ps} diff --git a/sim/L0_dds_writer_test1_aik.do b/sim/L0_dds_writer_test1_aik.do index b687f6d..fbe93d3 100644 --- a/sim/L0_dds_writer_test1_aik.do +++ b/sim/L0_dds_writer_test1_aik.do @@ -23,7 +23,6 @@ add wave -noupdate -group {RTPS OUT} -radix hexadecimal /l0_dds_writer_test1_aik add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test1_aik/uut/last_word_out_rtps add wave -noupdate -divider {DDS IN} add wave -noupdate -expand -group DDS /l0_dds_writer_test1_aik/uut/start_dds -add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_writer_test1_aik/uut/instance_handle_dds add wave -noupdate -expand -group DDS -radix unsigned /l0_dds_writer_test1_aik/uut/source_ts_dds add wave -noupdate -expand -group DDS /l0_dds_writer_test1_aik/uut/opcode_dds add wave -noupdate -expand -group DDS /l0_dds_writer_test1_aik/uut/ack_dds @@ -39,7 +38,6 @@ add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_writer_test1_ai add wave -noupdate -expand -group DDS /l0_dds_writer_test1_aik/uut/last_word_out_dds add wave -noupdate -divider {MAIN FSM} add wave -noupdate /l0_dds_writer_test1_aik/uut/stage -add wave -noupdate /l0_dds_writer_test1_aik/uut/stage_next add wave -noupdate /l0_dds_writer_test1_aik/uut/cnt add wave -noupdate -radix unsigned /l0_dds_writer_test1_aik/uut/global_seq_nr add wave -noupdate -radix unsigned /l0_dds_writer_test1_aik/uut/global_sample_cnt @@ -71,7 +69,6 @@ add wave -noupdate /l0_dds_writer_test1_aik/uut/inst_op_start add wave -noupdate /l0_dds_writer_test1_aik/uut/inst_opcode add wave -noupdate /l0_dds_writer_test1_aik/uut/inst_op_done add wave -noupdate /l0_dds_writer_test1_aik/uut/inst_stage -add wave -noupdate /l0_dds_writer_test1_aik/uut/inst_stage_next add wave -noupdate /l0_dds_writer_test1_aik/uut/inst_cnt add wave -noupdate -radix unsigned /l0_dds_writer_test1_aik/uut/inst_addr_base add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test1_aik/uut/inst_abort_read @@ -83,9 +80,7 @@ add wave -noupdate -group {INSTANCE MEM} -radix hexadecimal /l0_dds_writer_test1 add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test1_aik/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/ready_out add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test1_aik/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/valid_out add wave -noupdate -group {INSTANCE MEM} -radix hexadecimal /l0_dds_writer_test1_aik/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/data_out -add wave -noupdate -childformat {{/l0_dds_writer_test1_aik/uut/inst_data.key_hash -radix hexadecimal} {/l0_dds_writer_test1_aik/uut/inst_data.status_info -radix binary} {/l0_dds_writer_test1_aik/uut/inst_data.sample_cnt -radix unsigned} {/l0_dds_writer_test1_aik/uut/inst_data.ack_cnt -radix unsigned}} -expand -subitemconfig {/l0_dds_writer_test1_aik/uut/inst_data.key_hash {-height 15 -radix hexadecimal} /l0_dds_writer_test1_aik/uut/inst_data.status_info {-height 15 -radix binary} /l0_dds_writer_test1_aik/uut/inst_data.sample_cnt {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/inst_data.ack_cnt {-height 15 -radix unsigned}} /l0_dds_writer_test1_aik/uut/inst_data -add wave -noupdate -radix unsigned /l0_dds_writer_test1_aik/uut/inst_next_addr_base -add wave -noupdate -radix unsigned /l0_dds_writer_test1_aik/uut/inst_prev_addr_base +add wave -noupdate -childformat {{/l0_dds_writer_test1_aik/uut/inst_data.addr -radix unsigned} {/l0_dds_writer_test1_aik/uut/inst_data.key_hash -radix hexadecimal} {/l0_dds_writer_test1_aik/uut/inst_data.status_info -radix binary} {/l0_dds_writer_test1_aik/uut/inst_data.sample_cnt -radix unsigned} {/l0_dds_writer_test1_aik/uut/inst_data.ack_cnt -radix unsigned}} -subitemconfig {/l0_dds_writer_test1_aik/uut/inst_data.addr {-radix unsigned} /l0_dds_writer_test1_aik/uut/inst_data.key_hash {-height 15 -radix hexadecimal} /l0_dds_writer_test1_aik/uut/inst_data.status_info {-height 15 -radix binary} /l0_dds_writer_test1_aik/uut/inst_data.sample_cnt {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/inst_data.ack_cnt {-height 15 -radix unsigned}} /l0_dds_writer_test1_aik/uut/inst_data add wave -noupdate -divider {KEY HOLDER} add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test1_aik/uut/start_kh add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test1_aik/uut/opcode_kh @@ -115,23 +110,13 @@ add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test1_aik/uut/cur_inst add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test1_aik/uut/next_inst add wave -noupdate -divider TESTBENCH -add wave -noupdate -group TESTBENCH /l0_dds_writer_test1_aik/stim_start -add wave -noupdate -group TESTBENCH /l0_dds_writer_test1_aik/stim_stage -add wave -noupdate -group TESTBENCH /l0_dds_writer_test1_aik/stim_cnt -add wave -noupdate -group TESTBENCH /l0_dds_writer_test1_aik/stim_done -add wave -noupdate -group TESTBENCH /l0_dds_writer_test1_aik/ref_start -add wave -noupdate -group TESTBENCH /l0_dds_writer_test1_aik/ref_stage -add wave -noupdate -group TESTBENCH /l0_dds_writer_test1_aik/ref_cnt -add wave -noupdate -group TESTBENCH /l0_dds_writer_test1_aik/ref_done -add wave -noupdate -group TESTBENCH /l0_dds_writer_test1_aik/kh_cnt -add wave -noupdate -group TESTBENCH /l0_dds_writer_test1_aik/kh_stage add wave -noupdate -divider MISC add wave -noupdate /l0_dds_writer_test1_aik/uut/cnt2 add wave -noupdate /l0_dds_writer_test1_aik/uut/cnt3 add wave -noupdate -radix unsigned /l0_dds_writer_test1_aik/uut/long_latch add wave -noupdate /l0_dds_writer_test1_aik/uut/sample_status_info TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {106575000 ps} 0} +WaveRestoreCursors {{Cursor 1} {34725000 ps} 0} quietly wave cursor active 1 configure wave -namecolwidth 187 configure wave -valuecolwidth 100 @@ -147,4 +132,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {106074680 ps} {107075321 ps} +WaveRestoreZoom {34274712 ps} {35275353 ps} diff --git a/src/REF.txt b/src/REF.txt index aaa8c5e..9626085 100644 --- a/src/REF.txt +++ b/src/REF.txt @@ -603,27 +603,29 @@ READER +---------------------------------------------------------------+ 00| NEXT_ADDRESS | +---------------------------------------------------------------+ -01| | - + + +01| PREV_ADDRESS | + +---------------------------------------------------------------+ 02| | - + KEY_HASH + -03| | + + +03| | + + KEY_HASH + 04| | + + + +05| | +---------------------------------------------------------------+ -05| STATUS_INFO | +06| STATUS_INFO | +---------------------------------------------------------------+ -06| SAMPLE_COUNT | +07| SAMPLE_COUNT | +---------------------------------------------------------------+ -07| DISPOSED_GENERATION_COUNT | +08| DISPOSED_GENERATION_COUNT | +---------------------------------------------------------------+ -08| NO_WRITERS_GENERATION_COUNT | +09| NO_WRITERS_GENERATION_COUNT | +---------------------------------------------------------------+ -09| | - + IGNORE_DEADLINE + [only TIME_BASED_FILTER] 10| | - +---------------------------------------------------------------+ + + IGNORE_DEADLINE + [only TIME_BASED_FILTER] 11| | + +---------------------------------------------------------------+ +12| | ~ WRITER_BITMAP ~ **| | +---------------------------------------------------------------+ @@ -652,19 +654,21 @@ WRITER +---------------------------------------------------------------+ 00| NEXT_ADDRESS | +---------------------------------------------------------------+ -01| | - + + +01| PREV_ADDRESS | + +---------------------------------------------------------------+ 02| | - + KEY_HASH + -03| | + + +03| | + + KEY_HASH + 04| | + + + +05| | +---------------------------------------------------------------+ -05| STATUS_INFO | +06| STATUS_INFO | +---------------------------------------------------------------+ -06| SAMPLE_COUNT | +07| SAMPLE_COUNT | +---------------------------------------------------------------+ -07| ACK_COUNT | +08| ACK_COUNT | +---------------------------------------------------------------+ diff --git a/src/dds_reader.vhd b/src/dds_reader.vhd index b81673b..9abfd31 100644 --- a/src/dds_reader.vhd +++ b/src/dds_reader.vhd @@ -144,9 +144,9 @@ architecture arch of dds_reader is variable ret : natural := 0; begin if (time_based_filter = DURATION_ZERO) then - return 9 + round_div(MAX_REMOTE_ENDPOINTS, WORD_WIDTH); + return 10 + round_div(MAX_REMOTE_ENDPOINTS, WORD_WIDTH); else - return 11 + round_div(MAX_REMOTE_ENDPOINTS, WORD_WIDTH); + return 12 + round_div(MAX_REMOTE_ENDPOINTS, WORD_WIDTH); end if; end function; constant INSTANCE_FRAME_SIZE : natural := gen_inst_frame_size(TIME_BASED_FILTER_QOS); @@ -191,12 +191,13 @@ architecture arch of dds_reader is -- *INSTANCE MEMORY FRAME FIELD OFFSETS* -- 4-Byte Word Offsets to Beginning of Respective Fields in the Endpoint Memory Frame constant IMF_NEXT_ADDR_OFFSET : natural := 0; - constant IMF_KEY_HASH_OFFSET : natural := 1; - constant IMF_STATUS_INFO_OFFSET : natural := 5; - constant IMF_SAMPLE_CNT_OFFSET : natural := 6; - constant IMF_DISPOSED_GEN_CNT_OFFSET : natural := 7; - constant IMF_NO_WRITERS_GEN_CNT_OFFSET : natural := 8; - constant IMF_IGNORE_DEADLINE_OFFSET : natural := 9; + constant IMF_PREV_ADDR_OFFSET : natural := 1; + constant IMF_KEY_HASH_OFFSET : natural := 2; + constant IMF_STATUS_INFO_OFFSET : natural := 6; + constant IMF_SAMPLE_CNT_OFFSET : natural := 7; + constant IMF_DISPOSED_GEN_CNT_OFFSET : natural := 8; + constant IMF_NO_WRITERS_GEN_CNT_OFFSET : natural := 9; + constant IMF_IGNORE_DEADLINE_OFFSET : natural := 10; function gen_imf_writer_bitmap_offset(time_based_filter : DURATION_TYPE) return natural is variable ret : natural := 0; begin @@ -222,39 +223,36 @@ architecture arch of dds_reader is --*****TYPE DECLARATION***** -- FSM states. Explained below in detail - type STAGE_TYPE is (IDLE, RETURN_DDS, RETURN_RTPS, ADD_SAMPLE_INFO, ADD_PAYLOAD_ADDRESS, ADD_PAYLOAD, NEXT_PAYLOAD_SLOT, ALIGN_PAYLOAD, GET_KEY_HASH, INITIATE_INSTANCE_SEARCH, + type STAGE_TYPE is (IDLE, RETURN_DDS, RETURN_RTPS, ADD_SAMPLE_INFO, ADD_PAYLOAD, NEXT_PAYLOAD_SLOT, ALIGN_PAYLOAD, GET_KEY_HASH, INITIATE_INSTANCE_SEARCH, FILTER_STAGE, UPDATE_INSTANCE, FINALIZE_PAYLOAD, PRE_SAMPLE_FINALIZE, FIND_POS, FIX_POINTERS, FINALIZE_SAMPLE, GENERATE_SAMPLE, GET_OLDEST_SAMPLE_INSTANCE, FIND_OLDEST_INST_SAMPLE, REMOVE_SAMPLE, POST_SAMPLE_REMOVE, SKIP_AND_RETURN, REMOVE_WRITER, REMOVE_STALE_INSTANCE, GET_NEXT_SAMPLE, PRE_CALCULATE, FINALIZE_SAMPLE_INFO, GET_PAYLOAD, FIND_NEXT_INSTANCE, CHECK_INSTANCE, CHECK_LIFESPAN, PROCESS_PENDING_SAMPLE_GENERATION, GET_SAMPLE_REJECTED_STATUS, GET_REQUESTED_DEADLINE_MISSED_STATUS, CHECK_DEADLINE, RESET_SAMPLE_MEMORY, RESET_PAYLOAD_MEMORY); -- Instance Memory FSM states. Explained below in detail - type INST_STAGE_TYPE is (IDLE, SEARCH_INSTANCE_HASH, SEARCH_INSTANCE_ADDR, GET_NEXT_INSTANCE, GET_INSTANCE_DATA, FIND_POS, INSERT_INSTANCE, UPDATE_INSTANCE, + type INST_STAGE_TYPE is (IDLE, SEARCH_INSTANCE, GET_NEXT_INSTANCE, GET_INSTANCE_DATA, FIND_POS, INSERT_INSTANCE, UPDATE_INSTANCE, REMOVE_INSTANCE, UNMARK_INSTANCES, RESET_MEMORY); -- *Instance Memory Opcodes* -- OPCODE DESCRIPTION - -- SEARCH_INSTANCE_HASH Search Instance based on Key Hash pointed by "key_hash". - -- Set "inst_addr_base" to Base Address of found Instance, of INSTANCE_MEMORY_MAX_ADDRESS if nothing found. - -- "inst_data" contains Instance Data according to "inst_mem_fields". - -- SEARCH_INSTANCE_ADDR Search Instance based on Instance Pointer pointed by "inst_addr_update". - -- Set "inst_addr_base" to "inst_addr_update" - -- "inst_data" contains Instance Data according to "inst_mem_fields". - -- INSERT_INSTANCE Insert Instance to memory. The Instance is inserted in Key Hash Numerical Order. - -- UPDATE_INSTANCE Update Instance Data pointed by "inst_addr_base" according to "inst_mem_fields" - -- GET_FIRST_INSTANCE Get Instance Data of first Instance (Instance with smallest Key Hash Numerical Order) according to "inst_mem_fields". - -- Set "inst_addr_base" to Address of Instance or INSTANCE_MEMORY_MAX_ADDRESS if no Instance in Memory. - -- GET_NEXT_INSTANCE Get Instance Data of next Instance (from the Instance pointed by "inst_addr_base") according to "inst_mem_fields". - -- Set "inst_addr_base" to Address of Instance or INSTANCE_MEMORY_MAX_ADDRESS if no other Instance in Memory. - -- REMOVE_INSTANCE Remove Instance pointed by "inst_addr_base". - -- GET_INSTANCE Get Data of Instance pointed by "inst_addr_update" according to "inst_mem_fields". + -- SEARCH_INSTANCE Search Instance based on Key Hash pointed by "inst_r.key_hash". + -- Set "inst_data.addr" to Base Address of found Instance, or INSTANCE_MEMORY_MAX_ADDRESS if nothing found. + -- "inst_data" contains Instance Data according to "inst_r.field_flags". + -- INSERT_INSTANCE Insert Instance to memory. + -- UPDATE_INSTANCE Update Instance Data pointed by "inst_data.addr" according to "inst_r.field_flags" + -- GET_INSTANCE Get Data of Instance pointed by "inst_r.addr" according to "inst_r.field_flags". -- Already fetched Data of the Participant is not modified. + -- GET_NEXT_INSTANCE Get Instance Data of next Instance (from the Instance pointed by "inst_data.addr") according to "inst_r.field_flags". + -- Set "inst_data.addr" to Address of Instance or INSTANCE_MEMORY_MAX_ADDRESS if no other Instance in Memory. + -- REMOVE_INSTANCE Remove Instance pointed by "inst_data.addr". + -- "inst_data.addr" is set to the next Instance (or INSTANCE_MEMORY_MAX_ADDRESS if no next Instance exists) -- UNMARK_INSTANCES Reset the MARK_FLAG of all Instances in Memory. - type INSTANCE_OPCODE_TYPE is (NOP, SEARCH_INSTANCE_HASH, SEARCH_INSTANCE_ADDR, INSERT_INSTANCE, UPDATE_INSTANCE, GET_FIRST_INSTANCE, GET_NEXT_INSTANCE, REMOVE_INSTANCE, + type INSTANCE_OPCODE_TYPE is (NOP, SEARCH_INSTANCE, INSERT_INSTANCE, UPDATE_INSTANCE, GET_FIRST_INSTANCE, GET_NEXT_INSTANCE, REMOVE_INSTANCE, GET_INSTANCE, UNMARK_INSTANCES); type WRITER_BITMAP_ARRAY_TYPE is array (0 to round_div(MAX_REMOTE_ENDPOINTS, WORD_WIDTH)-1) of std_logic_vector(0 to WORD_WIDTH-1); constant ZERO_WRITER_BITMAP_ARRAY : WRITER_BITMAP_ARRAY_TYPE := (others => (others => '0')); constant WRITER_BITMAP_WIDTH : natural := WRITER_BITMAP_ARRAY_TYPE'length*WORD_WIDTH; -- Record of Instance Data type INSTANCE_DATA_TYPE is record + addr : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0); key_hash : KEY_HASH_TYPE; status_info : std_logic_vector(WORD_WIDTH-1 downto 0); sample_cnt : unsigned(WORD_WIDTH-1 downto 0); @@ -262,38 +260,19 @@ architecture arch of dds_reader is no_writers_gen_cnt : unsigned(WORD_WIDTH-1 downto 0); ignore_deadline : TIME_TYPE; writer_bitmap : WRITER_BITMAP_ARRAY_TYPE; + field_flags : std_logic_vector(0 to IMF_FLAG_WIDTH-1); end record; -- Zero initialized Endpoint Data constant ZERO_INSTANCE_DATA : INSTANCE_DATA_TYPE := ( + addr => INSTANCE_MEMORY_MAX_ADDRESS, key_hash => KEY_HASH_NIL, status_info => (others => '0'), sample_cnt => (others => '0'), disposed_gen_cnt => (others => '0'), no_writers_gen_cnt => (others => '0'), ignore_deadline => TIME_INVALID, - writer_bitmap => ZERO_WRITER_BITMAP_ARRAY - ); - -- Instance Data Latch used as temporal cache by Instance Memory FSM - type INST_LATCH_DATA_TYPE is record - key_hash : KEY_HASH_TYPE; - status_info : std_logic_vector(CDR_LONG_WIDTH-1 downto 0); - sample_cnt : unsigned(CDR_LONG_WIDTH-1 downto 0); - gen_cnt : unsigned(CDR_LONG_WIDTH-1 downto 0); - deadline : TIME_TYPE; - writer_bitmap : WRITER_BITMAP_ARRAY_TYPE; - field_flags : std_logic_vector(0 to IMF_FLAG_WIDTH-1); - addr : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0); - end record; - -- Zero initialized Instance Data Latch - constant ZERO_INST_LATCH_DATA : INST_LATCH_DATA_TYPE := ( - key_hash => KEY_HASH_NIL, - status_info => (others => '0'), - sample_cnt => (others => '0'), - gen_cnt => (others => '0'), - deadline => TIME_INVALID, - writer_bitmap => ZERO_WRITER_BITMAP_ARRAY, - field_flags => (others => '0'), - addr => (others => '0') + writer_bitmap => ZERO_WRITER_BITMAP_ARRAY, + field_flags => (others => '0') ); --*****SIGNAL DECLARATION***** @@ -385,26 +364,14 @@ architecture arch of dds_reader is signal inst_addr_latch_2, inst_addr_latch_2_next : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0); -- General Purpose Long Latch signal long_latch, long_latch_next : std_logic_vector(CDR_LONG_WIDTH-1 downto 0); - -- Signal used to pass Writer Bitmaps to Instance Memory Process - signal writer_bitmap : WRITER_BITMAP_ARRAY_TYPE; - -- Signal used to pass Sample Status Infos to Instance Memory Process - signal status_info_update : std_logic_vector(CDR_LONG_WIDTH-1 downto 0); - -- Signal used to pass Generation Counters to the Instance Memory Process - signal gen_cnt : unsigned(CDR_LONG_WIDTH-1 downto 0); - -- Signal used to pass TIMEs to the Instance Memory Process - signal deadline : TIME_TYPE; - -- Signal containing the relevant Instance Memory Frame Fields of the Instance Memory Operation - signal inst_mem_fields : std_logic_vector(0 to IMF_FLAG_WIDTH-1); - -- Signal used to pass Instance Pointers to the Instance Memory Process - signal inst_addr_update : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0); - -- Signal used to pass Sample Counts to the Instance Memory Process - signal sample_cnt : unsigned(CDR_LONG_WIDTH-1 downto 0); -- Signals start of Instance Memory Operation signal inst_op_start : std_logic; -- Opcode of Instance Memory Operation (Valid only when inst_op_start is high) signal inst_opcode : INSTANCE_OPCODE_TYPE; -- Signals the end of an Instance Memory Operation signal inst_op_done : std_logic; + -- Signal used to pass data to instance memory process + signal inst_r : INSTANCE_DATA_TYPE; -- Time of next Sample Lifespan Check signal lifespan_time, lifespan_time_next : TIME_TYPE; -- Signifies if a Lifespan Check is in progress @@ -491,16 +458,14 @@ architecture arch of dds_reader is signal inst_stage, inst_stage_next : INST_STAGE_TYPE; -- Pointer to current relevant Instance Memory Frame Address signal inst_addr_base, inst_addr_base_next : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0); - -- Pointer to next Instance Memory Frame Address - signal inst_next_addr_base, inst_next_addr_base_next : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0); - -- Pointer to previous Instacne Memory Address - signal inst_prev_addr_base, inst_prev_addr_base_next : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0); + -- General Purpose Instance Memory Address Latch + signal inst_addr_latch, inst_addr_latch_next : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0); -- Head of Empty Instance List signal inst_empty_head, inst_empty_head_next : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0); -- Head of Occupied Instance List signal inst_occupied_head, inst_occupied_head_next : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0); -- Latch for Instance Data from main process - signal inst_latch_data, inst_latch_data_next : INST_LATCH_DATA_TYPE; + signal inst_latch_data, inst_latch_data_next : INSTANCE_DATA_TYPE; -- NOTE: The next signal is driven by the inst_ctrl_prc. In case WITH_KEY is FALSE, no inst_ctrl_prc is generated and the inst_data is -- set by the main process directly by drivng the next2 signal. The sync_prc is responsible for latching the corrct next signal. -- Latch for Instance Data from memory @@ -511,8 +476,6 @@ architecture arch of dds_reader is signal inst_cnt2, inst_cnt2_next : natural range 0 to WRITER_BITMAP_ARRAY_TYPE'length; -- General Purpose Long Latch signal inst_long_latch, inst_long_latch_next : std_logic_vector(CDR_LONG_WIDTH-1 downto 0); - -- Instance Memory Flag Array denoting which inst_data Fields are up-to-date with the respective fields of the Instance (Pointed by inst_addr_base) - signal current_imf, current_imf_next : std_logic_vector(0 to IMF_FLAG_WIDTH-1); --*****ALIAS DECLARATION***** alias prev_sample : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) is sample_addr_latch_1; @@ -574,6 +537,17 @@ architecture arch of dds_reader is end if; end function; + -- HACK: Due to delta cycle race condition some assertions trigger false positives, + -- so we check the signals on the falling edge + function stable(clk : std_logic; a : boolean) return boolean is + begin + if (clk = '0') then + return a; + else + return TRUE; + end if; + end function; + begin --*****COMPONENT INSTANTIATION***** @@ -685,7 +659,6 @@ begin -- RETURN_DDS Return latched DDS Return Code -- RETURN_RTPS Return latched RTPS Return Code -- ADD_SAMPLE_INFO Latch and store Cache Change (pre-payload) - -- ADD_PAYLOAD_ADDRESS Store payload pointer. -- ADD_PAYLOAD Push payload to memory and key hash generator (as needed) -- NEXT_PAYLOAD_SLOT Get pointer to next empty payload slot -- ALIGN_PAYLOAD Store the offset of the actual payload in the last address of the last payload slot. @@ -831,17 +804,11 @@ begin idle_sig <= '0'; data_out_dds <= (others => '0'); data_out_kh <= (others => '0'); - writer_bitmap <= ZERO_WRITER_BITMAP_ARRAY; - inst_addr_update <= (others => '0'); sample_addr <= (others => '0'); sample_write_data <= (others => '0'); payload_addr <= (others => '0'); payload_write_data <= (others => '0'); - inst_mem_fields <= (others => '0'); - status_info_update <= (others => '0'); - sample_cnt <= (others => '0'); - gen_cnt <= (others => '0'); - deadline <= TIME_INVALID; + inst_r <= ZERO_INSTANCE_DATA; @@ -916,7 +883,7 @@ begin remove_oldest_sample_next <= '1'; cur_sample_next <= empty_sample_list_head; - cur_inst_next <= inst_addr_base; + cur_inst_next <= inst_data.addr; stage_next <= GENERATE_SAMPLE; cnt_next <= 0; end if; @@ -929,7 +896,7 @@ begin inst_data_next2.sample_cnt <= inst_data.sample_cnt + 1; cur_sample_next <= empty_sample_list_head; - cur_inst_next <= inst_addr_base; + cur_inst_next <= inst_data.addr; stage_next <= GENERATE_SAMPLE; cnt_next <= 0; end if; @@ -1012,8 +979,8 @@ begin elsif (WITH_KEY and unmark_instances_flag = '1') then -- Memory Operation Guard if (inst_op_done = '1') then - inst_op_start <= '1'; - inst_opcode <= UNMARK_INSTANCES; + inst_op_start <= '1'; + inst_opcode <= UNMARK_INSTANCES; unmark_instances_flag_next <= '0'; end if; -- DDS Operation @@ -1444,8 +1411,8 @@ begin -- and key hash generator (KHG). This state is taken on following cases: -- has_data has_key_hash -- 1 1 The payload is written to memory [Entered from INITIATE_INSTANCE_SEARCH] - -- 1 0 The payload is written to memory and the KHG at the same time (KHG controls the flow) [Entered from ADD_PAYLOAD_ADDRESS] - -- 0 0 There is no payload to write, but the input contains the key for the KHG [Entered from ADD_PAYLOAD_ADDRESS] + -- 1 0 The payload is written to memory and the KHG at the same time (KHG controls the flow) + -- 0 0 There is no payload to write, but the input contains the key for the KHG case (cnt) is -- Push to memory @@ -1656,8 +1623,9 @@ begin -- Memory Operation Guard if (inst_op_done = '1') then inst_op_start <= '1'; - inst_opcode <= SEARCH_INSTANCE_HASH; - inst_mem_fields <= IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_DISPOSED_CNT_FLAG or IMF_NO_WRITERS_CNT_FLAG or IMF_IGNORE_DEADLINE_FLAG or IMF_WRITER_BITMAP_FLAG; + inst_opcode <= SEARCH_INSTANCE; + inst_r.key_hash <= key_hash; + inst_r.field_flags <= IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_DISPOSED_CNT_FLAG or IMF_NO_WRITERS_CNT_FLAG or IMF_IGNORE_DEADLINE_FLAG or IMF_WRITER_BITMAP_FLAG; -- Payload not yet stored if (has_data = '1' and WITH_KEY and has_key_hash = '1') then @@ -1674,12 +1642,12 @@ begin -- Wait for Instance Search to finish if (not WITH_KEY or inst_op_done = '1') then - assert (not WITH_KEY or check_mask(current_imf, IMF_STATUS_FLAG or IMF_IGNORE_DEADLINE_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_DISPOSED_CNT_FLAG or IMF_NO_WRITERS_CNT_FLAG)) severity FAILURE; - -- Instance Found - if (not WITH_KEY or inst_addr_base /= INSTANCE_MEMORY_MAX_ADDRESS) then + if (not WITH_KEY or inst_data.addr /= INSTANCE_MEMORY_MAX_ADDRESS) then + assert (not WITH_KEY or stable(clk,check_mask(inst_data.field_flags, IMF_STATUS_FLAG or IMF_IGNORE_DEADLINE_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_DISPOSED_CNT_FLAG or IMF_NO_WRITERS_CNT_FLAG))) severity FAILURE; + -- Latch Instance Pointer - cur_inst_next <= inst_addr_base; + cur_inst_next <= inst_data.addr; -- Latch Instance Generation Counters dis_gen_cnt_latch_next <= inst_data.disposed_gen_cnt; no_w_gen_cnt_latch_next <= inst_data.no_writers_gen_cnt; @@ -1822,11 +1790,12 @@ begin ret_rtps <= OK; -- Remove Stale Instance and Insert Instance - inst_op_start <= '1'; - inst_opcode <= GET_FIRST_INSTANCE; - inst_mem_fields <= IMF_SAMPLE_CNT_FLAG or IMF_WRITER_BITMAP_FLAG; - stage_next <= REMOVE_STALE_INSTANCE; - cnt_next <= 0; + inst_op_start <= '1'; + inst_opcode <= GET_INSTANCE; + inst_r.addr <= inst_occupied_head; + inst_r.field_flags <= IMF_SAMPLE_CNT_FLAG or IMF_WRITER_BITMAP_FLAG; + stage_next <= REMOVE_STALE_INSTANCE; + cnt_next <= 0; end if; else -- Accept Change (Remove Oldest Sample) @@ -1837,16 +1806,17 @@ begin -- Insert New Instance inst_op_start <= '1'; inst_opcode <= INSERT_INSTANCE; - status_info_update <= (ISI_LIVELINESS_FLAG => '1', ISI_NOT_ALIVE_DISPOSED_FLAG => sample_status_info(SSI_DISPOSED_FLAG), others => '0'); - sample_cnt <= to_unsigned(1, WORD_WIDTH); + inst_r.key_hash <= key_hash; + inst_r.status_info <= (ISI_LIVELINESS_FLAG => '1', ISI_NOT_ALIVE_DISPOSED_FLAG => sample_status_info(SSI_DISPOSED_FLAG), others => '0'); + inst_r.sample_cnt <= to_unsigned(1, WORD_WIDTH); if (TIME_BASED_FILTER_QOS /= DURATION_ZERO) then - deadline <= time + TIME_BASED_FILTER_QOS; + inst_r.ignore_deadline <= time + TIME_BASED_FILTER_QOS; else - deadline <= TIME_INVALID; + inst_r.ignore_deadline <= TIME_INVALID; end if; tmp_bitmap := (others => '0'); tmp_bitmap(writer_id) := '1'; - writer_bitmap <= to_writer_bitmap_array(tmp_bitmap); + inst_r.writer_bitmap <= to_writer_bitmap_array(tmp_bitmap); if (DESTINATION_ORDER_QOS = BY_SOURCE_TIMESTAMP_DESTINATION_ORDER_QOS and newest_sample /= SAMPLE_MEMORY_MAX_ADDRESS) then stage_next <= FIND_POS; @@ -1886,11 +1856,12 @@ begin ret_rtps <= OK; -- Remove Stale Instance and Insert Instance - inst_op_start <= '1'; - inst_opcode <= GET_FIRST_INSTANCE; - inst_mem_fields <= IMF_SAMPLE_CNT_FLAG or IMF_WRITER_BITMAP_FLAG; - stage_next <= REMOVE_STALE_INSTANCE; - cnt_next <= 0; + inst_op_start <= '1'; + inst_opcode <= GET_INSTANCE; + inst_r.addr <= inst_occupied_head; + inst_r.field_flags <= IMF_SAMPLE_CNT_FLAG or IMF_WRITER_BITMAP_FLAG; + stage_next <= REMOVE_STALE_INSTANCE; + cnt_next <= 0; end if; else -- Accept Change @@ -1900,16 +1871,17 @@ begin -- Insert New Instance inst_op_start <= '1'; inst_opcode <= INSERT_INSTANCE; - status_info_update <= (ISI_LIVELINESS_FLAG => '1', ISI_NOT_ALIVE_DISPOSED_FLAG => sample_status_info(SSI_DISPOSED_FLAG), others => '0'); - sample_cnt <= to_unsigned(1, WORD_WIDTH); + inst_r.key_hash <= key_hash; + inst_r.status_info <= (ISI_LIVELINESS_FLAG => '1', ISI_NOT_ALIVE_DISPOSED_FLAG => sample_status_info(SSI_DISPOSED_FLAG), others => '0'); + inst_r.sample_cnt <= to_unsigned(1, WORD_WIDTH); if (TIME_BASED_FILTER_QOS /= DURATION_ZERO) then - deadline <= time + TIME_BASED_FILTER_QOS; + inst_r.ignore_deadline <= time + TIME_BASED_FILTER_QOS; else - deadline <= TIME_INVALID; + inst_r.ignore_deadline <= TIME_INVALID; end if; tmp_bitmap := (others => '0'); tmp_bitmap(writer_id) := '1'; - writer_bitmap <= to_writer_bitmap_array(tmp_bitmap); + inst_r.writer_bitmap <= to_writer_bitmap_array(tmp_bitmap); if (DESTINATION_ORDER_QOS = BY_SOURCE_TIMESTAMP_DESTINATION_ORDER_QOS and newest_sample /= SAMPLE_MEMORY_MAX_ADDRESS) then stage_next <= FIND_POS; @@ -2139,13 +2111,14 @@ begin -- Memory Operation Guard if (not WITH_KEY or inst_op_done = '1') then - assert (not WITH_KEY or check_mask(current_imf, IMF_STATUS_FLAG or IMF_WRITER_BITMAP_FLAG or IMF_DISPOSED_CNT_FLAG or IMF_NO_WRITERS_CNT_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_IGNORE_DEADLINE_FLAG)) severity FAILURE; + assert (not WITH_KEY or inst_data.addr /= INSTANCE_MEMORY_MAX_ADDRESS) severity FAILURE; + assert (not WITH_KEY or stable(clk, check_mask(inst_data.field_flags, IMF_STATUS_FLAG or IMF_WRITER_BITMAP_FLAG or IMF_DISPOSED_CNT_FLAG or IMF_NO_WRITERS_CNT_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_IGNORE_DEADLINE_FLAG))) severity FAILURE; -- DEFAULT STATUS INFO (LIVELINESS) if (WITH_KEY) then tmp_update := IMF_STATUS_FLAG; - status_info_update <= inst_data.status_info; - status_info_update(ISI_LIVELINESS_FLAG) <= '1'; + inst_r.status_info <= inst_data.status_info; + inst_r.status_info(ISI_LIVELINESS_FLAG) <= '1'; else inst_data_next2.status_info(ISI_LIVELINESS_FLAG) <= '1'; end if; @@ -2162,7 +2135,7 @@ begin -- Convert Back -- Synthesis Guard if (WITH_KEY) then - writer_bitmap <= to_writer_bitmap_array(tmp_bitmap); + inst_r.writer_bitmap <= to_writer_bitmap_array(tmp_bitmap); tmp_update := tmp_update or IMF_WRITER_BITMAP_FLAG; else inst_data_next2.writer_bitmap <= to_writer_bitmap_array(tmp_bitmap); @@ -2176,7 +2149,7 @@ begin -- Convert Back -- Synthesis Guard if (WITH_KEY) then - writer_bitmap <= to_writer_bitmap_array(tmp_bitmap); + inst_r.writer_bitmap <= to_writer_bitmap_array(tmp_bitmap); tmp_update := tmp_update or IMF_WRITER_BITMAP_FLAG; else inst_data_next2.writer_bitmap <= to_writer_bitmap_array(tmp_bitmap); @@ -2192,8 +2165,8 @@ begin -- Synthesis Guard if (WITH_KEY) then tmp_update := tmp_update or IMF_DISPOSED_CNT_FLAG; - gen_cnt <= inst_data.disposed_gen_cnt + 1; - status_info_update(ISI_VIEW_FLAG) <= '0'; + inst_r.disposed_gen_cnt <= inst_data.disposed_gen_cnt + 1; + inst_r.status_info(ISI_VIEW_FLAG) <= '0'; else inst_data_next2.disposed_gen_cnt <= inst_data.disposed_gen_cnt + 1; inst_data_next2.status_info(ISI_VIEW_FLAG) <= '0'; @@ -2203,8 +2176,8 @@ begin -- Synthesis Guard if (WITH_KEY) then tmp_update := tmp_update or IMF_NO_WRITERS_CNT_FLAG; - gen_cnt <= inst_data.no_writers_gen_cnt + 1; - status_info_update(ISI_VIEW_FLAG) <= '0'; + inst_r.no_writers_gen_cnt <= inst_data.no_writers_gen_cnt + 1; + inst_r.status_info(ISI_VIEW_FLAG) <= '0'; else inst_data_next2.no_writers_gen_cnt <= inst_data.no_writers_gen_cnt + 1; inst_data_next2.status_info(ISI_VIEW_FLAG) <= '0'; @@ -2222,8 +2195,8 @@ begin elsif (newer_inst_sample = '0') then -- Synthesis Guard if (WITH_KEY) then - status_info_update(ISI_NOT_ALIVE_DISPOSED_FLAG) <= '1'; - status_info_update(ISI_NOT_ALIVE_NO_WRITERS_FLAG) <= '0'; + inst_r.status_info(ISI_NOT_ALIVE_DISPOSED_FLAG) <= '1'; + inst_r.status_info(ISI_NOT_ALIVE_NO_WRITERS_FLAG) <= '0'; else inst_data_next2.status_info(ISI_NOT_ALIVE_DISPOSED_FLAG) <= '1'; inst_data_next2.status_info(ISI_NOT_ALIVE_NO_WRITERS_FLAG) <= '0'; @@ -2238,8 +2211,8 @@ begin elsif (newer_inst_sample = '0') then -- Synthesis Guard if (WITH_KEY) then - status_info_update(ISI_NOT_ALIVE_DISPOSED_FLAG) <= '0'; - status_info_update(ISI_NOT_ALIVE_NO_WRITERS_FLAG) <= '1'; + inst_r.status_info(ISI_NOT_ALIVE_DISPOSED_FLAG) <= '0'; + inst_r.status_info(ISI_NOT_ALIVE_NO_WRITERS_FLAG) <= '1'; else inst_data_next2.status_info(ISI_NOT_ALIVE_DISPOSED_FLAG) <= '0'; inst_data_next2.status_info(ISI_NOT_ALIVE_NO_WRITERS_FLAG) <= '1'; @@ -2259,8 +2232,8 @@ begin elsif (newer_inst_sample = '0') then -- Synthesis Guard if (WITH_KEY) then - status_info_update(ISI_NOT_ALIVE_DISPOSED_FLAG) <= '0'; - status_info_update(ISI_NOT_ALIVE_NO_WRITERS_FLAG) <= '0'; + inst_r.status_info(ISI_NOT_ALIVE_DISPOSED_FLAG) <= '0'; + inst_r.status_info(ISI_NOT_ALIVE_NO_WRITERS_FLAG) <= '0'; else inst_data_next2.status_info(ISI_NOT_ALIVE_DISPOSED_FLAG) <= '0'; inst_data_next2.status_info(ISI_NOT_ALIVE_NO_WRITERS_FLAG) <= '0'; @@ -2275,7 +2248,7 @@ begin -- Synthesis Guard if (WITH_KEY) then tmp_update := tmp_update or IMF_SAMPLE_CNT_FLAG; - sample_cnt <= inst_data.sample_cnt + 1; + inst_r.sample_cnt <= inst_data.sample_cnt + 1; else inst_data_next2.sample_cnt <= inst_data.sample_cnt + 1; end if; @@ -2286,7 +2259,7 @@ begin -- Synthesis Guard if (WITH_KEY) then tmp_update := tmp_update or IMF_IGNORE_DEADLINE_FLAG; - deadline <= time + TIME_BASED_FILTER_QOS; + inst_r.ignore_deadline <= time + TIME_BASED_FILTER_QOS; else inst_data_next2.ignore_deadline <= time + TIME_BASED_FILTER_QOS; end if; @@ -2317,9 +2290,10 @@ begin -- Synthesis Guard if (WITH_KEY) then -- UPDATE Instance - inst_op_start <= '1'; - inst_opcode <= UPDATE_INSTANCE; - inst_mem_fields <= tmp_update; + inst_op_start <= '1'; + inst_opcode <= UPDATE_INSTANCE; + inst_r.addr <= inst_data.addr; + inst_r.field_flags <= tmp_update; end if; if (not tmp_bool) then @@ -2378,7 +2352,8 @@ begin -- Wait for instance Update to Complete if (not WITH_KEY or inst_op_done = '1') then - assert (not WITH_KEY or check_mask(current_imf, IMF_DISPOSED_CNT_FLAG or IMF_NO_WRITERS_CNT_FLAG)) severity FAILURE; + assert (not WITH_KEY or inst_data.addr /= INSTANCE_MEMORY_MAX_ADDRESS) severity FAILURE; + assert (not WITH_KEY or stable(clk, check_mask(inst_data.field_flags, IMF_DISPOSED_CNT_FLAG or IMF_NO_WRITERS_CNT_FLAG))) severity FAILURE; case (cnt) is -- SET Disposed Generation Counter @@ -2587,7 +2562,8 @@ begin -- Wait for Instane Data if (not WITH_KEY or inst_op_done = '1') then - assert (not WITH_KEY or check_mask(current_imf, IMF_DISPOSED_CNT_FLAG or IMF_NO_WRITERS_CNT_FLAG)) severity FAILURE; + assert (not WITH_KEY or inst_data.addr /= INSTANCE_MEMORY_MAX_ADDRESS) severity FAILURE; + assert (not WITH_KEY or stable(clk, check_mask(inst_data.field_flags, IMF_DISPOSED_CNT_FLAG or IMF_NO_WRITERS_CNT_FLAG))) severity FAILURE; case (cnt) is -- GET Next Sample (Empty List) @@ -2864,15 +2840,15 @@ begin case (cnt) is -- GET Instance Data when 0 => - if (not WITH_KEY or (cur_inst = inst_addr_base and check_mask(current_imf, IMF_SAMPLE_CNT_FLAG or IMF_WRITER_BITMAP_FLAG))) then + if (not WITH_KEY or (cur_inst = inst_data.addr and check_mask(inst_data.field_flags, IMF_SAMPLE_CNT_FLAG or IMF_WRITER_BITMAP_FLAG))) then cnt_next <= cnt + 1; else -- Memory Operation Guard if (inst_op_done = '1') then inst_op_start <= '1'; inst_opcode <= GET_INSTANCE; - inst_mem_fields <= IMF_SAMPLE_CNT_FLAG or IMF_WRITER_BITMAP_FLAG or IMF_STATUS_FLAG; - inst_addr_update <= cur_inst; + inst_r.addr <= cur_inst; + inst_r.field_flags <= IMF_SAMPLE_CNT_FLAG or IMF_WRITER_BITMAP_FLAG or IMF_STATUS_FLAG; cnt_next <= cnt + 1; end if; end if; @@ -3076,7 +3052,8 @@ begin -- Memory Operation Guard if (not WITH_KEY or inst_op_done = '1') then - assert (not WITH_KEY or check_mask(current_imf, IMF_SAMPLE_CNT_FLAG or IMF_WRITER_BITMAP_FLAG or IMF_STATUS_FLAG)) severity FAILURE; + assert (not WITH_KEY or inst_data.addr /= INSTANCE_MEMORY_MAX_ADDRESS) severity FAILURE; + assert (not WITH_KEY or stable(clk, check_mask(inst_data.field_flags, IMF_SAMPLE_CNT_FLAG or IMF_WRITER_BITMAP_FLAG or IMF_STATUS_FLAG))) severity FAILURE; -- Synthesis Guard if (WITH_KEY) then @@ -3085,10 +3062,11 @@ begin stale_inst_cnt_next <= stale_inst_cnt + 1; end if; - inst_op_start <= '1'; - inst_opcode <= UPDATE_INSTANCE; - inst_mem_fields <= IMF_SAMPLE_CNT_FLAG; - sample_cnt <= inst_data.sample_cnt - 1; + inst_op_start <= '1'; + inst_opcode <= UPDATE_INSTANCE; + inst_r.addr <= inst_data.addr; + inst_r.field_flags <= IMF_SAMPLE_CNT_FLAG; + inst_r.sample_cnt <= inst_data.sample_cnt - 1; else inst_data_next2.sample_cnt <= inst_data.sample_cnt - 1; end if; @@ -3171,15 +3149,15 @@ begin if (inst_op_done = '1') then case (cnt) is when 0 => - assert check_mask(current_imf, IMF_WRITER_BITMAP_FLAG or IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG) severity FAILURE; - -- No More Instances - if (inst_addr_base = INSTANCE_MEMORY_MAX_ADDRESS) then + if (inst_data.addr = INSTANCE_MEMORY_MAX_ADDRESS) then -- DONE done_rtps <= '1'; ret_rtps <= OK; stage_next <= IDLE; else + assert stable(clk, check_mask(inst_data.field_flags, IMF_WRITER_BITMAP_FLAG or IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG)) severity FAILURE; + -- Convert Writer Bitmap to SLV tmp_bitmap := from_writer_bitmap_array(inst_data.writer_bitmap); @@ -3189,21 +3167,23 @@ begin -- NOTE: writer_bitmap is not latched, since the memory process is latching it at the -- same clock cycle. -- Convert Back - writer_bitmap <= to_writer_bitmap_array(tmp_bitmap); + inst_r.writer_bitmap <= to_writer_bitmap_array(tmp_bitmap); -- NOT_ALIVE_NO_WRITERS Transition if (tmp_bitmap = (tmp_bitmap'reverse_range => '0') and inst_data.status_info(ISI_NOT_ALIVE_DISPOSED_FLAG) = '0') then trigger_sample_gen_next <= '1'; - status_info_update <= inst_data.status_info; - status_info_update(ISI_NOT_ALIVE_NO_WRITERS_FLAG) <= '1'; - status_info_update(ISI_GENERATE_SAMPLE_FLAG) <= '1'; - inst_op_start <= '1'; - inst_opcode <= UPDATE_INSTANCE; - inst_mem_fields <= IMF_STATUS_FLAG or IMF_WRITER_BITMAP_FLAG; + inst_r.status_info <= inst_data.status_info; + inst_r.status_info(ISI_NOT_ALIVE_NO_WRITERS_FLAG) <= '1'; + inst_r.status_info(ISI_GENERATE_SAMPLE_FLAG) <= '1'; + inst_op_start <= '1'; + inst_opcode <= UPDATE_INSTANCE; + inst_r.addr <= inst_data.addr; + inst_r.field_flags <= IMF_STATUS_FLAG or IMF_WRITER_BITMAP_FLAG; else - inst_op_start <= '1'; - inst_opcode <= UPDATE_INSTANCE; - inst_mem_fields <= IMF_WRITER_BITMAP_FLAG; + inst_op_start <= '1'; + inst_opcode <= UPDATE_INSTANCE; + inst_r.addr <= inst_data.addr; + inst_r.field_flags <= IMF_WRITER_BITMAP_FLAG; end if; -- Update Stale Instance Count @@ -3215,17 +3195,19 @@ begin cnt_next <= 1; end if; when 1 => - inst_op_start <= '1'; - inst_opcode <= GET_NEXT_INSTANCE; - inst_mem_fields <= IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_WRITER_BITMAP_FLAG; - stage_next <= REMOVE_WRITER; - cnt_next <= 0; + inst_op_start <= '1'; + inst_opcode <= GET_NEXT_INSTANCE; + inst_r.addr <= inst_data.addr; + inst_r.field_flags <= IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_WRITER_BITMAP_FLAG; + stage_next <= REMOVE_WRITER; + cnt_next <= 0; when 2 => - inst_op_start <= '1'; - inst_opcode <= GET_FIRST_INSTANCE; - inst_mem_fields <= IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_WRITER_BITMAP_FLAG; - stage_next <= REMOVE_WRITER; - cnt_next <= 0; + inst_op_start <= '1'; + inst_opcode <= GET_INSTANCE; + inst_r.addr <= inst_occupied_head; + inst_r.field_flags <= IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_WRITER_BITMAP_FLAG; + stage_next <= REMOVE_WRITER; + cnt_next <= 0; when others => null; end case; @@ -3241,19 +3223,20 @@ begin case (cnt) is -- Find and Remove First Stale Instance when 0 => - assert check_mask(current_imf, IMF_SAMPLE_CNT_FLAG or IMF_WRITER_BITMAP_FLAG) severity FAILURE; - -- Iterated through all Instances - if (inst_addr_base = INSTANCE_MEMORY_MAX_ADDRESS) then + if (inst_data.addr = INSTANCE_MEMORY_MAX_ADDRESS) then -- NOTE: We should enter this state only if there is at least one stale Instance to be removed, so we should never enter this branch. - assert FALSE severity FAILURE; + assert stable(clk, FALSE) severity FAILURE; stage_next <= IDLE; else + assert stable(clk, check_mask(inst_data.field_flags, IMF_SAMPLE_CNT_FLAG or IMF_WRITER_BITMAP_FLAG)) severity FAILURE; + -- Found Stale Instance (No Samples and No Active Writers) if (inst_data.sample_cnt = 0 and inst_data.writer_bitmap = ZERO_WRITER_BITMAP_ARRAY) then -- Remove Stale Instance inst_op_start <= '1'; inst_opcode <= REMOVE_INSTANCE; + inst_r.addr <= inst_data.addr; -- Update Stale Instance Count stale_inst_cnt_next <= stale_inst_cnt - 1; @@ -3261,25 +3244,27 @@ begin else -- Continue Search - inst_op_start <= '1'; - inst_opcode <= GET_NEXT_INSTANCE; - inst_mem_fields <= IMF_SAMPLE_CNT_FLAG or IMF_WRITER_BITMAP_FLAG; + inst_op_start <= '1'; + inst_opcode <= GET_NEXT_INSTANCE; + inst_r.addr <= inst_data.addr; + inst_r.field_flags <= IMF_SAMPLE_CNT_FLAG or IMF_WRITER_BITMAP_FLAG; end if; end if; -- Insert New Instance when 1 => - inst_op_start <= '1'; - inst_opcode <= INSERT_INSTANCE; - status_info_update <= (ISI_LIVELINESS_FLAG => '1', ISI_NOT_ALIVE_DISPOSED_FLAG => sample_status_info(SSI_DISPOSED_FLAG), others => '0'); - sample_cnt <= to_unsigned(1, WORD_WIDTH); + inst_op_start <= '1'; + inst_opcode <= INSERT_INSTANCE; + inst_r.key_hash <= key_hash; + inst_r.status_info <= (ISI_LIVELINESS_FLAG => '1', ISI_NOT_ALIVE_DISPOSED_FLAG => sample_status_info(SSI_DISPOSED_FLAG), others => '0'); + inst_r.sample_cnt <= to_unsigned(1, WORD_WIDTH); if (TIME_BASED_FILTER_QOS /= DURATION_ZERO) then - deadline <= time + TIME_BASED_FILTER_QOS; + inst_r.ignore_deadline <= time + TIME_BASED_FILTER_QOS; else - deadline <= TIME_INVALID; + inst_r.ignore_deadline <= TIME_INVALID; end if; tmp_bitmap := (others => '0'); tmp_bitmap(writer_id) := '1'; - writer_bitmap <= to_writer_bitmap_array(tmp_bitmap); + inst_r.writer_bitmap <= to_writer_bitmap_array(tmp_bitmap); -- Latch Instance Pointer cur_inst_next <= inst_empty_head; @@ -3475,8 +3460,8 @@ begin if (inst_op_done = '1') then inst_op_start <= '1'; inst_opcode <= GET_INSTANCE; - inst_mem_fields <= IMF_STATUS_FLAG; - inst_addr_update <= next_inst; + inst_r.addr <= next_inst; + inst_r.field_flags <= IMF_STATUS_FLAG; cnt_next <= cnt + 1; end if; end if; @@ -3484,8 +3469,8 @@ begin when 7 => -- Wait for Instance Data if (not WITH_KEY or inst_op_done = '1') then - assert (not WITH_KEY or check_mask(current_imf, IMF_STATUS_FLAG)) severity FAILURE; - assert (not WITH_KEY or next_inst = inst_addr_base) severity FAILURE; + assert (not WITH_KEY or stable(clk, check_mask(inst_data.field_flags, IMF_STATUS_FLAG))) severity FAILURE; + assert (not WITH_KEY or next_inst = inst_data.addr) severity FAILURE; -- DEFAULT tmp_bool := TRUE; @@ -3911,8 +3896,8 @@ begin if (inst_op_done = '1') then inst_op_start <= '1'; inst_opcode <= GET_INSTANCE; - inst_mem_fields <= IMF_STATUS_FLAG; - inst_addr_update <= next_inst; + inst_r.addr <= next_inst; + inst_r.field_flags <= IMF_STATUS_FLAG; cnt_next <= cnt + 1; end if; end if; @@ -3922,8 +3907,8 @@ begin if (WITH_KEY) then -- Wait for Instance Data if (inst_op_done = '1') then - assert check_mask(current_imf, IMF_STATUS_FLAG) severity FAILURE; - assert (next_inst = inst_addr_base) severity FAILURE; + assert stable(clk, check_mask(inst_data.field_flags, IMF_STATUS_FLAG)) severity FAILURE; + assert (next_inst = inst_data.addr) severity FAILURE; -- DEFAULT tmp_bool := TRUE; @@ -4006,7 +3991,7 @@ begin -- Wait for Instance Data if (not WITH_KEY or inst_op_done = '1') then -- Instance Data valid - if (not WITH_KEY or (inst_addr_base = cur_inst and check_mask(current_imf,IMF_STATUS_FLAG or IMF_KEY_HASH_FLAG or IMF_DISPOSED_CNT_FLAG or IMF_NO_WRITERS_CNT_FLAG))) then + if (not WITH_KEY or (inst_data.addr = cur_inst and check_mask(inst_data.field_flags,IMF_STATUS_FLAG or IMF_KEY_HASH_FLAG or IMF_DISPOSED_CNT_FLAG or IMF_NO_WRITERS_CNT_FLAG))) then -- Sample Info View State if (inst_data.status_info(ISI_VIEW_FLAG) = '0') then @@ -4047,8 +4032,8 @@ begin -- Get Instance Data inst_op_start <= '1'; inst_opcode <= GET_INSTANCE; - inst_mem_fields <= IMF_KEY_HASH_FLAG or IMF_STATUS_FLAG or IMF_DISPOSED_CNT_FLAG or IMF_NO_WRITERS_CNT_FLAG; - inst_addr_update <= cur_inst; + inst_r.addr <= cur_inst; + inst_r.field_flags <= IMF_KEY_HASH_FLAG or IMF_STATUS_FLAG or IMF_DISPOSED_CNT_FLAG or IMF_NO_WRITERS_CNT_FLAG; end if; end if; -- Present Data @@ -4080,7 +4065,8 @@ begin when 2 => -- Memory Operation Guard if (not WITH_KEY or inst_op_done = '1') then - assert (not WITH_KEY or check_mask(current_imf, IMF_STATUS_FLAG)) severity FAILURE; + assert (not WITH_KEY or inst_data.addr /= INSTANCE_MEMORY_MAX_ADDRESS) severity FAILURE; + assert (not WITH_KEY or stable(clk, check_mask(inst_data.field_flags, IMF_STATUS_FLAG))) severity FAILURE; -- NOTE: If we have a presentation of consecutive same instance samples of multiple instances, we have to -- mark the instances we have already handled, in order to prevent the GET_NEXT_SAMPLE state to -- re-process them. @@ -4091,19 +4077,20 @@ begin inst_op_start <= '1'; inst_opcode <= UPDATE_INSTANCE; - inst_mem_fields <= IMF_STATUS_FLAG; - status_info_update <= inst_data.status_info; + inst_r.addr <= inst_data.addr; + inst_r.field_flags <= IMF_STATUS_FLAG; + inst_r.status_info <= inst_data.status_info; -- Consecutive Instance Sample Order of multiple Instances if ((not ORDERED_ACCESS or PRESENTATION_QOS = INSTANCE_PRESENTATION_QOS) and single_instance = '0') then -- Mark Instance - status_info_update(ISI_MARK_FLAG) <= '1'; + inst_r.status_info(ISI_MARK_FLAG) <= '1'; end if; -- Instance is NOT_VIEWED and sample is from last generation of Instance if (inst_data.status_info(ISI_VIEW_FLAG) = '0' and si_absolute_generation_rank_sig = 0) then -- Mark Instance as VIEWED - status_info_update(ISI_VIEW_FLAG) <= '1'; + inst_r.status_info(ISI_VIEW_FLAG) <= '1'; end if; else -- Instance is NOT_VIEWED and sample is from last generation of Instance @@ -4301,20 +4288,22 @@ begin when 0 => -- NOTE: The Generation Counters are not used directly in this state, but will be needed by the FINALIZE_SAMPLE_INFO state. inst_op_start <= '1'; - inst_opcode <= GET_FIRST_INSTANCE; - inst_mem_fields <= IMF_STATUS_FLAG or IMF_KEY_HASH_FLAG; + inst_opcode <= GET_INSTANCE; + inst_r.addr <= inst_occupied_head; + inst_r.field_flags <= IMF_STATUS_FLAG or IMF_KEY_HASH_FLAG; cnt_next <= 2; -- GET NEXT INSTANCE when 1 => -- NOTE: The Generation Counters are not used directly in this state, but will be needed by the FINALIZE_SAMPLE_INFO state. inst_op_start <= '1'; inst_opcode <= GET_NEXT_INSTANCE; - inst_mem_fields <= IMF_STATUS_FLAG or IMF_KEY_HASH_FLAG; + inst_r.addr <= inst_data.addr; + inst_r.field_flags <= IMF_STATUS_FLAG or IMF_KEY_HASH_FLAG; cnt_next <= 2; -- EXIT CONDITION when 2 => -- No More Instances - if (inst_addr_base = INSTANCE_MEMORY_MAX_ADDRESS) then + if (inst_data.addr = INSTANCE_MEMORY_MAX_ADDRESS) then -- DONE done_dds <= '1'; return_code_dds <= RETCODE_NO_DATA; @@ -4325,8 +4314,8 @@ begin end if; -- KEY HASH 1/4 when 3 => - assert (inst_addr_base /= INSTANCE_MEMORY_MAX_ADDRESS) severity FAILURE; - assert check_mask(current_imf, IMF_KEY_HASH_FLAG) severity FAILURE; + assert (inst_data.addr /= INSTANCE_MEMORY_MAX_ADDRESS) severity FAILURE; + assert stable(clk, check_mask(inst_data.field_flags, IMF_KEY_HASH_FLAG)) severity FAILURE; if (unsigned(inst_data.key_hash(0)) > unsigned(key_hash(0))) then cnt_next <= 7; -- INSTANCE STATUS CHECK @@ -4338,8 +4327,8 @@ begin end if; -- KEY HASH 2/4 when 4 => - assert (inst_addr_base /= INSTANCE_MEMORY_MAX_ADDRESS) severity FAILURE; - assert check_mask(current_imf, IMF_KEY_HASH_FLAG) severity FAILURE; + assert (inst_data.addr /= INSTANCE_MEMORY_MAX_ADDRESS) severity FAILURE; + assert stable(clk, check_mask(inst_data.field_flags, IMF_KEY_HASH_FLAG)) severity FAILURE; if (unsigned(inst_data.key_hash(1)) > unsigned(key_hash(1))) then cnt_next <= 7; -- INSTANCE STATUS CHECK @@ -4351,8 +4340,8 @@ begin end if; -- KEY HASH 3/4 when 5 => - assert (inst_addr_base /= INSTANCE_MEMORY_MAX_ADDRESS) severity FAILURE; - assert check_mask(current_imf, IMF_KEY_HASH_FLAG) severity FAILURE; + assert (inst_data.addr /= INSTANCE_MEMORY_MAX_ADDRESS) severity FAILURE; + assert stable(clk, check_mask(inst_data.field_flags, IMF_KEY_HASH_FLAG)) severity FAILURE; if (unsigned(inst_data.key_hash(2)) > unsigned(key_hash(2))) then cnt_next <= 7; -- INSTANCE STATUS CHECK @@ -4364,7 +4353,7 @@ begin end if; -- KEY HASH 4/4 when 6 => - assert check_mask(current_imf, IMF_KEY_HASH_FLAG) severity FAILURE; + assert stable(clk, check_mask(inst_data.field_flags, IMF_KEY_HASH_FLAG)) severity FAILURE; if (unsigned(inst_data.key_hash(3)) > unsigned(key_hash(3))) then cnt_next <= 7; -- INSTANCE STATUS CHECK @@ -4373,8 +4362,8 @@ begin end if; -- INSTANCE STATUS CHECK when 7 => - assert (inst_addr_base /= INSTANCE_MEMORY_MAX_ADDRESS) severity FAILURE; - assert check_mask(current_imf, IMF_STATUS_FLAG) severity FAILURE; + assert (inst_data.addr /= INSTANCE_MEMORY_MAX_ADDRESS) severity FAILURE; + assert stable(clk, check_mask(inst_data.field_flags, IMF_STATUS_FLAG)) severity FAILURE; -- DEFAULT tmp_bool := TRUE; @@ -4421,7 +4410,7 @@ begin -- Instance Passes Checks if (tmp_bool) then - cur_inst_next <= inst_addr_base; + cur_inst_next <= inst_data.addr; stage_next <= GET_NEXT_SAMPLE; cnt_next <= 0; -- Reset @@ -4445,14 +4434,15 @@ begin when 0 => -- NOTE: The Generation Counters are not used directly in this state, but will be needed by the FINALIZE_SAMPLE_INFO state. inst_op_start <= '1'; - inst_opcode <= SEARCH_INSTANCE_HASH; - inst_mem_fields <= IMF_STATUS_FLAG; + inst_opcode <= SEARCH_INSTANCE; + inst_r.key_hash <= key_hash; + inst_r.field_flags <= IMF_STATUS_FLAG; cnt_next <= cnt + 1; when 1 => - assert check_mask(current_imf, IMF_STATUS_FLAG) severity FAILURE; - -- Instance Found - if (inst_addr_base /= INSTANCE_MEMORY_MAX_ADDRESS) then + if (inst_data.addr /= INSTANCE_MEMORY_MAX_ADDRESS) then + assert stable(clk, check_mask(inst_data.field_flags, IMF_STATUS_FLAG)) severity FAILURE; + -- DEFAULT tmp_bool := TRUE; @@ -4499,7 +4489,7 @@ begin -- Instance Passes Checks if (tmp_bool) then -- Get Instance Samples - cur_inst_next <= inst_addr_base; + cur_inst_next <= inst_data.addr; stage_next <= GET_NEXT_SAMPLE; cnt_next <= 0; else @@ -4638,8 +4628,8 @@ begin -- Fetch Instance Data inst_op_start <= '1'; inst_opcode <= GET_INSTANCE; - inst_mem_fields <= IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_WRITER_BITMAP_FLAG; - inst_addr_update <= resize(unsigned(sample_read_data),INSTANCE_MEMORY_ADDR_WIDTH); + inst_r.addr <= resize(unsigned(sample_read_data),INSTANCE_MEMORY_ADDR_WIDTH); + inst_r.field_flags <= IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_WRITER_BITMAP_FLAG; -- Remove Sample stage_next <= REMOVE_SAMPLE; @@ -4658,33 +4648,36 @@ begin case (cnt) is when 0 => inst_op_start <= '1'; - inst_opcode <= GET_FIRST_INSTANCE; - inst_mem_fields <= IMF_STATUS_FLAG; + inst_opcode <= GET_INSTANCE; + inst_r.addr <= inst_occupied_head; + inst_r.field_flags <= IMF_STATUS_FLAG; cnt_next <= cnt + 2; when 1 => -- Continue inst_op_start <= '1'; inst_opcode <= GET_NEXT_INSTANCE; - inst_mem_fields <= IMF_STATUS_FLAG; + inst_r.addr <= inst_data.addr; + inst_r.field_flags <= IMF_STATUS_FLAG; cnt_next <= cnt + 1; when 2 => - assert check_mask(current_imf, IMF_STATUS_FLAG) severity FAILURE; - -- Instance Found - if (inst_addr_base /= INSTANCE_MEMORY_MAX_ADDRESS) then + if (inst_data.addr /= INSTANCE_MEMORY_MAX_ADDRESS) then + assert stable(clk, check_mask(inst_data.field_flags, IMF_STATUS_FLAG)) severity FAILURE; + -- Sample needs to be Generated if (inst_data.status_info(ISI_GENERATE_SAMPLE_FLAG) = '1') then -- GET Required Instance Data inst_op_start <= '1'; inst_opcode <= GET_INSTANCE; - inst_mem_fields <= IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_DISPOSED_CNT_FLAG or IMF_NO_WRITERS_CNT_FLAG; - inst_addr_update <= inst_addr_base; + inst_r.addr <= inst_data.addr; + inst_r.field_flags <= IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_DISPOSED_CNT_FLAG or IMF_NO_WRITERS_CNT_FLAG; cnt_next <= cnt + 1; else -- Continue inst_op_start <= '1'; inst_opcode <= GET_NEXT_INSTANCE; - inst_mem_fields <= IMF_STATUS_FLAG; + inst_r.addr <= inst_data.addr; + inst_r.field_flags <= IMF_STATUS_FLAG; end if; else -- Reset @@ -4693,7 +4686,8 @@ begin stage_next <= IDLE; end if; when 3 => - assert check_mask(current_imf, IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG) severity FAILURE; + assert (inst_data.addr /= INSTANCE_MEMORY_MAX_ADDRESS) severity FAILURE; + assert stable(clk, check_mask(inst_data.field_flags, IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG)) severity FAILURE; -- RESOURCE_LIMITS_QOS (MAX_SAMPLES_PER_INSTANCE) if (WITH_KEY and MAX_SAMPLES_PER_INSTANCE /= LENGTH_UNLIMITED and inst_data.sample_cnt = unsigned(MAX_SAMPLES_PER_INSTANCE)) then @@ -4701,7 +4695,8 @@ begin -- Continue inst_op_start <= '1'; inst_opcode <= GET_NEXT_INSTANCE; - inst_mem_fields <= IMF_STATUS_FLAG; + inst_r.addr <= inst_data.addr; + inst_r.field_flags <= IMF_STATUS_FLAG; cnt_next <= 2; else -- Accept Change (Remove Oldest Instance Sample) @@ -4710,14 +4705,15 @@ begin -- Update Instance inst_op_start <= '1'; inst_opcode <= UPDATE_INSTANCE; - inst_mem_fields <= IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG; - sample_cnt <= inst_data.sample_cnt + 1; - status_info_update <= inst_data.status_info; - status_info_update(ISI_GENERATE_SAMPLE_FLAG) <= '0'; + inst_r.addr <= inst_data.addr; + inst_r.field_flags <= IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG; + inst_r.sample_cnt <= inst_data.sample_cnt + 1; + inst_r.status_info <= inst_data.status_info; + inst_r.status_info(ISI_GENERATE_SAMPLE_FLAG) <= '0'; cur_sample_next <= empty_sample_list_head; - cur_inst_next <= inst_addr_base; + cur_inst_next <= inst_data.addr; stage_next <= GENERATE_SAMPLE; cnt_next <= 0; end if; @@ -4736,13 +4732,14 @@ begin -- Update Instance inst_op_start <= '1'; inst_opcode <= UPDATE_INSTANCE; - inst_mem_fields <= IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG; - sample_cnt <= inst_data.sample_cnt + 1; - status_info_update <= inst_data.status_info; - status_info_update(ISI_GENERATE_SAMPLE_FLAG) <= '0'; + inst_r.addr <= inst_data.addr; + inst_r.field_flags <= IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG; + inst_r.sample_cnt <= inst_data.sample_cnt + 1; + inst_r.status_info <= inst_data.status_info; + inst_r.status_info(ISI_GENERATE_SAMPLE_FLAG) <= '0'; cur_sample_next <= empty_sample_list_head; - cur_inst_next <= inst_addr_base; + cur_inst_next <= inst_data.addr; stage_next <= GENERATE_SAMPLE; cnt_next <= 0; end if; @@ -4750,13 +4747,14 @@ begin -- Update Instance inst_op_start <= '1'; inst_opcode <= UPDATE_INSTANCE; - inst_mem_fields <= IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG; - sample_cnt <= inst_data.sample_cnt + 1; - status_info_update <= inst_data.status_info; - status_info_update(ISI_GENERATE_SAMPLE_FLAG) <= '0'; + inst_r.addr <= inst_data.addr; + inst_r.field_flags <= IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG; + inst_r.sample_cnt <= inst_data.sample_cnt + 1; + inst_r.status_info <= inst_data.status_info; + inst_r.status_info(ISI_GENERATE_SAMPLE_FLAG) <= '0'; cur_sample_next <= empty_sample_list_head; - cur_inst_next <= inst_addr_base; + cur_inst_next <= inst_data.addr; stage_next <= GENERATE_SAMPLE; cnt_next <= 0; end if; @@ -4903,32 +4901,35 @@ begin -- Get First Instance when 0 => inst_op_start <= '1'; - inst_opcode <= GET_FIRST_INSTANCE; - inst_mem_fields <= IMF_KEY_HASH_FLAG or IMF_STATUS_FLAG; - cnt_next <= 2; + inst_opcode <= GET_INSTANCE; + inst_r.addr <= inst_occupied_head; + inst_r.field_flags <= IMF_KEY_HASH_FLAG or IMF_STATUS_FLAG; + cnt_next <= 2; -- Get Next Instance when 1 => inst_op_start <= '1'; inst_opcode <= GET_NEXT_INSTANCE; - inst_mem_fields <= IMF_KEY_HASH_FLAG or IMF_STATUS_FLAG; - cnt_next <= 2; + inst_r.addr <= inst_data.addr; + inst_r.field_flags <= IMF_KEY_HASH_FLAG or IMF_STATUS_FLAG; + cnt_next <= 2; -- Check Instance when 2 => - assert check_mask(current_imf, IMF_STATUS_FLAG or IMF_KEY_HASH_FLAG) severity FAILURE; - -- Reached End of Instances - if (inst_addr_base = INSTANCE_MEMORY_MAX_ADDRESS) then + if (inst_data.addr = INSTANCE_MEMORY_MAX_ADDRESS) then -- DONE stage_next <= IDLE; else + assert stable(clk, check_mask(inst_data.field_flags, IMF_STATUS_FLAG or IMF_KEY_HASH_FLAG)) severity FAILURE; + -- Instance received Sample if (inst_data.status_info(ISI_LIVELINESS_FLAG) = '1') then -- Reset Liveliness Flag inst_op_start <= '1'; inst_opcode <= UPDATE_INSTANCE; - inst_mem_fields <= IMF_STATUS_FLAG; - status_info_update <= inst_data.status_info; - status_info_update(ISI_LIVELINESS_FLAG) <= '0'; + inst_r.addr <= inst_data.addr; + inst_r.field_flags <= IMF_STATUS_FLAG; + inst_r.status_info <= inst_data.status_info; + inst_r.status_info(ISI_LIVELINESS_FLAG) <= '0'; cnt_next <= 1; else -- Update Requested Deadline Missed Status @@ -5018,8 +5019,6 @@ begin when others => null; end case; - when others => - null; end case; end process; @@ -5028,8 +5027,7 @@ begin -- *Instance Memory Process* -- STATE DESCRIPTION -- IDLE Idle State. Done Signal is pulled high and Memory FSM accepts new memory operations - -- SEARCH_INSTANCE_HASH See Memory OPCODE Description - -- SEARCH_INSTANCE_ADDR See Memory OPCODE Description + -- SEARCH_INSTANCE See Memory OPCODE Description -- GET_NEXT_INSTANCE See Memory OPCODE Description -- GET_INSTANCE_DATA Latch specified Instance Data for use by main process -- FIND_POS Find List position of Instance to be added @@ -5046,13 +5044,11 @@ begin inst_empty_head_next <= inst_empty_head; inst_occupied_head_next <= inst_occupied_head; inst_latch_data_next <= inst_latch_data; - inst_next_addr_base_next <= inst_next_addr_base; - inst_prev_addr_base_next <= inst_prev_addr_base; + inst_addr_latch_next <= inst_addr_latch; inst_cnt_next <= inst_cnt; inst_cnt2_next <= inst_cnt2; inst_data_next <= inst_data; inst_long_latch_next <= inst_long_latch; - current_imf_next <= current_imf; -- DEFAULT Unregistered inst_abort_read <= '0'; inst_ready_out <= '0'; @@ -5068,163 +5064,147 @@ begin inst_op_done <= '1'; if (inst_op_start = '1') then - -- Latch Signals needed for Mermory Operation (Use _next signals, because some signals are set in same clk) - inst_latch_data_next <= ( - key_hash => key_hash_next, - status_info => status_info_update, - sample_cnt => sample_cnt, - gen_cnt => gen_cnt, - deadline => deadline, - writer_bitmap => writer_bitmap, - field_flags => inst_mem_fields, - addr => inst_addr_update - ); + inst_latch_data_next <= inst_r; case(inst_opcode) is - when SEARCH_INSTANCE_HASH => + when SEARCH_INSTANCE => -- Reset Data - current_imf_next <= inst_mem_fields; - inst_data_next <= ZERO_INSTANCE_DATA; + inst_data_next <= ZERO_INSTANCE_DATA; + if (TIME_BASED_FILTER_QOS = DURATION_ZERO) then + inst_data_next.field_flags <= IMF_IGNORE_DEADLINE_FLAG; + end if; -- No Instances available - if (inst_occupied_head = INSTANCE_MEMORY_MAX_ADDRESS) then - inst_addr_base_next <= INSTANCE_MEMORY_MAX_ADDRESS; - else - inst_prev_addr_base_next <= INSTANCE_MEMORY_MAX_ADDRESS; - inst_addr_base_next <= inst_occupied_head; - inst_stage_next <= SEARCH_INSTANCE_HASH; - inst_cnt_next <= 0; - end if; - when SEARCH_INSTANCE_ADDR => - -- Reset Data - current_imf_next <= inst_mem_fields; - inst_data_next <= ZERO_INSTANCE_DATA; - - -- No Instances avialable - if (inst_occupied_head = INSTANCE_MEMORY_MAX_ADDRESS) then - inst_addr_base_next <= INSTANCE_MEMORY_MAX_ADDRESS; - else - inst_prev_addr_base_next <= INSTANCE_MEMORY_MAX_ADDRESS; - inst_addr_base_next <= inst_occupied_head; - inst_stage_next <= SEARCH_INSTANCE_ADDR; - inst_cnt_next <= 0; + if (inst_occupied_head /= INSTANCE_MEMORY_MAX_ADDRESS) then + inst_addr_base_next <= inst_occupied_head; + inst_stage_next <= SEARCH_INSTANCE; + inst_cnt_next <= 0; end if; when INSERT_INSTANCE => - -- NOTE: Since this process has no way to communicate a failed insert to the main process, it has to be made sure - -- by the main process that the operation can succeed (Memory is available) - assert (inst_empty_head /= INSTANCE_MEMORY_MAX_ADDRESS) report "Instance Insertion while memory Full" severity FAILURE; + assert (inst_empty_head /= INSTANCE_MEMORY_MAX_ADDRESS) severity FAILURE; - -- Reset Data - current_imf_next <= (others => '1'); - inst_data_next <= ZERO_INSTANCE_DATA; + inst_data_next <= ZERO_INSTANCE_DATA; + if (TIME_BASED_FILTER_QOS = DURATION_ZERO) then + inst_data_next.field_flags <= IMF_IGNORE_DEADLINE_FLAG; + end if; -- First Instance if (inst_occupied_head = INSTANCE_MEMORY_MAX_ADDRESS) then - inst_prev_addr_base_next <= INSTANCE_MEMORY_MAX_ADDRESS; - inst_next_addr_base_next <= INSTANCE_MEMORY_MAX_ADDRESS; - inst_addr_base_next <= inst_empty_head; - inst_stage_next <= INSERT_INSTANCE; - inst_cnt_next <= 1; -- Skip first Step - inst_occupied_head_next <= inst_empty_head; + + inst_data_next.addr <= inst_empty_head; + + inst_addr_base_next <= INSTANCE_MEMORY_MAX_ADDRESS; + inst_addr_latch_next <= INSTANCE_MEMORY_MAX_ADDRESS; + inst_stage_next <= INSERT_INSTANCE; + inst_cnt_next <= 0; else - inst_prev_addr_base_next <= INSTANCE_MEMORY_MAX_ADDRESS; - inst_addr_base_next <= inst_occupied_head; - inst_stage_next <= FIND_POS; - inst_cnt_next <= 0; + inst_data_next.addr <= inst_empty_head; + inst_addr_base_next <= inst_occupied_head; + inst_stage_next <= FIND_POS; + inst_cnt_next <= 0; end if; when UPDATE_INSTANCE => - current_imf_next <= current_imf or inst_mem_fields; - inst_stage_next <= UPDATE_INSTANCE; - - if check_mask(inst_mem_fields,IMF_STATUS_FLAG) then - inst_cnt_next <= 0; - elsif check_mask(inst_mem_fields,IMF_SAMPLE_CNT_FLAG) then - inst_cnt_next <= 1; - elsif check_mask(inst_mem_fields,IMF_DISPOSED_CNT_FLAG) then - inst_cnt_next <= 2; - elsif check_mask(inst_mem_fields,IMF_NO_WRITERS_CNT_FLAG) then - inst_cnt_next <= 3; - elsif (TIME_BASED_FILTER_QOS /= DURATION_ZERO and check_mask(inst_mem_fields,IMF_IGNORE_DEADLINE_FLAG)) then - inst_cnt_next <= 4; - elsif check_mask(inst_mem_fields,IMF_WRITER_BITMAP_FLAG) then - inst_cnt_next <= 6; - inst_cnt2_next <= 0; + if (inst_r.addr = INSTANCE_MEMORY_MAX_ADDRESS) then + inst_data_next <= ZERO_INSTANCE_DATA; + if (TIME_BASED_FILTER_QOS = DURATION_ZERO) then + inst_data_next.field_flags <= IMF_IGNORE_DEADLINE_FLAG; + end if; else - -- DONE - inst_stage_next <= IDLE; - end if; - when GET_FIRST_INSTANCE => - -- Reset - current_imf_next <= inst_mem_fields; - inst_data_next <= ZERO_INSTANCE_DATA; - - -- No Instances available - if (inst_occupied_head = INSTANCE_MEMORY_MAX_ADDRESS) then - inst_addr_base_next <= INSTANCE_MEMORY_MAX_ADDRESS; - else - inst_prev_addr_base_next <= INSTANCE_MEMORY_MAX_ADDRESS; - inst_addr_base_next <= inst_occupied_head; - inst_stage_next <= GET_NEXT_INSTANCE; - inst_cnt_next <= 0; - end if; - when GET_NEXT_INSTANCE => - -- Reset - current_imf_next <= inst_mem_fields; - inst_data_next <= ZERO_INSTANCE_DATA; - - -- No Instances available - if (inst_next_addr_base = INSTANCE_MEMORY_MAX_ADDRESS) then - inst_addr_base_next <= INSTANCE_MEMORY_MAX_ADDRESS; - else - inst_prev_addr_base_next <= inst_addr_base; - inst_addr_base_next <= inst_next_addr_base; - inst_stage_next <= GET_NEXT_INSTANCE; - inst_cnt_next <= 0; + if (inst_r.addr /= inst_data.addr) then + inst_data_next <= ZERO_INSTANCE_DATA; + if (TIME_BASED_FILTER_QOS = DURATION_ZERO) then + inst_data_next.field_flags <= IMF_IGNORE_DEADLINE_FLAG; + end if; + end if; + + inst_data_next.addr <= inst_r.addr; + inst_addr_base_next <= inst_r.addr; + inst_stage_next <= UPDATE_INSTANCE; + if check_mask(inst_r.field_flags,IMF_STATUS_FLAG) then + inst_cnt_next <= 0; + elsif check_mask(inst_r.field_flags,IMF_SAMPLE_CNT_FLAG) then + inst_cnt_next <= 1; + elsif check_mask(inst_r.field_flags,IMF_DISPOSED_CNT_FLAG) then + inst_cnt_next <= 2; + elsif check_mask(inst_r.field_flags,IMF_NO_WRITERS_CNT_FLAG) then + inst_cnt_next <= 3; + elsif (TIME_BASED_FILTER_QOS /= DURATION_ZERO and check_mask(inst_r.field_flags,IMF_IGNORE_DEADLINE_FLAG)) then + inst_cnt_next <= 4; + elsif check_mask(inst_r.field_flags,IMF_WRITER_BITMAP_FLAG) then + inst_cnt_next <= 6; + inst_cnt2_next <= 0; + else + -- DONE + inst_stage_next <= IDLE; + end if; end if; when REMOVE_INSTANCE => - -- Reset - current_imf_next <= (others => '0'); - inst_data_next <= ZERO_INSTANCE_DATA; - - inst_stage_next <= REMOVE_INSTANCE; - inst_cnt_next <= 0; - when GET_INSTANCE => - inst_addr_base_next <= inst_addr_update; - if (inst_addr_base /= inst_addr_update) then - -- Reset - current_imf_next <= inst_mem_fields; - inst_data_next <= ZERO_INSTANCE_DATA; - else - current_imf_next <= current_imf or inst_mem_fields; + inst_data_next <= ZERO_INSTANCE_DATA; + if (TIME_BASED_FILTER_QOS = DURATION_ZERO) then + inst_data_next.field_flags <= IMF_IGNORE_DEADLINE_FLAG; end if; - -- Get Instance Data - inst_stage_next <= GET_INSTANCE_DATA; - if check_mask(inst_mem_fields,IMF_KEY_HASH_FLAG) then - inst_cnt_next <= 0; - elsif check_mask(inst_mem_fields,IMF_STATUS_FLAG) then - inst_cnt_next <= 4; - elsif check_mask(inst_mem_fields,IMF_SAMPLE_CNT_FLAG) then - inst_cnt_next <= 5; - elsif check_mask(inst_mem_fields,IMF_DISPOSED_CNT_FLAG) then - inst_cnt_next <= 6; - elsif check_mask(inst_mem_fields,IMF_NO_WRITERS_CNT_FLAG) then - inst_cnt_next <= 7; - elsif (TIME_BASED_FILTER_QOS /= DURATION_ZERO and check_mask(inst_mem_fields,IMF_IGNORE_DEADLINE_FLAG)) then - inst_cnt_next <= 8; - elsif check_mask(inst_mem_fields,IMF_WRITER_BITMAP_FLAG) then - inst_cnt_next <= 10; - inst_cnt2_next <= 0; + if (inst_r.addr /= INSTANCE_MEMORY_MAX_ADDRESS) then + inst_addr_base_next <= inst_r.addr; + inst_stage_next <= REMOVE_INSTANCE; + inst_cnt_next <= 0; + end if; + when GET_NEXT_INSTANCE => + inst_data_next <= ZERO_INSTANCE_DATA; + if (TIME_BASED_FILTER_QOS = DURATION_ZERO) then + inst_data_next.field_flags <= IMF_IGNORE_DEADLINE_FLAG; + end if; + + -- No Instances available + if (inst_r.addr /= INSTANCE_MEMORY_MAX_ADDRESS) then + inst_addr_base_next <= inst_r.addr; + inst_stage_next <= GET_NEXT_INSTANCE; + inst_cnt_next <= 0; + end if; + when GET_INSTANCE => + if (inst_r.addr = INSTANCE_MEMORY_MAX_ADDRESS) then + inst_data_next <= ZERO_INSTANCE_DATA; + if (TIME_BASED_FILTER_QOS = DURATION_ZERO) then + inst_data_next.field_flags <= IMF_IGNORE_DEADLINE_FLAG; + end if; else - -- DONE - inst_stage_next <= IDLE; + if (inst_r.addr /= inst_data.addr) then + inst_data_next <= ZERO_INSTANCE_DATA; + if (TIME_BASED_FILTER_QOS = DURATION_ZERO) then + inst_data_next.field_flags <= IMF_IGNORE_DEADLINE_FLAG; + end if; + end if; + + inst_data_next.addr <= inst_r.addr; + inst_addr_base_next <= inst_r.addr; + inst_stage_next <= GET_INSTANCE_DATA; + if check_mask(inst_r.field_flags,IMF_KEY_HASH_FLAG) then + inst_cnt_next <= 0; + elsif check_mask(inst_r.field_flags,IMF_STATUS_FLAG) then + inst_cnt_next <= 4; + elsif check_mask(inst_r.field_flags,IMF_SAMPLE_CNT_FLAG) then + inst_cnt_next <= 5; + elsif check_mask(inst_r.field_flags,IMF_DISPOSED_CNT_FLAG) then + inst_cnt_next <= 6; + elsif check_mask(inst_r.field_flags,IMF_NO_WRITERS_CNT_FLAG) then + inst_cnt_next <= 7; + elsif (TIME_BASED_FILTER_QOS /= DURATION_ZERO and check_mask(inst_r.field_flags,IMF_IGNORE_DEADLINE_FLAG)) then + inst_cnt_next <= 8; + elsif check_mask(inst_r.field_flags,IMF_WRITER_BITMAP_FLAG) then + inst_cnt_next <= 10; + inst_cnt2_next <= 0; + else + -- DONE + inst_stage_next <= IDLE; + end if; end if; when UNMARK_INSTANCES => -- Empty Memory Guard if (inst_occupied_head /= INSTANCE_MEMORY_MAX_ADDRESS) then - -- Reset inst_data_next <= ZERO_INSTANCE_DATA; - current_imf_next <= (others => '0'); + if (TIME_BASED_FILTER_QOS = DURATION_ZERO) then + inst_data_next.field_flags <= IMF_IGNORE_DEADLINE_FLAG; + end if; inst_addr_base_next <= inst_occupied_head; inst_stage_next <= UNMARK_INSTANCES; @@ -5234,21 +5214,11 @@ begin null; end case; end if; - when SEARCH_INSTANCE_HASH => + when SEARCH_INSTANCE => case (inst_cnt) is - -- GET Next Instance - when 0 => - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_NEXT_ADDR_OFFSET; - inst_read <= '1'; - - -- Memory Flow Control Guard - if (inst_ready_in = '1') then - inst_cnt_next <= inst_cnt + 1; - end if; -- GET Key Hash 1/4 - when 1 => + when 0 => inst_valid_in <= '1'; inst_addr <= inst_addr_base + IMF_KEY_HASH_OFFSET; inst_read <= '1'; @@ -5258,7 +5228,7 @@ begin inst_cnt_next <= inst_cnt + 1; end if; -- GET Key Hash 2/4 - when 2 => + when 1 => inst_valid_in <= '1'; inst_addr <= inst_addr_base + IMF_KEY_HASH_OFFSET + 1; inst_read <= '1'; @@ -5268,7 +5238,7 @@ begin inst_cnt_next <= inst_cnt + 1; end if; -- GET Key Hash 3/4 - when 3 => + when 2 => inst_valid_in <= '1'; inst_addr <= inst_addr_base + IMF_KEY_HASH_OFFSET + 2; inst_read <= '1'; @@ -5278,7 +5248,7 @@ begin inst_cnt_next <= inst_cnt + 1; end if; -- GET Key Hash 4/4 - when 4 => + when 3 => inst_valid_in <= '1'; inst_addr <= inst_addr_base + IMF_KEY_HASH_OFFSET + 3; inst_read <= '1'; @@ -5287,17 +5257,8 @@ begin if (inst_ready_in = '1') then inst_cnt_next <= inst_cnt + 1; end if; - -- READ Next Instance - when 5 => - inst_ready_out <= '1'; - - -- Memory Flow Control Guard - if (inst_valid_out = '1') then - inst_next_addr_base_next <= resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH); - inst_cnt_next <= inst_cnt + 1; - end if; -- READ Key Hash 1/4 - when 6 => + when 4 => inst_ready_out <= '1'; -- Memory Flow Control Guard @@ -5305,23 +5266,13 @@ begin -- No Match if (inst_read_data /= inst_latch_data.key_hash(0)) then inst_abort_read <= '1'; - -- Reached List Tail, No Match - if (inst_next_addr_base = INSTANCE_MEMORY_MAX_ADDRESS) then - inst_addr_base_next <= INSTANCE_MEMORY_MAX_ADDRESS; --No match - -- DONE - inst_stage_next <= IDLE; - else - -- Continue Search - inst_prev_addr_base_next <= inst_addr_base; - inst_addr_base_next <= inst_next_addr_base; - inst_cnt_next <= 0; - end if; + inst_cnt_next <= 8; -- GET NEXT INSTANCE else inst_cnt_next <= inst_cnt + 1; end if; end if; -- READ Key Hash 2/4 - when 7 => + when 5 => inst_ready_out <= '1'; -- Memory Flow Control Guard @@ -5329,23 +5280,13 @@ begin -- No Match if (inst_read_data /= inst_latch_data.key_hash(1)) then inst_abort_read <= '1'; - -- Reached List Tail, No Match - if (inst_next_addr_base = INSTANCE_MEMORY_MAX_ADDRESS) then - inst_addr_base_next <= INSTANCE_MEMORY_MAX_ADDRESS; --No match - -- DONE - inst_stage_next <= IDLE; - else - -- Continue Search - inst_prev_addr_base_next <= inst_addr_base; - inst_addr_base_next <= inst_next_addr_base; - inst_cnt_next <= 0; - end if; + inst_cnt_next <= 8; -- GET NEXT INSTANCE else inst_cnt_next <= inst_cnt + 1; end if; end if; -- READ Key Hash 3/4 - when 8 => + when 6 => inst_ready_out <= '1'; -- Memory Flow Control Guard @@ -5353,41 +5294,22 @@ begin -- No Match if (inst_read_data /= inst_latch_data.key_hash(2)) then inst_abort_read <= '1'; - -- Reached List Tail, No Match - if (inst_next_addr_base = INSTANCE_MEMORY_MAX_ADDRESS) then - inst_addr_base_next <= INSTANCE_MEMORY_MAX_ADDRESS; --No match - -- DONE - inst_stage_next <= IDLE; - else - -- Continue Search - inst_prev_addr_base_next <= inst_addr_base; - inst_addr_base_next <= inst_next_addr_base; - inst_cnt_next <= 0; - end if; + inst_cnt_next <= 8; -- GET NEXT INSTANCE else inst_cnt_next <= inst_cnt + 1; end if; end if; -- READ Key Hash 4/4 - when 9 => + when 7 => inst_ready_out <= '1'; -- Memory Flow Control Guard if (inst_valid_out = '1') then -- No Match if (inst_read_data /= inst_latch_data.key_hash(3)) then - -- Reached List Tail, No Match - if (inst_next_addr_base = INSTANCE_MEMORY_MAX_ADDRESS) then - inst_addr_base_next <= INSTANCE_MEMORY_MAX_ADDRESS; --No match - -- DONE - inst_stage_next <= IDLE; - else - -- Continue Search - inst_prev_addr_base_next <= inst_addr_base; - inst_addr_base_next <= inst_next_addr_base; - inst_cnt_next <= 0; - end if; + inst_cnt_next <= 8; -- GET NEXT INSTANCE else + inst_data_next.addr <= inst_addr_base; -- Get Instance Data inst_stage_next <= GET_INSTANCE_DATA; if check_mask(inst_latch_data.field_flags,IMF_KEY_HASH_FLAG) then @@ -5411,14 +5333,8 @@ begin end if; end if; end if; - when others => - null; - end case; - when SEARCH_INSTANCE_ADDR => - - case (inst_cnt) is -- GET Next Instance - when 0 => + when 8 => inst_valid_in <= '1'; inst_addr <= inst_addr_base + IMF_NEXT_ADDR_OFFSET; inst_read <= '1'; @@ -5428,48 +5344,20 @@ begin inst_cnt_next <= inst_cnt + 1; end if; -- READ Next Instance - when 1 => + when 9 => inst_ready_out <= '1'; -- Memory Flow Control Guard if (inst_valid_out = '1') then - inst_prev_addr_base_next <= inst_addr_base; - inst_addr_base_next <= resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH); - - -- Match - if (resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH) = inst_latch_data.addr) then - -- Get Instance Data - inst_stage_next <= GET_INSTANCE_DATA; - if check_mask(inst_latch_data.field_flags,IMF_KEY_HASH_FLAG) then - inst_cnt_next <= 0; - elsif check_mask(inst_latch_data.field_flags,IMF_STATUS_FLAG) then - inst_cnt_next <= 4; - elsif check_mask(inst_latch_data.field_flags,IMF_SAMPLE_CNT_FLAG) then - inst_cnt_next <= 5; - elsif check_mask(inst_latch_data.field_flags,IMF_DISPOSED_CNT_FLAG) then - inst_cnt_next <= 6; - elsif check_mask(inst_latch_data.field_flags,IMF_NO_WRITERS_CNT_FLAG) then - inst_cnt_next <= 7; - elsif (TIME_BASED_FILTER_QOS /= DURATION_ZERO and check_mask(inst_latch_data.field_flags,IMF_IGNORE_DEADLINE_FLAG)) then - inst_cnt_next <= 8; - elsif check_mask(inst_latch_data.field_flags,IMF_WRITER_BITMAP_FLAG) then - inst_cnt_next <= 10; - inst_cnt2_next <= 0; - else - -- DONE - inst_stage_next <= IDLE; - end if; - -- No Match + -- No more Endpoints + if (resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH) = INSTANCE_MEMORY_MAX_ADDRESS) then + inst_data_next.addr <= INSTANCE_MEMORY_MAX_ADDRESS; --No match + -- DONE + inst_stage_next <= IDLE; else - -- Reached List Tail, No Match - if (resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH) = INSTANCE_MEMORY_MAX_ADDRESS) then - inst_addr_base_next <= INSTANCE_MEMORY_MAX_ADDRESS; --No match - -- DONE - inst_stage_next <= IDLE; - else - -- Continue Search - inst_cnt_next <= 0; - end if; + -- Continue + inst_addr_base_next <= resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH); + inst_cnt_next <= 0; end if; end if; when others => @@ -5493,27 +5381,35 @@ begin -- Memory Flow Control Guard if (inst_valid_out = '1') then - inst_next_addr_base_next <= resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH); - -- Get Instance Data - inst_stage_next <= GET_INSTANCE_DATA; - if check_mask(inst_latch_data.field_flags,IMF_KEY_HASH_FLAG) then - inst_cnt_next <= 0; - elsif check_mask(inst_latch_data.field_flags,IMF_STATUS_FLAG) then - inst_cnt_next <= 4; - elsif check_mask(inst_latch_data.field_flags,IMF_SAMPLE_CNT_FLAG) then - inst_cnt_next <= 5; - elsif check_mask(inst_latch_data.field_flags,IMF_DISPOSED_CNT_FLAG) then - inst_cnt_next <= 6; - elsif check_mask(inst_latch_data.field_flags,IMF_NO_WRITERS_CNT_FLAG) then - inst_cnt_next <= 7; - elsif (TIME_BASED_FILTER_QOS /= DURATION_ZERO and check_mask(inst_latch_data.field_flags,IMF_IGNORE_DEADLINE_FLAG)) then - inst_cnt_next <= 8; - elsif check_mask(inst_latch_data.field_flags,IMF_WRITER_BITMAP_FLAG) then - inst_cnt_next <= 10; - inst_cnt2_next <= 0; - else + if (resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH) = INSTANCE_MEMORY_MAX_ADDRESS) then + inst_data_next.addr <= INSTANCE_MEMORY_MAX_ADDRESS; -- DONE inst_stage_next <= IDLE; + else + inst_data_next.addr <= resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH); + + -- Get Instance Data + inst_addr_base_next <= resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH); + inst_stage_next <= GET_INSTANCE_DATA; + if check_mask(inst_latch_data.field_flags,IMF_KEY_HASH_FLAG) then + inst_cnt_next <= 0; + elsif check_mask(inst_latch_data.field_flags,IMF_STATUS_FLAG) then + inst_cnt_next <= 4; + elsif check_mask(inst_latch_data.field_flags,IMF_SAMPLE_CNT_FLAG) then + inst_cnt_next <= 5; + elsif check_mask(inst_latch_data.field_flags,IMF_DISPOSED_CNT_FLAG) then + inst_cnt_next <= 6; + elsif check_mask(inst_latch_data.field_flags,IMF_NO_WRITERS_CNT_FLAG) then + inst_cnt_next <= 7; + elsif (TIME_BASED_FILTER_QOS /= DURATION_ZERO and check_mask(inst_latch_data.field_flags,IMF_IGNORE_DEADLINE_FLAG)) then + inst_cnt_next <= 8; + elsif check_mask(inst_latch_data.field_flags,IMF_WRITER_BITMAP_FLAG) then + inst_cnt_next <= 10; + inst_cnt2_next <= 0; + else + -- DONE + inst_stage_next <= IDLE; + end if; end if; end if; when others => @@ -5791,7 +5687,8 @@ begin -- Memory Flow Control Guard if (inst_valid_out = '1') then - inst_data_next.key_hash(3) <= inst_read_data; + inst_data_next.key_hash(3) <= inst_read_data; + inst_data_next.field_flags <= inst_data.field_flags or IMF_KEY_HASH_FLAG; if check_mask(inst_latch_data.field_flags,IMF_STATUS_FLAG) then inst_cnt_next <= 15; @@ -5817,7 +5714,8 @@ begin -- Memory Flow Control Guard if (inst_valid_out = '1') then - inst_data_next.status_info <= inst_read_data; + inst_data_next.status_info <= inst_read_data; + inst_data_next.field_flags <= inst_data.field_flags or IMF_STATUS_FLAG; if check_mask(inst_latch_data.field_flags,IMF_SAMPLE_CNT_FLAG) then inst_cnt_next <= 16; @@ -5841,7 +5739,8 @@ begin -- Memory Flow Control Guard if (inst_valid_out = '1') then - inst_data_next.sample_cnt <= unsigned(inst_read_data); + inst_data_next.sample_cnt <= unsigned(inst_read_data); + inst_data_next.field_flags <= inst_data.field_flags or IMF_SAMPLE_CNT_FLAG; if check_mask(inst_latch_data.field_flags,IMF_DISPOSED_CNT_FLAG) then inst_cnt_next <= 17; @@ -5863,7 +5762,8 @@ begin -- Memory Flow Control Guard if (inst_valid_out = '1') then - inst_data_next.disposed_gen_cnt <= unsigned(inst_read_data); + inst_data_next.disposed_gen_cnt <= unsigned(inst_read_data); + inst_data_next.field_flags <= inst_data.field_flags or IMF_DISPOSED_CNT_FLAG; if check_mask(inst_latch_data.field_flags,IMF_NO_WRITERS_CNT_FLAG) then inst_cnt_next <= 18; @@ -5883,7 +5783,8 @@ begin -- Memory Flow Control Guard if (inst_valid_out = '1') then - inst_data_next.no_writers_gen_cnt <= unsigned(inst_read_data); + inst_data_next.no_writers_gen_cnt <= unsigned(inst_read_data); + inst_data_next.field_flags <= inst_data.field_flags or IMF_NO_WRITERS_CNT_FLAG; if (TIME_BASED_FILTER_QOS /= DURATION_ZERO and check_mask(inst_latch_data.field_flags,IMF_IGNORE_DEADLINE_FLAG)) then inst_cnt_next <= 19; @@ -5911,7 +5812,8 @@ begin -- Memory Flow Control Guard if (inst_valid_out = '1') then - inst_data_next.ignore_deadline(1) <= unsigned(inst_read_data); + inst_data_next.ignore_deadline(1) <= unsigned(inst_read_data); + inst_data_next.field_flags <= inst_data.field_flags or IMF_IGNORE_DEADLINE_FLAG; if check_mask(inst_latch_data.field_flags,IMF_WRITER_BITMAP_FLAG) then inst_cnt_next <= 21; @@ -5930,6 +5832,7 @@ begin inst_data_next.writer_bitmap(inst_cnt2) <= inst_read_data; -- Exit Condition if (inst_cnt2 = WRITER_BITMAP_ARRAY_TYPE'length-1) then + inst_data_next.field_flags <= inst_data.field_flags or IMF_WRITER_BITMAP_FLAG; -- DONE inst_stage_next <= IDLE; else @@ -5941,18 +5844,8 @@ begin -- NOTE: Instances are inserted in KEY_HASH numerical order. case (inst_cnt) is - -- GET Next Instance - when 0 => - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_NEXT_ADDR_OFFSET; - inst_read <= '1'; - - -- Memory Flow Control Guard - if (inst_ready_in = '1') then - inst_cnt_next <= inst_cnt + 1; - end if; -- GET Key Hash 1/4 - when 1 => + when 0 => inst_valid_in <= '1'; inst_addr <= inst_addr_base + IMF_KEY_HASH_OFFSET; inst_read <= '1'; @@ -5962,7 +5855,7 @@ begin inst_cnt_next <= inst_cnt + 1; end if; -- GET Key Hash 2/4 - when 2 => + when 1 => inst_valid_in <= '1'; inst_addr <= inst_addr_base + IMF_KEY_HASH_OFFSET + 1; inst_read <= '1'; @@ -5972,7 +5865,7 @@ begin inst_cnt_next <= inst_cnt + 1; end if; -- GET Key Hash 3/4 - when 3 => + when 2 => inst_valid_in <= '1'; inst_addr <= inst_addr_base + IMF_KEY_HASH_OFFSET + 2; inst_read <= '1'; @@ -5982,7 +5875,7 @@ begin inst_cnt_next <= inst_cnt + 1; end if; -- GET Key Hash 4/4 - when 4 => + when 3 => inst_valid_in <= '1'; inst_addr <= inst_addr_base + IMF_KEY_HASH_OFFSET + 3; inst_read <= '1'; @@ -5991,201 +5884,90 @@ begin if (inst_ready_in = '1') then inst_cnt_next <= inst_cnt + 1; end if; - -- READ Next Instance + -- READ Key Hash 1/4 + when 4 => + inst_ready_out <= '1'; + + -- Memory Flow Control Guard + if (inst_valid_out = '1') then + -- Found Position (Before Current Instance) + if (inst_latch_data.key_hash(0) < inst_read_data) then + inst_abort_read <= '1'; + inst_addr_latch_next <= inst_addr_base; + inst_stage_next <= INSERT_INSTANCE; + inst_cnt_next <= 0; + -- BIGGER-THAN + elsif (inst_latch_data.key_hash(0) /= inst_read_data) then + inst_abort_read <= '1'; + -- Continue + inst_cnt_next <= 8; -- GET NEXT INSTANCE + else + inst_cnt_next <= inst_cnt + 1; + end if; + end if; + -- READ Key Hash 2/4 when 5 => inst_ready_out <= '1'; -- Memory Flow Control Guard if (inst_valid_out = '1') then - inst_next_addr_base_next <= resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH); - inst_cnt_next <= inst_cnt + 1; + -- Found Position (Before Current Instance) + if (inst_latch_data.key_hash(1) < inst_read_data) then + inst_abort_read <= '1'; + inst_addr_latch_next <= inst_addr_base; + inst_stage_next <= INSERT_INSTANCE; + inst_cnt_next <= 0; + -- BIGGER-THAN + elsif (inst_latch_data.key_hash(1) /= inst_read_data) then + inst_abort_read <= '1'; + -- Continue + inst_cnt_next <= 8; -- GET NEXT INSTANCE + else + inst_cnt_next <= inst_cnt + 1; + end if; end if; - -- READ Key Hash 1/4 + -- READ Key Hash 3/4 when 6 => inst_ready_out <= '1'; -- Memory Flow Control Guard if (inst_valid_out = '1') then - inst_cnt_next <= inst_cnt + 1; -- Found Position (Before Current Instance) - if (inst_latch_data.key_hash(0) < inst_read_data) then - inst_next_addr_base_next <= inst_addr_base; - inst_abort_read <= '1'; - -- Occupied List Head - if (inst_prev_addr_base = INSTANCE_MEMORY_MAX_ADDRESS) then - assert (inst_addr_base = inst_occupied_head) severity FAILURE; - inst_occupied_head_next <= inst_empty_head; - - inst_addr_base_next <= inst_empty_head; - inst_stage_next <= INSERT_INSTANCE; - inst_cnt_next <= 1; -- Skip First Step - else - inst_addr_base_next <= inst_empty_head; - inst_stage_next <= INSERT_INSTANCE; - inst_cnt_next <= 0; - end if; - -- BIGGER-THAN - elsif (inst_latch_data.key_hash(0) /= inst_read_data) then + if (inst_latch_data.key_hash(2) < inst_read_data) then inst_abort_read <= '1'; - -- End of Instances - if (inst_next_addr_base = INSTANCE_MEMORY_MAX_ADDRESS) then - inst_next_addr_base_next <= INSTANCE_MEMORY_MAX_ADDRESS; - inst_prev_addr_base_next <= inst_addr_base; - inst_addr_base_next <= inst_empty_head; - inst_stage_next <= INSERT_INSTANCE; - inst_cnt_next <= 0; - else - -- Continue - inst_prev_addr_base_next <= inst_addr_base; - inst_addr_base_next <= inst_next_addr_base; - inst_cnt_next <= 0; - end if; + inst_addr_latch_next <= inst_addr_base; + inst_stage_next <= INSERT_INSTANCE; + inst_cnt_next <= 0; + -- BIGGER-THAN + elsif (inst_latch_data.key_hash(2) /= inst_read_data) then + inst_abort_read <= '1'; + -- Continue + inst_cnt_next <= 8; -- GET NEXT INSTANCE + else + inst_cnt_next <= inst_cnt + 1; end if; end if; - -- READ Key Hash 2/4 + -- Key Hash 4/4 when 7 => inst_ready_out <= '1'; -- Memory Flow Control Guard if (inst_valid_out = '1') then - inst_cnt_next <= inst_cnt + 1; - -- Found Position (Before Current Instance) - if (inst_latch_data.key_hash(1) < inst_read_data) then - inst_next_addr_base_next <= inst_addr_base; - inst_abort_read <= '1'; - -- Occupied List Head - if (inst_prev_addr_base = INSTANCE_MEMORY_MAX_ADDRESS) then - assert (inst_addr_base = inst_occupied_head) severity FAILURE; - inst_occupied_head_next <= inst_empty_head; - - inst_addr_base_next <= inst_empty_head; - inst_stage_next <= INSERT_INSTANCE; - inst_cnt_next <= 1; -- Skip First Step - else - inst_addr_base_next <= inst_empty_head; - inst_stage_next <= INSERT_INSTANCE; - inst_cnt_next <= 0; - end if; - -- BIGGER-THAN - elsif (inst_latch_data.key_hash(1) /= inst_read_data) then - inst_abort_read <= '1'; - -- End of Instances - if (inst_next_addr_base = INSTANCE_MEMORY_MAX_ADDRESS) then - inst_next_addr_base_next <= INSTANCE_MEMORY_MAX_ADDRESS; - inst_prev_addr_base_next <= inst_addr_base; - inst_addr_base_next <= inst_empty_head; - inst_stage_next <= INSERT_INSTANCE; - inst_cnt_next <= 0; - else - -- Continue - inst_prev_addr_base_next <= inst_addr_base; - inst_addr_base_next <= inst_next_addr_base; - inst_cnt_next <= 0; - end if; - end if; - end if; - -- READ Key Hash 3/4 - when 8 => - inst_ready_out <= '1'; - - -- Memory Flow Control Guard - if (inst_valid_out = '1') then - inst_cnt_next <= inst_cnt + 1; - -- Found Position (Before Current Instance) - if (inst_latch_data.key_hash(2) < inst_read_data) then - inst_next_addr_base_next <= inst_addr_base; - inst_abort_read <= '1'; - -- Occupied List Head - if (inst_prev_addr_base = INSTANCE_MEMORY_MAX_ADDRESS) then - assert (inst_addr_base = inst_occupied_head) severity FAILURE; - inst_occupied_head_next <= inst_empty_head; - - inst_addr_base_next <= inst_empty_head; - inst_stage_next <= INSERT_INSTANCE; - inst_cnt_next <= 1; -- Skip First Step - else - inst_addr_base_next <= inst_empty_head; - inst_stage_next <= INSERT_INSTANCE; - inst_cnt_next <= 0; - end if; - -- BIGGER-THAN - elsif (inst_latch_data.key_hash(2) /= inst_read_data) then - inst_abort_read <= '1'; - -- End of Instances - if (inst_next_addr_base = INSTANCE_MEMORY_MAX_ADDRESS) then - inst_next_addr_base_next <= INSTANCE_MEMORY_MAX_ADDRESS; - inst_prev_addr_base_next <= inst_addr_base; - inst_addr_base_next <= inst_empty_head; - inst_stage_next <= INSERT_INSTANCE; - inst_cnt_next <= 0; - else - -- Continue - inst_prev_addr_base_next <= inst_addr_base; - inst_addr_base_next <= inst_next_addr_base; - inst_cnt_next <= 0; - end if; - end if; - end if; - -- Key Hash 4/4 - when 9 => - inst_ready_out <= '1'; - - -- Memory Flow Control Guard - if (inst_valid_out = '1') then - inst_cnt_next <= inst_cnt + 1; -- Found Position (Before Current Instance) if (inst_latch_data.key_hash(3) < inst_read_data) then - inst_next_addr_base_next <= inst_addr_base; - -- Occupied List Head - if (inst_prev_addr_base = INSTANCE_MEMORY_MAX_ADDRESS) then - assert (inst_addr_base = inst_occupied_head) severity FAILURE; - inst_occupied_head_next <= inst_empty_head; - - inst_addr_base_next <= inst_empty_head; - inst_stage_next <= INSERT_INSTANCE; - inst_cnt_next <= 1; -- Skip First Step - else - inst_addr_base_next <= inst_empty_head; - inst_stage_next <= INSERT_INSTANCE; - inst_cnt_next <= 0; - end if; + inst_abort_read <= '1'; + inst_addr_latch_next <= inst_addr_base; + inst_stage_next <= INSERT_INSTANCE; + inst_cnt_next <= 0; else assert (inst_latch_data.key_hash(3) /= inst_read_data) report "Duplicate Instance Detected" severity FAILURE; - -- End of Instances - if (inst_next_addr_base = INSTANCE_MEMORY_MAX_ADDRESS) then - inst_next_addr_base_next <= INSTANCE_MEMORY_MAX_ADDRESS; - inst_prev_addr_base_next <= inst_addr_base; - inst_addr_base_next <= inst_empty_head; - inst_stage_next <= INSERT_INSTANCE; - inst_cnt_next <= 0; - else - -- Continue - inst_prev_addr_base_next <= inst_addr_base; - inst_addr_base_next <= inst_next_addr_base; - inst_cnt_next <= 0; - end if; + -- Continue + inst_cnt_next <= inst_cnt + 1; end if; end if; - when others => - null; - end case; - when INSERT_INSTANCE => - -- Precondition: inst_addr_base set, inst_prev_addr_base set (Only if first Step executed), inst_next_addr_base set - - case (inst_cnt) is - -- SET Next Pointer (Previous Instance) - when 0 => - inst_valid_in <= '1'; - inst_addr <= inst_prev_addr_base + IMF_NEXT_ADDR_OFFSET; - inst_write_data <= std_logic_vector(resize(inst_addr_base,WORD_WIDTH)); - - -- Memory Flow Control Guard - if (inst_ready_in = '1') then - inst_cnt_next <= inst_cnt + 1; - end if; - -- GET Next Pointer - when 1 => + -- GET Next Instance + when 8 => inst_valid_in <= '1'; inst_addr <= inst_addr_base + IMF_NEXT_ADDR_OFFSET; inst_read <= '1'; @@ -6194,29 +5976,125 @@ begin if (inst_ready_in = '1') then inst_cnt_next <= inst_cnt + 1; end if; - -- SET Next Pointer (New Instance) - when 2 => + -- READ Next Instance + when 9 => + inst_ready_out <= '1'; + + -- Memory Flow Control Guard + if (inst_valid_out = '1') then + -- No more Endpoints + if (resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH) = INSTANCE_MEMORY_MAX_ADDRESS) then + inst_addr_latch_next <= INSTANCE_MEMORY_MAX_ADDRESS; + inst_stage_next <= INSERT_INSTANCE; + inst_cnt_next <= 0; + else + -- Continue + inst_addr_base_next <= resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH); + inst_cnt_next <= 0; + end if; + end if; + when others => + null; + end case; + when INSERT_INSTANCE => + case (inst_cnt) is + -- GET NEXT ADDR + when 0 => inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_NEXT_ADDR_OFFSET; - inst_write_data <= std_logic_vector(resize(inst_next_addr_base,WORD_WIDTH)); + inst_addr <= inst_empty_head + IMF_NEXT_ADDR_OFFSET; + inst_read <= '1'; -- Memory Flow Control Guard if (inst_ready_in = '1') then inst_cnt_next <= inst_cnt + 1; end if; - -- READ Next Pointer - when 3 => + -- SET NEXT ADDR + when 1 => + inst_valid_in <= '1'; + inst_addr <= inst_empty_head + IMF_NEXT_ADDR_OFFSET; + inst_write_data <= std_logic_vector(resize(inst_addr_latch,WORD_WIDTH)); + + -- Memory Flow Control Guard + if (inst_ready_in = '1') then + inst_cnt_next <= inst_cnt + 1; + end if; + -- READ NEXT ADDR + when 2 => inst_ready_out <= '1'; -- Memory Flow Control Guard if (inst_valid_out = '1') then -- Fix Empty List Head inst_empty_head_next <= resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH); + inst_addr_base_next <= inst_empty_head; + + -- No Next Instance (Occupied Tail) + if (inst_addr_latch = INSTANCE_MEMORY_MAX_ADDRESS) then + inst_cnt_next <= inst_cnt + 4; -- SET PREV ADDR + -- NOTE: inst_addr_base contains the current occupied tail + inst_addr_latch_next <= inst_addr_base; + else + inst_cnt_next <= inst_cnt + 1; + end if; + end if; + -- GET PREV ADDR (Next Instance) + when 3 => + inst_valid_in <= '1'; + inst_addr <= inst_addr_latch + IMF_PREV_ADDR_OFFSET; + inst_read <= '1'; + + -- Memory Flow Control Guard + if (inst_ready_in = '1') then + inst_cnt_next <= inst_cnt + 1; + end if; + -- SET PREV ADDR (Next Instance) + when 4 => + inst_valid_in <= '1'; + inst_addr <= inst_addr_latch + IMF_PREV_ADDR_OFFSET; + inst_write_data <= std_logic_vector(resize(inst_addr_base,WORD_WIDTH)); + + -- Memory Flow Control Guard + if (inst_ready_in = '1') then + inst_cnt_next <= inst_cnt + 1; + end if; + -- READ PREV ADDR + when 5 => + inst_ready_out <= '1'; + + -- Memory Flow Control Guard + if (inst_valid_out = '1') then + inst_addr_latch_next <= resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH); inst_cnt_next <= inst_cnt + 1; end if; - -- Key Hash 1/4 - when 4 => + -- SET PREV ADDR + when 6 => + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_PREV_ADDR_OFFSET; + inst_write_data <= std_logic_vector(resize(inst_addr_latch,WORD_WIDTH)); + + -- Memory Flow Control Guard + if (inst_ready_in = '1') then + -- No Previous Instance (Occupied Head) + if (inst_addr_latch = INSTANCE_MEMORY_MAX_ADDRESS) then + inst_cnt_next <= inst_cnt + 2; -- SET Key Hash 1/4 + inst_occupied_head_next <= inst_addr_base; + else + inst_cnt_next <= inst_cnt + 1; + end if; + end if; + -- SET NEXT ADDR (Previous Instance) + when 7 => + inst_valid_in <= '1'; + inst_addr <= inst_addr_latch + IMF_NEXT_ADDR_OFFSET; + inst_write_data <= std_logic_vector(resize(inst_addr_base,WORD_WIDTH)); + + -- Memory Flow Control Guard + if (inst_ready_in = '1') then + inst_cnt_next <= inst_cnt + 1; + end if; + -- SET Key Hash 1/4 + when 8 => inst_valid_in <= '1'; inst_addr <= inst_addr_base + IMF_KEY_HASH_OFFSET; inst_write_data <= inst_latch_data.key_hash(0); @@ -6226,8 +6104,8 @@ begin if (inst_ready_in = '1') then inst_cnt_next <= inst_cnt + 1; end if; - -- Key Hash 2/4 - when 5 => + -- SET Key Hash 2/4 + when 9 => inst_valid_in <= '1'; inst_addr <= inst_addr_base + IMF_KEY_HASH_OFFSET + 1; inst_write_data <= inst_latch_data.key_hash(1); @@ -6237,8 +6115,8 @@ begin if (inst_ready_in = '1') then inst_cnt_next <= inst_cnt + 1; end if; - -- Key Hash 3/4 - when 6 => + -- SET Key Hash 3/4 + when 10 => inst_valid_in <= '1'; inst_addr <= inst_addr_base + IMF_KEY_HASH_OFFSET + 2; inst_write_data <= inst_latch_data.key_hash(2); @@ -6248,56 +6126,61 @@ begin if (inst_ready_in = '1') then inst_cnt_next <= inst_cnt + 1; end if; - -- Key Hash 4/4 - when 7 => + -- SET Key Hash 4/4 + when 11 => inst_valid_in <= '1'; inst_addr <= inst_addr_base + IMF_KEY_HASH_OFFSET + 3; inst_write_data <= inst_latch_data.key_hash(3); inst_data_next.key_hash(3) <= inst_latch_data.key_hash(3); + inst_data_next.field_flags <= inst_data.field_flags or IMF_KEY_HASH_FLAG; -- Memory Flow Control Guard if (inst_ready_in = '1') then inst_cnt_next <= inst_cnt + 1; end if; - -- Status Info - when 8 => + -- SET Status Info + when 12 => inst_valid_in <= '1'; inst_addr <= inst_addr_base + IMF_STATUS_INFO_OFFSET; inst_write_data <= inst_latch_data.status_info; inst_data_next.status_info <= inst_latch_data.status_info; + inst_data_next.field_flags <= inst_data.field_flags or IMF_STATUS_FLAG; -- Memory Flow Control Guard if (inst_ready_in = '1') then inst_cnt_next <= inst_cnt + 1; end if; - -- Sample Count - when 9 => + -- SET Sample Count + when 13 => inst_valid_in <= '1'; inst_addr <= inst_addr_base + IMF_SAMPLE_CNT_OFFSET; inst_write_data <= std_logic_vector(inst_latch_data.sample_cnt); inst_data_next.sample_cnt <= inst_latch_data.sample_cnt; + inst_data_next.field_flags <= inst_data.field_flags or IMF_SAMPLE_CNT_FLAG; -- Memory Flow Control Guard if (inst_ready_in = '1') then inst_cnt_next <= inst_cnt + 1; end if; - -- Disposed Generation Count - when 10 => + -- SET Disposed Generation Count + when 14 => inst_valid_in <= '1'; inst_addr <= inst_addr_base + IMF_DISPOSED_GEN_CNT_OFFSET; inst_write_data <= (others => '0'); inst_data_next.disposed_gen_cnt <= (others => '0'); + inst_data_next.field_flags <= inst_data.field_flags or IMF_DISPOSED_CNT_FLAG; -- Memory Flow Control Guard if (inst_ready_in = '1') then inst_cnt_next <= inst_cnt + 1; end if; - -- No Writers Generation Count - when 11 => + -- SET No Writers Generation Count + when 15 => inst_valid_in <= '1'; inst_addr <= inst_addr_base + IMF_NO_WRITERS_GEN_CNT_OFFSET; inst_write_data <= (others => '0'); inst_data_next.no_writers_gen_cnt <= (others => '0'); + inst_data_next.field_flags <= inst_data.field_flags or IMF_NO_WRITERS_CNT_FLAG; -- Memory Flow Control Guard if (inst_ready_in = '1') then @@ -6308,29 +6191,29 @@ begin inst_cnt2_next <= 0; end if; end if; - - -- Ignore Deadline 1/2 - when 12 => + -- SET Ignore Deadline 1/2 + when 16 => -- Synthesis Guard if (TIME_BASED_FILTER_QOS /= DURATION_ZERO) then inst_valid_in <= '1'; inst_addr <= inst_addr_base + IMF_IGNORE_DEADLINE_OFFSET; - inst_write_data <= std_logic_vector(inst_latch_data.deadline(0)); - inst_data_next.ignore_deadline(0) <= inst_latch_data.deadline(0); + inst_write_data <= std_logic_vector(inst_latch_data.ignore_deadline(0)); + inst_data_next.ignore_deadline(0) <= inst_latch_data.ignore_deadline(0); -- Memory Flow Control Guard if (inst_ready_in = '1') then inst_cnt_next <= inst_cnt + 1; end if; end if; - -- Ignore Deadline 2/2 - when 13 => + -- SET Ignore Deadline 2/2 + when 17 => -- Synthesis Guard if (TIME_BASED_FILTER_QOS /= DURATION_ZERO) then inst_valid_in <= '1'; inst_addr <= inst_addr_base + IMF_IGNORE_DEADLINE_OFFSET + 1; - inst_write_data <= std_logic_vector(inst_latch_data.deadline(1)); - inst_data_next.ignore_deadline(1) <= inst_latch_data.deadline(1); + inst_write_data <= std_logic_vector(inst_latch_data.ignore_deadline(1)); + inst_data_next.ignore_deadline(1) <= inst_latch_data.ignore_deadline(1); + inst_data_next.field_flags <= inst_data.field_flags or IMF_IGNORE_DEADLINE_FLAG; -- Memory Flow Control Guard if (inst_ready_in = '1') then @@ -6338,8 +6221,8 @@ begin inst_cnt2_next <= 0; end if; end if; - -- Writer Bitmap - when 14 => + -- SET Writer Bitmap + when 18 => -- XXX: Possible Worst case Path (2 Additions in same clock) inst_valid_in <= '1'; inst_addr <= inst_addr_base + IMF_WRITER_BITMAP_OFFSET + inst_cnt2; @@ -6350,6 +6233,7 @@ begin if (inst_ready_in = '1') then -- Exit Condition if (inst_cnt2 = WRITER_BITMAP_ARRAY_TYPE'length-1) then + inst_data_next.field_flags <= inst_data.field_flags or IMF_WRITER_BITMAP_FLAG; -- DONE inst_stage_next <= IDLE; else @@ -6367,6 +6251,7 @@ begin inst_addr <= inst_addr_base + IMF_STATUS_INFO_OFFSET; inst_write_data <= inst_latch_data.status_info; inst_data_next.status_info <= inst_latch_data.status_info; + inst_data_next.field_flags <= inst_data.field_flags or IMF_STATUS_FLAG; -- Memory Flow Control Guard if (inst_ready_in = '1') then if check_mask(inst_latch_data.field_flags,IMF_SAMPLE_CNT_FLAG) then @@ -6391,6 +6276,7 @@ begin inst_addr <= inst_addr_base + IMF_SAMPLE_CNT_OFFSET; inst_write_data <= std_logic_vector(inst_latch_data.sample_cnt); inst_data_next.sample_cnt <= inst_latch_data.sample_cnt; + inst_data_next.field_flags <= inst_data.field_flags or IMF_SAMPLE_CNT_FLAG; -- Memory Flow Control Guard if (inst_ready_in = '1') then if check_mask(inst_latch_data.field_flags,IMF_DISPOSED_CNT_FLAG) then @@ -6411,8 +6297,9 @@ begin when 2 => inst_valid_in <= '1'; inst_addr <= inst_addr_base + IMF_DISPOSED_GEN_CNT_OFFSET; - inst_write_data <= std_logic_vector(inst_latch_data.gen_cnt); - inst_data_next.disposed_gen_cnt <= inst_latch_data.gen_cnt; + inst_write_data <= std_logic_vector(inst_latch_data.disposed_gen_cnt); + inst_data_next.disposed_gen_cnt <= inst_latch_data.disposed_gen_cnt; + inst_data_next.field_flags <= inst_data.field_flags or IMF_DISPOSED_CNT_FLAG; -- Memory Flow Control Guard if (inst_ready_in = '1') then if check_mask(inst_latch_data.field_flags,IMF_NO_WRITERS_CNT_FLAG) then @@ -6431,8 +6318,9 @@ begin when 3 => inst_valid_in <= '1'; inst_addr <= inst_addr_base + IMF_NO_WRITERS_GEN_CNT_OFFSET; - inst_write_data <= std_logic_vector(inst_latch_data.gen_cnt); - inst_data_next.no_writers_gen_cnt <= inst_latch_data.gen_cnt; + inst_write_data <= std_logic_vector(inst_latch_data.no_writers_gen_cnt); + inst_data_next.no_writers_gen_cnt <= inst_latch_data.no_writers_gen_cnt; + inst_data_next.field_flags <= inst_data.field_flags or IMF_NO_WRITERS_CNT_FLAG; -- Memory Flow Control Guard if (inst_ready_in = '1') then if (TIME_BASED_FILTER_QOS /= DURATION_ZERO and check_mask(inst_latch_data.field_flags,IMF_IGNORE_DEADLINE_FLAG)) then @@ -6450,8 +6338,8 @@ begin if (TIME_BASED_FILTER_QOS /= DURATION_ZERO) then inst_valid_in <= '1'; inst_addr <= inst_addr_base + IMF_IGNORE_DEADLINE_OFFSET; - inst_write_data <= std_logic_vector(inst_latch_data.deadline(0)); - inst_data_next.ignore_deadline(0) <= inst_latch_data.deadline(0); + inst_write_data <= std_logic_vector(inst_latch_data.ignore_deadline(0)); + inst_data_next.ignore_deadline(0) <= inst_latch_data.ignore_deadline(0); -- Memory Flow Control Guard if (inst_ready_in = '1') then inst_cnt_next <= inst_cnt + 1; @@ -6462,8 +6350,9 @@ begin if (TIME_BASED_FILTER_QOS /= DURATION_ZERO) then inst_valid_in <= '1'; inst_addr <= inst_addr_base + IMF_IGNORE_DEADLINE_OFFSET + 1; - inst_write_data <= std_logic_vector(inst_latch_data.deadline(1)); - inst_data_next.ignore_deadline(1) <= inst_latch_data.deadline(1); + inst_write_data <= std_logic_vector(inst_latch_data.ignore_deadline(1)); + inst_data_next.ignore_deadline(1) <= inst_latch_data.ignore_deadline(1); + inst_data_next.field_flags <= inst_data.field_flags or IMF_IGNORE_DEADLINE_FLAG; -- Memory Flow Control Guard if (inst_ready_in = '1') then if check_mask(inst_latch_data.field_flags,IMF_WRITER_BITMAP_FLAG) then @@ -6486,6 +6375,7 @@ begin if (inst_ready_in = '1') then -- Exit Condition if (inst_cnt2 = WRITER_BITMAP_ARRAY_TYPE'length-1) then + inst_data_next.field_flags <= inst_data.field_flags or IMF_WRITER_BITMAP_FLAG; -- DONE inst_stage_next <= IDLE; else @@ -6496,67 +6386,98 @@ begin null; end case; when REMOVE_INSTANCE => - -- Precondition: inst_addr_base set, inst_prev_addr_base set - case (inst_cnt) is - -- GET Next Instance + -- GET Next Addr when 0 => - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_NEXT_ADDR_OFFSET; - inst_read <= '1'; - + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_NEXT_ADDR_OFFSET; + inst_read <= '1'; -- Memory Flow Control Guard if (inst_ready_in = '1') then - inst_cnt_next <= inst_cnt + 1; + inst_cnt_next <= inst_cnt + 1; end if; - -- READ Next Instance + -- GET Prev Addr when 1 => - inst_ready_out <= '1'; - + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_PREV_ADDR_OFFSET; + inst_read <= '1'; -- Memory Flow Control Guard - if (inst_valid_out = '1') then - inst_next_addr_base_next <= resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH); - - -- Removed Instance is List Head - if (inst_prev_addr_base = INSTANCE_MEMORY_MAX_ADDRESS) then - assert (inst_addr_base = inst_occupied_head) severity FAILURE; - - -- Fix Occupied Head - inst_occupied_head_next <= resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH); - - inst_cnt_next <= inst_cnt + 2; -- Skip Next Step - else - inst_cnt_next <= inst_cnt + 1; - end if; + if (inst_ready_in = '1') then + inst_cnt_next <= inst_cnt + 1; end if; - -- SET Next Pointer (Previous Instance) + -- SET Next Addr when 2 => - -- Point Previous instance to Next Instance (Remove current Instance from inbetween) - inst_valid_in <= '1'; - inst_addr <= inst_prev_addr_base + IMF_NEXT_ADDR_OFFSET; - inst_write_data <= std_logic_vector(resize(inst_next_addr_base,WORD_WIDTH)); + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_NEXT_ADDR_OFFSET; + inst_write_data <= std_logic_vector(resize(inst_empty_head,WORD_WIDTH)); - -- Memory Flow Control Guard if (inst_ready_in = '1') then - inst_cnt_next <= inst_cnt + 1; - end if; - -- SET Next Pointer (Current/Removed Instance) - when 3 => - -- Point Current Instance to Empty List Head (Make Removed Instance Head of the Empty List) - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_NEXT_ADDR_OFFSET; - inst_write_data <= std_logic_vector(resize(inst_empty_head,WORD_WIDTH)); - - -- Memory Flow Control Guard - if (inst_ready_in = '1') then - -- Fix Empty List Head + -- Set New Empty Head inst_empty_head_next <= inst_addr_base; - -- Reset - inst_addr_base_next <= INSTANCE_MEMORY_MAX_ADDRESS; - + inst_cnt_next <= inst_cnt + 1; + end if; + -- READ Next Addr + when 3 => + inst_ready_out <= '1'; + -- Memory Flow Control Guard + if (inst_valid_out = '1') then + inst_addr_latch_next <= resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH); + inst_cnt_next <= inst_cnt + 1; + end if; + -- READ Prev Addr + when 4 => + inst_ready_out <= '1'; + -- Memory Flow Control Guard + if (inst_valid_out = '1') then + if (inst_addr_latch = INSTANCE_MEMORY_MAX_ADDRESS) then + if (resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH) = INSTANCE_MEMORY_MAX_ADDRESS) then + -- RESET Occupied List Head + inst_occupied_head_next <= INSTANCE_MEMORY_MAX_ADDRESS; + + inst_data_next.addr <= INSTANCE_MEMORY_MAX_ADDRESS; + -- DONE + inst_stage_next <= IDLE; + else + inst_addr_base_next <= resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH); + inst_cnt_next <= inst_cnt + 2; -- Skip Next Step + end if; + else + inst_addr_base_next <= inst_addr_latch; + inst_addr_latch_next <= resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH); + inst_cnt_next <= inst_cnt + 1; + end if; + end if; + -- SET Prev Addr (Next Slot) + when 5 => + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_PREV_ADDR_OFFSET; + inst_write_data <= std_logic_vector(resize(inst_addr_latch,WORD_WIDTH)); + + if (inst_ready_in = '1') then + if (inst_addr_latch = INSTANCE_MEMORY_MAX_ADDRESS) then + -- Set New Occupied List Head + inst_occupied_head_next <= inst_addr_base; + + inst_data_next.addr <= inst_addr_base; + -- DONE + inst_stage_next <= IDLE; + else + inst_addr_base_next <= inst_addr_latch; + inst_addr_latch_next <= inst_addr_base; + inst_cnt_next <= inst_cnt + 1; + end if; + end if; + -- SET Next Addr (Previous Slot) + when 6 => + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_NEXT_ADDR_OFFSET; + inst_write_data <= std_logic_vector(resize(inst_addr_latch,WORD_WIDTH)); + + if (inst_ready_in = '1') then + inst_data_next.addr <= inst_addr_latch; -- DONE - inst_stage_next <= IDLE; + inst_stage_next <= IDLE; end if; when others => null; @@ -6591,7 +6512,7 @@ begin -- Memory Flow Control Guard if (inst_valid_out = '1') then - inst_next_addr_base_next <= resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH); + inst_addr_latch_next <= resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH); inst_cnt_next <= inst_cnt + 1; end if; -- READ Status Info @@ -6608,12 +6529,12 @@ begin inst_cnt_next <= inst_cnt + 1; else -- End of Instances - if (inst_next_addr_base = INSTANCE_MEMORY_MAX_ADDRESS) then + if (inst_addr_latch = INSTANCE_MEMORY_MAX_ADDRESS) then -- DONE inst_stage_next <= IDLE; else -- Continue - inst_addr_base_next <= inst_next_addr_base; + inst_addr_base_next <= inst_addr_latch; inst_cnt_next <= 0; end if; end if; @@ -6627,12 +6548,12 @@ begin -- Memory Flow Control Guard if (inst_ready_in = '1') then -- End of Instances - if (inst_next_addr_base = INSTANCE_MEMORY_MAX_ADDRESS) then + if (inst_addr_latch = INSTANCE_MEMORY_MAX_ADDRESS) then -- DONE inst_stage_next <= IDLE; else -- Continue - inst_addr_base_next <= inst_next_addr_base; + inst_addr_base_next <= inst_addr_latch; inst_cnt_next <= 0; end if; end if; @@ -6641,35 +6562,44 @@ begin end case; when RESET_MEMORY => case (inst_cnt) is - -- Initialize + -- SET Next Pointer when 0 => - inst_addr_base_next <= FIRST_INSTANCE_ADDRESS; - inst_cnt_next <= inst_cnt + 1; - -- Set Next Pointer - when 1 => - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_NEXT_ADDR_OFFSET; + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_NEXT_ADDR_OFFSET; if (inst_addr_base = MAX_INSTANCE_ADDRESS) then - inst_write_data <= std_logic_vector(resize(INSTANCE_MEMORY_MAX_ADDRESS,WORD_WIDTH)); + inst_write_data <= std_logic_vector(resize(INSTANCE_MEMORY_MAX_ADDRESS,WORD_WIDTH)); else - inst_write_data <= std_logic_vector(resize(inst_addr_base + INSTANCE_FRAME_SIZE,WORD_WIDTH)); + inst_write_data <= std_logic_vector(resize(inst_addr_base + INSTANCE_FRAME_SIZE,WORD_WIDTH)); end if; + -- Memory Flow Control Guard + if (inst_ready_in = '1') then + inst_cnt_next <= inst_cnt + 1; + end if; + -- SET Previous Pointer + when 1 => + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_PREV_ADDR_OFFSET; + inst_write_data <= std_logic_vector(resize(inst_addr_latch,WORD_WIDTH)); + -- Memory Flow Control Guard if (inst_ready_in = '1') then if (inst_addr_base = MAX_INSTANCE_ADDRESS) then - -- DONE - inst_stage_next <= IDLE; + -- Initialize Empty and Occupied Heads inst_empty_head_next <= FIRST_INSTANCE_ADDRESS; + inst_occupied_head_next <= INSTANCE_MEMORY_MAX_ADDRESS; + + -- DONE + inst_stage_next <= IDLE; else - inst_addr_base_next <= inst_addr_base + INSTANCE_FRAME_SIZE; + inst_addr_latch_next <= inst_addr_base; + inst_addr_base_next <= inst_addr_base + INSTANCE_FRAME_SIZE; + inst_cnt_next <= 0; end if; end if; when others => null; end case; - when others => - null; end case; end process; end generate; @@ -6685,10 +6615,9 @@ begin empty_sample_list_head <= SAMPLE_MEMORY_MAX_ADDRESS; empty_sample_list_tail <= SAMPLE_MEMORY_MAX_ADDRESS; empty_payload_list_head <= PAYLOAD_MEMORY_MAX_ADDRESS; - inst_addr_base <= INSTANCE_MEMORY_MAX_ADDRESS; + inst_addr_base <= FIRST_INSTANCE_ADDRESS; + inst_addr_latch <= INSTANCE_MEMORY_MAX_ADDRESS; inst_occupied_head <= INSTANCE_MEMORY_MAX_ADDRESS; - inst_next_addr_base <= INSTANCE_MEMORY_MAX_ADDRESS; - inst_prev_addr_base <= INSTANCE_MEMORY_MAX_ADDRESS; inst_empty_head <= INSTANCE_MEMORY_MAX_ADDRESS; key_hash <= KEY_HASH_NIL; si_instance_handle_sig <= HANDLE_NIL; @@ -6708,7 +6637,10 @@ begin si_instance_state_sig <= ANY_INSTANCE_STATE; instance_state <= ANY_INSTANCE_STATE; inst_data <= ZERO_INSTANCE_DATA; - inst_latch_data <= ZERO_INST_LATCH_DATA; + if (not WITH_KEY) then + inst_data.field_flags <= (others => '1'); + end if; + inst_latch_data <= ZERO_INSTANCE_DATA; sample_rej_last_reason <= NOT_REJECTED; rtps_return_code_latch <= ERROR; dds_return_code_latch <= RETCODE_ERROR; @@ -6736,7 +6668,6 @@ begin wait_for_sample_removal <= '0'; dis_gen_cnt_latch <= (others => '0'); no_w_gen_cnt_latch <= (others => '0'); - current_imf <= (others => '0'); sample_addr_latch_1 <= (others => '0'); sample_addr_latch_2 <= (others => '0'); sample_addr_latch_3 <= (others => '0'); @@ -6774,9 +6705,8 @@ begin empty_sample_list_tail <= empty_sample_list_tail_next; empty_payload_list_head <= empty_payload_list_head_next; inst_addr_base <= inst_addr_base_next; + inst_addr_latch <= inst_addr_latch_next; inst_occupied_head <= inst_occupied_head_next; - inst_next_addr_base <= inst_next_addr_base_next; - inst_prev_addr_base <= inst_prev_addr_base_next; inst_empty_head <= inst_empty_head_next; key_hash <= key_hash_next; si_instance_handle_sig <= si_instance_handle_sig_next; @@ -6828,11 +6758,6 @@ begin wait_for_sample_removal <= wait_for_sample_removal_next; dis_gen_cnt_latch <= dis_gen_cnt_latch_next; no_w_gen_cnt_latch <= no_w_gen_cnt_latch_next; - if (WITH_KEY) then - current_imf <= current_imf_next; - else - current_imf <= (others => '1'); - end if; sample_addr_latch_1 <= sample_addr_latch_1_next; sample_addr_latch_2 <= sample_addr_latch_2_next; sample_addr_latch_3 <= sample_addr_latch_3_next; diff --git a/src/dds_writer.vhd b/src/dds_writer.vhd index 6582ea1..6969868 100644 --- a/src/dds_writer.vhd +++ b/src/dds_writer.vhd @@ -142,7 +142,7 @@ architecture arch of dds_writer is -- *INSTANCE MEMORY* -- 4-Byte Word Size of a Instance Entry in Memory - constant INSTANCE_FRAME_SIZE : natural := 8; + constant INSTANCE_FRAME_SIZE : natural := 9; -- Instance Memory Size in 4-Byte Words constant INSTANCE_MEMORY_SIZE : natural := to_integer(unsigned(MAX_INSTANCES)) * INSTANCE_FRAME_SIZE; -- Instance Memory Address Width @@ -193,10 +193,11 @@ architecture arch of dds_writer is -- *INSTANCE MEMORY FIELD OFFSETS* -- 4-Byte Word Offsets to Beginning of Respective Fields in the Endpoint Memory Frame constant IMF_NEXT_ADDR_OFFSET : natural := 0; - constant IMF_KEY_HASH_OFFSET : natural := 1; - constant IMF_STATUS_INFO_OFFSET : natural := 5; - constant IMF_SAMPLE_CNT_OFFSET : natural := 6; - constant IMF_ACK_CNT_OFFSET : natural := 7; + constant IMF_PREV_ADDR_OFFSET : natural := 1; + constant IMF_KEY_HASH_OFFSET : natural := 2; + constant IMF_STATUS_INFO_OFFSET : natural := 6; + constant IMF_SAMPLE_CNT_OFFSET : natural := 7; + constant IMF_ACK_CNT_OFFSET : natural := 8; -- *INSTANCE MEMORY FRAME FIELD FLAGS* -- Flags mapping to the respective Endpoint Memory Frame Fields @@ -211,61 +212,42 @@ architecture arch of dds_writer is type STAGE_TYPE is (IDLE, UNKNOWN_OPERATION_DDS, UNKNOWN_OPERATION_RTPS, UNKNOWN_SEQ_NR, ASSERT_LIVELINESS, ADD_SAMPLE_INFO, ADD_PAYLOAD, NEXT_PAYLOAD_SLOT, ALIGN_PAYLOAD, GET_KEY_HASH, INITIATE_INSTANCE_SEARCH, REGISTER_OPERATION, LOOKUP_OPERATION, PUSH_KEY_HASH, FILTER_STAGE, UPDATE_INSTANCE, FINALIZE_PAYLOAD, FINALIZE_SAMPLE, GET_OLDEST_SAMPLE_INSTANCE, FIND_SAMPLE, REMOVE_ORPHAN_SAMPLES, REMOVE_SAMPLE, - POST_SAMPLE_REMOVE, SKIP_AND_RETURN, SKIP, REMOVE_STALE_INSTANCE, GET_SEQ_NR, FIND_SEQ_NR, ACKNACK_SAMPLE, GET_SAMPLE, GET_PAYLOAD, GET_SERIALIZED_KEY, + POST_SAMPLE_REMOVE, SKIP_AND_RETURN, SKIP, REMOVE_STALE_INSTANCE, GET_SEQ_NR, FIND_SEQ_NR, ACKNACK_SAMPLE, GET_SAMPLE, GET_PAYLOAD, CHECK_LIFESPAN, GET_LIVELINESS_LOST_STATUS, GET_OFFERED_DEADLINE_MISSED_STATUS, CHECK_DEADLINE, RESET_SAMPLE_MEMORY, RESET_PAYLOAD_MEMORY); -- Instance Memory FSM states. Explained below in detail - type INST_STAGE_TYPE is (IDLE, SEARCH_INSTANCE_HASH, SEARCH_INSTANCE_ADDR, GET_NEXT_INSTANCE, GET_INSTANCE_DATA, INSERT_INSTANCE, UPDATE_INSTANCE, + type INST_STAGE_TYPE is (IDLE, SEARCH_INSTANCE, GET_NEXT_INSTANCE, GET_INSTANCE_DATA, INSERT_INSTANCE, UPDATE_INSTANCE, REMOVE_INSTANCE, RESET_MEMORY); -- *Instance Memory Opcodes* -- OPCODE DESCRIPTION - -- SEARCH_INSTANCE_HASH Search Instance based on Key Hash pointed by "key_hash". - -- Set "inst_addr_base" to Base Address of found Instance, of INSTANCE_MEMORY_MAX_ADDRESS if nothing found. - -- "inst_data" contains Instance Data according to "inst_mem_fields". - -- SEARCH_INSTANCE_ADDR Search Instance based on Instance Pointer pointed by "inst_addr_update". - -- Set "inst_addr_base" to "inst_addr_update" - -- "inst_data" contains Instance Data according to "inst_mem_fields". + -- SEARCH_INSTANCE Search Instance based on Key Hash pointed by "inst_r.key_hash". + -- Set "inst_data.addr" to Base Address of found Instance, or INSTANCE_MEMORY_MAX_ADDRESS if nothing found. + -- "inst_data" contains Instance Data according to "inst_r.field_flags". -- INSERT_INSTANCE Insert Instance to memory. - -- UPDATE_INSTANCE Update Instance Data pointed by "inst_addr_base" according to "inst_mem_fields" - -- GET_FIRST_INSTANCE Get Instance Data of first Instance according to "inst_mem_fields". - -- Set "inst_addr_base" to Address of Instance or INSTANCE_MEMORY_MAX_ADDRESS if no Instance in Memory. - -- GET_NEXT_INSTANCE Get Instance Data of next Instance (from the Instance pointed by "inst_addr_base") according to "inst_mem_fields". - -- Set "inst_addr_base" to Address of Instance or INSTANCE_MEMORY_MAX_ADDRESS if no other Instance in Memory. - -- REMOVE_INSTANCE Remove Instance pointed by "inst_addr_base". - -- GET_INSTANCE Get Data of Instance pointed by "inst_addr_update" according to "inst_mem_fields". + -- UPDATE_INSTANCE Update Instance Data pointed by "inst_data.addr" according to "inst_r.field_flags" + -- GET_INSTANCE Get Data of Instance pointed by "inst_r.addr" according to "inst_r.field_flags". -- Already fetched Data of the Participant is not modified. - type INSTANCE_OPCODE_TYPE is (NOP, SEARCH_INSTANCE_HASH, SEARCH_INSTANCE_ADDR, INSERT_INSTANCE, UPDATE_INSTANCE, GET_FIRST_INSTANCE, GET_NEXT_INSTANCE, REMOVE_INSTANCE, - GET_INSTANCE); + -- GET_NEXT_INSTANCE Get Instance Data of next Instance (from the Instance pointed by "inst_data.addr") according to "inst_r.field_flags". + -- Set "inst_data.addr" to Address of Instance or INSTANCE_MEMORY_MAX_ADDRESS if no other Instance in Memory. + -- REMOVE_INSTANCE Remove Instance pointed by "inst_data.addr". + -- "inst_data.addr" is set to the next Instance (or INSTANCE_MEMORY_MAX_ADDRESS if no next Instance exists) + type INSTANCE_OPCODE_TYPE is (NOP, SEARCH_INSTANCE, INSERT_INSTANCE, UPDATE_INSTANCE, GET_INSTANCE, GET_NEXT_INSTANCE, REMOVE_INSTANCE); -- Record of Instance Data type INSTANCE_DATA_TYPE is record - key_hash : KEY_HASH_TYPE; - status_info : std_logic_vector(WORD_WIDTH-1 downto 0); - sample_cnt : unsigned(WORD_WIDTH-1 downto 0); - ack_cnt : unsigned(WORD_WIDTH-1 downto 0); - end record; - -- Zero initialized Endpoint Data - constant ZERO_INSTANCE_DATA : INSTANCE_DATA_TYPE := ( - key_hash => KEY_HASH_NIL, - status_info => (others => '0'), - sample_cnt => (others => '0'), - ack_cnt => (others => '0') - ); - -- Instance Data Latch used as temporal cache by Instance Memory FSM - type INST_LATCH_DATA_TYPE is record + addr : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0); key_hash : KEY_HASH_TYPE; status_info : std_logic_vector(CDR_LONG_WIDTH-1 downto 0); sample_cnt : unsigned(CDR_LONG_WIDTH-1 downto 0); ack_cnt : unsigned(CDR_LONG_WIDTH-1 downto 0); field_flags : std_logic_vector(0 to IMF_FLAG_WIDTH-1); - addr : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0); end record; - -- Zero initialized Instance Data Latch - constant ZERO_INST_LATCH_DATA : INST_LATCH_DATA_TYPE := ( + -- Zero initialized Endpoint Data + constant ZERO_INSTANCE_DATA : INSTANCE_DATA_TYPE := ( + addr => INSTANCE_MEMORY_MAX_ADDRESS, key_hash => KEY_HASH_NIL, status_info => (others => '0'), sample_cnt => (others => '0'), ack_cnt => (others => '0'), - field_flags => (others => '0'), - addr => (others => '0') + field_flags => (others => '0') ); --*****SIGNAL DECLARATION***** @@ -357,22 +339,14 @@ architecture arch of dds_writer is signal inst_addr_latch_2, inst_addr_latch_2_next : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0); -- General Purpose Long Latch signal long_latch, long_latch_next : std_logic_vector(CDR_LONG_WIDTH-1 downto 0); - -- Signal used to pass Sample Status Infos to Instance Memory Process - signal status_info_update : std_logic_vector(CDR_LONG_WIDTH-1 downto 0); - -- Signal containing the relevant Instance Memory Frame Fields of the Instance Memory Operation - signal inst_mem_fields : std_logic_vector(0 to IMF_FLAG_WIDTH-1); - -- Signal used to pass Instance Pointers to the Instance Memory Process - signal inst_addr_update : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0); - -- Signal used to pass Sample Counts to the Instance Memory Process - signal sample_cnt : unsigned(CDR_LONG_WIDTH-1 downto 0); - -- Signal used to pass ACK Counts to the Instance Memory Process - signal ack_cnt : unsigned(CDR_LONG_WIDTH-1 downto 0); -- Signals start of Instance Memory Operation signal inst_op_start : std_logic; -- Opcode of Instance Memory Operation (Valid only when inst_op_start is high) signal inst_opcode : INSTANCE_OPCODE_TYPE; -- Signals the end of an Instance Memory Operation signal inst_op_done : std_logic; + -- Signal used to pass data to instance memory process + signal inst_r : INSTANCE_DATA_TYPE; -- Time of next Sample Lifespan Check signal lifespan_time, lifespan_time_next : TIME_TYPE; -- Signifies if a Lifespan Check is in progress @@ -436,26 +410,22 @@ architecture arch of dds_writer is signal inst_stage, inst_stage_next : INST_STAGE_TYPE; -- Pointer to current relevant Instance Memory Frame Address signal inst_addr_base, inst_addr_base_next : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0); - -- Pointer to next Instance Memory Frame Address - signal inst_next_addr_base, inst_next_addr_base_next : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0); - -- Pointer to previous Instacne Memory Address - signal inst_prev_addr_base, inst_prev_addr_base_next : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0); + -- General Purpose Instance Memory Address Latch + signal inst_addr_latch, inst_addr_latch_next : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0); -- Head of Empty Instance List signal inst_empty_head, inst_empty_head_next : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0); -- Head of Occupied Instance List signal inst_occupied_head, inst_occupied_head_next : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0); -- Latch for Instance Data from main process - signal inst_latch_data, inst_latch_data_next : INST_LATCH_DATA_TYPE; + signal inst_latch_data, inst_latch_data_next : INSTANCE_DATA_TYPE; -- NOTE: The next signal is driven by the inst_ctrl_prc. In case WITH_KEY is FALSE, no inst_ctrl_prc is generated and the inst_data is - -- set by the main process directly by drivng the next2 signal. The sync_prc is responsible for latching the corrct next signal. + -- set by the main process directly by drivng the next2 signal. The sync_prc is responsible for latching the correct next signal. -- Latch for Instance Data from memory signal inst_data, inst_data_next, inst_data_next2 : INSTANCE_DATA_TYPE; -- General Purpose Counter signal inst_cnt, inst_cnt_next : natural range 0 to 13; -- General Purpose Long Latch signal inst_long_latch, inst_long_latch_next : std_logic_vector(CDR_LONG_WIDTH-1 downto 0); - -- Instance Memory Flag Array denoting which inst_data Fields are up-to-date with the respective fields of the Instance (Pointed by inst_addr_base) - signal current_imf, current_imf_next : std_logic_vector(0 to IMF_FLAG_WIDTH-1); --*****ALIAS DECLARATION***** alias prev_sample : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) is sample_addr_latch_1; @@ -489,6 +459,17 @@ architecture arch of dds_writer is return ret; end function; + -- HACK: Due to delta cycle race condition some assertions trigger false positives, + -- so we check the signals on the falling edge + function stable(clk : std_logic; a : boolean) return boolean is + begin + if (clk = '0') then + return a; + else + return TRUE; + end if; + end function; + begin --*****COMPONENT INSTANTIATION***** @@ -619,7 +600,6 @@ begin -- ACKNACK_SAMPLE Acknowledge/Unacknowledge specied Sample -- GET_SAMPLE Push Sample Data to RTPS output -- GET_PAYLOAD Push linked Payload to output, or to the serialized key generator - -- GET_SERIALIZED_KEY Push serialized key to output -- CHECK_LIFESPAN Check and remove samples with expired Lifespans -- GET_LIVELINESS_LOST_STATUS Return Liveliness Loss Status -- GET_OFFERED_DEADLINE_MISSED_STATUS Return Offered Deadline Missed Status @@ -723,17 +703,13 @@ begin abort_kh <= '0'; idle_sig <= '0'; data_out_kh <= (others => '0'); - inst_addr_update <= (others => '0'); sample_addr <= (others => '0'); sample_write_data <= (others => '0'); payload_addr <= (others => '0'); payload_write_data <= (others => '0'); data_out_rtps <= (others => '0'); data_out_dds <= (others => '0'); - status_info_update <= (others => '0'); - inst_mem_fields <= (others => '0'); - sample_cnt <= (others => '0'); - ack_cnt <= (others => '0'); + inst_r <= ZERO_INSTANCE_DATA; @@ -1506,8 +1482,9 @@ begin -- Memory Operation Guard if (inst_op_done = '1') then inst_op_start <= '1'; - inst_opcode <= SEARCH_INSTANCE_HASH; - inst_mem_fields <= IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_ACK_CNT_FLAG; + inst_opcode <= SEARCH_INSTANCE; + inst_r.key_hash <= key_hash; + inst_r.field_flags <= IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_ACK_CNT_FLAG; -- Register Operation in Progress if (WITH_KEY and register_op = '1') then @@ -1525,16 +1502,14 @@ begin end if; end if; when REGISTER_OPERATION => - -- Precondition: inst_data set (IMF_STATUS_FLAG, IMF_SAMPLE_CNT_FLAG, IMF_ACK_CNT_FLAG) - -- Synthesis Guard if (WITH_KEY) then -- Wait for Instance Search to finish if (inst_op_done = '1') then - assert check_mask(current_imf, IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_ACK_CNT_FLAG) severity FAILURE; - -- Instance already in Memory - if (inst_addr_base /= INSTANCE_MEMORY_MAX_ADDRESS) then + if (inst_data.addr /= INSTANCE_MEMORY_MAX_ADDRESS) then + assert stable(clk, check_mask(inst_data.field_flags, IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_ACK_CNT_FLAG)) severity FAILURE; + -- Accept Registration stage_next <= PUSH_KEY_HASH; @@ -1543,9 +1518,10 @@ begin -- Re-register Instance inst_op_start <= '1'; inst_opcode <= UPDATE_INSTANCE; - inst_mem_fields <= IMF_STATUS_FLAG; - status_info_update <= inst_data.status_info; - status_info_update(ISI_UNREGISTERED_FLAG) <= '0'; + inst_r.addr <= inst_data.addr; + inst_r.field_flags <= IMF_STATUS_FLAG; + inst_r.status_info <= inst_data.status_info; + inst_r.status_info(ISI_UNREGISTERED_FLAG) <= '0'; -- Update Stale Instance Count if (inst_data.sample_cnt = inst_data.ack_cnt) then @@ -1557,12 +1533,14 @@ begin if (inst_empty_head = INSTANCE_MEMORY_MAX_ADDRESS) then -- Stale Instances are available if (stale_inst_cnt /= 0) then + -- Remove Stale and insert new Instance - inst_op_start <= '1'; - inst_opcode <= GET_FIRST_INSTANCE; - inst_mem_fields <= IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_ACK_CNT_FLAG; - stage_next <= REMOVE_STALE_INSTANCE; - cnt_next <= 0; + inst_op_start <= '1'; + inst_opcode <= GET_INSTANCE; + inst_r.addr <= inst_occupied_head; + inst_r.field_flags <= IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_ACK_CNT_FLAG; + stage_next <= REMOVE_STALE_INSTANCE; + cnt_next <= 0; else -- Reject Registration key_hash_next <= KEY_HASH_NIL; @@ -1573,11 +1551,9 @@ begin stage_next <= PUSH_KEY_HASH; -- Insert New Instance - inst_op_start <= '1'; - inst_opcode <= INSERT_INSTANCE; - status_info_update <= (others => '0'); - sample_cnt <= (others => '0'); - ack_cnt <= (others => '0'); + inst_op_start <= '1'; + inst_opcode <= INSERT_INSTANCE; + inst_r.key_hash <= key_hash; end if; end if; end if; @@ -1588,7 +1564,7 @@ begin -- Wait for Instance Search to finish if (inst_op_done = '1') then -- Instance Found - if (inst_addr_base /= INSTANCE_MEMORY_MAX_ADDRESS) then + if (inst_data.addr /= INSTANCE_MEMORY_MAX_ADDRESS) then stage_next <= PUSH_KEY_HASH; else -- Return Special Value @@ -1607,12 +1583,12 @@ begin -- Wait for Instance Search to finish if (not WITH_KEY or inst_op_done = '1') then - assert (not WITH_KEY or check_mask(current_imf, IMF_SAMPLE_CNT_FLAG or IMF_ACK_CNT_FLAG)) severity FAILURE; - -- Instance Found - if (not WITH_KEY or inst_addr_base /= INSTANCE_MEMORY_MAX_ADDRESS) then + if (not WITH_KEY or inst_data.addr /= INSTANCE_MEMORY_MAX_ADDRESS) then + assert (not WITH_KEY or stable(clk,check_mask(inst_data.field_flags, IMF_SAMPLE_CNT_FLAG or IMF_ACK_CNT_FLAG))) severity FAILURE; + -- Latch Instance Pointer - cur_inst_next <= inst_addr_base; + cur_inst_next <= inst_data.addr; -- RESOURCE_LIMITS_QOS (MAX_SAMPLES_PER_INSTANCE) if (WITH_KEY and MAX_SAMPLES_PER_INSTANCE /= LENGTH_UNLIMITED and inst_data.sample_cnt = unsigned(MAX_SAMPLES_PER_INSTANCE)) then @@ -1724,11 +1700,12 @@ begin return_code_dds <= RETCODE_OK; -- Remove Stale and insert new Instance - inst_op_start <= '1'; - inst_opcode <= GET_FIRST_INSTANCE; - inst_mem_fields <= IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_ACK_CNT_FLAG; - stage_next <= REMOVE_STALE_INSTANCE; - cnt_next <= 0; + inst_op_start <= '1'; + inst_opcode <= GET_INSTANCE; + inst_r.addr <= inst_occupied_head; + inst_r.field_flags <= IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_ACK_CNT_FLAG; + stage_next <= REMOVE_STALE_INSTANCE; + cnt_next <= 0; end if; else -- HISTORY_QOS = KEEP_LAST_HISTORY_QOS -- Accept Change (Remove Oldest (ACKed) Sample) @@ -1742,11 +1719,12 @@ begin return_code_dds <= RETCODE_OK; -- Remove Stale and insert new Instance - inst_op_start <= '1'; - inst_opcode <= GET_FIRST_INSTANCE; - inst_mem_fields <= IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_ACK_CNT_FLAG; - stage_next <= REMOVE_STALE_INSTANCE; - cnt_next <= 0; + inst_op_start <= '1'; + inst_opcode <= GET_INSTANCE; + inst_r.addr <= inst_occupied_head; + inst_r.field_flags <= IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_ACK_CNT_FLAG; + stage_next <= REMOVE_STALE_INSTANCE; + cnt_next <= 0; end if; else -- Accept Change @@ -1754,11 +1732,12 @@ begin return_code_dds <= RETCODE_OK; -- Remove Stale and insert new Instance - inst_op_start <= '1'; - inst_opcode <= GET_FIRST_INSTANCE; - inst_mem_fields <= IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_ACK_CNT_FLAG; - stage_next <= REMOVE_STALE_INSTANCE; - cnt_next <= 0; + inst_op_start <= '1'; + inst_opcode <= GET_INSTANCE; + inst_r.addr <= inst_occupied_head; + inst_r.field_flags <= IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_ACK_CNT_FLAG; + stage_next <= REMOVE_STALE_INSTANCE; + cnt_next <= 0; end if; else -- RESOURCE_LIMITS_QOS (MAX_SAMPLES) @@ -1781,9 +1760,10 @@ begin -- Insert New Instance inst_op_start <= '1'; inst_opcode <= INSERT_INSTANCE; - status_info_update <= (ISI_LIVELINESS_FLAG => '1', others => '0'); - sample_cnt <= to_unsigned(1, WORD_WIDTH); - ack_cnt <= (others => '0'); + inst_r.key_hash <= key_hash; + inst_r.status_info <= (ISI_LIVELINESS_FLAG => '1', others => '0'); + inst_r.sample_cnt <= to_unsigned(1, WORD_WIDTH); + inst_r.ack_cnt <= (others => '0'); stage_next <= FINALIZE_PAYLOAD; cnt_next <= 0; @@ -1802,9 +1782,10 @@ begin -- Insert New Instance inst_op_start <= '1'; inst_opcode <= INSERT_INSTANCE; - status_info_update <= (ISI_LIVELINESS_FLAG => '1', others => '0'); - sample_cnt <= to_unsigned(1, WORD_WIDTH); - ack_cnt <= (others => '0'); + inst_r.key_hash <= key_hash; + inst_r.status_info <= (ISI_LIVELINESS_FLAG => '1', others => '0'); + inst_r.sample_cnt <= to_unsigned(1, WORD_WIDTH); + inst_r.ack_cnt <= (others => '0'); stage_next <= FINALIZE_PAYLOAD; cnt_next <= 0; @@ -1817,9 +1798,10 @@ begin -- Insert New Instance inst_op_start <= '1'; inst_opcode <= INSERT_INSTANCE; - status_info_update <= (ISI_LIVELINESS_FLAG => '1', others => '0'); - sample_cnt <= to_unsigned(1, WORD_WIDTH); - ack_cnt <= (others => '0'); + inst_r.key_hash <= key_hash; + inst_r.status_info <= (ISI_LIVELINESS_FLAG => '1', others => '0'); + inst_r.sample_cnt <= to_unsigned(1, WORD_WIDTH); + inst_r.ack_cnt <= (others => '0'); stage_next <= FINALIZE_PAYLOAD; cnt_next <= 0; @@ -1832,24 +1814,26 @@ begin -- Memory Operation Guard if (not WITH_KEY or inst_op_done = '1') then - assert (not WITH_KEY or check_mask(current_imf, IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_ACK_CNT_FLAG)) severity FAILURE; - -- Synthesis Guard if (WITH_KEY) then + assert (inst_data.addr /= INSTANCE_MEMORY_MAX_ADDRESS) severity FAILURE; + assert stable(clk,check_mask(inst_data.field_flags, IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_ACK_CNT_FLAG)) severity FAILURE; + inst_op_start <= '1'; inst_opcode <= UPDATE_INSTANCE; - inst_mem_fields <= IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG; - status_info_update <= inst_data.status_info; - status_info_update(ISI_LIVELINESS_FLAG) <= '1'; + inst_r.addr <= inst_data.addr; + inst_r.field_flags <= IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG; + inst_r.status_info <= inst_data.status_info; + inst_r.status_info(ISI_LIVELINESS_FLAG) <= '1'; if (sample_status_info(SSI_DISPOSED_FLAG) = '0' and sample_status_info(SSI_UNREGISTERED_FLAG) = '0') then - status_info_update(ISI_DISPOSED_FLAG) <= '0'; - status_info_update(ISI_UNREGISTERED_FLAG) <= '0'; + inst_r.status_info(ISI_DISPOSED_FLAG) <= '0'; + inst_r.status_info(ISI_UNREGISTERED_FLAG) <= '0'; elsif (sample_status_info(SSI_DISPOSED_FLAG) = '1') then - status_info_update(ISI_DISPOSED_FLAG) <= '1'; + inst_r.status_info(ISI_DISPOSED_FLAG) <= '1'; elsif (sample_status_info(SSI_UNREGISTERED_FLAG) = '1') then - status_info_update(ISI_UNREGISTERED_FLAG) <= '1'; + inst_r.status_info(ISI_UNREGISTERED_FLAG) <= '1'; end if; - sample_cnt <= inst_data.sample_cnt + 1; + inst_r.sample_cnt <= inst_data.sample_cnt + 1; -- Update Stale Instance Count -- NOTE: We enter this state only when we have a new sample, so an instance cannot turn stale, but only @@ -2071,8 +2055,8 @@ begin if (sample_valid_out = '1') then inst_op_start <= '1'; inst_opcode <= GET_INSTANCE; - inst_mem_fields <= IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_ACK_CNT_FLAG; - inst_addr_update <= resize(unsigned(sample_read_data), INSTANCE_MEMORY_ADDR_WIDTH); + inst_r.addr <= resize(unsigned(sample_read_data), INSTANCE_MEMORY_ADDR_WIDTH); + inst_r.field_flags <= IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_ACK_CNT_FLAG; cur_sample_next <= oldest_sample; stage_next <= REMOVE_SAMPLE; @@ -2180,8 +2164,8 @@ begin if (remove_oldest_sample = '1') then inst_op_start <= '1'; inst_opcode <= GET_INSTANCE; - inst_mem_fields <= IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_ACK_CNT_FLAG; - inst_addr_update <= resize(unsigned(sample_read_data), INSTANCE_MEMORY_ADDR_WIDTH); + inst_r.addr <= resize(unsigned(sample_read_data), INSTANCE_MEMORY_ADDR_WIDTH); + inst_r.field_flags <= IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_ACK_CNT_FLAG; stage_next <= REMOVE_SAMPLE; cnt_next <= 0; @@ -2534,18 +2518,20 @@ begin -- Memory Operation Guard if (not WITH_KEY or inst_op_done = '1') then - assert (not WITH_KEY or check_mask(current_imf, IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_ACK_CNT_FLAG)) severity FAILURE; - -- Synthesis Guard if (WITH_KEY) then - inst_op_start <= '1'; - inst_opcode <= UPDATE_INSTANCE; - inst_mem_fields <= IMF_SAMPLE_CNT_FLAG; - sample_cnt <= inst_data.sample_cnt - 1; + assert (inst_data.addr /= INSTANCE_MEMORY_MAX_ADDRESS) severity FAILURE; + assert stable(clk, check_mask(inst_data.field_flags, IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_ACK_CNT_FLAG)) severity FAILURE; + + inst_op_start <= '1'; + inst_opcode <= UPDATE_INSTANCE; + inst_r.addr <= inst_data.addr; + inst_r.field_flags <= IMF_SAMPLE_CNT_FLAG; + inst_r.sample_cnt <= inst_data.sample_cnt - 1; -- Sample was ACKed if (sample_status_info(SSI_ACK_FLAG) = '1') then - inst_mem_fields <= IMF_SAMPLE_CNT_FLAG or IMF_ACK_CNT_FLAG; - ack_cnt <= inst_data.ack_cnt - 1; + inst_r.field_flags <= IMF_SAMPLE_CNT_FLAG or IMF_ACK_CNT_FLAG; + inst_r.ack_cnt <= inst_data.ack_cnt - 1; else -- Update Stale Instance Count -- Instance is Unregistered and last NACKed sample is removed @@ -2609,8 +2595,6 @@ begin cnt_next <= 0; end if; when REMOVE_STALE_INSTANCE => - -- Precondition: inst_data set (IMF_STATUS_FLAG, IMF_SAMPLE_CNT_FLAG, IMF_ACK_CNT_FLAG) - -- Synthesis Guard if (WITH_KEY) then -- Wait for Instance Data @@ -2618,19 +2602,20 @@ begin case (cnt) is -- Find and Remove First Stale Instance when 0 => - assert check_mask(current_imf, IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_ACK_CNT_FLAG) severity FAILURE; - -- Iterated through all Instances - if (inst_addr_base = INSTANCE_MEMORY_MAX_ADDRESS) then + if (inst_data.addr = INSTANCE_MEMORY_MAX_ADDRESS) then -- NOTE: We should enter this state only if there is at least one stale Instance to be removed, so we should never enter this branch. - assert FALSE severity FAILURE; + assert stable(clk,FALSE) severity FAILURE; stage_next <= IDLE; else + assert stable(clk,check_mask(inst_data.field_flags, IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_ACK_CNT_FLAG)) severity FAILURE; + -- Found Stale Instance (Unregistered and all Samples ACKed) if (inst_data.status_info(ISI_UNREGISTERED_FLAG) = '1' and inst_data.sample_cnt = inst_data.ack_cnt) then -- Remove Stale Instance inst_op_start <= '1'; inst_opcode <= REMOVE_INSTANCE; + inst_r.addr <= inst_data.addr; -- Update Stale Instance Count stale_inst_cnt_next <= stale_inst_cnt - 1; @@ -2641,28 +2626,30 @@ begin -- finalized. So we postpone the Sample removal until after the finalization of the -- current sample. orphan_samples_next <= '1'; - dead_inst_next <= inst_addr_base; + dead_inst_next <= inst_data.addr; end if; cnt_next <= cnt + 1; else -- Continue Search - inst_op_start <= '1'; - inst_opcode <= GET_NEXT_INSTANCE; - inst_mem_fields <= IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_ACK_CNT_FLAG; + inst_op_start <= '1'; + inst_opcode <= GET_NEXT_INSTANCE; + inst_r.addr <= inst_data.addr; + inst_r.field_flags <= IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_ACK_CNT_FLAG; end if; end if; -- Insert New Instance when 1 => - inst_op_start <= '1'; - inst_opcode <= INSERT_INSTANCE; - ack_cnt <= (others => '0'); + inst_op_start <= '1'; + inst_opcode <= INSERT_INSTANCE; + inst_r.key_hash <= key_hash; + inst_r.ack_cnt <= (others => '0'); if (register_op = '1') then - status_info_update <= (others => '0'); - sample_cnt <= (others => '0'); + inst_r.status_info <= (others => '0'); + inst_r.sample_cnt <= (others => '0'); else - status_info_update <= (ISI_LIVELINESS_FLAG => '1', others => '0'); - sample_cnt <= to_unsigned(1, WORD_WIDTH); + inst_r.status_info <= (ISI_LIVELINESS_FLAG => '1', others => '0'); + inst_r.sample_cnt <= to_unsigned(1, WORD_WIDTH); end if; -- Latch Instance Pointer @@ -2869,8 +2856,8 @@ begin -- Fetch Instance Data inst_op_start <= '1'; inst_opcode <= GET_INSTANCE; - inst_mem_fields <= IMF_KEY_HASH_FLAG or IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_ACK_CNT_FLAG; - inst_addr_update <= cur_inst; + inst_r.addr <= cur_inst; + inst_r.field_flags <= IMF_KEY_HASH_FLAG or IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_ACK_CNT_FLAG; stage_next <= return_stage; cnt_next <= 0; @@ -2937,17 +2924,18 @@ begin if (WITH_KEY) then -- Wait for Instance Data if (inst_op_done = '1') then - assert check_mask(current_imf, IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_ACK_CNT_FLAG) severity FAILURE; + assert (inst_data.addr /= INSTANCE_MEMORY_MAX_ADDRESS) severity FAILURE; + assert stable(clk, check_mask(inst_data.field_flags, IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_ACK_CNT_FLAG)) severity FAILURE; -- Update inst_op_start <= '1'; inst_opcode <= UPDATE_INSTANCE; - inst_mem_fields <= IMF_ACK_CNT_FLAG; - inst_addr_update <= cur_inst; + inst_r.addr <= cur_inst; + inst_r.field_flags <= IMF_ACK_CNT_FLAG; if (is_ack = '1') then - ack_cnt <= inst_data.ack_cnt + 1; + inst_r.ack_cnt <= inst_data.ack_cnt + 1; else - ack_cnt <= inst_data.ack_cnt - 1; + inst_r.ack_cnt <= inst_data.ack_cnt - 1; end if; -- Update Stale Instance Count @@ -3078,7 +3066,8 @@ begin if (WITH_KEY) then -- Wait for Instance Data if (inst_op_done = '1') then - assert check_mask(current_imf, IMF_KEY_HASH_FLAG) severity FAILURE; + assert (inst_data.addr /= INSTANCE_MEMORY_MAX_ADDRESS) severity FAILURE; + assert stable(clk, check_mask(inst_data.field_flags, IMF_KEY_HASH_FLAG)) severity FAILURE; cc_instance_handle_sig_next <= inst_data.key_hash; @@ -3350,8 +3339,8 @@ begin -- Fetch Instance Data inst_op_start <= '1'; inst_opcode <= GET_INSTANCE; - inst_mem_fields <= IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_ACK_CNT_FLAG; - inst_addr_update <= resize(unsigned(sample_read_data),INSTANCE_MEMORY_ADDR_WIDTH); + inst_r.addr <= resize(unsigned(sample_read_data),INSTANCE_MEMORY_ADDR_WIDTH); + inst_r.field_flags <= IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_ACK_CNT_FLAG; -- Remove Sample stage_next <= REMOVE_SAMPLE; @@ -3466,32 +3455,35 @@ begin -- Get First Instance when 0 => inst_op_start <= '1'; - inst_opcode <= GET_FIRST_INSTANCE; - inst_mem_fields <= IMF_KEY_HASH_FLAG or IMF_STATUS_FLAG; - cnt_next <= 2; + inst_opcode <= GET_INSTANCE; + inst_r.addr <= inst_occupied_head; + inst_r.field_flags <= IMF_KEY_HASH_FLAG or IMF_STATUS_FLAG; + cnt_next <= 2; -- Get Next Instance when 1 => inst_op_start <= '1'; inst_opcode <= GET_NEXT_INSTANCE; - inst_mem_fields <= IMF_KEY_HASH_FLAG or IMF_STATUS_FLAG; - cnt_next <= 2; + inst_r.addr <= inst_data.addr; + inst_r.field_flags <= IMF_KEY_HASH_FLAG or IMF_STATUS_FLAG; + cnt_next <= 2; -- Check Instance when 2 => - assert check_mask(current_imf, IMF_STATUS_FLAG or IMF_KEY_HASH_FLAG) severity FAILURE; - -- Reached End of Instances - if (inst_addr_base = INSTANCE_MEMORY_MAX_ADDRESS) then + if (inst_data.addr = INSTANCE_MEMORY_MAX_ADDRESS) then -- DONE stage_next <= IDLE; else + assert stable(clk, check_mask(inst_data.field_flags, IMF_STATUS_FLAG or IMF_KEY_HASH_FLAG)) severity FAILURE; + -- Instance received Sample if (inst_data.status_info(ISI_LIVELINESS_FLAG) = '1') then -- Reset Liveliness Flag inst_op_start <= '1'; inst_opcode <= UPDATE_INSTANCE; - inst_mem_fields <= IMF_STATUS_FLAG; - status_info_update <= inst_data.status_info; - status_info_update(ISI_LIVELINESS_FLAG) <= '0'; + inst_r.addr <= inst_data.addr; + inst_r.field_flags <= IMF_STATUS_FLAG; + inst_r.status_info <= inst_data.status_info; + inst_r.status_info(ISI_LIVELINESS_FLAG) <= '0'; cnt_next <= 1; else -- Update Requested Deadline Missed Status @@ -3581,8 +3573,6 @@ begin when others => null; end case; - when others => - null; end case; end process; @@ -3591,8 +3581,7 @@ begin -- *Instance Memory Process* -- STATE DESCRIPTION -- IDLE Idle State. Done Signal is pulled high and Memory FSM accepts new memory operations - -- SEARCH_INSTANCE_HASH See Memory OPCODE Description - -- SEARCH_INSTANCE_ADDR See Memory OPCODE Description + -- SEARCH_INSTANCE See Memory OPCODE Description -- GET_NEXT_INSTANCE See Memory OPCODE Description -- GET_INSTANCE_DATA Latch specified Instance Data for use by main process -- INSERT_INSTANCE See Memory OPCODE Description @@ -3604,15 +3593,13 @@ begin -- DEFAULT Registered inst_stage_next <= inst_stage; inst_addr_base_next <= inst_addr_base; + inst_addr_latch_next <= inst_addr_latch; inst_empty_head_next <= inst_empty_head; inst_occupied_head_next <= inst_occupied_head; inst_latch_data_next <= inst_latch_data; - inst_next_addr_base_next <= inst_next_addr_base; - inst_prev_addr_base_next <= inst_prev_addr_base; inst_cnt_next <= inst_cnt; inst_data_next <= inst_data; inst_long_latch_next <= inst_long_latch; - current_imf_next <= current_imf; -- DEFAULT Unregistered inst_ready_out <= '0'; inst_valid_in <= '0'; @@ -3628,155 +3615,100 @@ begin inst_op_done <= '1'; if (inst_op_start = '1') then - -- Latch Signals needed for Mermory Operation (Use _next signals, because some signals are set in same clk) - inst_latch_data_next <= ( - key_hash => key_hash_next, - status_info => status_info_update, - sample_cnt => sample_cnt, - ack_cnt => ack_cnt, - field_flags => inst_mem_fields, - addr => inst_addr_update - ); + inst_latch_data_next <= inst_r; case(inst_opcode) is - when SEARCH_INSTANCE_HASH => + when SEARCH_INSTANCE => -- Reset Data - current_imf_next <= inst_mem_fields; - inst_data_next <= ZERO_INSTANCE_DATA; + inst_data_next <= ZERO_INSTANCE_DATA; -- No Instances available - if (inst_occupied_head = INSTANCE_MEMORY_MAX_ADDRESS) then - inst_addr_base_next <= INSTANCE_MEMORY_MAX_ADDRESS; - else - inst_prev_addr_base_next <= INSTANCE_MEMORY_MAX_ADDRESS; - inst_addr_base_next <= inst_occupied_head; - inst_stage_next <= SEARCH_INSTANCE_HASH; - inst_cnt_next <= 0; - end if; - when SEARCH_INSTANCE_ADDR => - -- Reset Data - current_imf_next <= inst_mem_fields; - inst_data_next <= ZERO_INSTANCE_DATA; - - -- No Instances avialable - if (inst_occupied_head = INSTANCE_MEMORY_MAX_ADDRESS) then - inst_addr_base_next <= INSTANCE_MEMORY_MAX_ADDRESS; - else - inst_prev_addr_base_next <= INSTANCE_MEMORY_MAX_ADDRESS; - inst_addr_base_next <= inst_occupied_head; - inst_stage_next <= SEARCH_INSTANCE_ADDR; - inst_cnt_next <= 0; + if (inst_occupied_head /= INSTANCE_MEMORY_MAX_ADDRESS) then + inst_addr_base_next <= inst_occupied_head; + inst_stage_next <= SEARCH_INSTANCE; + inst_cnt_next <= 0; end if; when INSERT_INSTANCE => - -- NOTE: Since this process has no way to communicate a failed insert to the main process, it has to be made sure - -- by the main process that the operation can succeed (Memory is available) - assert (inst_empty_head /= INSTANCE_MEMORY_MAX_ADDRESS) report "Instance Insertion while memory Full" severity FAILURE; + assert (inst_empty_head /= INSTANCE_MEMORY_MAX_ADDRESS) severity FAILURE; - -- Reset Data - current_imf_next <= (others => '1'); - inst_data_next <= ZERO_INSTANCE_DATA; + inst_data_next <= ZERO_INSTANCE_DATA; - inst_addr_base_next <= inst_empty_head; - inst_stage_next <= INSERT_INSTANCE; - inst_cnt_next <= 0; - - -- SET Instance Data - inst_data_next.key_hash <= key_hash_next; - inst_data_next.status_info <= status_info_update; - inst_data_next.sample_cnt <= sample_cnt; - inst_data_next.ack_cnt <= ack_cnt; + inst_data_next.addr <= inst_empty_head; + inst_addr_base_next <= inst_empty_head; + inst_stage_next <= INSERT_INSTANCE; + inst_cnt_next <= 0; when UPDATE_INSTANCE => - current_imf_next <= current_imf or inst_mem_fields; - inst_stage_next <= UPDATE_INSTANCE; - - if check_mask(inst_mem_fields,IMF_STATUS_FLAG) then - inst_cnt_next <= 0; - elsif check_mask(inst_mem_fields,IMF_SAMPLE_CNT_FLAG) then - inst_cnt_next <= 1; - elsif check_mask(inst_mem_fields,IMF_ACK_CNT_FLAG) then - inst_cnt_next <= 2; + if (inst_r.addr = INSTANCE_MEMORY_MAX_ADDRESS) then + inst_data_next <= ZERO_INSTANCE_DATA; else - -- DONE - inst_stage_next <= IDLE; - end if; - when GET_FIRST_INSTANCE => - -- Reset - current_imf_next <= inst_mem_fields; - inst_data_next <= ZERO_INSTANCE_DATA; - - -- No Instances avialable - if (inst_occupied_head = INSTANCE_MEMORY_MAX_ADDRESS) then - inst_addr_base_next <= INSTANCE_MEMORY_MAX_ADDRESS; - else - inst_prev_addr_base_next <= INSTANCE_MEMORY_MAX_ADDRESS; - inst_addr_base_next <= inst_occupied_head; - inst_stage_next <= GET_NEXT_INSTANCE; - inst_cnt_next <= 0; - end if; - when GET_NEXT_INSTANCE => - -- Reset - current_imf_next <= inst_mem_fields; - inst_data_next <= ZERO_INSTANCE_DATA; - - -- No Instances avialable - if (inst_next_addr_base = INSTANCE_MEMORY_MAX_ADDRESS) then - inst_addr_base_next <= INSTANCE_MEMORY_MAX_ADDRESS; - else - inst_prev_addr_base_next <= inst_addr_base; - inst_addr_base_next <= inst_next_addr_base; - inst_stage_next <= GET_NEXT_INSTANCE; - inst_cnt_next <= 0; + if (inst_r.addr /= inst_data.addr) then + inst_data_next <= ZERO_INSTANCE_DATA; + end if; + + inst_data_next.addr <= inst_r.addr; + inst_addr_base_next <= inst_r.addr; + inst_stage_next <= UPDATE_INSTANCE; + if check_mask(inst_r.field_flags,IMF_STATUS_FLAG) then + inst_cnt_next <= 0; + elsif check_mask(inst_r.field_flags,IMF_SAMPLE_CNT_FLAG) then + inst_cnt_next <= 1; + elsif check_mask(inst_r.field_flags,IMF_ACK_CNT_FLAG) then + inst_cnt_next <= 2; + else + -- DONE + inst_stage_next <= IDLE; + end if; end if; when REMOVE_INSTANCE => - -- Reset - current_imf_next <= (others => '0'); - inst_data_next <= ZERO_INSTANCE_DATA; + inst_data_next <= ZERO_INSTANCE_DATA; - inst_stage_next <= REMOVE_INSTANCE; - inst_cnt_next <= 0; - when GET_INSTANCE => - inst_addr_base_next <= inst_addr_update; - if (inst_addr_base /= inst_addr_update) then - -- Reset - current_imf_next <= inst_mem_fields; - inst_data_next <= ZERO_INSTANCE_DATA; - else - current_imf_next <= current_imf or inst_mem_fields; + if (inst_r.addr /= INSTANCE_MEMORY_MAX_ADDRESS) then + inst_addr_base_next <= inst_r.addr; + inst_stage_next <= REMOVE_INSTANCE; + inst_cnt_next <= 0; end if; + when GET_NEXT_INSTANCE => + inst_data_next <= ZERO_INSTANCE_DATA; - -- Get Instance Data - inst_stage_next <= GET_INSTANCE_DATA; - if check_mask(inst_mem_fields,IMF_KEY_HASH_FLAG) then - inst_cnt_next <= 0; - elsif check_mask(inst_mem_fields,IMF_STATUS_FLAG) then - inst_cnt_next <= 4; - elsif check_mask(inst_mem_fields,IMF_SAMPLE_CNT_FLAG) then - inst_cnt_next <= 5; - elsif check_mask(inst_mem_fields,IMF_ACK_CNT_FLAG) then - inst_cnt_next <= 6; + -- No Instances available + if (inst_r.addr /= INSTANCE_MEMORY_MAX_ADDRESS) then + inst_addr_base_next <= inst_r.addr; + inst_stage_next <= GET_NEXT_INSTANCE; + inst_cnt_next <= 0; + end if; + when GET_INSTANCE => + if (inst_r.addr = INSTANCE_MEMORY_MAX_ADDRESS) then + inst_data_next <= ZERO_INSTANCE_DATA; else - -- DONE - inst_stage_next <= IDLE; + if (inst_r.addr /= inst_data.addr) then + inst_data_next <= ZERO_INSTANCE_DATA; + end if; + + inst_data_next.addr <= inst_r.addr; + inst_addr_base_next <= inst_r.addr; + inst_stage_next <= GET_INSTANCE_DATA; + if check_mask(inst_r.field_flags,IMF_KEY_HASH_FLAG) then + inst_cnt_next <= 0; + elsif check_mask(inst_r.field_flags,IMF_STATUS_FLAG) then + inst_cnt_next <= 4; + elsif check_mask(inst_r.field_flags,IMF_SAMPLE_CNT_FLAG) then + inst_cnt_next <= 5; + elsif check_mask(inst_r.field_flags,IMF_ACK_CNT_FLAG) then + inst_cnt_next <= 6; + else + -- DONE + inst_stage_next <= IDLE; + end if; end if; when others => null; end case; end if; - when SEARCH_INSTANCE_HASH => + when SEARCH_INSTANCE => case (inst_cnt) is - -- GET Next Instance - when 0 => - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_NEXT_ADDR_OFFSET; - inst_read <= '1'; - - -- Memory Flow Control Guard - if (inst_ready_in = '1') then - inst_cnt_next <= inst_cnt + 1; - end if; -- GET Key Hash 1/4 - when 1 => + when 0 => inst_valid_in <= '1'; inst_addr <= inst_addr_base + IMF_KEY_HASH_OFFSET; inst_read <= '1'; @@ -3786,7 +3718,7 @@ begin inst_cnt_next <= inst_cnt + 1; end if; -- GET Key Hash 2/4 - when 2 => + when 1 => inst_valid_in <= '1'; inst_addr <= inst_addr_base + IMF_KEY_HASH_OFFSET + 1; inst_read <= '1'; @@ -3796,7 +3728,7 @@ begin inst_cnt_next <= inst_cnt + 1; end if; -- GET Key Hash 3/4 - when 3 => + when 2 => inst_valid_in <= '1'; inst_addr <= inst_addr_base + IMF_KEY_HASH_OFFSET + 2; inst_read <= '1'; @@ -3806,7 +3738,7 @@ begin inst_cnt_next <= inst_cnt + 1; end if; -- GET Key Hash 4/4 - when 4 => + when 3 => inst_valid_in <= '1'; inst_addr <= inst_addr_base + IMF_KEY_HASH_OFFSET + 3; inst_read <= '1'; @@ -3815,17 +3747,8 @@ begin if (inst_ready_in = '1') then inst_cnt_next <= inst_cnt + 1; end if; - -- READ Next Instance - when 5 => - inst_ready_out <= '1'; - - -- Memory Flow Control Guard - if (inst_valid_out = '1') then - inst_next_addr_base_next <= resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH); - inst_cnt_next <= inst_cnt + 1; - end if; -- READ Key Hash 1/4 - when 6 => + when 4 => inst_ready_out <= '1'; -- Memory Flow Control Guard @@ -3833,23 +3756,13 @@ begin -- No Match if (inst_read_data /= inst_latch_data.key_hash(0)) then inst_abort_read <= '1'; - -- Reached List Tail, No Match - if (inst_next_addr_base = INSTANCE_MEMORY_MAX_ADDRESS) then - inst_addr_base_next <= INSTANCE_MEMORY_MAX_ADDRESS; --No match - -- DONE - inst_stage_next <= IDLE; - else - -- Continue Search - inst_prev_addr_base_next <= inst_addr_base; - inst_addr_base_next <= inst_next_addr_base; - inst_cnt_next <= 0; - end if; + inst_cnt_next <= 8; -- GET NEXT INSTANCE else inst_cnt_next <= inst_cnt + 1; end if; end if; -- READ Key Hash 2/4 - when 7 => + when 5 => inst_ready_out <= '1'; -- Memory Flow Control Guard @@ -3857,23 +3770,13 @@ begin -- No Match if (inst_read_data /= inst_latch_data.key_hash(1)) then inst_abort_read <= '1'; - -- Reached List Tail, No Match - if (inst_next_addr_base = INSTANCE_MEMORY_MAX_ADDRESS) then - inst_addr_base_next <= INSTANCE_MEMORY_MAX_ADDRESS; --No match - -- DONE - inst_stage_next <= IDLE; - else - -- Continue Search - inst_prev_addr_base_next <= inst_addr_base; - inst_addr_base_next <= inst_next_addr_base; - inst_cnt_next <= 0; - end if; + inst_cnt_next <= 8; -- GET NEXT INSTANCE else inst_cnt_next <= inst_cnt + 1; end if; end if; -- READ Key Hash 3/4 - when 8 => + when 6 => inst_ready_out <= '1'; -- Memory Flow Control Guard @@ -3881,43 +3784,23 @@ begin -- No Match if (inst_read_data /= inst_latch_data.key_hash(2)) then inst_abort_read <= '1'; - -- Reached List Tail, No Match - if (inst_next_addr_base = INSTANCE_MEMORY_MAX_ADDRESS) then - inst_addr_base_next <= INSTANCE_MEMORY_MAX_ADDRESS; --No match - -- DONE - inst_stage_next <= IDLE; - else - -- Continue Search - inst_prev_addr_base_next <= inst_addr_base; - inst_addr_base_next <= inst_next_addr_base; - inst_cnt_next <= 0; - end if; + inst_cnt_next <= 8; -- GET NEXT INSTANCE else inst_cnt_next <= inst_cnt + 1; end if; end if; -- READ Key Hash 4/4 - when 9 => + when 7 => inst_ready_out <= '1'; -- Memory Flow Control Guard if (inst_valid_out = '1') then -- No Match if (inst_read_data /= inst_latch_data.key_hash(3)) then - -- Reached List Tail, No Match - if (inst_next_addr_base = INSTANCE_MEMORY_MAX_ADDRESS) then - inst_addr_base_next <= INSTANCE_MEMORY_MAX_ADDRESS; --No match - -- DONE - inst_stage_next <= IDLE; - else - -- Continue Search - inst_prev_addr_base_next <= inst_addr_base; - inst_addr_base_next <= inst_next_addr_base; - inst_cnt_next <= 0; - end if; + inst_cnt_next <= 8; -- GET NEXT INSTANCE else + inst_data_next.addr <= inst_addr_base; -- Get Instance Data - inst_data_next <= ZERO_INSTANCE_DATA; inst_stage_next <= GET_INSTANCE_DATA; if check_mask(inst_latch_data.field_flags,IMF_KEY_HASH_FLAG) then inst_cnt_next <= 0; @@ -3933,11 +3816,37 @@ begin end if; end if; end if; + -- GET Next Instance + when 8 => + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_NEXT_ADDR_OFFSET; + inst_read <= '1'; + + -- Memory Flow Control Guard + if (inst_ready_in = '1') then + inst_cnt_next <= inst_cnt + 1; + end if; + -- READ Next Instance + when 9 => + inst_ready_out <= '1'; + + -- Memory Flow Control Guard + if (inst_valid_out = '1') then + -- No more Endpoints + if (resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH) = INSTANCE_MEMORY_MAX_ADDRESS) then + inst_data_next.addr <= INSTANCE_MEMORY_MAX_ADDRESS; --No match + -- DONE + inst_stage_next <= IDLE; + else + -- Continue + inst_addr_base_next <= resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH); + inst_cnt_next <= 0; + end if; + end if; when others => null; end case; - when SEARCH_INSTANCE_ADDR => - + when GET_NEXT_INSTANCE => case (inst_cnt) is -- GET Next Instance when 0 => @@ -3955,14 +3864,16 @@ begin -- Memory Flow Control Guard if (inst_valid_out = '1') then - inst_prev_addr_base_next <= inst_addr_base; - inst_addr_base_next <= resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH); - - -- Match - if (resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH) = inst_latch_data.addr) then + if (resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH) = INSTANCE_MEMORY_MAX_ADDRESS) then + inst_data_next.addr <= INSTANCE_MEMORY_MAX_ADDRESS; + -- DONE + inst_stage_next <= IDLE; + else + inst_data_next.addr <= resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH); + -- Get Instance Data + inst_addr_base_next <= resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH); inst_stage_next <= GET_INSTANCE_DATA; - inst_data_next <= ZERO_INSTANCE_DATA; if check_mask(inst_latch_data.field_flags,IMF_KEY_HASH_FLAG) then inst_cnt_next <= 0; elsif check_mask(inst_latch_data.field_flags,IMF_STATUS_FLAG) then @@ -3975,55 +3886,6 @@ begin -- DONE inst_stage_next <= IDLE; end if; - -- No Match - else - -- Reached List Tail, No Match - if (resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH) = INSTANCE_MEMORY_MAX_ADDRESS) then - inst_addr_base_next <= INSTANCE_MEMORY_MAX_ADDRESS; --No match - -- DONE - inst_stage_next <= IDLE; - else - -- Continue Search - inst_cnt_next <= 0; - end if; - end if; - end if; - when others => - null; - end case; - when GET_NEXT_INSTANCE => - case (inst_cnt) is - -- GET next Instance - when 0 => - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_NEXT_ADDR_OFFSET; - inst_read <= '1'; - - -- Memory Flow Control Guard - if (inst_ready_in = '1') then - inst_cnt_next <= inst_cnt + 1; - end if; - -- READ Next Instance - when 1 => - inst_ready_out <= '1'; - - -- Memory Flow Control Guard - if (inst_valid_out = '1') then - inst_next_addr_base_next <= resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH); - -- Get Instance Data - inst_data_next <= ZERO_INSTANCE_DATA; - inst_stage_next <= GET_INSTANCE_DATA; - if check_mask(inst_latch_data.field_flags,IMF_KEY_HASH_FLAG) then - inst_cnt_next <= 0; - elsif check_mask(inst_latch_data.field_flags,IMF_STATUS_FLAG) then - inst_cnt_next <= 4; - elsif check_mask(inst_latch_data.field_flags,IMF_SAMPLE_CNT_FLAG) then - inst_cnt_next <= 5; - elsif check_mask(inst_latch_data.field_flags,IMF_ACK_CNT_FLAG) then - inst_cnt_next <= 6; - else - -- DONE - inst_stage_next <= IDLE; end if; end if; when others => @@ -4171,6 +4033,7 @@ begin -- Memory Flow Control Guard if (inst_valid_out = '1') then inst_data_next.key_hash(3) <= inst_read_data; + inst_data_next.field_flags <= inst_data.field_flags or IMF_KEY_HASH_FLAG; if check_mask(inst_latch_data.field_flags,IMF_STATUS_FLAG) then inst_cnt_next <= 11; @@ -4190,6 +4053,7 @@ begin -- Memory Flow Control Guard if (inst_valid_out = '1') then inst_data_next.status_info <= inst_read_data; + inst_data_next.field_flags <= inst_data.field_flags or IMF_STATUS_FLAG; if check_mask(inst_latch_data.field_flags,IMF_SAMPLE_CNT_FLAG) then inst_cnt_next <= 12; @@ -4207,6 +4071,7 @@ begin -- Memory Flow Control Guard if (inst_valid_out = '1') then inst_data_next.sample_cnt <= unsigned(inst_read_data); + inst_data_next.field_flags <= inst_data.field_flags or IMF_SAMPLE_CNT_FLAG; if check_mask(inst_latch_data.field_flags,IMF_ACK_CNT_FLAG) then inst_cnt_next <= 13; @@ -4222,16 +4087,15 @@ begin -- Memory Flow Control Guard if (inst_valid_out = '1') then inst_data_next.ack_cnt <= unsigned(inst_read_data); + inst_data_next.field_flags <= inst_data.field_flags or IMF_ACK_CNT_FLAG; -- DONE inst_stage_next <= IDLE; end if; end case; when INSERT_INSTANCE => - -- Precondition: inst_addr_base set - case (inst_cnt) is - -- GET Next Instance Pointer + -- GET Next Instance when 0 => inst_valid_in <= '1'; inst_addr <= inst_addr_base + IMF_NEXT_ADDR_OFFSET; @@ -4239,34 +4103,10 @@ begin -- Memory Flow Control Guard if (inst_ready_in = '1') then - inst_cnt_next <= inst_cnt + 1; - end if; - -- SET Next Instance Pointer - when 1 => - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_NEXT_ADDR_OFFSET; - inst_write_data <= std_logic_vector(resize(inst_occupied_head,WORD_WIDTH)); - - -- Memory Flow Control Guard - if (inst_ready_in = '1') then - -- Fix Occupied List Head - inst_occupied_head_next <= inst_addr_base; - - inst_cnt_next <= inst_cnt + 1; - end if; - -- READ Next Instance Pointer - when 2 => - inst_ready_out <= '1'; - - -- Memory Flow Control Guard - if (inst_valid_out = '1') then - -- Fix Empty List Head - inst_empty_head_next <= resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH); - inst_cnt_next <= inst_cnt + 1; end if; -- SET Key Hash 1/4 - when 3 => + when 1 => inst_valid_in <= '1'; inst_addr <= inst_addr_base + IMF_KEY_HASH_OFFSET; inst_write_data <= inst_latch_data.key_hash(0); @@ -4276,7 +4116,7 @@ begin inst_cnt_next <= inst_cnt + 1; end if; -- SET Key Hash 2/4 - when 4 => + when 2 => inst_valid_in <= '1'; inst_addr <= inst_addr_base + IMF_KEY_HASH_OFFSET + 1; inst_write_data <= inst_latch_data.key_hash(1); @@ -4286,7 +4126,7 @@ begin inst_cnt_next <= inst_cnt + 1; end if; -- SET Key Hash 3/4 - when 5 => + when 3 => inst_valid_in <= '1'; inst_addr <= inst_addr_base + IMF_KEY_HASH_OFFSET + 2; inst_write_data <= inst_latch_data.key_hash(2); @@ -4296,45 +4136,95 @@ begin inst_cnt_next <= inst_cnt + 1; end if; -- SET Key Hash 4/4 - when 6 => + when 4 => inst_valid_in <= '1'; inst_addr <= inst_addr_base + IMF_KEY_HASH_OFFSET + 3; inst_write_data <= inst_latch_data.key_hash(3); + inst_data_next.field_flags <= inst_data.field_flags or IMF_KEY_HASH_FLAG; -- Memory Flow Control Guard if (inst_ready_in = '1') then inst_cnt_next <= inst_cnt + 1; end if; -- SET Status Info - when 7 => + when 5 => inst_valid_in <= '1'; inst_addr <= inst_addr_base + IMF_STATUS_INFO_OFFSET; inst_write_data <= inst_latch_data.status_info; + inst_data_next.field_flags <= inst_data.field_flags or IMF_STATUS_FLAG; -- Memory Flow Control Guard if (inst_ready_in = '1') then inst_cnt_next <= inst_cnt + 1; end if; -- SET Sample Count - when 8 => + when 6 => inst_valid_in <= '1'; inst_addr <= inst_addr_base + IMF_SAMPLE_CNT_OFFSET; inst_write_data <= std_logic_vector(inst_latch_data.sample_cnt); + inst_data_next.field_flags <= inst_data.field_flags or IMF_SAMPLE_CNT_FLAG; -- Memory Flow Control Guard if (inst_ready_in = '1') then inst_cnt_next <= inst_cnt + 1; end if; -- SET ACK Count - when 9 => + when 7 => inst_valid_in <= '1'; inst_addr <= inst_addr_base + IMF_ACK_CNT_OFFSET; inst_write_data <= std_logic_vector(inst_latch_data.ack_cnt); + inst_data_next.field_flags <= inst_data.field_flags or IMF_ACK_CNT_FLAG; -- Memory Flow Control Guard if (inst_ready_in = '1') then + inst_cnt_next <= inst_cnt + 1; + end if; + -- SET Next Addr + when 8 => + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_NEXT_ADDR_OFFSET; + inst_write_data <= std_logic_vector(resize(inst_occupied_head,WORD_WIDTH)); + + -- Memory Flow Control Guard + if (inst_ready_in = '1') then + inst_cnt_next <= inst_cnt + 1; + end if; + -- SET Prev Addr + when 9 => + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_PREV_ADDR_OFFSET; + inst_write_data <= std_logic_vector(resize(INSTANCE_MEMORY_MAX_ADDRESS,WORD_WIDTH)); + + -- Memory Flow Control Guard + if (inst_ready_in = '1') then + if (inst_occupied_head = INSTANCE_MEMORY_MAX_ADDRESS) then + inst_cnt_next <= inst_cnt + 2; -- Skip Next Step + else + inst_cnt_next <= inst_cnt + 1; + end if; + end if; + -- SET Prev Addr (Occupied Head) + when 10 => + inst_valid_in <= '1'; + inst_addr <= inst_occupied_head + IMF_PREV_ADDR_OFFSET; + inst_write_data <= std_logic_vector(resize(inst_addr_base,WORD_WIDTH)); + + -- Memory Flow Control Guard + if (inst_ready_in = '1') then + inst_cnt_next <= inst_cnt + 1; + end if; + -- READ Next Addr + when 11 => + inst_ready_out <= '1'; + -- Memory Flow Control Guard + if (inst_valid_out = '1') then + + -- Update List Heads + inst_empty_head_next <= resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH); + inst_occupied_head_next <= inst_addr_base; + -- DONE - inst_stage_next <= IDLE; + inst_stage_next <= IDLE; end if; when others => null; @@ -4347,6 +4237,7 @@ begin inst_addr <= inst_addr_base + IMF_STATUS_INFO_OFFSET; inst_write_data <= inst_latch_data.status_info; inst_data_next.status_info <= inst_latch_data.status_info; + inst_data_next.field_flags <= inst_data.field_flags or IMF_STATUS_FLAG; -- Memory Flow Control Guard if (inst_ready_in = '1') then if check_mask(inst_latch_data.field_flags,IMF_SAMPLE_CNT_FLAG) then @@ -4364,6 +4255,7 @@ begin inst_addr <= inst_addr_base + IMF_SAMPLE_CNT_OFFSET; inst_write_data <= std_logic_vector(inst_latch_data.sample_cnt); inst_data_next.sample_cnt <= inst_latch_data.sample_cnt; + inst_data_next.field_flags <= inst_data.field_flags or IMF_SAMPLE_CNT_FLAG; -- Memory Flow Control Guard if (inst_ready_in = '1') then if check_mask(inst_latch_data.field_flags,IMF_ACK_CNT_FLAG) then @@ -4379,6 +4271,7 @@ begin inst_addr <= inst_addr_base + IMF_ACK_CNT_OFFSET; inst_write_data <= std_logic_vector(inst_latch_data.ack_cnt); inst_data_next.ack_cnt <= inst_latch_data.ack_cnt; + inst_data_next.field_flags <= inst_data.field_flags or IMF_ACK_CNT_FLAG; -- Memory Flow Control Guard if (inst_ready_in = '1') then -- DONE @@ -4388,103 +4281,142 @@ begin null; end case; when REMOVE_INSTANCE => - -- Precondition: inst_addr_base set, inst_prev_addr_base set - case (inst_cnt) is - -- GET Next Instance + -- GET Next Addr when 0 => - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_NEXT_ADDR_OFFSET; - inst_read <= '1'; - + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_NEXT_ADDR_OFFSET; + inst_read <= '1'; -- Memory Flow Control Guard if (inst_ready_in = '1') then - inst_cnt_next <= inst_cnt + 1; + inst_cnt_next <= inst_cnt + 1; end if; - -- READ Next Instance + -- GET Prev Addr when 1 => - inst_ready_out <= '1'; - + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_PREV_ADDR_OFFSET; + inst_read <= '1'; -- Memory Flow Control Guard - if (inst_valid_out = '1') then - inst_next_addr_base_next <= resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH); - - -- Removed Instance is List Head - if (inst_prev_addr_base = INSTANCE_MEMORY_MAX_ADDRESS) then - assert (inst_addr_base = inst_occupied_head) severity FAILURE; - - -- Fix Occupied Head - inst_occupied_head_next <= resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH); - - inst_cnt_next <= inst_cnt + 2; -- Skip Next Step - else - inst_cnt_next <= inst_cnt + 1; - end if; + if (inst_ready_in = '1') then + inst_cnt_next <= inst_cnt + 1; end if; - -- SET Next Pointer (Previous Instance) + -- SET Next Addr when 2 => - -- Point Previous instance to Next Instance (Remove current Instance from inbetween) - inst_valid_in <= '1'; - inst_addr <= inst_prev_addr_base + IMF_NEXT_ADDR_OFFSET; - inst_write_data <= std_logic_vector(resize(inst_next_addr_base,WORD_WIDTH)); + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_NEXT_ADDR_OFFSET; + inst_write_data <= std_logic_vector(resize(inst_empty_head,WORD_WIDTH)); - -- Memory Flow Control Guard if (inst_ready_in = '1') then - inst_cnt_next <= inst_cnt + 1; - end if; - -- SET Next Pointer (Current/Removed Instance) - when 3 => - -- Point Current Instance to Empty List Head (Make Removed Instance Head of the Empty List) - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_NEXT_ADDR_OFFSET; - inst_write_data <= std_logic_vector(resize(inst_empty_head,WORD_WIDTH)); - - -- Memory Flow Control Guard - if (inst_ready_in = '1') then - -- Fix Empty List Head + -- Set New Empty Head inst_empty_head_next <= inst_addr_base; - -- Reset - inst_data_next <= ZERO_INSTANCE_DATA; - inst_addr_base_next <= INSTANCE_MEMORY_MAX_ADDRESS; - + inst_cnt_next <= inst_cnt + 1; + end if; + -- READ Next Addr + when 3 => + inst_ready_out <= '1'; + -- Memory Flow Control Guard + if (inst_valid_out = '1') then + inst_addr_latch_next <= resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH); + inst_cnt_next <= inst_cnt + 1; + end if; + -- READ Prev Addr + when 4 => + inst_ready_out <= '1'; + -- Memory Flow Control Guard + if (inst_valid_out = '1') then + if (inst_addr_latch = INSTANCE_MEMORY_MAX_ADDRESS) then + if (resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH) = INSTANCE_MEMORY_MAX_ADDRESS) then + -- RESET Occupied List Head + inst_occupied_head_next <= INSTANCE_MEMORY_MAX_ADDRESS; + + inst_data_next.addr <= INSTANCE_MEMORY_MAX_ADDRESS; + -- DONE + inst_stage_next <= IDLE; + else + inst_addr_base_next <= resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH); + inst_cnt_next <= inst_cnt + 2; -- Skip Next Step + end if; + else + inst_addr_base_next <= inst_addr_latch; + inst_addr_latch_next <= resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH); + inst_cnt_next <= inst_cnt + 1; + end if; + end if; + -- SET Prev Addr (Next Slot) + when 5 => + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_PREV_ADDR_OFFSET; + inst_write_data <= std_logic_vector(resize(inst_addr_latch,WORD_WIDTH)); + + if (inst_ready_in = '1') then + if (inst_addr_latch = INSTANCE_MEMORY_MAX_ADDRESS) then + -- Set New Occupied List Head + inst_occupied_head_next <= inst_addr_base; + + inst_data_next.addr <= inst_addr_base; + -- DONE + inst_stage_next <= IDLE; + else + inst_addr_base_next <= inst_addr_latch; + inst_addr_latch_next <= inst_addr_base; + inst_cnt_next <= inst_cnt + 1; + end if; + end if; + -- SET Next Addr (Previous Slot) + when 6 => + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_NEXT_ADDR_OFFSET; + inst_write_data <= std_logic_vector(resize(inst_addr_latch,WORD_WIDTH)); + + if (inst_ready_in = '1') then + inst_data_next.addr <= inst_addr_latch; -- DONE - inst_stage_next <= IDLE; + inst_stage_next <= IDLE; end if; when others => null; end case; when RESET_MEMORY => case (inst_cnt) is - -- Initialize - when 0 => - inst_addr_base_next <= FIRST_INSTANCE_ADDRESS; - inst_cnt_next <= inst_cnt + 1; -- SET Next Pointer - when 1 => - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_NEXT_ADDR_OFFSET; + when 0 => + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_NEXT_ADDR_OFFSET; if (inst_addr_base = MAX_INSTANCE_ADDRESS) then - inst_write_data <= std_logic_vector(resize(INSTANCE_MEMORY_MAX_ADDRESS,WORD_WIDTH)); + inst_write_data <= std_logic_vector(resize(INSTANCE_MEMORY_MAX_ADDRESS,WORD_WIDTH)); else - inst_write_data <= std_logic_vector(resize(inst_addr_base + INSTANCE_FRAME_SIZE,WORD_WIDTH)); + inst_write_data <= std_logic_vector(resize(inst_addr_base + INSTANCE_FRAME_SIZE,WORD_WIDTH)); end if; + -- Memory Flow Control Guard + if (inst_ready_in = '1') then + inst_cnt_next <= inst_cnt + 1; + end if; + -- SET Previous Pointer + when 1 => + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_PREV_ADDR_OFFSET; + inst_write_data <= std_logic_vector(resize(inst_addr_latch,WORD_WIDTH)); + -- Memory Flow Control Guard if (inst_ready_in = '1') then if (inst_addr_base = MAX_INSTANCE_ADDRESS) then - -- DONE - inst_stage_next <= IDLE; + -- Initialize Empty and Occupied Heads inst_empty_head_next <= FIRST_INSTANCE_ADDRESS; + inst_occupied_head_next <= INSTANCE_MEMORY_MAX_ADDRESS; + + -- DONE + inst_stage_next <= IDLE; else - inst_addr_base_next <= inst_addr_base + INSTANCE_FRAME_SIZE; + inst_addr_latch_next <= inst_addr_base; + inst_addr_base_next <= inst_addr_base + INSTANCE_FRAME_SIZE; + inst_cnt_next <= 0; end if; end if; when others => null; end case; - when others => - null; end case; end process; end generate; @@ -4513,7 +4445,10 @@ begin cc_seq_nr_sig <= SEQUENCENUMBER_UNKNOWN; cc_kind_sig <= ALIVE; inst_data <= ZERO_INSTANCE_DATA; - inst_latch_data <= ZERO_INST_LATCH_DATA; + if (not WITH_KEY) then + inst_data.field_flags <= (others => '1'); + end if; + inst_latch_data <= ZERO_INSTANCE_DATA; cnt <= 0; cnt2 <= 0; cnt3 <= 0; @@ -4555,13 +4490,11 @@ begin liveliness_lost_cnt <= (others => '0'); liveliness_lost_cnt_change <= (others => '0'); status_sig <= (others => '0'); - current_imf <= (others => '0'); - inst_addr_base <= (others => '0'); + inst_addr_base <= FIRST_INSTANCE_ADDRESS; inst_empty_head <= INSTANCE_MEMORY_MAX_ADDRESS; inst_occupied_head <= INSTANCE_MEMORY_MAX_ADDRESS; + inst_addr_latch <= INSTANCE_MEMORY_MAX_ADDRESS; inst_long_latch <= (others => '0'); - inst_next_addr_base <= (others => '0'); - inst_prev_addr_base <= (others => '0'); return_code_latch <= RETCODE_UNSUPPORTED; else stage <= stage_next; @@ -4630,17 +4563,11 @@ begin liveliness_lost_cnt <= liveliness_lost_cnt_next; liveliness_lost_cnt_change <= liveliness_lost_cnt_change_next; status_sig <= status_sig_next; - if (WITH_KEY) then - current_imf <= current_imf_next; - else - current_imf <= (others => '1'); - end if; inst_addr_base <= inst_addr_base_next; inst_empty_head <= inst_empty_head_next; inst_occupied_head <= inst_occupied_head_next; + inst_addr_latch <= inst_addr_latch_next; inst_long_latch <= inst_long_latch_next; - inst_next_addr_base <= inst_next_addr_base_next; - inst_prev_addr_base <= inst_prev_addr_base_next; return_code_latch <= return_code_latch_next; end if; end if; diff --git a/src/rtps_discovery_module.vhd b/src/rtps_discovery_module.vhd index 8180d87..ba410af 100644 --- a/src/rtps_discovery_module.vhd +++ b/src/rtps_discovery_module.vhd @@ -140,7 +140,7 @@ architecture arch of rtps_discovery_module is LATCH_LIFESPAN_DURATION, RXO_RELIABILITY, RXO_DESTINATION_ORDER, RXO_OWNERSHIP, RXO_PRESENTATION, RXO_PARTITION, RXO_LATENCY_BUDGET, CHECK_MAX_SIZE_SERIALIZED, MATCH_DOMAIN_ID, MATCH_PROTOCOL_VERSION, LATCH_LOCATOR, LATCH_EXPECTS_INLINE_QOS, MATCH_GUID, CHECK_REMOTE_BUILTIN_ENDPOINTS, CHECK_STATUS_INFO, PARTICIPANT_MATCH_STAGE, INFORM_ENDPOINTS_MATCH, INFORM_ENDPOINTS_UNMATCH, INFORM_ENDPOINTS_PARTICIPANT_UNMATCH, PARTICIPANT_STALE_CHECK, - LATCH_REMOVED_GUIDPREFIX, PROCESS_HEARTBEAT, PROCESS_HEARTBEAT_SEQUENCE_NUMBERS, SEND_ACKNACK, SEND_HEARTBEAT, PROCESS_ACKNACK, + PROCESS_HEARTBEAT, PROCESS_HEARTBEAT_SEQUENCE_NUMBERS, SEND_ACKNACK, SEND_HEARTBEAT, PROCESS_ACKNACK, PROCESS_ACKNACK_SEQUENCE_NUMBERS, FIND_PARTICIPANT_DEST, SEND_HEADER, SEND_PARTICIPANT_ANNOUNCEMENT, SEND_PUB_DATA, SEND_SUB_DATA, SEND_MES_MAN_LIVE, SEND_MES_GAP, SEND_MES_AUTO_LIVE, LIVELINESS_UPDATE, SKIP_PARAMETER, SKIP_PACKET); -- Memory FSM states. Explained below in detail @@ -3958,8 +3958,6 @@ begin -- Skip-Read rd_guard := '1'; end if; - when others => - null; end case; -- OVERREAD GUARD @@ -6225,8 +6223,6 @@ begin when others => null; end case; - when others => - null; end case; end process; diff --git a/src/rtps_handler.vhd b/src/rtps_handler.vhd index b667f07..b972b22 100644 --- a/src/rtps_handler.vhd +++ b/src/rtps_handler.vhd @@ -1306,8 +1306,6 @@ begin rd_guard := '1'; end if; -- NOTE: Exit condition is via the OVERREAD GUARD - when others => - null; end case; -- OVERREAD GUARD diff --git a/src/rtps_out.vhd b/src/rtps_out.vhd index 758e392..2580f5f 100644 --- a/src/rtps_out.vhd +++ b/src/rtps_out.vhd @@ -236,8 +236,6 @@ begin end if; end if; end if; - when others => - null; end case; end process; @@ -336,8 +334,6 @@ begin -- DONE output_stage_next <= IDLE; end if; - when others => - null; end case; end process; diff --git a/src/rtps_reader.vhd b/src/rtps_reader.vhd index 9bd5f14..408a030 100644 --- a/src/rtps_reader.vhd +++ b/src/rtps_reader.vhd @@ -142,7 +142,7 @@ architecture arch of rtps_reader is type MEM_STAGE_TYPE is (IDLE, SEARCH_ENDPOINT, GET_ENDPOINT_DATA, INSERT_ENDPOINT, UPDATE_ENDPOINT, REMOVE_ENDPOINT, GET_NEXT_ENDPOINT, RESET_MEMORY); -- *Memory FSM Opcodes* -- OPCODE DESCRIPTION - -- SEARCH_ENDPOINT Search memory for Endpoint with GUID equal to "guid" signal. + -- SEARCH_ENDPOINT Search memory for Endpoint with GUID equal to "mem_r.guid" signal. -- Set "mem_endpoint_data.addr" to base Address of found Endpoint, or ENDPOINT_MEMORY_MAX_ADDRESS if nothing found. -- "mem_endpoint_data" contains Endpoint Data according to "mem_r.field_flags". -- INSERT_ENDPOINT Insert Endpoint in memory @@ -550,6 +550,7 @@ begin payload_read <= '0'; payload_valid_in <= '0'; payload_ready_out <= '0'; + payload_abort_read <= '0'; @@ -2169,8 +2170,6 @@ begin -- Skip-Read rd_meta <= '1'; end if; - when others => - null; end case; -- OVERREAD GUARD @@ -3643,8 +3642,6 @@ begin when others => null; end case; - when others => - null; end case; end process; diff --git a/syn/rtps_reader_syn.vhd b/syn/rtps_reader_syn.vhd index c37078e..2119df1 100644 --- a/syn/rtps_reader_syn.vhd +++ b/syn/rtps_reader_syn.vhd @@ -17,12 +17,12 @@ entity rtps_reader_syn is reset : in std_logic; time : in TIME_TYPE; -- FROM RTPS HANDLER (USER TRAFFIC) - empty_user : in std_logic_vector(0 to NUM_READERS-1); + empty_user : in std_logic_vector(0 to 0); rd_user : out std_logic; data_in_user : in std_logic_vector(WORD_WIDTH-1 downto 0); last_word_in_user : in std_logic; -- FROM RTPS BUILTIN ENDPOINT (META TRAFFIC) - empty_meta : in std_logic_vector(0 to NUM_READERS-1); + empty_meta : in std_logic_vector(0 to 0); rd_meta : out std_logic; data_in_meta : in std_logic_vector(WORD_WIDTH-1 downto 0); last_word_in_meta : in std_logic; @@ -32,15 +32,15 @@ entity rtps_reader_syn is data_out_ro : out std_logic_vector(WORD_WIDTH-1 downto 0); last_word_out_ro : out std_logic; -- TO HISTORY CACHE - start_hc : out std_logic_vector(0 to NUM_READERS-1); - opcode_hc : out HISTORY_CACHE_OPCODE_ARRAY_TYPE(0 to NUM_READERS-1); - ack_hc : in std_logic_vector(0 to NUM_READERS-1); - done_hc : in std_logic_vector(0 to NUM_READERS-1); - ret_hc : in HISTORY_CACHE_RESPONSE_ARRAY_TYPE(0 to NUM_READERS-1); - valid_out_hc : out std_logic_vector(0 to NUM_READERS-1); - ready_out_hc : in std_logic_vector(0 to NUM_READERS-1); - data_out_hc : out WORD_ARRAY_TYPE(0 to NUM_READERS-1); - last_word_out_hc : out std_logic_vector(0 to NUM_READERS-1) + start_hc : out std_logic_vector(0 to 0); + opcode_hc : out HISTORY_CACHE_OPCODE_ARRAY_TYPE(0 to 0); + ack_hc : in std_logic_vector(0 to 0); + done_hc : in std_logic_vector(0 to 0); + ret_hc : in HISTORY_CACHE_RESPONSE_ARRAY_TYPE(0 to 0); + valid_out_hc : out std_logic_vector(0 to 0); + ready_out_hc : in std_logic_vector(0 to 0); + data_out_hc : out WORD_ARRAY_TYPE(0 to 0); + last_word_out_hc : out std_logic_vector(0 to 0) ); end entity; diff --git a/syn/rtps_writer_syn.vhd b/syn/rtps_writer_syn.vhd index 99333c6..7527597 100644 --- a/syn/rtps_writer_syn.vhd +++ b/syn/rtps_writer_syn.vhd @@ -17,40 +17,40 @@ entity rtps_writer_syn is reset : in std_logic; time : in TIME_TYPE; -- FROM RTPS HANDLER (USER TRAFFIC) - empty_user : in std_logic_vector(0 to NUM_WRITERS-1); + empty_user : in std_logic_vector(0 to 0); rd_user : out std_logic; data_in_user : in std_logic_vector(WORD_WIDTH-1 downto 0); last_word_in_user : in std_logic; -- FROM DISCOVERY MODULE (META TRAFFIC) - empty_meta : in std_logic_vector(0 to NUM_WRITERS-1); + empty_meta : in std_logic_vector(0 to 0); rd_meta : out std_logic; data_in_meta : in std_logic_vector(WORD_WIDTH-1 downto 0); last_word_in_meta : in std_logic; -- TO DISCOVERY MODULE (META TRAFFIC) - alive_sig : out std_logic_vector(0 to NUM_WRITERS-1); + alive_sig : out std_logic_vector(0 to 0); -- RTPS OUTPUT full_ro : in std_logic; wr_ro : out std_logic; data_out_ro : out std_logic_vector(WORD_WIDTH-1 downto 0); last_word_out_ro : out std_logic; -- FROM HISTORY CACHE - liveliness_assertion : in std_logic_vector(0 to NUM_WRITERS-1); - data_available : in std_logic_vector(0 to NUM_WRITERS-1); - start_hc : out std_logic_vector(0 to NUM_WRITERS-1); - opcode_hc : out HISTORY_CACHE_OPCODE_ARRAY_TYPE(0 to NUM_WRITERS-1); - ack_hc : in std_logic_vector(0 to NUM_WRITERS-1); - seq_nr_hc : out SEQUENCENUMBER_ARRAY_TYPE(0 to NUM_WRITERS-1); - done_hc : in std_logic_vector(0 to NUM_WRITERS-1); - ret_hc : in HISTORY_CACHE_RESPONSE_ARRAY_TYPE(0 to NUM_WRITERS-1); - get_data_hc : out std_logic_vector(0 to NUM_WRITERS-1); - valid_in_hc : in std_logic_vector(0 to NUM_WRITERS-1); - ready_in_hc : out std_logic_vector(0 to NUM_WRITERS-1); - data_in_hc : in WORD_ARRAY_TYPE(0 to NUM_WRITERS-1); - last_word_in_hc : in std_logic_vector(0 to NUM_WRITERS-1); - cc_instance_handle : in INSTANCE_HANDLE_ARRAY_TYPE(0 to NUM_WRITERS-1); - cc_kind : in CACHE_CHANGE_KIND_ARRAY_TYPE(0 to NUM_WRITERS-1); - cc_source_timestamp : in TIME_ARRAY_TYPE(0 to NUM_WRITERS-1); - cc_seq_nr : in SEQUENCENUMBER_ARRAY_TYPE(0 to NUM_WRITERS-1) + liveliness_assertion : in std_logic_vector(0 to 0); + data_available : in std_logic_vector(0 to 0); + start_hc : out std_logic_vector(0 to 0); + opcode_hc : out HISTORY_CACHE_OPCODE_ARRAY_TYPE(0 to 0); + ack_hc : in std_logic_vector(0 to 0); + seq_nr_hc : out SEQUENCENUMBER_ARRAY_TYPE(0 to 0); + done_hc : in std_logic_vector(0 to 0); + ret_hc : in HISTORY_CACHE_RESPONSE_ARRAY_TYPE(0 to 0); + get_data_hc : out std_logic_vector(0 to 0); + valid_in_hc : in std_logic_vector(0 to 0); + ready_in_hc : out std_logic_vector(0 to 0); + data_in_hc : in WORD_ARRAY_TYPE(0 to 0); + last_word_in_hc : in std_logic_vector(0 to 0); + cc_instance_handle : in INSTANCE_HANDLE_ARRAY_TYPE(0 to 0); + cc_kind : in CACHE_CHANGE_KIND_ARRAY_TYPE(0 to 0); + cc_source_timestamp : in TIME_ARRAY_TYPE(0 to 0); + cc_seq_nr : in SEQUENCENUMBER_ARRAY_TYPE(0 to 0) ); end entity;