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Add test 4 of DDS Reader

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Test Deadline Handling of the DDS Reader.
Test the GET_REQUESTED_DEADLINE_MISSED_STATUS DDS Operation.
Add Documentation to some Testbenches.
This commit is contained in:
Greek 2021-04-26 12:57:09 +02:00
parent 0beafe13b3
commit 7a096de5c1
14 changed files with 2030 additions and 49 deletions
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sim/L0_dds_reader_test4_arzkriu.do Normal file
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sim/L0_dds_reader_test4_arznriu.do Normal file
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src/Tests/Level_0/L0_dds_reader_test2_arpkriu.vhd
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@ -10,7 +10,7 @@ use work.user_config.all;
use work.rtps_config_package.all;
use work.rtps_test_package.all;
-- This testbench tests the handling of the TIME_BASED_FILTER QoS.
-- This testbench tests the handling of the TIME_BASED_FILTER QoS of the DDS Reader.
entity L0_dds_reader_test2_arpkriu is
end entity;

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src/Tests/Level_0/L0_dds_reader_test4_arzkriu.vhd Normal file
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@ -0,0 +1,846 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library osvvm; -- Utility Library
context osvvm.OsvvmContext;
use work.rtps_package.all;
use work.user_config.all;
use work.rtps_config_package.all;
use work.rtps_test_package.all;
-- This testbench tests the Deadline Handling of the DDS Reader, and more specifically the GET_REQUESTED_DEADLINE_MISSED_STATUS DDS Operation.
entity L0_dds_reader_test4_arzkriu is
end entity;
architecture testbench of L0_dds_reader_test4_arzkriu is
-- *CONSTANT DECLARATION*
constant MAX_REMOTE_ENDPOINTS : natural := 3;
-- *TYPE DECLARATION*
type DDS_STAGE_TYPE is (IDLE, START, DONE, CHECK_SI, CHECK_DATA, WAIT_EOC, CHECK_DEADLINE);
type RTPS_STAGE_TYPE is (IDLE, START, PUSH, DONE);
type KH_STAGE_TYPE is (IDLE, READ_DATA, PUSH_KEY_HASH);
-- *SIGNAL DECLARATION*
signal clk : std_logic := '0';
signal reset : std_logic := '1';
signal check_time : TIME_TYPE := TIME_ZERO;
signal start_rtps, start_dds, start_kh, ack_rtps, ack_dds, ack_kh, done_rtps, done_dds : std_logic := '0';
signal opcode_rtps : HISTORY_CACHE_OPCODE_TYPE := NOP;
signal opcode_dds : DDS_READER_OPCODE_TYPE := NOP;
signal opcode_kh : KEY_HOLDER_OPCODE_TYPE := NOP;
signal ret_rtps : HISTORY_CACHE_RESPONSE_TYPE := ERROR;
signal ready_in_rtps, valid_in_rtps, last_word_in_rtps : std_logic := '0';
signal ready_out_dds, valid_out_dds, last_word_out_dds : std_logic := '0';
signal ready_in_kh, ready_out_kh, valid_in_kh, valid_out_kh, last_word_in_kh, last_word_out_kh : std_logic := '0';
signal data_in_rtps, data_out_dds, data_in_kh, data_out_kh : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
signal get_data_dds, si_valid_data, si_valid, eoc, abort_kh : std_logic := '0';
signal return_code_dds : std_logic_vector(RETURN_CODE_WIDTH-1 downto 0) := (others => '0');
signal status : std_logic_vector(STATUS_KIND_WIDTH-1 downto 0) := (others => '0');
signal instance_state_dds, si_instance_state : std_logic_vector(INSTANCE_STATE_KIND_WIDTH-1 downto 0) := ANY_INSTANCE_STATE;
signal view_state_dds, si_view_state : std_logic_vector(VIEW_STATE_KIND_WIDTH-1 downto 0) := ANY_VIEW_STATE;
signal sample_state_dds, si_sample_state : std_logic_vector(SAMPLE_STATE_KIND_WIDTH-1 downto 0) := ANY_SAMPLE_STATE;
signal instance_handle_dds, si_instance_handle : INSTANCE_HANDLE_TYPE := HANDLE_NIL;
signal max_samples_dds : std_logic_vector(MAX_SAMPLES_WIDTH-1 downto 0) := (others => '0');
signal si_source_timestamp : TIME_TYPE := TIME_INVALID;
signal si_publication_handle : PUBLICATION_HANDLE_TYPE := (others => (others => '0'));
signal si_disposed_generation_count : std_logic_vector(DISPOSED_GENERATION_COUNT_WIDTH-1 downto 0) := (others => '0');
signal si_no_writers_generation_count : std_logic_vector(NO_WRITERS_GENERATION_COUNT_WIDTH-1 downto 0) := (others => '0');
signal si_sample_rank : std_logic_vector(SAMPLE_RANK_WIDTH-1 downto 0) := (others => '0');
signal si_generation_rank : std_logic_vector(GENERATION_RANK_WIDTH-1 downto 0) := (others => '0');
signal si_absolute_generation_rank: std_logic_vector(ABSOLUTE_GENERATION_COUNT_WIDTH-1 downto 0) := (others => '0');
signal dds_start , dds_done , rtps_start, rtps_done : std_logic := '0';
signal dds_cnt, dds_cnt2, rtps_cnt, kh_cnt : natural := 0;
signal dds_stage : DDS_STAGE_TYPE := IDLE;
signal rtps_stage : RTPS_STAGE_TYPE := IDLE;
signal kh_stage : KH_STAGE_TYPE := IDLE;
signal kh_data : TEST_PACKET_TYPE := EMPTY_TEST_PACKET;
shared variable dds : DDS_READER_TEST_TYPE := DEFAULT_DDS_READER_TEST;
shared variable rtps : RTPS_READER_TEST_TYPE := DEFAULT_RTPS_READER_TEST;
shared variable mem : DDS_READER_MEM_TYPE := DEFAULT_DDS_READER_MEM;
signal data_id, ret_id, sstate_id, vstate_id, istate_id, inst_id, ts_id, pub_id, dis_gen_cnt_id, no_w_gen_cnt_id, srank_id, grank_id, agrank_id, eoc_id, valid_id, status_id : AlertLogIDType;
-- *FUNCTION DECLARATION*
function extract_key_hash (payload : TEST_PACKET_TYPE) return INSTANCE_HANDLE_TYPE is
variable ret : INSTANCE_HANDLE_TYPE := HANDLE_NIL;
begin
for i in 0 to 3 loop
ret(i) := not payload.data(i);
end loop;
return ret;
end function;
function gen_sn(input : natural) return SEQUENCENUMBER_TYPE is
variable ret : SEQUENCENUMBER_TYPE;
begin
ret(0) := (others => '0');
ret(1) := unsigned(int(input, WORD_WIDTH));
return ret;
end function;
begin
-- Unit Under Test
uut : entity work.dds_reader(arch)
generic map (
TIME_BASED_FILTER_QOS => DURATION_ZERO,
DEADLINE_QOS => gen_duration(1,0),
MAX_SAMPLES => std_logic_vector(to_unsigned(10,CDR_LONG_WIDTH)),
MAX_INSTANCES => std_logic_vector(to_unsigned(4,CDR_LONG_WIDTH)),
MAX_SAMPLES_PER_INSTANCE => std_logic_vector(to_unsigned(10,CDR_LONG_WIDTH)),
HISTORY_QOS => KEEP_ALL_HISTORY_QOS,
RELIABILITY_QOS => RELIABLE_RELIABILITY_QOS,
PRESENTATION_QOS => INSTANCE_PRESENTATION_QOS,
DESTINATION_ORDER_QOS => BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS,
COHERENT_ACCESS => FALSE,
ORDERED_ACCESS => FALSE,
WITH_KEY => TRUE,
PAYLOAD_FRAME_SIZE => 11,
MAX_REMOTE_ENDPOINTS => MAX_REMOTE_ENDPOINTS
)
port map (
clk => clk,
reset => reset,
time => check_time,
start_rtps => start_rtps,
opcode_rtps => opcode_rtps,
ack_rtps => ack_rtps,
done_rtps => done_rtps,
ret_rtps => ret_rtps,
data_in_rtps => data_in_rtps,
valid_in_rtps => valid_in_rtps,
ready_in_rtps => ready_in_rtps,
last_word_in_rtps => last_word_in_rtps,
start_kh => start_kh,
opcode_kh => opcode_kh,
ack_kh => ack_kh,
data_in_kh => data_in_kh,
valid_in_kh => valid_in_kh,
ready_in_kh => ready_in_kh,
last_word_in_kh => last_word_in_kh,
data_out_kh => data_out_kh,
valid_out_kh => valid_out_kh,
ready_out_kh => ready_out_kh,
last_word_out_kh => last_word_out_kh,
abort_kh => abort_kh,
start_dds => start_dds,
ack_dds => ack_dds,
opcode_dds => opcode_dds,
instance_state_dds => instance_state_dds,
view_state_dds => view_state_dds,
sample_state_dds => sample_state_dds,
instance_handle_dds => instance_handle_dds,
max_samples_dds => max_samples_dds,
get_data_dds => get_data_dds,
done_dds => done_dds,
return_code_dds => return_code_dds,
ready_out_dds => ready_out_dds,
valid_out_dds => valid_out_dds,
data_out_dds => data_out_dds,
last_word_out_dds => last_word_out_dds,
si_sample_state => si_sample_state,
si_view_state => si_view_state,
si_instance_state => si_instance_state,
si_source_timestamp => si_source_timestamp,
si_instance_handle => si_instance_handle,
si_publication_handle => si_publication_handle,
si_disposed_generation_count => si_disposed_generation_count,
si_no_writers_generation_count => si_no_writers_generation_count,
si_sample_rank => si_sample_rank,
si_generation_rank => si_generation_rank,
si_absolute_generation_rank => si_absolute_generation_rank,
si_valid_data => si_valid_data,
si_valid => si_valid,
eoc => eoc,
status => status
);
stimulus_prc : process
variable RV : RandomPType;
variable kh1, kh2, kh3, kh4 : INSTANCE_HANDLE_TYPE := HANDLE_NIL;
variable cc1, cc2, cc3, cc4, cc : CACHE_CHANGE_TYPE := DEFAULT_CACHE_CHANGE;
variable s : SAMPLE_TYPE := DEFAULT_SAMPLE;
alias idle_sig is <<signal uut.idle_sig : std_logic>>;
impure function gen_payload(key_hash : INSTANCE_HANDLE_TYPE; len : natural) return TEST_PACKET_TYPE is
variable ret : TEST_PACKET_TYPE := EMPTY_TEST_PACKET;
begin
assert (len >= 4) report "Payload length has to be at least 16 Bytes long" severity FAILURE;
for i in 0 to len-1 loop
if (i < 4) then
-- NOTE: Beginning of payload is negated key to allow deterministic Key Hash generation from the kh_prc
ret.data(ret.length) := not key_hash(i);
else
ret.data(ret.length) := RV.RandSlv(WORD_WIDTH);
end if;
ret.length := ret.length + 1;
end loop;
ret.last(ret.length-1) := '1';
return ret;
end function;
impure function gen_key_hash return KEY_HASH_TYPE is
variable ret : KEY_HASH_TYPE := (others => (others => '0'));
begin
for i in 0 to KEY_HASH_TYPE'length-1 loop
ret(i) := RV.RandSlv(WORD_WIDTH);
end loop;
return ret;
end function;
procedure start_dds is
begin
dds_start <= '1';
wait until rising_edge(clk);
dds_start <= '0';
wait until rising_edge(clk);
end procedure;
procedure start_rtps is
begin
rtps_start <= '1';
wait until rising_edge(clk);
rtps_start <= '0';
wait until rising_edge(clk);
end procedure;
procedure wait_on_dds is
begin
if (dds_done /= '1') then
wait until dds_done = '1';
end if;
end procedure;
procedure wait_on_rtps is
begin
if (rtps_done /= '1') then
wait until rtps_done = '1';
end if;
end procedure;
procedure wait_on_completion is
begin
if (rtps_done /= '1' or dds_done /= '1') then
wait until rtps_done = '1' and dds_done = '1';
end if;
end procedure;
-- NOTE: This procedure waits until the idle_sig is high for at least
-- two consecutive clock cycles.
procedure wait_on_idle is
begin
loop
if (idle_sig /= '1') then
wait until idle_sig = '1';
else
exit;
end if;
wait until rising_edge(clk);
wait until rising_edge(clk);
end loop;
end procedure;
begin
SetAlertLogName("dds_reader - (KEEP ALL, Reliable, Zero TIME_BASED_FILTER, Keyed, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER, ACCESS SCOPE Instance, Unordered) - Level 0 - Deadline Handling");
SetAlertEnable(FAILURE, TRUE);
SetAlertEnable(ERROR, TRUE);
SetAlertEnable(WARNING, TRUE);
SetLogEnable(DEBUG, FALSE);
SetLogEnable(PASSED, FALSE);
SetLogEnable(INFO, TRUE);
RV.InitSeed(RV'instance_name);
sstate_id <= GetAlertLogID("Sample State", ALERTLOG_BASE_ID);
vstate_id <= GetAlertLogID("View State", ALERTLOG_BASE_ID);
istate_id <= GetAlertLogID("Instance State", ALERTLOG_BASE_ID);
ts_id <= GetAlertLogID("Source Timestamp", ALERTLOG_BASE_ID);
inst_id <= GetAlertLogID("Instance Handle", ALERTLOG_BASE_ID);
pub_id <= GetAlertLogID("Publication Hanlde", ALERTLOG_BASE_ID);
dis_gen_cnt_id <= GetAlertLogID("Disposed Generation Count", ALERTLOG_BASE_ID);
no_w_gen_cnt_id <= GetAlertLogID("No Writers Generation Count", ALERTLOG_BASE_ID);
srank_id <= GetAlertLogID("Sample Rank", ALERTLOG_BASE_ID);
grank_id <= GetAlertLogID("Generation Rank", ALERTLOG_BASE_ID);
agrank_id <= GetAlertLogID("Absolute Generation Rank", ALERTLOG_BASE_ID);
eoc_id <= GetAlertLogID("End of Collection", ALERTLOG_BASE_ID);
valid_id <= GetAlertLogID("Valid Data", ALERTLOG_BASE_ID);
data_id <= GetAlertLogID("Data Out", ALERTLOG_BASE_ID);
ret_id <= GetAlertLogID("Return Code", ALERTLOG_BASE_ID);
status_id <= GetAlertLogID("Communication Status", ALERTLOG_BASE_ID);
-- Key Hashes
kh1 := (x"F12C31DA", x"E3FE0F3F", x"01F36685", x"446518CA");
kh2 := (x"BC070AC4", x"0BAB5811", x"14EA8D61", x"F669189B");
kh3 := (x"0CEAB0C6", x"FA04B9AD", x"A96EB495", x"4E0EB999");
kh4 := (x"A7EB605C", x"FF4BEF3A", x"3C5E8724", x"CCA0CA67");
Log("Initiating Test", INFO);
Log("Current Time: 0s", INFO);
check_time <= TIME_ZERO;
reset <= '1';
wait until rising_edge(clk);
wait until rising_edge(clk);
reset <= '0';
wait_on_idle;
-- MEM: 0, 0, 0, 0
-- ISTATE: -
-- WRITER: -
AffirmIf(status_id,(status and REQUESTED_DEADLINE_MISSED_STATUS) /= REQUESTED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1");
Log("Current Time: 1s", INFO);
check_time <= gen_duration(1,0);
wait until rising_edge(clk);
wait until rising_edge(clk);
wait_on_idle;
AffirmIf(status_id,(status and REQUESTED_DEADLINE_MISSED_STATUS) /= REQUESTED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1");
cc := DEFAULT_CACHE_CHANGE;
cc.serialized_key := FALSE;
cc.kind := ALIVE;
cc.instance := kh1;
cc.payload := gen_payload(kh1,10);
cc.src_timestamp := gen_duration(1,0);
Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Aligned Payload] (ACCEPTED)", INFO);
rtps := DEFAULT_RTPS_READER_TEST;
rtps.opcode := ADD_CACHE_CHANGE;
rtps.cc := cc;
rtps.writer_pos := 0;
rtps.ret_code := OK;
s := to_sample(cc,ALIVE_INSTANCE_STATE);
add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
start_rtps;
wait_on_rtps;
wait_on_idle;
-- MEM: I1S1
-- ISTATE: I1:ALIVE
-- WRITER: W0:I1
cc := DEFAULT_CACHE_CHANGE;
cc.serialized_key := FALSE;
cc.kind := ALIVE;
cc.instance := kh2;
cc.payload := gen_payload(kh2,10);
cc.src_timestamp := gen_duration(2,0);
Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 2, Writer 1, Aligned Payload] (ACCEPTED)", INFO);
rtps := DEFAULT_RTPS_READER_TEST;
rtps.opcode := ADD_CACHE_CHANGE;
rtps.cc := cc;
rtps.writer_pos := 1;
rtps.ret_code := OK;
s := to_sample(cc,ALIVE_INSTANCE_STATE);
add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
start_rtps;
wait_on_rtps;
wait_on_idle;
-- MEM: I1S1, I2S1
-- ISTATE: I1:ALIVE, I2:ALIVE
-- WRITER: W0:I1, W1:I2
cc := DEFAULT_CACHE_CHANGE;
cc.serialized_key := FALSE;
cc.kind := ALIVE;
cc.instance := kh4;
cc.payload := gen_payload(kh4,10);
cc.src_timestamp := gen_duration(3,0);
Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 4, Writer 0, Aligned Payload] (ACCEPTED)", INFO);
rtps := DEFAULT_RTPS_READER_TEST;
rtps.opcode := ADD_CACHE_CHANGE;
rtps.cc := cc;
rtps.writer_pos := 0;
rtps.ret_code := OK;
s := to_sample(cc,ALIVE_INSTANCE_STATE);
add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
start_rtps;
wait_on_rtps;
wait_on_idle;
-- MEM: I1S1, I2S1, I4S1
-- ISTATE: I1:ALIVE, I2:ALIVE, I4:ALIVE
-- WRITER: W0:I1,I4, W1:I2
Log("Current Time: 2s", INFO);
check_time <= gen_duration(2,0);
wait until rising_edge(clk);
wait until rising_edge(clk);
wait_on_idle;
AffirmIf(status_id,(status and REQUESTED_DEADLINE_MISSED_STATUS) /= REQUESTED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1");
cc := DEFAULT_CACHE_CHANGE;
cc.serialized_key := FALSE;
cc.kind := ALIVE;
cc.instance := kh1;
cc.payload := gen_payload(kh1,10);
cc.src_timestamp := gen_duration(4,0);
Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Aligned Payload] (ACCEPTED)", INFO);
rtps := DEFAULT_RTPS_READER_TEST;
rtps.opcode := ADD_CACHE_CHANGE;
rtps.cc := cc;
rtps.writer_pos := 0;
rtps.ret_code := OK;
s := to_sample(cc,ALIVE_INSTANCE_STATE);
add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
start_rtps;
wait_on_rtps;
wait_on_idle;
-- MEM: I1S1, I2S1, I4S1, I1S2
-- ISTATE: I1:ALIVE, I2:ALIVE, I4:ALIVE
-- WRITER: W0:I1,I4, W1:I2
cc := DEFAULT_CACHE_CHANGE;
cc.serialized_key := FALSE;
cc.kind := ALIVE;
cc.instance := kh4;
cc.payload := gen_payload(kh4,10);
cc.src_timestamp := gen_duration(5,0);
Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 1, Aligned Payload] (ACCEPTED)", INFO);
rtps := DEFAULT_RTPS_READER_TEST;
rtps.opcode := ADD_CACHE_CHANGE;
rtps.cc := cc;
rtps.writer_pos := 1;
rtps.ret_code := OK;
s := to_sample(cc,ALIVE_INSTANCE_STATE);
add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
start_rtps;
wait_on_rtps;
wait_on_idle;
-- MEM: I1S1, I2S1, I4S1, I1S2, I4S2
-- ISTATE: I1:ALIVE, I2:ALIVE, I4:ALIVE
-- WRITER: W0:I1,I4, W1:I2,I4
Log("Current Time: 3s", INFO);
check_time <= gen_duration(3,0);
wait until rising_edge(clk);
wait until rising_edge(clk);
wait_on_idle;
AffirmIf(status_id,(status and REQUESTED_DEADLINE_MISSED_STATUS) = REQUESTED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0");
Log("DDS Operation GET_REQUESTED_DEADLINE_MISSED_STATUS (Expected: count 1, change 1, Instance 2)", INFO);
dds := DEFAULT_DDS_READER_TEST;
dds.opcode := GET_REQUESTED_DEADLINE_MISSED_STATUS;
dds.ret_code := RETCODE_OK;
dds.count := 1;
dds.change := 1;
dds.inst := kh2;
start_dds;
wait_on_dds;
wait_on_idle;
AffirmIf(status_id,(status and REQUESTED_DEADLINE_MISSED_STATUS) /= REQUESTED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1");
cc := DEFAULT_CACHE_CHANGE;
cc.serialized_key := FALSE;
cc.kind := ALIVE;
cc.instance := kh3;
cc.payload := gen_payload(kh3,10);
cc.src_timestamp := gen_duration(6,0);
Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 3, Writer 2, Aligned Payload] (ACCEPTED)", INFO);
rtps := DEFAULT_RTPS_READER_TEST;
rtps.opcode := ADD_CACHE_CHANGE;
rtps.cc := cc;
rtps.writer_pos := 2;
rtps.ret_code := OK;
s := to_sample(cc,ALIVE_INSTANCE_STATE);
add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
start_rtps;
wait_on_rtps;
wait_on_idle;
-- MEM: I1S1, I2S1, I4S1, I1S2, I4S2, I3S1
-- ISTATE: I1:ALIVE, I2:ALIVE, I3:ALIVE, I4:ALIVE
-- WRITER: W0:I1,I4, W1:I2,I4, W2:I3
Log("Current Time: 4s", INFO);
check_time <= gen_duration(4,0);
wait until rising_edge(clk);
wait until rising_edge(clk);
wait_on_idle;
AffirmIf(status_id,(status and REQUESTED_DEADLINE_MISSED_STATUS) = REQUESTED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0");
Log("DDS Operation GET_REQUESTED_DEADLINE_MISSED_STATUS (Expected: count 4, change 3, Instance 1)", INFO);
dds := DEFAULT_DDS_READER_TEST;
dds.opcode := GET_REQUESTED_DEADLINE_MISSED_STATUS;
dds.ret_code := RETCODE_OK;
dds.count := 4;
dds.change := 3;
dds.inst := kh1;
start_dds;
wait_on_dds;
wait_on_idle;
cc := DEFAULT_CACHE_CHANGE;
cc.serialized_key := FALSE;
cc.kind := ALIVE;
cc.instance := kh4;
cc.payload := gen_payload(kh4,10);
cc.src_timestamp := gen_duration(7,0);
Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 4, Writer 2, Aligned Payload] (ACCEPTED)", INFO);
rtps := DEFAULT_RTPS_READER_TEST;
rtps.opcode := ADD_CACHE_CHANGE;
rtps.cc := cc;
rtps.writer_pos := 2;
rtps.ret_code := OK;
s := to_sample(cc,ALIVE_INSTANCE_STATE);
add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
start_rtps;
wait_on_rtps;
wait_on_idle;
-- MEM: I1S1, I2S1, I4S1, I1S2, I4S2, I3S1, I4S3
-- ISTATE: I1:ALIVE, I2:ALIVE, I3:ALIVE, I4:ALIVE
-- WRITER: W0:I1,I4, W1:I2,I4, W2:I3,I4
AffirmIf(status_id,(status and REQUESTED_DEADLINE_MISSED_STATUS) /= REQUESTED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1");
Log("Current Time: 5s", INFO);
check_time <= gen_duration(5,0);
wait until rising_edge(clk);
wait until rising_edge(clk);
wait_on_idle;
AffirmIf(status_id,(status and REQUESTED_DEADLINE_MISSED_STATUS) = REQUESTED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0");
Log("Current Time: 6s", INFO);
check_time <= gen_duration(6,0);
wait until rising_edge(clk);
wait until rising_edge(clk);
wait_on_idle;
AffirmIf(status_id,(status and REQUESTED_DEADLINE_MISSED_STATUS) = REQUESTED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0");
Log("DDS Operation GET_REQUESTED_DEADLINE_MISSED_STATUS (Expected: count 11, change 7, Instance 1)", INFO);
dds := DEFAULT_DDS_READER_TEST;
dds.opcode := GET_REQUESTED_DEADLINE_MISSED_STATUS;
dds.ret_code := RETCODE_OK;
dds.count := 11;
dds.change := 7;
dds.inst := kh1;
start_dds;
wait_on_dds;
wait_on_idle;
AffirmIf(status_id,(status and REQUESTED_DEADLINE_MISSED_STATUS) /= REQUESTED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1");
wait_on_completion;
TranscriptOpen(RESULTS_FILE, APPEND_MODE);
SetTranscriptMirror;
ReportAlerts;
TranscriptClose;
std.env.stop;
wait;
end process;
clock_prc : process
begin
clk <= '0';
wait for 25 ns;
clk <= '1';
wait for 25 ns;
end process;
alert_prc : process(all)
begin
if rising_edge(clk) then
-- TODO
end if;
end process;
dds_prc : process(all)
variable col : COLLECTION_TYPE := DEFAULT_COLLECTION;
begin
if rising_edge(clk) then
dds_done <= '0';
case (dds_stage ) is
when IDLE =>
if (dds_start = '1') then
dds_stage <= START;
else
dds_done <= '1';
end if;
when START =>
if (ack_dds = '1') then
dds_stage <= DONE;
dds_cnt <= 0;
end if;
when DONE =>
if (done_dds = '1') then
AffirmIfEqual(ret_id, return_code_dds, dds.ret_code);
case (dds.ret_code) is
when RETCODE_OK =>
case (dds.opcode) is
when GET_REQUESTED_DEADLINE_MISSED_STATUS =>
dds_stage <= CHECK_DEADLINE;
dds_cnt <= 0;
when others =>
gen_collection(mem, col, dds, INSTANCE_PRESENTATION_QOS, FALSE);
dds_stage <= CHECK_SI;
dds_cnt <= 0;
end case;
when others =>
dds_stage <= IDLE;
end case;
end if;
when CHECK_SI =>
if (si_valid = '1') then
AffirmIfEqual(sstate_id, si_sample_state, col.s(dds_cnt).sstate);
AffirmIfEqual(vstate_id, si_view_state, col.s(dds_cnt).vstate);
AffirmIfEqual(istate_id, si_instance_state, col.s(dds_cnt).istate);
AffirmIfEqual(ts_id, convert_from_double_word(si_source_timestamp), convert_from_double_word(col.s(dds_cnt).ts));
AffirmIfEqual(inst_id, to_unsigned(si_instance_handle), to_unsigned(col.s(dds_cnt).inst));
AffirmIfEqual(pub_id, to_unsigned(si_publication_handle), to_unsigned(HANDLE_NIL));
AffirmIfEqual(dis_gen_cnt_id, si_disposed_generation_count, std_logic_vector(to_unsigned(col.s(dds_cnt).dis_gen_cnt,WORD_WIDTH)));
AffirmIfEqual(no_w_gen_cnt_id, si_no_writers_generation_count, std_logic_vector(to_unsigned(col.s(dds_cnt).no_w_gen_cnt,WORD_WIDTH)));
AffirmIfEqual(srank_id, si_sample_rank, std_logic_vector(to_unsigned(col.s(dds_cnt).srank,WORD_WIDTH)));
AffirmIfEqual(grank_id, si_generation_rank, std_logic_vector(to_unsigned(col.s(dds_cnt).grank,WORD_WIDTH)));
AffirmIfEqual(agrank_id, si_absolute_generation_rank, std_logic_vector(to_unsigned(col.s(dds_cnt).agrank,WORD_WIDTH)));
if (si_valid_data = '1') then
AffirmIf(valid_id, col.s(dds_cnt).data /= EMPTY_TEST_PACKET, "Sample with Data not expected");
dds_stage <= CHECK_DATA;
dds_cnt2 <= 0;
else
AffirmIf(valid_id, col.s(dds_cnt).data = EMPTY_TEST_PACKET, "Sample with Data expected");
if (dds_cnt = col.len-1) then
-- DONE
dds_stage <= WAIT_EOC;
else
dds_cnt <= dds_cnt + 1;
end if;
end if;
end if;
AffirmIf(eoc_id, eoc = '0', "EOC pulled high");
when CHECK_DATA =>
if (valid_out_dds = '1') then
AffirmIfEqual(data_id, data_out_dds, col.s(dds_cnt).data.data(dds_cnt2));
dds_cnt2 <= dds_cnt2 + 1;
if (dds_cnt2 = col.s(dds_cnt).data.length-1) then
AlertIf(data_id, last_word_out_dds /= '1', "Last Word Signal not pulled High", ERROR);
if (dds_cnt = col.len-1) then
-- DONE
dds_stage <= WAIT_EOC;
else
dds_stage <= CHECK_SI;
dds_cnt <= dds_cnt + 1;
end if;
end if;
end if;
when WAIT_EOC =>
if (eoc = '1') then
dds_stage <= IDLE;
end if;
when CHECK_DEADLINE =>
if (valid_out_dds = '1') then
dds_cnt <= dds_cnt + 1;
case (dds_cnt) is
when 0 =>
AffirmIfEqual(data_id, data_out_dds, std_logic_vector(to_unsigned(dds.count,CDR_LONG_WIDTH)));
when 1 =>
AffirmIfEqual(data_id, data_out_dds, std_logic_vector(to_unsigned(dds.change,CDR_LONG_WIDTH)));
when 2 =>
AffirmIfEqual(data_id, data_out_dds, std_logic_vector(dds.inst(0)));
when 3 =>
AffirmIfEqual(data_id, data_out_dds, std_logic_vector(dds.inst(1)));
when 4 =>
AffirmIfEqual(data_id, data_out_dds, std_logic_vector(dds.inst(2)));
when 5 =>
AffirmIfEqual(data_id, data_out_dds, std_logic_vector(dds.inst(3)));
AlertIf(data_id, last_word_out_dds /= '1', "Last Word Signal not pulled High", ERROR);
dds_stage <= IDLE;
when others =>
null;
end case;
end if;
end case;
end if;
-- DEFAULT
start_dds <= '0';
opcode_dds <= NOP;
instance_state_dds <= ANY_INSTANCE_STATE;
view_state_dds <= ANY_VIEW_STATE;
sample_state_dds <= ANY_SAMPLE_STATE;
instance_handle_dds <= HANDLE_NIL;
max_samples_dds <= (others => '0');
get_data_dds <= '0';
ready_out_dds <= '0';
case (dds_stage ) is
when START =>
start_dds <= '1';
opcode_dds <= dds.opcode;
instance_state_dds <= dds.istate;
view_state_dds <= dds.vstate;
sample_state_dds <= dds.sstate;
instance_handle_dds <= dds.inst;
max_samples_dds <= std_logic_vector(to_unsigned(dds.max_samples, WORD_WIDTH));
when CHECK_SI =>
if (si_valid = '1' and si_valid_data = '1') then
get_data_dds <= '1';
end if;
when CHECK_DATA =>
ready_out_dds <= '1';
when CHECK_DEADLINE =>
ready_out_dds <= '1';
when others =>
null;
end case;
end process;
rtps_prc : process(all)
variable stimulus : TEST_PACKET_TYPE := EMPTY_TEST_PACKET;
begin
if rising_edge(clk) then
rtps_done <= '0';
case (rtps_stage) is
when IDLE =>
if (rtps_start = '1') then
rtps_stage <= START;
else
rtps_done <= '1';
end if;
when START =>
if (ack_rtps = '1') then
case (rtps.opcode) is
when ADD_CACHE_CHANGE =>
gen_add_cache_change_dds(rtps.cc, rtps.lifespan, rtps.writer_pos, stimulus);
rtps_stage <= PUSH;
when others =>
rtps_stage <= DONE;
end case;
end if;
when PUSH =>
if (ready_in_rtps = '1') then
rtps_cnt <= rtps_cnt + 1;
if (rtps_cnt = stimulus.length-1) then
rtps_stage <= DONE;
end if;
end if;
when DONE =>
if (done_rtps = '1') then
AffirmIfEqual(ret_id, HISTORY_CACHE_RESPONSE_TYPE'pos(ret_rtps), HISTORY_CACHE_RESPONSE_TYPE'pos(rtps.ret_code));
rtps_stage <= IDLE;
end if;
end case;
end if;
-- DEFAULT
start_rtps <= '0';
opcode_rtps <= NOP;
valid_in_rtps <= '0';
last_word_in_rtps <= '0';
data_in_rtps <= (others => '0');
case (rtps_stage) is
when START =>
start_rtps <= '1';
opcode_rtps <= rtps.opcode;
case (rtps.opcode) is
when REMOVE_WRITER =>
data_in_rtps <= std_logic_vector(to_unsigned(rtps.writer_pos,WORD_WIDTH));
when others =>
null;
end case;
when PUSH =>
valid_in_rtps <= '1';
data_in_rtps <= stimulus.data(rtps_cnt);
last_word_in_rtps <= stimulus.last(rtps_cnt);
when others =>
null;
end case;
end process;
kh_prc : process (all)
variable tmp_key_hash : INSTANCE_HANDLE_TYPE := HANDLE_NIL;
begin
if rising_edge(clk) then
case (kh_stage) is
when IDLE =>
if (start_kh = '1') then
case (opcode_kh) is
when PUSH_DATA =>
kh_stage <= READ_DATA;
kh_cnt <= 0;
kh_data <= EMPTY_TEST_PACKET;
when PUSH_SERIALIZED_KEY =>
kh_stage <= READ_DATA;
kh_cnt <= 0;
kh_data <= EMPTY_TEST_PACKET;
when READ_KEY_HASH =>
kh_stage <= PUSH_KEY_HASH;
kh_cnt <= 0;
when others =>
Alert("Unexpected Key Holder Operation", FAILURE);
end case;
end if;
when READ_DATA =>
if (valid_out_kh = '1') then
kh_data.data(kh_cnt) <= data_out_kh;
kh_data.last(kh_cnt) <= last_word_out_kh;
kh_data.length <= kh_data.length + 1;
kh_cnt <= kh_cnt + 1;
if (last_word_out_kh = '1') then
kh_stage <= IDLE;
end if;
end if;
when PUSH_KEY_HASH =>
if (ready_in_kh = '1') then
kh_cnt <= kh_cnt + 1;
if (kh_cnt = INSTANCE_HANDLE_TYPE'length-1) then
kh_stage <= IDLE;
end if;
end if;
end case;
end if;
-- DEFAULT
ack_kh <= '0';
ready_out_kh <= '0';
valid_in_kh <= '0';
data_in_kh <= (others => '0');
last_word_in_kh <= '0';
case (kh_stage) is
when IDLE =>
if (start_kh = '1') then
ack_kh <= '1';
end if;
when READ_DATA =>
ready_out_kh <= '1';
when PUSH_KEY_HASH =>
valid_in_kh <= '1';
tmp_key_hash := extract_key_hash(kh_data);
data_in_kh <= tmp_key_hash(kh_cnt);
if (kh_cnt = INSTANCE_HANDLE_TYPE'length-1) then
last_word_in_kh <= '1';
end if;
end case;
end process;
watchdog : process
begin
wait for 1 ms;
Alert("Test timeout", FAILURE);
std.env.stop;
end process;
end architecture;

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src/Tests/Level_0/L0_dds_reader_test4_arznriu.vhd Normal file
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library osvvm; -- Utility Library
context osvvm.OsvvmContext;
use work.rtps_package.all;
use work.user_config.all;
use work.rtps_config_package.all;
use work.rtps_test_package.all;
-- This testbench tests the Deadline Handling of the DDS Reader, and more specifically the GET_REQUESTED_DEADLINE_MISSED_STATUS DDS Operation.
entity L0_dds_reader_test4_arznriu is
end entity;
architecture testbench of L0_dds_reader_test4_arznriu is
-- *CONSTANT DECLARATION*
constant MAX_REMOTE_ENDPOINTS : natural := 3;
-- *TYPE DECLARATION*
type DDS_STAGE_TYPE is (IDLE, START, DONE, CHECK_SI, CHECK_DATA, WAIT_EOC, CHECK_DEADLINE);
type RTPS_STAGE_TYPE is (IDLE, START, PUSH, DONE);
type KH_STAGE_TYPE is (IDLE, READ_DATA, PUSH_KEY_HASH);
-- *SIGNAL DECLARATION*
signal clk : std_logic := '0';
signal reset : std_logic := '1';
signal check_time : TIME_TYPE := TIME_ZERO;
signal start_rtps, start_dds, start_kh, ack_rtps, ack_dds, ack_kh, done_rtps, done_dds : std_logic := '0';
signal opcode_rtps : HISTORY_CACHE_OPCODE_TYPE := NOP;
signal opcode_dds : DDS_READER_OPCODE_TYPE := NOP;
signal opcode_kh : KEY_HOLDER_OPCODE_TYPE := NOP;
signal ret_rtps : HISTORY_CACHE_RESPONSE_TYPE := ERROR;
signal ready_in_rtps, valid_in_rtps, last_word_in_rtps : std_logic := '0';
signal ready_out_dds, valid_out_dds, last_word_out_dds : std_logic := '0';
signal ready_in_kh, ready_out_kh, valid_in_kh, valid_out_kh, last_word_in_kh, last_word_out_kh : std_logic := '0';
signal data_in_rtps, data_out_dds, data_in_kh, data_out_kh : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
signal get_data_dds, si_valid_data, si_valid, eoc, abort_kh : std_logic := '0';
signal return_code_dds : std_logic_vector(RETURN_CODE_WIDTH-1 downto 0) := (others => '0');
signal status : std_logic_vector(STATUS_KIND_WIDTH-1 downto 0) := (others => '0');
signal instance_state_dds, si_instance_state : std_logic_vector(INSTANCE_STATE_KIND_WIDTH-1 downto 0) := ANY_INSTANCE_STATE;
signal view_state_dds, si_view_state : std_logic_vector(VIEW_STATE_KIND_WIDTH-1 downto 0) := ANY_VIEW_STATE;
signal sample_state_dds, si_sample_state : std_logic_vector(SAMPLE_STATE_KIND_WIDTH-1 downto 0) := ANY_SAMPLE_STATE;
signal instance_handle_dds, si_instance_handle : INSTANCE_HANDLE_TYPE := HANDLE_NIL;
signal max_samples_dds : std_logic_vector(MAX_SAMPLES_WIDTH-1 downto 0) := (others => '0');
signal si_source_timestamp : TIME_TYPE := TIME_INVALID;
signal si_publication_handle : PUBLICATION_HANDLE_TYPE := (others => (others => '0'));
signal si_disposed_generation_count : std_logic_vector(DISPOSED_GENERATION_COUNT_WIDTH-1 downto 0) := (others => '0');
signal si_no_writers_generation_count : std_logic_vector(NO_WRITERS_GENERATION_COUNT_WIDTH-1 downto 0) := (others => '0');
signal si_sample_rank : std_logic_vector(SAMPLE_RANK_WIDTH-1 downto 0) := (others => '0');
signal si_generation_rank : std_logic_vector(GENERATION_RANK_WIDTH-1 downto 0) := (others => '0');
signal si_absolute_generation_rank: std_logic_vector(ABSOLUTE_GENERATION_COUNT_WIDTH-1 downto 0) := (others => '0');
signal dds_start , dds_done , rtps_start, rtps_done : std_logic := '0';
signal dds_cnt, dds_cnt2, rtps_cnt, kh_cnt : natural := 0;
signal dds_stage : DDS_STAGE_TYPE := IDLE;
signal rtps_stage : RTPS_STAGE_TYPE := IDLE;
signal kh_stage : KH_STAGE_TYPE := IDLE;
signal kh_data : TEST_PACKET_TYPE := EMPTY_TEST_PACKET;
shared variable dds : DDS_READER_TEST_TYPE := DEFAULT_DDS_READER_TEST;
shared variable rtps : RTPS_READER_TEST_TYPE := DEFAULT_RTPS_READER_TEST;
shared variable mem : DDS_READER_MEM_TYPE := DEFAULT_DDS_READER_MEM;
signal data_id, ret_id, sstate_id, vstate_id, istate_id, inst_id, ts_id, pub_id, dis_gen_cnt_id, no_w_gen_cnt_id, srank_id, grank_id, agrank_id, eoc_id, valid_id, status_id : AlertLogIDType;
-- *FUNCTION DECLARATION*
function extract_key_hash (payload : TEST_PACKET_TYPE) return INSTANCE_HANDLE_TYPE is
variable ret : INSTANCE_HANDLE_TYPE := HANDLE_NIL;
begin
for i in 0 to 3 loop
ret(i) := not payload.data(i);
end loop;
return ret;
end function;
function gen_sn(input : natural) return SEQUENCENUMBER_TYPE is
variable ret : SEQUENCENUMBER_TYPE;
begin
ret(0) := (others => '0');
ret(1) := unsigned(int(input, WORD_WIDTH));
return ret;
end function;
begin
-- Unit Under Test
uut : entity work.dds_reader(arch)
generic map (
TIME_BASED_FILTER_QOS => DURATION_ZERO,
DEADLINE_QOS => gen_duration(1,0),
MAX_SAMPLES => std_logic_vector(to_unsigned(10,CDR_LONG_WIDTH)),
MAX_INSTANCES => std_logic_vector(to_unsigned(4,CDR_LONG_WIDTH)),
MAX_SAMPLES_PER_INSTANCE => std_logic_vector(to_unsigned(10,CDR_LONG_WIDTH)),
HISTORY_QOS => KEEP_ALL_HISTORY_QOS,
RELIABILITY_QOS => RELIABLE_RELIABILITY_QOS,
PRESENTATION_QOS => INSTANCE_PRESENTATION_QOS,
DESTINATION_ORDER_QOS => BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS,
COHERENT_ACCESS => FALSE,
ORDERED_ACCESS => FALSE,
WITH_KEY => FALSE,
PAYLOAD_FRAME_SIZE => 11,
MAX_REMOTE_ENDPOINTS => MAX_REMOTE_ENDPOINTS
)
port map (
clk => clk,
reset => reset,
time => check_time,
start_rtps => start_rtps,
opcode_rtps => opcode_rtps,
ack_rtps => ack_rtps,
done_rtps => done_rtps,
ret_rtps => ret_rtps,
data_in_rtps => data_in_rtps,
valid_in_rtps => valid_in_rtps,
ready_in_rtps => ready_in_rtps,
last_word_in_rtps => last_word_in_rtps,
start_kh => start_kh,
opcode_kh => opcode_kh,
ack_kh => ack_kh,
data_in_kh => data_in_kh,
valid_in_kh => valid_in_kh,
ready_in_kh => ready_in_kh,
last_word_in_kh => last_word_in_kh,
data_out_kh => data_out_kh,
valid_out_kh => valid_out_kh,
ready_out_kh => ready_out_kh,
last_word_out_kh => last_word_out_kh,
abort_kh => abort_kh,
start_dds => start_dds,
ack_dds => ack_dds,
opcode_dds => opcode_dds,
instance_state_dds => instance_state_dds,
view_state_dds => view_state_dds,
sample_state_dds => sample_state_dds,
instance_handle_dds => instance_handle_dds,
max_samples_dds => max_samples_dds,
get_data_dds => get_data_dds,
done_dds => done_dds,
return_code_dds => return_code_dds,
ready_out_dds => ready_out_dds,
valid_out_dds => valid_out_dds,
data_out_dds => data_out_dds,
last_word_out_dds => last_word_out_dds,
si_sample_state => si_sample_state,
si_view_state => si_view_state,
si_instance_state => si_instance_state,
si_source_timestamp => si_source_timestamp,
si_instance_handle => si_instance_handle,
si_publication_handle => si_publication_handle,
si_disposed_generation_count => si_disposed_generation_count,
si_no_writers_generation_count => si_no_writers_generation_count,
si_sample_rank => si_sample_rank,
si_generation_rank => si_generation_rank,
si_absolute_generation_rank => si_absolute_generation_rank,
si_valid_data => si_valid_data,
si_valid => si_valid,
eoc => eoc,
status => status
);
stimulus_prc : process
variable RV : RandomPType;
variable kh1, kh2, kh3, kh4 : INSTANCE_HANDLE_TYPE := HANDLE_NIL;
variable cc1, cc2, cc3, cc4, cc : CACHE_CHANGE_TYPE := DEFAULT_CACHE_CHANGE;
variable s : SAMPLE_TYPE := DEFAULT_SAMPLE;
alias idle_sig is <<signal uut.idle_sig : std_logic>>;
impure function gen_payload(key_hash : INSTANCE_HANDLE_TYPE; len : natural) return TEST_PACKET_TYPE is
variable ret : TEST_PACKET_TYPE := EMPTY_TEST_PACKET;
begin
assert (len >= 4) report "Payload length has to be at least 16 Bytes long" severity FAILURE;
for i in 0 to len-1 loop
if (i < 4) then
-- NOTE: Beginning of payload is negated key to allow deterministic Key Hash generation from the kh_prc
ret.data(ret.length) := not key_hash(i);
else
ret.data(ret.length) := RV.RandSlv(WORD_WIDTH);
end if;
ret.length := ret.length + 1;
end loop;
ret.last(ret.length-1) := '1';
return ret;
end function;
impure function gen_key_hash return KEY_HASH_TYPE is
variable ret : KEY_HASH_TYPE := (others => (others => '0'));
begin
for i in 0 to KEY_HASH_TYPE'length-1 loop
ret(i) := RV.RandSlv(WORD_WIDTH);
end loop;
return ret;
end function;
procedure start_dds is
begin
dds_start <= '1';
wait until rising_edge(clk);
dds_start <= '0';
wait until rising_edge(clk);
end procedure;
procedure start_rtps is
begin
rtps_start <= '1';
wait until rising_edge(clk);
rtps_start <= '0';
wait until rising_edge(clk);
end procedure;
procedure wait_on_dds is
begin
if (dds_done /= '1') then
wait until dds_done = '1';
end if;
end procedure;
procedure wait_on_rtps is
begin
if (rtps_done /= '1') then
wait until rtps_done = '1';
end if;
end procedure;
procedure wait_on_completion is
begin
if (rtps_done /= '1' or dds_done /= '1') then
wait until rtps_done = '1' and dds_done = '1';
end if;
end procedure;
-- NOTE: This procedure waits until the idle_sig is high for at least
-- two consecutive clock cycles.
procedure wait_on_idle is
begin
loop
if (idle_sig /= '1') then
wait until idle_sig = '1';
else
exit;
end if;
wait until rising_edge(clk);
wait until rising_edge(clk);
end loop;
end procedure;
begin
SetAlertLogName("dds_reader - (KEEP ALL, Reliable, Zero TIME_BASED_FILTER, Keyless, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER, ACCESS SCOPE Instance, Unordered) - Level 0 - Deadline Handling");
SetAlertEnable(FAILURE, TRUE);
SetAlertEnable(ERROR, TRUE);
SetAlertEnable(WARNING, TRUE);
SetLogEnable(DEBUG, FALSE);
SetLogEnable(PASSED, FALSE);
SetLogEnable(INFO, TRUE);
RV.InitSeed(RV'instance_name);
sstate_id <= GetAlertLogID("Sample State", ALERTLOG_BASE_ID);
vstate_id <= GetAlertLogID("View State", ALERTLOG_BASE_ID);
istate_id <= GetAlertLogID("Instance State", ALERTLOG_BASE_ID);
ts_id <= GetAlertLogID("Source Timestamp", ALERTLOG_BASE_ID);
inst_id <= GetAlertLogID("Instance Handle", ALERTLOG_BASE_ID);
pub_id <= GetAlertLogID("Publication Hanlde", ALERTLOG_BASE_ID);
dis_gen_cnt_id <= GetAlertLogID("Disposed Generation Count", ALERTLOG_BASE_ID);
no_w_gen_cnt_id <= GetAlertLogID("No Writers Generation Count", ALERTLOG_BASE_ID);
srank_id <= GetAlertLogID("Sample Rank", ALERTLOG_BASE_ID);
grank_id <= GetAlertLogID("Generation Rank", ALERTLOG_BASE_ID);
agrank_id <= GetAlertLogID("Absolute Generation Rank", ALERTLOG_BASE_ID);
eoc_id <= GetAlertLogID("End of Collection", ALERTLOG_BASE_ID);
valid_id <= GetAlertLogID("Valid Data", ALERTLOG_BASE_ID);
data_id <= GetAlertLogID("Data Out", ALERTLOG_BASE_ID);
ret_id <= GetAlertLogID("Return Code", ALERTLOG_BASE_ID);
status_id <= GetAlertLogID("Communication Status", ALERTLOG_BASE_ID);
-- Key Hashes
kh1 := (x"F12C31DA", x"E3FE0F3F", x"01F36685", x"446518CA");
kh2 := (x"BC070AC4", x"0BAB5811", x"14EA8D61", x"F669189B");
kh3 := (x"0CEAB0C6", x"FA04B9AD", x"A96EB495", x"4E0EB999");
kh4 := (x"A7EB605C", x"FF4BEF3A", x"3C5E8724", x"CCA0CA67");
Log("Initiating Test", INFO);
Log("Current Time: 0s", INFO);
check_time <= TIME_ZERO;
reset <= '1';
wait until rising_edge(clk);
wait until rising_edge(clk);
reset <= '0';
wait_on_idle;
-- MEM: -
-- ISTATE: -
-- WRITER: -
AffirmIf(status_id,(status and REQUESTED_DEADLINE_MISSED_STATUS) /= REQUESTED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1");
Log("Current Time: 1s", INFO);
check_time <= gen_duration(1,0);
wait until rising_edge(clk);
wait until rising_edge(clk);
wait_on_idle;
AffirmIf(status_id,(status and REQUESTED_DEADLINE_MISSED_STATUS) = REQUESTED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0");
Log("DDS Operation GET_REQUESTED_DEADLINE_MISSED_STATUS (Expected: count 1, change 1)", INFO);
dds := DEFAULT_DDS_READER_TEST;
dds.opcode := GET_REQUESTED_DEADLINE_MISSED_STATUS;
dds.ret_code := RETCODE_OK;
dds.count := 1;
dds.change := 1;
dds.inst := HANDLE_NIL;
start_dds;
wait_on_dds;
wait_on_idle;
AffirmIf(status_id,(status and REQUESTED_DEADLINE_MISSED_STATUS) /= REQUESTED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1");
cc := DEFAULT_CACHE_CHANGE;
cc.serialized_key := FALSE;
cc.kind := ALIVE;
cc.instance := HANDLE_NIL;
cc.payload := gen_payload(HANDLE_NIL,10);
cc.src_timestamp := gen_duration(1,0);
Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Writer 0, Aligned Payload] (ACCEPTED)", INFO);
rtps := DEFAULT_RTPS_READER_TEST;
rtps.opcode := ADD_CACHE_CHANGE;
rtps.cc := cc;
rtps.writer_pos := 0;
rtps.ret_code := OK;
s := to_sample(cc,ALIVE_INSTANCE_STATE);
add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
start_rtps;
wait_on_rtps;
wait_on_idle;
-- MEM: S1
-- ISTATE: ALIVE
-- WRITER: W0
Log("Current Time: 2s", INFO);
check_time <= gen_duration(2,0);
wait until rising_edge(clk);
wait until rising_edge(clk);
wait_on_idle;
AffirmIf(status_id,(status and REQUESTED_DEADLINE_MISSED_STATUS) /= REQUESTED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1");
cc := DEFAULT_CACHE_CHANGE;
cc.serialized_key := FALSE;
cc.kind := ALIVE;
cc.instance := HANDLE_NIL;
cc.payload := gen_payload(HANDLE_NIL,10);
cc.src_timestamp := gen_duration(2,0);
Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Writer 1, Aligned Payload] (ACCEPTED)", INFO);
rtps := DEFAULT_RTPS_READER_TEST;
rtps.opcode := ADD_CACHE_CHANGE;
rtps.cc := cc;
rtps.writer_pos := 1;
rtps.ret_code := OK;
s := to_sample(cc,ALIVE_INSTANCE_STATE);
add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS);
start_rtps;
wait_on_rtps;
wait_on_idle;
-- MEM: S1, S2
-- ISTATE: ALIVE
-- WRITER: W0, W1
Log("Current Time: 3s", INFO);
check_time <= gen_duration(3,0);
wait until rising_edge(clk);
wait until rising_edge(clk);
wait_on_idle;
AffirmIf(status_id,(status and REQUESTED_DEADLINE_MISSED_STATUS) /= REQUESTED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1");
Log("Current Time: 4s", INFO);
check_time <= gen_duration(4,0);
wait until rising_edge(clk);
wait until rising_edge(clk);
wait_on_idle;
AffirmIf(status_id,(status and REQUESTED_DEADLINE_MISSED_STATUS) = REQUESTED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0");
Log("Current Time: 5s", INFO);
check_time <= gen_duration(5,0);
wait until rising_edge(clk);
wait until rising_edge(clk);
wait_on_idle;
AffirmIf(status_id,(status and REQUESTED_DEADLINE_MISSED_STATUS) = REQUESTED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0");
Log("DDS Operation GET_REQUESTED_DEADLINE_MISSED_STATUS (Expected: count 3, change 2)", INFO);
dds := DEFAULT_DDS_READER_TEST;
dds.opcode := GET_REQUESTED_DEADLINE_MISSED_STATUS;
dds.ret_code := RETCODE_OK;
dds.count := 3;
dds.change := 2;
dds.inst := HANDLE_NIL;
start_dds;
wait_on_dds;
wait_on_idle;
AffirmIf(status_id,(status and REQUESTED_DEADLINE_MISSED_STATUS) /= REQUESTED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1");
wait_on_completion;
TranscriptOpen(RESULTS_FILE, APPEND_MODE);
SetTranscriptMirror;
ReportAlerts;
TranscriptClose;
std.env.stop;
wait;
end process;
clock_prc : process
begin
clk <= '0';
wait for 25 ns;
clk <= '1';
wait for 25 ns;
end process;
alert_prc : process(all)
begin
if rising_edge(clk) then
-- TODO
end if;
end process;
dds_prc : process(all)
variable col : COLLECTION_TYPE := DEFAULT_COLLECTION;
begin
if rising_edge(clk) then
dds_done <= '0';
case (dds_stage ) is
when IDLE =>
if (dds_start = '1') then
dds_stage <= START;
else
dds_done <= '1';
end if;
when START =>
if (ack_dds = '1') then
dds_stage <= DONE;
dds_cnt <= 0;
end if;
when DONE =>
if (done_dds = '1') then
AffirmIfEqual(ret_id, return_code_dds, dds.ret_code);
case (dds.ret_code) is
when RETCODE_OK =>
case (dds.opcode) is
when GET_REQUESTED_DEADLINE_MISSED_STATUS =>
dds_stage <= CHECK_DEADLINE;
dds_cnt <= 0;
when others =>
gen_collection(mem, col, dds, INSTANCE_PRESENTATION_QOS, FALSE);
dds_stage <= CHECK_SI;
dds_cnt <= 0;
end case;
when others =>
dds_stage <= IDLE;
end case;
end if;
when CHECK_SI =>
if (si_valid = '1') then
AffirmIfEqual(sstate_id, si_sample_state, col.s(dds_cnt).sstate);
AffirmIfEqual(vstate_id, si_view_state, col.s(dds_cnt).vstate);
AffirmIfEqual(istate_id, si_instance_state, col.s(dds_cnt).istate);
AffirmIfEqual(ts_id, convert_from_double_word(si_source_timestamp), convert_from_double_word(col.s(dds_cnt).ts));
AffirmIfEqual(inst_id, to_unsigned(si_instance_handle), to_unsigned(col.s(dds_cnt).inst));
AffirmIfEqual(pub_id, to_unsigned(si_publication_handle), to_unsigned(HANDLE_NIL));
AffirmIfEqual(dis_gen_cnt_id, si_disposed_generation_count, std_logic_vector(to_unsigned(col.s(dds_cnt).dis_gen_cnt,WORD_WIDTH)));
AffirmIfEqual(no_w_gen_cnt_id, si_no_writers_generation_count, std_logic_vector(to_unsigned(col.s(dds_cnt).no_w_gen_cnt,WORD_WIDTH)));
AffirmIfEqual(srank_id, si_sample_rank, std_logic_vector(to_unsigned(col.s(dds_cnt).srank,WORD_WIDTH)));
AffirmIfEqual(grank_id, si_generation_rank, std_logic_vector(to_unsigned(col.s(dds_cnt).grank,WORD_WIDTH)));
AffirmIfEqual(agrank_id, si_absolute_generation_rank, std_logic_vector(to_unsigned(col.s(dds_cnt).agrank,WORD_WIDTH)));
if (si_valid_data = '1') then
AffirmIf(valid_id, col.s(dds_cnt).data /= EMPTY_TEST_PACKET, "Sample with Data not expected");
dds_stage <= CHECK_DATA;
dds_cnt2 <= 0;
else
AffirmIf(valid_id, col.s(dds_cnt).data = EMPTY_TEST_PACKET, "Sample with Data expected");
if (dds_cnt = col.len-1) then
-- DONE
dds_stage <= WAIT_EOC;
else
dds_cnt <= dds_cnt + 1;
end if;
end if;
end if;
AffirmIf(eoc_id, eoc = '0', "EOC pulled high");
when CHECK_DATA =>
if (valid_out_dds = '1') then
AffirmIfEqual(data_id, data_out_dds, col.s(dds_cnt).data.data(dds_cnt2));
dds_cnt2 <= dds_cnt2 + 1;
if (dds_cnt2 = col.s(dds_cnt).data.length-1) then
AlertIf(data_id, last_word_out_dds /= '1', "Last Word Signal not pulled High", ERROR);
if (dds_cnt = col.len-1) then
-- DONE
dds_stage <= WAIT_EOC;
else
dds_stage <= CHECK_SI;
dds_cnt <= dds_cnt + 1;
end if;
end if;
end if;
when WAIT_EOC =>
if (eoc = '1') then
dds_stage <= IDLE;
end if;
when CHECK_DEADLINE =>
if (valid_out_dds = '1') then
dds_cnt <= dds_cnt + 1;
case (dds_cnt) is
when 0 =>
AffirmIfEqual(data_id, data_out_dds, std_logic_vector(to_unsigned(dds.count,CDR_LONG_WIDTH)));
when 1 =>
AffirmIfEqual(data_id, data_out_dds, std_logic_vector(to_unsigned(dds.change,CDR_LONG_WIDTH)));
when 2 =>
AffirmIfEqual(data_id, data_out_dds, std_logic_vector(dds.inst(0)));
when 3 =>
AffirmIfEqual(data_id, data_out_dds, std_logic_vector(dds.inst(1)));
when 4 =>
AffirmIfEqual(data_id, data_out_dds, std_logic_vector(dds.inst(2)));
when 5 =>
AffirmIfEqual(data_id, data_out_dds, std_logic_vector(dds.inst(3)));
AlertIf(data_id, last_word_out_dds /= '1', "Last Word Signal not pulled High", ERROR);
dds_stage <= IDLE;
when others =>
null;
end case;
end if;
end case;
end if;
-- DEFAULT
start_dds <= '0';
opcode_dds <= NOP;
instance_state_dds <= ANY_INSTANCE_STATE;
view_state_dds <= ANY_VIEW_STATE;
sample_state_dds <= ANY_SAMPLE_STATE;
instance_handle_dds <= HANDLE_NIL;
max_samples_dds <= (others => '0');
get_data_dds <= '0';
ready_out_dds <= '0';
case (dds_stage ) is
when START =>
start_dds <= '1';
opcode_dds <= dds.opcode;
instance_state_dds <= dds.istate;
view_state_dds <= dds.vstate;
sample_state_dds <= dds.sstate;
instance_handle_dds <= dds.inst;
max_samples_dds <= std_logic_vector(to_unsigned(dds.max_samples, WORD_WIDTH));
when CHECK_SI =>
if (si_valid = '1' and si_valid_data = '1') then
get_data_dds <= '1';
end if;
when CHECK_DATA =>
ready_out_dds <= '1';
when CHECK_DEADLINE =>
ready_out_dds <= '1';
when others =>
null;
end case;
end process;
rtps_prc : process(all)
variable stimulus : TEST_PACKET_TYPE := EMPTY_TEST_PACKET;
begin
if rising_edge(clk) then
rtps_done <= '0';
case (rtps_stage) is
when IDLE =>
if (rtps_start = '1') then
rtps_stage <= START;
else
rtps_done <= '1';
end if;
when START =>
if (ack_rtps = '1') then
case (rtps.opcode) is
when ADD_CACHE_CHANGE =>
gen_add_cache_change_dds(rtps.cc, rtps.lifespan, rtps.writer_pos, stimulus);
rtps_stage <= PUSH;
when others =>
rtps_stage <= DONE;
end case;
end if;
when PUSH =>
if (ready_in_rtps = '1') then
rtps_cnt <= rtps_cnt + 1;
if (rtps_cnt = stimulus.length-1) then
rtps_stage <= DONE;
end if;
end if;
when DONE =>
if (done_rtps = '1') then
AffirmIfEqual(ret_id, HISTORY_CACHE_RESPONSE_TYPE'pos(ret_rtps), HISTORY_CACHE_RESPONSE_TYPE'pos(rtps.ret_code));
rtps_stage <= IDLE;
end if;
end case;
end if;
-- DEFAULT
start_rtps <= '0';
opcode_rtps <= NOP;
valid_in_rtps <= '0';
last_word_in_rtps <= '0';
data_in_rtps <= (others => '0');
case (rtps_stage) is
when START =>
start_rtps <= '1';
opcode_rtps <= rtps.opcode;
case (rtps.opcode) is
when REMOVE_WRITER =>
data_in_rtps <= std_logic_vector(to_unsigned(rtps.writer_pos,WORD_WIDTH));
when others =>
null;
end case;
when PUSH =>
valid_in_rtps <= '1';
data_in_rtps <= stimulus.data(rtps_cnt);
last_word_in_rtps <= stimulus.last(rtps_cnt);
when others =>
null;
end case;
end process;
kh_prc : process (all)
variable tmp_key_hash : INSTANCE_HANDLE_TYPE := HANDLE_NIL;
begin
if rising_edge(clk) then
case (kh_stage) is
when IDLE =>
if (start_kh = '1') then
case (opcode_kh) is
when PUSH_DATA =>
kh_stage <= READ_DATA;
kh_cnt <= 0;
kh_data <= EMPTY_TEST_PACKET;
when PUSH_SERIALIZED_KEY =>
kh_stage <= READ_DATA;
kh_cnt <= 0;
kh_data <= EMPTY_TEST_PACKET;
when READ_KEY_HASH =>
kh_stage <= PUSH_KEY_HASH;
kh_cnt <= 0;
when others =>
Alert("Unexpected Key Holder Operation", FAILURE);
end case;
end if;
when READ_DATA =>
if (valid_out_kh = '1') then
kh_data.data(kh_cnt) <= data_out_kh;
kh_data.last(kh_cnt) <= last_word_out_kh;
kh_data.length <= kh_data.length + 1;
kh_cnt <= kh_cnt + 1;
if (last_word_out_kh = '1') then
kh_stage <= IDLE;
end if;
end if;
when PUSH_KEY_HASH =>
if (ready_in_kh = '1') then
kh_cnt <= kh_cnt + 1;
if (kh_cnt = INSTANCE_HANDLE_TYPE'length-1) then
kh_stage <= IDLE;
end if;
end if;
end case;
end if;
-- DEFAULT
ack_kh <= '0';
ready_out_kh <= '0';
valid_in_kh <= '0';
data_in_kh <= (others => '0');
last_word_in_kh <= '0';
case (kh_stage) is
when IDLE =>
if (start_kh = '1') then
ack_kh <= '1';
end if;
when READ_DATA =>
ready_out_kh <= '1';
when PUSH_KEY_HASH =>
valid_in_kh <= '1';
tmp_key_hash := extract_key_hash(kh_data);
data_in_kh <= tmp_key_hash(kh_cnt);
if (kh_cnt = INSTANCE_HANDLE_TYPE'length-1) then
last_word_in_kh <= '1';
end if;
end case;
end process;
watchdog : process
begin
wait for 1 ms;
Alert("Test timeout", FAILURE);
std.env.stop;
end process;
end architecture;

2
src/Tests/Level_0/L0_dds_writer_test2_aik.vhd
View File

@ -10,6 +10,8 @@ use work.user_config.all;
use work.rtps_config_package.all;
use work.rtps_test_package.all;
-- This testbench tests the DDS WAIT_FOR_ACKNOWLEDGEMENTS Operation of the DDS Writer.
entity L0_dds_writer_test2_aik is
end entity;

34
src/Tests/Level_0/L0_dds_writer_test3_aik.vhd
View File

@ -10,6 +10,8 @@ use work.user_config.all;
use work.rtps_config_package.all;
use work.rtps_test_package.all;
-- This testbench tests the Deadline Handling of the DDS Writer, and more specifically the GET_OFFERED_DEADLINE_MISSED_STATUS DDS Operation.
entity L0_dds_writer_test3_aik is
end entity;
@ -264,7 +266,7 @@ begin
wait_on_idle;
-- Stored CC: 0, 0, 0, 0
AffirmIf(status_id,(status and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received 1");
AffirmIf(status_id,(status and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1");
Log("Current Time: 1s", INFO);
check_time <= gen_duration(1,0);
@ -272,7 +274,7 @@ begin
wait until rising_edge(clk);
wait_on_idle;
AffirmIf(status_id,(status and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received 1");
AffirmIf(status_id,(status and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1");
cc := DEFAULT_CACHE_CHANGE;
cc.serialized_key := FALSE;
@ -316,7 +318,7 @@ begin
wait until rising_edge(clk);
wait_on_idle;
AffirmIf(status_id,(status and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received 1");
AffirmIf(status_id,(status and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1");
cc := DEFAULT_CACHE_CHANGE;
cc.serialized_key := FALSE;
@ -342,7 +344,7 @@ begin
wait until rising_edge(clk);
wait_on_idle;
AffirmIf(status_id,(status and OFFERED_DEADLINE_MISSED_STATUS) = OFFERED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received 0");
AffirmIf(status_id,(status and OFFERED_DEADLINE_MISSED_STATUS) = OFFERED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0");
Log("DDS Operation GET_OFFERED_DEADLINE_MISSED_STATUS (Expected: count 1, change 1, Instance 2)", INFO);
dds := DEFAULT_DDS_WRITER_TEST;
@ -355,7 +357,7 @@ begin
wait_on_dds;
wait_on_idle;
AffirmIf(status_id,(status and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received 1");
AffirmIf(status_id,(status and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1");
cc := DEFAULT_CACHE_CHANGE;
cc.serialized_key := FALSE;
@ -381,9 +383,9 @@ begin
wait until rising_edge(clk);
wait_on_idle;
AffirmIf(status_id,(status and OFFERED_DEADLINE_MISSED_STATUS) = OFFERED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received 0");
AffirmIf(status_id,(status and OFFERED_DEADLINE_MISSED_STATUS) = OFFERED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0");
Log("DDS Operation GET_OFFERED_DEADLINE_MISSED_STATUS (Expected: count 3, change 2, Instance 2)", INFO);
Log("DDS Operation GET_OFFERED_DEADLINE_MISSED_STATUS (Expected: count 3, change 2, Instance 1)", INFO);
dds := DEFAULT_DDS_WRITER_TEST;
dds.opcode := GET_OFFERED_DEADLINE_MISSED_STATUS;
dds.ret_code := RETCODE_OK;
@ -394,7 +396,7 @@ begin
wait_on_dds;
wait_on_idle;
AffirmIf(status_id,(status and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received 1");
AffirmIf(status_id,(status and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1");
Log("Current Time: 5s", INFO);
check_time <= gen_duration(5,0);
@ -402,7 +404,7 @@ begin
wait until rising_edge(clk);
wait_on_idle;
AffirmIf(status_id,(status and OFFERED_DEADLINE_MISSED_STATUS) = OFFERED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received 0");
AffirmIf(status_id,(status and OFFERED_DEADLINE_MISSED_STATUS) = OFFERED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0");
Log("Current Time: 6s", INFO);
check_time <= gen_duration(6,0);
@ -410,9 +412,9 @@ begin
wait until rising_edge(clk);
wait_on_idle;
AffirmIf(status_id,(status and OFFERED_DEADLINE_MISSED_STATUS) = OFFERED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received 0");
AffirmIf(status_id,(status and OFFERED_DEADLINE_MISSED_STATUS) = OFFERED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0");
Log("DDS Operation GET_OFFERED_DEADLINE_MISSED_STATUS (Expected: count 3, change 2, Instance 2)", INFO);
Log("DDS Operation GET_OFFERED_DEADLINE_MISSED_STATUS (Expected: count 9, change 6, Instance 1)", INFO);
dds := DEFAULT_DDS_WRITER_TEST;
dds.opcode := GET_OFFERED_DEADLINE_MISSED_STATUS;
dds.ret_code := RETCODE_OK;
@ -423,7 +425,7 @@ begin
wait_on_dds;
wait_on_idle;
AffirmIf(status_id,(status and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received 1");
AffirmIf(status_id,(status and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1");
wait_on_completion;
TranscriptOpen(RESULTS_FILE, APPEND_MODE);
@ -523,13 +525,13 @@ begin
when 1 =>
AffirmIfEqual(data_id, data_out_dds, std_logic_vector(to_unsigned(dds.change,CDR_LONG_WIDTH)));
when 2 =>
AffirmIfEqual(data_id, data_out_dds, std_logic_vector(dds.inst (0)));
AffirmIfEqual(data_id, data_out_dds, std_logic_vector(dds.inst(0)));
when 3 =>
AffirmIfEqual(data_id, data_out_dds, std_logic_vector(dds.inst (1)));
AffirmIfEqual(data_id, data_out_dds, std_logic_vector(dds.inst(1)));
when 4 =>
AffirmIfEqual(data_id, data_out_dds, std_logic_vector(dds.inst (2)));
AffirmIfEqual(data_id, data_out_dds, std_logic_vector(dds.inst(2)));
when 5 =>
AffirmIfEqual(data_id, data_out_dds, std_logic_vector(dds.inst (3)));
AffirmIfEqual(data_id, data_out_dds, std_logic_vector(dds.inst(3)));
AlertIf(data_id, last_word_out_dds /= '1', "Last Word Signal not pulled High", ERROR);
dds_stage <= IDLE;
when others =>

28
src/Tests/Level_0/L0_dds_writer_test3_ain.vhd
View File

@ -10,6 +10,8 @@ use work.user_config.all;
use work.rtps_config_package.all;
use work.rtps_test_package.all;
-- This testbench tests the Deadline Handling of the DDS Writer, and more specifically the GET_OFFERED_DEADLINE_MISSED_STATUS DDS Operation.
entity L0_dds_writer_test3_ain is
end entity;
@ -264,7 +266,7 @@ begin
wait_on_idle;
-- Stored CC: 0, 0, 0, 0
AffirmIf(status_id,(status and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received 1");
AffirmIf(status_id,(status and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1");
Log("Current Time: 1s", INFO);
check_time <= gen_duration(1,0);
@ -272,9 +274,9 @@ begin
wait until rising_edge(clk);
wait_on_idle;
AffirmIf(status_id,(status and OFFERED_DEADLINE_MISSED_STATUS) = OFFERED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received 0");
AffirmIf(status_id,(status and OFFERED_DEADLINE_MISSED_STATUS) = OFFERED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0");
Log("DDS Operation GET_OFFERED_DEADLINE_MISSED_STATUS (Expected: count 3, change 2, Instance 2)", INFO);
Log("DDS Operation GET_OFFERED_DEADLINE_MISSED_STATUS (Expected: count 1, change 1)", INFO);
dds := DEFAULT_DDS_WRITER_TEST;
dds.opcode := GET_OFFERED_DEADLINE_MISSED_STATUS;
dds.ret_code := RETCODE_OK;
@ -284,7 +286,7 @@ begin
wait_on_dds;
wait_on_idle;
AffirmIf(status_id,(status and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received 1");
AffirmIf(status_id,(status and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1");
cc := DEFAULT_CACHE_CHANGE;
cc.serialized_key := FALSE;
@ -310,7 +312,7 @@ begin
wait until rising_edge(clk);
wait_on_idle;
AffirmIf(status_id,(status and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received 1");
AffirmIf(status_id,(status and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1");
Log("Current Time: 3s", INFO);
check_time <= gen_duration(3,0);
@ -318,7 +320,7 @@ begin
wait until rising_edge(clk);
wait_on_idle;
AffirmIf(status_id,(status and OFFERED_DEADLINE_MISSED_STATUS) = OFFERED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received 0");
AffirmIf(status_id,(status and OFFERED_DEADLINE_MISSED_STATUS) = OFFERED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0");
Log("Current Time: 4s", INFO);
check_time <= gen_duration(4,0);
@ -326,9 +328,9 @@ begin
wait until rising_edge(clk);
wait_on_idle;
AffirmIf(status_id,(status and OFFERED_DEADLINE_MISSED_STATUS) = OFFERED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received 0");
AffirmIf(status_id,(status and OFFERED_DEADLINE_MISSED_STATUS) = OFFERED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0");
Log("DDS Operation GET_OFFERED_DEADLINE_MISSED_STATUS (Expected: count 3, change 2, Instance 2)", INFO);
Log("DDS Operation GET_OFFERED_DEADLINE_MISSED_STATUS (Expected: count 3, change 2)", INFO);
dds := DEFAULT_DDS_WRITER_TEST;
dds.opcode := GET_OFFERED_DEADLINE_MISSED_STATUS;
dds.ret_code := RETCODE_OK;
@ -338,7 +340,7 @@ begin
wait_on_dds;
wait_on_idle;
AffirmIf(status_id,(status and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received 1");
AffirmIf(status_id,(status and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1");
wait_on_completion;
TranscriptOpen(RESULTS_FILE, APPEND_MODE);
@ -438,13 +440,13 @@ begin
when 1 =>
AffirmIfEqual(data_id, data_out_dds, std_logic_vector(to_unsigned(dds.change,CDR_LONG_WIDTH)));
when 2 =>
AffirmIfEqual(data_id, data_out_dds, std_logic_vector(dds.inst (0)));
AffirmIfEqual(data_id, data_out_dds, std_logic_vector(dds.inst(0)));
when 3 =>
AffirmIfEqual(data_id, data_out_dds, std_logic_vector(dds.inst (1)));
AffirmIfEqual(data_id, data_out_dds, std_logic_vector(dds.inst(1)));
when 4 =>
AffirmIfEqual(data_id, data_out_dds, std_logic_vector(dds.inst (2)));
AffirmIfEqual(data_id, data_out_dds, std_logic_vector(dds.inst(2)));
when 5 =>
AffirmIfEqual(data_id, data_out_dds, std_logic_vector(dds.inst (3)));
AffirmIfEqual(data_id, data_out_dds, std_logic_vector(dds.inst(3)));
AlertIf(data_id, last_word_out_dds /= '1', "Last Word Signal not pulled High", ERROR);
dds_stage <= IDLE;
when others =>

2
src/Tests/Level_0/L0_dds_writer_test4_aik.vhd
View File

@ -10,6 +10,8 @@ use work.user_config.all;
use work.rtps_config_package.all;
use work.rtps_test_package.all;
-- This testbench tests the Liveliness Handling of the DDS Writer, and more specifically the DDS GET_LIVELINESS_LOST_STATUS, and ASSERT_LIVELINESS Operations.
entity L0_dds_writer_test4_aik is
end entity;

2
src/Tests/Level_0/L0_dds_writer_test5_afk.vhd
View File

@ -10,6 +10,8 @@ use work.user_config.all;
use work.rtps_config_package.all;
use work.rtps_test_package.all;
-- This testbench tests the Lifespan Handling of the DDS Writer.
entity L0_dds_writer_test5_afk is
end entity;

2
src/Tests/Level_0/L0_mem_ctrl_test1.vhd
View File

@ -7,6 +7,8 @@ context osvvm.OsvvmContext;
use work.rtps_test_package.all;
-- This testbench tests the general operation of thr Memory Controler.
entity L0_mem_ctrl_test1 is
end entity;

20
src/Tests/testbench.pro
View File

@ -71,12 +71,14 @@ analyze ../dds_reader.vhd
#analyze Level_0/L0_dds_reader_test1_arznriu.vhd
#analyze Level_0/L0_dds_reader_test1_arzksiu.vhd
#analyze Level_0/L0_dds_reader_test2_arpkriu.vhd
analyze Level_0/L0_dds_reader_test3_arzkriu.vhd
analyze Level_0/L0_dds_reader_test3_arzkrio.vhd
analyze Level_0/L0_dds_reader_test3_arzkrtu.vhd
analyze Level_0/L0_dds_reader_test3_arzkrto.vhd
analyze Level_0/L0_dds_reader_test3_arznriu.vhd
analyze Level_0/L0_dds_reader_test3_arzksto.vhd
#analyze Level_0/L0_dds_reader_test3_arzkriu.vhd
#analyze Level_0/L0_dds_reader_test3_arzkrio.vhd
#analyze Level_0/L0_dds_reader_test3_arzkrtu.vhd
#analyze Level_0/L0_dds_reader_test3_arzkrto.vhd
#analyze Level_0/L0_dds_reader_test3_arznriu.vhd
#analyze Level_0/L0_dds_reader_test3_arzksto.vhd
analyze Level_0/L0_dds_reader_test4_arzkriu.vhd
analyze Level_0/L0_dds_reader_test4_arznriu.vhd
#simulate L0_rtps_handler_test1
#simulate L0_rtps_handler_test2
@ -129,9 +131,11 @@ analyze Level_0/L0_dds_reader_test3_arzksto.vhd
#simulate L0_dds_reader_test1_arznriu
#simulate L0_dds_reader_test1_arzksiu
#simulate L0_dds_reader_test2_arpkriu
simulate L0_dds_reader_test3_arzkriu
#simulate L0_dds_reader_test3_arzkriu
#simulate L0_dds_reader_test3_arzkrio
#simulate L0_dds_reader_test3_arzkrtu
#simulate L0_dds_reader_test3_arzkrto
#simulate L0_dds_reader_test3_arznriu
#simulate L0_dds_reader_test3_arzksto
#simulate L0_dds_reader_test3_arzksto
simulate L0_dds_reader_test4_arzkriu
#simulate L0_dds_reader_test4_arznriu

20
src/dds_reader.vhd
View File

@ -793,7 +793,7 @@ begin
inst_data_next2.status_info(ISI_LIVELINESS_FLAG) <= '0';
else
-- Update Requested Deadline Missed Status
status_sig_next <= status_sig and REQUESTED_DEADLINE_MISSED_STATUS;
status_sig_next <= status_sig or REQUESTED_DEADLINE_MISSED_STATUS;
deadline_miss_cnt_next <= deadline_miss_cnt + 1;
deadline_miss_cnt_change_next <= deadline_miss_cnt_change + 1;
end if;
@ -1430,7 +1430,7 @@ begin
-- Abort Key Hash Generation
abort_kh <= '1';
-- Update Sample Reject Status
status_sig_next <= status_sig and SAMPLE_REJECTED_STATUS;
status_sig_next <= status_sig or SAMPLE_REJECTED_STATUS;
sample_rej_cnt_next <= sample_rej_cnt + 1;
sample_rej_cnt_change_next <= sample_rej_cnt_change + 1;
sample_rej_last_reason_next <= REJECTED_BY_SAMPLES_LIMIT;
@ -1557,7 +1557,7 @@ begin
ret_rtps <= REJECTED;
stage_next <= IDLE;
-- Update Sample Reject Status
status_sig_next <= status_sig and SAMPLE_REJECTED_STATUS;
status_sig_next <= status_sig or SAMPLE_REJECTED_STATUS;
sample_rej_cnt_next <= sample_rej_cnt + 1;
sample_rej_cnt_change_next <= sample_rej_cnt_change + 1;
sample_rej_last_reason_next <= REJECTED_BY_SAMPLES_PER_INSTANCE_LIMIT;
@ -1585,7 +1585,7 @@ begin
ret_rtps <= REJECTED;
stage_next <= IDLE;
-- Update Sample Reject Status
status_sig_next <= status_sig and SAMPLE_REJECTED_STATUS;
status_sig_next <= status_sig or SAMPLE_REJECTED_STATUS;
sample_rej_cnt_next <= sample_rej_cnt + 1;
sample_rej_cnt_change_next <= sample_rej_cnt_change + 1;
sample_rej_last_reason_next <= REJECTED_BY_SAMPLES_LIMIT;
@ -1639,7 +1639,7 @@ begin
ret_rtps <= REJECTED;
stage_next <= IDLE;
-- Update Sample Reject Status
status_sig_next <= status_sig and SAMPLE_REJECTED_STATUS;
status_sig_next <= status_sig or SAMPLE_REJECTED_STATUS;
sample_rej_cnt_next <= sample_rej_cnt + 1;
sample_rej_cnt_change_next <= sample_rej_cnt_change + 1;
sample_rej_last_reason_next <= REJECTED_BY_SAMPLES_LIMIT;
@ -1655,7 +1655,7 @@ begin
-- DONE
stage_next <= IDLE;
-- Update Sample Reject Status
status_sig_next <= status_sig and SAMPLE_REJECTED_STATUS;
status_sig_next <= status_sig or SAMPLE_REJECTED_STATUS;
sample_rej_cnt_next <= sample_rej_cnt + 1;
sample_rej_cnt_change_next <= sample_rej_cnt_change + 1;
sample_rej_last_reason_next <= REJECTED_BY_INSTANCES_LIMIT;
@ -1717,7 +1717,7 @@ begin
-- DONE
stage_next <= IDLE;
-- Update Sample Reject Status
status_sig_next <= status_sig and SAMPLE_REJECTED_STATUS;
status_sig_next <= status_sig or SAMPLE_REJECTED_STATUS;
sample_rej_cnt_next <= sample_rej_cnt + 1;
sample_rej_cnt_change_next <= sample_rej_cnt_change + 1;
sample_rej_last_reason_next <= REJECTED_BY_INSTANCES_LIMIT;
@ -2369,7 +2369,7 @@ begin
end if;
-- Signal Data Available
status_sig_next <= status_sig and DATA_AVAILABLE_STATUS;
status_sig_next <= status_sig or DATA_AVAILABLE_STATUS;
-- Update Lifespan Check Time
if (lifespan /= TIME_INVALID and lifespan < lifespan_time) then
@ -4309,7 +4309,7 @@ begin
-- Last Instance Handle 4/4
when 6 =>
data_out_dds <= deadline_miss_last_inst(3);
valid_out_dds <= '1';
valid_out_dds <= '1';
last_word_out_dds <= '1';
if (ready_out_dds = '1') then
-- Reset
@ -4357,7 +4357,7 @@ begin
cnt_next <= 1;
else
-- Update Requested Deadline Missed Status
status_sig_next <= status_sig and REQUESTED_DEADLINE_MISSED_STATUS;
status_sig_next <= status_sig or REQUESTED_DEADLINE_MISSED_STATUS;
deadline_miss_cnt_next <= deadline_miss_cnt + 1;
deadline_miss_cnt_change_next <= deadline_miss_cnt_change + 1;
deadline_miss_last_inst_next <= inst_data.key_hash;

8
src/rtps_test_package.vhd
View File

@ -283,6 +283,9 @@ package rtps_test_package is
max_samples : natural;
inst : INSTANCE_HANDLE_TYPE;
ret_code : std_logic_vector(RETURN_CODE_WIDTH-1 downto 0);
count : natural;
change : natural;
last_reason : std_logic_vector(CDR_ENUMERATION_WIDTH-1 downto 0);
end record;
constant DEFAULT_DDS_READER_TEST : DDS_READER_TEST_TYPE; -- Deferred to Package Body
@ -664,7 +667,10 @@ package body rtps_test_package is
vstate => ANY_VIEW_STATE,
max_samples => 1,
inst => HANDLE_NIL,
ret_code => RETCODE_OK
ret_code => RETCODE_OK,
count => 0,
change => 0,
last_reason => NOT_REJECTED
);
constant DEFAULT_RTPS_WRITER_TEST : RTPS_WRITER_TEST_TYPE := (