diff --git a/src/mult.vhd b/src/mult.vhd new file mode 100644 index 0000000..83419f1 --- /dev/null +++ b/src/mult.vhd @@ -0,0 +1,52 @@ +-- altera vhdl_input_version vhdl_2008 +-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html) + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity mult is + generic ( + PIPELINE_STAGES : natural := 1; + DATAA_WIDTH : natural; + DATAB_WIDTH : natural; + DATAB_CONST : boolean := FALSE + ); + port ( + clk : in std_logic; + reset : in std_logic; + dataa : in std_logic_vector(DATAA_WIDTH-1 downto 0); + datab : in std_logic_vector(DATAB_WIDTH-1 downto 0); + result : out std_logic_vector(DATAA_WIDTH+DATAB_WIDTH-1 downto 0) + ); +end entity; + +architecture arch of mult is + + type PIPELINE_STAGE_ARRAY is array (0 to PIPELINE_STAGES-1) of std_logic_vector(DATAA_WIDTH+DATAB_WIDTH-1 downto 0); + + signal pipeline : PIPELINE_STAGE_ARRAY := (others => (others => '0')); + +begin + + assert (PIPELINE_STAGES >= 1) report "MULT has to have at least 1 pipeline stage" severity FAILURE; + + result <= pipeline(PIPELINE_STAGES-1); + + sync_prc : process(clk) + begin + if rising_edge(clk) then + if (reset = '1') then + pipeline <= (others => (others => '0')); + else + pipeline(0) <= std_logic_vector(unsigned(dataa) * unsigned(datab)); + if (PIPELINE_STAGES > 1) then + for i in 1 to PIPELINE_STAGES-1 loop + pipeline(i) <= pipeline(i-1); + end loop; + end if; + end if; + end if; + end process; + +end architecture; \ No newline at end of file diff --git a/src/mult_Altera.vhd b/src/mult_Altera.vhd new file mode 100644 index 0000000..1036aef --- /dev/null +++ b/src/mult_Altera.vhd @@ -0,0 +1,58 @@ +-- altera vhdl_input_version vhdl_2008 +-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html) + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +LIBRARY lpm; +USE lpm.all; + +architecture altera of mult is + function gen_hint return string is + begin + if (DATAB_CONST) then + return "INPUT_B_IS_CONSTANT=YES,MAXIMIZE_SPEED=5"; + else + return "MAXIMIZE_SPEED=5"; + end if; + end function; + + component lpm_mult + generic ( + lpm_hint : string; + lpm_pipeline : natural; + lpm_representation : string; + lpm_type : string; + lpm_widtha : natural; + lpm_widthb : natural; + lpm_widthp : natural + ); + port ( + clock : IN std_logic; + dataa : IN std_logic_vector(DATAA_WIDTH-1 DOWNTO 0); + datab : IN std_logic_vector(DATAB_WIDTH-1 DOWNTO 0); + result : OUT std_logic_vector(DATAA_WIDTH+DATAB_WIDTH-1 DOWNTO 0) + ); + END COMPONENT; + +begin + + lpm_mult_component : lpm_mult + generic map ( + lpm_hint => gen_hint, + lpm_pipeline => PIPELINE_STAGES, + lpm_representation => "UNSIGNED", + lpm_type => "LPM_MULT", + lpm_widtha => DATAA_WIDTH, + lpm_widthb => DATAB_WIDTH, + lpm_widthp => DATAA_WIDTH+DATAB_WIDTH + ) + port map ( + clock => clk, + dataa => dataa, + datab => datab, + result => result + ); + +end architecture; \ No newline at end of file diff --git a/src/mult_cfg.vhd b/src/mult_cfg.vhd new file mode 100644 index 0000000..92fdba0 --- /dev/null +++ b/src/mult_cfg.vhd @@ -0,0 +1,7 @@ +-- altera vhdl_input_version vhdl_2008 +-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html) + +configuration mult_cfg of mult is + for altera + end for; +end configuration; diff --git a/src/ros2/Tests/mult_cfg.vhd b/src/ros2/Tests/mult_cfg.vhd new file mode 100644 index 0000000..819d35a --- /dev/null +++ b/src/ros2/Tests/mult_cfg.vhd @@ -0,0 +1,7 @@ +-- altera vhdl_input_version vhdl_2008 +-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html) + +configuration mult_cfg of mult is + for arch + end for; +end configuration; diff --git a/syn/DE10-Nano/top.qsf b/syn/DE10-Nano/top.qsf index 5987a19..2829f63 100644 --- a/syn/DE10-Nano/top.qsf +++ b/syn/DE10-Nano/top.qsf @@ -39,7 +39,7 @@ set_global_assignment -name FAMILY "Cyclone V" set_global_assignment -name DEVICE 5CSEBA6U23I7 -set_global_assignment -name TOP_LEVEL_ENTITY test_top +set_global_assignment -name TOP_LEVEL_ENTITY test7 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.0 set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:33:09 NOVEMBER 02, 2020" set_global_assignment -name LAST_QUARTUS_VERSION "21.1.0 Lite Edition" @@ -47,14 +47,13 @@ set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40" set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100 set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" -set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top -set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top -set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name VHDL_FILE ../test7.vhd -hdl_version VHDL_2008 +set_global_assignment -name VHDL_FILE ../../download/tmp/mult/mult.vhd -hdl_version VHDL_2008 set_global_assignment -name SDC_FILE ../top.sdc set_global_assignment -name VHDL_FILE ../test_top.vhd -hdl_version VHDL_2008 set_global_assignment -name VHDL_FILE ../../src/ros2/Tests/Level_2/L2_Testbench_ROS_Lib2.vhd -hdl_version VHDL_2008 -set_global_assignment -name VHDL_FILE ../../src/ros2/example_interfaces/AddTwoInts_srv_server.vhd -hdl_version VHDL_2008 -set_global_assignment -name VHDL_FILE ../../src/ros2/example_interfaces/AddTwoInts_srv_client.vhd -hdl_version VHDL_2008 +set_global_assignment -name VHDL_FILE ../../src/ros2/example_interfaces/AddTwoInts_ros_srv_server.vhd -hdl_version VHDL_2008 +set_global_assignment -name VHDL_FILE ../../src/ros2/example_interfaces/AddTwoInts_ros_srv_client.vhd -hdl_version VHDL_2008 set_global_assignment -name VHDL_FILE ../../src/ros2/Tests/AddTwoInts.vhd -hdl_version VHDL_2008 set_global_assignment -name VHDL_FILE ../../src/ros2/ros_static_discovery_writer.vhd -hdl_version VHDL_2008 set_global_assignment -name VHDL_FILE ../../src/Avalon_MM_wrapper.vhd -hdl_version VHDL_2008 @@ -103,7 +102,14 @@ set_global_assignment -name VHDL_FILE ../../src/rtps_config_package.vhd -hdl_ver set_global_assignment -name VHDL_FILE ../../src/ros2/dds_user_config.vhd -hdl_version VHDL_2008 set_global_assignment -name VHDL_FILE ../syn_ros_service_config.vhd -hdl_version VHDL_2008 set_global_assignment -name VHDL_FILE ../../src/ros2/example_interfaces/AddTwoInts_package.vhd -hdl_version VHDL_2008 +set_global_assignment -name VHDL_FILE ../../src/ros2/rcl_interfaces/action_msgs/CancelGoal_package.vhd -hdl_version VHDL_2008 +set_global_assignment -name VHDL_FILE ../../src/ros2/rcl_interfaces/action_msgs/GoalStatusArray_package.vhd -hdl_version VHDL_2008 +set_global_assignment -name VHDL_FILE ../../src/ros2/rcl_interfaces/action_msgs/GoalStatus_package.vhd -hdl_version VHDL_2008 +set_global_assignment -name VHDL_FILE ../../src/ros2/rcl_interfaces/action_msgs/GoalInfo_package.vhd -hdl_version VHDL_2008 set_global_assignment -name VHDL_FILE ../../src/ros2/ros_package.vhd -hdl_version VHDL_2008 set_global_assignment -name VHDL_FILE ../../src/rtps_package.vhd -hdl_version VHDL_2008 set_global_assignment -name VHDL_FILE ../../src/math_pkg.vhd -hdl_version VHDL_2008 +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/syn/test7.vhd b/syn/test7.vhd new file mode 100644 index 0000000..c97413a --- /dev/null +++ b/syn/test7.vhd @@ -0,0 +1,57 @@ +-- altera vhdl_input_version vhdl_2008 +-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html) + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.test_package.all; + +-- Test synthesis of array indexing + +entity test7 is + port ( + clk : in std_logic; + reset : in std_logic; + in1 : in std_logic; + in2 : in std_logic; + output : out std_logic_vector(84 downto 0) + ); +end entity; + +architecture arch of test7 is + signal a : std_logic_vector(52 downto 0); + signal b : std_logic_vector(31 downto 0); + signal res : std_logic_vector(84 downto 0); +begin + + output <= res; + + mult_inst : entity work.mult(SYN) + generic map ( + PIPELINE_STAGES => 1, + DATAA_WIDTH => 32, + DATAB_WIDTH => 53, + DATAB_CONST => FALSE + ) + port map ( + clk => clk, + reset => reset, + dataa => a, + datab => b, + result => res + ); + + sync_prc : process(clk) + begin + if rising_edge(clk) then + if (reset = '1') then + a <= (others => '0'); + b <= (others => '0'); + else + a <= a(51 downto 0) & in1; + b <= b(30 downto 0) & in2; + end if; + end if; + end process; +end architecture; \ No newline at end of file