Add vector_FIFO

src/TODO.txt

@@ -437,6 +437,35 @@ DESIGN DECISIONS
     it was decided that the entire server works on this representation to avoid costly conversions. This in 
     effect mitigates the converion problem to the instantiating entity, but a single conversion point could
     be defined that can be used throughout the system.
+    
+*   Initialy the RTPS/DDS Endpoints were designed as one Endpoint per Entity. This allows maximum parallel
+    processing and each entity having the bare minimum HW beased on generics that define the properties of
+    each Endpoint. Nevertheless the amount of Resources needed to synthesize are quite substantial, and there
+    is a (low) limit of how many Endpoints can be instantiated. This limit was reached when trying to 
+    synthesize a ROS action server, which instantiates 9 RTPS and DDS Endpoints.
+    Since the only real difference between the Endpoints is the Memory, we could reuse the main state 
+    machine for all Endpoints and just instantiate different memories.
+    A redesign of all Endpoints was decided, in which multiple Endpoints are simulated by one Entity.
+    The contained Endpoints are addressed in sequential order, meaning that we lose the parrallel processing,
+    but since the RTPS protocol is primarilly used over UDP, there is no difference in performance.
+    Although the ports of the entity could remain single dimension (since only one Endpoint is 
+    reading/writing at a time), we would lose the information of which Endpoint is addressed and would have 
+    to extend the inter-communication shema to relay this information. To avoid this, and to be backwards 
+    compatible (allow to instantiate multiple Endpoint Entities), the dimensions of the ports of the 
+    Endpoints will be extended by the dimension of Endpoinst contained with some exceptions.
+    These exceptions are the all RTPS Output ports, and the read,data_in, and last_word_in RTPS Handler 
+    and DISCOVERY Module ports. This prevents wasting resources on FIFOs, but still conveys addressing 
+    information via the empty signal.
+    This works, because the RTPS Handler and DISCOVERY MODULE write in a multicast fashion (meaning that all
+    addressed Entities become the smae data).
+    
+*   The above decision brings which it another challenge. Sice now the input signals are unbalanced 
+    (empty port is vector, but read, data_in, and last_word_in are not) we need a special kind of FIFO
+    to connect to the input ports of the Endpoints. This special FIFO is called "vector_FIFO" and contains
+    a FIFO for the data, and a FIFO for the write signal, that is internally converted to the empty signal
+    and simulates multiple FIFOs.
+    
+    
 
 BRAINSTORMING
 -------------

src/vector_FIFO.vhd

@@ -0,0 +1,90 @@
+-- altera vhdl_input_version vhdl_2008
+-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity vector_FIFO is
+    generic(
+        FIFO_DEPTH  : natural := 2;
+        DATA_WIDTH  : natural := 32;
+        FIFO_WIDTH  : natural
+    );
+    port
+    (
+        -- SYSTEM
+        clk         : in std_logic;
+        reset       : in std_logic;
+        -- INPUT
+        full        : out std_logic_vector(0 to FIFO_WIDTH-1);
+        write       : in std_logic_vector(0 to FIFO_WIDTH-1);
+        data_in     : in std_logic_vector(DATA_WIDTH-1 downto 0);
+        -- OUTPUT
+        empty       : out std_logic_vector(0 to FIFO_WIDTH-1);
+        read        : in std_logic;
+        data_out    : out std_logic_vector(DATA_WIDTH-1 downto 0)
+    );
+end entity;
+
+architecture arch of vector_FIFO is
+    signal main_full, sup_full, main_empty, sup_empty : std_logic;
+    signal sup_data : std_logic_vector(0 to FIFO_WIDTH-1);
+    
+    -- HACK: Quartus Workaround (Does not support unary or [VHDL 2008])
+    function or_reduce(input : std_logic_vector) return std_logic is
+        variable ret : std_logic := '0';
+    begin
+        for i in 0 to input'length-1 loop
+            ret := ret or input(i);
+        end loop;
+        return ret;
+    end function;
+begin
+    
+    full    <= (others => (main_full or sup_full));
+    empty   <= (not sup_data) or (empty'range => (main_empty or sup_empty));
+    
+    fifo_main_inst : configuration work.FWFT_FIFO_cfg
+        generic map (
+            FIFO_DEPTH  => FIFO_DEPTH,
+            DATA_WIDTH  => DATA_WIDTH
+        )
+        port map (
+            -- SYSTEM
+            reset       => reset,
+            clk         => clk,
+            -- INPUT
+            full        => main_full,
+            write       => or_reduce(write), --or write,
+            data_in     => data_in,
+            -- OUTPUT
+            empty       => main_empty,
+            read        => read,
+            data_out    => data_out,
+            -- MISC
+            free        => open
+        );
+        
+    fifo_sup_inst : configuration work.FWFT_FIFO_cfg
+        generic map (
+            FIFO_DEPTH  => FIFO_DEPTH,
+            DATA_WIDTH  => FIFO_WIDTH
+        )
+        port map (
+            -- SYSTEM
+            reset       => reset,
+            clk         => clk,
+            -- INPUT
+            full        => sup_full,
+            write       => or_reduce(write), --or write,
+            data_in     => write,
+            -- OUTPUT
+            empty       => sup_empty,
+            read        => read,
+            data_out    => sup_data,
+            -- MISC
+            free        => open
+        );
+    
+end architecture;