From 981ca09149e73ebb628a152772d5f19849778b37 Mon Sep 17 00:00:00 2001 From: Greek Date: Tue, 9 Mar 2021 14:56:54 +0100 Subject: [PATCH] Change Type-Dependant Code Interface, and Code refactoring The instantiation of the KEY related entities is moved outside the DDS Endpoints (Currently only changed in DDS Writer). Define new KEY_HOLDER entity that is responsible for all Key related type-specific code. Fix syntax of DDS Writer, and misc code refactoring. --- src/TODO.txt | 15 + .../Level_0/L0_rtps_writer_test1_vbkdp.vhd | 66 +- .../Level_0/L0_rtps_writer_test1_vrkdp.vhd | 66 +- .../Level_0/L0_rtps_writer_test2_vrkdp.vhd | 66 +- .../Level_1/L1_rtps_writer_test1_tbkdp.vhd | 66 +- .../Level_1/L1_rtps_writer_test1_trkdn.vhd | 66 +- .../Level_1/L1_rtps_writer_test1_trkdp.vhd | 66 +- .../Level_1/L1_rtps_writer_test1_vbkdp.vhd | 66 +- .../Level_1/L1_rtps_writer_test1_vrkdn.vhd | 66 +- .../Level_1/L1_rtps_writer_test1_vrkdp.vhd | 66 +- .../Level_1/L1_rtps_writer_test1_vrksp.vhd | 66 +- .../Level_1/L1_rtps_writer_test1_vrndp.vhd | 66 +- .../Level_1/L1_rtps_writer_test2_vrkdn.vhd | 82 +- src/dds_writer.vhd | 947 ++++++++++-------- src/key_hash_generator.vhd | 35 +- src/key_holder.vhd | 24 + src/rtps_config_package.vhd | 2 + src/rtps_reader.vhd | 8 + src/rtps_writer.vhd | 68 +- 19 files changed, 1031 insertions(+), 876 deletions(-) create mode 100644 src/key_holder.vhd diff --git a/src/TODO.txt b/src/TODO.txt index 7f32f27..4b640c8 100644 --- a/src/TODO.txt +++ b/src/TODO.txt @@ -267,6 +267,21 @@ DESIGN DECISIONS requested until reception). This means that during the ACKNACK response delay, we can just parse the new request bitmap and overwrite the last old one. +* Since all code related to encoding/decoding the DATA stream is dependent on the IDL type + specification, we have to encapsule that code separately and link them as necessary. Two such + dynamic Entities are defined: KEY_HOLDER, and _WRAPPER. + The KEY_HOLDER Entity contains a Byte-Wide internal memory (In size equal to the maximum key size), + that can be filled with both PLAIN_CDR/PL_CDR DATA Streams, and PLAIN_CDR/PL_CDR Serialized Key + Streams. The Entity allows outputting the memory contents (Key) either in a KEY_HASH format (needs + to instantiate a MD5 calculator), or in Serialized Key Format. The Entity uses the start/opcode/ack + interface for operations (similar to the RTPS/DDS Interface). + The _WRAPPER entity has all type-components linked to ports and latched in registers. In + output mode the entity is able to fill the registers with a PLAIN_CDR/PL_CDR Data Stream, and in + input mode the registers are filled directly from the input ports and the Entity is able to produce + a PLAIN_CDR/PL_CDR Data Stream from the registers. + Due to the type-specific nature of the entities, those are not instantiated inside the DDS Endpoints, + but will be instantiated in a wrapper and linked through port mapping with the DDS Enspoints. + PROTOCOL UNCOMPLIANCE ===================== * Partition QoS diff --git a/src/Tests/Level_0/L0_rtps_writer_test1_vbkdp.vhd b/src/Tests/Level_0/L0_rtps_writer_test1_vbkdp.vhd index a02e4b8..50b5df7 100644 --- a/src/Tests/Level_0/L0_rtps_writer_test1_vbkdp.vhd +++ b/src/Tests/Level_0/L0_rtps_writer_test1_vbkdp.vhd @@ -85,39 +85,39 @@ begin MAX_REMOTE_ENDPOINTS => MAX_REMOTE_ENDPOINTS ) port map ( - clk => clk, - reset => reset, - time => TIME_ZERO, - empty_user => '1', - rd_user => open, - data_in_user => (others => '0'), - last_word_in_user => '0', - empty_meta => empty_meta or packet_sent, - rd_meta => rd_meta, - data_in_meta => data_in_meta, - last_word_in_meta => last_word_in_meta, - alive_sig => open, - wr_rtps => open, - full_rtps => '0', - last_word_out_rtps => open, - data_out_rtps => open, - assert_liveliness => '0', - data_available => '0', - start_hc => start_hc, - opcode_hc => open, - ack_hc => '0', - seq_nr_hc => open, - done_hc => '0', - ret_hc => ERROR, - get_data_hc => open, - data_in_hc => (others => '0'), - valid_in_hc => '0', - ready_in_hc => open, - last_word_in_hc => '0', - cc_instance_handle => HANDLE_NIL, - cc_kind => ALIVE, - cc_source_timestamp => TIME_INVALID, - cc_seq_nr => SEQUENCENUMBER_UNKNOWN + clk => clk, + reset => reset, + time => TIME_ZERO, + empty_user => '1', + rd_user => open, + data_in_user => (others => '0'), + last_word_in_user => '0', + empty_meta => empty_meta or packet_sent, + rd_meta => rd_meta, + data_in_meta => data_in_meta, + last_word_in_meta => last_word_in_meta, + alive_sig => open, + wr_rtps => open, + full_rtps => '0', + last_word_out_rtps => open, + data_out_rtps => open, + liveliness_assertion => '0', + data_available => '0', + start_hc => start_hc, + opcode_hc => open, + ack_hc => '0', + seq_nr_hc => open, + done_hc => '0', + ret_hc => ERROR, + get_data_hc => open, + data_in_hc => (others => '0'), + valid_in_hc => '0', + ready_in_hc => open, + last_word_in_hc => '0', + cc_instance_handle => HANDLE_NIL, + cc_kind => ALIVE, + cc_source_timestamp => TIME_INVALID, + cc_seq_nr => SEQUENCENUMBER_UNKNOWN ); stimulus_prc : process diff --git a/src/Tests/Level_0/L0_rtps_writer_test1_vrkdp.vhd b/src/Tests/Level_0/L0_rtps_writer_test1_vrkdp.vhd index 9d43d23..6858af2 100644 --- a/src/Tests/Level_0/L0_rtps_writer_test1_vrkdp.vhd +++ b/src/Tests/Level_0/L0_rtps_writer_test1_vrkdp.vhd @@ -85,39 +85,39 @@ begin MAX_REMOTE_ENDPOINTS => MAX_REMOTE_ENDPOINTS ) port map ( - clk => clk, - reset => reset, - time => TIME_ZERO, - empty_user => '1', - rd_user => open, - data_in_user => (others => '0'), - last_word_in_user => '0', - empty_meta => empty_meta or packet_sent, - rd_meta => rd_meta, - data_in_meta => data_in_meta, - last_word_in_meta => last_word_in_meta, - alive_sig => open, - wr_rtps => open, - full_rtps => '0', - last_word_out_rtps => open, - data_out_rtps => open, - assert_liveliness => '0', - data_available => '0', - start_hc => start_hc, - opcode_hc => open, - ack_hc => '0', - seq_nr_hc => open, - done_hc => '0', - ret_hc => ERROR, - get_data_hc => open, - data_in_hc => (others => '0'), - valid_in_hc => '0', - ready_in_hc => open, - last_word_in_hc => '0', - cc_instance_handle => HANDLE_NIL, - cc_kind => ALIVE, - cc_source_timestamp => TIME_INVALID, - cc_seq_nr => SEQUENCENUMBER_UNKNOWN + clk => clk, + reset => reset, + time => TIME_ZERO, + empty_user => '1', + rd_user => open, + data_in_user => (others => '0'), + last_word_in_user => '0', + empty_meta => empty_meta or packet_sent, + rd_meta => rd_meta, + data_in_meta => data_in_meta, + last_word_in_meta => last_word_in_meta, + alive_sig => open, + wr_rtps => open, + full_rtps => '0', + last_word_out_rtps => open, + data_out_rtps => open, + liveliness_assertion => '0', + data_available => '0', + start_hc => start_hc, + opcode_hc => open, + ack_hc => '0', + seq_nr_hc => open, + done_hc => '0', + ret_hc => ERROR, + get_data_hc => open, + data_in_hc => (others => '0'), + valid_in_hc => '0', + ready_in_hc => open, + last_word_in_hc => '0', + cc_instance_handle => HANDLE_NIL, + cc_kind => ALIVE, + cc_source_timestamp => TIME_INVALID, + cc_seq_nr => SEQUENCENUMBER_UNKNOWN ); stimulus_prc : process diff --git a/src/Tests/Level_0/L0_rtps_writer_test2_vrkdp.vhd b/src/Tests/Level_0/L0_rtps_writer_test2_vrkdp.vhd index a68e879..033c254 100644 --- a/src/Tests/Level_0/L0_rtps_writer_test2_vrkdp.vhd +++ b/src/Tests/Level_0/L0_rtps_writer_test2_vrkdp.vhd @@ -69,39 +69,39 @@ begin MAX_REMOTE_ENDPOINTS => MAX_REMOTE_ENDPOINTS ) port map ( - clk => clk, - reset => reset, - time => test_time, - empty_user => empty_user or packet_sent_user, - rd_user => rd_user, - data_in_user => data_in_user, - last_word_in_user => last_word_in_user, - empty_meta => empty_meta or packet_sent_meta, - rd_meta => rd_meta, - data_in_meta => data_in_meta, - last_word_in_meta => last_word_in_meta, - alive_sig => open, - wr_rtps => open, - full_rtps => '0', - last_word_out_rtps => open, - data_out_rtps => open, - assert_liveliness => '0', - data_available => '0', - start_hc => start_hc, - opcode_hc => open, - ack_hc => '0', - seq_nr_hc => open, - done_hc => '0', - ret_hc => ERROR, - get_data_hc => open, - data_in_hc => (others => '0'), - valid_in_hc => '0', - ready_in_hc => open, - last_word_in_hc => '0', - cc_instance_handle => HANDLE_NIL, - cc_kind => ALIVE, - cc_source_timestamp => TIME_INVALID, - cc_seq_nr => SEQUENCENUMBER_UNKNOWN + clk => clk, + reset => reset, + time => test_time, + empty_user => empty_user or packet_sent_user, + rd_user => rd_user, + data_in_user => data_in_user, + last_word_in_user => last_word_in_user, + empty_meta => empty_meta or packet_sent_meta, + rd_meta => rd_meta, + data_in_meta => data_in_meta, + last_word_in_meta => last_word_in_meta, + alive_sig => open, + wr_rtps => open, + full_rtps => '0', + last_word_out_rtps => open, + data_out_rtps => open, + liveliness_assertion => '0', + data_available => '0', + start_hc => start_hc, + opcode_hc => open, + ack_hc => '0', + seq_nr_hc => open, + done_hc => '0', + ret_hc => ERROR, + get_data_hc => open, + data_in_hc => (others => '0'), + valid_in_hc => '0', + ready_in_hc => open, + last_word_in_hc => '0', + cc_instance_handle => HANDLE_NIL, + cc_kind => ALIVE, + cc_source_timestamp => TIME_INVALID, + cc_seq_nr => SEQUENCENUMBER_UNKNOWN ); stimulus_prc : process diff --git a/src/Tests/Level_1/L1_rtps_writer_test1_tbkdp.vhd b/src/Tests/Level_1/L1_rtps_writer_test1_tbkdp.vhd index 653bfd1..e392486 100644 --- a/src/Tests/Level_1/L1_rtps_writer_test1_tbkdp.vhd +++ b/src/Tests/Level_1/L1_rtps_writer_test1_tbkdp.vhd @@ -92,39 +92,39 @@ begin MAX_REMOTE_ENDPOINTS => MAX_REMOTE_ENDPOINTS ) port map ( - clk => clk, - reset => reset, - time => test_time, - empty_user => empty_user or packet_sent_user, - rd_user => rd_user, - data_in_user => data_in_user, - last_word_in_user => last_word_in_user, - empty_meta => empty_meta or packet_sent_meta, - rd_meta => rd_meta, - data_in_meta => data_in_meta, - last_word_in_meta => last_word_in_meta, - alive_sig => open, - wr_rtps => fifo_wr, - full_rtps => fifo_full, - last_word_out_rtps => fifo_in(WORD_WIDTH), - data_out_rtps => fifo_in(WORD_WIDTH-1 downto 0), - assert_liveliness => '0', - data_available => data_available, - start_hc => start_hc, - opcode_hc => opcode_hc, - ack_hc => ack_hc, - seq_nr_hc => seq_nr_hc, - done_hc => done_hc, - ret_hc => ret_hc, - get_data_hc => get_data_hc, - data_in_hc => data_in_hc, - valid_in_hc => valid_in_hc, - ready_in_hc => ready_in_hc, - last_word_in_hc => last_word_in_hc, - cc_instance_handle => cc_instance_handle, - cc_kind => cc_kind, - cc_source_timestamp => cc_source_timestamp, - cc_seq_nr => cc_seq_nr + clk => clk, + reset => reset, + time => test_time, + empty_user => empty_user or packet_sent_user, + rd_user => rd_user, + data_in_user => data_in_user, + last_word_in_user => last_word_in_user, + empty_meta => empty_meta or packet_sent_meta, + rd_meta => rd_meta, + data_in_meta => data_in_meta, + last_word_in_meta => last_word_in_meta, + alive_sig => open, + wr_rtps => fifo_wr, + full_rtps => fifo_full, + last_word_out_rtps => fifo_in(WORD_WIDTH), + data_out_rtps => fifo_in(WORD_WIDTH-1 downto 0), + liveliness_assertion => '0', + data_available => data_available, + start_hc => start_hc, + opcode_hc => opcode_hc, + ack_hc => ack_hc, + seq_nr_hc => seq_nr_hc, + done_hc => done_hc, + ret_hc => ret_hc, + get_data_hc => get_data_hc, + data_in_hc => data_in_hc, + valid_in_hc => valid_in_hc, + ready_in_hc => ready_in_hc, + last_word_in_hc => last_word_in_hc, + cc_instance_handle => cc_instance_handle, + cc_kind => cc_kind, + cc_source_timestamp => cc_source_timestamp, + cc_seq_nr => cc_seq_nr ); fifo_inst : entity work.FWFT_FIFO(arch) diff --git a/src/Tests/Level_1/L1_rtps_writer_test1_trkdn.vhd b/src/Tests/Level_1/L1_rtps_writer_test1_trkdn.vhd index 2bf3b37..f86a86d 100644 --- a/src/Tests/Level_1/L1_rtps_writer_test1_trkdn.vhd +++ b/src/Tests/Level_1/L1_rtps_writer_test1_trkdn.vhd @@ -92,39 +92,39 @@ begin MAX_REMOTE_ENDPOINTS => MAX_REMOTE_ENDPOINTS ) port map ( - clk => clk, - reset => reset, - time => test_time, - empty_user => empty_user or packet_sent_user, - rd_user => rd_user, - data_in_user => data_in_user, - last_word_in_user => last_word_in_user, - empty_meta => empty_meta or packet_sent_meta, - rd_meta => rd_meta, - data_in_meta => data_in_meta, - last_word_in_meta => last_word_in_meta, - alive_sig => open, - wr_rtps => fifo_wr, - full_rtps => fifo_full, - last_word_out_rtps => fifo_in(WORD_WIDTH), - data_out_rtps => fifo_in(WORD_WIDTH-1 downto 0), - assert_liveliness => '0', - data_available => data_available, - start_hc => start_hc, - opcode_hc => opcode_hc, - ack_hc => ack_hc, - seq_nr_hc => seq_nr_hc, - done_hc => done_hc, - ret_hc => ret_hc, - get_data_hc => get_data_hc, - data_in_hc => data_in_hc, - valid_in_hc => valid_in_hc, - ready_in_hc => ready_in_hc, - last_word_in_hc => last_word_in_hc, - cc_instance_handle => cc_instance_handle, - cc_kind => cc_kind, - cc_source_timestamp => cc_source_timestamp, - cc_seq_nr => cc_seq_nr + clk => clk, + reset => reset, + time => test_time, + empty_user => empty_user or packet_sent_user, + rd_user => rd_user, + data_in_user => data_in_user, + last_word_in_user => last_word_in_user, + empty_meta => empty_meta or packet_sent_meta, + rd_meta => rd_meta, + data_in_meta => data_in_meta, + last_word_in_meta => last_word_in_meta, + alive_sig => open, + wr_rtps => fifo_wr, + full_rtps => fifo_full, + last_word_out_rtps => fifo_in(WORD_WIDTH), + data_out_rtps => fifo_in(WORD_WIDTH-1 downto 0), + liveliness_assertion => '0', + data_available => data_available, + start_hc => start_hc, + opcode_hc => opcode_hc, + ack_hc => ack_hc, + seq_nr_hc => seq_nr_hc, + done_hc => done_hc, + ret_hc => ret_hc, + get_data_hc => get_data_hc, + data_in_hc => data_in_hc, + valid_in_hc => valid_in_hc, + ready_in_hc => ready_in_hc, + last_word_in_hc => last_word_in_hc, + cc_instance_handle => cc_instance_handle, + cc_kind => cc_kind, + cc_source_timestamp => cc_source_timestamp, + cc_seq_nr => cc_seq_nr ); fifo_inst : entity work.FWFT_FIFO(arch) diff --git a/src/Tests/Level_1/L1_rtps_writer_test1_trkdp.vhd b/src/Tests/Level_1/L1_rtps_writer_test1_trkdp.vhd index 414883f..1c8a8a2 100644 --- a/src/Tests/Level_1/L1_rtps_writer_test1_trkdp.vhd +++ b/src/Tests/Level_1/L1_rtps_writer_test1_trkdp.vhd @@ -92,39 +92,39 @@ begin MAX_REMOTE_ENDPOINTS => MAX_REMOTE_ENDPOINTS ) port map ( - clk => clk, - reset => reset, - time => test_time, - empty_user => empty_user or packet_sent_user, - rd_user => rd_user, - data_in_user => data_in_user, - last_word_in_user => last_word_in_user, - empty_meta => empty_meta or packet_sent_meta, - rd_meta => rd_meta, - data_in_meta => data_in_meta, - last_word_in_meta => last_word_in_meta, - alive_sig => open, - wr_rtps => fifo_wr, - full_rtps => fifo_full, - last_word_out_rtps => fifo_in(WORD_WIDTH), - data_out_rtps => fifo_in(WORD_WIDTH-1 downto 0), - assert_liveliness => '0', - data_available => data_available, - start_hc => start_hc, - opcode_hc => opcode_hc, - ack_hc => ack_hc, - seq_nr_hc => seq_nr_hc, - done_hc => done_hc, - ret_hc => ret_hc, - get_data_hc => get_data_hc, - data_in_hc => data_in_hc, - valid_in_hc => valid_in_hc, - ready_in_hc => ready_in_hc, - last_word_in_hc => last_word_in_hc, - cc_instance_handle => cc_instance_handle, - cc_kind => cc_kind, - cc_source_timestamp => cc_source_timestamp, - cc_seq_nr => cc_seq_nr + clk => clk, + reset => reset, + time => test_time, + empty_user => empty_user or packet_sent_user, + rd_user => rd_user, + data_in_user => data_in_user, + last_word_in_user => last_word_in_user, + empty_meta => empty_meta or packet_sent_meta, + rd_meta => rd_meta, + data_in_meta => data_in_meta, + last_word_in_meta => last_word_in_meta, + alive_sig => open, + wr_rtps => fifo_wr, + full_rtps => fifo_full, + last_word_out_rtps => fifo_in(WORD_WIDTH), + data_out_rtps => fifo_in(WORD_WIDTH-1 downto 0), + liveliness_assertion => '0', + data_available => data_available, + start_hc => start_hc, + opcode_hc => opcode_hc, + ack_hc => ack_hc, + seq_nr_hc => seq_nr_hc, + done_hc => done_hc, + ret_hc => ret_hc, + get_data_hc => get_data_hc, + data_in_hc => data_in_hc, + valid_in_hc => valid_in_hc, + ready_in_hc => ready_in_hc, + last_word_in_hc => last_word_in_hc, + cc_instance_handle => cc_instance_handle, + cc_kind => cc_kind, + cc_source_timestamp => cc_source_timestamp, + cc_seq_nr => cc_seq_nr ); fifo_inst : entity work.FWFT_FIFO(arch) diff --git a/src/Tests/Level_1/L1_rtps_writer_test1_vbkdp.vhd b/src/Tests/Level_1/L1_rtps_writer_test1_vbkdp.vhd index 2eb570a..2f8ecad 100644 --- a/src/Tests/Level_1/L1_rtps_writer_test1_vbkdp.vhd +++ b/src/Tests/Level_1/L1_rtps_writer_test1_vbkdp.vhd @@ -92,39 +92,39 @@ begin MAX_REMOTE_ENDPOINTS => MAX_REMOTE_ENDPOINTS ) port map ( - clk => clk, - reset => reset, - time => test_time, - empty_user => empty_user or packet_sent_user, - rd_user => rd_user, - data_in_user => data_in_user, - last_word_in_user => last_word_in_user, - empty_meta => empty_meta or packet_sent_meta, - rd_meta => rd_meta, - data_in_meta => data_in_meta, - last_word_in_meta => last_word_in_meta, - alive_sig => open, - wr_rtps => fifo_wr, - full_rtps => fifo_full, - last_word_out_rtps => fifo_in(WORD_WIDTH), - data_out_rtps => fifo_in(WORD_WIDTH-1 downto 0), - assert_liveliness => '0', - data_available => data_available, - start_hc => start_hc, - opcode_hc => opcode_hc, - ack_hc => ack_hc, - seq_nr_hc => seq_nr_hc, - done_hc => done_hc, - ret_hc => ret_hc, - get_data_hc => get_data_hc, - data_in_hc => data_in_hc, - valid_in_hc => valid_in_hc, - ready_in_hc => ready_in_hc, - last_word_in_hc => last_word_in_hc, - cc_instance_handle => cc_instance_handle, - cc_kind => cc_kind, - cc_source_timestamp => cc_source_timestamp, - cc_seq_nr => cc_seq_nr + clk => clk, + reset => reset, + time => test_time, + empty_user => empty_user or packet_sent_user, + rd_user => rd_user, + data_in_user => data_in_user, + last_word_in_user => last_word_in_user, + empty_meta => empty_meta or packet_sent_meta, + rd_meta => rd_meta, + data_in_meta => data_in_meta, + last_word_in_meta => last_word_in_meta, + alive_sig => open, + wr_rtps => fifo_wr, + full_rtps => fifo_full, + last_word_out_rtps => fifo_in(WORD_WIDTH), + data_out_rtps => fifo_in(WORD_WIDTH-1 downto 0), + liveliness_assertion => '0', + data_available => data_available, + start_hc => start_hc, + opcode_hc => opcode_hc, + ack_hc => ack_hc, + seq_nr_hc => seq_nr_hc, + done_hc => done_hc, + ret_hc => ret_hc, + get_data_hc => get_data_hc, + data_in_hc => data_in_hc, + valid_in_hc => valid_in_hc, + ready_in_hc => ready_in_hc, + last_word_in_hc => last_word_in_hc, + cc_instance_handle => cc_instance_handle, + cc_kind => cc_kind, + cc_source_timestamp => cc_source_timestamp, + cc_seq_nr => cc_seq_nr ); fifo_inst : entity work.FWFT_FIFO(arch) diff --git a/src/Tests/Level_1/L1_rtps_writer_test1_vrkdn.vhd b/src/Tests/Level_1/L1_rtps_writer_test1_vrkdn.vhd index 6a742c6..ae7f1b0 100644 --- a/src/Tests/Level_1/L1_rtps_writer_test1_vrkdn.vhd +++ b/src/Tests/Level_1/L1_rtps_writer_test1_vrkdn.vhd @@ -92,39 +92,39 @@ begin MAX_REMOTE_ENDPOINTS => MAX_REMOTE_ENDPOINTS ) port map ( - clk => clk, - reset => reset, - time => test_time, - empty_user => empty_user or packet_sent_user, - rd_user => rd_user, - data_in_user => data_in_user, - last_word_in_user => last_word_in_user, - empty_meta => empty_meta or packet_sent_meta, - rd_meta => rd_meta, - data_in_meta => data_in_meta, - last_word_in_meta => last_word_in_meta, - alive_sig => open, - wr_rtps => fifo_wr, - full_rtps => fifo_full, - last_word_out_rtps => fifo_in(WORD_WIDTH), - data_out_rtps => fifo_in(WORD_WIDTH-1 downto 0), - assert_liveliness => '0', - data_available => data_available, - start_hc => start_hc, - opcode_hc => opcode_hc, - ack_hc => ack_hc, - seq_nr_hc => seq_nr_hc, - done_hc => done_hc, - ret_hc => ret_hc, - get_data_hc => get_data_hc, - data_in_hc => data_in_hc, - valid_in_hc => valid_in_hc, - ready_in_hc => ready_in_hc, - last_word_in_hc => last_word_in_hc, - cc_instance_handle => cc_instance_handle, - cc_kind => cc_kind, - cc_source_timestamp => cc_source_timestamp, - cc_seq_nr => cc_seq_nr + clk => clk, + reset => reset, + time => test_time, + empty_user => empty_user or packet_sent_user, + rd_user => rd_user, + data_in_user => data_in_user, + last_word_in_user => last_word_in_user, + empty_meta => empty_meta or packet_sent_meta, + rd_meta => rd_meta, + data_in_meta => data_in_meta, + last_word_in_meta => last_word_in_meta, + alive_sig => open, + wr_rtps => fifo_wr, + full_rtps => fifo_full, + last_word_out_rtps => fifo_in(WORD_WIDTH), + data_out_rtps => fifo_in(WORD_WIDTH-1 downto 0), + liveliness_assertion => '0', + data_available => data_available, + start_hc => start_hc, + opcode_hc => opcode_hc, + ack_hc => ack_hc, + seq_nr_hc => seq_nr_hc, + done_hc => done_hc, + ret_hc => ret_hc, + get_data_hc => get_data_hc, + data_in_hc => data_in_hc, + valid_in_hc => valid_in_hc, + ready_in_hc => ready_in_hc, + last_word_in_hc => last_word_in_hc, + cc_instance_handle => cc_instance_handle, + cc_kind => cc_kind, + cc_source_timestamp => cc_source_timestamp, + cc_seq_nr => cc_seq_nr ); fifo_inst : entity work.FWFT_FIFO(arch) diff --git a/src/Tests/Level_1/L1_rtps_writer_test1_vrkdp.vhd b/src/Tests/Level_1/L1_rtps_writer_test1_vrkdp.vhd index 26d546d..f757ebd 100644 --- a/src/Tests/Level_1/L1_rtps_writer_test1_vrkdp.vhd +++ b/src/Tests/Level_1/L1_rtps_writer_test1_vrkdp.vhd @@ -92,39 +92,39 @@ begin MAX_REMOTE_ENDPOINTS => MAX_REMOTE_ENDPOINTS ) port map ( - clk => clk, - reset => reset, - time => test_time, - empty_user => empty_user or packet_sent_user, - rd_user => rd_user, - data_in_user => data_in_user, - last_word_in_user => last_word_in_user, - empty_meta => empty_meta or packet_sent_meta, - rd_meta => rd_meta, - data_in_meta => data_in_meta, - last_word_in_meta => last_word_in_meta, - alive_sig => open, - wr_rtps => fifo_wr, - full_rtps => fifo_full, - last_word_out_rtps => fifo_in(WORD_WIDTH), - data_out_rtps => fifo_in(WORD_WIDTH-1 downto 0), - assert_liveliness => '0', - data_available => data_available, - start_hc => start_hc, - opcode_hc => opcode_hc, - ack_hc => ack_hc, - seq_nr_hc => seq_nr_hc, - done_hc => done_hc, - ret_hc => ret_hc, - get_data_hc => get_data_hc, - data_in_hc => data_in_hc, - valid_in_hc => valid_in_hc, - ready_in_hc => ready_in_hc, - last_word_in_hc => last_word_in_hc, - cc_instance_handle => cc_instance_handle, - cc_kind => cc_kind, - cc_source_timestamp => cc_source_timestamp, - cc_seq_nr => cc_seq_nr + clk => clk, + reset => reset, + time => test_time, + empty_user => empty_user or packet_sent_user, + rd_user => rd_user, + data_in_user => data_in_user, + last_word_in_user => last_word_in_user, + empty_meta => empty_meta or packet_sent_meta, + rd_meta => rd_meta, + data_in_meta => data_in_meta, + last_word_in_meta => last_word_in_meta, + alive_sig => open, + wr_rtps => fifo_wr, + full_rtps => fifo_full, + last_word_out_rtps => fifo_in(WORD_WIDTH), + data_out_rtps => fifo_in(WORD_WIDTH-1 downto 0), + liveliness_assertion => '0', + data_available => data_available, + start_hc => start_hc, + opcode_hc => opcode_hc, + ack_hc => ack_hc, + seq_nr_hc => seq_nr_hc, + done_hc => done_hc, + ret_hc => ret_hc, + get_data_hc => get_data_hc, + data_in_hc => data_in_hc, + valid_in_hc => valid_in_hc, + ready_in_hc => ready_in_hc, + last_word_in_hc => last_word_in_hc, + cc_instance_handle => cc_instance_handle, + cc_kind => cc_kind, + cc_source_timestamp => cc_source_timestamp, + cc_seq_nr => cc_seq_nr ); fifo_inst : entity work.FWFT_FIFO(arch) diff --git a/src/Tests/Level_1/L1_rtps_writer_test1_vrksp.vhd b/src/Tests/Level_1/L1_rtps_writer_test1_vrksp.vhd index 2617892..ad928e5 100644 --- a/src/Tests/Level_1/L1_rtps_writer_test1_vrksp.vhd +++ b/src/Tests/Level_1/L1_rtps_writer_test1_vrksp.vhd @@ -92,39 +92,39 @@ begin MAX_REMOTE_ENDPOINTS => MAX_REMOTE_ENDPOINTS ) port map ( - clk => clk, - reset => reset, - time => test_time, - empty_user => empty_user or packet_sent_user, - rd_user => rd_user, - data_in_user => data_in_user, - last_word_in_user => last_word_in_user, - empty_meta => empty_meta or packet_sent_meta, - rd_meta => rd_meta, - data_in_meta => data_in_meta, - last_word_in_meta => last_word_in_meta, - alive_sig => open, - wr_rtps => fifo_wr, - full_rtps => fifo_full, - last_word_out_rtps => fifo_in(WORD_WIDTH), - data_out_rtps => fifo_in(WORD_WIDTH-1 downto 0), - assert_liveliness => '0', - data_available => data_available, - start_hc => start_hc, - opcode_hc => opcode_hc, - ack_hc => ack_hc, - seq_nr_hc => seq_nr_hc, - done_hc => done_hc, - ret_hc => ret_hc, - get_data_hc => get_data_hc, - data_in_hc => data_in_hc, - valid_in_hc => valid_in_hc, - ready_in_hc => ready_in_hc, - last_word_in_hc => last_word_in_hc, - cc_instance_handle => cc_instance_handle, - cc_kind => cc_kind, - cc_source_timestamp => cc_source_timestamp, - cc_seq_nr => cc_seq_nr + clk => clk, + reset => reset, + time => test_time, + empty_user => empty_user or packet_sent_user, + rd_user => rd_user, + data_in_user => data_in_user, + last_word_in_user => last_word_in_user, + empty_meta => empty_meta or packet_sent_meta, + rd_meta => rd_meta, + data_in_meta => data_in_meta, + last_word_in_meta => last_word_in_meta, + alive_sig => open, + wr_rtps => fifo_wr, + full_rtps => fifo_full, + last_word_out_rtps => fifo_in(WORD_WIDTH), + data_out_rtps => fifo_in(WORD_WIDTH-1 downto 0), + liveliness_assertion => '0', + data_available => data_available, + start_hc => start_hc, + opcode_hc => opcode_hc, + ack_hc => ack_hc, + seq_nr_hc => seq_nr_hc, + done_hc => done_hc, + ret_hc => ret_hc, + get_data_hc => get_data_hc, + data_in_hc => data_in_hc, + valid_in_hc => valid_in_hc, + ready_in_hc => ready_in_hc, + last_word_in_hc => last_word_in_hc, + cc_instance_handle => cc_instance_handle, + cc_kind => cc_kind, + cc_source_timestamp => cc_source_timestamp, + cc_seq_nr => cc_seq_nr ); fifo_inst : entity work.FWFT_FIFO(arch) diff --git a/src/Tests/Level_1/L1_rtps_writer_test1_vrndp.vhd b/src/Tests/Level_1/L1_rtps_writer_test1_vrndp.vhd index 15b6e34..6db3115 100644 --- a/src/Tests/Level_1/L1_rtps_writer_test1_vrndp.vhd +++ b/src/Tests/Level_1/L1_rtps_writer_test1_vrndp.vhd @@ -92,39 +92,39 @@ begin MAX_REMOTE_ENDPOINTS => MAX_REMOTE_ENDPOINTS ) port map ( - clk => clk, - reset => reset, - time => test_time, - empty_user => empty_user or packet_sent_user, - rd_user => rd_user, - data_in_user => data_in_user, - last_word_in_user => last_word_in_user, - empty_meta => empty_meta or packet_sent_meta, - rd_meta => rd_meta, - data_in_meta => data_in_meta, - last_word_in_meta => last_word_in_meta, - alive_sig => open, - wr_rtps => fifo_wr, - full_rtps => fifo_full, - last_word_out_rtps => fifo_in(WORD_WIDTH), - data_out_rtps => fifo_in(WORD_WIDTH-1 downto 0), - assert_liveliness => '0', - data_available => data_available, - start_hc => start_hc, - opcode_hc => opcode_hc, - ack_hc => ack_hc, - seq_nr_hc => seq_nr_hc, - done_hc => done_hc, - ret_hc => ret_hc, - get_data_hc => get_data_hc, - data_in_hc => data_in_hc, - valid_in_hc => valid_in_hc, - ready_in_hc => ready_in_hc, - last_word_in_hc => last_word_in_hc, - cc_instance_handle => cc_instance_handle, - cc_kind => cc_kind, - cc_source_timestamp => cc_source_timestamp, - cc_seq_nr => cc_seq_nr + clk => clk, + reset => reset, + time => test_time, + empty_user => empty_user or packet_sent_user, + rd_user => rd_user, + data_in_user => data_in_user, + last_word_in_user => last_word_in_user, + empty_meta => empty_meta or packet_sent_meta, + rd_meta => rd_meta, + data_in_meta => data_in_meta, + last_word_in_meta => last_word_in_meta, + alive_sig => open, + wr_rtps => fifo_wr, + full_rtps => fifo_full, + last_word_out_rtps => fifo_in(WORD_WIDTH), + data_out_rtps => fifo_in(WORD_WIDTH-1 downto 0), + liveliness_assertion => '0', + data_available => data_available, + start_hc => start_hc, + opcode_hc => opcode_hc, + ack_hc => ack_hc, + seq_nr_hc => seq_nr_hc, + done_hc => done_hc, + ret_hc => ret_hc, + get_data_hc => get_data_hc, + data_in_hc => data_in_hc, + valid_in_hc => valid_in_hc, + ready_in_hc => ready_in_hc, + last_word_in_hc => last_word_in_hc, + cc_instance_handle => cc_instance_handle, + cc_kind => cc_kind, + cc_source_timestamp => cc_source_timestamp, + cc_seq_nr => cc_seq_nr ); fifo_inst : entity work.FWFT_FIFO(arch) diff --git a/src/Tests/Level_1/L1_rtps_writer_test2_vrkdn.vhd b/src/Tests/Level_1/L1_rtps_writer_test2_vrkdn.vhd index 86a36c1..288bc67 100644 --- a/src/Tests/Level_1/L1_rtps_writer_test2_vrkdn.vhd +++ b/src/Tests/Level_1/L1_rtps_writer_test2_vrkdn.vhd @@ -34,7 +34,7 @@ architecture testbench of L1_rtps_writer_test2_vrkdn is signal clk, empty_user, empty_meta, rd_meta, last_word_in_meta, last_word_in_hc, last_word_out_rtps : std_logic := '0'; signal reset : std_logic := '1'; signal data_in_meta, data_out, data_in_hc : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); - signal wr_sig, full, data_available, assert_liveliness : std_logic := '0'; + signal wr_sig, full, data_available, liveliness_assertion : std_logic := '0'; signal ready_in_hc, valid_in_hc, ack_hc, done_hc, get_data_hc, start_hc : std_logic := '0'; signal seq_nr_hc : SEQUENCENUMBER_TYPE := SEQUENCENUMBER_UNKNOWN; signal stim_stage_meta : SEND_STAGE_TYPE := IDLE; @@ -91,39 +91,39 @@ begin MAX_REMOTE_ENDPOINTS => MAX_REMOTE_ENDPOINTS ) port map ( - clk => clk, - reset => reset, - time => test_time, - empty_user => '1', - rd_user => open, - data_in_user => (others => '0'), - last_word_in_user => '0', - empty_meta => empty_meta or packet_sent_meta, - rd_meta => rd_meta, - data_in_meta => data_in_meta, - last_word_in_meta => last_word_in_meta, - alive_sig => open, - wr_rtps => fifo_wr, - full_rtps => fifo_full, - last_word_out_rtps => fifo_in(WORD_WIDTH), - data_out_rtps => fifo_in(WORD_WIDTH-1 downto 0), - assert_liveliness => assert_liveliness, - data_available => data_available, - start_hc => start_hc, - opcode_hc => opcode_hc, - ack_hc => ack_hc, - seq_nr_hc => seq_nr_hc, - done_hc => done_hc, - ret_hc => ret_hc, - get_data_hc => get_data_hc, - data_in_hc => data_in_hc, - valid_in_hc => valid_in_hc, - ready_in_hc => ready_in_hc, - last_word_in_hc => last_word_in_hc, - cc_instance_handle => cc_instance_handle, - cc_kind => cc_kind, - cc_source_timestamp => cc_source_timestamp, - cc_seq_nr => cc_seq_nr + clk => clk, + reset => reset, + time => test_time, + empty_user => '1', + rd_user => open, + data_in_user => (others => '0'), + last_word_in_user => '0', + empty_meta => empty_meta or packet_sent_meta, + rd_meta => rd_meta, + data_in_meta => data_in_meta, + last_word_in_meta => last_word_in_meta, + alive_sig => open, + wr_rtps => fifo_wr, + full_rtps => fifo_full, + last_word_out_rtps => fifo_in(WORD_WIDTH), + data_out_rtps => fifo_in(WORD_WIDTH-1 downto 0), + liveliness_assertion => liveliness_assertion, + data_available => data_available, + start_hc => start_hc, + opcode_hc => opcode_hc, + ack_hc => ack_hc, + seq_nr_hc => seq_nr_hc, + done_hc => done_hc, + ret_hc => ret_hc, + get_data_hc => get_data_hc, + data_in_hc => data_in_hc, + valid_in_hc => valid_in_hc, + ready_in_hc => ready_in_hc, + last_word_in_hc => last_word_in_hc, + cc_instance_handle => cc_instance_handle, + cc_kind => cc_kind, + cc_source_timestamp => cc_source_timestamp, + cc_seq_nr => cc_seq_nr ); fifo_inst : entity work.FWFT_FIFO(arch) @@ -248,7 +248,7 @@ begin end if; end procedure; - procedure push_hb(endpoint : in ENDPOINT_DATA_TYPE; first : in SEQUENCENUMBER_TYPE; last : in SEQUENCENUMBER_TYPE; assert_liveliness : in boolean) is + procedure push_hb(endpoint : in ENDPOINT_DATA_TYPE; first : in SEQUENCENUMBER_TYPE; last : in SEQUENCENUMBER_TYPE; liveliness_assertion : in boolean) is begin reference := EMPTY_TEST_PACKET; -- OUTPUT HEADER @@ -266,7 +266,7 @@ begin sub.readerId := ENTITYID_UNKNOWN; sub.firstSN := first; sub.lastSN := last; - sub.flags(SUBMESSAGE_LIVELINESS_FLAG_POS) := '1' when (assert_liveliness) else '0'; + sub.flags(SUBMESSAGE_LIVELINESS_FLAG_POS) := '1' when (liveliness_assertion) else '0'; sub.count := std_logic_vector(to_unsigned(count, CDR_LONG_WIDTH)); gen_rtps_submessage(sub, reference); fix_output_packet(reference); @@ -335,7 +335,7 @@ begin new_cc <= '0'; stim_done <= '0'; start_meta <= '0'; - assert_liveliness <= '0'; + liveliness_assertion <= '0'; reset <= '1'; wait until rising_edge(clk); wait until rising_edge(clk); @@ -399,10 +399,10 @@ begin test_cc(2).payload <= gen_payload; test_cc_fill <= 3; new_cc <= '1'; - assert_liveliness <= '1'; + liveliness_assertion <= '1'; wait until rising_edge(clk); new_cc <= '0'; - assert_liveliness <= '0'; + liveliness_assertion <= '0'; wait until rising_edge(clk); Log("Send HEARTBEAT to Endpoint 0,1 [Liveliness Flag]", INFO); @@ -511,9 +511,9 @@ begin wait_on_idle; Log("Assert Liveliness", INFO); - assert_liveliness <= '1'; + liveliness_assertion <= '1'; wait until rising_edge(clk); - assert_liveliness <= '0'; + liveliness_assertion <= '0'; wait until rising_edge(clk); Log("Send HEARTBEAT to Endpoint 0,1,2,3,4", INFO); diff --git a/src/dds_writer.vhd b/src/dds_writer.vhd index bc3f269..37c9217 100644 --- a/src/dds_writer.vhd +++ b/src/dds_writer.vhd @@ -2,68 +2,87 @@ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; +use work.math_pkg.all; +use work.rtps_package.all; +use work.user_config.all; +use work.rtps_config_package.all; + -- TODO: Check if sample_cnt is always maintained (also with MAX_SAMPLES_PER_INSTANCE = LENGTH_UNLIMITED) entity dds_writer is generic ( - TIME_BASED_FILTER_QOS : DURATION_TYPE := DEFAULT_TIME_BASED_FILTER_QOS; - MAX_INSTANCES : natural := DEFAULT_MAX_INSTANCES; - MAX_SAMPLES_PER_INSTANCE : natural := DEFAULT_MAX_SAMPLES_PER_INSTANCE; - HISTORY_QOS : std_logic_vector(CDR_ENUMERATION_WIDTH-1 downto 0) := DEFAULT_HISTORY_QOS; - RELIABILITY_QOS : std_logic_vector(CDR_ENUMERATION_WIDTH-1 downto 0) := DEFAULT_RELIABILTY_QOS; - PRESENTATION_QOS : std_logic_vector(CDR_ENUMERATION_WIDTH-1 downto 0) := DEFAULT_PRESENTATION_QOS; - DESTINATION_ORDER_QOS : std_logic_vector(CDR_ENUMERATION_WIDTH-1 downto 0) := DEFAULT_DESTINATION_ORDER_QOS; - COHERENT_ACCESS : boolean := DEFAULT_COHERENT_ACCESS; - ORDERED_ACCESS : boolean := DEFAULT_ORDERED_ACCESS; - WITH_KEY : boolean := FALSE; -- TODO: Default - LIFESPAN_QOS : DURATION_TYPE := DEFAULT_LIFESPAN_QOS; - LEASE_DURATION : DURATION_TYPE := DEFAULT_LEASE_DURATION; + HISTORY_QOS : std_logic_vector(CDR_ENUMERATION_WIDTH-1 downto 0); + RELIABILITY_QOS : std_logic_vector(CDR_ENUMERATION_WIDTH-1 downto 0); + PRESENTATION_QOS : std_logic_vector(CDR_ENUMERATION_WIDTH-1 downto 0); + DESTINATION_ORDER_QOS : std_logic_vector(CDR_ENUMERATION_WIDTH-1 downto 0); + DEADLINE_QOS : DURATION_TYPE; + TIME_BASED_FILTER_QOS : DURATION_TYPE; + LIFESPAN_QOS : DURATION_TYPE; + LEASE_DURATION : DURATION_TYPE; + COHERENT_ACCESS : boolean; + ORDERED_ACCESS : boolean; + WITH_KEY : boolean; + MAX_SAMPLES : std_logic_vector(CDR_LONG_WIDTH-1 downto 0); + MAX_INSTANCES : std_logic_vector(CDR_LONG_WIDTH-1 downto 0); + MAX_SAMPLES_PER_INSTANCE : std_logic_vector(CDR_LONG_WIDTH-1 downto 0); + PAYLOAD_FRAME_SIZE : natural ); port ( -- SYSTEM - clk : in std_logic; - reset : in std_logic; - time : in TIME_TYPE; - - -- TO RTPS ENDPOINT - start_rtps : in std_logic; - opcode_rtps : in HISTORY_CACHE_OPCODE_TYPE; - ack_rtps : out std_logic; - done_rtps : out std_logic; - ret_rtps : out HISTORY_CACHE_RESPOSNE_TYPE; - seq_nr_rtps : in SEQUENCENUMBER_TYPE; - get_data_rtps : in std_logic; - data_out_rtps : out std_logic_vector(WORD_WIDTH-1 downto 0); - valid_out_rtps : out std_logic; - ready_out_rtps : in std_logic; - last_word_out_rtps : out std_logic; - assert_liveliness : out std_logic; - data_available : out std_logic; + clk : in std_logic; + reset : in std_logic; + time : in TIME_TYPE; + -- TO/FROM RTPS ENDPOINT + start_rtps : in std_logic; + opcode_rtps : in HISTORY_CACHE_OPCODE_TYPE; + ack_rtps : out std_logic; + done_rtps : out std_logic; + ret_rtps : out HISTORY_CACHE_RESPONSE_TYPE; + seq_nr_rtps : in SEQUENCENUMBER_TYPE; + get_data_rtps : in std_logic; + data_out_rtps : out std_logic_vector(WORD_WIDTH-1 downto 0); + valid_out_rtps : out std_logic; + ready_out_rtps : in std_logic; + last_word_out_rtps : out std_logic; + liveliness_assertion : out std_logic; + data_available : out std_logic; -- Cache Change - cc_instance_handle : out INSTANCE_HANDLE_TYPE; - cc_kind : out CACHE_CHANGE_KIND_TYPE; - cc_source_timestamp : out TIME_TYPE; - - -- FROM USER ENTITY - start_dds : in std_logic; - ack_dds : out std_logic; - opcode_dds : in HISTORY_CACHE_OPCODE_TYPE; - instance_handle_dds : in INSTANCE_HANDLE_TYPE; - source_ts_dds : in TIME_TYPE; - max_wait_dds : in DURATION_TYPE; - done_dds : out std_logic; - return_code_dds : out std_logic_vector(RETURN_CODE_WIDTH-1 downto 0); - ready_in_dds : out std_logic; - valid_in_dds : in std_logic; - data_in_dds : in std_logic_vector(WORD_WIDTH-1 downto 0); - last_word_in_dds : in std_logic; - ready_out_dds : in std_logic; - valid_out_dds : out std_logic; - data_out_dds : out std_logic_vector(WORD_WIDTH-1 downto 0); - last_word_out_dds : out std_logic; - - -- COMMUNICATION STATUS - status : out std_logic_vector(STATUS_KIND_WIDTH-1 downto 0); + cc_instance_handle : out INSTANCE_HANDLE_TYPE; + cc_kind : out CACHE_CHANGE_KIND_TYPE; + cc_source_timestamp : out TIME_TYPE; + cc_seq_nr : out SEQUENCENUMBER_TYPE; + -- TO/FROM KEY_HOLDER + start_kh : out std_logic; + opcode_kh : out KEY_HOLDER_TYPE; + ack_kh : in std_logic; + data_in_kh : in std_logic_vector(WORD_WIDTH-1 downto 0); + valid_in_kh : in std_logic; + ready_in_kh : out std_logic; + last_word_in_kh : in std_logic; + data_out_kh : out std_logic_vector(WORD_WIDTH-1 downto 0); + valid_out_kh : out std_logic; + ready_out_kh : in std_logic; + last_word_out_kh : out std_logic; + abort_kh : out std_logic; + -- TO/FROM USER ENTITY + start_dds : in std_logic; + ack_dds : out std_logic; + opcode_dds : in DDS_WRITER_OPCODE_TYPE; + instance_handle_dds : in INSTANCE_HANDLE_TYPE; + source_ts_dds : in TIME_TYPE; + max_wait_dds : in DURATION_TYPE; + done_dds : out std_logic; + return_code_dds : out std_logic_vector(RETURN_CODE_WIDTH-1 downto 0); + ready_in_dds : out std_logic; + valid_in_dds : in std_logic; + data_in_dds : in std_logic_vector(WORD_WIDTH-1 downto 0); + last_word_in_dds : in std_logic; + ready_out_dds : in std_logic; + valid_out_dds : out std_logic; + data_out_dds : out std_logic_vector(WORD_WIDTH-1 downto 0); + last_word_out_dds : out std_logic; + -- Communication Status + status : out std_logic_vector(STATUS_KIND_WIDTH-1 downto 0) ); end entity; @@ -71,8 +90,16 @@ architecture arch of dds_writer is --*****CONSTANT DECLARATION***** -- *SAMPLE MEMORY* + -- 4-Byte Word Size of a Remote Endpoint Entry in Memory + function gen_frame_size(lifespan : DURATION_TYPE) return natural is + variable ret : natural := 0; + begin + ret := 11 when (lifespan /= DURATION_INFINITE) else 9; + return ret; + end function; + constant SAMPLE_FRAME_SIZE : natural := gen_frame_size(LIFESPAN_QOS); -- Sample Info Memory Size in 4-Byte Words - constant SAMPLE_MEMORY_SIZE : natural := TODO; + constant SAMPLE_MEMORY_SIZE : natural := to_integer(unsigned(MAX_SAMPLES)) * SAMPLE_FRAME_SIZE; -- Sample Info Memory Address Width constant SAMPLE_MEMORY_ADDR_WIDTH : natural := log2c(SAMPLE_MEMORY_SIZE); -- Highest Sample Info Memory Address @@ -82,7 +109,7 @@ architecture arch of dds_writer is -- *PAYLOAD MEMORY* -- Payload Memory Size in 4-Byte Words - constant PAYLOAD_MEMORY_SIZE : natural := TODO; + constant PAYLOAD_MEMORY_SIZE : natural := to_integer(unsigned(MAX_SAMPLES)) * PAYLOAD_FRAME_SIZE; -- Payload Memory Address Width constant PAYLOAD_MEMORY_ADDR_WIDTH : natural := log2c(PAYLOAD_MEMORY_SIZE); -- Highest Payload Memory Address @@ -91,14 +118,16 @@ architecture arch of dds_writer is constant MAX_PAYLOAD_ADDRESS : unsigned(PAYLOAD_MEMORY_ADDR_WIDTH-1 downto 0) := PAYLOAD_MEMORY_MAX_ADDRESS - PAYLOAD_FRAME_SIZE + 1; -- *INSTANCE MEMORY* + -- 4-Byte Word Size of a Remote Endpoint Entry in Memory + constant INSTANCE_FRAME_SIZE : natural := 8; -- Instance Memory Size in 4-Byte Words - constant INSTANCE_MEMORY_SIZE : natural := TODO; + constant INSTANCE_MEMORY_SIZE : natural := to_integer(unsigned(MAX_INSTANCES)) * INSTANCE_FRAME_SIZE; -- Instance Memory Address Width constant INSTANCE_MEMORY_ADDR_WIDTH : natural := log2c(INSTANCE_MEMORY_SIZE); -- Highest Instance Memory Address constant INSTANCE_MEMORY_MAX_ADDRESS: unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0) := to_unsigned(INSTANCE_MEMORY_SIZE-1, INSTANCE_MEMORY_ADDR_WIDTH); -- Highest Instance Frame Address - constant MAX_INSTANCE_ADDRESS : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0) := INSTANCE_MEMORY_MAX_ADDRESS - INSTANCE_FRAME_SIZE + 1; + constant MAX_INSTANCE_ADDRESS : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0) := INSTANCE_MEMORY_MAX_ADDRESS - INSTANCE_FRAME_SIZE + 1; -- Address pointing to the beginning of the first Instance Data Frame constant FIRST_INSTANCE_ADDRESS : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); @@ -108,7 +137,13 @@ architecture arch of dds_writer is constant SMF_SEQ_NR_OFFSET : natural := 1; constant SMF_TIMESTAMP_OFFSET : natural := 3; constant SMF_LIFESPAN_DEADLINE_OFFSET : natural := 5; - constant SMF_PAYLOAD_ADDR_OFFSET : natural := (SMF_LIFESPAN_DEADLINE_OFFSET + 2) when (LIFESPAN_QOS /= DURATION_INFINITE) else (SMF_TIMESTAMP_OFFSET + 2); + function gen_smf_payload_addr_offset(lifespan : DURATION_TYPE) return natural is + variable ret : natural := 0; + begin + ret := (SMF_LIFESPAN_DEADLINE_OFFSET + 2) when (lifespan /= DURATION_INFINITE) else (SMF_TIMESTAMP_OFFSET + 2); + return ret; + end function; + constant SMF_PAYLOAD_ADDR_OFFSET : natural := gen_smf_payload_addr_offset(LIFESPAN_QOS); constant SMF_INSTANCE_ADDR_OFFSET : natural := SMF_PAYLOAD_ADDR_OFFSET + 1; constant SMF_PREV_ADDR_OFFSET : natural := SMF_INSTANCE_ADDR_OFFSET + 1; constant SMF_NEXT_ADDR_OFFSET : natural := SMF_PREV_ADDR_OFFSET + 1; @@ -129,21 +164,21 @@ architecture arch of dds_writer is -- *INSTANCE MEMORY FRAME FORMAT FLAGS* -- Flags mapping to the respective Endpoint Memory Frame Fields constant IMF_FLAG_WIDTH : natural := 4; - constant IMF_KEY_HASH_FLAG : std_logic_vector(0 to IMF_FLAG_WIDTH-1) := (0 => 1, others => '0'); - constant IMF_STATUS_FLAG : std_logic_vector(0 to IMF_FLAG_WIDTH-1) := (1 => 1, others => '0'); - constant IMF_SAMPLE_CNT_FLAG : std_logic_vector(0 to IMF_FLAG_WIDTH-1) := (2 => 1, others => '0'); - constant IMF_ACK_CNT_FLAG : std_logic_vector(0 to IMF_FLAG_WIDTH-1) := (3 => 1, others => '0'); + constant IMF_KEY_HASH_FLAG : std_logic_vector(0 to IMF_FLAG_WIDTH-1) := (0 => '1', others => '0'); + constant IMF_STATUS_FLAG : std_logic_vector(0 to IMF_FLAG_WIDTH-1) := (1 => '1', others => '0'); + constant IMF_SAMPLE_CNT_FLAG : std_logic_vector(0 to IMF_FLAG_WIDTH-1) := (2 => '1', others => '0'); + constant IMF_ACK_CNT_FLAG : std_logic_vector(0 to IMF_FLAG_WIDTH-1) := (3 => '1', others => '0'); --*****TYPE DECLARATION***** -- FSM states. Explained below in detail type STAGE_TYPE is (IDLE, UNKNOWN_OPERATION_DDS, UNKNOWN_OPERATION_RTPS, UNKNOWN_SEQ_NR, ASSERT_LIVELINESS, ADD_SAMPLE_INFO, ADD_PAYLOAD, NEXT_PAYLOAD_SLOT, ALIGN_PAYLOAD, GET_KEY_HASH, INITIATE_INSTANCE_SEARCH, REGISTER_OPERATION, LOOKUP_OPERATION, PUSH_KEY_HASH, FILTER_STAGE, UPDATE_INSTANCE, - FINALIZE_PAYLOAD, FIX_POINTERS, FINALIZE_SAMPLE, GET_OLDEST_SAMPLE_INSTANCE, FIND_OLDEST_INST_SAMPLE, REMOVE_SAMPLE, POST_SAMPLE_REMOVE, SKIP_ADD_REJECT, - REMOVE_STALE_INSTANCE, GET_SEQ_NR, FIND_SEQ_NR, ACKNACK_SAMPLE, GET_SAMPLE, GET_PAYLOAD, GET_SERIALIZED_KEY, CHECK_LIFESPAN, GET_LIVELINESS_LOST_STATUS, - GET_OFFERED_DEADLINE_MISSED_STATUS, CHECK_DEADLINE, RESET_SAMPLE_MEMORY, RESET_PAYLOAD_MEMORY); + FINALIZE_PAYLOAD, FIX_POINTERS, FINALIZE_SAMPLE, GET_OLDEST_SAMPLE_INSTANCE, FIND_OLDEST_INST_SAMPLE, REMOVE_ORPHAN_SAMPLES, REMOVE_SAMPLE, + POST_SAMPLE_REMOVE, SKIP_ADD_REJECT, REMOVE_STALE_INSTANCE, GET_SEQ_NR, FIND_SEQ_NR, ACKNACK_SAMPLE, GET_SAMPLE, GET_PAYLOAD, GET_SERIALIZED_KEY, + CHECK_LIFESPAN, GET_LIVELINESS_LOST_STATUS, GET_OFFERED_DEADLINE_MISSED_STATUS, CHECK_DEADLINE, RESET_SAMPLE_MEMORY, RESET_PAYLOAD_MEMORY); -- Instance Memory FSM states. Explained below in detail type INST_STAGE_TYPE is (IDLE, SEARCH_INSTANCE_HASH, SEARCH_INSTANCE_ADDR, GET_NEXT_INSTANCE, GET_INSTANCE_DATA, FIND_POS, INSERT_INSTANCE, UPDATE_INSTANCE, - REMOVE_INSTANCE); + REMOVE_INSTANCE, RESET_MEMORY); -- *Instance Memory Opcodes* -- OPCODE DESCRIPTION -- SEARCH_INSTANCE_HASH Search Instance based on Key Hash pointed by key_hash. @@ -154,7 +189,7 @@ architecture arch of dds_writer is -- GET_NEXT_INSTANCE Get Instance Data of next Instance (from the Instance pointed by inst_addr_base) (inst_mem_fields specifies which Fields to get) -- REMOVE_INSTANCE Remove Instance pointed by inst_addr_base -- GET_INSTANCE Get Data of Instance pointed by inst_addr_update. (inst_mem_fields specifies which Fields to get) - type INSTANCE_OPCODE_TYPE is (SEARCH_INSTANCE_HASH, SEARCH_INSTANCE_ADDR, INSERT_INSTANCE, UPDATE_INSTANCE, GET_FIRST_INSTANCE, GET_NEXT_INSTANCE, REMOVE_INSTANCE, + type INSTANCE_OPCODE_TYPE is (NOP, SEARCH_INSTANCE_HASH, SEARCH_INSTANCE_ADDR, INSERT_INSTANCE, UPDATE_INSTANCE, GET_FIRST_INSTANCE, GET_NEXT_INSTANCE, REMOVE_INSTANCE, GET_INSTANCE); -- Record of Instance Data type INSTANCE_DATA_TYPE is record @@ -174,8 +209,8 @@ architecture arch of dds_writer is type INST_LATCH_DATA_TYPE is record key_hash : KEY_HASH_TYPE; status_info : std_logic_vector(CDR_LONG_WIDTH-1 downto 0); - sample_cnt : std_logic_vector(CDR_LONG_WIDTH-1 downto 0); - ack_cnt : std_logic_vector(CDR_LONG_WIDTH-1 downto 0); + sample_cnt : unsigned(CDR_LONG_WIDTH-1 downto 0); + ack_cnt : unsigned(CDR_LONG_WIDTH-1 downto 0); field_flags : std_logic_vector(0 to IMF_FLAG_WIDTH-1); addr : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0); end record; @@ -214,23 +249,13 @@ architecture arch of dds_writer is signal inst_ready_out, inst_valid_out : std_logic := '0'; signal inst_abort_read : std_logic := '0'; - -- *KEY HASH GENERATOR CONNECTION SIGNALS* - signal khg_valid_in, khg_ready_in, khg_last_word_in, khg_valid_out, khg_ready_out, khg_last_word_out : std_logic := '0'; - signal khg_data_in, khg_data_out : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); - signal khg_abort : std_logic := '0'; - - -- *SERIALIZED KEY GENERATOR CONNECTION SIGNALS* - signal skg_valid_in, skg_ready_in, skg_last_word_in, skg_valid_out, skg_ready_out, skg_last_word_out : std_logic := '0'; - signal skg_data_in, skg_data_out : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); - signal skg_abort : std_logic := '0'; - -- *MAIN PROCESS* -- FSM state signal stage, stage_next : STAGE_TYPE := IDLE; -- FSM state latch. Used to transition dynamically to different states from the same state. signal return_stage, return_stage_next : STAGE_TYPE := IDLE; -- General Purpose Counter - signal cnt, cnt_next : natural range TODO := 0; + signal cnt, cnt_next : natural range 0 to 14 := 0; -- Counter used to read/write Payload Fames signal cnt2, cnt2_next : natural range 0 to PAYLOAD_FRAME_SIZE := 0; -- Counter used to read/write Payload Fames @@ -254,7 +279,7 @@ architecture arch of dds_writer is -- Key hash Latch signal key_hash, key_hash_next : KEY_HASH_TYPE := (others => (others => '0')); -- Instance Handle Latch - signal instance_handle, instance_handle_next : INSTANCE_HANDLE_TYPE := (others => '0'); + signal instance_handle, instance_handle_next : INSTANCE_HANDLE_TYPE := HANDLE_NIL; -- Source Timestamp Latch signal source_ts, source_ts_next : TIME_TYPE := TIME_INVALID; -- Sequence Number Latch @@ -289,6 +314,8 @@ architecture arch of dds_writer is signal inst_addr_update : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); -- Signal used to pass Sample Counts to the Instance Memory Process signal sample_cnt : unsigned(CDR_LONG_WIDTH-1 downto 0) := (others => '0'); + -- Signal used to pass ACK Counts to the Instance Memory Process + signal ack_cnt : unsigned(CDR_LONG_WIDTH-1 downto 0) := (others => '0'); -- Signals start of Instance Memory Operation signal inst_op_start : std_logic := '0'; -- Opcode of Instance Memory Operation (Valid only when inst_op_start is high) @@ -303,11 +330,11 @@ architecture arch of dds_writer is -- It contains the next applicable Sequence Number signal global_seq_nr, global_seq_nr_next : SEQUENCENUMBER_TYPE := SEQUENCENUMBER_UNKNOWN; -- Signal containing the current number of stored samples - signal global_sample_cnt, global_sample_cnt_next : natural range TODO := 0; + signal global_sample_cnt, global_sample_cnt_next : natural range 0 to to_integer(unsigned(MAX_SAMPLES)) := 0; -- Signal containing the current number of ACKed stored samples - signal global_ack_cnt, global_ack_cnt_next : natural range TODO := 0; + signal global_ack_cnt, global_ack_cnt_next : natural range 0 to to_integer(unsigned(MAX_SAMPLES)) := 0; -- Signal containing the number of currently stale Instances - signal stale_inst_cnt, stale_inst_cnt_next : natural range 0 to MAX_INSTANCES := 0; + signal stale_inst_cnt, stale_inst_cnt_next : natural range 0 to to_integer(unsigned(MAX_INSTANCES)) := 0; -- Signifies if a Instance Register Operation is in progress signal register_op, register_op_next : std_logic := '0'; -- Signifies if a Instance Lookup Operation is in progress @@ -349,6 +376,7 @@ architecture arch of dds_writer is signal cc_instance_handle_sig, cc_instance_handle_sig_next : INSTANCE_HANDLE_TYPE := HANDLE_NIL; signal cc_kind_sig, cc_kind_sig_next : CACHE_CHANGE_KIND_TYPE := ALIVE; signal cc_source_timestamp_sig, cc_source_timestamp_sig_next : TIME_TYPE := TIME_INVALID; + signal cc_seq_nr_sig, cc_seq_nr_sig_next : SEQUENCENUMBER_TYPE := SEQUENCENUMBER_UNKNOWN; -- *INSTANCE MEMORY PROCESS* -- Instance Memory FSM state @@ -368,9 +396,9 @@ architecture arch of dds_writer is -- Latch for Instance Data from memory signal inst_data, inst_data_next : INSTANCE_DATA_TYPE := ZERO_INSTANCE_DATA; -- General Purpose Counter - signal inst_cnt, inst_cnt_next : natural range TODO := 0; + signal inst_cnt, inst_cnt_next : natural range 0 to 13 := 0; -- Counter used to read/write the Writer Bitmap - signal inst_cnt2, inst_cnt2_next : natural 0 to ENDPOINT_BITMAP_ARRAY_TYPE'length := 0; + signal inst_cnt2, inst_cnt2_next : natural range 0 to ENDPOINT_BITMAP_ARRAY_TYPE'length := 0; -- General Purpose Long Latch signal inst_long_latch, inst_long_latch_next : std_logic_vector(CDR_LONG_WIDTH-1 downto 0) := (others => '0'); @@ -401,7 +429,7 @@ architecture arch of dds_writer is variable ret : unsigned((KEY_HASH_WIDTH*WORD_WIDTH)-1 downto 0) := (others => '0'); begin for i in 0 to KEY_HASH_WIDTH-1 loop - ret(((KEY_HASH_WIDTH-i)*WORD_WIDTH)-1 downto (KEY_HASH_WIDTH-1-i)*WORD_WIDTH) := input(i); + ret(((KEY_HASH_WIDTH-i)*WORD_WIDTH)-1 downto (KEY_HASH_WIDTH-1-i)*WORD_WIDTH) := unsigned(input(i)); end loop; return ret; end function; @@ -462,41 +490,13 @@ begin clk => clk, reset => reset or sample_abort_read, addr => std_logic_vector(sample_addr), - read => instance_read, - ready_in => instance_ready_in, - valid_in => instance_valid_in, - data_in => instance_write_data, - ready_out => instance_ready_out, - valid_out => instance_valid_out, - data_out => instance_read_data - ); - - key_hash_generator_inst : entity work.key_hash_generator(arch) - port ( - clk => clk, - reset => reset or khg_abort, - data_in => khg_data_in, - valid_in => khg_valid_in, - ready_in => khg_ready_in, - last_word_in => khg_last_word_in, - data_out => khg_data_out, - valid_out => khg_valid_out, - ready_out => khg_ready_out, - last_word_out => khg_last_word_out - ); - - serialized_key_generator_inst : entity work.serialized_key_generator(arch) - port ( - clk => clk, - reset => reset or skg_abort, - data_in => skg_data_in, - valid_in => skg_valid_in, - ready_in => skg_ready_in, - last_word_in => skg_last_word_in, - data_out => skg_data_out, - valid_out => skg_valid_out, - ready_out => skg_ready_out, - last_word_out => skg_last_word_out + read => inst_read, + ready_in => inst_ready_in, + valid_in => inst_valid_in, + data_in => inst_write_data, + ready_out => inst_ready_out, + valid_out => inst_valid_out, + data_out => inst_read_data ); end generate; @@ -530,6 +530,7 @@ begin -- FINALIZE_SAMPLE Update inserted sample and list pointers. (Second Step of Sample Addition Finalization) -- GET_OLDEST_SAMPLE_INSTANCE Fetch the Instance Data of the oldest sample -- FIND_OLDEST_INST_SAMPLE Find the oldest sample of a specific Instance + -- REMOVE_ORPHAN_SAMPLES Remove all Samples of the removed Instance (dead_inst) -- REMOVE_SAMPLE Remove sample and linked payload -- POST_SAMPLE_REMOVE Update Instance Data of removed sample. If Instance Memory is full, and Instance is now eligible for removal, it is removed. -- SKIP_ADD_REJECT Skip RTPS Cache Change and signal rejection to RTPS. @@ -551,10 +552,10 @@ begin variable tmp_bitmap : std_logic_vector(0 to ENDPOINT_BITMAP_WIDTH-1) := (others => '0'); variable tmp_update : std_logic_vector(0 to IMF_FLAG_WIDTH-1) := (others => '0'); variable tmp_bool : boolean := FALSE; - variable valid_out_tmp, last_word_out_tmp, ready_out_tmp : std_logic := '0'; begin -- DEFAULT Registered stage_next <= stage; + oldest_sample_next <= oldest_sample; newest_sample_next <= newest_sample; empty_payload_list_head_next <= empty_payload_list_head; empty_sample_list_head_next <= empty_sample_list_head; @@ -571,9 +572,7 @@ begin sample_status_info_next <= sample_status_info; remove_oldest_sample_next <= remove_oldest_sample; remove_oldest_inst_sample_next <= remove_oldest_inst_sample; - added_new_instance_next <= added_new_instance; instance_handle_next <= instance_handle; - is_first_instance_sample_next <= is_first_instance_sample; sample_rej_cnt_next <= sample_rej_cnt; sample_rej_cnt_change_next <= sample_rej_cnt_change; sample_rej_last_reason_next <= sample_rej_last_reason; @@ -587,7 +586,9 @@ begin lifespan_time_next <= lifespan_time; is_lifespan_check_next <= is_lifespan_check; status_sig_next <= status_sig; + cnt_next <= cnt; cnt2_next <= cnt2; + cnt3_next <= cnt3; source_ts_next <= source_ts; global_seq_nr_next <= global_seq_nr; global_sample_cnt_next <= global_sample_cnt; @@ -608,22 +609,17 @@ begin is_rtps_next <= is_rtps; data_available_sig_next <= data_available_sig; orphan_samples_next <= orphan_samples; + key_hash_next <= key_hash; -- DEFAULT Unregistered inst_opcode <= NOP; ret_rtps <= ERROR; return_code_dds <= RETCODE_UNSUPPORTED; + opcode_kh <= NOP; ack_dds <= '0'; done_dds <= '0'; ack_rtps <= '0'; done_rtps <= '0'; - khg_abort <= '0'; inst_op_start <= '0'; - khg_last_word_in <= '0'; - khg_valid_in <= '0'; - khg_ready_out <= '0'; - skg_last_word_in <= '0'; - skg_valid_in <= '0'; - skg_ready_out <= '0'; sample_read <= '0'; sample_ready_out <= '0'; sample_valid_in <= '0'; @@ -633,14 +629,16 @@ begin payload_valid_in <= '0'; payload_abort_read <= '0'; ready_in_dds <= '0'; - assert_liveliness <= '0'; + liveliness_assertion <= '0'; valid_out_rtps <= '0'; last_word_out_rtps <= '0'; valid_out_dds <= '0'; last_word_out_dds <= '0'; - khg_data_in <= (others => '0'); - skg_data_in <= (others => '0'); - writer_bitmap <= (others => '0'); + start_kh <= '0'; + ready_in_kh <= '0'; + valid_out_kh <= '0'; + last_word_out_kh <= '0'; + data_out_kh <= (others => '0'); inst_addr_update <= (others => '0'); sample_addr <= (others => '0'); sample_write_data <= (others => '0'); @@ -659,7 +657,6 @@ begin register_op_next <= '0'; is_rtps_next <= '0'; - -- Orphan Samples Available if (orphan_samples = '1') then assert (oldest_sample /= SAMPLE_MEMORY_MAX_ADDRESS) severity FAILURE; @@ -681,7 +678,7 @@ begin inst_data_next.status_info(ISI_LIVELINESS_FLAG) <= '0'; else -- Update Requested Deadline Missed Status - status_sig_next(REQUESTED_DEADLINE_MISSED_STATUS) <= '1'; + status_sig_next <= status_sig and REQUESTED_DEADLINE_MISSED_STATUS; deadline_miss_cnt_next <= deadline_miss_cnt + 1; deadline_miss_cnt_change_next <= deadline_miss_cnt_change + 1; end if; @@ -690,12 +687,12 @@ begin elsif (LEASE_DURATION /= DURATION_INFINITE and lease_deadline <= time) then liveliness_lost_cnt_next <= liveliness_lost_cnt + 1; liveliness_lost_cnt_change_next <= liveliness_lost_cnt_change + 1; - status_sig_next(LIVELINESS_LOST_STATUS) <= '1'; + status_sig_next <= status_sig and LIVELINESS_LOST_STATUS; -- Reset lease_deadline_next <= time + LEASE_DURATION; -- WAIT_FOR_ACKNOWLEDGEMENT Done - elsif (ack_wait and global_ack_cnt = global_sample_cnt) then + elsif (ack_wait = '1' and global_ack_cnt = global_sample_cnt) then -- Reset ack_wait_next <= '0'; @@ -703,7 +700,7 @@ begin done_dds <= '1'; return_code_dds <= RETCODE_OK; -- WAIT_FOR_ACKNOWLEDGEMENT Timeout - elsif (ack_wait and timeout_time <= time) then + elsif (ack_wait = '1' and timeout_time <= time) then -- Reset ack_wait_next <= '0'; @@ -732,8 +729,9 @@ begin ack_rtps <= '1'; if (oldest_sample = SAMPLE_MEMORY_MAX_ADDRESS) then -- NOTE: If the HC is empty we return the Special value SEQUENCENUMBER_UNKNOWN - stage_next <= GET_SEQ_NR; - cnt_next <= 4; + stage_next <= GET_SEQ_NR; + cnt_next <= 4; + cc_seq_nr_sig_next <= SEQUENCENUMBER_UNKNOWN; else cur_sample_next <= oldest_sample; stage_next <= GET_SEQ_NR; @@ -747,8 +745,9 @@ begin if (newest_sample = SAMPLE_MEMORY_MAX_ADDRESS) then -- NOTE: If the HC is empty we return the Special value SEQUENCENUMBER_UNKNOWN - stage_next <= GET_SEQ_NR; - cnt_next <= 4; + stage_next <= GET_SEQ_NR; + cnt_next <= 4; + cc_seq_nr_sig_next <= SEQUENCENUMBER_UNKNOWN; else cur_sample_next <= newest_sample; stage_next <= GET_SEQ_NR; @@ -759,8 +758,11 @@ begin -- No Samples Available if (newest_sample = SAMPLE_MEMORY_MAX_ADDRESS) then - stage_next <= UNKNOWN_SEQ_NR; + stage_next <= UNKNOWN_SEQ_NR; + cc_seq_nr_sig_next <= SEQUENCENUMBER_UNKNOWN; else + seq_nr_next <= seq_nr_rtps; + cc_seq_nr_sig_next <= seq_nr_rtps; cur_sample_next <= newest_sample; stage_next <= FIND_SEQ_NR; cnt_next <= 0; @@ -772,7 +774,8 @@ begin -- No Samples Available if (newest_sample = SAMPLE_MEMORY_MAX_ADDRESS) then - stage_next <= UNKNOWN_SEQ_NR; + stage_next <= UNKNOWN_SEQ_NR; + cc_seq_nr_sig_next <= SEQUENCENUMBER_UNKNOWN; else cur_sample_next <= newest_sample; stage_next <= FIND_SEQ_NR; @@ -784,7 +787,8 @@ begin -- No Samples Available if (newest_sample = SAMPLE_MEMORY_MAX_ADDRESS) then - stage_next <= UNKNOWN_SEQ_NR; + stage_next <= UNKNOWN_SEQ_NR; + cc_seq_nr_sig_next <= SEQUENCENUMBER_UNKNOWN; else cur_sample_next <= newest_sample; stage_next <= FIND_SEQ_NR; @@ -796,7 +800,8 @@ begin -- No Samples Available if (newest_sample = SAMPLE_MEMORY_MAX_ADDRESS) then - stage_next <= UNKNOWN_SEQ_NR; + stage_next <= UNKNOWN_SEQ_NR; + cc_seq_nr_sig_next <= SEQUENCENUMBER_UNKNOWN; else cur_sample_next <= newest_sample; stage_next <= FIND_SEQ_NR; @@ -810,6 +815,13 @@ begin end case; -- DDS Operation elsif (ack_wait = '0' and start_dds = '1') then + -- Reset + register_op_next <= '0'; + instance_handle_next <= HANDLE_NIL; + source_ts_next <= TIME_INVALID; + sample_status_info_next <= (others => '0'); + key_hash_next <= HANDLE_NIL; + case (opcode_dds) is when REGISTER_INSTANCE => ack_dds <= '1'; @@ -833,7 +845,7 @@ begin -- NOTE: The ALIGNED_FLAG is set by default. if actual Payload is not aligned, need to reset. sample_status_info_next <= (SSI_PAYLOAD_FLAG => '1', SSI_ALIGNED_FLAG => '1', others => '0'); - cur_sample_next <= empty_sample_list_head; + cur_sample_next <= empty_sample_list_head; -- Instance Handle provided if (WITH_KEY and instance_handle_dds /= HANDLE_NIL) then @@ -894,9 +906,9 @@ begin ack_dds <= '1'; -- Synthesis Guard if (WITH_KEY) then - lookup_op_next <= '1'; - stage_next <= ADD_PAYLOAD; - cnt_next <= 1; + lookup_op_next <= '1'; + stage_next <= ADD_PAYLOAD; + cnt_next <= 1; else stage_next <= UNKNOWN_OPERATION_DDS; end if; @@ -913,7 +925,7 @@ begin -- Reset Liveliness lease_deadline_next <= time + LEASE_DURATION; - ack_dds <== '1'; + ack_dds <= '1'; stage_next <= ASSERT_LIVELINESS; when GET_LIVELINESS_LOST_STATUS => ack_dds <= '1'; @@ -937,15 +949,15 @@ begin -- DONE stage_next <= IDLE; when UNKNOWN_SEQ_NR => - done_rtps <= '1'; - ret_rtps <= INVALID; + done_rtps <= '1'; + ret_rtps <= INVALID; -- DONE - stage_next <= ILDE; + stage_next <= IDLE; when ASSERT_LIVELINESS => -- Propagate Liveliness Assertion - assert_liveliness <= '1'; + liveliness_assertion <= '1'; done_dds <= '0'; return_code_dds <= RETCODE_OK; @@ -969,7 +981,7 @@ begin when 1 => sample_valid_in <= '1'; sample_addr <= cur_sample + SMF_SEQ_NR_OFFSET; - sample_write_data <= global_seq_nr(0); + sample_write_data <= std_logic_vector(global_seq_nr(0)); -- Memory Flow Control Guard if (sample_ready_in = '1') then cnt_next <= cnt + 1; @@ -978,7 +990,7 @@ begin when 2 => sample_valid_in <= '1'; sample_addr <= cur_sample + SMF_SEQ_NR_OFFSET + 1; - sample_write_data <= global_seq_nr(1); + sample_write_data <= std_logic_vector(global_seq_nr(1)); -- Memory Flow Control Guard if (sample_ready_in = '1') then cnt_next <= cnt + 1; @@ -987,7 +999,7 @@ begin when 3 => sample_valid_in <= '1'; sample_addr <= cur_sample + SMF_TIMESTAMP_OFFSET; - sample_write_data <= source_ts(0) when source_ts /= TIME_INVALID else time(0); + sample_write_data <= std_logic_vector(source_ts(0)) when source_ts /= TIME_INVALID else std_logic_vector(time(0)); -- Memory Flow Control Guard if (sample_ready_in = '1') then cnt_next <= cnt + 1; @@ -996,7 +1008,7 @@ begin when 4 => sample_valid_in <= '1'; sample_addr <= cur_sample + SMF_TIMESTAMP_OFFSET + 1; - sample_write_data <= source_ts(1) when source_ts /= TIME_INVALID else time(1); + sample_write_data <= std_logic_vector(source_ts(1)) when source_ts /= TIME_INVALID else std_logic_vector(time(1)); -- Memory Flow Control Guard if (sample_ready_in = '1') then -- Synthesis Guard @@ -1013,7 +1025,7 @@ begin if (LIFESPAN_QOS /= DURATION_INFINITE) then sample_valid_in <= '1'; sample_addr <= cur_sample + SMF_LIFESPAN_DEADLINE_OFFSET; - sample_write_data <= lifespan(0); + sample_write_data <= std_logic_vector(lifespan(0)); -- Memory Flow Control Guard if (sample_ready_in = '1') then cnt_next <= cnt + 1; @@ -1025,7 +1037,7 @@ begin if (LIFESPAN_QOS /= DURATION_INFINITE) then sample_valid_in <= '1'; sample_addr <= cur_sample + SMF_LIFESPAN_DEADLINE_OFFSET; - sample_write_data <= lifespan(1); + sample_write_data <= std_logic_vector(lifespan(1)); -- Memory Flow Control Guard if (sample_ready_in = '1') then cnt_next <= cnt + 1; @@ -1035,12 +1047,36 @@ begin when 7 => sample_valid_in <= '1'; sample_addr <= cur_sample + SMF_PAYLOAD_ADDR_OFFSET; - sample_write_data <= empty_payload_list_head; + sample_write_data <= std_logic_vector(resize(empty_payload_list_head, WORD_WIDTH)); cur_payload_next <= empty_payload_list_head; -- Memory Flow Control Guard if (sample_ready_in = '1') then - stage_next <= ADD_PAYLOAD; - cnt_next <= 0; + -- Key Hash needs to be calculated + if (WITH_KEY and instance_handle = HANDLE_NIL) then + cnt_next <= cnt + 1; + else + stage_next <= ADD_PAYLOAD; + cnt_next <= 0; + cnt2_next <= 1; + end if; + end if; + -- Initiate KH Operation + when 8 => + -- Synthesis Guard + if (WITH_KEY) then + start_kh <= '1'; + -- Payload is Serialized Key + if (sample_status_info(SSI_DISPOSED_FLAG) = '1' or sample_status_info(SSI_UNREGISTERED_FLAG) = '1' or sample_status_info(SSI_FILTERED_FLAG) = '1') then + opcode_kh <= PUSH_SERIALIZED_KEY; + else + opcode_kh <= PUSH_DATA; + end if; + + if (ack_kh = '1') then + stage_next <= ADD_PAYLOAD; + cnt_next <= 0; + cnt2_next <= 1; + end if; end if; when others => null; @@ -1055,7 +1091,7 @@ begin if (valid_in_dds = '1') then payload_valid_in <= '1'; payload_addr <= cur_payload + cnt2; - payload_write_data <= data_in_rtps; + payload_write_data <= data_in_dds; -- Memory Control Flow Guard if (payload_ready_in = '1') then -- Key Hash needs to be calculated @@ -1070,6 +1106,7 @@ begin stage_next <= FILTER_STAGE; else stage_next <= ALIGN_PAYLOAD; + cnt_next <= 0; end if; else -- End of Payload Slot @@ -1084,26 +1121,27 @@ begin end if; end if; end if; - -- Push to KHG + -- Push to KH when 1 => -- Synthesis Guard if (WITH_KEY) then -- Input Guard if (valid_in_dds = '1') then - khg_valid_in <= '1'; - khg_data_in <= data_in_rtps; + valid_out_kh <= '1'; + data_out_kh <= data_in_dds; -- Output Guard - if (khg_ready_in = '1') then + if (ready_out_kh = '1') then ready_in_dds <= '1'; - -- Register/Lookup Operation in progress - if (WITH_KEY and (register_op = '1' or lookup_op = '1')) then + -- Operation does not have Payload to store + if (sample_status_info(SSI_PAYLOAD_FLAG) = '0') then -- End of Payload if (last_word_in_dds = '1') then + last_word_out_kh <= '1'; -- Fetch the Key Hash - stage_next <= GET_KEY_HASH; - cnt_next <= 0; + stage_next <= GET_KEY_HASH; + cnt_next <= 0; else -- Next Word cnt_next <= 1; -- Same Sub-state @@ -1114,10 +1152,11 @@ begin -- End of Payload Slot if (cnt2 = PAYLOAD_FRAME_SIZE) then -- Fetch the Key Hash - stage_next <= GET_KEY_HASH; - cnt_next <= 0; + stage_next <= GET_KEY_HASH; + cnt_next <= 0; else stage_next <= ALIGN_PAYLOAD; + cnt_next <= 0; end if; else -- End of Payload Slot @@ -1158,14 +1197,15 @@ begin -- Memory Control Flow Guard if (payload_valid_out = '1') then -- No Empty Payload Slots available - if (payload_read_data = PAYLOAD_MEMORY_MAX_ADDRESS) then + if (unsigned(payload_read_data) = PAYLOAD_MEMORY_MAX_ADDRESS) then -- Reject Change stage_next <= SKIP_ADD_REJECT; + cnt_next <= 0; -- Abort Key Hash Generation - khg_abort <= '1'; + abort_kh <= '1'; else -- Latch next Payload Slot and Continue - cur_payload_next <= payload_read_data; + cur_payload_next <= resize(unsigned(payload_read_data), PAYLOAD_MEMORY_ADDR_WIDTH); stage_next <= ADD_PAYLOAD; cnt_next <= 0; cnt2_next <= 1; @@ -1191,7 +1231,7 @@ begin when 1 => payload_valid_in <= '1'; payload_addr <= cur_payload + PAYLOAD_FRAME_SIZE-1; - payload_write_data <= to_unsigned(cnt2, WORD_WIDTH); + payload_write_data <= std_logic_vector(to_unsigned(cnt2, WORD_WIDTH)); -- Memory Control Flow Guard if (payload_ready_in = '1') then @@ -1208,16 +1248,16 @@ begin when GET_KEY_HASH => -- Synthesis Guard if (WITH_KEY) then - khg_ready_out <= '1'; + ready_in_kh <= '1'; - if (khg_valid_out = '1') then - cnt_next <= cnt + 1; + if (valid_in_kh = '1') then + cnt_next <= cnt + 1; -- Latch Key Hash - key_hash_next(cnt) <= khg_data_out; + key_hash_next(cnt) <= data_in_kh; -- Exit Condition - if (khg_last_word_out = '1') then + if (last_word_in_kh = '1') then -- DONE stage_next <= INITIATE_INSTANCE_SEARCH; end if; @@ -1240,10 +1280,10 @@ begin stage_next <= LOOKUP_OPERATION; -- Cache Change not yet Stored elsif (instance_handle /= HANDLE_NIL) then - stage_next <= ADD_SAMPLE_INFO; - cnt_next <= 0; + stage_next <= ADD_SAMPLE_INFO; + cnt_next <= 0; else - stage_next <= FILTER_STAGE; + stage_next <= FILTER_STAGE; end if; end if; end if; @@ -1258,6 +1298,7 @@ begin done_dds <= '1'; return_code_dds <= RETCODE_OK; stage_next <= PUSH_KEY_HASH; + cnt_next <= 0; -- Instance is Unregistered if (inst_data.status_info(ISI_UNREGISTERED_FLAG) = '1') then @@ -1295,6 +1336,7 @@ begin done_dds <= '1'; return_code_dds <= RETCODE_OK; stage_next <= PUSH_KEY_HASH; + cnt_next <= 0; -- Insert New Instance inst_op_start <= '1'; @@ -1363,6 +1405,7 @@ begin if (ready_out_dds = '1') then cnt_next <= cnt + 1; end if; + -- Return Code when 4 => done_dds <= '1'; return_code_dds <= RETCODE_OK; @@ -1385,7 +1428,7 @@ begin cur_inst_next <= inst_addr_base; -- RESOURCE_LIMITS_QOS (MAX_SAMPLES_PER_INSTANCE) - if (WITH_KEY and MAX_SAMPLES_PER_INSTANCE /= LENGTH_UNLIMITED and inst_data.sample_cnt = MAX_SAMPLES_PER_INSTANCE) then + if (WITH_KEY and MAX_SAMPLES_PER_INSTANCE /= LENGTH_UNLIMITED and inst_data.sample_cnt = unsigned(MAX_SAMPLES_PER_INSTANCE)) then if (inst_data.ack_cnt = 0 and HISTORY_QOS = KEEP_ALL_HISTORY_QOS) then -- Reject Change done_dds <= '1'; @@ -1571,7 +1614,7 @@ begin payload_valid_in <= '1'; payload_addr <= cur_payload + PMF_NEXT_ADDR_OFFSET; -- Make current Slot the Tail - payload_write_data <= PAYLOAD_MEMORY_MAX_ADDRESS; + payload_write_data <= std_logic_vector(resize(PAYLOAD_MEMORY_MAX_ADDRESS, WORD_WIDTH)); -- Memory Control Flow Guard if (payload_ready_in = '1') then @@ -1584,7 +1627,7 @@ begin -- Memory Control Flow Guard if (payload_valid_out = '1') then -- Fix New Empty List Head - empty_payload_list_head_next <= payload_read_data; + empty_payload_list_head_next <= resize(unsigned(payload_read_data), PAYLOAD_MEMORY_ADDR_WIDTH); -- First Sample if (newest_sample = SAMPLE_MEMORY_MAX_ADDRESS) then @@ -1613,7 +1656,7 @@ begin -- Fix Next Pointer sample_valid_in <= '1'; sample_addr <= prev_sample + SMF_NEXT_ADDR_OFFSET; - sample_write_data <= empty_sample_list_head; + sample_write_data <= std_logic_vector(resize(empty_sample_list_head, WORD_WIDTH)); -- Memory Flow Control Guard if (sample_ready_in = '1') then @@ -1633,7 +1676,7 @@ begin -- Fix Previous Pointer sample_valid_in <= '1'; sample_addr <= next_sample + SMF_PREV_ADDR_OFFSET; - sample_write_data <= empty_sample_list_head; + sample_write_data <= std_logic_vector(resize(empty_sample_list_head, WORD_WIDTH)); -- Memory Flow Control Guard if (sample_ready_in = '1') then @@ -1662,7 +1705,7 @@ begin -- Write Instance Pointer sample_valid_in <= '1'; sample_addr <= cur_sample + SMF_INSTANCE_ADDR_OFFSET; - sample_write_data <= cur_inst; + sample_write_data <= std_logic_vector(resize(cur_inst, WORD_WIDTH)); -- Memory Flow Control Guard if (sample_ready_in = '1') then @@ -1673,7 +1716,7 @@ begin -- Write Previous Pointer sample_valid_in <= '1'; sample_addr <= cur_sample + SMF_PREV_ADDR_OFFSET; - sample_write_data <= prev_sample; + sample_write_data <= std_logic_vector(resize(prev_sample, WORD_WIDTH)); -- Memory Flow Control Guard if (sample_ready_in = '1') then @@ -1684,7 +1727,7 @@ begin -- Write Next Pointer sample_valid_in <= '1'; sample_addr <= cur_sample + SMF_NEXT_ADDR_OFFSET; - sample_write_data <= next_sample; + sample_write_data <= std_logic_vector(resize(next_sample, WORD_WIDTH)); -- Memory Flow Control Guard if (sample_ready_in = '1') then @@ -1699,7 +1742,7 @@ begin if (sample_valid_out = '1') then -- Fix new Empty List Head - empty_sample_list_head_next <= sample_read_data; + empty_sample_list_head_next <= resize(unsigned(sample_read_data), SAMPLE_MEMORY_ADDR_WIDTH); -- If newest Sample is now previous, select current sample as new newest if (newest_sample = prev_sample) then @@ -1723,13 +1766,16 @@ begin if (WITH_KEY and remove_oldest_inst_sample = '1') then cur_sample <= oldest_sample; stage_next <= FIND_OLDEST_INST_SAMPLE; + cnt_next <= 0; elsif (remove_oldest_sample = '1') then -- Synthesis Guard if (WITH_KEY) then stage_next <= GET_OLDEST_SAMPLE_INSTANCE; + cnt_next <= 0; else cur_sample_next <= oldest_sample; stage_next <= REMOVE_SAMPLE; + cnt_next <= 0; end if; else -- DONE @@ -1767,10 +1813,11 @@ begin inst_op_start <= '1'; inst_opcode <= SEARCH_INSTANCE_ADDR; inst_mem_fields <= IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_ACK_CNT_FLAG; - inst_addr_update <= sample_read_data; + inst_addr_update <= resize(unsigned(sample_read_data), INSTANCE_MEMORY_ADDR_WIDTH); cur_sample_next <= oldest_sample; stage_next <= REMOVE_SAMPLE; + cnt_next <= 0; end if; end if; when others => @@ -1804,26 +1851,27 @@ begin cnt_next <= cnt + 1; end if; -- READ Instance Pointer - when 1 => + when 2 => sample_ready_out <= '1'; -- Memory Flow Control Guard if (sample_valid_out = '1') then -- Oldest Instance Sample Found - if (sample_read_data = cur_inst) then + if (resize(unsigned(sample_read_data),INSTANCE_MEMORY_ADDR_WIDTH) = cur_inst) then stage_next <= REMOVE_SAMPLE; + cnt_next <= 0; sample_abort_read <= '1'; else cnt_next <= cnt + 1; end if; end if; -- READ Next Sample - when 2 => + when 3 => sample_ready_out <= '1'; -- Memory Flow Control Guard if (sample_valid_out = '1') then - cur_sample_next <= sample_read_data; + cur_sample_next <= resize(unsigned(sample_read_data), SAMPLE_MEMORY_ADDR_WIDTH); cnt_next <= 0; end if; when others => @@ -1856,7 +1904,7 @@ begin -- Memory Flow Control Guard if (sample_valid_out = '1') then -- Sample is Orphan - if (sample_read_data = dead_inst) then + if (resize(unsigned(sample_read_data),INSTANCE_MEMORY_ADDR_WIDTH) = dead_inst) then -- Remove Orphan Sample stage_next <= REMOVE_SAMPLE; cnt_next <= 0; @@ -1871,13 +1919,13 @@ begin -- Memory Flow Control Guard if (sample_valid_out = '1') then -- End of Samples - if (sample_read_data = SAMPLE_MEMORY_MAX_ADDRESS) then + if (resize(unsigned(sample_read_data),SAMPLE_MEMORY_ADDR_WIDTH) = SAMPLE_MEMORY_MAX_ADDRESS) then -- DONE orphan_samples_next <= '0'; stage_next <= IDLE; else -- Continue - cur_sample_next <= sample_read_data; + cur_sample_next <= resize(unsigned(sample_read_data),SAMPLE_MEMORY_ADDR_WIDTH); cnt_next <= 0; end if; end if; @@ -1945,7 +1993,7 @@ begin sample_ready_out <= '1'; -- Memory Flow Control Guard if (sample_valid_out = '1') then - prev_sample_next <= sample_read_data; + prev_sample_next <= resize(unsigned(sample_read_data),SAMPLE_MEMORY_ADDR_WIDTH); cnt_next <= cnt + 1; end if; -- READ Next Sample @@ -1953,7 +2001,7 @@ begin sample_ready_out <= '1'; -- Memory Flow Control Guard if (sample_valid_out = '1') then - next_sample_next <= sample_read_data; + next_sample_next <= resize(unsigned(sample_read_data),SAMPLE_MEMORY_ADDR_WIDTH); -- Sample Memory Full if (empty_sample_list_head = SAMPLE_MEMORY_MAX_ADDRESS) then @@ -1969,7 +2017,7 @@ begin -- Add Current Sample after Empty List Tail sample_valid_in <= '1'; sample_addr <= empty_sample_list_tail + SMF_NEXT_ADDR_OFFSET; - sample_write_data <= cur_sample; + sample_write_data <= std_logic_vector(resize(cur_sample,WORD_WIDTH)); -- Memory Flow Control Guard if (sample_ready_in = '1') then @@ -1980,7 +2028,7 @@ begin -- Make Current Sample Empty List Tail sample_valid_in <= '1'; sample_addr <= cur_sample + SMF_NEXT_ADDR_OFFSET; - sample_write_data <= INSTANCE_MEMORY_MAX_ADDRESS; + sample_write_data <= std_logic_vector(resize(INSTANCE_MEMORY_MAX_ADDRESS,WORD_WIDTH)); -- Memory Flow Control Guard if (sample_ready_in = '1') then @@ -2016,7 +2064,7 @@ begin -- Remove link to cur_sample sample_valid_in <= '1'; sample_addr <= next_sample + SMF_PREV_ADDR_OFFSET; - sample_write_data <= prev_sample; + sample_write_data <= std_logic_vector(resize(prev_sample,WORD_WIDTH)); -- Memory Flow Control Guard if (sample_ready_in = '1') then @@ -2037,7 +2085,7 @@ begin -- Remove link to cur_sample sample_valid_in <= '1'; sample_addr <= prev_sample + SMF_NEXT_ADDR_OFFSET; - sample_write_data <= next_sample; + sample_write_data <= std_logic_vector(resize(next_sample,WORD_WIDTH)); -- Memory Flow Control Guard if (sample_ready_in = '1') then @@ -2049,17 +2097,17 @@ begin -- Memory Flow Control Guard if (sample_valid_out = '1') then - cur_payload_next <= sample_read_data; + cur_payload_next <= resize(unsigned(sample_read_data),PAYLOAD_MEMORY_ADDR_WIDTH); -- Sample has no Data - if (sample_read_data = PAYLOAD_MEMORY_MAX_ADDRESS) then + if (resize(unsigned(sample_read_data),PAYLOAD_MEMORY_ADDR_WIDTH) = PAYLOAD_MEMORY_MAX_ADDRESS) then stage_next <= POST_SAMPLE_REMOVE; -- Payload Memory Full elsif (empty_payload_list_head = PAYLOAD_MEMORY_MAX_ADDRESS) then - empty_payload_list_head_next <= sample_read_data; + empty_payload_list_head_next <= resize(unsigned(sample_read_data),PAYLOAD_MEMORY_ADDR_WIDTH); stage_next <= POST_SAMPLE_REMOVE; else - empty_payload_list_head_next <= sample_read_data; + empty_payload_list_head_next <= resize(unsigned(sample_read_data),PAYLOAD_MEMORY_ADDR_WIDTH); cnt_next <= cnt + 1; end if; end if; @@ -2080,10 +2128,10 @@ begin -- Memory Flow Control Guard if (payload_valid_out = '1') then -- Found Empty List Tail - if (payload_read_data = PAYLOAD_MEMORY_MAX_ADDRESS) then + if (resize(unsigned(payload_read_data),PAYLOAD_MEMORY_ADDR_WIDTH) = PAYLOAD_MEMORY_MAX_ADDRESS) then cnt_next <= cnt + 1; else - cur_payload_next <= payload_read_data; + cur_payload_next <= resize(unsigned(payload_read_data),PAYLOAD_MEMORY_ADDR_WIDTH); cnt_next <= cnt - 1; end if; end if; @@ -2091,7 +2139,7 @@ begin when 14 => payload_valid_in <= '1'; payload_addr <= cur_payload + PMF_NEXT_ADDR_OFFSET; - payload_write_data <= empty_payload_list_head; + payload_write_data <= std_logic_vector(resize(empty_payload_list_head,WORD_WIDTH)); -- Memory Flow Control Guard if (payload_ready_in = '1') then @@ -2291,48 +2339,22 @@ begin end if; -- READ Sequence Number 1/2 when 2 => + sample_ready_out <= '1'; -- Memory Flow Control Guard if (sample_valid_out = '1') then - data_out_rtps <= sample_read_data; - valid_out_rtps <= '1'; - -- Input Guard - if (ready_out_rtps = '1') then - sample_ready_out <= '1'; - cnt_next <= cnt + 1; - end if; + cc_seq_nr_sig_next(0) <= unsigned(sample_read_data); + cnt_next <= cnt + 1; end if; -- READ Sequence Number 2/2 when 3 => + sample_ready_out <= '1'; -- Memory Flow Control Guard if (sample_valid_out = '1') then - data_out_rtps <= sample_read_data; - valid_out_rtps <= '1'; - -- Input Guard - if (ready_out_rtps = '1') then - sample_ready_out <= '1'; - cnt_next <= cnt + 3; -- Skip Special Sequence Number - end if; - end if; - -- Special Sequence Number 1/2 - when 4 => - data_out_rtps <= SEQUENCENUMBER_UNKNOWN(0); - valid_out_rtps <= '1'; - -- Input Guard - if (ready_out_rtps = '1') then - sample_ready_out <= '1'; - cnt_next <= cnt + 1; - end if; - -- Special Sequence Number 2/2 - when 5 => - data_out_rtps <= SEQUENCENUMBER_UNKNOWN(1); - valid_out_rtps <= '1'; - -- Input Guard - if (ready_out_rtps = '1') then - sample_ready_out <= '1'; + cc_seq_nr_sig_next(1) <= unsigned(sample_read_data); cnt_next <= cnt + 1; end if; -- Return Code - when 6 => + when 4 => done_rtps <= '1'; ret_rtps <= OK; @@ -2390,7 +2412,7 @@ begin -- Memory Flow Control Guard if (sample_valid_out = '1') then - prev_sample_next <= sample_read_data; + prev_sample_next <= resize(unsigned(sample_read_data),SAMPLE_MEMORY_ADDR_WIDTH); cnt_next <= cnt + 1; end if; -- READ Sequence Number 1/2 @@ -2400,7 +2422,7 @@ begin -- Memory Flow Control Guard if (sample_valid_out = '1') then -- No Match - if (sample_read_data /= seq_nr(0)) then + if (unsigned(sample_read_data) /= seq_nr(0)) then sample_abort_read <= '1'; -- End of Samples if (prev_sample = SAMPLE_MEMORY_MAX_ADDRESS) then @@ -2423,7 +2445,7 @@ begin -- Memory Flow Control Guard if (sample_valid_out = '1') then -- No Match - if (sample_read_data /= seq_nr(1)) then + if (unsigned(sample_read_data) /= seq_nr(1)) then sample_abort_read <= '1'; -- End of Samples if (prev_sample = SAMPLE_MEMORY_MAX_ADDRESS) then @@ -2445,7 +2467,7 @@ begin -- Memory Flow Control Guard if (sample_valid_out = '1') then - cur_inst_next <= sample_read_data; + cur_inst_next <= resize(unsigned(sample_read_data),INSTANCE_MEMORY_ADDR_WIDTH); cnt_next <= cnt + 1; end if; -- Check Result @@ -2590,7 +2612,7 @@ begin -- can still be Unregistered, but not the other way around. if (sample_read_data(SSI_UNREGISTERED_FLAG) = '1') then cc_kind_sig_next <= NOT_ALIVE_UNREGISTERED; - elsif (sample_read_data(SSI_DISPOSED_FLAG) = '1') + elsif (sample_read_data(SSI_DISPOSED_FLAG) = '1') then cc_kind_sig_next <= NOT_ALIVE_DISPOSED; else cc_kind_sig_next <= ALIVE; @@ -2605,7 +2627,7 @@ begin sample_ready_out <= '1'; -- Memory Flow Control Guard if (sample_valid_out = '1') then - cc_source_timestamp_sig_next(0) <= sample_read_data; + cc_source_timestamp_sig_next(0) <= unsigned(sample_read_data); cnt_next <= cnt + 1; end if; @@ -2614,7 +2636,7 @@ begin sample_ready_out <= '1'; -- Memory Flow Control Guard if (sample_valid_out = '1') then - cc_source_timestamp_sig_next(1) <= sample_read_data; + cc_source_timestamp_sig_next(1) <= unsigned(sample_read_data); cnt_next <= cnt + 1; end if; @@ -2623,7 +2645,7 @@ begin sample_ready_out <= '1'; -- Memory Flow Control Guard if (sample_valid_out = '1') then - cur_payload_next <= sample_read_data; + cur_payload_next <= resize(unsigned(sample_read_data),PAYLOAD_MEMORY_ADDR_WIDTH); cnt_next <= cnt + 1; end if; @@ -2642,8 +2664,16 @@ begin -- RTPS Requestes Payload if (get_data_rtps = '1') then - -- Get Payload - stage_next <= GET_PAYLOAD; + if (cur_payload /= INSTANCE_MEMORY_MAX_ADDRESS) then + -- Get Payload + stage_next <= GET_PAYLOAD; + cnt_next <= 0; + cnt2_next <= 0; + cnt3_next <= 0; + else + assert FALSE report "Payload Requested, while no Payload available" severity FAILURE; + stage_next <= IDLE; + end if; else -- DONE stage_next <= IDLE; @@ -2679,15 +2709,15 @@ begin -- Memory Flow Control Guard if (payload_valid_out = '1') then - next_payload_next <= payload_read_data; - cnt2 <= 1; + next_payload_next <= resize(unsigned(payload_read_data),PAYLOAD_MEMORY_ADDR_WIDTH); + cnt2_next <= 1; -- Last Payload Slot is unaligned - if (payload_read_data = PAYLOAD_MEMORY_MAX_ADDRESS and sample_status_info(SSI_ALIGNED_FLAG) = '0') then - cnt_next <= cnt + 1 + if (resize(unsigned(payload_read_data),PAYLOAD_MEMORY_ADDR_WIDTH) = PAYLOAD_MEMORY_MAX_ADDRESS and sample_status_info(SSI_ALIGNED_FLAG) = '0') then + cnt_next <= cnt + 1; else cnt_next <= cnt + 3; - long_latch_next <= PAYLOAD_FRAME_SIZE-1; + long_latch_next <= std_logic_vector(to_unsigned(PAYLOAD_FRAME_SIZE-1,CDR_LONG_WIDTH)); end if; end if; -- GET Payload Offset @@ -2738,22 +2768,19 @@ begin null; end case; - -- Placeholder Pre-Mapping - ready_out_tmp := skg_ready_in when (cc_kind_sig /= ALIVE) else ready_out_rtps; - -- Data available for Output if (cnt3 /= 0) then -- Memory Flow Control Guard if (payload_valid_out = '1') then - valid_out_tmp := '1'; + valid_out_dds <= '1'; -- End of Payload if (cnt3 = 1 and cnt = 4) then - last_word_out_tmp := '1'; + last_word_out_dds <= '1'; end if; -- DDS Read - if (ready_out_tmp = '1') then + if (ready_out_dds = '1') then payload_ready_out <= '1'; -- NOTE: We are using the tmp_bool variable to signal if there is an increment -- on the same clock cycle. @@ -2768,38 +2795,8 @@ begin -- Finished Reading elsif (cnt = 4) then assert (cnt3 = 0) severity FAILURE; - -- Need to push Serialized Key - if (cc_kind_sig /= ALIVE) then - stage_next <= GET_SERIALIZED_KEY; - else - -- DONE - stage_next <= IDLE; - end if; - end if; - - -- Placeholder Post-Mapping - if (cc_kind_sig /= ALIVE) then - skg_valid_out <= valid_out_tmp; - skg_last_word_out <= last_word_out_tmp; - else - valid_out_rtps <= valid_out_tmp; - last_word_out_rtps <= last_word_out_tmp; - end if; - when GET_SERIALIZED_KEY => - if (skg_valid_out = '1') then - valid_out_rtps <= '1'; - data_out_rtps <= skg_data_out; - last_word_out_rtps <= skg_last_word_out; - -- Output Guard - if (ready_out_rtps = '1') then - skg_ready_out <= '1'; - - -- Exit Condition - if (skg_last_word_out = '1') then - -- DONE - stage_next <= IDLE; - end if; - end if; + -- DONE + stage_next <= IDLE; end if; when CHECK_LIFESPAN => -- Precondition: cur_sample set, @@ -2851,7 +2848,7 @@ begin -- Memory Control Flow Guard if (sample_valid_out = '1') then - next_sample_next <= sample_read_data; + next_sample_next <= resize(unsigned(sample_read_data),SAMPLE_MEMORY_ADDR_WIDTH); cnt_next <= cnt + 1; end if; -- READ Lifespan 1/2 @@ -2905,7 +2902,7 @@ begin inst_op_start <= '1'; inst_opcode <= GET_INSTANCE; inst_mem_fields <= IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_ACK_CNT_FLAG; - inst_addr_update <= sample_read_data; + inst_addr_update <= resize(unsigned(sample_read_data),INSTANCE_MEMORY_ADDR_WIDTH); -- Remove Sample stage_next <= REMOVE_SAMPLE; @@ -2919,7 +2916,7 @@ begin case (cnt) is -- Total Count when 0 => - data_out_dds <= liveliness_lost_cnt; + data_out_dds <= std_logic_vector(liveliness_lost_cnt); valid_out_dds <= '1'; if (ready_out_dds = '1') then @@ -2927,7 +2924,7 @@ begin end if; -- Total Count Change when 1 => - data_out_dds <= liveliness_lost_cnt_change; + data_out_dds <= std_logic_vector(liveliness_lost_cnt_change); valid_out_dds <= '1'; if (ready_out_dds = '1') then @@ -2943,7 +2940,7 @@ begin if (ready_out_dds = '1') then -- Reset - status_sig_next(LIVELINESS_LOST_STATUS) <= '0'; + status_sig_next <= status_sig and (not LIVELINESS_LOST_STATUS); -- DONE stage_next <= IDLE; @@ -2955,7 +2952,7 @@ begin case (cnt) is -- Total Count when 0 => - data_out_dds <= deadline_miss_cnt; + data_out_dds <= std_logic_vector(deadline_miss_cnt); valid_out_dds <= '1'; if (ready_out_dds = '1') then @@ -2963,7 +2960,7 @@ begin end if; -- Total Count Change when 1 => - data_out_dds <= deadline_miss_cnt_change; + data_out_dds <= std_logic_vector(deadline_miss_cnt_change); valid_out_dds <= '1'; if (ready_out_dds = '1') then @@ -3007,7 +3004,7 @@ begin return_code_dds <= RETCODE_OK; if (ready_out_dds = '1') then -- Reset - status_sig_next(OFFERED_DEADLINE_MISSED_STATUS) <= '0'; + status_sig_next <= status_sig and (not OFFERED_DEADLINE_MISSED_STATUS); -- DONE stage_next <= IDLE; @@ -3051,7 +3048,7 @@ begin cnt_next <= 1; else -- Update Requested Deadline Missed Status - status_sig_next(OFFERED_DEADLINE_MISSED_STATUS) <= '1'; + status_sig_next <= status_sig and OFFERED_DEADLINE_MISSED_STATUS; deadline_miss_cnt_next <= deadline_miss_cnt + 1; deadline_miss_cnt_change_next <= deadline_miss_cnt_change + 1; deadline_miss_last_inst_next <= inst_data.key_hash; @@ -3074,7 +3071,7 @@ begin when 1 => sample_valid_in <= '1'; sample_addr <= cur_sample + SMF_PREV_ADDR_OFFSET; - sample_write_data <= prev_sample; + sample_write_data <= std_logic_vector(resize(prev_sample,WORD_WIDTH)); -- Memory Flow Control Guard if (sample_ready_in = '1') then @@ -3085,9 +3082,9 @@ begin sample_valid_in <= '1'; sample_addr <= cur_sample + SMF_NEXT_ADDR_OFFSET; if (cur_sample = MAX_SAMPLE_ADDRESS) then - sample_write_data <= SAMPLE_MEMORY_MAX_ADDRESS; + sample_write_data <= std_logic_vector(resize(SAMPLE_MEMORY_MAX_ADDRESS,WORD_WIDTH)); else - sample_write_data <= cur_sample + SAMPLE_FRAME_SIZE; + sample_write_data <= std_logic_vector(resize(cur_sample + SAMPLE_FRAME_SIZE,WORD_WIDTH)); end if; -- Memory Flow Control Guard @@ -3117,9 +3114,9 @@ begin payload_valid_in <= '1'; payload_addr <= cur_payload + PMF_NEXT_ADDR_OFFSET; if (cur_payload = MAX_PAYLOAD_ADDRESS) then - payload_write_data <= PAYLOAD_MEMORY_MAX_ADDRESS; + payload_write_data <= std_logic_vector(resize(PAYLOAD_MEMORY_MAX_ADDRESS,WORD_WIDTH)); else - payload_write_data <= cur_payload + PAYLOAD_FRAME_SIZE; + payload_write_data <= std_logic_vector(resize(cur_payload + PAYLOAD_FRAME_SIZE,WORD_WIDTH)); end if; -- Memory Flow Control Guard @@ -3176,7 +3173,7 @@ begin inst_write_data <= (others => '0'); - case (mem_stage) is + case (inst_stage) is when IDLE => inst_op_done <= '1'; @@ -3226,13 +3223,18 @@ begin inst_addr_base_next <= inst_occupied_head; inst_stage_next <= FIND_POS; inst_cnt_next <= 0; + -- Set Instance Data + inst_data_next.key_hash <= key_hash_next; + inst_data_next.status_info <= status_info_update; + inst_data_next.sample_cnt <= sample_cnt; + inst_data_next.ack_cnt <= ack_cnt; when UPDATE_INSTANCE => inst_stage_next <= UPDATE_INSTANCE; - if check_mask(inst_latch_data.field_flag,IMF_STATUS_FLAG) then + if check_mask(inst_mem_fields,IMF_STATUS_FLAG) then inst_cnt_next <= 0; - elsif check_mask(inst_latch_data.field_flag,IMF_SAMPLE_CNT_FLAG) then + elsif check_mask(inst_mem_fields,IMF_SAMPLE_CNT_FLAG) then inst_cnt_next <= 1; - elsif check_mask(inst_latch_data.field_flag,IMF_ACK_CNT_FLAG) then + elsif check_mask(inst_mem_fields,IMF_ACK_CNT_FLAG) then inst_cnt_next <= 2; else -- DONE @@ -3248,21 +3250,14 @@ begin -- Get Instance Data inst_data_next <= ZERO_INSTANCE_DATA; inst_stage_next <= GET_INSTANCE_DATA; - if check_mask(inst_mem_fields.field_flag,IMF_KEY_HASH_FLAG) then + if check_mask(inst_mem_fields,IMF_KEY_HASH_FLAG) then inst_cnt_next <= 0; - elsif check_mask(inst_mem_fields.field_flag,IMF_STATUS_FLAG) then + elsif check_mask(inst_mem_fields,IMF_STATUS_FLAG) then inst_cnt_next <= 4; - elsif check_mask(inst_mem_fields.field_flag,IMF_SAMPLE_CNT_FLAG) then + elsif check_mask(inst_mem_fields,IMF_SAMPLE_CNT_FLAG) then inst_cnt_next <= 5; - elsif check_mask(inst_mem_fields.field_flag,IMF_DISPOSED_CNT_FLAG) then + elsif check_mask(inst_mem_fields,IMF_ACK_CNT_FLAG) then inst_cnt_next <= 6; - elsif check_mask(inst_mem_fields.field_flag,IMF_NO_WRITERS_CNT_FLAG) then - inst_cnt_next <= 7; - elsif (TIME_BASED_FILTER_QOS /= DURATION_ZERO and check_mask(inst_mem_fields.field_flag,IMF_IGNORE_DEADLINE_FLAG)) then - inst_cnt_next <= 8; - elsif check_mask(inst_mem_fields.field_flag,IMF_WRITER_BITMAP_FLAG) then - inst_cnt_next <= 10; - inst_cnt2_next <= 0; else -- DONE inst_stage_next <= IDLE; @@ -3286,32 +3281,18 @@ begin -- Get Instance Data inst_data_next <= ZERO_INSTANCE_DATA; inst_stage_next <= GET_INSTANCE_DATA; - if check_mask(inst_mem_fields.field_flag,IMF_KEY_HASH_FLAG) then + if check_mask(inst_mem_fields,IMF_KEY_HASH_FLAG) then inst_cnt_next <= 0; - elsif check_mask(inst_mem_fields.field_flag,IMF_STATUS_FLAG) then + elsif check_mask(inst_mem_fields,IMF_STATUS_FLAG) then inst_cnt_next <= 4; - elsif check_mask(inst_mem_fields.field_flag,IMF_SAMPLE_CNT_FLAG) then + elsif check_mask(inst_mem_fields,IMF_SAMPLE_CNT_FLAG) then inst_cnt_next <= 5; - elsif check_mask(inst_mem_fields.field_flag,IMF_DISPOSED_CNT_FLAG) then + elsif check_mask(inst_mem_fields,IMF_ACK_CNT_FLAG) then inst_cnt_next <= 6; - elsif check_mask(inst_mem_fields.field_flag,IMF_NO_WRITERS_CNT_FLAG) then - inst_cnt_next <= 7; - elsif (TIME_BASED_FILTER_QOS /= DURATION_ZERO and check_mask(inst_mem_fields.field_flag,IMF_IGNORE_DEADLINE_FLAG)) then - inst_cnt_next <= 8; - elsif check_mask(inst_mem_fields.field_flag,IMF_WRITER_BITMAP_FLAG) then - inst_cnt_next <= 10; - inst_cnt2_next <= 0; else -- DONE inst_stage_next <= IDLE; end if; - when UNMARK_INSTANCES => - -- Empty Memory Guard - if (inst_occupied_head /= INSTANCE_MEMORY_MAX_ADDRESS) then - inst_addr_base_next <= inst_occupied_head; - inst_stage_next <= UNMARK_INSTANCES; - inst_cnt_next <= 0; - end if; when others => null; end case; @@ -3375,7 +3356,7 @@ begin -- Memory Flow Control Guard if (inst_valid_out = '1') then - inst_next_addr_base_next <= inst_read_data; + inst_next_addr_base_next <= resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH); inst_cnt_next <= inst_cnt + 1; end if; -- READ Key Hash 1/4 @@ -3474,13 +3455,13 @@ begin -- Get Instance Data inst_data_next <= ZERO_INSTANCE_DATA; inst_stage_next <= GET_INSTANCE_DATA; - if check_mask(inst_latch_data.field_flag,IMF_KEY_HASH_FLAG) then + if check_mask(inst_latch_data.field_flags,IMF_KEY_HASH_FLAG) then inst_cnt_next <= 0; - elsif check_mask(inst_latch_data.field_flag,IMF_STATUS_FLAG) then + elsif check_mask(inst_latch_data.field_flags,IMF_STATUS_FLAG) then inst_cnt_next <= 4; - elsif check_mask(inst_latch_data.field_flag,IMF_SAMPLE_CNT_FLAG) then + elsif check_mask(inst_latch_data.field_flags,IMF_SAMPLE_CNT_FLAG) then inst_cnt_next <= 5; - elsif check_mask(inst_latch_data.field_flag,IMF_ACK_CNT_FLAG) then + elsif check_mask(inst_latch_data.field_flags,IMF_ACK_CNT_FLAG) then inst_cnt_next <= 6; else -- DONE @@ -3511,20 +3492,20 @@ begin -- Memory Flow Control Guard if (inst_valid_out = '1') then inst_prev_addr_base_next <= inst_addr_base; - inst_addr_base_next <= inst_read_data; + inst_addr_base_next <= resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH); -- Match - if (inst_read_data = inst_latch_data.addr) then + if (resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH) = inst_latch_data.addr) then -- Get Instance Data inst_stage_next <= GET_INSTANCE_DATA; inst_data_next <= ZERO_INSTANCE_DATA; - if check_mask(inst_latch_data.field_flag,IMF_KEY_HASH_FLAG) then + if check_mask(inst_latch_data.field_flags,IMF_KEY_HASH_FLAG) then inst_cnt_next <= 0; - elsif check_mask(inst_latch_data.field_flag,IMF_STATUS_FLAG) then + elsif check_mask(inst_latch_data.field_flags,IMF_STATUS_FLAG) then inst_cnt_next <= 4; - elsif check_mask(inst_latch_data.field_flag,IMF_SAMPLE_CNT_FLAG) then + elsif check_mask(inst_latch_data.field_flags,IMF_SAMPLE_CNT_FLAG) then inst_cnt_next <= 5; - elsif check_mask(inst_latch_data.field_flag,IMF_ACK_CNT_FLAG) then + elsif check_mask(inst_latch_data.field_flags,IMF_ACK_CNT_FLAG) then inst_cnt_next <= 6; else -- DONE @@ -3533,7 +3514,7 @@ begin -- No Match else -- Reached List Tail, No Match - if (inst_read_data = INSTANCE_MEMORY_MAX_ADDRESS) then + if (resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH) = INSTANCE_MEMORY_MAX_ADDRESS) then inst_addr_base_next <= INSTANCE_MEMORY_MAX_ADDRESS; --No match -- DONE inst_stage_next <= IDLE; @@ -3564,17 +3545,17 @@ begin -- Memory Flow Control Guard if (inst_valid_out = '1') then - inst_next_addr_base_next <= inst_read_data; + inst_next_addr_base_next <= resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH); -- Get Instance Data inst_data_next <= ZERO_INSTANCE_DATA; inst_stage_next <= GET_INSTANCE_DATA; - if check_mask(inst_latch_data.field_flag,IMF_KEY_HASH_FLAG) then + if check_mask(inst_latch_data.field_flags,IMF_KEY_HASH_FLAG) then inst_cnt_next <= 0; - elsif check_mask(inst_latch_data.field_flag,IMF_STATUS_FLAG) then + elsif check_mask(inst_latch_data.field_flags,IMF_STATUS_FLAG) then inst_cnt_next <= 4; - elsif check_mask(inst_latch_data.field_flag,IMF_SAMPLE_CNT_FLAG) then + elsif check_mask(inst_latch_data.field_flags,IMF_SAMPLE_CNT_FLAG) then inst_cnt_next <= 5; - elsif check_mask(inst_latch_data.field_flag,IMF_ACK_CNT_FLAG) then + elsif check_mask(inst_latch_data.field_flags,IMF_ACK_CNT_FLAG) then inst_cnt_next <= 6; else -- DONE @@ -3624,11 +3605,11 @@ begin -- Memory Flow Control Guard if (inst_ready_in = '1') then - if check_mask(inst_latch_data.field_flag,IMF_STATUS_FLAG) then + if check_mask(inst_latch_data.field_flags,IMF_STATUS_FLAG) then inst_cnt_next <= 4; - elsif check_mask(inst_latch_data.field_flag,IMF_SAMPLE_CNT_FLAG) then + elsif check_mask(inst_latch_data.field_flags,IMF_SAMPLE_CNT_FLAG) then inst_cnt_next <= 5; - elsif check_mask(inst_latch_data.field_flag,IMF_ACK_CNT_FLAG) then + elsif check_mask(inst_latch_data.field_flags,IMF_ACK_CNT_FLAG) then inst_cnt_next <= 6; else inst_cnt_next <= 7; @@ -3642,12 +3623,12 @@ begin -- Memory Flow Control Guard if (inst_ready_in = '1') then - if check_mask(inst_latch_data.field_flag,IMF_SAMPLE_CNT_FLAG) then + if check_mask(inst_latch_data.field_flags,IMF_SAMPLE_CNT_FLAG) then inst_cnt_next <= 5; - elsif check_mask(inst_latch_data.field_flag,IMF_ACK_CNT_FLAG) then + elsif check_mask(inst_latch_data.field_flags,IMF_ACK_CNT_FLAG) then inst_cnt_next <= 6; else - if check_mask(inst_latch_data.field_flag,IMF_KEY_HASH_FLAG) then + if check_mask(inst_latch_data.field_flags,IMF_KEY_HASH_FLAG) then inst_cnt_next <= 7; else inst_cnt_next <= 11; @@ -3662,12 +3643,12 @@ begin -- Memory Flow Control Guard if (inst_ready_in = '1') then - if check_mask(inst_latch_data.field_flag,IMF_ACK_CNT_FLAG) then + if check_mask(inst_latch_data.field_flags,IMF_ACK_CNT_FLAG) then inst_cnt_next <= 6; else - if check_mask(inst_latch_data.field_flag,IMF_KEY_HASH_FLAG) then + if check_mask(inst_latch_data.field_flags,IMF_KEY_HASH_FLAG) then inst_cnt_next <= 7; - elsif check_mask(inst_latch_data.field_flag,IMF_STATUS_FLAG) then + elsif check_mask(inst_latch_data.field_flags,IMF_STATUS_FLAG) then inst_cnt_next <= 11; else inst_cnt_next <= 12; @@ -3682,11 +3663,11 @@ begin -- Memory Flow Control Guard if (inst_ready_in = '1') then - if check_mask(inst_latch_data.field_flag,IMF_KEY_HASH_FLAG) then + if check_mask(inst_latch_data.field_flags,IMF_KEY_HASH_FLAG) then inst_cnt_next <= 7; - elsif check_mask(inst_latch_data.field_flag,IMF_STATUS_FLAG) then + elsif check_mask(inst_latch_data.field_flags,IMF_STATUS_FLAG) then inst_cnt_next <= 11; - elsif check_mask(inst_latch_data.field_flag,IMF_SAMPLE_CNT_FLAG) then + elsif check_mask(inst_latch_data.field_flags,IMF_SAMPLE_CNT_FLAG) then inst_cnt_next <= 12; else inst_cnt_next <= 13; @@ -3727,11 +3708,11 @@ begin if (inst_valid_out = '1') then inst_latch_data_next.key_hash(3) <= inst_read_data; - if check_mask(inst_latch_data.field_flag,IMF_STATUS_FLAG) then + if check_mask(inst_latch_data.field_flags,IMF_STATUS_FLAG) then inst_cnt_next <= 11; - elsif check_mask(inst_latch_data.field_flag,IMF_SAMPLE_CNT_FLAG) then + elsif check_mask(inst_latch_data.field_flags,IMF_SAMPLE_CNT_FLAG) then inst_cnt_next <= 12; - elsif check_mask(inst_latch_data.field_flag,IMF_ACK_CNT_FLAG) then + elsif check_mask(inst_latch_data.field_flags,IMF_ACK_CNT_FLAG) then inst_cnt_next <= 13; else -- DONE @@ -3746,9 +3727,9 @@ begin if (inst_valid_out = '1') then inst_latch_data_next.status_info <= inst_read_data; - if check_mask(inst_latch_data.field_flag,IMF_SAMPLE_CNT_FLAG) then + if check_mask(inst_latch_data.field_flags,IMF_SAMPLE_CNT_FLAG) then inst_cnt_next <= 12; - elsif check_mask(inst_latch_data.field_flag,IMF_ACK_CNT_FLAG) then + elsif check_mask(inst_latch_data.field_flags,IMF_ACK_CNT_FLAG) then inst_cnt_next <= 13; else -- DONE @@ -3761,9 +3742,9 @@ begin -- Memory Flow Control Guard if (inst_valid_out = '1') then - inst_latch_data_next.sample_cnt <= inst_read_data; + inst_latch_data_next.sample_cnt <= unsigned(inst_read_data); - if check_mask(inst_latch_data.field_flag,IMF_ACK_CNT_FLAG) then + if check_mask(inst_latch_data.field_flags,IMF_ACK_CNT_FLAG) then inst_cnt_next <= 13; else -- DONE @@ -3776,7 +3757,7 @@ begin -- Memory Flow Control Guard if (inst_valid_out = '1') then - inst_latch_data_next.ack_cnt <= inst_read_data; + inst_latch_data_next.ack_cnt <= unsigned(inst_read_data); -- DONE inst_stage_next <= IDLE; @@ -3844,7 +3825,7 @@ begin -- Memory Flow Control Guard if (inst_valid_out = '1') then - inst_next_addr_base_next <= inst_read_data; + inst_next_addr_base_next <= resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH); inst_cnt_next <= inst_cnt + 1; end if; -- READ Key Hash 1/4 @@ -3858,7 +3839,7 @@ begin inst_next_addr_base_next <= inst_addr_base; -- Occupied List Head if (inst_prev_addr_base = INSTANCE_MEMORY_MAX_ADDRESS) then - assert (inst_addr_base = inst_occupied_head) + assert (inst_addr_base = inst_occupied_head) severity FAILURE; inst_occupied_head_next <= inst_empty_head; inst_addr_base_next <= inst_empty_head; @@ -3889,7 +3870,7 @@ begin inst_next_addr_base_next <= inst_addr_base; -- Occupied List Head if (inst_prev_addr_base = INSTANCE_MEMORY_MAX_ADDRESS) then - assert (inst_addr_base = inst_occupied_head) + assert (inst_addr_base = inst_occupied_head) severity FAILURE; inst_occupied_head_next <= inst_empty_head; inst_addr_base_next <= inst_empty_head; @@ -3920,7 +3901,7 @@ begin inst_next_addr_base_next <= inst_addr_base; -- Occupied List Head if (inst_prev_addr_base = INSTANCE_MEMORY_MAX_ADDRESS) then - assert (inst_addr_base = inst_occupied_head) + assert (inst_addr_base = inst_occupied_head) severity FAILURE; inst_occupied_head_next <= inst_empty_head; inst_addr_base_next <= inst_empty_head; @@ -3941,7 +3922,7 @@ begin end if; end if; -- Key Hash 4/4 - when 5 => + when 9 => inst_ready_out <= '1'; -- Memory Flow Control Guard @@ -3951,7 +3932,7 @@ begin inst_next_addr_base_next <= inst_addr_base; -- Occupied List Head if (inst_prev_addr_base = INSTANCE_MEMORY_MAX_ADDRESS) then - assert (inst_addr_base = inst_occupied_head) + assert (inst_addr_base = inst_occupied_head) severity FAILURE; inst_occupied_head_next <= inst_empty_head; inst_addr_base_next <= inst_empty_head; @@ -3997,7 +3978,7 @@ begin when 1 => inst_valid_in <= '1'; inst_addr <= inst_prev_addr_base + IMF_NEXT_ADDR_OFFSET; - inst_write_data <= inst_addr_base; + inst_write_data <= std_logic_vector(resize(inst_addr_base,WORD_WIDTH)); -- Memory Flow Control Guard if (inst_ready_in = '1') then @@ -4010,9 +3991,9 @@ begin -- Memory Flow Control Guard if (inst_valid_out = '1') then -- Fix Empty List Head - inst_empty_head_next <= inst_read_data; + inst_empty_head_next <= resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH); - -- TODO + inst_cnt_next <= inst_cnt + 1; end if; -- Key Hash 1/4 when 3 => @@ -4068,7 +4049,7 @@ begin when 8 => inst_valid_in <= '1'; inst_addr <= inst_addr_base + IMF_SAMPLE_CNT_OFFSET; - inst_write_data <= inst_latch_data.sample_cnt; + inst_write_data <= std_logic_vector(inst_latch_data.sample_cnt); -- Memory Flow Control Guard if (inst_ready_in = '1') then @@ -4078,7 +4059,7 @@ begin when 9 => inst_valid_in <= '1'; inst_addr <= inst_addr_base + IMF_ACK_CNT_OFFSET; - inst_write_data <= inst_latch_data.ack_cnt; + inst_write_data <= std_logic_vector(inst_latch_data.ack_cnt); -- Memory Flow Control Guard if (inst_ready_in = '1') then @@ -4098,9 +4079,9 @@ begin inst_data_next.status_info <= inst_latch_data.status_info; -- Memory Flow Control Guard if (inst_ready_in = '1') then - if check_mask(inst_latch_data.field_flag,IMF_SAMPLE_CNT_FLAG) then + if check_mask(inst_latch_data.field_flags,IMF_SAMPLE_CNT_FLAG) then inst_cnt_next <= 1; - elsif check_mask(inst_latch_data.field_flag,IMF_ACK_CNT_FLAG) then + elsif check_mask(inst_latch_data.field_flags,IMF_ACK_CNT_FLAG) then inst_cnt_next <= 2; else -- DONE @@ -4111,11 +4092,11 @@ begin when 1 => inst_valid_in <= '1'; inst_addr <= inst_addr_base + IMF_SAMPLE_CNT_OFFSET; - inst_write_data <= inst_latch_data.sample_cnt; + inst_write_data <= std_logic_vector(inst_latch_data.sample_cnt); inst_data_next.sample_cnt <= inst_latch_data.sample_cnt; -- Memory Flow Control Guard if (inst_ready_in = '1') then - if check_mask(inst_latch_data.field_flag,IMF_ACK_CNT_FLAG) then + if check_mask(inst_latch_data.field_flags,IMF_ACK_CNT_FLAG) then inst_cnt_next <= 2; else -- DONE @@ -4126,7 +4107,7 @@ begin when 2 => inst_valid_in <= '1'; inst_addr <= inst_addr_base + IMF_ACK_CNT_OFFSET; - inst_write_data <= inst_latch_data.ack_cnt; + inst_write_data <= std_logic_vector(inst_latch_data.ack_cnt); inst_data_next.ack_cnt <= inst_latch_data.ack_cnt; -- Memory Flow Control Guard if (inst_ready_in = '1') then @@ -4156,7 +4137,7 @@ begin -- Memory Flow Control Guard if (inst_valid_out = '1') then - inst_next_addr_base_next <= inst_read_data; + inst_next_addr_base_next <= resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH); inst_cnt_next <= inst_cnt + 1; end if; -- Next Pointer (Previous Instance) @@ -4164,7 +4145,7 @@ begin -- Point Previous instance to Next Instance (Remove current Instance from inbetween) inst_valid_in <= '1'; inst_addr <= inst_prev_addr_base + IMF_NEXT_ADDR_OFFSET; - inst_write_data <= inst_next_addr_base; + inst_write_data <= std_logic_vector(resize(inst_next_addr_base,WORD_WIDTH)); -- Memory Flow Control Guard if (inst_ready_in = '1') then @@ -4175,7 +4156,7 @@ begin -- Point Current Instance to Empty List Head (Make Removed Instance Head of the Empty List) inst_valid_in <= '1'; inst_addr <= inst_addr_base + IMF_NEXT_ADDR_OFFSET; - inst_write_data <= inst_empty_head; + inst_write_data <= std_logic_vector(resize(inst_empty_head,WORD_WIDTH)); -- Memory Flow Control Guard if (inst_ready_in = '1') then @@ -4203,9 +4184,9 @@ begin inst_valid_in <= '1'; inst_addr <= inst_addr_base + IMF_NEXT_ADDR_OFFSET; if (inst_addr_base = MAX_INSTANCE_ADDRESS) then - inst_write_data <= INSTANCE_MEMORY_MAX_ADDRESS; + inst_write_data <= std_logic_vector(resize(INSTANCE_MEMORY_MAX_ADDRESS,WORD_WIDTH)); else - inst_write_data <= inst_addr_base + INSTANCE_FRAME_SIZE; + inst_write_data <= std_logic_vector(resize(inst_addr_base + INSTANCE_FRAME_SIZE,WORD_WIDTH)); end if; -- Memory Flow Control Guard @@ -4225,4 +4206,148 @@ begin end case; end process; end generate; + + sync_prc : process(clk) + begin + if rising_edge(clk) then + if (reset = '1') then + stage <= RESET_SAMPLE_MEMORY; + return_stage <= IDLE; + inst_stage <= RESET_MEMORY; + instance_handle <= HANDLE_NIL; + cc_instance_handle_sig <= HANDLE_NIL; + sample_rej_last_inst <= HANDLE_NIL; + deadline_miss_last_inst <= HANDLE_NIL; + key_hash <= HANDLE_NIL; + deadline_time <= TIME_INVALID; + lifespan_time <= TIME_INVALID; + source_ts <= TIME_INVALID; + timeout_time <= TIME_INVALID; + lease_deadline <= TIME_INVALID; + cc_source_timestamp_sig <= TIME_INVALID; + lifespan <= DURATION_INFINITE; + global_seq_nr <= SEQUENCENUMBER_UNKNOWN; + seq_nr <= SEQUENCENUMBER_UNKNOWN; + cc_kind_sig <= ALIVE; + inst_data <= ZERO_INSTANCE_DATA; + inst_latch_data <= ZERO_INST_LATCH_DATA; + cnt <= 0; + cnt2 <= 0; + cnt3 <= 0; + global_sample_cnt <= 0; + global_ack_cnt <= 0; + stale_inst_cnt <= 0; + inst_cnt <= 0; + inst_cnt2 <= 0; + remove_oldest_sample <= '0'; + remove_oldest_inst_sample <= '0'; + is_lifespan_check <= '0'; + register_op <= '0'; + lookup_op <= '0'; + ack_wait <= '0'; + is_ack <= '0'; + is_rtps <= '0'; + data_available_sig <= '0'; + orphan_samples <= '0'; + newest_sample <= (others => '0'); + oldest_sample <= (others => '0'); + empty_payload_list_head <= (others => '0'); + empty_sample_list_head <= (others => '0'); + empty_sample_list_tail <= (others => '0'); + payload_addr_latch_1 <= (others => '0'); + payload_addr_latch_2 <= (others => '0'); + long_latch <= (others => '0'); + sample_addr_latch_1 <= (others => '0'); + sample_addr_latch_2 <= (others => '0'); + sample_addr_latch_3 <= (others => '0'); + sample_addr_latch_4 <= (others => '0'); + inst_addr_latch_1 <= (others => '0'); + inst_addr_latch_2 <= (others => '0'); + sample_status_info <= (others => '0'); + sample_rej_cnt <= (others => '0'); + sample_rej_cnt_change <= (others => '0'); + sample_rej_last_reason <= (others => '0'); + deadline_miss_cnt <= (others => '0'); + deadline_miss_cnt_change <= (others => '0'); + liveliness_lost_cnt <= (others => '0'); + liveliness_lost_cnt_change <= (others => '0'); + status_sig <= (others => '0'); + inst_addr_base <= (others => '0'); + inst_empty_head <= (others => '0'); + inst_occupied_head <= (others => '0'); + inst_long_latch <= (others => '0'); + inst_next_addr_base <= (others => '0'); + inst_prev_addr_base <= (others => '0'); + else + stage <= stage_next; + return_stage <= return_stage_next; + inst_stage <= inst_stage_next; + instance_handle <= instance_handle_next; + cc_instance_handle_sig <= cc_instance_handle_sig_next; + sample_rej_last_inst <= sample_rej_last_inst_next; + deadline_miss_last_inst <= deadline_miss_last_inst_next; + key_hash <= key_hash_next; + deadline_time <= deadline_time_next; + lifespan_time <= lifespan_time_next; + source_ts <= source_ts_next; + timeout_time <= timeout_time_next; + lease_deadline <= lease_deadline_next; + cc_source_timestamp_sig <= cc_source_timestamp_sig; + lifespan <= lifespan_next; + global_seq_nr <= global_seq_nr_next; + seq_nr <= seq_nr_next; + cc_kind_sig <= cc_kind_sig_next; + inst_data <= inst_data_next; + inst_latch_data <= inst_latch_data_next; + cnt <= cnt_next; + cnt2 <= cnt2_next; + cnt3 <= cnt3_next; + global_sample_cnt <= global_sample_cnt_next; + global_ack_cnt <= global_ack_cnt_next; + stale_inst_cnt <= stale_inst_cnt_next; + inst_cnt <= inst_cnt_next; + inst_cnt2 <= inst_cnt2_next; + remove_oldest_sample <= remove_oldest_sample_next; + remove_oldest_inst_sample <= remove_oldest_inst_sample_next; + is_lifespan_check <= is_lifespan_check_next; + register_op <= register_op_next; + lookup_op <= lookup_op_next; + ack_wait <= ack_wait_next; + is_ack <= is_ack_next; + is_rtps <= is_rtps_next; + data_available_sig <= data_available_sig_next; + orphan_samples <= orphan_samples_next; + newest_sample <= newest_sample_next; + oldest_sample <= oldest_sample_next; + empty_payload_list_head <= empty_payload_list_head_next; + empty_sample_list_head <= empty_sample_list_head_next; + empty_sample_list_tail <= empty_sample_list_tail_next; + payload_addr_latch_1 <= payload_addr_latch_1_next; + payload_addr_latch_2 <= payload_addr_latch_2_next; + long_latch <= long_latch_next; + sample_addr_latch_1 <= sample_addr_latch_1_next; + sample_addr_latch_2 <= sample_addr_latch_2_next; + sample_addr_latch_3 <= sample_addr_latch_3_next; + sample_addr_latch_4 <= sample_addr_latch_4_next; + inst_addr_latch_1 <= inst_addr_latch_1_next; + inst_addr_latch_2 <= inst_addr_latch_2_next; + sample_status_info <= sample_status_info_next; + sample_rej_cnt <= sample_rej_cnt_next; + sample_rej_cnt_change <= sample_rej_cnt_change_next; + sample_rej_last_reason <= sample_rej_last_reason_next; + deadline_miss_cnt <= deadline_miss_cnt_next; + deadline_miss_cnt_change <= deadline_miss_cnt_change_next; + liveliness_lost_cnt <= liveliness_lost_cnt_next; + liveliness_lost_cnt_change <= liveliness_lost_cnt_change_next; + status_sig <= status_sig_next; + inst_addr_base <= inst_addr_base_next; + inst_empty_head <= inst_empty_head_next; + inst_occupied_head <= inst_occupied_head_next; + inst_long_latch <= inst_long_latch_next; + inst_next_addr_base <= inst_next_addr_base_next; + inst_prev_addr_base <= inst_prev_addr_base_next; + end if; + end if; + end process; + end architecture; \ No newline at end of file diff --git a/src/key_hash_generator.vhd b/src/key_hash_generator.vhd index 1c4ddbf..ea81952 100644 --- a/src/key_hash_generator.vhd +++ b/src/key_hash_generator.vhd @@ -120,18 +120,7 @@ begin if (key_gen_valid_out) then cnt_next <= cnt + 1; - case (cnt) is - when 0 => - key_hash_next(0) <= key_gen_data_out; - when 1 => - key_hash_next(1) <= key_gen_data_out; - when 2 => - key_hash_next(2) <= key_gen_data_out; - when 3 => - key_hash_next(3) <= key_gen_data_out; - when others => - null; - end case; + key_hash_next(cnt) <= key_gen_data_out; if (key_gen_last_word_out = '1') then stage_next <= FINISHED_KEY_HASH; @@ -143,21 +132,13 @@ begin if (ready_out = '1') then cnt_next <= cnt + 1; - case (cnt) is - when 0 => - data_out <= key_hash(0); - when 1 => - data_out <= key_hash(1); - when 2 => - data_out <= key_hash(2); - when 3 => - data_out <= key_hash(3); - last_word_out <= '1'; - - stage_next <= IDLE; - when others => - null; - end case; + data_out <= key_hash(cnt); + + if (cnt = key_hash'length-1) then + last_word_out <= '1'; + -- DONE + stage_next <= IDLE; + end if; end if; when others => null; diff --git a/src/key_holder.vhd b/src/key_holder.vhd new file mode 100644 index 0000000..b56e56d --- /dev/null +++ b/src/key_holder.vhd @@ -0,0 +1,24 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity key_holder is + port ( + clk : in std_logic; + reset : in std_logic; + + start : in std_logic; + opcode : in KEY_HOLDER_TYPE; + ack : in std_logic; + + data_in : in std_logic_vector(WORD_WIDTH-1 downto 0); + valid_in : in std_logic; + ready_in : out std_logic; + last_word_in : in std_logic; + + data_out : out std_logic_vector(WORD_WIDTH-1 downto 0); + valid_out : out std_logic; + ready_out : in std_logic; + last_word_out : out std_logic + ); +end entity; \ No newline at end of file diff --git a/src/rtps_config_package.vhd b/src/rtps_config_package.vhd index e3384a8..2d19267 100644 --- a/src/rtps_config_package.vhd +++ b/src/rtps_config_package.vhd @@ -42,8 +42,10 @@ package rtps_config_package is constant OPCODE_LIVELINESS_UPDATE : std_logic_vector(ENDPOINT_MATCH_OPCODE_WIDTH-1 downto 0) := x"55000003"; type HISTORY_CACHE_OPCODE_TYPE is (NOP, ADD_CACHE_CHANGE, GET_CACHE_CHANGE, ACK_CACHE_CHANGE, NACK_CACHE_CHANGE, REMOVE_CACHE_CHANGE, REMOVE_WRITER, GET_MIN_SN, GET_MAX_SN); + type KEY_HOLDER_TYPE is (NOP, PUSH_DATA, PUSH_SERIALIZED_KEY, READ_KEY_HASH, READ_SERIALIZED_KEY); type KEY_GENERATOR_OPCODE_TYPE is (NOP, WRITE_PAYLOAD, READ_KEY, READ_SIZE); type HISTORY_CACHE_RESPONSE_TYPE is (OK, REJECTED, INVALID, ERROR); + type DDS_WRITER_OPCODE_TYPE is (NOP, REGISTER_INSTANCE, WRITE, DISPOSE, UNREGISTER_INSTANCE, LOOKUP_INSTANCE, WAIT_FOR_ACKNOWLEDGEMENTS, GET_OFFERED_DEADLINE_MISSED_STATUS, ASSERT_LIVELINESS, GET_LIVELINESS_LOST_STATUS); -- Sample Status Info Flags constant SSI_DISPOSED_FLAG : natural := STATUS_INFO_DISPOSED_FLAG; diff --git a/src/rtps_reader.vhd b/src/rtps_reader.vhd index 3611aa2..efde791 100644 --- a/src/rtps_reader.vhd +++ b/src/rtps_reader.vhd @@ -1742,6 +1742,14 @@ begin mem_pos_next <= 0; mem_stage_next <= FIND_EMPTY_SLOT; mem_cnt_next <= 0; + -- Set Endpoint Data + mem_endpoint_data_next <= ZERO_ENDPOINT_DATA; + mem_endpoint_data_next.guid <= guid_next; + mem_endpoint_data_next.addr <= addr_next; + mem_endpoint_data_next.portn <= portn_next; + mem_endpoint_data_next.next_seq_nr <= SEQUENCENUMBER_UNKNOWN when (DURABILITY_QOS = VOLATILE_DURABILITY_QOS) else FIRST_SEQUENCENUMBER; + mem_endpoint_data_next.lease_deadline <= lease_deadline; + mem_endpoint_data_next.res_time <= TIME_INVALID; when UPDATE_ENDPOINT => mem_stage_next <= UPDATE_ENDPOINT; if (RELIABILTY_QOS = RELIABLE_RELIABILITY_QOS and check_mask(mem_field_flags,EMF_IPV4_ADDR_FLAG)) then diff --git a/src/rtps_writer.vhd b/src/rtps_writer.vhd index d6cbd05..a0fef60 100644 --- a/src/rtps_writer.vhd +++ b/src/rtps_writer.vhd @@ -27,44 +27,44 @@ entity rtps_writer is ); port ( -- SYSTEM - clk : in std_logic; - reset : in std_logic; - time : in TIME_TYPE; + clk : in std_logic; + reset : in std_logic; + time : in TIME_TYPE; -- FROM RTPS_HANDLER (USER TRAFFIC) - empty_user : in std_logic; - rd_user : out std_logic; - data_in_user : in std_logic_vector(WORD_WIDTH-1 downto 0); - last_word_in_user : in std_logic; + empty_user : in std_logic; + rd_user : out std_logic; + data_in_user : in std_logic_vector(WORD_WIDTH-1 downto 0); + last_word_in_user : in std_logic; -- FROM RTPS_BUILTIN_ENDPOINT (META TRAFFIC) - empty_meta : in std_logic; - rd_meta : out std_logic; - data_in_meta : in std_logic_vector(WORD_WIDTH-1 downto 0); - last_word_in_meta : in std_logic; + empty_meta : in std_logic; + rd_meta : out std_logic; + data_in_meta : in std_logic_vector(WORD_WIDTH-1 downto 0); + last_word_in_meta : in std_logic; -- TO RTPS_BUILTIN_ENDPOINT (META TRAFFIC) - alive_sig : out std_logic; + alive_sig : out std_logic; -- RTPS OUTPUT - wr_rtps : out std_logic; - full_rtps : in std_logic; - last_word_out_rtps : out std_logic; - data_out_rtps : out std_logic_vector(WORD_WIDTH-1 downto 0); + wr_rtps : out std_logic; + full_rtps : in std_logic; + last_word_out_rtps : out std_logic; + data_out_rtps : out std_logic_vector(WORD_WIDTH-1 downto 0); -- FROM HC - assert_liveliness : in std_logic; - data_available : in std_logic; - start_hc : out std_logic; - opcode_hc : out HISTORY_CACHE_OPCODE_TYPE; - ack_hc : in std_logic; - seq_nr_hc : out SEQUENCENUMBER_TYPE; - done_hc : in std_logic; - ret_hc : in HISTORY_CACHE_RESPONSE_TYPE; - get_data_hc : out std_logic; - data_in_hc : in std_logic_vector(WORD_WIDTH-1 downto 0); - valid_in_hc : in std_logic; - ready_in_hc : out std_logic; - last_word_in_hc : in std_logic; - cc_instance_handle : in INSTANCE_HANDLE_TYPE; - cc_kind : in CACHE_CHANGE_KIND_TYPE; - cc_source_timestamp : in TIME_TYPE; - cc_seq_nr : in SEQUENCENUMBER_TYPE + liveliness_assertion : in std_logic; + data_available : in std_logic; + start_hc : out std_logic; + opcode_hc : out HISTORY_CACHE_OPCODE_TYPE; + ack_hc : in std_logic; + seq_nr_hc : out SEQUENCENUMBER_TYPE; + done_hc : in std_logic; + ret_hc : in HISTORY_CACHE_RESPONSE_TYPE; + get_data_hc : out std_logic; + data_in_hc : in std_logic_vector(WORD_WIDTH-1 downto 0); + valid_in_hc : in std_logic; + ready_in_hc : out std_logic; + last_word_in_hc : in std_logic; + cc_instance_handle : in INSTANCE_HANDLE_TYPE; + cc_kind : in CACHE_CHANGE_KIND_TYPE; + cc_source_timestamp : in TIME_TYPE; + cc_seq_nr : in SEQUENCENUMBER_TYPE ); end entity; @@ -467,7 +467,7 @@ begin data_out_rtps <= (others => '0'); -- Assert Liveliness Latch Setter - if (assert_liveliness = '1') then + if (liveliness_assertion = '1') then assert_liveliness_latch_next <= '1'; end if;