diff --git a/src/Tests/Level_0/L0_dds_reader_test1.vhd b/src/Tests/Level_0/L0_dds_reader_test1.vhd index 9679fe2..8fb8366 100644 --- a/src/Tests/Level_0/L0_dds_reader_test1.vhd +++ b/src/Tests/Level_0/L0_dds_reader_test1.vhd @@ -19,6 +19,7 @@ use work.rtps_test_package.all; -- TEST: REMOVE_WRITER [KNOWN WRITER (1 Instance)] -- TEST: REMOVE_WRITER [KNOWN WRITER (>1 Instances)] -- TEST: REMOVE_WRITER [NOT_ALIVE_NO_WRITERS Transition] +-- TEST: REMOVE_WRITER [NOT_ALIVE_NO_WRITERS Transition, Empty Sample Memory] -- TEST: REMOVE_WRITER [Multiple Pending NOT_ALIVE_NO_WRITERS Transitions] -- TEST: REMOVE_WRITER ON MAX_SAMPLES [NOT_ALIVE_NO_WRITERS Transition] -- TEST: REMOVE_WRITER ON MAX_SAMPLES_PER_INSTANCE [NOT_ALIVE_NO_WRITERS Transition] @@ -66,7 +67,7 @@ architecture testbench of L0_dds_reader_test1 is -- *CONSTANT DECLARATION* constant MAX_REMOTE_ENDPOINTS : natural := 3; - constant NUM_READERS : natural := 6; + constant NUM_READERS : natural := 7; impure function gen_test_config return CONFIG_ARRAY_TYPE is variable ret : CONFIG_ARRAY_TYPE(0 to NUM_READERS-1) := (others => DEFAULT_WRITER_CONFIG); @@ -155,6 +156,20 @@ architecture testbench of L0_dds_reader_test1 is ret(5).ORDERED_ACCESS := FALSE; ret(5).WITH_KEY := TRUE; ret(5).MAX_PAYLOAD_SIZE := 40; + -- arzkriu + ret(6).TIME_BASED_FILTER_QOS := DURATION_ZERO; + ret(6).DEADLINE_QOS := DURATION_INFINITE; + ret(6).MAX_SAMPLES := std_logic_vector(to_unsigned(1,CDR_LONG_WIDTH)); + ret(6).MAX_INSTANCES := std_logic_vector(to_unsigned(1,CDR_LONG_WIDTH)); + ret(6).MAX_SAMPLES_PER_INSTANCE := std_logic_vector(to_unsigned(1,CDR_LONG_WIDTH)); + ret(6).HISTORY_QOS := KEEP_ALL_HISTORY_QOS; + ret(6).RELIABILITY_QOS := RELIABLE_RELIABILITY_QOS; + ret(6).PRESENTATION_QOS := INSTANCE_PRESENTATION_QOS; + ret(6).DESTINATION_ORDER_QOS := BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS; + ret(6).COHERENT_ACCESS := FALSE; + ret(6).ORDERED_ACCESS := FALSE; + ret(6).WITH_KEY := TRUE; + ret(6).MAX_PAYLOAD_SIZE := 40; return ret; end function; constant TEST_CONFIG : CONFIG_ARRAY_TYPE := gen_test_config; @@ -1579,7 +1594,7 @@ begin AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - Log("R0: DDS Operation TAKE_INSTANCE [Instance 4, MAX_SAMPLES 1, NOT_READ_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); + Log("R0,R5: DDS Operation TAKE_INSTANCE [Instance 4, MAX_SAMPLES 1, NOT_READ_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); dds := DEFAULT_DDS_READER_TEST; dds.opcode := TAKE_INSTANCE; dds.max_samples := 1; @@ -6715,6 +6730,135 @@ begin AffirmIf(status_id,(status(4) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + Log("*READER 6*", INFO); + + -- READER 6 + AlertIf(empty_sample_head(6) /= 0, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(6) /= 0, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(6) /= 0, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: -/0,11 + -- PAYLOAD MEMORY: -/0,11 + -- INSTANCE MEMORY: -/0 + -- ISTATE: - + -- WRITER: - + + AffirmIf(status_id,(status(6) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh1; + cc.payload := gen_payload(kh1,10); + cc.src_timestamp := gen_duration(1 sec); + + Log("R6: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Aligned Payload]", INFO); + Log("R6: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 0; + rtps.ret_code := OK; + s := to_sample(cc,ALIVE_INSTANCE_STATE); + add_sample(s,mem(6), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + -- READER 6 + ind <= 6; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 6 + AlertIf(empty_sample_head(6) /= 11, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(6) /= 11, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(6) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I1S1)/11 + -- PAYLOAD MEMORY: 0(I1S1)/11 + -- INSTANCE MEMORY: 0(I1)/- + -- ISTATE: I1:ALIVE + -- WRITER: W0:I1 + + AffirmIf(status_id,(status(6) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + + Log("R6: DDS Operation TAKE [MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := TAKE; + dds.max_samples := 1; + dds.sstate := ANY_SAMPLE_STATE; + dds.istate := ANY_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + -- READER 6 + ind <= 6; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- READER 6 + AlertIf(empty_sample_head(6) /= 11, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(6) /= 0, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(6) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: -/11,0 + -- PAYLOAD MEMORY: -/0,11 + -- INSTANCE MEMORY: 0(I1)/- + -- ISTATE: I1:ALIVE + -- WRITER: W0:I1 + + AffirmIf(status_id,(status(6) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + + -- TEST: REMOVE_WRITER [NOT_ALIVE_NO_WRITERS Transition, Empty Sample Memory] + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := TRUE; + cc.kind := NOT_ALIVE_UNREGISTERED; + cc.instance := kh1; + cc.src_timestamp := check_time; + + Log("R6: RTPS Operation REMOVE_WRITER [Writer 0]", INFO); + Log("R6: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := REMOVE_WRITER; + rtps.writer_pos := 0; + change_istate(kh1, NOT_ALIVE_NO_WRITERS_INSTANCE_STATE, mem(6)); + rtps.ret_code := OK; + s := to_sample(cc,NOT_ALIVE_NO_WRITERS_INSTANCE_STATE); + add_sample(s,mem(6), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + -- READER 6 + ind <= 6; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 6 + AlertIf(empty_sample_head(6) /= 0, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(6) /= 0, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(6) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 11(I1S2)/0 + -- PAYLOAD MEMORY: -/0,11 + -- INSTANCE MEMORY: 0(I1)/- + -- ISTATE: I1:NOT_ALIVE_NO_WRITERS + -- WRITER: - + + AffirmIf(status_id,(status(6) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + + Log("R6: DDS Operation TAKE [MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := TAKE; + dds.max_samples := 1; + dds.sstate := ANY_SAMPLE_STATE; + dds.istate := ANY_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + -- READER 6 + ind <= 6; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- READER 6 + AlertIf(empty_sample_head(6) /= 0, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(6) /= 0, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(6) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: -/0,11 + -- PAYLOAD MEMORY: -/0,11 + -- INSTANCE MEMORY: 0(I1)/- + -- ISTATE: I1:NOT_ALIVE_NO_WRITERS + -- WRITER: - + + AffirmIf(status_id,(status(6) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + wait_on_completion; TranscriptOpen(RESULTS_FILE, APPEND_MODE); SetTranscriptMirror; diff --git a/src/dds_reader.vhd b/src/dds_reader.vhd index 722d705..df80bb0 100644 --- a/src/dds_reader.vhd +++ b/src/dds_reader.vhd @@ -2616,11 +2616,19 @@ begin -- Memory Flow Control Guard if (sample_ready_in = '1') then - assert (newest_sample(ind) /= SAMPLE_MEMORY_MAX_ADDRESS) severity FAILURE; - cnt_next <= cnt + 1; + if (newest_sample(ind) = SAMPLE_MEMORY_MAX_ADDRESS) then + -- Update Sample List Head + oldest_sample_next(ind) <= cur_sample; + + cnt_next <= cnt + 2; -- READ Next Address + else + cnt_next <= cnt + 1; + end if; end if; -- SET Next Sample Pointer (Previous Sample) when 12 => + assert (newest_sample(ind) /= SAMPLE_MEMORY_MAX_ADDRESS) severity FAILURE; + sample_valid_in1 <= '1'; sample_addr1 <= newest_sample(ind) + SMF_NEXT_ADDR_OFFSET; sample_write_data1 <= std_logic_vector(resize(empty_sample_list_head(ind),WORD_WIDTH));