From 9aa7607d920eaac48e8e3d83ba9d237dc8286c04 Mon Sep 17 00:00:00 2001
From: John Daktylidis <greek64.mail@gmail.com>
Date: Thu, 3 Aug 2023 18:01:36 +0200
Subject: [PATCH] Add missing hps_0.h Header File

---
 sw/standalone/.gitignore |  9 +++++
 sw/standalone/hps_0.h    | 75 ++++++++++++++++++++++++++++++++++++++++
 2 files changed, 84 insertions(+)
 create mode 100644 sw/standalone/.gitignore
 create mode 100644 sw/standalone/hps_0.h

diff --git a/sw/standalone/.gitignore b/sw/standalone/.gitignore
new file mode 100644
index 0000000..a7cc3ae
--- /dev/null
+++ b/sw/standalone/.gitignore
@@ -0,0 +1,9 @@
+#Ignore Everything
+*
+
+#WHITELIST
+!.gitignore
+!*.c
+!*.cpp
+!*.h
+!*.hpp
diff --git a/sw/standalone/hps_0.h b/sw/standalone/hps_0.h
new file mode 100644
index 0000000..b9dfadf
--- /dev/null
+++ b/sw/standalone/hps_0.h
@@ -0,0 +1,75 @@
+#ifndef _ALTERA_HPS_0_H_
+#define _ALTERA_HPS_0_H_
+
+/*
+ * This file was automatically generated by the swinfo2header utility.
+ * 
+ * Created from SOPC Builder system 'soc_system' in
+ * file './soc_system.sopcinfo'.
+ */
+
+/*
+ * This file contains macros for module 'hps_0' and devices
+ * connected to the following masters:
+ *   h2f_axi_master
+ *   h2f_lw_axi_master
+ * 
+ * Do not include this header file and another header file created for a
+ * different module or master group at the same time.
+ * Doing so may result in duplicate macro names.
+ * Instead, use the system header file which has macros with unique names.
+ */
+
+/*
+ * Macros for device 'test_fpga_0', class 'test_fpga'
+ * The macros are prefixed with 'TEST_FPGA_0_'.
+ * The prefix is the slave descriptor.
+ */
+#define TEST_FPGA_0_COMPONENT_TYPE test_fpga
+#define TEST_FPGA_0_COMPONENT_NAME test_fpga_0
+#define TEST_FPGA_0_BASE 0x0
+#define TEST_FPGA_0_SPAN 16
+#define TEST_FPGA_0_END 0xf
+
+/*
+ * Macros for device 'sysid_qsys', class 'altera_avalon_sysid_qsys'
+ * The macros are prefixed with 'SYSID_QSYS_'.
+ * The prefix is the slave descriptor.
+ */
+#define SYSID_QSYS_COMPONENT_TYPE altera_avalon_sysid_qsys
+#define SYSID_QSYS_COMPONENT_NAME sysid_qsys
+#define SYSID_QSYS_BASE 0x1000
+#define SYSID_QSYS_SPAN 8
+#define SYSID_QSYS_END 0x1007
+#define SYSID_QSYS_ID 2899645186
+#define SYSID_QSYS_TIMESTAMP 1638038262
+
+/*
+ * Macros for device 'jtag_uart', class 'altera_avalon_jtag_uart'
+ * The macros are prefixed with 'JTAG_UART_'.
+ * The prefix is the slave descriptor.
+ */
+#define JTAG_UART_COMPONENT_TYPE altera_avalon_jtag_uart
+#define JTAG_UART_COMPONENT_NAME jtag_uart
+#define JTAG_UART_BASE 0x2000
+#define JTAG_UART_SPAN 8
+#define JTAG_UART_END 0x2007
+#define JTAG_UART_IRQ 2
+#define JTAG_UART_READ_DEPTH 64
+#define JTAG_UART_READ_THRESHOLD 8
+#define JTAG_UART_WRITE_DEPTH 64
+#define JTAG_UART_WRITE_THRESHOLD 8
+
+/*
+ * Macros for device 'ILC', class 'interrupt_latency_counter'
+ * The macros are prefixed with 'ILC_'.
+ * The prefix is the slave descriptor.
+ */
+#define ILC_COMPONENT_TYPE interrupt_latency_counter
+#define ILC_COMPONENT_NAME ILC
+#define ILC_BASE 0x30000
+#define ILC_SPAN 256
+#define ILC_END 0x300ff
+
+
+#endif /* _ALTERA_HPS_0_H_ */