greek64/rtps-fpga
2
1
Fork 0
Code Issues Pull Requests Releases Wiki Activity

Remove HIGHEST_AVAILABLE_SN from local endpoint buffer

Browse Source
This commit is contained in:
Greek 2021-01-11 18:45:37 +01:00
parent 0574f9e69d
commit 9ff39c6fea
3 changed files with 10 additions and 74 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/REF.txt
View File

@ -330,10 +330,6 @@ LOCAL ENDPOINT BUFFER
+ NEXT_SEQ_NR + + NEXT_SEQ_NR +
11| | 11| |
+-------------------------------------------------------------+ +-------------------------------------------------------------+
12| |
+ HIGHEST_AVAIL_SEQ_NR + [Reliable Only]
13| |
+-------------------------------------------------------------+
HISTORY CACHE HISTORY CACHE

2
src/Tests/testbench.pro
View File

@ -35,6 +35,6 @@ analyze Level_1/L1_rtps_builtin_endpoint_test1.vhd
#simulate L0_rtps_builtin_endpoint_test4 #simulate L0_rtps_builtin_endpoint_test4
#simulate L0_rtps_builtin_endpoint_test5 #simulate L0_rtps_builtin_endpoint_test5
#simulate L0_rtps_builtin_endpoint_test6 #simulate L0_rtps_builtin_endpoint_test6
simulate L0_rtps_builtin_endpoint_test7 #simulate L0_rtps_builtin_endpoint_test7
#simulate L0_rtps_out_test1 #simulate L0_rtps_out_test1
#simulate L1_rtps_builtin_endpoint_test1 #simulate L1_rtps_builtin_endpoint_test1

78
src/rtps_endpoint.vhd
View File

@ -65,17 +65,15 @@ architecture arch of rtps_endpoint is
constant FIRST_ENDPOINT_ADDRESS : unsigned(ENDPOINT_MEMORY_WIDTH-1 downto 0) := (others => '0'); constant FIRST_ENDPOINT_ADDRESS : unsigned(ENDPOINT_MEMORY_WIDTH-1 downto 0) := (others => '0');
-- *UPDATE PARTICIPANT FLAG POSITIONS* -- *UPDATE PARTICIPANT FLAG POSITIONS*
constant UPDATE_ENDPOINT_FLAG_WIDTH : natural := 6; constant UPDATE_ENDPOINT_FLAG_WIDTH : natural := 4;
-- Signifies that the main Endpoint Data are updated -- Signifies that the main Endpoint Data are updated
constant ENDPOINT_DATA_FLAG : std_logic_vector(UPDATE_ENDPOINT_FLAG_WIDTH-1 downto 0) := (0 => 1, others => '0'); constant ENDPOINT_DATA_FLAG : std_logic_vector(UPDATE_ENDPOINT_FLAG_WIDTH-1 downto 0) := (0 => 1, others => '0');
-- Signifies that the Lease Deadline of the Endpoint Data is updated -- Signifies that the Lease Deadline of the Endpoint Data is updated
constant LEASE_DEADLINE_FLAG : std_logic_vector(UPDATE_ENDPOINT_FLAG_WIDTH-1 downto 0) := (1 => 1, others => '0'); constant LEASE_DEADLINE_FLAG : std_logic_vector(UPDATE_ENDPOINT_FLAG_WIDTH-1 downto 0) := (1 => 1, others => '0');
-- Signifies that the last Sequence Number of the Endpoint Data is updated -- Signifies that the last Sequence Number of the Endpoint Data is updated
constant NEXT_SEQ_NR_FLAG : std_logic_vector(UPDATE_ENDPOINT_FLAG_WIDTH-1 downto 0) := (2 => 1, others => '0'); constant NEXT_SEQ_NR_FLAG : std_logic_vector(UPDATE_ENDPOINT_FLAG_WIDTH-1 downto 0) := (2 => 1, others => '0');
-- Signifies that the Highest Available Sequence Number of the Endpoint Data is updated
constant HIGHEST_SEQ_NR_FLAG : std_logic_vector(UPDATE_ENDPOINT_FLAG_WIDTH-1 downto 0) := (3 => 1, others => '0');
-- Signifies that the HEARTBEAT/ACKNACK Timeout Time of the Endpoint Data is updated -- Signifies that the HEARTBEAT/ACKNACK Timeout Time of the Endpoint Data is updated
constant RES_TIME_FLAG : std_logic_vector(UPDATE_ENDPOINT_FLAG_WIDTH-1 downto 0) := (4 => 1, others => '0'); constant RES_TIME_FLAG : std_logic_vector(UPDATE_ENDPOINT_FLAG_WIDTH-1 downto 0) := (3 => 1, others => '0');
constant BITMAP_BLOCK_SIZE : natural := 16; constant BITMAP_BLOCK_SIZE : natural := 16;
--*****TYPE DECLARATION***** --*****TYPE DECLARATION*****
@ -92,7 +90,6 @@ architecture arch of rtps_endpoint is
lease_deadline : TIME_TYPE; lease_deadline : TIME_TYPE;
res_time : TIME_TYPE; res_time : TIME_TYPE;
next_seq_nr : SEQUENCENUMBER_TYPE; next_seq_nr : SEQUENCENUMBER_TYPE;
highest_seq_nr : SEQUENCENUMBER_TYPE;
end record; end record;
constant ZERO_ENDPOINT_DATA : ENDPOINT_DATA_TYPE := ( constant ZERO_ENDPOINT_DATA : ENDPOINT_DATA_TYPE := (
addr => IPv4_ADDRESS_INVALID, addr => IPv4_ADDRESS_INVALID,
@ -100,8 +97,7 @@ architecture arch of rtps_endpoint is
expects_inline_qos => '0', expects_inline_qos => '0',
lease_deadline => TIME_INVALID, lease_deadline => TIME_INVALID,
res_time => TIME_INVALID, res_time => TIME_INVALID,
next_seq_nr => SEQUENCENUMBER_UNKNOWN, next_seq_nr => SEQUENCENUMBER_UNKNOWN
highest_seq_nr => SEQUENCENUMBER_UNKNOWN
); );
type MEM_CTRL_DATA_TYPE is record type MEM_CTRL_DATA_TYPE is record
guid : GUID_TYPE; guid : GUID_TYPE;
@ -110,7 +106,6 @@ architecture arch of rtps_endpoint is
expects_inline_qos : std_logic; expects_inline_qos : std_logic;
deadline : TIME_TYPE; deadline : TIME_TYPE;
next_seq_nr : SEQUENCENUMBER_TYPE; next_seq_nr : SEQUENCENUMBER_TYPE;
highest_seq_nr : SEQUENCENUMBER_TYPE;
update_flags : std_logic_vector(UPDATE_ENDPOINT_FLAG_WIDTH-1 downto 0); update_flags : std_logic_vector(UPDATE_ENDPOINT_FLAG_WIDTH-1 downto 0);
mem_opcode : MEM_OPCODE_TYPE; mem_opcode : MEM_OPCODE_TYPE;
end record; end record;
@ -121,7 +116,6 @@ architecture arch of rtps_endpoint is
expects_inline_qos => '0', expects_inline_qos => '0',
deadline => TIME_INVALID, deadline => TIME_INVALID,
next_seq_nr => SEQUENCENUMBER_UNKNOWN, next_seq_nr => SEQUENCENUMBER_UNKNOWN,
highest_seq_nr => SEQUENCENUMBER_UNKNOWN,
update_flags => (others => '0'), update_flags => (others => '0'),
mem_opcode => IDLE mem_opcode => IDLE
); );
@ -584,12 +578,7 @@ begin
deadline_next <= time + ENDPOINT_HEARTBEAT_RESPONSE_DELAY(ID); deadline_next <= time + ENDPOINT_HEARTBEAT_RESPONSE_DELAY(ID);
-- NOTE: Last Bit denotes if this is Response or Suppression Delay -- NOTE: Last Bit denotes if this is Response or Suppression Delay
deadline_next(1)(0) <= '0'; deadline_next(1)(0) <= '0';
-- Update also highest available sequence number if necessary update_endpoint_flags <= NEXT_SEQ_NR_FLAG or RES_TIME_FLAG;
if (last_seq_nr /= mem_endpoint_data.highest_seq_nr) then
update_endpoint_flags <= NEXT_SEQ_NR_FLAG or HIGHEST_SEQ_NR_FLAG or RES_TIME_FLAG;
else
update_endpoint_flags <= NEXT_SEQ_NR_FLAG or RES_TIME_FLAG;
end if;
-- If new Sequence Number is available or Writer expects ACKNACK -- If new Sequence Number is available or Writer expects ACKNACK
elsif (last_seq_nr >= mem_endpoint_data.next_seq_nr or final_flag = '0') then elsif (last_seq_nr >= mem_endpoint_data.next_seq_nr or final_flag = '0') then
-- Set Response Delay -- Set Response Delay
@ -598,12 +587,7 @@ begin
deadline_next <= time + ENDPOINT_HEARTBEAT_RESPONSE_DELAY(ID); deadline_next <= time + ENDPOINT_HEARTBEAT_RESPONSE_DELAY(ID);
-- NOTE: Last Bit denotes if this is Response or Suppression Delay -- NOTE: Last Bit denotes if this is Response or Suppression Delay
deadline_next(1)(0) <= '0'; deadline_next(1)(0) <= '0';
-- Update also highest available sequence number if necessary update_endpoint_flags <= RES_TIME_FLAG;
if (last_seq_nr /= mem_endpoint_data.highest_seq_nr) then
update_endpoint_flags <= HIGHEST_SEQ_NR_FLAG or RES_TIME_FLAG;
else
update_endpoint_flags <= RES_TIME_FLAG;
end if;
end if; end if;
-- Currently in Heartbeat Response Delay -- Currently in Heartbeat Response Delay
elsif (mem_participant_data.res_time(1)(0) = '0') then elsif (mem_participant_data.res_time(1)(0) = '0') then
@ -613,17 +597,7 @@ begin
next_seq_nr_next <= first_seq_nr; next_seq_nr_next <= first_seq_nr;
mem_op_start <= '1'; mem_op_start <= '1';
mem_opcode <= UPDATE_ENDPOINT; mem_opcode <= UPDATE_ENDPOINT;
-- Update also highest available sequence number if different update_endpoint_flags <= NEXT_SEQ_NR_FLAG;
if (last_seq_nr /= mem_endpoint_data.highest_seq_nr) then
update_endpoint_flags <= NEXT_SEQ_NR_FLAG or HIGHEST_SEQ_NR_FLAG;
else
update_endpoint_flags <= NEXT_SEQ_NR_FLAG;
end if;
elsif (last_seq_nr /= mem_endpoint_data.highest_seq_nr and first_seq_nr <= last_seq_nr) then
-- Store new highest available sequence number
mem_op_start <= '1';
mem_opcode <= UPDATE_ENDPOINT;
update_endpoint_flags <= HIGHEST_SEQ_NR_FLAG;
end if; end if;
end if; end if;
end if; end if;
@ -1225,7 +1199,6 @@ begin
expects_inline_qos => expects_inline_qos_next, expects_inline_qos => expects_inline_qos_next,
deadline => deadline_next, deadline => deadline_next,
next_seq_nr => next_seq_nr_next, next_seq_nr => next_seq_nr_next,
highest_seq_nr => last_seq_nr_next,
update_flags => update_endpoint_flags_next, update_flags => update_endpoint_flags_next,
mem_opcode => mem_opcode_next mem_opcode => mem_opcode_next
); );
@ -1259,10 +1232,6 @@ begin
mem_stage_next <= UPDATE_ENDPOINT; mem_stage_next <= UPDATE_ENDPOINT;
mem_addr_next <= addr_res + 10; mem_addr_next <= addr_res + 10;
mem_cnt_next <= 6; mem_cnt_next <= 6;
elsif ((update_endpoint_flags and HIGHEST_SEQ_NR_FLAG) = HIGHEST_SEQ_NR_FLAG) then
mem_stage_next <= UPDATE_ENDPOINT;
mem_addr_next <= addr_res + 12;
mem_cnt_next <= 8;
end if; end if;
when REMOVE_ENDPOINT => when REMOVE_ENDPOINT =>
mem_addr_next <= addr_res; mem_addr_next <= addr_res;
@ -1429,12 +1398,6 @@ begin
-- Next Sequence Number 2/2 -- Next Sequence Number 2/2
when 8 => when 8 =>
mem_endpoint_data_next.next_seq_nr(1) <= unsigned(mem_read_data); mem_endpoint_data_next.next_seq_nr(1) <= unsigned(mem_read_data);
-- Highest Available Sequence Number 1/2
when 9 =>
mem_endpoint_data_next.highest_seq_nr(0) <= unsigned(mem_read_data);
-- Highest Available Sequence Number 2/2
when 10 =>
mem_endpoint_data_next.highest_seq_nr(1) <= unsigned(mem_read_data);
-- DONE -- DONE
mem_stage_next <= IDLE; mem_stage_next <= IDLE;
when others => when others =>
@ -1482,12 +1445,6 @@ begin
-- Next Sequence Number 2/2 -- Next Sequence Number 2/2
when 11 => when 11 =>
mem_write_data <= to_unsigned(1,CDR_LONG_WIDTH); mem_write_data <= to_unsigned(1,CDR_LONG_WIDTH);
-- Highest Available Sequence Number 1/2
when 12 =>
mem_write_data <= (others => '0');
-- Highest Available Sequence Number 2/2
when 13 =>
mem_write_data <= (others => '0');
-- DONE -- DONE
mem_stage_next <= IDLE; mem_stage_next <= IDLE;
when others => when others =>
@ -1511,7 +1468,7 @@ begin
mem_wr <= '1'; mem_wr <= '1';
end if; end if;
-- If nothing else to update -- If nothing else to update
if ((mem_ctrl_data.update_flags and (LEASE_DEADLINE_FLAG or NEXT_SEQ_NR_FLAG or HIGHEST_SEQ_NR_FLAG or RES_TIME_FLAG)) = (mem_ctrl_data.update_flags'range => '0')) then if ((mem_ctrl_data.update_flags and (LEASE_DEADLINE_FLAG or NEXT_SEQ_NR_FLAG or RES_TIME_FLAG)) = (mem_ctrl_data.update_flags'range => '0')) then
-- DONE -- DONE
mem_stage_next <= IDLE; mem_stage_next <= IDLE;
end if; end if;
@ -1528,7 +1485,7 @@ begin
mem_wr <= '1'; mem_wr <= '1';
end if; end if;
-- If nothing else to update -- If nothing else to update
if ((mem_ctrl_data.update_flags and (NEXT_SEQ_NR_FLAG or HIGHEST_SEQ_NR_FLAG or RES_TIME_FLAG)) = (mem_ctrl_data.update_flags'range => '0')) then if ((mem_ctrl_data.update_flags and (NEXT_SEQ_NR_FLAG or RES_TIME_FLAG)) = (mem_ctrl_data.update_flags'range => '0')) then
-- DONE -- DONE
mem_stage_next <= IDLE; mem_stage_next <= IDLE;
end if; end if;
@ -1545,7 +1502,7 @@ begin
mem_wr <= '1'; mem_wr <= '1';
end if; end if;
-- If nothing else to update -- If nothing else to update
if ((mem_ctrl_data.update_flags and (HIGHEST_SEQ_NR_FLAG or NEXT_SEQ_NR_FLAG)) = (mem_ctrl_data.update_flags'range => '0')) then if ((mem_ctrl_data.update_flags and (NEXT_SEQ_NR_FLAG)) = (mem_ctrl_data.update_flags'range => '0')) then
-- DONE -- DONE
mem_stage_next <= IDLE; mem_stage_next <= IDLE;
end if; end if;
@ -1561,23 +1518,6 @@ begin
if ((mem_ctrl_data.update_flags and NEXT_SEQ_NR_FLAG) = NEXT_SEQ_NR_FLAG) then if ((mem_ctrl_data.update_flags and NEXT_SEQ_NR_FLAG) = NEXT_SEQ_NR_FLAG) then
mem_wr <= '1'; mem_wr <= '1';
end if; end if;
-- If nothing else to update
if ((mem_ctrl_data.update_flags and (HIGHEST_SEQ_NR_FLAG)) = (mem_ctrl_data.update_flags'range => '0')) then
-- DONE
mem_stage_next <= IDLE;
end if;
-- Highest Available Sequence Number 1/2
when 8 =>
mem_write_data <= std_logic_vector(mem_ctrl_data.highest_seq_nr(0));
if ((mem_ctrl_data.update_flags and HIGHEST_SEQ_NR_FLAG) = HIGHEST_SEQ_NR_FLAG) then
mem_wr <= '1';
end if;
-- Highest Available Sequence Number 2/2
when 9 =>
mem_write_data <= std_logic_vector(mem_ctrl_data.highest_seq_nr(1));
if ((mem_ctrl_data.update_flags and HIGHEST_SEQ_NR_FLAG) = HIGHEST_SEQ_NR_FLAG) then
mem_wr <= '1';
end if;
-- DONE -- DONE
mem_stage_next <= IDLE; mem_stage_next <= IDLE;
when others => when others =>