Modify test_top and config for ROS RTT Test and add to DE10-Nano Project

syn/DE10-Nano/top.qsf

@@ -49,8 +49,16 @@ set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH
 set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
 set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
 set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+
 set_global_assignment -name SDC_FILE top.sdc
 set_global_assignment -name VHDL_FILE ../test_top.vhd -hdl_version VHDL_2008
+set_global_assignment -name VHDL_FILE ../../src/ros2/Tests/Level_2/L2_Testbench_ROS_Lib6.vhd -hdl_version VHDL_2008
+set_global_assignment -name VHDL_FILE ../../src/ros2/Tests/test_loopback_util.vhd -hdl_version VHDL_2008
+set_global_assignment -name VHDL_FILE ../../src/ros2/Tests/Type1_ros_pub.vhd -hdl_version VHDL_2008
+set_global_assignment -name VHDL_FILE ../../src/ros2/Tests/Type1_ros_sub.vhd -hdl_version VHDL_2008
 set_global_assignment -name VHDL_FILE ../../src/ros2/Tests/Level_2/L2_Testbench_ROS_Lib4.vhd -hdl_version VHDL_2008
 set_global_assignment -name VHDL_FILE ../../src/ros2/Tests/Fibonacci.vhd -hdl_version VHDL_2008
 set_global_assignment -name VHDL_FILE ../../src/ros2/example_interfaces/Fibonacci_ros_action_server.vhd -hdl_version VHDL_2008
@@ -73,18 +81,17 @@ set_global_assignment -name VHDL_FILE ../../src/ros2/example_interfaces/AddTwoIn
 set_global_assignment -name VHDL_FILE ../../src/ros2/ros_time_converter.vhd -hdl_version VHDL_2008
 set_global_assignment -name VHDL_FILE ../../src/ros2/ros_static_discovery_writer.vhd -hdl_version VHDL_2008
 set_global_assignment -name VHDL_FILE ../../src/Avalon_MM_wrapper.vhd -hdl_version VHDL_2008
-set_global_assignment -name VHDL_FILE ../../src/Tests/Level_2/L2_testbench_Lib4.vhd -hdl_version VHDL_2008
+set_global_assignment -name VHDL_FILE ../../src/Tests/Level_2/L2_Testbench_Lib4.vhd -hdl_version VHDL_2008
 set_global_assignment -name VHDL_FILE ../../src/Tests/test_loopback.vhd -hdl_version VHDL_2008
 set_global_assignment -name VHDL_FILE ../test_fpga.vhd -hdl_version VHDL_2008
 set_global_assignment -name VHDL_FILE ../dds_reader_syn.vhd -hdl_version VHDL_2008
 set_global_assignment -name VHDL_FILE ../../src/dds_reader.vhd -hdl_version VHDL_2008
 set_global_assignment -name VHDL_FILE ../dds_writer_syn.vhd -hdl_version VHDL_2008
 set_global_assignment -name VHDL_FILE ../../src/dds_writer.vhd -hdl_version VHDL_2008
-set_global_assignment -name VHDL_FILE ../../src/Tests/Type1_config.vhd -hdl_version VHDL_2008
+set_global_assignment -name VHDL_FILE ../../src/Tests/Type1_cfg.vhd -hdl_version VHDL_2008
 set_global_assignment -name VHDL_FILE ../../src/Tests/Type1_writer_interface.vhd -hdl_version VHDL_2008
 set_global_assignment -name VHDL_FILE ../../src/Tests/Type1_reader_interface.vhd -hdl_version VHDL_2008
 set_global_assignment -name VHDL_FILE ../../src/Tests/Type1_key_holder.vhd -hdl_version VHDL_2008
-set_global_assignment -name VHDL_FILE ../../src/Tests/Type1_package.vhd -hdl_version VHDL_2008
 set_global_assignment -name VHDL_FILE ../../src/verbatim_key_hash_generator.vhd -hdl_version VHDL_2008
 set_global_assignment -name VHDL_FILE ../../src/key_hash_generator.vhd -hdl_version VHDL_2008
 set_global_assignment -name VHDL_FILE ../../src/key_holder.vhd -hdl_version VHDL_2008
@@ -95,6 +102,8 @@ set_global_assignment -name VHDL_FILE ../../src/rtps_writer.vhd -hdl_version VHD
 set_global_assignment -name VHDL_FILE ../../src/rtps_discovery_module.vhd -hdl_version VHDL_2008
 set_global_assignment -name VHDL_FILE ../../src/rtps_handler.vhd -hdl_version VHDL_2008
 set_global_assignment -name VHDL_FILE ../../src/rtps_out.vhd -hdl_version VHDL_2008
+set_global_assignment -name VHDL_FILE ../../src/moving_average_wrapper.vhd -hdl_version VHDL_2008
+set_global_assignment -name VHDL_FILE ../../src/moving_average.vhd -hdl_version VHDL_2008
 set_global_assignment -name VHDL_FILE ../test7.vhd -hdl_version VHDL_2008
 set_global_assignment -name VHDL_FILE ../test6.vhd -hdl_version VHDL_2008
 set_global_assignment -name VHDL_FILE ../test5.vhd -hdl_version VHDL_2008
@@ -121,7 +130,8 @@ set_global_assignment -name VHDL_FILE ../../src/single_port_ram.vhd -hdl_version
 set_global_assignment -name VHDL_FILE ../../src/ros2/ros_config_package.vhd -hdl_version VHDL_2008
 set_global_assignment -name VHDL_FILE ../../src/rtps_config_package.vhd -hdl_version VHDL_2008
 set_global_assignment -name VHDL_FILE ../../src/ros2/dds_user_config.vhd -hdl_version VHDL_2008
-set_global_assignment -name VHDL_FILE ../syn_ros_action_config.vhd -hdl_version VHDL_2008
+set_global_assignment -name VHDL_FILE ../syn_ros_rtt_config.vhd -hdl_version VHDL_2008
+set_global_assignment -name VHDL_FILE ../../src/ros2/Tests/Type1_package.vhd -hdl_version VHDL_2008
 set_global_assignment -name VHDL_FILE ../../src/ros2/example_interfaces/Fibonacci_package.vhd -hdl_version VHDL_2008
 set_global_assignment -name VHDL_FILE ../../src/ros2/example_interfaces/AddTwoInts_package.vhd -hdl_version VHDL_2008
 set_global_assignment -name VHDL_FILE ../../src/ros2/rcl_interfaces/action_msgs/CancelGoal_package.vhd -hdl_version VHDL_2008
@@ -131,7 +141,5 @@ set_global_assignment -name VHDL_FILE ../../src/ros2/rcl_interfaces/action_msgs/
 set_global_assignment -name VHDL_FILE ../../src/ros2/ros_package.vhd -hdl_version VHDL_2008
 set_global_assignment -name VHDL_FILE ../../src/rtps_package.vhd -hdl_version VHDL_2008
 set_global_assignment -name VHDL_FILE ../../src/math_pkg.vhd -hdl_version VHDL_2008
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+
-set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
-set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

syn/syn_ros_rtt_config.vhd

@@ -0,0 +1,98 @@
+-- altera vhdl_input_version vhdl_2008
+-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.rtps_package.all;
+use work.ros_package.all;
+use work.Type1_package.all;
+
+package ros_config is
+    
+    -- Period of ros system clock
+    constant ROS_CLOCK_PERIOD   : time := 20 ns; -- 50 MHz
+    -- IPv4 Address of ROS System [192.168.0.90]
+    constant ROS_ADDRESS    : std_logic_vector(IPv4_ADDRESS_WIDTH-1 downto 0) := x"C0A8005A";
+    -- Random Key used to generate GUIDs
+    constant ROS_RAND_KEY   : std_logic_vector(47 downto 0) := x"E2A53AA91CC5";
+    
+    constant NUM_NODES : natural := 1;
+    
+    constant ROS_NODES : ROS_NODE_ARRAY_TYPE(0 to NUM_NODES-1) := (
+        0 => (
+            name            => gen_user_string("test_loopback_server"),
+            namespace       => gen_user_string(""),
+            domain_id       => 0,
+            NUM_PUBS        => 1,
+            NUM_SUBS        => 1,
+            NUM_SERVICES    => 0,
+            NUM_ACTIONS     => 0
+        )
+    );
+    
+    constant NUM_PUBS       : natural := get_num_pubs(ROS_NODES);
+    constant NUM_SUBS       : natural := get_num_subs(ROS_NODES);
+    constant NUM_SERVICES   : natural := get_num_services(ROS_NODES);
+    constant NUM_ACTIONS    : natural := get_num_actions(ROS_NODES);
+    
+    constant ROS_PUBLICATIONS : ROS_TOPIC_ARRAY_TYPE(0 to NUM_PUBS-1) := (
+        0 => (
+            node_id     => 0,
+            TOPICNAME   => gen_user_string("rt/Loopback_2"),
+            TYPENAME    => gen_user_string("tutorial_interfaces::msg::dds_::Type1_"),
+            QOS         => ROS_QOS_PROFILE_TRANSIENT,
+            MAX_SIZE    => MAX_TYPE1_SIZE
+        )
+    );
+    
+    constant ROS_SUBSCRIPTIONS : ROS_TOPIC_ARRAY_TYPE(0 to NUM_SUBS-1) := (
+        0 => (
+            node_id     => 0,
+            TOPICNAME   => gen_user_string("rt/Loopback_1"),
+            TYPENAME    => gen_user_string("tutorial_interfaces::msg::dds_::Type1_"),
+            QOS         => ROS_QOS_PROFILE_TRANSIENT,
+            MAX_SIZE    => MAX_TYPE1_SIZE
+        )
+    );
+    
+    constant ROS_SERVICES : ROS_SERVICE_ARRAY_TYPE(0 to NUM_SERVICES-1) := (
+        others => (
+            node_id     => 0,
+            SERVICENAME => gen_user_string(""),
+            RQ_TYPENAME => gen_user_string(""),
+            RR_TYPENAME => gen_user_string(""),
+            QOS         => ROS_QOS_PROFILE_SERVICES_DEFAULT,
+            MAX_RQ_SIZE => 0,
+            MAX_RR_SIZE => 0,
+            is_client   => FALSE
+        )
+    );
+    
+    constant ROS_ACTIONS : ROS_ACTION_ARRAY_TYPE(0 to NUM_ACTIONS-1) := (
+        others => (
+            node_id             => 0,
+            ACTIONNAME          => gen_user_string(""),
+            GOAL_RQ_TYPENAME    => gen_user_string(""),
+            GOAL_RR_TYPENAME    => gen_user_string(""),
+            RESULT_RQ_TYPENAME  => gen_user_string(""),
+            RESULT_RR_TYPENAME  => gen_user_string(""),
+            FEEDBACK_TYPENAME   => gen_user_string(""),
+            GOAL_QOS            => ROS_QOS_PROFILE_SERVICES_DEFAULT,
+            RESULT_QOS          => ROS_QOS_PROFILE_SERVICES_DEFAULT,
+            FEEDBACK_QOS        => ROS_QOS_PROFILE_DEFAULT,
+            CANCEL_QOS          => ROS_QOS_PROFILE_SERVICES_DEFAULT,
+            MAX_GOAL_RQ_SIZE    => 0,
+            MAX_GOAL_RR_SIZE    => 0,
+            MAX_RESULT_RQ_SIZE  => 0,
+            MAX_RESULT_RR_SIZE  => 0,
+            MAX_FEEDBACK_SIZE   => 0,
+            is_client           => FALSE,
+            enable_feedback     => TRUE
+        )
+    );
+    
+    -- Defines sensible RTPS timings for simulation
+    constant SIMULATION_TIMING : boolean := FALSE;
+end package;

syn/test_top.vhd

@@ -28,6 +28,7 @@ architecture arch of test_top is
     signal full_fi_wr, write_wr_fi, empty_fo_wr, read_wr_fo, empty_fi_test, read_test_fi, full_fo_test, write_test_fo : std_logic;
     signal data_wr_fi, data_fo_wr, data_fi_test, data_test_fo : std_logic_vector(WORD_WIDTH-1 downto 0);
     signal time : TIME_TYPE;
+    signal input_util, output_util : natural;
     
 begin
     
@@ -63,7 +64,7 @@ begin
             data_out    => data_fi_test,
             empty       => empty_fi_test,
             full        => full_fi_wr,
-            free        => open
+            free        => input_util
         );
     
     FIFO_OUT_inst : configuration work.FWFT_FIFO_cfg
@@ -80,7 +81,7 @@ begin
             data_out    => data_fo_wr,
             empty       => empty_fo_wr,
             full        => full_fo_test,
-            free        => open
+            free        => output_util
         );
     
     --dds_loopback_inst : entity work.L2_Testbench_Lib4(arch)
@@ -115,12 +116,31 @@ begin
     --        data_out    => data_test_fo
     --    );
         
-    ros_action_inst : entity work.L2_Testbench_ROS_Lib4(arch)
+    --ros_action_inst : entity work.L2_Testbench_ROS_Lib4(arch)
+    --    port map (
+    --        -- SYSTEM
+    --        clk         => clk,
+    --        reset       => reset,
+    --        time        => time,
+    --        -- INPUT
+    --        empty       => empty_fi_test,
+    --        read        => read_test_fi,
+    --        data_in     => data_fi_test,
+    --        -- OUTPUT
+    --        full        => full_fo_test,
+    --        write       => write_test_fo,
+    --        data_out    => data_test_fo
+    --    );
+    
+    ros_rtt : entity work.L2_Testbench_ROS_Lib6(arch)
         port map (
             -- SYSTEM
             clk         => clk,
             reset       => reset,
             time        => time,
+            -- UTILIZATION
+            input_util  => std_logic_vector(to_unsigned(input_util, WORD_WIDTH)),
+            output_util => std_logic_vector(to_unsigned(output_util, WORD_WIDTH)),
             -- INPUT
             empty       => empty_fi_test,
             read        => read_test_fi,