From a26faff89a45a9bdb7782c0d9959ad06a58a0883 Mon Sep 17 00:00:00 2001 From: Greek64 Date: Thu, 3 Feb 2022 14:35:54 +0100 Subject: [PATCH] Move functions between rtps_package and rtps_config_package --- src/rtps_config_package.vhd | 70 ------------------------------------- src/rtps_package.vhd | 68 +++++++++++++++++++++++++++++++++++ 2 files changed, 68 insertions(+), 70 deletions(-) diff --git a/src/rtps_config_package.vhd b/src/rtps_config_package.vhd index a12ef16..3cebc02 100644 --- a/src/rtps_config_package.vhd +++ b/src/rtps_config_package.vhd @@ -143,19 +143,6 @@ package rtps_config_package is function gen_inline_qos (id : natural) return OUTPUT_DATA_TYPE; - -- Indexing Function to extract sub-vectors from std_logic_vector signals - -- input SLV from which to extract a sub-vector - -- index The SLV is divided in width-sized sub-vectors. index states which sub-vector to extract (depending on invert) - -- width width of sub-vector (NOTE: SLV must have a length multiple to width) - -- invert If invert=TRUE, index 0 is the leftmost sub-vector, else the rightmost - function get_sub_vector (input : std_logic_vector; index : natural; width : natural; invert : boolean) return std_logic_vector; - -- Indexing Function to write sub-vectors to std_logic_vector signals - -- input SLV from to which to write a sub-vector - -- sub Sub-vector to write into the SLV - -- index The SLV is divided in sub-sized 'sub'-vectors. index states which sub-vector to write (depending on invert) - -- invert If invert=TRUE, index 0 is the leftmost sub-vector, else the rightmost - function write_sub_vector(input : std_logic_vector; sub : std_logic_vector; index : natural; invert : boolean) return std_logic_vector; - end package; package body rtps_config_package is @@ -1198,61 +1185,4 @@ package body rtps_config_package is return FALSE; end if; end function; - - function get_sub_vector (input : std_logic_vector; index : natural; width : natural; invert : boolean) return std_logic_vector is - variable ret : std_logic_vector(width-1 downto 0) := (others => '0'); - begin - assert(input'length mod width = 0) report "Input Length has to be multiple of width" severity FAILURE; - assert(input'length / width > index) report "Index out of bounds" severity FAILURE; - - if (invert = TRUE) then - -- XXX: Synthesis Hack - --ret := input(input'length-(index*width)-1 downto input'length-((index+1)*width)); - for i in 0 to (input'length/width)-1 loop - if (index = i) then - ret := input(input'length-(i*width)-1 downto input'length-((i+1)*width)); - end if; - end loop; - else - -- XXX: Synthesis Hack - --ret := input(((index+1)*width)-1 downto index*width); - for i in 0 to (input'length/width)-1 loop - if (index = i) then - ret := input(((i+1)*width)-1 downto i*width); - end if; - end loop; - end if; - - return ret; - end function; - - function write_sub_vector(input : std_logic_vector; sub : std_logic_vector; index : natural; invert : boolean) return std_logic_vector is - variable ret : std_logic_vector(input'length-1 downto 0) := (others => '0'); - begin - assert(input'length mod sub'length = 0) report "Input Length has to be multiple of sub width" severity FAILURE; - assert(input'length / sub'length > index) report "Index out of bounds" severity FAILURE; - - ret := input; - - if (invert = TRUE) then - -- XXX: Synthesis Hack - --ret(input'length-(index*sub'length)-1 downto input'length-((index+1)*sub'length)) := sub; - for i in 0 to (input'length/sub'length)-1 loop - if (index = i) then - ret(input'length-(i*sub'length)-1 downto input'length-((i+1)*sub'length)) := sub; - end if; - end loop; - else - -- XXX: Synthesis Hack - --ret(((index+1)*sub'length)-1 downto index*sub'length) := sub; - for i in 0 to (input'length/sub'length)-1 loop - if (index = i) then - ret(((i+1)*sub'length)-1 downto i*sub'length) := sub; - end if; - end loop; - end if; - - return ret; - end function; - end package body; diff --git a/src/rtps_package.vhd b/src/rtps_package.vhd index c011c8c..60a0699 100644 --- a/src/rtps_package.vhd +++ b/src/rtps_package.vhd @@ -594,6 +594,19 @@ package rtps_package is function to_integer(dw : DOUBLE_WORD_ARRAY) return integer; function to_unsigned(input : KEY_HASH_TYPE) return unsigned; function to_unsigned(input : GUID_TYPE) return unsigned; + + -- Indexing Function to extract sub-vectors from std_logic_vector signals + -- input SLV from which to extract a sub-vector + -- index The SLV is divided in width-sized sub-vectors. index states which sub-vector to extract (depending on invert) + -- width width of sub-vector (NOTE: SLV must have a length multiple to width) + -- invert If invert=TRUE, index 0 is the leftmost sub-vector, else the rightmost + function get_sub_vector (input : std_logic_vector; index : natural; width : natural; invert : boolean) return std_logic_vector; + -- Indexing Function to write sub-vectors to std_logic_vector signals + -- input SLV from to which to write a sub-vector + -- sub Sub-vector to write into the SLV + -- index The SLV is divided in sub-sized 'sub'-vectors. index states which sub-vector to write (depending on invert) + -- invert If invert=TRUE, index 0 is the leftmost sub-vector, else the rightmost + function write_sub_vector(input : std_logic_vector; sub : std_logic_vector; index : natural; invert : boolean) return std_logic_vector; end package; package body rtps_package is @@ -1014,4 +1027,59 @@ package body rtps_package is return ret; end function; + function get_sub_vector (input : std_logic_vector; index : natural; width : natural; invert : boolean) return std_logic_vector is + variable ret : std_logic_vector(width-1 downto 0) := (others => '0'); + begin + assert(input'length mod width = 0) report "Input Length has to be multiple of width" severity FAILURE; + assert(input'length / width > index) report "Index out of bounds" severity FAILURE; + + if (invert = TRUE) then + -- XXX: Synthesis Hack + --ret := input(input'length-(index*width)-1 downto input'length-((index+1)*width)); + for i in 0 to (input'length/width)-1 loop + if (index = i) then + ret := input(input'length-(i*width)-1 downto input'length-((i+1)*width)); + end if; + end loop; + else + -- XXX: Synthesis Hack + --ret := input(((index+1)*width)-1 downto index*width); + for i in 0 to (input'length/width)-1 loop + if (index = i) then + ret := input(((i+1)*width)-1 downto i*width); + end if; + end loop; + end if; + + return ret; + end function; + + function write_sub_vector(input : std_logic_vector; sub : std_logic_vector; index : natural; invert : boolean) return std_logic_vector is + variable ret : std_logic_vector(input'length-1 downto 0) := (others => '0'); + begin + assert(input'length mod sub'length = 0) report "Input Length has to be multiple of sub width" severity FAILURE; + assert(input'length / sub'length > index) report "Index out of bounds" severity FAILURE; + + ret := input; + + if (invert = TRUE) then + -- XXX: Synthesis Hack + --ret(input'length-(index*sub'length)-1 downto input'length-((index+1)*sub'length)) := sub; + for i in 0 to (input'length/sub'length)-1 loop + if (index = i) then + ret(input'length-(i*sub'length)-1 downto input'length-((i+1)*sub'length)) := sub; + end if; + end loop; + else + -- XXX: Synthesis Hack + --ret(((index+1)*sub'length)-1 downto index*sub'length) := sub; + for i in 0 to (input'length/sub'length)-1 loop + if (index = i) then + ret(((i+1)*sub'length)-1 downto i*sub'length) := sub; + end if; + end loop; + end if; + + return ret; + end function; end package body;