From a6802cc5389f2cbf28f99d1daa106a3e35420e6a Mon Sep 17 00:00:00 2001 From: Greek Date: Sun, 21 Mar 2021 18:49:59 +0100 Subject: [PATCH] Add Test1 of DDS Writer Test RTPS GET_MIN_SN, GET_MAX_SN, GET_CACHE_CHANGE, REMOVE_CACHE_CHANGE, ACK_CACHE_CHANGE, and NACK_CACHE_CHANGE Operations. Test DDS Register, Unregister, Write, Dispose, and Lookup Instance Operations. --- sim/L0_dds_writer_test1_aik.do | 150 ++ sim/L0_dds_writer_test1_ain.do | 128 + sim/L0_dds_writer_test1_lik.do | 150 ++ src/REF.txt | 12 +- src/TODO.txt | 58 +- src/Tests/Level_0/L0_dds_writer_test1_afk.vhd | 2179 +++++++++++++++++ src/Tests/Level_0/L0_dds_writer_test1_aik.txt | 270 ++ src/Tests/Level_0/L0_dds_writer_test1_aik.vhd | 2179 +++++++++++++++++ src/Tests/Level_0/L0_dds_writer_test1_ain.txt | 69 + src/Tests/Level_0/L0_dds_writer_test1_ain.vhd | 1134 +++++++++ src/Tests/Level_0/L0_dds_writer_test1_lik.txt | 225 ++ src/Tests/Level_0/L0_dds_writer_test1_lik.vhd | 1953 +++++++++++++++ src/Tests/Level_0/dds_writer_tests.txt | 81 + src/Tests/testbench.pro | 11 +- src/dds_writer.vhd | 1937 ++++++++------- src/rtps_config_package.vhd | 2 +- src/rtps_test_package.vhd | 13 +- 17 files changed, 9659 insertions(+), 892 deletions(-) create mode 100644 sim/L0_dds_writer_test1_aik.do create mode 100644 sim/L0_dds_writer_test1_ain.do create mode 100644 sim/L0_dds_writer_test1_lik.do create mode 100644 src/Tests/Level_0/L0_dds_writer_test1_afk.vhd create mode 100644 src/Tests/Level_0/L0_dds_writer_test1_aik.txt create mode 100644 src/Tests/Level_0/L0_dds_writer_test1_aik.vhd create mode 100644 src/Tests/Level_0/L0_dds_writer_test1_ain.txt create mode 100644 src/Tests/Level_0/L0_dds_writer_test1_ain.vhd create mode 100644 src/Tests/Level_0/L0_dds_writer_test1_lik.txt create mode 100644 src/Tests/Level_0/L0_dds_writer_test1_lik.vhd create mode 100644 src/Tests/Level_0/dds_writer_tests.txt diff --git a/sim/L0_dds_writer_test1_aik.do b/sim/L0_dds_writer_test1_aik.do new file mode 100644 index 0000000..b687f6d --- /dev/null +++ b/sim/L0_dds_writer_test1_aik.do @@ -0,0 +1,150 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate -divider SYSTEM +add wave -noupdate /l0_dds_writer_test1_aik/uut/clk +add wave -noupdate /l0_dds_writer_test1_aik/uut/reset +add wave -noupdate -radix unsigned /l0_dds_writer_test1_aik/uut/time +add wave -noupdate -divider {RTPS IN} +add wave -noupdate -group {RTPS IN} /l0_dds_writer_test1_aik/uut/start_rtps +add wave -noupdate -group {RTPS IN} -radix unsigned /l0_dds_writer_test1_aik/uut/seq_nr_rtps +add wave -noupdate -group {RTPS IN} /l0_dds_writer_test1_aik/uut/opcode_rtps +add wave -noupdate -group {RTPS IN} /l0_dds_writer_test1_aik/uut/ack_rtps +add wave -noupdate -group {RTPS IN} /l0_dds_writer_test1_aik/uut/done_rtps +add wave -noupdate -group {RTPS IN} /l0_dds_writer_test1_aik/uut/ret_rtps +add wave -noupdate -divider {RTPS OUT} +add wave -noupdate -group {RTPS OUT} -radix hexadecimal /l0_dds_writer_test1_aik/uut/cc_instance_handle +add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test1_aik/uut/cc_kind +add wave -noupdate -group {RTPS OUT} -radix unsigned /l0_dds_writer_test1_aik/uut/cc_source_timestamp +add wave -noupdate -group {RTPS OUT} -radix unsigned -childformat {{/l0_dds_writer_test1_aik/uut/cc_seq_nr(0) -radix unsigned -childformat {{/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(31) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(30) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(29) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(28) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(27) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(26) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(25) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(24) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(23) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(22) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(21) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(20) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(19) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(18) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(17) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(16) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(15) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(14) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(13) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(12) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(11) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(10) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(9) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(8) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(7) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(6) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(5) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(4) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(3) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(2) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(1) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(0) -radix unsigned}}} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(1) -radix unsigned}} -subitemconfig {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0) {-height 15 -radix unsigned -childformat {{/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(31) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(30) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(29) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(28) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(27) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(26) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(25) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(24) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(23) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(22) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(21) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(20) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(19) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(18) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(17) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(16) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(15) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(14) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(13) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(12) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(11) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(10) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(9) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(8) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(7) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(6) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(5) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(4) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(3) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(2) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(1) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(0) -radix unsigned}}} /l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(31) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(30) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(29) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(28) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(27) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(26) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(25) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(24) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(23) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(22) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(21) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(20) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(19) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(18) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(17) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(16) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(15) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(14) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(13) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(12) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(11) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(10) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(9) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(8) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(7) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(6) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(5) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(4) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(3) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(2) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(1) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(0) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/cc_seq_nr(1) {-height 15 -radix unsigned}} /l0_dds_writer_test1_aik/uut/cc_seq_nr +add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test1_aik/uut/get_data_rtps +add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test1_aik/uut/ready_out_rtps +add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test1_aik/uut/valid_out_rtps +add wave -noupdate -group {RTPS OUT} -radix hexadecimal /l0_dds_writer_test1_aik/uut/data_out_rtps +add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test1_aik/uut/last_word_out_rtps +add wave -noupdate -divider {DDS IN} +add wave -noupdate -expand -group DDS /l0_dds_writer_test1_aik/uut/start_dds +add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_writer_test1_aik/uut/instance_handle_dds +add wave -noupdate -expand -group DDS -radix unsigned /l0_dds_writer_test1_aik/uut/source_ts_dds +add wave -noupdate -expand -group DDS /l0_dds_writer_test1_aik/uut/opcode_dds +add wave -noupdate -expand -group DDS /l0_dds_writer_test1_aik/uut/ack_dds +add wave -noupdate -expand -group DDS /l0_dds_writer_test1_aik/uut/done_dds +add wave -noupdate -expand -group DDS -radix unsigned /l0_dds_writer_test1_aik/uut/return_code_dds +add wave -noupdate -expand -group DDS /l0_dds_writer_test1_aik/uut/ready_in_dds +add wave -noupdate -expand -group DDS /l0_dds_writer_test1_aik/uut/valid_in_dds +add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_writer_test1_aik/uut/data_in_dds +add wave -noupdate -expand -group DDS /l0_dds_writer_test1_aik/uut/last_word_in_dds +add wave -noupdate -expand -group DDS /l0_dds_writer_test1_aik/uut/ready_out_dds +add wave -noupdate -expand -group DDS /l0_dds_writer_test1_aik/uut/valid_out_dds +add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_writer_test1_aik/uut/data_out_dds +add wave -noupdate -expand -group DDS /l0_dds_writer_test1_aik/uut/last_word_out_dds +add wave -noupdate -divider {MAIN FSM} +add wave -noupdate /l0_dds_writer_test1_aik/uut/stage +add wave -noupdate /l0_dds_writer_test1_aik/uut/stage_next +add wave -noupdate /l0_dds_writer_test1_aik/uut/cnt +add wave -noupdate -radix unsigned /l0_dds_writer_test1_aik/uut/global_seq_nr +add wave -noupdate -radix unsigned /l0_dds_writer_test1_aik/uut/global_sample_cnt +add wave -noupdate -radix unsigned /l0_dds_writer_test1_aik/uut/global_ack_cnt +add wave -noupdate -radix unsigned /l0_dds_writer_test1_aik/uut/stale_inst_cnt +add wave -noupdate /l0_dds_writer_test1_aik/uut/remove_oldest_inst_sample +add wave -noupdate /l0_dds_writer_test1_aik/uut/remove_oldest_sample +add wave -noupdate /l0_dds_writer_test1_aik/uut/remove_ack_sample +add wave -noupdate -divider MEMORY +add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test1_aik/uut/sample_abort_read +add wave -noupdate -group {SAMPLE MEM} -radix unsigned -childformat {{/l0_dds_writer_test1_aik/uut/sample_mem_ctrl_inst/addr(5) -radix unsigned} {/l0_dds_writer_test1_aik/uut/sample_mem_ctrl_inst/addr(4) -radix unsigned} {/l0_dds_writer_test1_aik/uut/sample_mem_ctrl_inst/addr(3) -radix unsigned} {/l0_dds_writer_test1_aik/uut/sample_mem_ctrl_inst/addr(2) -radix unsigned} {/l0_dds_writer_test1_aik/uut/sample_mem_ctrl_inst/addr(1) -radix unsigned} {/l0_dds_writer_test1_aik/uut/sample_mem_ctrl_inst/addr(0) -radix unsigned}} -subitemconfig {/l0_dds_writer_test1_aik/uut/sample_mem_ctrl_inst/addr(5) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/sample_mem_ctrl_inst/addr(4) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/sample_mem_ctrl_inst/addr(3) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/sample_mem_ctrl_inst/addr(2) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/sample_mem_ctrl_inst/addr(1) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/sample_mem_ctrl_inst/addr(0) {-height 15 -radix unsigned}} /l0_dds_writer_test1_aik/uut/sample_mem_ctrl_inst/addr +add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test1_aik/uut/sample_mem_ctrl_inst/read +add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test1_aik/uut/sample_mem_ctrl_inst/ready_in +add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test1_aik/uut/sample_mem_ctrl_inst/valid_in +add wave -noupdate -group {SAMPLE MEM} -radix hexadecimal /l0_dds_writer_test1_aik/uut/sample_mem_ctrl_inst/data_in +add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test1_aik/uut/sample_mem_ctrl_inst/ready_out +add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test1_aik/uut/sample_mem_ctrl_inst/valid_out +add wave -noupdate -group {SAMPLE MEM} -radix hexadecimal /l0_dds_writer_test1_aik/uut/sample_mem_ctrl_inst/data_out +add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test1_aik/uut/payload_abort_read +add wave -noupdate -group {PAYLOAD MEM} -radix unsigned /l0_dds_writer_test1_aik/uut/payload_mem_ctrl_inst/addr +add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test1_aik/uut/payload_mem_ctrl_inst/read +add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test1_aik/uut/payload_mem_ctrl_inst/ready_in +add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test1_aik/uut/payload_mem_ctrl_inst/valid_in +add wave -noupdate -group {PAYLOAD MEM} -radix hexadecimal /l0_dds_writer_test1_aik/uut/payload_mem_ctrl_inst/data_in +add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test1_aik/uut/payload_mem_ctrl_inst/ready_out +add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test1_aik/uut/payload_mem_ctrl_inst/valid_out +add wave -noupdate -group {PAYLOAD MEM} -radix hexadecimal /l0_dds_writer_test1_aik/uut/payload_mem_ctrl_inst/data_out +add wave -noupdate /l0_dds_writer_test1_aik/uut/inst_op_start +add wave -noupdate /l0_dds_writer_test1_aik/uut/inst_opcode +add wave -noupdate /l0_dds_writer_test1_aik/uut/inst_op_done +add wave -noupdate /l0_dds_writer_test1_aik/uut/inst_stage +add wave -noupdate /l0_dds_writer_test1_aik/uut/inst_stage_next +add wave -noupdate /l0_dds_writer_test1_aik/uut/inst_cnt +add wave -noupdate -radix unsigned /l0_dds_writer_test1_aik/uut/inst_addr_base +add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test1_aik/uut/inst_abort_read +add wave -noupdate -group {INSTANCE MEM} -radix unsigned /l0_dds_writer_test1_aik/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/addr +add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test1_aik/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/read +add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test1_aik/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/ready_in +add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test1_aik/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/valid_in +add wave -noupdate -group {INSTANCE MEM} -radix hexadecimal /l0_dds_writer_test1_aik/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/data_in +add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test1_aik/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/ready_out +add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test1_aik/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/valid_out +add wave -noupdate -group {INSTANCE MEM} -radix hexadecimal /l0_dds_writer_test1_aik/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/data_out +add wave -noupdate -childformat {{/l0_dds_writer_test1_aik/uut/inst_data.key_hash -radix hexadecimal} {/l0_dds_writer_test1_aik/uut/inst_data.status_info -radix binary} {/l0_dds_writer_test1_aik/uut/inst_data.sample_cnt -radix unsigned} {/l0_dds_writer_test1_aik/uut/inst_data.ack_cnt -radix unsigned}} -expand -subitemconfig {/l0_dds_writer_test1_aik/uut/inst_data.key_hash {-height 15 -radix hexadecimal} /l0_dds_writer_test1_aik/uut/inst_data.status_info {-height 15 -radix binary} /l0_dds_writer_test1_aik/uut/inst_data.sample_cnt {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/inst_data.ack_cnt {-height 15 -radix unsigned}} /l0_dds_writer_test1_aik/uut/inst_data +add wave -noupdate -radix unsigned /l0_dds_writer_test1_aik/uut/inst_next_addr_base +add wave -noupdate -radix unsigned /l0_dds_writer_test1_aik/uut/inst_prev_addr_base +add wave -noupdate -divider {KEY HOLDER} +add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test1_aik/uut/start_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test1_aik/uut/opcode_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test1_aik/uut/ack_kh +add wave -noupdate -group {KEY HOLDER} -radix hexadecimal /l0_dds_writer_test1_aik/uut/data_in_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test1_aik/uut/valid_in_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test1_aik/uut/ready_in_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test1_aik/uut/last_word_in_kh +add wave -noupdate -group {KEY HOLDER} -radix hexadecimal /l0_dds_writer_test1_aik/uut/data_out_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test1_aik/uut/valid_out_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test1_aik/uut/ready_out_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test1_aik/uut/last_word_out_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test1_aik/uut/abort_kh +add wave -noupdate -divider POINTERS +add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test1_aik/uut/empty_sample_list_head +add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test1_aik/uut/empty_sample_list_tail +add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test1_aik/uut/empty_payload_list_head +add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test1_aik/uut/oldest_sample +add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test1_aik/uut/newest_sample +add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test1_aik/uut/inst_empty_head +add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test1_aik/uut/inst_occupied_head +add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test1_aik/uut/cur_sample +add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test1_aik/uut/prev_sample +add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test1_aik/uut/next_sample +add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test1_aik/uut/cur_payload +add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test1_aik/uut/next_payload +add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test1_aik/uut/cur_inst +add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test1_aik/uut/next_inst +add wave -noupdate -divider TESTBENCH +add wave -noupdate -group TESTBENCH /l0_dds_writer_test1_aik/stim_start +add wave -noupdate -group TESTBENCH /l0_dds_writer_test1_aik/stim_stage +add wave -noupdate -group TESTBENCH /l0_dds_writer_test1_aik/stim_cnt +add wave -noupdate -group TESTBENCH /l0_dds_writer_test1_aik/stim_done +add wave -noupdate -group TESTBENCH /l0_dds_writer_test1_aik/ref_start +add wave -noupdate -group TESTBENCH /l0_dds_writer_test1_aik/ref_stage +add wave -noupdate -group TESTBENCH /l0_dds_writer_test1_aik/ref_cnt +add wave -noupdate -group TESTBENCH /l0_dds_writer_test1_aik/ref_done +add wave -noupdate -group TESTBENCH /l0_dds_writer_test1_aik/kh_cnt +add wave -noupdate -group TESTBENCH /l0_dds_writer_test1_aik/kh_stage +add wave -noupdate -divider MISC +add wave -noupdate /l0_dds_writer_test1_aik/uut/cnt2 +add wave -noupdate /l0_dds_writer_test1_aik/uut/cnt3 +add wave -noupdate -radix unsigned /l0_dds_writer_test1_aik/uut/long_latch +add wave -noupdate /l0_dds_writer_test1_aik/uut/sample_status_info +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {106575000 ps} 0} +quietly wave cursor active 1 +configure wave -namecolwidth 187 +configure wave -valuecolwidth 100 +configure wave -justifyvalue left +configure wave -signalnamewidth 1 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ns +update +WaveRestoreZoom {106074680 ps} {107075321 ps} diff --git a/sim/L0_dds_writer_test1_ain.do b/sim/L0_dds_writer_test1_ain.do new file mode 100644 index 0000000..2a05b49 --- /dev/null +++ b/sim/L0_dds_writer_test1_ain.do @@ -0,0 +1,128 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate -divider SYSTEM +add wave -noupdate /l0_dds_writer_test1_ain/uut/clk +add wave -noupdate /l0_dds_writer_test1_ain/uut/reset +add wave -noupdate -radix unsigned /l0_dds_writer_test1_ain/uut/time +add wave -noupdate -divider {RTPS IN} +add wave -noupdate -group {RTPS IN} /l0_dds_writer_test1_ain/uut/start_rtps +add wave -noupdate -group {RTPS IN} -radix unsigned /l0_dds_writer_test1_ain/uut/seq_nr_rtps +add wave -noupdate -group {RTPS IN} /l0_dds_writer_test1_ain/uut/opcode_rtps +add wave -noupdate -group {RTPS IN} /l0_dds_writer_test1_ain/uut/ack_rtps +add wave -noupdate -group {RTPS IN} /l0_dds_writer_test1_ain/uut/done_rtps +add wave -noupdate -group {RTPS IN} /l0_dds_writer_test1_ain/uut/ret_rtps +add wave -noupdate -divider {RTPS OUT} +add wave -noupdate -group {RTPS OUT} -radix hexadecimal /l0_dds_writer_test1_ain/uut/cc_instance_handle +add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test1_ain/uut/cc_kind +add wave -noupdate -group {RTPS OUT} -radix unsigned /l0_dds_writer_test1_ain/uut/cc_source_timestamp +add wave -noupdate -group {RTPS OUT} -radix unsigned -childformat {{/l0_dds_writer_test1_ain/uut/cc_seq_nr(0) -radix unsigned -childformat {{/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(31) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(30) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(29) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(28) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(27) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(26) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(25) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(24) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(23) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(22) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(21) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(20) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(19) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(18) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(17) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(16) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(15) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(14) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(13) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(12) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(11) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(10) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(9) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(8) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(7) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(6) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(5) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(4) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(3) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(2) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(1) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(0) -radix unsigned}}} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(1) -radix unsigned}} -subitemconfig {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0) {-height 15 -radix unsigned -childformat {{/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(31) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(30) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(29) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(28) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(27) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(26) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(25) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(24) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(23) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(22) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(21) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(20) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(19) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(18) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(17) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(16) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(15) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(14) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(13) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(12) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(11) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(10) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(9) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(8) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(7) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(6) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(5) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(4) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(3) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(2) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(1) -radix unsigned} {/l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(0) -radix unsigned}}} /l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(31) {-height 15 -radix unsigned} /l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(30) {-height 15 -radix unsigned} /l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(29) {-height 15 -radix unsigned} /l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(28) {-height 15 -radix unsigned} /l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(27) {-height 15 -radix unsigned} /l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(26) {-height 15 -radix unsigned} /l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(25) {-height 15 -radix unsigned} /l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(24) {-height 15 -radix unsigned} /l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(23) {-height 15 -radix unsigned} /l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(22) {-height 15 -radix unsigned} /l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(21) {-height 15 -radix unsigned} /l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(20) {-height 15 -radix unsigned} /l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(19) {-height 15 -radix unsigned} /l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(18) {-height 15 -radix unsigned} /l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(17) {-height 15 -radix unsigned} /l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(16) {-height 15 -radix unsigned} /l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(15) {-height 15 -radix unsigned} /l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(14) {-height 15 -radix unsigned} /l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(13) {-height 15 -radix unsigned} /l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(12) {-height 15 -radix unsigned} /l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(11) {-height 15 -radix unsigned} /l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(10) {-height 15 -radix unsigned} /l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(9) {-height 15 -radix unsigned} /l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(8) {-height 15 -radix unsigned} /l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(7) {-height 15 -radix unsigned} /l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(6) {-height 15 -radix unsigned} /l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(5) {-height 15 -radix unsigned} /l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(4) {-height 15 -radix unsigned} /l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(3) {-height 15 -radix unsigned} /l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(2) {-height 15 -radix unsigned} /l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(1) {-height 15 -radix unsigned} /l0_dds_writer_test1_ain/uut/cc_seq_nr(0)(0) {-height 15 -radix unsigned} /l0_dds_writer_test1_ain/uut/cc_seq_nr(1) {-height 15 -radix unsigned}} /l0_dds_writer_test1_ain/uut/cc_seq_nr +add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test1_ain/uut/get_data_rtps +add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test1_ain/uut/ready_out_rtps +add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test1_ain/uut/valid_out_rtps +add wave -noupdate -group {RTPS OUT} -radix hexadecimal /l0_dds_writer_test1_ain/uut/data_out_rtps +add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test1_ain/uut/last_word_out_rtps +add wave -noupdate -divider {DDS IN} +add wave -noupdate -expand -group DDS /l0_dds_writer_test1_ain/uut/start_dds +add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_writer_test1_ain/uut/instance_handle_dds +add wave -noupdate -expand -group DDS -radix unsigned /l0_dds_writer_test1_ain/uut/source_ts_dds +add wave -noupdate -expand -group DDS /l0_dds_writer_test1_ain/uut/opcode_dds +add wave -noupdate -expand -group DDS /l0_dds_writer_test1_ain/uut/ack_dds +add wave -noupdate -expand -group DDS /l0_dds_writer_test1_ain/uut/done_dds +add wave -noupdate -expand -group DDS -radix unsigned /l0_dds_writer_test1_ain/uut/return_code_dds +add wave -noupdate -expand -group DDS /l0_dds_writer_test1_ain/uut/ready_in_dds +add wave -noupdate -expand -group DDS /l0_dds_writer_test1_ain/uut/valid_in_dds +add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_writer_test1_ain/uut/data_in_dds +add wave -noupdate -expand -group DDS /l0_dds_writer_test1_ain/uut/last_word_in_dds +add wave -noupdate -expand -group DDS /l0_dds_writer_test1_ain/uut/ready_out_dds +add wave -noupdate -expand -group DDS /l0_dds_writer_test1_ain/uut/valid_out_dds +add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_writer_test1_ain/uut/data_out_dds +add wave -noupdate -expand -group DDS /l0_dds_writer_test1_ain/uut/last_word_out_dds +add wave -noupdate -divider {MAIN FSM} +add wave -noupdate /l0_dds_writer_test1_ain/uut/stage +add wave -noupdate /l0_dds_writer_test1_ain/uut/stage_next +add wave -noupdate /l0_dds_writer_test1_ain/uut/cnt +add wave -noupdate -radix unsigned /l0_dds_writer_test1_ain/uut/global_seq_nr +add wave -noupdate -radix unsigned /l0_dds_writer_test1_ain/uut/global_sample_cnt +add wave -noupdate -radix unsigned /l0_dds_writer_test1_ain/uut/global_ack_cnt +add wave -noupdate -radix unsigned /l0_dds_writer_test1_ain/uut/stale_inst_cnt +add wave -noupdate /l0_dds_writer_test1_ain/uut/remove_oldest_inst_sample +add wave -noupdate /l0_dds_writer_test1_ain/uut/remove_oldest_sample +add wave -noupdate /l0_dds_writer_test1_ain/uut/remove_ack_sample +add wave -noupdate -divider MEMORY +add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test1_ain/uut/sample_abort_read +add wave -noupdate -group {SAMPLE MEM} -radix unsigned -childformat {{/l0_dds_writer_test1_ain/uut/sample_mem_ctrl_inst/addr(5) -radix unsigned} {/l0_dds_writer_test1_ain/uut/sample_mem_ctrl_inst/addr(4) -radix unsigned} {/l0_dds_writer_test1_ain/uut/sample_mem_ctrl_inst/addr(3) -radix unsigned} {/l0_dds_writer_test1_ain/uut/sample_mem_ctrl_inst/addr(2) -radix unsigned} {/l0_dds_writer_test1_ain/uut/sample_mem_ctrl_inst/addr(1) -radix unsigned} {/l0_dds_writer_test1_ain/uut/sample_mem_ctrl_inst/addr(0) -radix unsigned}} -subitemconfig {/l0_dds_writer_test1_ain/uut/sample_mem_ctrl_inst/addr(5) {-height 15 -radix unsigned} /l0_dds_writer_test1_ain/uut/sample_mem_ctrl_inst/addr(4) {-height 15 -radix unsigned} /l0_dds_writer_test1_ain/uut/sample_mem_ctrl_inst/addr(3) {-height 15 -radix unsigned} /l0_dds_writer_test1_ain/uut/sample_mem_ctrl_inst/addr(2) {-height 15 -radix unsigned} /l0_dds_writer_test1_ain/uut/sample_mem_ctrl_inst/addr(1) {-height 15 -radix unsigned} /l0_dds_writer_test1_ain/uut/sample_mem_ctrl_inst/addr(0) {-height 15 -radix unsigned}} /l0_dds_writer_test1_ain/uut/sample_mem_ctrl_inst/addr +add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test1_ain/uut/sample_mem_ctrl_inst/read +add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test1_ain/uut/sample_mem_ctrl_inst/ready_in +add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test1_ain/uut/sample_mem_ctrl_inst/valid_in +add wave -noupdate -group {SAMPLE MEM} -radix hexadecimal /l0_dds_writer_test1_ain/uut/sample_mem_ctrl_inst/data_in +add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test1_ain/uut/sample_mem_ctrl_inst/ready_out +add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test1_ain/uut/sample_mem_ctrl_inst/valid_out +add wave -noupdate -group {SAMPLE MEM} -radix hexadecimal /l0_dds_writer_test1_ain/uut/sample_mem_ctrl_inst/data_out +add wave -noupdate -expand -group {PAYLOAD MEM} /l0_dds_writer_test1_ain/uut/payload_abort_read +add wave -noupdate -expand -group {PAYLOAD MEM} -radix unsigned /l0_dds_writer_test1_ain/uut/payload_mem_ctrl_inst/addr +add wave -noupdate -expand -group {PAYLOAD MEM} /l0_dds_writer_test1_ain/uut/payload_mem_ctrl_inst/read +add wave -noupdate -expand -group {PAYLOAD MEM} /l0_dds_writer_test1_ain/uut/payload_mem_ctrl_inst/ready_in +add wave -noupdate -expand -group {PAYLOAD MEM} /l0_dds_writer_test1_ain/uut/payload_mem_ctrl_inst/valid_in +add wave -noupdate -expand -group {PAYLOAD MEM} -radix hexadecimal /l0_dds_writer_test1_ain/uut/payload_mem_ctrl_inst/data_in +add wave -noupdate -expand -group {PAYLOAD MEM} /l0_dds_writer_test1_ain/uut/payload_mem_ctrl_inst/ready_out +add wave -noupdate -expand -group {PAYLOAD MEM} /l0_dds_writer_test1_ain/uut/payload_mem_ctrl_inst/valid_out +add wave -noupdate -expand -group {PAYLOAD MEM} -radix hexadecimal /l0_dds_writer_test1_ain/uut/payload_mem_ctrl_inst/data_out +add wave -noupdate -childformat {{/l0_dds_writer_test1_ain/uut/inst_data.key_hash -radix hexadecimal} {/l0_dds_writer_test1_ain/uut/inst_data.status_info -radix binary} {/l0_dds_writer_test1_ain/uut/inst_data.sample_cnt -radix unsigned} {/l0_dds_writer_test1_ain/uut/inst_data.ack_cnt -radix unsigned}} -expand -subitemconfig {/l0_dds_writer_test1_ain/uut/inst_data.key_hash {-height 15 -radix hexadecimal} /l0_dds_writer_test1_ain/uut/inst_data.status_info {-height 15 -radix binary} /l0_dds_writer_test1_ain/uut/inst_data.sample_cnt {-height 15 -radix unsigned} /l0_dds_writer_test1_ain/uut/inst_data.ack_cnt {-height 15 -radix unsigned}} /l0_dds_writer_test1_ain/uut/inst_data +add wave -noupdate -divider {KEY HOLDER} +add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test1_ain/uut/start_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test1_ain/uut/opcode_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test1_ain/uut/ack_kh +add wave -noupdate -group {KEY HOLDER} -radix hexadecimal /l0_dds_writer_test1_ain/uut/data_in_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test1_ain/uut/valid_in_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test1_ain/uut/ready_in_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test1_ain/uut/last_word_in_kh +add wave -noupdate -group {KEY HOLDER} -radix hexadecimal /l0_dds_writer_test1_ain/uut/data_out_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test1_ain/uut/valid_out_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test1_ain/uut/ready_out_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test1_ain/uut/last_word_out_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test1_ain/uut/abort_kh +add wave -noupdate -divider POINTERS +add wave -noupdate -expand -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test1_ain/uut/empty_sample_list_head +add wave -noupdate -expand -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test1_ain/uut/empty_sample_list_tail +add wave -noupdate -expand -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test1_ain/uut/empty_payload_list_head +add wave -noupdate -expand -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test1_ain/uut/oldest_sample +add wave -noupdate -expand -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test1_ain/uut/newest_sample +add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test1_ain/uut/cur_sample +add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test1_ain/uut/prev_sample +add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test1_ain/uut/next_sample +add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test1_ain/uut/cur_payload +add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test1_ain/uut/next_payload +add wave -noupdate -divider TESTBENCH +add wave -noupdate -expand -group TESTBENCH /l0_dds_writer_test1_ain/stim_start +add wave -noupdate -expand -group TESTBENCH /l0_dds_writer_test1_ain/stim_stage +add wave -noupdate -expand -group TESTBENCH /l0_dds_writer_test1_ain/stim_cnt +add wave -noupdate -expand -group TESTBENCH /l0_dds_writer_test1_ain/stim_done +add wave -noupdate -expand -group TESTBENCH /l0_dds_writer_test1_ain/ref_start +add wave -noupdate -expand -group TESTBENCH /l0_dds_writer_test1_ain/ref_stage +add wave -noupdate -expand -group TESTBENCH /l0_dds_writer_test1_ain/ref_cnt +add wave -noupdate -expand -group TESTBENCH /l0_dds_writer_test1_ain/ref_done +add wave -noupdate -expand -group TESTBENCH /l0_dds_writer_test1_ain/kh_cnt +add wave -noupdate -expand -group TESTBENCH /l0_dds_writer_test1_ain/kh_stage +add wave -noupdate -divider MISC +add wave -noupdate /l0_dds_writer_test1_ain/uut/cnt2 +add wave -noupdate /l0_dds_writer_test1_ain/uut/cnt3 +add wave -noupdate -radix unsigned /l0_dds_writer_test1_ain/uut/long_latch +add wave -noupdate /l0_dds_writer_test1_ain/uut/sample_status_info +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {642360 ps} 0} +quietly wave cursor active 1 +configure wave -namecolwidth 187 +configure wave -valuecolwidth 100 +configure wave -justifyvalue left +configure wave -signalnamewidth 1 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ns +update +WaveRestoreZoom {300185 ps} {1300826 ps} diff --git a/sim/L0_dds_writer_test1_lik.do b/sim/L0_dds_writer_test1_lik.do new file mode 100644 index 0000000..41021ad --- /dev/null +++ b/sim/L0_dds_writer_test1_lik.do @@ -0,0 +1,150 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate -divider SYSTEM +add wave -noupdate /l0_dds_writer_test1_lik/uut/clk +add wave -noupdate /l0_dds_writer_test1_lik/uut/reset +add wave -noupdate -radix unsigned /l0_dds_writer_test1_lik/uut/time +add wave -noupdate -divider {RTPS IN} +add wave -noupdate -group {RTPS IN} /l0_dds_writer_test1_lik/uut/start_rtps +add wave -noupdate -group {RTPS IN} -radix unsigned /l0_dds_writer_test1_lik/uut/seq_nr_rtps +add wave -noupdate -group {RTPS IN} /l0_dds_writer_test1_lik/uut/opcode_rtps +add wave -noupdate -group {RTPS IN} /l0_dds_writer_test1_lik/uut/ack_rtps +add wave -noupdate -group {RTPS IN} /l0_dds_writer_test1_lik/uut/done_rtps +add wave -noupdate -group {RTPS IN} /l0_dds_writer_test1_lik/uut/ret_rtps +add wave -noupdate -divider {RTPS OUT} +add wave -noupdate -group {RTPS OUT} -radix hexadecimal /l0_dds_writer_test1_lik/uut/cc_instance_handle +add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test1_lik/uut/cc_kind +add wave -noupdate -group {RTPS OUT} -radix unsigned /l0_dds_writer_test1_lik/uut/cc_source_timestamp +add wave -noupdate -group {RTPS OUT} -radix unsigned -childformat {{/l0_dds_writer_test1_lik/uut/cc_seq_nr(0) -radix unsigned -childformat {{/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(31) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(30) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(29) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(28) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(27) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(26) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(25) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(24) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(23) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(22) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(21) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(20) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(19) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(18) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(17) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(16) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(15) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(14) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(13) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(12) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(11) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(10) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(9) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(8) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(7) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(6) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(5) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(4) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(3) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(2) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(1) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(0) -radix unsigned}}} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(1) -radix unsigned}} -subitemconfig {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0) {-height 15 -radix unsigned -childformat {{/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(31) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(30) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(29) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(28) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(27) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(26) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(25) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(24) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(23) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(22) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(21) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(20) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(19) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(18) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(17) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(16) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(15) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(14) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(13) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(12) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(11) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(10) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(9) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(8) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(7) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(6) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(5) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(4) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(3) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(2) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(1) -radix unsigned} {/l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(0) -radix unsigned}}} /l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(31) {-height 15 -radix unsigned} /l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(30) {-height 15 -radix unsigned} /l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(29) {-height 15 -radix unsigned} /l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(28) {-height 15 -radix unsigned} /l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(27) {-height 15 -radix unsigned} /l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(26) {-height 15 -radix unsigned} /l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(25) {-height 15 -radix unsigned} /l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(24) {-height 15 -radix unsigned} /l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(23) {-height 15 -radix unsigned} /l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(22) {-height 15 -radix unsigned} /l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(21) {-height 15 -radix unsigned} /l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(20) {-height 15 -radix unsigned} /l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(19) {-height 15 -radix unsigned} /l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(18) {-height 15 -radix unsigned} /l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(17) {-height 15 -radix unsigned} /l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(16) {-height 15 -radix unsigned} /l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(15) {-height 15 -radix unsigned} /l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(14) {-height 15 -radix unsigned} /l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(13) {-height 15 -radix unsigned} /l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(12) {-height 15 -radix unsigned} /l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(11) {-height 15 -radix unsigned} /l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(10) {-height 15 -radix unsigned} /l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(9) {-height 15 -radix unsigned} /l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(8) {-height 15 -radix unsigned} /l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(7) {-height 15 -radix unsigned} /l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(6) {-height 15 -radix unsigned} /l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(5) {-height 15 -radix unsigned} /l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(4) {-height 15 -radix unsigned} /l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(3) {-height 15 -radix unsigned} /l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(2) {-height 15 -radix unsigned} /l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(1) {-height 15 -radix unsigned} /l0_dds_writer_test1_lik/uut/cc_seq_nr(0)(0) {-height 15 -radix unsigned} /l0_dds_writer_test1_lik/uut/cc_seq_nr(1) {-height 15 -radix unsigned}} /l0_dds_writer_test1_lik/uut/cc_seq_nr +add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test1_lik/uut/get_data_rtps +add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test1_lik/uut/ready_out_rtps +add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test1_lik/uut/valid_out_rtps +add wave -noupdate -group {RTPS OUT} -radix hexadecimal /l0_dds_writer_test1_lik/uut/data_out_rtps +add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test1_lik/uut/last_word_out_rtps +add wave -noupdate -divider {DDS IN} +add wave -noupdate -expand -group DDS /l0_dds_writer_test1_lik/uut/start_dds +add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_writer_test1_lik/uut/instance_handle_dds +add wave -noupdate -expand -group DDS -radix unsigned /l0_dds_writer_test1_lik/uut/source_ts_dds +add wave -noupdate -expand -group DDS /l0_dds_writer_test1_lik/uut/opcode_dds +add wave -noupdate -expand -group DDS /l0_dds_writer_test1_lik/uut/ack_dds +add wave -noupdate -expand -group DDS /l0_dds_writer_test1_lik/uut/done_dds +add wave -noupdate -expand -group DDS -radix unsigned /l0_dds_writer_test1_lik/uut/return_code_dds +add wave -noupdate -expand -group DDS /l0_dds_writer_test1_lik/uut/ready_in_dds +add wave -noupdate -expand -group DDS /l0_dds_writer_test1_lik/uut/valid_in_dds +add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_writer_test1_lik/uut/data_in_dds +add wave -noupdate -expand -group DDS /l0_dds_writer_test1_lik/uut/last_word_in_dds +add wave -noupdate -expand -group DDS /l0_dds_writer_test1_lik/uut/ready_out_dds +add wave -noupdate -expand -group DDS /l0_dds_writer_test1_lik/uut/valid_out_dds +add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_writer_test1_lik/uut/data_out_dds +add wave -noupdate -expand -group DDS /l0_dds_writer_test1_lik/uut/last_word_out_dds +add wave -noupdate -divider {MAIN FSM} +add wave -noupdate /l0_dds_writer_test1_lik/uut/stage +add wave -noupdate /l0_dds_writer_test1_lik/uut/stage_next +add wave -noupdate /l0_dds_writer_test1_lik/uut/cnt +add wave -noupdate -radix unsigned /l0_dds_writer_test1_lik/uut/global_seq_nr +add wave -noupdate -radix unsigned /l0_dds_writer_test1_lik/uut/global_sample_cnt +add wave -noupdate -radix unsigned /l0_dds_writer_test1_lik/uut/global_ack_cnt +add wave -noupdate -radix unsigned /l0_dds_writer_test1_lik/uut/stale_inst_cnt +add wave -noupdate /l0_dds_writer_test1_lik/uut/remove_oldest_inst_sample +add wave -noupdate /l0_dds_writer_test1_lik/uut/remove_oldest_sample +add wave -noupdate /l0_dds_writer_test1_lik/uut/remove_ack_sample +add wave -noupdate -divider MEMORY +add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test1_lik/uut/sample_abort_read +add wave -noupdate -group {SAMPLE MEM} -radix unsigned -childformat {{/l0_dds_writer_test1_lik/uut/sample_mem_ctrl_inst/addr(5) -radix unsigned} {/l0_dds_writer_test1_lik/uut/sample_mem_ctrl_inst/addr(4) -radix unsigned} {/l0_dds_writer_test1_lik/uut/sample_mem_ctrl_inst/addr(3) -radix unsigned} {/l0_dds_writer_test1_lik/uut/sample_mem_ctrl_inst/addr(2) -radix unsigned} {/l0_dds_writer_test1_lik/uut/sample_mem_ctrl_inst/addr(1) -radix unsigned} {/l0_dds_writer_test1_lik/uut/sample_mem_ctrl_inst/addr(0) -radix unsigned}} -subitemconfig {/l0_dds_writer_test1_lik/uut/sample_mem_ctrl_inst/addr(5) {-height 15 -radix unsigned} /l0_dds_writer_test1_lik/uut/sample_mem_ctrl_inst/addr(4) {-height 15 -radix unsigned} /l0_dds_writer_test1_lik/uut/sample_mem_ctrl_inst/addr(3) {-height 15 -radix unsigned} /l0_dds_writer_test1_lik/uut/sample_mem_ctrl_inst/addr(2) {-height 15 -radix unsigned} /l0_dds_writer_test1_lik/uut/sample_mem_ctrl_inst/addr(1) {-height 15 -radix unsigned} /l0_dds_writer_test1_lik/uut/sample_mem_ctrl_inst/addr(0) {-height 15 -radix unsigned}} /l0_dds_writer_test1_lik/uut/sample_mem_ctrl_inst/addr +add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test1_lik/uut/sample_mem_ctrl_inst/read +add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test1_lik/uut/sample_mem_ctrl_inst/ready_in +add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test1_lik/uut/sample_mem_ctrl_inst/valid_in +add wave -noupdate -group {SAMPLE MEM} -radix hexadecimal /l0_dds_writer_test1_lik/uut/sample_mem_ctrl_inst/data_in +add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test1_lik/uut/sample_mem_ctrl_inst/ready_out +add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test1_lik/uut/sample_mem_ctrl_inst/valid_out +add wave -noupdate -group {SAMPLE MEM} -radix hexadecimal /l0_dds_writer_test1_lik/uut/sample_mem_ctrl_inst/data_out +add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test1_lik/uut/payload_abort_read +add wave -noupdate -group {PAYLOAD MEM} -radix unsigned /l0_dds_writer_test1_lik/uut/payload_mem_ctrl_inst/addr +add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test1_lik/uut/payload_mem_ctrl_inst/read +add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test1_lik/uut/payload_mem_ctrl_inst/ready_in +add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test1_lik/uut/payload_mem_ctrl_inst/valid_in +add wave -noupdate -group {PAYLOAD MEM} -radix hexadecimal /l0_dds_writer_test1_lik/uut/payload_mem_ctrl_inst/data_in +add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test1_lik/uut/payload_mem_ctrl_inst/ready_out +add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test1_lik/uut/payload_mem_ctrl_inst/valid_out +add wave -noupdate -group {PAYLOAD MEM} -radix hexadecimal /l0_dds_writer_test1_lik/uut/payload_mem_ctrl_inst/data_out +add wave -noupdate /l0_dds_writer_test1_lik/uut/inst_op_start +add wave -noupdate /l0_dds_writer_test1_lik/uut/inst_opcode +add wave -noupdate /l0_dds_writer_test1_lik/uut/inst_op_done +add wave -noupdate /l0_dds_writer_test1_lik/uut/inst_stage +add wave -noupdate /l0_dds_writer_test1_lik/uut/inst_stage_next +add wave -noupdate /l0_dds_writer_test1_lik/uut/inst_cnt +add wave -noupdate -radix unsigned /l0_dds_writer_test1_lik/uut/inst_addr_base +add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test1_lik/uut/inst_abort_read +add wave -noupdate -group {INSTANCE MEM} -radix unsigned /l0_dds_writer_test1_lik/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/addr +add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test1_lik/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/read +add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test1_lik/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/ready_in +add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test1_lik/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/valid_in +add wave -noupdate -group {INSTANCE MEM} -radix hexadecimal /l0_dds_writer_test1_lik/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/data_in +add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test1_lik/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/ready_out +add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test1_lik/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/valid_out +add wave -noupdate -group {INSTANCE MEM} -radix hexadecimal /l0_dds_writer_test1_lik/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/data_out +add wave -noupdate -childformat {{/l0_dds_writer_test1_lik/uut/inst_data.key_hash -radix hexadecimal} {/l0_dds_writer_test1_lik/uut/inst_data.status_info -radix binary} {/l0_dds_writer_test1_lik/uut/inst_data.sample_cnt -radix unsigned} {/l0_dds_writer_test1_lik/uut/inst_data.ack_cnt -radix unsigned}} -expand -subitemconfig {/l0_dds_writer_test1_lik/uut/inst_data.key_hash {-height 15 -radix hexadecimal} /l0_dds_writer_test1_lik/uut/inst_data.status_info {-height 15 -radix binary} /l0_dds_writer_test1_lik/uut/inst_data.sample_cnt {-height 15 -radix unsigned} /l0_dds_writer_test1_lik/uut/inst_data.ack_cnt {-height 15 -radix unsigned}} /l0_dds_writer_test1_lik/uut/inst_data +add wave -noupdate -radix unsigned /l0_dds_writer_test1_lik/uut/inst_next_addr_base +add wave -noupdate -radix unsigned /l0_dds_writer_test1_lik/uut/inst_prev_addr_base +add wave -noupdate -divider {KEY HOLDER} +add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test1_lik/uut/start_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test1_lik/uut/opcode_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test1_lik/uut/ack_kh +add wave -noupdate -group {KEY HOLDER} -radix hexadecimal /l0_dds_writer_test1_lik/uut/data_in_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test1_lik/uut/valid_in_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test1_lik/uut/ready_in_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test1_lik/uut/last_word_in_kh +add wave -noupdate -group {KEY HOLDER} -radix hexadecimal /l0_dds_writer_test1_lik/uut/data_out_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test1_lik/uut/valid_out_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test1_lik/uut/ready_out_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test1_lik/uut/last_word_out_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test1_lik/uut/abort_kh +add wave -noupdate -divider POINTERS +add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test1_lik/uut/empty_sample_list_head +add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test1_lik/uut/empty_sample_list_tail +add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test1_lik/uut/empty_payload_list_head +add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test1_lik/uut/oldest_sample +add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test1_lik/uut/newest_sample +add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test1_lik/uut/inst_empty_head +add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test1_lik/uut/inst_occupied_head +add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test1_lik/uut/cur_sample +add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test1_lik/uut/prev_sample +add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test1_lik/uut/next_sample +add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test1_lik/uut/cur_payload +add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test1_lik/uut/next_payload +add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test1_lik/uut/cur_inst +add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test1_lik/uut/next_inst +add wave -noupdate -divider TESTBENCH +add wave -noupdate -group TESTBENCH /l0_dds_writer_test1_lik/stim_start +add wave -noupdate -group TESTBENCH /l0_dds_writer_test1_lik/stim_stage +add wave -noupdate -group TESTBENCH /l0_dds_writer_test1_lik/stim_cnt +add wave -noupdate -group TESTBENCH /l0_dds_writer_test1_lik/stim_done +add wave -noupdate -group TESTBENCH /l0_dds_writer_test1_lik/ref_start +add wave -noupdate -group TESTBENCH /l0_dds_writer_test1_lik/ref_stage +add wave -noupdate -group TESTBENCH /l0_dds_writer_test1_lik/ref_cnt +add wave -noupdate -group TESTBENCH /l0_dds_writer_test1_lik/ref_done +add wave -noupdate -group TESTBENCH /l0_dds_writer_test1_lik/kh_cnt +add wave -noupdate -group TESTBENCH /l0_dds_writer_test1_lik/kh_stage +add wave -noupdate -divider MISC +add wave -noupdate /l0_dds_writer_test1_lik/uut/cnt2 +add wave -noupdate /l0_dds_writer_test1_lik/uut/cnt3 +add wave -noupdate -radix unsigned /l0_dds_writer_test1_lik/uut/long_latch +add wave -noupdate /l0_dds_writer_test1_lik/uut/sample_status_info +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {106575000 ps} 0} +quietly wave cursor active 1 +configure wave -namecolwidth 187 +configure wave -valuecolwidth 100 +configure wave -justifyvalue left +configure wave -signalnamewidth 1 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ns +update +WaveRestoreZoom {106074680 ps} {107075321 ps} diff --git a/src/REF.txt b/src/REF.txt index 3fe993f..af7c70d 100644 --- a/src/REF.txt +++ b/src/REF.txt @@ -468,7 +468,7 @@ WRITER +-------------------------------------------------------------+ 07| PAYLOAD_ADDRESS | +-------------------------------------------------------------+ -08| INSTANCE_ADDRESS | +08| INSTANCE_ADDRESS | [only if WITH_KEY] +-------------------------------------------------------------+ 09| PREV_ADDRESS | +-------------------------------------------------------------+ @@ -783,6 +783,16 @@ NOTE: Writing data via the write operation on a DataWriter asserts liveliness on and its DomainParticipant. Consequently the use of assert_liveliness is only needed if the application is not writing data regularly. +2.2.2.4.2.11 write (DDS) +If (RESOURCE_LIMITS max_samples < RESOURCE_LIMITS max_instances * HISTORY depth), then in the situation +where the max_samples resource limit is exhausted the Service is allowed to discard samples of some other +instance as long as at least one sample remains for such an instance. If it is still not possible to make +space available to store the modification, the writer is allowed to block. + +2.2.2.4.2.7 unregister_instance (DDS) +If after that, the application wants to modify (write or dispose) the instance, it has to register it again, +or else use the special handle value HANDLE_NIL. + INVALIDATION ============ diff --git a/src/TODO.txt b/src/TODO.txt index 4b640c8..e74bf2b 100644 --- a/src/TODO.txt +++ b/src/TODO.txt @@ -66,8 +66,7 @@ - opendds sends Payload Encapsulation with a Key Holder Object (As defined in XType 7.6.8) - opensplice seems todo the same as opendds * Currently the builtin-endpoint does only acknowledge SN, but does not negatively acknowledge any SN (Bitamp is always empty). - A writer usually responds with repqirs only to negative acknowledgements. -* Currently a RTPS Writer with DURABILITY TARNSIENT_LOCAL does send historical data to all matched readers, not depending if they are VOLATILE or TRANSIENT_LOCAL. + A writer usually responds with repairs only to negative acknowledgements. * Assert Heartbeat period > Heartbeat Suppression Period * Can I request (NACK) SNs that were NOT announced by the writer (> last_sn in Heartbeat)? * Does AUTOMATIC Liveliness QoS also update the lease on write/assert_liveliness operations? @@ -153,7 +152,14 @@ - 2.2.3 Supported QoS Partition is marked as RxO=No, but should be RxO=Yes? Or not? - Existing Issue: https://issues.omg.org/issues/DDS15-245 - + - How is History QoS affecting MAX_INSTANCES handling (if at all). When is an instance eligibale for + replacement. + - 2.2.2.4.2.5 register_instance + This operation may block and return TIMEOUT under the same circumstances described for the write operation + This operation may return OUT_OF_RESOURCES under the same circumstances described for the write operation + But the opration only returns InstanceHandle_t. Other vendors return HANDLE_NIL also on error and not only + "if the Service does not want to allocate any handle for that instance". + It should propably behave like the Lookup_Instance operation. * Source Port of SPDP is irrelevant, since it is BEST EFFORT and we do not reply (only Destination Port is of significance) @@ -254,6 +260,23 @@ DESIGN DECISIONS The RTPS Endpoint will have to output multiple versions of Changes, depending on the connected Entity, in order to facilitate this design decision. +* Because the Key Hash has to be known in order to make an ACCEPT/REJECT decision for the new + Sample, and the fact that the Key Hash is not always given and has to be manually calculated from + the payload, we need "buffer" slots to store the Sample and Payload until the decision can be + made. This temporal "buffer" is not implemented explicitly, but implicitly by having an extra + slot in the empty list of the memory. The Sample is added to the Empty List Head, and only added + to the occupied list tail if the Sample is accepted. In case an Older Sample needs to be removed + due to the QoS policy, this is done after the Sample Addition has been finalized (has been added + to the Occupied List), because the Sample Removal will modify the Empty List and the new Sample + would be lost if done prior to the finalization. + I.e. a single slot has to be available in the Sample/Payload Memory at all times. This is easy + for the Sample Memory, but more complicated for the Payload memory due to the dynamic slot nature + that it can have. It may happen that after an addition we have a "buffer" Sample Memory Slot, but + no Payload slot. In order to mitigate this we have to actively check the payload memory prior to + the addition and either delete the oldest sample or immediately reject the operation. This may lead + to multiple Sample removals (One prior the addition in order to free up a Payload "buffer", and + one after addition as a result of QoS policies). + * Since the "reading" side needs to have consistent state during it's processing, it does not make sense to implement dual port RAMs for the History Cache. @@ -281,6 +304,35 @@ DESIGN DECISIONS a PLAIN_CDR/PL_CDR Data Stream from the registers. Due to the type-specific nature of the entities, those are not instantiated inside the DDS Endpoints, but will be instantiated in a wrapper and linked through port mapping with the DDS Enspoints. + +* Due to the requirements of read_next_instance/take_next_instance of the DDS Reader, the Instances are + inserted in numerical Key Hash order into the Instance Memory. This extra sorting logic is not needed + in the DDS Writer, where Instances are inserted normally to the end of the List. + +* The Specification does not really specify how handling of MAX_INSTANCES is affected by the HISTORY QoS + Policy (if at all). The current implementation ignores the HISTORY QoS and only removes stale instances + (Instances that are Unregistered and have all Samples acknowledged). + +* According to the DDS Specification the resources taken from an instance can be freed locally if the + instance is Unregistered, and globally if the Instance is Disposed (And all Instance Samples have been + ACKed/READ/Taken). There are scenarios where removing a Disposed, but still registered Instance may + lead to inconsistent behavior (see REF.txt). RTI has thus decided to only delete unregistered + instances. I will copy this behavior. + +* DATA WRITER: Once an instance is unregistered, it is eligible for deletion except if it is + Re-registered, or a write operation occurs on that instance. Disposal of an unregistered Instance + does not re-register the instance (State remains NOT_ALIVE) and is still eligible for deletion. + +* The DDS Specification does not explicitly state that the behaviour of the Register/Unregister/Dispose + Operations have on non-keyed Topics. RTI basically does a NOP and does not modify the instance in + any way. I basically do a NOP for the Register Operation (in the sense that it does not modify the + instance in any kind of way), but still implemented the Unregister and Dispose Operations, meaning + that the Data Readers will receive a state change. + +* The DDS Specification states that if after an Unregister Operation "the application wants to modify + (write or dispose) the instance, it has to register it again, or else use the special handle value + HANDLE_NIL". I do not have this prerequirement. it will return BAD_PARAMETER only if the Instance + is not in the memory anymore. PROTOCOL UNCOMPLIANCE ===================== diff --git a/src/Tests/Level_0/L0_dds_writer_test1_afk.vhd b/src/Tests/Level_0/L0_dds_writer_test1_afk.vhd new file mode 100644 index 0000000..5821274 --- /dev/null +++ b/src/Tests/Level_0/L0_dds_writer_test1_afk.vhd @@ -0,0 +1,2179 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library osvvm; -- Utility Library +context osvvm.OsvvmContext; + +use work.rtps_package.all; +use work.user_config.all; +use work.rtps_config_package.all; +use work.rtps_test_package.all; + +entity L0_dds_writer_test1_afk is +end entity; + +-- This testbench tests the General Operation of the DDS Writer. It tests the correctness of the RTPS +-- GET_MIN_SN, GET_MAX_SN, GET_CACHE_CHANGE, REMOVE_CACHE_CHANGE, ACK_CACHE_CHANGE, and NACK_CACHE_CHANGE Operations and the +-- DDS REGISTER_INSTANCE, UNREGISTER_INSTANCE, WRITE, DISPOSE, and LOOKUP_INSTANCE Operations. +-- More specifically the testbench covers following tests: +-- TEST: GET_MIN_SN/GET_MAX_SN ON EMPTY +-- TEST: GET_MIN_SN/GET_MAX_SN ON 1 SAMPLE +-- TEST: GET_MIN_SN/GET_MAX_SN ON >1 SAMPLE +-- TEST: ADD SAMPLE WITH KEY_HASH [UNKNOWN INSTANCE] +-- TEST: ADD SAMPLE WITH KEY_HASH [KNOWN INSTANCE] +-- TEST: ADD SAMPLE WITH HANDLE_NIL [UNKNOWN INSTANCE] +-- TEST: ADD SAMPLE WITH HANDLE_NIL [KNOWN INSTANCE] +-- TEST: NORMAL WRITE +-- TEST: WRITE ON PAYLOAD MEMORY FULL [WITHOUT ACKed SAMPLES] +-- TEST: WRITE ON PAYLOAD MEMORY FULL [WITH ACKed SAMPLES] +-- TEST: WRITE ON DISPOSED INSTANCE +-- TEST: WRITE ON UNREGISTERED INSTANCE +-- TEST: WRITE ALIGNED PAYLOAD +-- TEST: WRITE UNALIGNED PAYLOAD [>1 SLOT] +-- TEST: WRITE UNALIGNED PAYLOAD [<1 SLOT] +-- TEST: NORMAL REGISTER +-- TEST: REGISTER INSTANCE [KNOWN INSTANCE] +-- TEST: REGISTER INSTANCE ON MAX_INSTANCES [UNKNOWN INSTANCE, WITHOUT STALE INSTANCE] +-- TEST: REGISTER INSTANCE ON MAX_INSTANCES [UNKNOWN INSTANCE, WITH STALE INSTANCE] +-- TEST: REGISTER ON UNREGISTERED INSTANCE +-- TEST: NORMAL DISPOSE +-- TEST: DISPOSE ON PAYLOAD MEMORY FULL [WITHOUT ACKed SAMPLES] +-- TEST: DISPOSE ON PAYLOAD MEMORY FULL [WITH ACKed SAMPLES] +-- TEST: DISPOSE ON UNREGISTERED INSTANCE +-- TEST: GET_CACHE_CHANGE [UNKNOWN SN] +-- TEST: GET_CACHE_CHANGE [KNOWN SN, ALIGNED PAYLOAD] +-- TEST: GET_CACHE_CHANGE [KNOWN SN, UNALIGNED PAYLOAD, >1 SLOT] +-- TEST: GET_CACHE_CHANGE [KNOWN SN, UNALIGNED PAYLOAD, <1 SLOT] +-- TEST: NORMAL ACK_CACHE_CHANGE +-- TEST: ACK_CACHE_CHANGE [ALREADY ACKed SN] +-- TEST: NORMAL NACK_CACHE_CHANGE +-- TEST: REMOVE_CACHE_CHANGE [UNKNOWN SN] +-- TEST: REMOVE_CACHE_CHANGE [KNOWN SN] +-- TEST: NORMAL UNREGISTER +-- TEST: UNREGISTER INSTANCE ON PAYLOAD MEMORY FULL [WITHOUT ACKed SAMPLES] +-- TEST: UNREGISTER INSTANCE ON PAYLOAD MEMORY FULL [WITH ACKed SAMPLES] +-- TEST: UNREGISTER ON DISPOSED INSTANCE +-- TEST: UNREGISTER UNKNOWN INSTANCE +-- TEST: REMOVE STALE INSTANCE WITH 0 SAMPLES +-- TEST: REMOVE STALE INSTANCE WITH 1 SAMPLES +-- TEST: REMOVE STALE INSTANCE WITH >1 SAMPLES +-- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKNOWN INSTANCE, WITH STALE INSTANCE] +-- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKNOWN INSTANCE, WITHOUT STALE INSTANCES] +-- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKNOWN INSTANCE, WITH FULLY ACKed INSTANCE, WITHOUT STALE INSTANCE] +-- TEST: ADD SAMPLE ON MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE, WITHOUT ACKed SAMPLES] +-- TEST: ADD SAMPLE ON MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE, WITH ACKed SAMPLES, WITHOUT ACKed INSTANCE SAMPLES] +-- TEST: ADD SAMPLE ON MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE, WITH ACKed INSTANCE SAMPLE] +-- TEST: ADD SAMPLE ON MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE, WITH ACKed INSTANCE SAMPLES(>1)] +-- TEST: ADD SAMPLE ON MAX_SAMPLES [KNOWN INSTANCE,WITHOUT ACKed SAMPLES] +-- TEST: ADD SAMPLE ON MAX_SAMPLES [KNOWN INSTANCE,WITH ACKed SAMPLE] +-- TEST: ADD SAMPLE ON MAX_SAMPLES [KNOWN INSTANCE,WITH ACKed SAMPLES (>1)] +-- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE,WITHOUT ACKed SAMPLES] +-- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE,WITH ACKed SAMPLES, WITHOUT ACKed INSTANCE SAMPLES] +-- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE,WITH ACKed INSTANCE SAMPLES] +-- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE,WITH STALE INSTANCE, WITHOUT ACKed SAMPLE] +-- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE,WITHOUT STALE INSTANCES,WITHOUT ACKed SAMPLES] +-- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE,WITHOUT STALE INSTANCE, WITH ACKed SAMPLE] +-- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE,WITH STALE INSTANCE (>0 SAMPLES)] +-- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE,WITH STALE INSTANCE, WITH ACKed SAMPLE] +-- TEST: ADD SAMPLE ON PAYLOAD FULL & MAX_INSTANCES [UNKNOWN INSTANCE,WITH ACKed SAMPLES,WITH STALE INSTANCE (>= 1 SAMPLE)] (Induce Double Remove) +-- TEST: ADD SAMPLE BIGGER THAN AVAILABLE MEMORY SPACE [WITH ACKed SAMPLES] +-- TEST: INSTANCE LOOKUP [KNOWN INSTANCE] +-- TEST: INSTANCE LOOKUP [UNKNOWN INSTANCE] + +architecture testbench of L0_dds_writer_test1_afk is + + -- *CONSTANT DECLARATION* + constant MAX_REMOTE_ENDPOINTS : natural := 3; + + -- *TYPE DECLARATION* + type STIM_STAGE_TYPE is (IDLE, START, PUSH, DONE, CHECK); + type REF_STAGE_TYPE is (IDLE, START, DONE, CHECK); + type KH_STAGE_TYPE is (IDLE, READ_DATA, PUSH_KEY_HASH); + type RTPS_TEST_TYPE is record + opcode : HISTORY_CACHE_OPCODE_TYPE; + cc : CACHE_CHANGE_TYPE; + ret_code : HISTORY_CACHE_RESPONSE_TYPE; + end record; + constant DEFAULT_RTPS_TEST : RTPS_TEST_TYPE := ( + opcode => NOP, + cc => DEFAULT_CACHE_CHANGE, + ret_code => OK + ); + type DDS_TEST_TYPE is record + opcode : DDS_WRITER_OPCODE_TYPE; + cc : CACHE_CHANGE_TYPE; + ret_code : std_logic_vector(RETURN_CODE_WIDTH-1 downto 0); + end record; + constant DEFAULT_DDS_TEST : DDS_TEST_TYPE := ( + opcode => NOP, + cc => DEFAULT_CACHE_CHANGE, + ret_code => RETCODE_OK + ); + + -- *SIGNAL DECLARATION* + signal clk : std_logic := '0'; + signal reset : std_logic := '1'; + signal check_time : TIME_TYPE := TIME_ZERO; + signal start_rtps, start_dds, start_kh, ack_rtps, ack_dds, ack_kh, done_rtps, done_dds : std_logic := '0'; + signal opcode_rtps : HISTORY_CACHE_OPCODE_TYPE := NOP; + signal opcode_dds : DDS_WRITER_OPCODE_TYPE := NOP; + signal opcode_kh : KEY_HOLDER_OPCODE_TYPE := NOP; + signal ret_rtps : HISTORY_CACHE_RESPONSE_TYPE := ERROR; + signal seq_nr_rtps, cc_seq_nr : SEQUENCENUMBER_TYPE := SEQUENCENUMBER_UNKNOWN; + signal ready_out_rtps, valid_out_rtps, last_word_out_rtps : std_logic := '0'; + signal ready_in_dds, ready_out_dds, valid_in_dds, valid_out_dds, last_word_in_dds, last_word_out_dds : std_logic := '0'; + signal ready_in_kh, ready_out_kh, valid_in_kh, valid_out_kh, last_word_in_kh, last_word_out_kh : std_logic := '0'; + signal data_out_rtps, data_in_dds, data_out_dds, data_in_kh, data_out_kh : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); + signal get_data_rtps, liveliness_assertion, data_available, abort_kh : std_logic := '0'; + signal cc_source_timestamp, source_ts_dds : TIME_TYPE := TIME_INVALID; + signal cc_kind : CACHE_CHANGE_KIND_TYPE := ALIVE; + signal cc_instance_handle, instance_handle_dds : INSTANCE_HANDLE_TYPE := HANDLE_NIL; + signal max_wait_dds : DURATION_TYPE := DURATION_INFINITE; + signal return_code_dds : std_logic_vector(RETURN_CODE_WIDTH-1 downto 0) := (others => '0'); + signal status : std_logic_vector(STATUS_KIND_WIDTH-1 downto 0) := (others => '0'); + + signal stim_start, stim_done, ref_start, ref_done : std_logic := '0'; + signal stim_cnt, ref_cnt, kh_cnt : natural := 0; + signal stim_stage : STIM_STAGE_TYPE := IDLE; + signal ref_stage : REF_STAGE_TYPE := IDLE; + signal kh_stage : KH_STAGE_TYPE := IDLE; + signal kh_data : TEST_PACKET_TYPE := EMPTY_TEST_PACKET; + shared variable stimulus : DDS_TEST_TYPE := DEFAULT_DDS_TEST; + shared variable reference : RTPS_TEST_TYPE := DEFAULT_RTPS_TEST; + signal inst_id, kind_id, sn_id, ts_id, data_id, ret_id : AlertLogIDType; + + -- *FUNCTION DECLARATION* + function extract_key_hash (payload : TEST_PACKET_TYPE) return INSTANCE_HANDLE_TYPE is + variable ret : INSTANCE_HANDLE_TYPE := HANDLE_NIL; + begin + for i in 0 to 3 loop + ret(i) := not payload.data(i); + end loop; + + return ret; + end function; + + function gen_sn(input : natural) return SEQUENCENUMBER_TYPE is + variable ret : SEQUENCENUMBER_TYPE; + begin + ret(0) := (others => '0'); + ret(1) := unsigned(int(input, WORD_WIDTH)); + return ret; + end function; + +begin + + -- Unit Under Test + uut : entity work.dds_writer(arch) + generic map( + HISTORY_QOS => KEEP_ALL_HISTORY_QOS, + DEADLINE_QOS => DURATION_INFINITE, + LIFESPAN_QOS => gen_duration(1,0), + LEASE_DURATION => DURATION_INFINITE, + WITH_KEY => TRUE, + MAX_SAMPLES => std_logic_vector(to_unsigned(4,CDR_LONG_WIDTH)), + MAX_INSTANCES => std_logic_vector(to_unsigned(3,CDR_LONG_WIDTH)), + MAX_SAMPLES_PER_INSTANCE => std_logic_vector(to_unsigned(2,CDR_LONG_WIDTH)), + PAYLOAD_FRAME_SIZE => 11 + ) + port map ( + clk => clk, + reset => reset, + time => check_time, + start_rtps => start_rtps, + opcode_rtps => opcode_rtps, + ack_rtps => ack_rtps, + done_rtps => done_rtps, + ret_rtps => ret_rtps, + seq_nr_rtps => seq_nr_rtps, + get_data_rtps => get_data_rtps, + data_out_rtps => data_out_rtps, + valid_out_rtps => valid_out_rtps, + ready_out_rtps => ready_out_rtps, + last_word_out_rtps => last_word_out_rtps, + liveliness_assertion => liveliness_assertion, + data_available => data_available, + cc_instance_handle => cc_instance_handle, + cc_kind => cc_kind, + cc_source_timestamp => cc_source_timestamp, + cc_seq_nr => cc_seq_nr, + start_kh => start_kh, + opcode_kh => opcode_kh, + ack_kh => ack_kh, + data_in_kh => data_in_kh, + valid_in_kh => valid_in_kh, + ready_in_kh => ready_in_kh, + last_word_in_kh => last_word_in_kh, + data_out_kh => data_out_kh, + valid_out_kh => valid_out_kh, + ready_out_kh => ready_out_kh, + last_word_out_kh => last_word_out_kh, + abort_kh => abort_kh, + start_dds => start_dds, + ack_dds => ack_dds, + opcode_dds => opcode_dds, + instance_handle_dds => instance_handle_dds, + source_ts_dds => source_ts_dds, + max_wait_dds => max_wait_dds, + done_dds => done_dds, + return_code_dds => return_code_dds, + ready_in_dds => ready_in_dds, + valid_in_dds => valid_in_dds, + data_in_dds => data_in_dds, + last_word_in_dds => last_word_in_dds, + ready_out_dds => ready_out_dds, + valid_out_dds => valid_out_dds, + data_out_dds => data_out_dds, + last_word_out_dds => last_word_out_dds, + status => status + ); + + stimulus_prc : process + variable RV : RandomPType; + variable kh1, kh2, kh3, kh4 : INSTANCE_HANDLE_TYPE := HANDLE_NIL; + variable cc1, cc2, cc3, cc4, cc : CACHE_CHANGE_TYPE := DEFAULT_CACHE_CHANGE; + + impure function gen_payload(key_hash : INSTANCE_HANDLE_TYPE; len : natural) return TEST_PACKET_TYPE is + variable ret : TEST_PACKET_TYPE := EMPTY_TEST_PACKET; + begin + assert (len >= 4) report "Payload length has to be at least 16 Bytes long" severity FAILURE; + + for i in 0 to len-1 loop + if (i < 4) then + -- NOTE: Beginning of payload is negated key to allow deterministic Key Hash generation from the kh_prc + ret.data(ret.length) := not key_hash(i); + else + ret.data(ret.length) := RV.RandSlv(WORD_WIDTH); + end if; + ret.length := ret.length + 1; + end loop; + ret.last(ret.length-1) := '1'; + + return ret; + end function; + + impure function gen_key_hash return KEY_HASH_TYPE is + variable ret : KEY_HASH_TYPE := (others => (others => '0')); + begin + for i in 0 to KEY_HASH_TYPE'length-1 loop + ret(i) := RV.RandSlv(WORD_WIDTH); + end loop; + return ret; + end function; + + procedure start_stim is + begin + stim_start <= '1'; + wait until rising_edge(clk); + stim_start <= '0'; + wait until rising_edge(clk); + end procedure; + + procedure start_ref is + begin + ref_start <= '1'; + wait until rising_edge(clk); + ref_start <= '0'; + wait until rising_edge(clk); + end procedure; + + procedure wait_on_stim is + begin + if (stim_done /= '1') then + wait until stim_done = '1'; + end if; + end procedure; + + procedure wait_on_ref is + begin + if (ref_done /= '1') then + wait until ref_done = '1'; + end if; + end procedure; + + procedure wait_on_completion is + begin + if (ref_done /= '1' or stim_done /= '1') then + wait until ref_done = '1' and stim_done = '1'; + end if; + end procedure; + + begin + + SetAlertLogName("dds_writer - (KEEP ALL, Finite Lifespan, Keyed) - Level 0 - General"); + SetAlertEnable(FAILURE, TRUE); + SetAlertEnable(ERROR, TRUE); + SetAlertEnable(WARNING, TRUE); + SetLogEnable(DEBUG, FALSE); + SetLogEnable(PASSED, FALSE); + SetLogEnable(INFO, TRUE); + RV.InitSeed(RV'instance_name); + inst_id <= GetAlertLogID("Instance", ALERTLOG_BASE_ID); + kind_id <= GetAlertLogID("Cache Change Kind", ALERTLOG_BASE_ID); + sn_id <= GetAlertLogID("SequenceNumber", ALERTLOG_BASE_ID); + ts_id <= GetAlertLogID("TimeStamp", ALERTLOG_BASE_ID); + data_id <= GetAlertLogID("Data Out", ALERTLOG_BASE_ID); + ret_id <= GetAlertLogID("Return Code", ALERTLOG_BASE_ID); + + -- Key Hashes + kh1 := gen_key_hash; + kh2 := gen_key_hash; + kh3 := gen_key_hash; + kh4 := gen_key_hash; + + + + Log("Initiating Test", INFO); + reset <= '1'; + wait until rising_edge(clk); + wait until rising_edge(clk); + reset <= '0'; + -- Stored CC: 0, 0, 0, 0 + + -- TEST: GET_MIN_SN/GET_MAX_SN ON EMPTY + + Log("RTPS Operation GET_MIN_SN (Expected SEQUENCENUMBER_UNKNOWN)", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_MIN_SN; + reference.cc.seq_nr := SEQUENCENUMBER_UNKNOWN; + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_MAX_SN (Expected SEQUENCENUMBER_UNKNOWN)", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_MAX_SN; + reference.cc.seq_nr := SEQUENCENUMBER_UNKNOWN; + start_ref; + wait_on_ref; + + -- TEST: WRITE ALIGNED PAYLOAD + -- TEST: NORMAL WRITE + -- TEST: ADD SAMPLE WITH KEY_HASH [UNKNOWN INSTANCE] + + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh1; + cc.payload := gen_payload(kh1,10); + cc.seq_nr := gen_sn(1); + cc.src_timestamp := gen_duration(1,0); + + Log("DDS Operation WRITE [TS 1s, Instance 1] (REJECTED: Instance not Registered)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_BAD_PARAMETER; + start_stim; + wait_on_stim; + + -- TEST: ADD SAMPLE WITH HANDLE_NIL [UNKNOWN INSTANCE] + + Log("DDS Operation WRITE [TS 1s, Instance 1, HANDLE_NIL] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.cc.instance:= HANDLE_NIL; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc1 := cc; + -- Stored CC: I1S1, 0, 0, 0 + + -- TEST: GET_MIN_SN/GET_MAX_SN ON 1 SAMPLE + + Log("RTPS Operation GET_MIN_SN (Expected SN 1)", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_MIN_SN; + reference.cc.seq_nr := gen_sn(1); + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_MAX_SN (Expected SN 1)", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_MAX_SN; + reference.cc.seq_nr := gen_sn(1); + start_ref; + wait_on_ref; + + -- TEST: WRITE UNALIGNED PAYLOAD [>1 SLOT] + + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh2; + cc.payload := gen_payload(kh2,12); + cc.seq_nr := gen_sn(2); + cc.src_timestamp := gen_duration(2,0); + + Log("DDS Operation WRITE [TS 2s, Instance 2, Unaligned Payload (2 Slots)] (REJECTED: Instance not Registered)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_BAD_PARAMETER; + start_stim; + wait_on_stim; + + -- TEST: NORMAL REGISTER + + Log("DDS Operation REGISTER_INSTANCE 2 (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := REGISTER_INSTANCE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + + -- TEST: ADD SAMPLE WITH KEY_HASH [KNOWN INSTANCE] + + Log("DDS Operation WRITE [TS 2s, Instance 2, Unaligned Payload (2 Slots)] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc2 := cc; + -- Stored CC: I1S1, I2S2, 0, 0 + + -- TEST: ADD SAMPLE WITH HANDLE_NIL [KNOWN INSTANCE] + + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh1; + cc.payload := gen_payload(kh1,15); + cc.seq_nr := gen_sn(3); + cc.src_timestamp := gen_duration(3,0); + + Log("DDS Operation WRITE [TS 3s, Instance 1, Unaligned Payload (2 Slots)] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.cc.instance:= HANDLE_NIL; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc3 := cc; + -- Stored CC: I1S1, I2S2, I1S3, 0 + + -- TEST: GET_CACHE_CHANGE [UNKNOWN SN] + + Log("RTPS Operation GET_CACHE_CHANGE SN 4 (Invalid)", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_CACHE_CHANGE; + reference.cc.seq_nr := gen_sn(4); + reference.ret_code := INVALID; + start_ref; + wait_on_ref; + + -- TEST: GET_CACHE_CHANGE [KNOWN SN, ALIGNED PAYLOAD] + + Log("RTPS Operation GET_CACHE_CHANGE SN 1", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_CACHE_CHANGE; + reference.cc := cc1; + start_ref; + wait_on_ref; + + -- TEST: GET_CACHE_CHANGE [KNOWN SN, UNALIGNED PAYLOAD, >1 SLOT] + + Log("RTPS Operation GET_CACHE_CHANGE SN 2", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_CACHE_CHANGE; + reference.cc := cc2; + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_CACHE_CHANGE SN 3", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_CACHE_CHANGE; + reference.cc := cc3; + start_ref; + wait_on_ref; + + -- TEST: WRITE UNALIGNED PAYLOAD [<1 SLOT] + + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh3; + cc.payload := gen_payload(kh3,8); + cc.seq_nr := gen_sn(4); + cc.src_timestamp := gen_duration(4,0); + + -- TEST: WRITE ON PAYLOAD MEMORY FULL [WITHOUT ACKed SAMPLES] + + Log("DDS Operation WRITE [TS 4s, Instance 3, HANDLE_NIL, Unaligned Payload (1 Slot)] (REJECTED: Payload Memory Full)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.cc.instance:= HANDLE_NIL; + stimulus.ret_code := RETCODE_OUT_OF_RESOURCES; + start_stim; + wait_on_stim; + -- Stored CC: I1S1, I2S2, I1S3, 0 + + -- TEST: REMOVE_CACHE_CHANGE [UNKNOWN SN] + + Log("RTPS Operation REMOVE_CACHE_CHANGE SN 5 (Invalid)", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := REMOVE_CACHE_CHANGE; + reference.cc.seq_nr := gen_sn(5); + reference.ret_code := INVALID; + start_ref; + wait_on_ref; + + -- TEST: REMOVE_CACHE_CHANGE [KNOWN SN] + + Log("RTPS Operation REMOVE_CACHE_CHANGE SN 2", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := REMOVE_CACHE_CHANGE; + reference.cc := cc2; + start_ref; + wait_on_ref; + -- Stored CC: I1S1, 0, I1S3, 0 + + Log("DDS Operation WRITE [TS 4s, Instance 3, HANDLE_NIL, Unaligned Payload (1 Slot)] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.cc.instance:= HANDLE_NIL; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc2 := cc; + -- Stored CC: I1S1, I3S4, I1S3, 0 + + -- TEST: GET_CACHE_CHANGE [KNOWN SN, UNALIGNED PAYLOAD, <1 SLOT] + + Log("RTPS Operation GET_CACHE_CHANGE SN 4", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_CACHE_CHANGE; + reference.cc := cc2; + start_ref; + wait_on_ref; + + -- TEST: REGISTER INSTANCE [KNOWN INSTANCE] + + Log("DDS Operation REGISTER_INSTANCE 3 (No Change)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := REGISTER_INSTANCE; + stimulus.cc := cc2; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + + -- TEST: NORMAL DISPOSE + + cc.serialized_key := TRUE; + cc.kind := NOT_ALIVE_DISPOSED; + cc.instance := kh1; + cc.payload := gen_payload(kh1,5); + cc.seq_nr := gen_sn(5); + cc.src_timestamp := gen_duration(5,0); + + -- TEST: ADD SAMPLE ON MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE, WITHOUT ACKed SAMPLES] + + Log("DDS Operation DISPOSE [TS 5s, Instance 1] (REJECTED: MAX_SAMPLES_PER_INSTANCE Exceeded)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := DISPOSE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OUT_OF_RESOURCES; + start_stim; + wait_on_stim; + + -- TEST: NORMAL ACK_CACHE_CHANGE + + Log("RTPS Operation ACK_CACHE_CHANGE SN 4", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := ACK_CACHE_CHANGE; + reference.cc := cc2; + start_ref; + wait_on_ref; + + -- TEST: ADD SAMPLE ON MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE, WITH ACKed SAMPLES, WITHOUT ACKed INSTANCE SAMPLES] + + Log("DDS Operation DISPOSE [TS 5s, Instance 1] (REJECTED: MAX_SAMPLES_PER_INSTANCE Exceeded)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := DISPOSE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OUT_OF_RESOURCES; + start_stim; + wait_on_stim; + + Log("RTPS Operation ACK_CACHE_CHANGE SN 1", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := ACK_CACHE_CHANGE; + reference.cc := cc1; + start_ref; + wait_on_ref; + + -- TEST: ADD SAMPLE ON MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE, WITH ACKed INSTANCE SAMPLE] + + Log("DDS Operation DISPOSE [TS 5s, Instance 1] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := DISPOSE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc1 := cc; + -- Stored CC: I1S5, I3S4, I1S3, 0 + + -- VALIDATE STATE + -- TEST: GET_MIN_SN/GET_MAX_SN ON >1 SAMPLE + + Log("RTPS Operation GET_MIN_SN (Expected SN 3)", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_MIN_SN; + reference.cc.seq_nr := gen_sn(3); + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_MAX_SN (Expected SN 5)", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_MAX_SN; + reference.cc.seq_nr := gen_sn(5); + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_CACHE_CHANGE SN 5", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_CACHE_CHANGE; + reference.cc := cc1; + start_ref; + wait_on_ref; + + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh4; + cc.payload := gen_payload(kh4,10); + cc.seq_nr := gen_sn(6); + cc.src_timestamp := gen_duration(6,0); + + -- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKNOWN INSTANCE, WITHOUT STALE INSTANCES] + + Log("DDS Operation WRITE [TS 6s, Instance 4, HANDLE_NIL, Aligned Payload] (REJECTED: MAX_INSTANCES exceeded)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.cc.instance:= HANDLE_NIL; + stimulus.ret_code := RETCODE_OUT_OF_RESOURCES; + start_stim; + wait_on_stim; + + Log("RTPS Operation ACK_CACHE_CHANGE SN 3", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := ACK_CACHE_CHANGE; + reference.cc := cc3; + start_ref; + wait_on_ref; + + -- TEST: ACK_CACHE_CHANGE [ALREADY ACKed SN] + + Log("RTPS Operation ACK_CACHE_CHANGE SN 4", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := ACK_CACHE_CHANGE; + reference.cc := cc2; + start_ref; + wait_on_ref; + + Log("RTPS Operation ACK_CACHE_CHANGE SN 5", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := ACK_CACHE_CHANGE; + reference.cc := cc1; + start_ref; + wait_on_ref; + + -- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKNOWN INSTANCE, WITH FULLY ACKed INSTANCE, WITHOUT STALE INSTANCE] + + Log("DDS Operation WRITE [TS 6s, Instance 4, HANDLE_NIL, Aligned Payload] (REJECTED: MAX_INSTANCES exceeded)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.cc.instance:= HANDLE_NIL; + stimulus.ret_code := RETCODE_OUT_OF_RESOURCES; + start_stim; + wait_on_stim; + + -- TEST: NORMAL UNREGISTER + + cc.serialized_key := TRUE; + cc.kind := NOT_ALIVE_UNREGISTERED; + cc.instance := kh1; + cc.payload := gen_payload(kh1,5); + cc.seq_nr := gen_sn(6); + cc.src_timestamp := gen_duration(6,0); + + -- TEST: UNREGISTER ON DISPOSED INSTANCE + + Log("DDS Operation UNREGISTER_INSTANCE [TS 6s, Instance 1] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := UNREGISTER_INSTANCE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc3 := cc; + -- Stored CC: I1S5, I3S4, I1S6, 0 + + -- VALIDATE STATE + + Log("RTPS Operation GET_MIN_SN (Expected SN 4)", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_MIN_SN; + reference.cc.seq_nr := gen_sn(4); + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_MAX_SN (Expected SN 6)", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_MAX_SN; + reference.cc.seq_nr := gen_sn(6); + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_CACHE_CHANGE SN 6", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_CACHE_CHANGE; + reference.cc := cc3; + start_ref; + wait_on_ref; + + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh4; + cc.payload := gen_payload(kh4,10); + cc.seq_nr := gen_sn(7); + cc.src_timestamp := gen_duration(7,0); + + Log("DDS Operation WRITE [TS 7s, Instance 4, HANDLE_NIL, Aligned Payload] (REJECTED: MAX_INSTANCES exceeded)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.cc.instance:= HANDLE_NIL; + stimulus.ret_code := RETCODE_OUT_OF_RESOURCES; + start_stim; + wait_on_stim; + + Log("RTPS Operation ACK_CACHE_CHANGE SN 6", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := ACK_CACHE_CHANGE; + reference.cc := cc3; + start_ref; + wait_on_ref; + + -- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKNOWN INSTANCE, WITH STALE INSTANCE] + -- TEST: REMOVE STALE INSTANCE WITH >1 SAMPLES + + Log("DDS Operation WRITE [TS 7s, Instance 4, HANDLE_NIL, Aligned Payload] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.cc.instance:= HANDLE_NIL; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc1 := cc; + -- Stored CC: I4S7, I3S4, 0, 0 + + Log("RTPS Operation GET_CACHE_CHANGE SN 5 (Invalid)", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_CACHE_CHANGE; + reference.cc.seq_nr := gen_sn(5); + reference.ret_code := INVALID; + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_CACHE_CHANGE SN 6 (Invalid)", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_CACHE_CHANGE; + reference.cc.seq_nr := gen_sn(6); + reference.ret_code := INVALID; + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_CACHE_CHANGE SN 7", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_CACHE_CHANGE; + reference.cc := cc1; + start_ref; + wait_on_ref; + + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh2; + cc.payload := gen_payload(kh2,15); + cc.seq_nr := gen_sn(8); + cc.src_timestamp := gen_duration(8,0); + + Log("DDS Operation WRITE [TS 8s, Instance 2, Unaligned Payload (2 Slot)] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc3 := cc; + -- Stored CC: I4S7, I3S4, I2S8, 0 + + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh1; + cc.payload := gen_payload(kh1,10); + cc.seq_nr := gen_sn(9); + cc.src_timestamp := gen_duration(9,0); + + Log("DDS Operation WRITE [TS 9s, Instance 1, Aligned Payload] (REJECTED: Instance not Registered)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_BAD_PARAMETER; + start_stim; + wait_on_stim; + + -- TEST: REGISTER INSTANCE ON MAX_INSTANCES [UNKNOWN INSTANCE, WITHOUT STALE INSTANCE] + + Log("DDS Operation REGISTER_INSTANCE 1 (REJECTED: MAX_INSTANCES exceeded)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := REGISTER_INSTANCE; + stimulus.cc := cc; + stimulus.cc.instance:= HANDLE_NIL; + start_stim; + wait_on_stim; + + cc.serialized_key := FALSE; + cc.kind := NOT_ALIVE_UNREGISTERED; + cc.instance := kh3; + cc.payload := gen_payload(kh3,5); + cc.seq_nr := gen_sn(9); + cc.src_timestamp := gen_duration(9,0); + + Log("DDS Operation UNREGISTER_INSTANCE [TS 9s, Instance 3] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := UNREGISTER_INSTANCE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc4 := cc; + -- Stored CC: I4S7, I3S4, I2S8, I3S9 + + -- VALIDATE STATE + + Log("RTPS Operation GET_MIN_SN (Expected SN 4)", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_MIN_SN; + reference.cc.seq_nr := gen_sn(4); + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_MAX_SN (Expected SN 9)", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_MAX_SN; + reference.cc.seq_nr := gen_sn(9); + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_CACHE_CHANGE SN 8", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_CACHE_CHANGE; + reference.cc := cc3; + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_CACHE_CHANGE SN 9", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_CACHE_CHANGE; + reference.cc := cc4; + start_ref; + wait_on_ref; + + Log("RTPS Operation ACK_CACHE_CHANGE SN 9", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := ACK_CACHE_CHANGE; + reference.cc := cc4; + start_ref; + wait_on_ref; + + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh1; + cc.payload := gen_payload(kh1,10); + cc.seq_nr := gen_sn(10); + cc.src_timestamp := gen_duration(10,0); + + -- TEST: REGISTER INSTANCE ON MAX_INSTANCES [UNKNOWN INSTANCE, WITH STALE INSTANCE] + + Log("DDS Operation REGISTER_INSTANCE 1 (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := REGISTER_INSTANCE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + + Log("DDS Operation WRITE [TS 10s, Instance 1, Aligned Payload] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc2 := cc; + -- Stored CC: I4S7, I1S10, I2S8, 0 + + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh4; + cc.payload := gen_payload(kh4,10); + cc.seq_nr := gen_sn(11); + cc.src_timestamp := gen_duration(11,0); + + Log("DDS Operation WRITE [TS 11s, Instance 1, Aligned Payload] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc4 := cc; + -- Stored CC: I4S7, I1S10, I2S8, I4S11 + + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh2; + cc.payload := gen_payload(kh2,10); + cc.seq_nr := gen_sn(12); + cc.src_timestamp := gen_duration(12,0); + + Log("DDS Operation WRITE [TS 12s, Instance 2, Aligned Payload] (REJECTED: Payload Memory Full)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OUT_OF_RESOURCES; + start_stim; + wait_on_stim; + + Log("RTPS Operation ACK_CACHE_CHANGE SN 8", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := ACK_CACHE_CHANGE; + reference.cc := cc3; + start_ref; + wait_on_ref; + + -- TEST: WRITE ON PAYLOAD MEMORY FULL [WITH ACKed SAMPLES] + + Log("DDS Operation WRITE [TS 12s, Instance 2, Aligned Payload] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc3 := cc; + -- Stored CC: I4S7, I1S10, I2S12, I4S11 + + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh4; + cc.payload := gen_payload(kh4,10); + cc.seq_nr := gen_sn(13); + cc.src_timestamp := gen_duration(13,0); + + -- TEST: ADD SAMPLE ON MAX_SAMPLES [KNOWN INSTANCE,WITHOUT ACKed SAMPLES] + + Log("DDS Operation WRITE [TS 13s, Instance 4, Aligned Payload] (REJECTED: MAX_SAMPLES exceeded)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OUT_OF_RESOURCES; + start_stim; + wait_on_stim; + + Log("RTPS Operation ACK_CACHE_CHANGE SN 7", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := ACK_CACHE_CHANGE; + reference.cc := cc1; + start_ref; + wait_on_ref; + + -- TEST: ADD SAMPLE ON MAX_SAMPLES [KNOWN INSTANCE,WITH ACKed SAMPLES] + + Log("DDS Operation WRITE [TS 13s, Instance 4, Aligned Payload] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc1 := cc; + -- Stored CC: I4S13, I1S10, I2S12, I4S11 + + -- VALIDATE STATE + + Log("RTPS Operation GET_MIN_SN (Expected SN 4)", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_MIN_SN; + reference.cc.seq_nr := gen_sn(10); + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_MAX_SN (Expected SN 9)", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_MAX_SN; + reference.cc.seq_nr := gen_sn(13); + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_CACHE_CHANGE SN 10", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_CACHE_CHANGE; + reference.cc := cc2; + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_CACHE_CHANGE SN 11", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_CACHE_CHANGE; + reference.cc := cc4; + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_CACHE_CHANGE SN 12", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_CACHE_CHANGE; + reference.cc := cc3; + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_CACHE_CHANGE SN 13", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_CACHE_CHANGE; + reference.cc := cc1; + start_ref; + wait_on_ref; + + Log("RTPS Operation ACK_CACHE_CHANGE SN 12", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := ACK_CACHE_CHANGE; + reference.cc := cc3; + start_ref; + wait_on_ref; + + cc.serialized_key := FALSE; + cc.kind := NOT_ALIVE_UNREGISTERED; + cc.instance := kh2; + cc.payload := gen_payload(kh2,5); + cc.seq_nr := gen_sn(14); + cc.src_timestamp := gen_duration(14,0); + + Log("DDS Operation UNREGISTER_INSTANCE [TS 14s, Instance 2] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := UNREGISTER_INSTANCE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc3 := cc; + -- Stored CC: I4S13, I1S10, I2S14, I4S11 + + Log("RTPS Operation ACK_CACHE_CHANGE SN 11", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := ACK_CACHE_CHANGE; + reference.cc := cc4; + start_ref; + wait_on_ref; + + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh4; + cc.payload := gen_payload(kh4,20); + cc.seq_nr := gen_sn(15); + cc.src_timestamp := gen_duration(15,0); + + -- TEST: ADD SAMPLE BIGGER THAN AVAILABLE MEMORY SPACE [WITH ACKed SAMPLES] + + Log("DDS Operation WRITE [TS 15s, Instance 4, Aligned Payload (2 Slots)] (REJECTED: Payload Memory Full)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OUT_OF_RESOURCES; + start_stim; + wait_on_stim; + + Log("RTPS Operation REMOVE_CACHE_CHANGE SN 11", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := REMOVE_CACHE_CHANGE; + reference.cc := cc4; + start_ref; + wait_on_ref; + -- Stored CC: I4S13, I1S10, I2S14, 0 + + Log("DDS Operation WRITE [TS 15s, Instance 4, Aligned Payload (2 Slots)] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc4 := cc; + -- Stored CC: I4S13, I1S10, I2S14, I4S15 + + -- TEST: UNREGISTER INSTANCE ON PAYLOAD MEMORY FULL [WITHOUT ACKed SAMPLES] + + cc.serialized_key := FALSE; + cc.kind := NOT_ALIVE_UNREGISTERED; + cc.instance := kh1; + cc.payload := gen_payload(kh1,5); + cc.seq_nr := gen_sn(16); + cc.src_timestamp := gen_duration(16,0); + + Log("DDS Operation UNREGISTER_INSTANCE [TS 16s, Instance 1] (REJECTED: Payload memory Full, MAX_SAMPLES exceeded)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := UNREGISTER_INSTANCE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OUT_OF_RESOURCES; + start_stim; + wait_on_stim; + + Log("RTPS Operation ACK_CACHE_CHANGE SN 10", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := ACK_CACHE_CHANGE; + reference.cc := cc2; + start_ref; + wait_on_ref; + + -- TEST: UNREGISTER INSTANCE ON PAYLOAD MEMORY FULL [WITH ACKed SAMPLES] + + Log("DDS Operation UNREGISTER_INSTANCE [TS 16s, Instance 1] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := UNREGISTER_INSTANCE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc2 := cc; + -- Stored CC: I4S13, I1S16, I2S14, I4S15 + + + cc.serialized_key := FALSE; + cc.kind := NOT_ALIVE_DISPOSED; + cc.instance := kh3; + cc.payload := gen_payload(kh3,5); + cc.seq_nr := gen_sn(17); + cc.src_timestamp := gen_duration(17,0); + + -- TEST: DISPOSE ON PAYLOAD MEMORY FULL [WITHOUT ACKed SAMPLES] + + Log("DDS Operation DISPOSE [TS 17s, Instance 3] (REJECTED: Payload memory Full, MAX_SAMPLES exceeded)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := DISPOSE; + stimulus.cc := cc; + stimulus.cc.instance:= HANDLE_NIL; + stimulus.ret_code := RETCODE_OUT_OF_RESOURCES; + start_stim; + wait_on_stim; + + Log("RTPS Operation ACK_CACHE_CHANGE SN 13", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := ACK_CACHE_CHANGE; + reference.cc := cc1; + start_ref; + wait_on_ref; + + Log("RTPS Operation ACK_CACHE_CHANGE SN 14", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := ACK_CACHE_CHANGE; + reference.cc := cc3; + start_ref; + wait_on_ref; + + -- TEST: DISPOSE ON PAYLOAD MEMORY FULL [WITH ACKed SAMPLES] + -- TEST: ADD SAMPLE ON PAYLOAD FULL & MAX_INSTANCES [UNKNOWN INSTANCE,WITH ACKed SAMPLES,WITH STALE INSTANCE (>= 1 SAMPLE)] (Induce Double Remove) + -- TEST: REMOVE STALE INSTANCE WITH 1 SAMPLES + + Log("DDS Operation DISPOSE [TS 17s, Instance 3] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := DISPOSE; + stimulus.cc := cc; + stimulus.cc.instance:= HANDLE_NIL; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc1 := cc; + -- Stored CC: I3S17, I1S16, 0, I4S15 + + -- VALIDATE STATE + + Log("RTPS Operation GET_MIN_SN (Expected SN 15)", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_MIN_SN; + reference.cc.seq_nr := gen_sn(15); + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_MAX_SN (Expected SN 17)", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_MAX_SN; + reference.cc.seq_nr := gen_sn(17); + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_CACHE_CHANGE SN 15", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_CACHE_CHANGE; + reference.cc := cc4; + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_CACHE_CHANGE SN 16", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_CACHE_CHANGE; + reference.cc := cc2; + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_CACHE_CHANGE SN 17", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_CACHE_CHANGE; + reference.cc := cc1; + start_ref; + wait_on_ref; + + Log("RTPS Operation REMOVE_CACHE_CHANGE SN 15", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := REMOVE_CACHE_CHANGE; + reference.cc := cc4; + start_ref; + wait_on_ref; + -- Stored CC: I3S17, I1S16, 0, 0 + + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh3; + cc.payload := gen_payload(kh3,10); + cc.seq_nr := gen_sn(18); + cc.src_timestamp := gen_duration(18,0); + + -- TEST: WRITE ON DISPOSED INSTANCE + + Log("DDS Operation WRITE [TS 18s, Instance 3, Aligned Payload] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc3 := cc; + -- Stored CC: I3S17, I1S16, I3S18, 0 + + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh4; + cc.payload := gen_payload(kh4,10); + cc.seq_nr := gen_sn(19); + cc.src_timestamp := gen_duration(19,0); + + Log("DDS Operation WRITE [TS 19s, Instance 4, Aligned Payload] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc4 := cc; + -- Stored CC: I3S17, I1S16, I3S18, I4S19 + + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh2; + cc.payload := gen_payload(kh2,10); + cc.seq_nr := gen_sn(20); + cc.src_timestamp := gen_duration(20,0); + + -- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE,WITHOUT STALE INSTANCES,WITHOUT ACKed SAMPLES] + + Log("DDS Operation WRITE [TS 20s, Instance 2, Aligned Payload] (REJECTED: MAX_SAMPLES exceeded, MAX_INSTANCES exceeded)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.cc.instance:= HANDLE_NIL; + stimulus.ret_code := RETCODE_OUT_OF_RESOURCES; + start_stim; + wait_on_stim; + + Log("RTPS Operation ACK_CACHE_CHANGE SN 16", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := ACK_CACHE_CHANGE; + reference.cc := cc2; + start_ref; + wait_on_ref; + + -- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE,WITH STALE INSTANCE (>0 SAMPLES)] + + Log("DDS Operation WRITE [TS 20s, Instance 2, Aligned Payload] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.cc.instance:= HANDLE_NIL; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc2 := cc; + -- Stored CC: I3S17, I2S20, I3S18, I4S19 + + Log("RTPS Operation ACK_CACHE_CHANGE SN 17", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := ACK_CACHE_CHANGE; + reference.cc := cc1; + start_ref; + wait_on_ref; + + cc.serialized_key := FALSE; + cc.kind := NOT_ALIVE_UNREGISTERED; + cc.instance := kh4; + cc.payload := gen_payload(kh4,5); + cc.seq_nr := gen_sn(21); + cc.src_timestamp := gen_duration(21,0); + + Log("DDS Operation UNREGISTER_INSTANCE [TS 21s, Instance 4] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := UNREGISTER_INSTANCE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc1 := cc; + -- Stored CC: I4S21, I2S20, I3S18, I4S19 + + Log("RTPS Operation ACK_CACHE_CHANGE SN 19", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := ACK_CACHE_CHANGE; + reference.cc := cc4; + start_ref; + wait_on_ref; + + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh1; + cc.payload := gen_payload(kh1,10); + cc.seq_nr := gen_sn(22); + cc.src_timestamp := gen_duration(22,0); + + -- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE,WITHOUT STALE INSTANCE, WITH ACKed SAMPLE] + + Log("DDS Operation WRITE [TS 22s, Instance 1, Aligned Payload] (REJECTED: MAX_SAMPLES exceeded, MAX_INSTANCES exceeded)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.cc.instance:= HANDLE_NIL; + stimulus.ret_code := RETCODE_OUT_OF_RESOURCES; + start_stim; + wait_on_stim; + + Log("RTPS Operation REMOVE_CACHE_CHANGE SN 19", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := REMOVE_CACHE_CHANGE; + reference.cc := cc4; + start_ref; + wait_on_ref; + -- Stored CC: I4S21, I2S20, I3S18, 0 + + Log("RTPS Operation REMOVE_CACHE_CHANGE SN 21", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := REMOVE_CACHE_CHANGE; + reference.cc := cc1; + start_ref; + wait_on_ref; + -- Stored CC: 0, I2S20, I3S18, 0 + + cc.serialized_key := FALSE; + cc.kind := NOT_ALIVE_UNREGISTERED; + cc.instance := kh2; + cc.payload := gen_payload(kh2,5); + cc.seq_nr := gen_sn(22); + cc.src_timestamp := gen_duration(22,0); + + Log("DDS Operation UNREGISTER_INSTANCE [TS 22s, Instance 2] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := UNREGISTER_INSTANCE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc1 := cc; + -- Stored CC: I2S22, I2S20, I3S18, 0 + + cc.serialized_key := FALSE; + cc.kind := NOT_ALIVE_UNREGISTERED; + cc.instance := kh3; + cc.payload := gen_payload(kh3,5); + cc.seq_nr := gen_sn(23); + cc.src_timestamp := gen_duration(23,0); + + Log("DDS Operation UNREGISTER_INSTANCE [TS 23s, Instance 3] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := UNREGISTER_INSTANCE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc4 := cc; + -- Stored CC: I2S22, I2S20, I3S18, I3S23 + + -- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE,WITH STALE INSTANCE, WITHOUT ACKed SAMPLE] + + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh1; + cc.payload := gen_payload(kh1,10); + cc.seq_nr := gen_sn(24); + cc.src_timestamp := gen_duration(24,0); + + Log("DDS Operation WRITE [TS 24s, Instance 1, Aligned Payload] (REJECTED: MAX_SAMPLES exceeded, MAX_INSTANCES exceeded)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.cc.instance:= HANDLE_NIL; + stimulus.ret_code := RETCODE_OUT_OF_RESOURCES; + start_stim; + wait_on_stim; + + Log("RTPS Operation ACK_CACHE_CHANGE SN 20", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := ACK_CACHE_CHANGE; + reference.cc := cc2; + start_ref; + wait_on_ref; + + -- TEST: REMOVE STALE INSTANCE WITH 0 SAMPLES + -- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE,WITH STALE INSTANCE, WITH ACKed SAMPLE] + + Log("DDS Operation WRITE [TS 24s, Instance 1, Aligned Payload] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.cc.instance:= HANDLE_NIL; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc2 := cc; + -- Stored CC: I2S22, I1S24, I3S18, I3S23 + + Log("RTPS Operation ACK_CACHE_CHANGE SN 22", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := ACK_CACHE_CHANGE; + reference.cc := cc1; + start_ref; + wait_on_ref; + + -- TEST: NORMAL NACK_CACHE_CHANGE + + Log("RTPS Operation NACK_CACHE_CHANGE SN 22", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := NACK_CACHE_CHANGE; + reference.cc := cc1; + start_ref; + wait_on_ref; + + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh4; + cc.payload := gen_payload(kh4,10); + cc.seq_nr := gen_sn(25); + cc.src_timestamp := gen_duration(25,0); + + Log("DDS Operation REGISTER_INSTANCE 4 (REJECTED: MAX_INSTANCES exceeded)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := REGISTER_INSTANCE; + stimulus.cc := cc; + stimulus.cc.instance:= HANDLE_NIL; + start_stim; + wait_on_stim; + + Log("RTPS Operation ACK_CACHE_CHANGE SN 22", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := ACK_CACHE_CHANGE; + reference.cc := cc1; + start_ref; + wait_on_ref; + + -- TEST: REGISTER ON UNREGISTERED INSTANCE + + Log("DDS Operation REGISTER_INSTANCE 2 (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := REGISTER_INSTANCE; + stimulus.cc := cc1; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + + Log("DDS Operation REGISTER_INSTANCE 4 (REJECTED: MAX_INSTANCES exceeded)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := REGISTER_INSTANCE; + stimulus.cc := cc; + stimulus.cc.instance:= HANDLE_NIL; + start_stim; + wait_on_stim; + + Log("RTPS Operation ACK_CACHE_CHANGE SN 18", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := ACK_CACHE_CHANGE; + reference.cc := cc3; + start_ref; + wait_on_ref; + + Log("RTPS Operation ACK_CACHE_CHANGE SN 23", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := ACK_CACHE_CHANGE; + reference.cc := cc4; + start_ref; + wait_on_ref; + + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh3; + cc.payload := gen_payload(kh3,10); + cc.seq_nr := gen_sn(25); + cc.src_timestamp := gen_duration(25,0); + + -- TEST: WRITE ON UNREGISTERED INSTANCE + + Log("DDS Operation WRITE [TS 25s, Instance 3, Aligned Payload] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.cc.instance:= HANDLE_NIL; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc3 := cc; + -- Stored CC: I2S22, I1S24, I3S25, I3S23 + + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh4; + cc.payload := gen_payload(kh4,10); + cc.seq_nr := gen_sn(26); + cc.src_timestamp := gen_duration(26,0); + + Log("DDS Operation REGISTER_INSTANCE 4 (REJECTED: MAX_INSTANCES exceeded)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := REGISTER_INSTANCE; + stimulus.cc := cc; + stimulus.cc.instance:= HANDLE_NIL; + start_stim; + wait_on_stim; + + cc.serialized_key := FALSE; + cc.kind := NOT_ALIVE_UNREGISTERED; + cc.instance := kh4; + cc.payload := gen_payload(kh4,5); + cc.seq_nr := gen_sn(26); + cc.src_timestamp := gen_duration(26,0); + + -- TEST: UNREGISTER UNKNOWN INSTANCE + + Log("DDS Operation UNREGISTER_INSTANCE [TS 26s, HANDLE_NIL, Instance 4] (IGNORED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := UNREGISTER_INSTANCE; + stimulus.cc := cc; + stimulus.cc.instance:= HANDLE_NIL; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + + Log("RTPS Operation NACK_CACHE_CHANGE SN 22", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := NACK_CACHE_CHANGE; + reference.cc := cc1; + start_ref; + wait_on_ref; + + Log("RTPS Operation NACK_CACHE_CHANGE SN 23", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := NACK_CACHE_CHANGE; + reference.cc := cc4; + start_ref; + wait_on_ref; + + cc.serialized_key := TRUE; + cc.kind := NOT_ALIVE_UNREGISTERED; + cc.instance := kh3; + cc.payload := gen_payload(kh3,5); + cc.seq_nr := gen_sn(26); + cc.src_timestamp := gen_duration(26,0); + + -- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE,WITHOUT ACKed SAMPLES] + + Log("DDS Operation UNREGISTER_INSTANCE [TS 26s, Instance 3] (REJECTED: MAX_SAMPLES_PER_INSTANCE exceeded, MAX_SAMPLES exceeded)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := UNREGISTER_INSTANCE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OUT_OF_RESOURCES; + start_stim; + wait_on_stim; + + Log("RTPS Operation ACK_CACHE_CHANGE SN 22", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := ACK_CACHE_CHANGE; + reference.cc := cc1; + start_ref; + wait_on_ref; + + -- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE,WITH ACKed SAMPLES, WITHOUT ACKed INSTANCE SAMPLES] + + Log("DDS Operation UNREGISTER_INSTANCE [TS 26s, Instance 3] (REJECTED: MAX_SAMPLES_PER_INSTANCE exceeded, MAX_SAMPLES exceeded)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := UNREGISTER_INSTANCE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OUT_OF_RESOURCES; + start_stim; + wait_on_stim; + + Log("RTPS Operation ACK_CACHE_CHANGE SN 23", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := ACK_CACHE_CHANGE; + reference.cc := cc4; + start_ref; + wait_on_ref; + + -- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE,WITH ACKed INSTANCE SAMPLES] + + Log("DDS Operation UNREGISTER_INSTANCE [TS 26s, Instance 3] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := UNREGISTER_INSTANCE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc4 := cc; + -- Stored CC: I2S22, I1S24, I3S25, I3S26 + + Log("RTPS Operation ACK_CACHE_CHANGE SN 25", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := ACK_CACHE_CHANGE; + reference.cc := cc3; + start_ref; + wait_on_ref; + + cc.serialized_key := TRUE; + cc.kind := NOT_ALIVE_DISPOSED; + cc.instance := kh3; + cc.payload := gen_payload(kh3,5); + cc.seq_nr := gen_sn(27); + cc.src_timestamp := gen_duration(27,0); + + -- TEST: DISPOSE ON UNREGISTERED INSTANCE + + Log("DDS Operation DISPOSE [TS 27s, Instance 3] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := DISPOSE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc3 := cc; + -- Stored CC: I2S22, I1S24, I3S27, I3S26 + + Log("RTPS Operation ACK_CACHE_CHANGE SN 26", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := ACK_CACHE_CHANGE; + reference.cc := cc4; + start_ref; + wait_on_ref; + + Log("RTPS Operation ACK_CACHE_CHANGE SN 27", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := ACK_CACHE_CHANGE; + reference.cc := cc3; + start_ref; + wait_on_ref; + + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh4; + cc.payload := gen_payload(kh4,10); + cc.seq_nr := gen_sn(28); + cc.src_timestamp := gen_duration(28,0); + + Log("DDS Operation REGISTER_INSTANCE 4 (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := REGISTER_INSTANCE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + -- Stored CC: I2S22, I1S24, 0, 0 + + -- VALIDATE STATE + + Log("RTPS Operation GET_MIN_SN (Expected SN 22)", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_MIN_SN; + reference.cc.seq_nr := gen_sn(22); + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_MAX_SN (Expected SN 24)", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_MAX_SN; + reference.cc.seq_nr := gen_sn(24); + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_CACHE_CHANGE SN 22", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_CACHE_CHANGE; + reference.cc := cc1; + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_CACHE_CHANGE SN 24", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_CACHE_CHANGE; + reference.cc := cc2; + start_ref; + wait_on_ref; + + Log("RTPS Operation NACK_CACHE_CHANGE SN 22", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := NACK_CACHE_CHANGE; + reference.cc := cc1; + start_ref; + wait_on_ref; + + Log("RTPS Operation NACK_CACHE_CHANGE SN 24", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := NACK_CACHE_CHANGE; + reference.cc := cc2; + start_ref; + wait_on_ref; + + Log("DDS Operation WRITE [TS 28s, Instance 4, Aligned Payload] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc3 := cc; + -- Stored CC: I2S22, I1S24, I4S28, 0 + + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh2; + cc.payload := gen_payload(kh2,10); + cc.seq_nr := gen_sn(29); + cc.src_timestamp := gen_duration(29,0); + + Log("DDS Operation WRITE [TS 29s, Instance 2, Aligned Payload] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc4 := cc; + -- Stored CC: I2S22, I1S24, I4S28, I2S29 + + Log("RTPS Operation ACK_CACHE_CHANGE SN 24", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := ACK_CACHE_CHANGE; + reference.cc := cc2; + start_ref; + wait_on_ref; + + Log("RTPS Operation ACK_CACHE_CHANGE SN 28", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := ACK_CACHE_CHANGE; + reference.cc := cc3; + start_ref; + wait_on_ref; + + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh1; + cc.payload := gen_payload(kh1,10); + cc.seq_nr := gen_sn(30); + cc.src_timestamp := gen_duration(30,0); + + -- TEST: ADD SAMPLE ON MAX_SAMPLES [KNOWN INSTANCE,WITH ACKed SAMPLES (>1)] + + Log("DDS Operation WRITE [TS 30s, Instance 1, Aligned Payload] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc2 := cc; + -- Stored CC: I2S22, I1S30, I4S28, I2S29 + + Log("RTPS Operation REMOVE_CACHE_CHANGE SN 28", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := REMOVE_CACHE_CHANGE; + reference.cc := cc3; + start_ref; + wait_on_ref; + -- Stored CC: I2S22, I1S30, 0, I2S29 + + Log("RTPS Operation ACK_CACHE_CHANGE SN 22", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := ACK_CACHE_CHANGE; + reference.cc := cc1; + start_ref; + wait_on_ref; + + Log("RTPS Operation ACK_CACHE_CHANGE SN 29", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := ACK_CACHE_CHANGE; + reference.cc := cc4; + start_ref; + wait_on_ref; + + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh2; + cc.payload := gen_payload(kh2,10); + cc.seq_nr := gen_sn(31); + cc.src_timestamp := gen_duration(31,0); + + -- TEST: ADD SAMPLE ON MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE, WITH ACKed INSTANCE SAMPLES(>1)] + + Log("DDS Operation WRITE [TS 31s, Instance 2, Aligned Payload] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc1 := cc; + -- Stored CC: I2S31, I1S30, 0, I2S29 + + -- VALIDATE STATE + + Log("RTPS Operation GET_MIN_SN (Expected SN 29)", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_MIN_SN; + reference.cc.seq_nr := gen_sn(29); + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_MAX_SN (Expected SN 31)", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_MAX_SN; + reference.cc.seq_nr := gen_sn(31); + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_CACHE_CHANGE SN 29", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_CACHE_CHANGE; + reference.cc := cc4; + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_CACHE_CHANGE SN 30", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_CACHE_CHANGE; + reference.cc := cc2; + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_CACHE_CHANGE SN 31", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_CACHE_CHANGE; + reference.cc := cc1; + start_ref; + wait_on_ref; + + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh1; + cc.payload := gen_payload(kh1,10); + cc.seq_nr := gen_sn(1); + cc.src_timestamp := gen_duration(1,0); + + -- TEST: INSTANCE LOOKUP [KNOWN INSTANCE] + + Log("DDS Operation LOOKUP_INSTANCE [Instance 1]", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := LOOKUP_INSTANCE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh3; + cc.payload := gen_payload(kh3,10); + cc.seq_nr := gen_sn(1); + cc.src_timestamp := gen_duration(1,0); + + -- TEST: INSTANCE LOOKUP [UNKNOWN INSTANCE] + + Log("DDS Operation LOOKUP_INSTANCE [Unknown Instance]", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := LOOKUP_INSTANCE; + stimulus.cc := cc; + stimulus.cc.instance:= HANDLE_NIL; + start_stim; + wait_on_stim; + + wait_on_completion; + TranscriptOpen(RESULTS_FILE, APPEND_MODE); + SetTranscriptMirror; + ReportAlerts; + TranscriptClose; + std.env.stop; + wait; + end process; + + clock_prc : process + begin + clk <= '0'; + wait for 25 ns; + clk <= '1'; + wait for 25 ns; + end process; + + alert_prc : process(all) + begin + if rising_edge(clk) then + -- TODO + end if; + end process; + + stim_prc : process(all) + begin + if rising_edge(clk) then + stim_done <= '0'; + case (stim_stage) is + when IDLE => + if (stim_start = '1') then + stim_stage <= START; + else + stim_done <= '1'; + end if; + when START => + if (ack_dds = '1') then + stim_stage <= PUSH; + stim_cnt <= 0; + end if; + when PUSH => + if (ready_in_dds = '1') then + stim_cnt <= stim_cnt + 1; + if (stim_cnt = stimulus.cc.payload.length-1) then + -- DEFAULT + stim_stage <= DONE; + + case (stimulus.opcode) is + when REGISTER_INSTANCE => + stim_stage <= CHECK; + stim_cnt <= 0; + when LOOKUP_INSTANCE => + stim_stage <= CHECK; + stim_cnt <= 0; + when others => + null; + end case; + end if; + end if; + when DONE => + if (done_dds = '1') then + AffirmIfEqual(ret_id, return_code_dds, stimulus.ret_code); + stim_stage <= IDLE; + end if; + when CHECK => + if (valid_out_dds = '1') then + AffirmIfEqual(data_id, data_out_dds, stimulus.cc.instance(stim_cnt)); + stim_cnt <= stim_cnt + 1; + if (stim_cnt = 3) then + AlertIf(data_id, last_word_out_dds /= '1', "Last Word Signal not pulled High", ERROR); + stim_stage <= IDLE; + end if; + end if; + end case; + end if; + + -- DEFAULT + start_dds <= '0'; + valid_in_dds <= '0'; + last_word_in_dds <= '0'; + data_in_dds <= (others => '0'); + instance_handle_dds <= HANDLE_NIL; + source_ts_dds <= TIME_INVALID; + ready_out_dds <= '0'; + + case (stim_stage) is + when START => + start_dds <= '1'; + opcode_dds <= stimulus.opcode; + instance_handle_dds <= stimulus.cc.instance; + source_ts_dds <= stimulus.cc.src_timestamp; + when PUSH => + valid_in_dds <= '1'; + data_in_dds <= stimulus.cc.payload.data(stim_cnt); + last_word_in_dds <= stimulus.cc.payload.last(stim_cnt); + when CHECK => + ready_out_dds <= '1'; + when others => + null; + end case; + end process; + + ref_prc : process(all) + begin + if rising_edge(clk) then + ref_done <= '0'; + case (ref_stage) is + when IDLE => + if (ref_start = '1') then + ref_stage <= START; + else + ref_done <= '1'; + end if; + when START => + if (ack_rtps = '1') then + ref_stage <= DONE; + end if; + when DONE => + if (done_rtps = '1') then + -- DEFAULT + ref_stage <= IDLE; + + AffirmIfEqual(ret_id, HISTORY_CACHE_RESPONSE_TYPE'pos(ret_rtps), HISTORY_CACHE_RESPONSE_TYPE'pos(reference.ret_code)); + case (reference.opcode) is + when GET_CACHE_CHANGE => + if (reference.ret_code = OK) then + AffirmIfEqual(inst_id, cc_instance_handle(0), reference.cc.instance(0)); + AffirmIfEqual(inst_id, cc_instance_handle(1), reference.cc.instance(1)); + AffirmIfEqual(inst_id, cc_instance_handle(2), reference.cc.instance(2)); + AffirmIfEqual(inst_id, cc_instance_handle(3), reference.cc.instance(3)); + AffirmIfEqual(kind_id, CACHE_CHANGE_KIND_TYPE'pos(cc_kind), CACHE_CHANGE_KIND_TYPE'pos(reference.cc.kind)); + AffirmIfEqual(sn_id, convert_from_double_word(cc_seq_nr), convert_from_double_word(reference.cc.seq_nr)); + AffirmIfEqual(ts_id, convert_from_double_word(cc_source_timestamp), convert_from_double_word(reference.cc.src_timestamp)); + ref_stage <= CHECK; + ref_cnt <= 0; + end if; + when GET_MIN_SN => + AffirmIfEqual(sn_id, convert_from_double_word(cc_seq_nr), convert_from_double_word(reference.cc.seq_nr)); + when GET_MAX_SN => + AffirmIfEqual(sn_id, convert_from_double_word(cc_seq_nr), convert_from_double_word(reference.cc.seq_nr)); + when others => + null; + end case; + end if; + when CHECK => + if (valid_out_rtps = '1') then + AffirmIfEqual(data_id, last_word_out_rtps & data_out_rtps, reference.cc.payload.last(ref_cnt) & reference.cc.payload.data(ref_cnt)); + ref_cnt <= ref_cnt + 1; + if (ref_cnt = reference.cc.payload.length-1) then + ref_stage <= IDLE; + end if; + end if; + end case; + end if; + + -- DEFAULT + start_rtps <= '0'; + get_data_rtps <= '0'; + ready_out_rtps <= '0'; + + case (ref_stage) is + when START => + start_rtps <= '1'; + opcode_rtps <= reference.opcode; + seq_nr_rtps <= reference.cc.seq_nr; + when DONE => + if (done_rtps = '1') then + case (reference.opcode) is + when GET_CACHE_CHANGE => + get_data_rtps <= '1'; + when others => + null; + end case; + end if; + when CHECK => + ready_out_rtps <= '1'; + when others => + null; + end case; + end process; + + kh_prc : process (all) + variable tmp_key_hash : INSTANCE_HANDLE_TYPE := HANDLE_NIL; + begin + if rising_edge(clk) then + case (kh_stage) is + when IDLE => + if (start_kh = '1') then + case (opcode_kh) is + when PUSH_DATA => + kh_stage <= READ_DATA; + kh_cnt <= 0; + kh_data <= EMPTY_TEST_PACKET; + when PUSH_SERIALIZED_KEY => + kh_stage <= READ_DATA; + kh_cnt <= 0; + kh_data <= EMPTY_TEST_PACKET; + when READ_KEY_HASH => + kh_stage <= PUSH_KEY_HASH; + kh_cnt <= 0; + when others => + Alert("Unexpected Key Holder Operation", FAILURE); + end case; + end if; + when READ_DATA => + if (valid_out_kh = '1') then + kh_data.data(kh_cnt) <= data_out_kh; + kh_data.last(kh_cnt) <= last_word_out_kh; + kh_data.length <= kh_data.length + 1; + + kh_cnt <= kh_cnt + 1; + if (last_word_out_kh = '1') then + kh_stage <= IDLE; + end if; + end if; + when PUSH_KEY_HASH => + if (ready_in_kh = '1') then + kh_cnt <= kh_cnt + 1; + if (kh_cnt = INSTANCE_HANDLE_TYPE'length-1) then + kh_stage <= IDLE; + end if; + end if; + end case; + end if; + + -- DEFAULT + ack_kh <= '0'; + ready_out_kh <= '0'; + valid_in_kh <= '0'; + data_in_kh <= (others => '0'); + last_word_in_kh <= '0'; + + case (kh_stage) is + when IDLE => + if (start_kh = '1') then + ack_kh <= '1'; + end if; + when READ_DATA => + ready_out_kh <= '1'; + when PUSH_KEY_HASH => + valid_in_kh <= '1'; + tmp_key_hash := extract_key_hash(kh_data); + data_in_kh <= tmp_key_hash(kh_cnt); + if (kh_cnt = INSTANCE_HANDLE_TYPE'length-1) then + last_word_in_kh <= '1'; + end if; + end case; + end process; + + watchdog : process + begin + wait for 1 ms; + Alert("Test timeout", FAILURE); + std.env.stop; + end process; + +end architecture; \ No newline at end of file diff --git a/src/Tests/Level_0/L0_dds_writer_test1_aik.txt b/src/Tests/Level_0/L0_dds_writer_test1_aik.txt new file mode 100644 index 0000000..97efd6f --- /dev/null +++ b/src/Tests/Level_0/L0_dds_writer_test1_aik.txt @@ -0,0 +1,270 @@ + SAMPLE MEMORY: -/0,9,18,27,36 + PAYLOAD MEMORY: -/0,11,22,33,44 + INSTANCE MEMORY: -/0,8,16 +RTPS Operation GET_MIN_SN (Expected SEQUENCENUMBER_UNKNOWN) +RTPS Operation GET_MAX_SN (Expected SEQUENCENUMBER_UNKNOWN) +DDS Operation WRITE [TS 1s, Instance 1] (REJECTED: Instance not Registered) +DDS Operation WRITE [TS 1s, Instance 1, HANDLE_NIL] (ACCEPTED) + SAMPLE MEMORY: 0(I1S1)/9,18,27,36 + PAYLOAD MEMORY: 0(I1S1)/11,22,33,44 + INSTANCE MEMORY: 0(I1)/8,16 +RTPS Operation GET_MIN_SN (Expected SN 1) +RTPS Operation GET_MAX_SN (Expected SN 1) +DDS Operation WRITE [TS 2s, Instance 2, Unaligned Payload (2 Slots)] (REJECTED: Instance not Registered) +DDS Operation REGISTER_INSTANCE 2 (ACCEPTED) + SAMPLE MEMORY: 0(I1S1)/9,18,27,36 + PAYLOAD MEMORY: 0(I1S1)/11,22,33,44 + INSTANCE MEMORY: 8(I2),0(I1)/16 +DDS Operation WRITE [TS 2s, Instance 2, Unaligned Payload (2 Slots)] (ACCEPTED) + SAMPLE MEMORY: 0(I1S1),9(I2S2)/18,27,36 + PAYLOAD MEMORY: 0(I1S1),11(I2S2),22(I2S2)/33,44 + INSTANCE MEMORY: 8(I2),0(I1)/16 +DDS Operation WRITE [TS 3s, Instance 1, Unaligned Payload (2 Slots)] (ACCEPTED) + SAMPLE MEMORY: 0(I1S1),9(I2S2),18(I1S3)/27,36 + PAYLOAD MEMORY: 0(I1S1),11(I2S2),22(I2S2),33(I1S3),44(I1S3)/- + INSTANCE MEMORY: 8(I2),0(I1)/16 +RTPS Operation GET_CACHE_CHANGE SN 4 (Invalid) +RTPS Operation GET_CACHE_CHANGE SN 1 +RTPS Operation GET_CACHE_CHANGE SN 2 +RTPS Operation GET_CACHE_CHANGE SN 3 +DDS Operation WRITE [TS 4s, Instance 3, HANDLE_NIL, Unaligned Payload (1 Slot)] (REJECTED: Payload Memory Full) +RTPS Operation REMOVE_CACHE_CHANGE SN 5 (Invalid) +RTPS Operation REMOVE_CACHE_CHANGE SN 2 + SAMPLE MEMORY: 0(I1S1),18(I1S3)/27,36,9 + PAYLOAD MEMORY: 0(I1S1),33(I1S3),44(I1S3)/11,22 + INSTANCE MEMORY: 8(I2),0(I1)/16 +DDS Operation WRITE [TS 4s, Instance 3, HANDLE_NIL, Unaligned Payload (1 Slot)] (ACCEPTED) + SAMPLE MEMORY: 0(I1S1),18(I1S3),27(I3S4)/36,9 + PAYLOAD MEMORY: 0(I1S1),33(I1S3),44(I1S3),11(I3S4)/22 + INSTANCE MEMORY: 16(I3),8(I2),0(I1)/- +RTPS Operation GET_CACHE_CHANGE SN 4 +DDS Operation REGISTER_INSTANCE 3 (No Change) +DDS Operation DISPOSE [TS 5s, Instance 1] (REJECTED: MAX_SAMPLES_PER_INSTANCE Exceeded) +RTPS Operation ACK_CACHE_CHANGE SN 4 +DDS Operation DISPOSE [TS 5s, Instance 1] (REJECTED: MAX_SAMPLES_PER_INSTANCE Exceeded) +RTPS Operation ACK_CACHE_CHANGE SN 1 +DDS Operation DISPOSE [TS 5s, Instance 1] (ACCEPTED) + SAMPLE MEMORY: 18(I1S3),27(I3S4),36(I1S5)/9,0 + PAYLOAD MEMORY: 33(I1S3),44(I1S3),11(I3S4),22(I1S5)/0 + INSTANCE MEMORY: 16(I3),8(I2),0(I1)/- +RTPS Operation GET_MIN_SN (Expected SN 3) +RTPS Operation GET_MAX_SN (Expected SN 5) +RTPS Operation GET_CACHE_CHANGE SN 5 +DDS Operation WRITE [TS 6s, Instance 4, HANDLE_NIL, Aligned Payload] (REJECTED: MAX_INSTANCES exceeded) +RTPS Operation ACK_CACHE_CHANGE SN 3 +RTPS Operation ACK_CACHE_CHANGE SN 4 +RTPS Operation ACK_CACHE_CHANGE SN 5 +DDS Operation WRITE [TS 6s, Instance 4, HANDLE_NIL, Aligned Payload] (REJECTED: MAX_INSTANCES exceeded) +DDS Operation UNREGISTER_INSTANCE [TS 6s, Instance 1] (ACCEPTED) + SAMPLE MEMORY: 27(I3S4),36(I1S5),9(I1S6)/0,18 + PAYLOAD MEMORY: 11(I3S4),22(I1S5),0(I1S6)/33,44 + INSTANCE MEMORY: 16(I3),8(I2),0(I1)/- +RTPS Operation GET_MIN_SN (Expected SN 4) +RTPS Operation GET_MAX_SN (Expected SN 6) +RTPS Operation GET_CACHE_CHANGE SN 6 +DDS Operation WRITE [TS 7s, Instance 4, HANDLE_NIL, Aligned Payload] (REJECTED: MAX_INSTANCES exceeded) +RTPS Operation ACK_CACHE_CHANGE SN 6 +DDS Operation WRITE [TS 7s, Instance 4, HANDLE_NIL, Aligned Payload] (ACCEPTED) + SAMPLE MEMORY: 27(I3S4),0(I4S7)/18,36,9 + PAYLOAD MEMORY: 11(I3S4),33(I4S7)/0,22,44 + INSTANCE MEMORY: 0(I4),16(I3),8(I2)/- +RTPS Operation GET_CACHE_CHANGE SN 5 (Invalid) +RTPS Operation GET_CACHE_CHANGE SN 6 (Invalid) +RTPS Operation GET_CACHE_CHANGE SN 7 +DDS Operation WRITE [TS 8s, Instance 2, Unaligned Payload (2 Slots)] (ACCEPTED) + SAMPLE MEMORY: 27(I3S4),0(I4S7),18(I2S8)/36,9 + PAYLOAD MEMORY: 11(I3S4),33(I4S7),0(I2S8),22(I2S8)/44 + INSTANCE MEMORY: 0(I4),16(I3),8(I2)/- +DDS Operation WRITE [TS 9s, Instance 1, Aligned Payload] (REJECTED: Instance not Registered) +DDS Operation REGISTER_INSTANCE 1 (REJECTED: MAX_INSTANCES exceeded) +DDS Operation UNREGISTER_INSTANCE [TS 9s, Instance 3] (ACCEPTED) + SAMPLE MEMORY: 27(I3S4),0(I4S7),18(I2S8),36(I3S9)/9 + PAYLOAD MEMORY: 11(I3S4),33(I4S7),0(I2S8),22(I2S8),44(I3S9)/- + INSTANCE MEMORY: 0(I4),16(I3),8(I2)/- +RTPS Operation GET_MIN_SN (Expected SN 4) +RTPS Operation GET_MAX_SN (Expected SN 9) +RTPS Operation GET_CACHE_CHANGE SN 8 +RTPS Operation GET_CACHE_CHANGE SN 9 +RTPS Operation ACK_CACHE_CHANGE SN 9 +DDS Operation REGISTER_INSTANCE 1 (ACCPETED) + SAMPLE MEMORY: 0(I4S7),18(I2S8)/9,27,36 + PAYLOAD MEMORY: 33(I4S7),0(I2S8),22(I2S8)/44,11 + INSTANCE MEMORY: 16(I1),0(I4),8(I2)/- +DDS Operation WRITE [TS 10s, Instance 1, Aligned Payload] (ACCEPTED) + SAMPLE MEMORY: 0(I4S7),18(I2S8),9(I1S10)/27,36 + PAYLOAD MEMORY: 33(I4S7),0(I2S8),22(I2S8),44(I1S10)/11 + INSTANCE MEMORY: 16(I1),0(I4),8(I2)/- +DDS Operation WRITE [TS 11s, Instance 1, Aligned Payload] (ACCEPTED) + SAMPLE MEMORY: 0(I4S7),18(I2S8),9(I1S10),27(I4S11)/36 + PAYLOAD MEMORY: 33(I4S7),0(I2S8),22(I2S8),44(I1S10),11(I4S11)/- + INSTANCE MEMORY: 16(I1),0(I4),8(I2)/- +DDS Operation WRITE [TS 12s, Instance 2, Aligned Payload] (REJECTED: Payload Memory Full) +RTPS Operation ACK_CACHE_CHANGE SN 8 +DDS Operation WRITE [TS 12s, Instance 2, Aligned Payload] (ACCEPTED) + SAMPLE MEMORY: 0(I4S7),9(I1S10),27(I4S11),36(I2S12)/18 + PAYLOAD MEMORY: 33(I4S7),44(I1S10),11(I4S11),0(I2S12)/22 + INSTANCE MEMORY: 16(I1),0(I4),8(I2)/- +DDS Operation WRITE [TS 13s, Instance 4, Aligned Payload] (REJECTED: MAX_SAMPLES exceeded) +RTPS Operation ACK_CACHE_CHANGE SN 7 +DDS Operation WRITE [TS 13s, Instance 4, Aligned Payload] (ACCEPTED) + SAMPLE MEMORY: 9(I1S10),27(I4S11),36(I2S12),18(I4S13)/0 + PAYLOAD MEMORY: 44(I1S10),11(I4S11),0(I2S12),22(I4S13)/33 + INSTANCE MEMORY: 16(I1),0(I4),8(I2)/- +RTPS Operation GET_MIN_SN (Expected SN 4) +RTPS Operation GET_MAX_SN (Expected SN 9) +RTPS Operation GET_CACHE_CHANGE SN 10 +RTPS Operation GET_CACHE_CHANGE SN 11 +RTPS Operation GET_CACHE_CHANGE SN 12 +RTPS Operation GET_CACHE_CHANGE SN 13 +RTPS Operation ACK_CACHE_CHANGE SN 12 +DDS Operation UNREGISTER_INSTANCE [TS 14s, Instance 2] (ACCEPTED) + SAMPLE MEMORY: 9(I1S10),27(I4S11),18(I4S13),0(I2S14)/36 + PAYLOAD MEMORY: 44(I1S10),11(I4S11),22(I4S13),33(I2S14)/0 + INSTANCE MEMORY: 16(I1),0(I4),8(I2)/- +RTPS Operation ACK_CACHE_CHANGE SN 11 +DDS Operation WRITE [TS 15s, Instance 4, Aligned Payload (2 Slots)] (REJECTED: Payload Memory Full) +RTPS Operation REMOVE_CACHE_CHANGE SN 11 + SAMPLE MEMORY: 9(I1S10),18(I4S13),0(I2S14)/36,27 + PAYLOAD MEMORY: 44(I1S10),22(I4S13),33(I2S14)/11,0 + INSTANCE MEMORY: 16(I1),0(I4),8(I2)/- +DDS Operation WRITE [TS 15s, Instance 4, Aligned Payload (2 Slots)] (ACCEPTED) + SAMPLE MEMORY: 9(I1S10),18(I4S13),0(I2S14),36(I4S15)/27 + PAYLOAD MEMORY: 44(I1S10),22(I4S13),33(I2S14),11(I4S15),0(I4S15)/- + INSTANCE MEMORY: 16(I1),0(I4),8(I2)/- +DDS Operation UNREGISTER_INSTANCE [TS 16s, Instance 1] (REJECTED: Payload memory Full, MAX_SAMPLES exceeded) +RTPS Operation ACK_CACHE_CHANGE SN 10 +DDS Operation UNREGISTER_INSTANCE [TS 16s, Instance 1] (ACCEPTED) + SAMPLE MEMORY: 18(I4S13),0(I2S14),36(I4S15),27(I1S16)/9 + PAYLOAD MEMORY: 22(I4S13),33(I2S14),11(I4S15),0(I4S15),44(I1S16)/- + INSTANCE MEMORY: 16(I1),0(I4),8(I2)/- +DDS Operation DISPOSE [TS 17s, Instance 3] (REJECTED: Payload memory Full, MAX_SAMPLES exceeded) +RTPS Operation ACK_CACHE_CHANGE SN 13 +RTPS Operation ACK_CACHE_CHANGE SN 14 +DDS Operation DISPOSE [TS 17s, Instance 3] (ACCEPTED) + SAMPLE MEMORY: 36(I4S15),27(I1S16),9(I3S17)/18,0 + PAYLOAD MEMORY: 11(I4S15),0(I4S15),44(I1S16),22(I3S17)/33 + INSTANCE MEMORY: 8(I3),16(I1),0(I4)/- +RTPS Operation GET_MIN_SN (Expected SN 15) +RTPS Operation GET_MAX_SN (Expected SN 17) +RTPS Operation GET_CACHE_CHANGE SN 15 +RTPS Operation GET_CACHE_CHANGE SN 16 +RTPS Operation GET_CACHE_CHANGE SN 17 +RTPS Operation REMOVE_CACHE_CHANGE SN 15 + SAMPLE MEMORY: 27(I1S16),9(I3S17)/18,0,36 + PAYLOAD MEMORY: 44(I1S16),22(I3S17)/11,0,33 + INSTANCE MEMORY: 8(I3),16(I1),0(I4)/- +DDS Operation WRITE [TS 18s, Instance 3, Aligned Payload] (ACCEPTED) + SAMPLE MEMORY: 27(I1S16),9(I3S17),18(I3S18)/0,36 + PAYLOAD MEMORY: 44(I1S16),22(I3S17),11(I3S18)/0,33 + INSTANCE MEMORY: 8(I3),16(I1),0(I4)/- +DDS Operation WRITE [TS 19s, Instance 4, Aligned Payload] (ACCEPTED) + SAMPLE MEMORY: 27(I1S16),9(I3S17),18(I3S18),0(I4S19)/36 + PAYLOAD MEMORY: 44(I1S16),22(I3S17),11(I3S18),0(I4S19)/33 + INSTANCE MEMORY: 8(I3),16(I1),0(I4)/- +DDS Operation WRITE [TS 20s, Instance 2, Aligned Payload] (REJECTED: MAX_SAMPLES exceeded, MAX_INSTANCES exceeded) +RTPS Operation ACK_CACHE_CHANGE SN 16 +DDS Operation WRITE [TS 20s, Instance 2, Aligned Payload] (ACCEPTED) + SAMPLE MEMORY: 9(I3S17),18(I3S18),0(I4S19),36(I2S20)/27 + PAYLOAD MEMORY: 22(I3S17),11(I3S18),0(I4S19),33(I2S20)/44 + INSTANCE MEMORY: 16(I2),8(I3),0(I4)/- +RTPS Operation ACK_CACHE_CHANGE SN 17 +DDS Operation UNREGISTER_INSTANCE [TS 21s, Instance 4] (ACCEPTED) + SAMPLE MEMORY: 18(I3S18),0(I4S19),36(I2S20),27(I4S21)/9 + PAYLOAD MEMORY: 11(I3S18),0(I4S19),33(I2S20),44(I4S21)/22 + INSTANCE MEMORY: 16(I2),8(I3),0(I4)/- +RTPS Operation ACK_CACHE_CHANGE SN 19 +DDS Operation WRITE [TS 22s, Instance 1, Aligned Payload] (REJECTED: MAX_SAMPLES exceeded, MAX_INSTANCES exceeded) +RTPS Operation REMOVE_CACHE_CHANGE SN 19 + SAMPLE MEMORY: 18(I3S18),36(I2S20),27(I4S21)/9,0 + PAYLOAD MEMORY: 11(I3S18),33(I2S20),44(I4S21)/0,22 + INSTANCE MEMORY: 16(I2),8(I3),0(I4)/- +RTPS Operation REMOVE_CACHE_CHANGE SN 21 + SAMPLE MEMORY: 18(I3S18),36(I2S20)/9,0,27 + PAYLOAD MEMORY: 11(I3S18),33(I2S20)/44,0,22 + INSTANCE MEMORY: 16(I2),8(I3),0(I4)/- +DDS Operation UNREGISTER_INSTANCE [TS 22s, Instance 2] (ACCEPTED) + SAMPLE MEMORY: 18(I3S18),36(I2S20),9(I2S22)/0,27 + PAYLOAD MEMORY: 11(I3S18),33(I2S20),44(I2S22)/0,22 + INSTANCE MEMORY: 16(I2),8(I3),0(I4)/- +DDS Operation UNREGISTER_INSTANCE [TS 23s, Instance 3] (ACCEPTED) + SAMPLE MEMORY: 18(I3S18),36(I2S20),9(I2S22),0(I3S23)/27 + PAYLOAD MEMORY: 11(I3S18),33(I2S20),44(I2S22),0(I3S23)/22 + INSTANCE MEMORY: 16(I2),8(I3),0(I4)/- +DDS Operation WRITE [TS 24s, Instance 1, Aligned Payload] (REJECTED: MAX_SAMPLES exceeded, MAX_INSTANCES exceeded) +RTPS Operation ACK_CACHE_CHANGE SN 20 +DDS Operation WRITE [TS 24s, Instance 1, Aligned Payload] (ACCEPTED) + SAMPLE MEMORY: 18(I3S18),9(I2S22),0(I3S23),27(I1S24)/36 + PAYLOAD MEMORY: 11(I3S18),44(I2S22),0(I3S23),22(I1S24)/33 + INSTANCE MEMORY: 0(I1),16(I2),8(I3)/- +RTPS Operation ACK_CACHE_CHANGE SN 22 +RTPS Operation NACK_CACHE_CHANGE SN 22 +DDS Operation REGISTER_INSTANCE 4 (REJECTED: MAX_INSTANCES exceeded) +RTPS Operation ACK_CACHE_CHANGE SN 22 +DDS Operation REGISTER_INSTANCE 2 (ACCEPTED) +DDS Operation REGISTER_INSTANCE 4 (REJECTED: MAX_INSTANCES exceeded) +RTPS Operation ACK_CACHE_CHANGE SN 18 +RTPS Operation ACK_CACHE_CHANGE SN 23 +DDS Operation WRITE [TS 25s, Instance 3, Aligned Payload] (ACCEPTED) + SAMPLE MEMORY: 9(I2S22),0(I3S23),27(I1S24),36(I3S25)/18 + PAYLOAD MEMORY: 44(I2S22),0(I3S23),22(I1S24),33(I3S25)/11 + INSTANCE MEMORY: 0(I1),16(I2),8(I3)/- +DDS Operation REGISTER_INSTANCE 4 (REJECTED: MAX_INSTANCES exceeded) +DDS Operation UNREGISTER_INSTANCE [TS 26s, Instance 4] (REJECTED: Instance not Registered) +RTPS Operation NACK_CACHE_CHANGE SN 22 +RTPS Operation NACK_CACHE_CHANGE SN 23 +DDS Operation UNREGISTER_INSTANCE [TS 26s, Instance 3] (REJECTED: MAX_SAMPLES_PER_INSTANCE exceeded, MAX_SAMPLES exceeded) +RTPS Operation ACK_CACHE_CHANGE SN 22 +DDS Operation UNREGISTER_INSTANCE [TS 26s, Instance 3] (REJECTED: MAX_SAMPLES_PER_INSTANCE exceeded, MAX_SAMPLES exceeded) +RTPS Operation ACK_CACHE_CHANGE SN 23 +DDS Operation UNREGISTER_INSTANCE [TS 26s, Instance 3] (ACCEPTED) + SAMPLE MEMORY: 9(I2S22),27(I1S24),36(I3S25),18(I3S26)/0 + PAYLOAD MEMORY: 44(I2S22),22(I1S24),33(I3S25),11(I3S26)/0 + INSTANCE MEMORY: 0(I1),16(I2),8(I3)/- +RTPS Operation ACK_CACHE_CHANGE SN 25 +DDS Operation DISPOSE [TS 27s, Instance 3] (ACCEPTED) + SAMPLE MEMORY: 9(I2S22),27(I1S24),18(I3S26),0(I3S27)/36 + PAYLOAD MEMORY: 44(I2S22),22(I1S24),11(I3S26),0(I3S27)/33 + INSTANCE MEMORY: 0(I1),16(I2),8(I3)/- +RTPS Operation ACK_CACHE_CHANGE SN 26 +RTPS Operation ACK_CACHE_CHANGE SN 27 +DDS Operation REGISTER_INSTANCE 4 (ACCEPTED) + SAMPLE MEMORY: 9(I2S22),27(I1S24)/36,18,0 + PAYLOAD MEMORY: 44(I2S22),22(I1S24)/0,11,33 + INSTANCE MEMORY: 8(I4),0(I1),16(I2)/- +RTPS Operation GET_MIN_SN (Expected SN 22) +RTPS Operation GET_MAX_SN (Expected SN 24) +RTPS Operation GET_CACHE_CHANGE SN 22 +RTPS Operation GET_CACHE_CHANGE SN 24 +RTPS Operation NACK_CACHE_CHANGE SN 22 +RTPS Operation NACK_CACHE_CHANGE SN 24 +DDS Operation WRITE [TS 28s, Instance 4, Aligned Payload] (ACCEPTED) + SAMPLE MEMORY: 9(I2S22),27(I1S24),36(I4S28)/18,0 + PAYLOAD MEMORY: 44(I2S22),22(I1S24),0(I4S28)/11,33 + INSTANCE MEMORY: 8(I4),0(I1),16(I2)/- +DDS Operation WRITE [TS 29s, Instance 2, Aligned Payload] (ACCEPTED) + SAMPLE MEMORY: 9(I2S22),27(I1S24),36(I4S28),18(I2S29)/0 + PAYLOAD MEMORY: 44(I2S22),22(I1S24),0(I4S28),11(I2S29)/33 + INSTANCE MEMORY: 8(I4),0(I1),16(I2)/- +RTPS Operation ACK_CACHE_CHANGE SN 24 +RTPS Operation ACK_CACHE_CHANGE SN 28 +DDS Operation WRITE [TS 30s, Instance 1, Aligned Payload] (ACCEPTED) + SAMPLE MEMORY: 9(I2S22),36(I4S28),18(I2S29),0(I1S30)/27 + PAYLOAD MEMORY: 44(I2S22),0(I4S28),11(I2S29),33(I1S30)/22 + INSTANCE MEMORY: 8(I4),0(I1),16(I2)/- +RTPS Operation REMOVE_CACHE_CHANGE SN 28 + SAMPLE MEMORY: 9(I2S22),18(I2S29),0(I1S30)/27,36 + PAYLOAD MEMORY: 44(I2S22),11(I2S29),33(I1S30)/0,22 + INSTANCE MEMORY: 8(I4),0(I1),16(I2)/- +RTPS Operation ACK_CACHE_CHANGE SN 22 +RTPS Operation ACK_CACHE_CHANGE SN 29 +DDS Operation WRITE [TS 31s, Instance 2, Aligned Payload] (ACCEPTED) + SAMPLE MEMORY: 18(I2S29),0(I1S30),27(I2S31)/36,9 + PAYLOAD MEMORY: 11(I2S29),33(I1S30),0(I2S31)/44,22 + INSTANCE MEMORY: 8(I4),0(I1),16(I2)/- +RTPS Operation GET_MIN_SN (Expected SN 29) +RTPS Operation GET_MAX_SN (Expected SN 31) +RTPS Operation GET_CACHE_CHANGE SN 29 +RTPS Operation GET_CACHE_CHANGE SN 30 +RTPS Operation GET_CACHE_CHANGE SN 31 +DDS Operation LOOKUP_INSTANCE [Instance 1] +DDS Operation LOOKUP_INSTANCE [Unknown Instance] \ No newline at end of file diff --git a/src/Tests/Level_0/L0_dds_writer_test1_aik.vhd b/src/Tests/Level_0/L0_dds_writer_test1_aik.vhd new file mode 100644 index 0000000..9700cf3 --- /dev/null +++ b/src/Tests/Level_0/L0_dds_writer_test1_aik.vhd @@ -0,0 +1,2179 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library osvvm; -- Utility Library +context osvvm.OsvvmContext; + +use work.rtps_package.all; +use work.user_config.all; +use work.rtps_config_package.all; +use work.rtps_test_package.all; + +entity L0_dds_writer_test1_aik is +end entity; + +-- This testbench tests the General Operation of the DDS Writer. It tests the correctness of the RTPS +-- GET_MIN_SN, GET_MAX_SN, GET_CACHE_CHANGE, REMOVE_CACHE_CHANGE, ACK_CACHE_CHANGE, and NACK_CACHE_CHANGE Operations and the +-- DDS REGISTER_INSTANCE, UNREGISTER_INSTANCE, WRITE, DISPOSE, and LOOKUP_INSTANCE Operations. +-- More specifically the testbench covers following tests: +-- TEST: GET_MIN_SN/GET_MAX_SN ON EMPTY +-- TEST: GET_MIN_SN/GET_MAX_SN ON 1 SAMPLE +-- TEST: GET_MIN_SN/GET_MAX_SN ON >1 SAMPLE +-- TEST: ADD SAMPLE WITH KEY_HASH [UNKNOWN INSTANCE] +-- TEST: ADD SAMPLE WITH KEY_HASH [KNOWN INSTANCE] +-- TEST: ADD SAMPLE WITH HANDLE_NIL [UNKNOWN INSTANCE] +-- TEST: ADD SAMPLE WITH HANDLE_NIL [KNOWN INSTANCE] +-- TEST: NORMAL WRITE +-- TEST: WRITE ON PAYLOAD MEMORY FULL [WITHOUT ACKed SAMPLES] +-- TEST: WRITE ON PAYLOAD MEMORY FULL [WITH ACKed SAMPLES] +-- TEST: WRITE ON DISPOSED INSTANCE +-- TEST: WRITE ON UNREGISTERED INSTANCE +-- TEST: WRITE ALIGNED PAYLOAD +-- TEST: WRITE UNALIGNED PAYLOAD [>1 SLOT] +-- TEST: WRITE UNALIGNED PAYLOAD [<1 SLOT] +-- TEST: NORMAL REGISTER +-- TEST: REGISTER INSTANCE [KNOWN INSTANCE] +-- TEST: REGISTER INSTANCE ON MAX_INSTANCES [UNKNOWN INSTANCE, WITHOUT STALE INSTANCE] +-- TEST: REGISTER INSTANCE ON MAX_INSTANCES [UNKNOWN INSTANCE, WITH STALE INSTANCE] +-- TEST: REGISTER ON UNREGISTERED INSTANCE +-- TEST: NORMAL DISPOSE +-- TEST: DISPOSE ON PAYLOAD MEMORY FULL [WITHOUT ACKed SAMPLES] +-- TEST: DISPOSE ON PAYLOAD MEMORY FULL [WITH ACKed SAMPLES] +-- TEST: DISPOSE ON UNREGISTERED INSTANCE +-- TEST: GET_CACHE_CHANGE [UNKNOWN SN] +-- TEST: GET_CACHE_CHANGE [KNOWN SN, ALIGNED PAYLOAD] +-- TEST: GET_CACHE_CHANGE [KNOWN SN, UNALIGNED PAYLOAD, >1 SLOT] +-- TEST: GET_CACHE_CHANGE [KNOWN SN, UNALIGNED PAYLOAD, <1 SLOT] +-- TEST: NORMAL ACK_CACHE_CHANGE +-- TEST: ACK_CACHE_CHANGE [ALREADY ACKed SN] +-- TEST: NORMAL NACK_CACHE_CHANGE +-- TEST: REMOVE_CACHE_CHANGE [UNKNOWN SN] +-- TEST: REMOVE_CACHE_CHANGE [KNOWN SN] +-- TEST: NORMAL UNREGISTER +-- TEST: UNREGISTER INSTANCE ON PAYLOAD MEMORY FULL [WITHOUT ACKed SAMPLES] +-- TEST: UNREGISTER INSTANCE ON PAYLOAD MEMORY FULL [WITH ACKed SAMPLES] +-- TEST: UNREGISTER ON DISPOSED INSTANCE +-- TEST: UNREGISTER UNKNOWN INSTANCE +-- TEST: REMOVE STALE INSTANCE WITH 0 SAMPLES +-- TEST: REMOVE STALE INSTANCE WITH 1 SAMPLES +-- TEST: REMOVE STALE INSTANCE WITH >1 SAMPLES +-- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKNOWN INSTANCE, WITH STALE INSTANCE] +-- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKNOWN INSTANCE, WITHOUT STALE INSTANCES] +-- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKNOWN INSTANCE, WITH FULLY ACKed INSTANCE, WITHOUT STALE INSTANCE] +-- TEST: ADD SAMPLE ON MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE, WITHOUT ACKed SAMPLES] +-- TEST: ADD SAMPLE ON MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE, WITH ACKed SAMPLES, WITHOUT ACKed INSTANCE SAMPLES] +-- TEST: ADD SAMPLE ON MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE, WITH ACKed INSTANCE SAMPLE] +-- TEST: ADD SAMPLE ON MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE, WITH ACKed INSTANCE SAMPLES(>1)] +-- TEST: ADD SAMPLE ON MAX_SAMPLES [KNOWN INSTANCE,WITHOUT ACKed SAMPLES] +-- TEST: ADD SAMPLE ON MAX_SAMPLES [KNOWN INSTANCE,WITH ACKed SAMPLE] +-- TEST: ADD SAMPLE ON MAX_SAMPLES [KNOWN INSTANCE,WITH ACKed SAMPLES (>1)] +-- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE,WITHOUT ACKed SAMPLES] +-- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE,WITH ACKed SAMPLES, WITHOUT ACKed INSTANCE SAMPLES] +-- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE,WITH ACKed INSTANCE SAMPLES] +-- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE,WITH STALE INSTANCE, WITHOUT ACKed SAMPLE] +-- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE,WITHOUT STALE INSTANCES,WITHOUT ACKed SAMPLES] +-- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE,WITHOUT STALE INSTANCE, WITH ACKed SAMPLE] +-- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE,WITH STALE INSTANCE (>0 SAMPLES)] +-- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE,WITH STALE INSTANCE, WITH ACKed SAMPLE] +-- TEST: ADD SAMPLE ON PAYLOAD FULL & MAX_INSTANCES [UNKNOWN INSTANCE,WITH ACKed SAMPLES,WITH STALE INSTANCE (>= 1 SAMPLE)] (Induce Double Remove) +-- TEST: ADD SAMPLE BIGGER THAN AVAILABLE MEMORY SPACE [WITH ACKed SAMPLES] +-- TEST: INSTANCE LOOKUP [KNOWN INSTANCE] +-- TEST: INSTANCE LOOKUP [UNKNOWN INSTANCE] + +architecture testbench of L0_dds_writer_test1_aik is + + -- *CONSTANT DECLARATION* + constant MAX_REMOTE_ENDPOINTS : natural := 3; + + -- *TYPE DECLARATION* + type STIM_STAGE_TYPE is (IDLE, START, PUSH, DONE, CHECK); + type REF_STAGE_TYPE is (IDLE, START, DONE, CHECK); + type KH_STAGE_TYPE is (IDLE, READ_DATA, PUSH_KEY_HASH); + type RTPS_TEST_TYPE is record + opcode : HISTORY_CACHE_OPCODE_TYPE; + cc : CACHE_CHANGE_TYPE; + ret_code : HISTORY_CACHE_RESPONSE_TYPE; + end record; + constant DEFAULT_RTPS_TEST : RTPS_TEST_TYPE := ( + opcode => NOP, + cc => DEFAULT_CACHE_CHANGE, + ret_code => OK + ); + type DDS_TEST_TYPE is record + opcode : DDS_WRITER_OPCODE_TYPE; + cc : CACHE_CHANGE_TYPE; + ret_code : std_logic_vector(RETURN_CODE_WIDTH-1 downto 0); + end record; + constant DEFAULT_DDS_TEST : DDS_TEST_TYPE := ( + opcode => NOP, + cc => DEFAULT_CACHE_CHANGE, + ret_code => RETCODE_OK + ); + + -- *SIGNAL DECLARATION* + signal clk : std_logic := '0'; + signal reset : std_logic := '1'; + signal check_time : TIME_TYPE := TIME_ZERO; + signal start_rtps, start_dds, start_kh, ack_rtps, ack_dds, ack_kh, done_rtps, done_dds : std_logic := '0'; + signal opcode_rtps : HISTORY_CACHE_OPCODE_TYPE := NOP; + signal opcode_dds : DDS_WRITER_OPCODE_TYPE := NOP; + signal opcode_kh : KEY_HOLDER_OPCODE_TYPE := NOP; + signal ret_rtps : HISTORY_CACHE_RESPONSE_TYPE := ERROR; + signal seq_nr_rtps, cc_seq_nr : SEQUENCENUMBER_TYPE := SEQUENCENUMBER_UNKNOWN; + signal ready_out_rtps, valid_out_rtps, last_word_out_rtps : std_logic := '0'; + signal ready_in_dds, ready_out_dds, valid_in_dds, valid_out_dds, last_word_in_dds, last_word_out_dds : std_logic := '0'; + signal ready_in_kh, ready_out_kh, valid_in_kh, valid_out_kh, last_word_in_kh, last_word_out_kh : std_logic := '0'; + signal data_out_rtps, data_in_dds, data_out_dds, data_in_kh, data_out_kh : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); + signal get_data_rtps, liveliness_assertion, data_available, abort_kh : std_logic := '0'; + signal cc_source_timestamp, source_ts_dds : TIME_TYPE := TIME_INVALID; + signal cc_kind : CACHE_CHANGE_KIND_TYPE := ALIVE; + signal cc_instance_handle, instance_handle_dds : INSTANCE_HANDLE_TYPE := HANDLE_NIL; + signal max_wait_dds : DURATION_TYPE := DURATION_INFINITE; + signal return_code_dds : std_logic_vector(RETURN_CODE_WIDTH-1 downto 0) := (others => '0'); + signal status : std_logic_vector(STATUS_KIND_WIDTH-1 downto 0) := (others => '0'); + + signal stim_start, stim_done, ref_start, ref_done : std_logic := '0'; + signal stim_cnt, ref_cnt, kh_cnt : natural := 0; + signal stim_stage : STIM_STAGE_TYPE := IDLE; + signal ref_stage : REF_STAGE_TYPE := IDLE; + signal kh_stage : KH_STAGE_TYPE := IDLE; + signal kh_data : TEST_PACKET_TYPE := EMPTY_TEST_PACKET; + shared variable stimulus : DDS_TEST_TYPE := DEFAULT_DDS_TEST; + shared variable reference : RTPS_TEST_TYPE := DEFAULT_RTPS_TEST; + signal inst_id, kind_id, sn_id, ts_id, data_id, ret_id : AlertLogIDType; + + -- *FUNCTION DECLARATION* + function extract_key_hash (payload : TEST_PACKET_TYPE) return INSTANCE_HANDLE_TYPE is + variable ret : INSTANCE_HANDLE_TYPE := HANDLE_NIL; + begin + for i in 0 to 3 loop + ret(i) := not payload.data(i); + end loop; + + return ret; + end function; + + function gen_sn(input : natural) return SEQUENCENUMBER_TYPE is + variable ret : SEQUENCENUMBER_TYPE; + begin + ret(0) := (others => '0'); + ret(1) := unsigned(int(input, WORD_WIDTH)); + return ret; + end function; + +begin + + -- Unit Under Test + uut : entity work.dds_writer(arch) + generic map( + HISTORY_QOS => KEEP_ALL_HISTORY_QOS, + DEADLINE_QOS => DURATION_INFINITE, + LIFESPAN_QOS => DURATION_INFINITE, + LEASE_DURATION => DURATION_INFINITE, + WITH_KEY => TRUE, + MAX_SAMPLES => std_logic_vector(to_unsigned(4,CDR_LONG_WIDTH)), + MAX_INSTANCES => std_logic_vector(to_unsigned(3,CDR_LONG_WIDTH)), + MAX_SAMPLES_PER_INSTANCE => std_logic_vector(to_unsigned(2,CDR_LONG_WIDTH)), + PAYLOAD_FRAME_SIZE => 11 + ) + port map ( + clk => clk, + reset => reset, + time => check_time, + start_rtps => start_rtps, + opcode_rtps => opcode_rtps, + ack_rtps => ack_rtps, + done_rtps => done_rtps, + ret_rtps => ret_rtps, + seq_nr_rtps => seq_nr_rtps, + get_data_rtps => get_data_rtps, + data_out_rtps => data_out_rtps, + valid_out_rtps => valid_out_rtps, + ready_out_rtps => ready_out_rtps, + last_word_out_rtps => last_word_out_rtps, + liveliness_assertion => liveliness_assertion, + data_available => data_available, + cc_instance_handle => cc_instance_handle, + cc_kind => cc_kind, + cc_source_timestamp => cc_source_timestamp, + cc_seq_nr => cc_seq_nr, + start_kh => start_kh, + opcode_kh => opcode_kh, + ack_kh => ack_kh, + data_in_kh => data_in_kh, + valid_in_kh => valid_in_kh, + ready_in_kh => ready_in_kh, + last_word_in_kh => last_word_in_kh, + data_out_kh => data_out_kh, + valid_out_kh => valid_out_kh, + ready_out_kh => ready_out_kh, + last_word_out_kh => last_word_out_kh, + abort_kh => abort_kh, + start_dds => start_dds, + ack_dds => ack_dds, + opcode_dds => opcode_dds, + instance_handle_dds => instance_handle_dds, + source_ts_dds => source_ts_dds, + max_wait_dds => max_wait_dds, + done_dds => done_dds, + return_code_dds => return_code_dds, + ready_in_dds => ready_in_dds, + valid_in_dds => valid_in_dds, + data_in_dds => data_in_dds, + last_word_in_dds => last_word_in_dds, + ready_out_dds => ready_out_dds, + valid_out_dds => valid_out_dds, + data_out_dds => data_out_dds, + last_word_out_dds => last_word_out_dds, + status => status + ); + + stimulus_prc : process + variable RV : RandomPType; + variable kh1, kh2, kh3, kh4 : INSTANCE_HANDLE_TYPE := HANDLE_NIL; + variable cc1, cc2, cc3, cc4, cc : CACHE_CHANGE_TYPE := DEFAULT_CACHE_CHANGE; + + impure function gen_payload(key_hash : INSTANCE_HANDLE_TYPE; len : natural) return TEST_PACKET_TYPE is + variable ret : TEST_PACKET_TYPE := EMPTY_TEST_PACKET; + begin + assert (len >= 4) report "Payload length has to be at least 16 Bytes long" severity FAILURE; + + for i in 0 to len-1 loop + if (i < 4) then + -- NOTE: Beginning of payload is negated key to allow deterministic Key Hash generation from the kh_prc + ret.data(ret.length) := not key_hash(i); + else + ret.data(ret.length) := RV.RandSlv(WORD_WIDTH); + end if; + ret.length := ret.length + 1; + end loop; + ret.last(ret.length-1) := '1'; + + return ret; + end function; + + impure function gen_key_hash return KEY_HASH_TYPE is + variable ret : KEY_HASH_TYPE := (others => (others => '0')); + begin + for i in 0 to KEY_HASH_TYPE'length-1 loop + ret(i) := RV.RandSlv(WORD_WIDTH); + end loop; + return ret; + end function; + + procedure start_stim is + begin + stim_start <= '1'; + wait until rising_edge(clk); + stim_start <= '0'; + wait until rising_edge(clk); + end procedure; + + procedure start_ref is + begin + ref_start <= '1'; + wait until rising_edge(clk); + ref_start <= '0'; + wait until rising_edge(clk); + end procedure; + + procedure wait_on_stim is + begin + if (stim_done /= '1') then + wait until stim_done = '1'; + end if; + end procedure; + + procedure wait_on_ref is + begin + if (ref_done /= '1') then + wait until ref_done = '1'; + end if; + end procedure; + + procedure wait_on_completion is + begin + if (ref_done /= '1' or stim_done /= '1') then + wait until ref_done = '1' and stim_done = '1'; + end if; + end procedure; + + begin + + SetAlertLogName("dds_writer - (KEEP ALL, Infinite Lifespan, Keyed) - Level 0 - General"); + SetAlertEnable(FAILURE, TRUE); + SetAlertEnable(ERROR, TRUE); + SetAlertEnable(WARNING, TRUE); + SetLogEnable(DEBUG, FALSE); + SetLogEnable(PASSED, FALSE); + SetLogEnable(INFO, TRUE); + RV.InitSeed(RV'instance_name); + inst_id <= GetAlertLogID("Instance", ALERTLOG_BASE_ID); + kind_id <= GetAlertLogID("Cache Change Kind", ALERTLOG_BASE_ID); + sn_id <= GetAlertLogID("SequenceNumber", ALERTLOG_BASE_ID); + ts_id <= GetAlertLogID("TimeStamp", ALERTLOG_BASE_ID); + data_id <= GetAlertLogID("Data Out", ALERTLOG_BASE_ID); + ret_id <= GetAlertLogID("Return Code", ALERTLOG_BASE_ID); + + -- Key Hashes + kh1 := gen_key_hash; + kh2 := gen_key_hash; + kh3 := gen_key_hash; + kh4 := gen_key_hash; + + + + Log("Initiating Test", INFO); + reset <= '1'; + wait until rising_edge(clk); + wait until rising_edge(clk); + reset <= '0'; + -- Stored CC: 0, 0, 0, 0 + + -- TEST: GET_MIN_SN/GET_MAX_SN ON EMPTY + + Log("RTPS Operation GET_MIN_SN (Expected SEQUENCENUMBER_UNKNOWN)", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_MIN_SN; + reference.cc.seq_nr := SEQUENCENUMBER_UNKNOWN; + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_MAX_SN (Expected SEQUENCENUMBER_UNKNOWN)", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_MAX_SN; + reference.cc.seq_nr := SEQUENCENUMBER_UNKNOWN; + start_ref; + wait_on_ref; + + -- TEST: WRITE ALIGNED PAYLOAD + -- TEST: NORMAL WRITE + -- TEST: ADD SAMPLE WITH KEY_HASH [UNKNOWN INSTANCE] + + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh1; + cc.payload := gen_payload(kh1,10); + cc.seq_nr := gen_sn(1); + cc.src_timestamp := gen_duration(1,0); + + Log("DDS Operation WRITE [TS 1s, Instance 1] (REJECTED: Instance not Registered)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_BAD_PARAMETER; + start_stim; + wait_on_stim; + + -- TEST: ADD SAMPLE WITH HANDLE_NIL [UNKNOWN INSTANCE] + + Log("DDS Operation WRITE [TS 1s, Instance 1, HANDLE_NIL] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.cc.instance:= HANDLE_NIL; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc1 := cc; + -- Stored CC: I1S1, 0, 0, 0 + + -- TEST: GET_MIN_SN/GET_MAX_SN ON 1 SAMPLE + + Log("RTPS Operation GET_MIN_SN (Expected SN 1)", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_MIN_SN; + reference.cc.seq_nr := gen_sn(1); + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_MAX_SN (Expected SN 1)", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_MAX_SN; + reference.cc.seq_nr := gen_sn(1); + start_ref; + wait_on_ref; + + -- TEST: WRITE UNALIGNED PAYLOAD [>1 SLOT] + + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh2; + cc.payload := gen_payload(kh2,12); + cc.seq_nr := gen_sn(2); + cc.src_timestamp := gen_duration(2,0); + + Log("DDS Operation WRITE [TS 2s, Instance 2, Unaligned Payload (2 Slots)] (REJECTED: Instance not Registered)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_BAD_PARAMETER; + start_stim; + wait_on_stim; + + -- TEST: NORMAL REGISTER + + Log("DDS Operation REGISTER_INSTANCE 2 (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := REGISTER_INSTANCE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + + -- TEST: ADD SAMPLE WITH KEY_HASH [KNOWN INSTANCE] + + Log("DDS Operation WRITE [TS 2s, Instance 2, Unaligned Payload (2 Slots)] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc2 := cc; + -- Stored CC: I1S1, I2S2, 0, 0 + + -- TEST: ADD SAMPLE WITH HANDLE_NIL [KNOWN INSTANCE] + + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh1; + cc.payload := gen_payload(kh1,15); + cc.seq_nr := gen_sn(3); + cc.src_timestamp := gen_duration(3,0); + + Log("DDS Operation WRITE [TS 3s, Instance 1, Unaligned Payload (2 Slots)] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.cc.instance:= HANDLE_NIL; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc3 := cc; + -- Stored CC: I1S1, I2S2, I1S3, 0 + + -- TEST: GET_CACHE_CHANGE [UNKNOWN SN] + + Log("RTPS Operation GET_CACHE_CHANGE SN 4 (Invalid)", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_CACHE_CHANGE; + reference.cc.seq_nr := gen_sn(4); + reference.ret_code := INVALID; + start_ref; + wait_on_ref; + + -- TEST: GET_CACHE_CHANGE [KNOWN SN, ALIGNED PAYLOAD] + + Log("RTPS Operation GET_CACHE_CHANGE SN 1", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_CACHE_CHANGE; + reference.cc := cc1; + start_ref; + wait_on_ref; + + -- TEST: GET_CACHE_CHANGE [KNOWN SN, UNALIGNED PAYLOAD, >1 SLOT] + + Log("RTPS Operation GET_CACHE_CHANGE SN 2", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_CACHE_CHANGE; + reference.cc := cc2; + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_CACHE_CHANGE SN 3", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_CACHE_CHANGE; + reference.cc := cc3; + start_ref; + wait_on_ref; + + -- TEST: WRITE UNALIGNED PAYLOAD [<1 SLOT] + + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh3; + cc.payload := gen_payload(kh3,8); + cc.seq_nr := gen_sn(4); + cc.src_timestamp := gen_duration(4,0); + + -- TEST: WRITE ON PAYLOAD MEMORY FULL [WITHOUT ACKed SAMPLES] + + Log("DDS Operation WRITE [TS 4s, Instance 3, HANDLE_NIL, Unaligned Payload (1 Slot)] (REJECTED: Payload Memory Full)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.cc.instance:= HANDLE_NIL; + stimulus.ret_code := RETCODE_OUT_OF_RESOURCES; + start_stim; + wait_on_stim; + -- Stored CC: I1S1, I2S2, I1S3, 0 + + -- TEST: REMOVE_CACHE_CHANGE [UNKNOWN SN] + + Log("RTPS Operation REMOVE_CACHE_CHANGE SN 5 (Invalid)", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := REMOVE_CACHE_CHANGE; + reference.cc.seq_nr := gen_sn(5); + reference.ret_code := INVALID; + start_ref; + wait_on_ref; + + -- TEST: REMOVE_CACHE_CHANGE [KNOWN SN] + + Log("RTPS Operation REMOVE_CACHE_CHANGE SN 2", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := REMOVE_CACHE_CHANGE; + reference.cc := cc2; + start_ref; + wait_on_ref; + -- Stored CC: I1S1, 0, I1S3, 0 + + Log("DDS Operation WRITE [TS 4s, Instance 3, HANDLE_NIL, Unaligned Payload (1 Slot)] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.cc.instance:= HANDLE_NIL; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc2 := cc; + -- Stored CC: I1S1, I3S4, I1S3, 0 + + -- TEST: GET_CACHE_CHANGE [KNOWN SN, UNALIGNED PAYLOAD, <1 SLOT] + + Log("RTPS Operation GET_CACHE_CHANGE SN 4", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_CACHE_CHANGE; + reference.cc := cc2; + start_ref; + wait_on_ref; + + -- TEST: REGISTER INSTANCE [KNOWN INSTANCE] + + Log("DDS Operation REGISTER_INSTANCE 3 (No Change)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := REGISTER_INSTANCE; + stimulus.cc := cc2; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + + -- TEST: NORMAL DISPOSE + + cc.serialized_key := TRUE; + cc.kind := NOT_ALIVE_DISPOSED; + cc.instance := kh1; + cc.payload := gen_payload(kh1,5); + cc.seq_nr := gen_sn(5); + cc.src_timestamp := gen_duration(5,0); + + -- TEST: ADD SAMPLE ON MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE, WITHOUT ACKed SAMPLES] + + Log("DDS Operation DISPOSE [TS 5s, Instance 1] (REJECTED: MAX_SAMPLES_PER_INSTANCE Exceeded)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := DISPOSE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OUT_OF_RESOURCES; + start_stim; + wait_on_stim; + + -- TEST: NORMAL ACK_CACHE_CHANGE + + Log("RTPS Operation ACK_CACHE_CHANGE SN 4", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := ACK_CACHE_CHANGE; + reference.cc := cc2; + start_ref; + wait_on_ref; + + -- TEST: ADD SAMPLE ON MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE, WITH ACKed SAMPLES, WITHOUT ACKed INSTANCE SAMPLES] + + Log("DDS Operation DISPOSE [TS 5s, Instance 1] (REJECTED: MAX_SAMPLES_PER_INSTANCE Exceeded)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := DISPOSE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OUT_OF_RESOURCES; + start_stim; + wait_on_stim; + + Log("RTPS Operation ACK_CACHE_CHANGE SN 1", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := ACK_CACHE_CHANGE; + reference.cc := cc1; + start_ref; + wait_on_ref; + + -- TEST: ADD SAMPLE ON MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE, WITH ACKed INSTANCE SAMPLE] + + Log("DDS Operation DISPOSE [TS 5s, Instance 1] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := DISPOSE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc1 := cc; + -- Stored CC: I1S5, I3S4, I1S3, 0 + + -- VALIDATE STATE + -- TEST: GET_MIN_SN/GET_MAX_SN ON >1 SAMPLE + + Log("RTPS Operation GET_MIN_SN (Expected SN 3)", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_MIN_SN; + reference.cc.seq_nr := gen_sn(3); + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_MAX_SN (Expected SN 5)", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_MAX_SN; + reference.cc.seq_nr := gen_sn(5); + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_CACHE_CHANGE SN 5", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_CACHE_CHANGE; + reference.cc := cc1; + start_ref; + wait_on_ref; + + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh4; + cc.payload := gen_payload(kh4,10); + cc.seq_nr := gen_sn(6); + cc.src_timestamp := gen_duration(6,0); + + -- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKNOWN INSTANCE, WITHOUT STALE INSTANCES] + + Log("DDS Operation WRITE [TS 6s, Instance 4, HANDLE_NIL, Aligned Payload] (REJECTED: MAX_INSTANCES exceeded)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.cc.instance:= HANDLE_NIL; + stimulus.ret_code := RETCODE_OUT_OF_RESOURCES; + start_stim; + wait_on_stim; + + Log("RTPS Operation ACK_CACHE_CHANGE SN 3", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := ACK_CACHE_CHANGE; + reference.cc := cc3; + start_ref; + wait_on_ref; + + -- TEST: ACK_CACHE_CHANGE [ALREADY ACKed SN] + + Log("RTPS Operation ACK_CACHE_CHANGE SN 4", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := ACK_CACHE_CHANGE; + reference.cc := cc2; + start_ref; + wait_on_ref; + + Log("RTPS Operation ACK_CACHE_CHANGE SN 5", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := ACK_CACHE_CHANGE; + reference.cc := cc1; + start_ref; + wait_on_ref; + + -- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKNOWN INSTANCE, WITH FULLY ACKed INSTANCE, WITHOUT STALE INSTANCE] + + Log("DDS Operation WRITE [TS 6s, Instance 4, HANDLE_NIL, Aligned Payload] (REJECTED: MAX_INSTANCES exceeded)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.cc.instance:= HANDLE_NIL; + stimulus.ret_code := RETCODE_OUT_OF_RESOURCES; + start_stim; + wait_on_stim; + + -- TEST: NORMAL UNREGISTER + + cc.serialized_key := TRUE; + cc.kind := NOT_ALIVE_UNREGISTERED; + cc.instance := kh1; + cc.payload := gen_payload(kh1,5); + cc.seq_nr := gen_sn(6); + cc.src_timestamp := gen_duration(6,0); + + -- TEST: UNREGISTER ON DISPOSED INSTANCE + + Log("DDS Operation UNREGISTER_INSTANCE [TS 6s, Instance 1] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := UNREGISTER_INSTANCE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc3 := cc; + -- Stored CC: I1S5, I3S4, I1S6, 0 + + -- VALIDATE STATE + + Log("RTPS Operation GET_MIN_SN (Expected SN 4)", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_MIN_SN; + reference.cc.seq_nr := gen_sn(4); + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_MAX_SN (Expected SN 6)", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_MAX_SN; + reference.cc.seq_nr := gen_sn(6); + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_CACHE_CHANGE SN 6", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_CACHE_CHANGE; + reference.cc := cc3; + start_ref; + wait_on_ref; + + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh4; + cc.payload := gen_payload(kh4,10); + cc.seq_nr := gen_sn(7); + cc.src_timestamp := gen_duration(7,0); + + Log("DDS Operation WRITE [TS 7s, Instance 4, HANDLE_NIL, Aligned Payload] (REJECTED: MAX_INSTANCES exceeded)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.cc.instance:= HANDLE_NIL; + stimulus.ret_code := RETCODE_OUT_OF_RESOURCES; + start_stim; + wait_on_stim; + + Log("RTPS Operation ACK_CACHE_CHANGE SN 6", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := ACK_CACHE_CHANGE; + reference.cc := cc3; + start_ref; + wait_on_ref; + + -- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKNOWN INSTANCE, WITH STALE INSTANCE] + -- TEST: REMOVE STALE INSTANCE WITH >1 SAMPLES + + Log("DDS Operation WRITE [TS 7s, Instance 4, HANDLE_NIL, Aligned Payload] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.cc.instance:= HANDLE_NIL; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc1 := cc; + -- Stored CC: I4S7, I3S4, 0, 0 + + Log("RTPS Operation GET_CACHE_CHANGE SN 5 (Invalid)", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_CACHE_CHANGE; + reference.cc.seq_nr := gen_sn(5); + reference.ret_code := INVALID; + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_CACHE_CHANGE SN 6 (Invalid)", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_CACHE_CHANGE; + reference.cc.seq_nr := gen_sn(6); + reference.ret_code := INVALID; + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_CACHE_CHANGE SN 7", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_CACHE_CHANGE; + reference.cc := cc1; + start_ref; + wait_on_ref; + + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh2; + cc.payload := gen_payload(kh2,15); + cc.seq_nr := gen_sn(8); + cc.src_timestamp := gen_duration(8,0); + + Log("DDS Operation WRITE [TS 8s, Instance 2, Unaligned Payload (2 Slot)] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc3 := cc; + -- Stored CC: I4S7, I3S4, I2S8, 0 + + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh1; + cc.payload := gen_payload(kh1,10); + cc.seq_nr := gen_sn(9); + cc.src_timestamp := gen_duration(9,0); + + Log("DDS Operation WRITE [TS 9s, Instance 1, Aligned Payload] (REJECTED: Instance not Registered)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_BAD_PARAMETER; + start_stim; + wait_on_stim; + + -- TEST: REGISTER INSTANCE ON MAX_INSTANCES [UNKNOWN INSTANCE, WITHOUT STALE INSTANCE] + + Log("DDS Operation REGISTER_INSTANCE 1 (REJECTED: MAX_INSTANCES exceeded)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := REGISTER_INSTANCE; + stimulus.cc := cc; + stimulus.cc.instance:= HANDLE_NIL; + start_stim; + wait_on_stim; + + cc.serialized_key := FALSE; + cc.kind := NOT_ALIVE_UNREGISTERED; + cc.instance := kh3; + cc.payload := gen_payload(kh3,5); + cc.seq_nr := gen_sn(9); + cc.src_timestamp := gen_duration(9,0); + + Log("DDS Operation UNREGISTER_INSTANCE [TS 9s, Instance 3] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := UNREGISTER_INSTANCE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc4 := cc; + -- Stored CC: I4S7, I3S4, I2S8, I3S9 + + -- VALIDATE STATE + + Log("RTPS Operation GET_MIN_SN (Expected SN 4)", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_MIN_SN; + reference.cc.seq_nr := gen_sn(4); + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_MAX_SN (Expected SN 9)", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_MAX_SN; + reference.cc.seq_nr := gen_sn(9); + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_CACHE_CHANGE SN 8", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_CACHE_CHANGE; + reference.cc := cc3; + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_CACHE_CHANGE SN 9", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_CACHE_CHANGE; + reference.cc := cc4; + start_ref; + wait_on_ref; + + Log("RTPS Operation ACK_CACHE_CHANGE SN 9", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := ACK_CACHE_CHANGE; + reference.cc := cc4; + start_ref; + wait_on_ref; + + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh1; + cc.payload := gen_payload(kh1,10); + cc.seq_nr := gen_sn(10); + cc.src_timestamp := gen_duration(10,0); + + -- TEST: REGISTER INSTANCE ON MAX_INSTANCES [UNKNOWN INSTANCE, WITH STALE INSTANCE] + + Log("DDS Operation REGISTER_INSTANCE 1 (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := REGISTER_INSTANCE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + + Log("DDS Operation WRITE [TS 10s, Instance 1, Aligned Payload] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc2 := cc; + -- Stored CC: I4S7, I1S10, I2S8, 0 + + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh4; + cc.payload := gen_payload(kh4,10); + cc.seq_nr := gen_sn(11); + cc.src_timestamp := gen_duration(11,0); + + Log("DDS Operation WRITE [TS 11s, Instance 1, Aligned Payload] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc4 := cc; + -- Stored CC: I4S7, I1S10, I2S8, I4S11 + + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh2; + cc.payload := gen_payload(kh2,10); + cc.seq_nr := gen_sn(12); + cc.src_timestamp := gen_duration(12,0); + + Log("DDS Operation WRITE [TS 12s, Instance 2, Aligned Payload] (REJECTED: Payload Memory Full)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OUT_OF_RESOURCES; + start_stim; + wait_on_stim; + + Log("RTPS Operation ACK_CACHE_CHANGE SN 8", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := ACK_CACHE_CHANGE; + reference.cc := cc3; + start_ref; + wait_on_ref; + + -- TEST: WRITE ON PAYLOAD MEMORY FULL [WITH ACKed SAMPLES] + + Log("DDS Operation WRITE [TS 12s, Instance 2, Aligned Payload] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc3 := cc; + -- Stored CC: I4S7, I1S10, I2S12, I4S11 + + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh4; + cc.payload := gen_payload(kh4,10); + cc.seq_nr := gen_sn(13); + cc.src_timestamp := gen_duration(13,0); + + -- TEST: ADD SAMPLE ON MAX_SAMPLES [KNOWN INSTANCE,WITHOUT ACKed SAMPLES] + + Log("DDS Operation WRITE [TS 13s, Instance 4, Aligned Payload] (REJECTED: MAX_SAMPLES exceeded)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OUT_OF_RESOURCES; + start_stim; + wait_on_stim; + + Log("RTPS Operation ACK_CACHE_CHANGE SN 7", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := ACK_CACHE_CHANGE; + reference.cc := cc1; + start_ref; + wait_on_ref; + + -- TEST: ADD SAMPLE ON MAX_SAMPLES [KNOWN INSTANCE,WITH ACKed SAMPLES] + + Log("DDS Operation WRITE [TS 13s, Instance 4, Aligned Payload] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc1 := cc; + -- Stored CC: I4S13, I1S10, I2S12, I4S11 + + -- VALIDATE STATE + + Log("RTPS Operation GET_MIN_SN (Expected SN 4)", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_MIN_SN; + reference.cc.seq_nr := gen_sn(10); + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_MAX_SN (Expected SN 9)", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_MAX_SN; + reference.cc.seq_nr := gen_sn(13); + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_CACHE_CHANGE SN 10", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_CACHE_CHANGE; + reference.cc := cc2; + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_CACHE_CHANGE SN 11", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_CACHE_CHANGE; + reference.cc := cc4; + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_CACHE_CHANGE SN 12", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_CACHE_CHANGE; + reference.cc := cc3; + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_CACHE_CHANGE SN 13", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_CACHE_CHANGE; + reference.cc := cc1; + start_ref; + wait_on_ref; + + Log("RTPS Operation ACK_CACHE_CHANGE SN 12", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := ACK_CACHE_CHANGE; + reference.cc := cc3; + start_ref; + wait_on_ref; + + cc.serialized_key := FALSE; + cc.kind := NOT_ALIVE_UNREGISTERED; + cc.instance := kh2; + cc.payload := gen_payload(kh2,5); + cc.seq_nr := gen_sn(14); + cc.src_timestamp := gen_duration(14,0); + + Log("DDS Operation UNREGISTER_INSTANCE [TS 14s, Instance 2] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := UNREGISTER_INSTANCE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc3 := cc; + -- Stored CC: I4S13, I1S10, I2S14, I4S11 + + Log("RTPS Operation ACK_CACHE_CHANGE SN 11", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := ACK_CACHE_CHANGE; + reference.cc := cc4; + start_ref; + wait_on_ref; + + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh4; + cc.payload := gen_payload(kh4,20); + cc.seq_nr := gen_sn(15); + cc.src_timestamp := gen_duration(15,0); + + -- TEST: ADD SAMPLE BIGGER THAN AVAILABLE MEMORY SPACE [WITH ACKed SAMPLES] + + Log("DDS Operation WRITE [TS 15s, Instance 4, Aligned Payload (2 Slots)] (REJECTED: Payload Memory Full)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OUT_OF_RESOURCES; + start_stim; + wait_on_stim; + + Log("RTPS Operation REMOVE_CACHE_CHANGE SN 11", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := REMOVE_CACHE_CHANGE; + reference.cc := cc4; + start_ref; + wait_on_ref; + -- Stored CC: I4S13, I1S10, I2S14, 0 + + Log("DDS Operation WRITE [TS 15s, Instance 4, Aligned Payload (2 Slots)] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc4 := cc; + -- Stored CC: I4S13, I1S10, I2S14, I4S15 + + -- TEST: UNREGISTER INSTANCE ON PAYLOAD MEMORY FULL [WITHOUT ACKed SAMPLES] + + cc.serialized_key := FALSE; + cc.kind := NOT_ALIVE_UNREGISTERED; + cc.instance := kh1; + cc.payload := gen_payload(kh1,5); + cc.seq_nr := gen_sn(16); + cc.src_timestamp := gen_duration(16,0); + + Log("DDS Operation UNREGISTER_INSTANCE [TS 16s, Instance 1] (REJECTED: Payload memory Full, MAX_SAMPLES exceeded)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := UNREGISTER_INSTANCE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OUT_OF_RESOURCES; + start_stim; + wait_on_stim; + + Log("RTPS Operation ACK_CACHE_CHANGE SN 10", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := ACK_CACHE_CHANGE; + reference.cc := cc2; + start_ref; + wait_on_ref; + + -- TEST: UNREGISTER INSTANCE ON PAYLOAD MEMORY FULL [WITH ACKed SAMPLES] + + Log("DDS Operation UNREGISTER_INSTANCE [TS 16s, Instance 1] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := UNREGISTER_INSTANCE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc2 := cc; + -- Stored CC: I4S13, I1S16, I2S14, I4S15 + + + cc.serialized_key := FALSE; + cc.kind := NOT_ALIVE_DISPOSED; + cc.instance := kh3; + cc.payload := gen_payload(kh3,5); + cc.seq_nr := gen_sn(17); + cc.src_timestamp := gen_duration(17,0); + + -- TEST: DISPOSE ON PAYLOAD MEMORY FULL [WITHOUT ACKed SAMPLES] + + Log("DDS Operation DISPOSE [TS 17s, Instance 3] (REJECTED: Payload memory Full, MAX_SAMPLES exceeded)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := DISPOSE; + stimulus.cc := cc; + stimulus.cc.instance:= HANDLE_NIL; + stimulus.ret_code := RETCODE_OUT_OF_RESOURCES; + start_stim; + wait_on_stim; + + Log("RTPS Operation ACK_CACHE_CHANGE SN 13", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := ACK_CACHE_CHANGE; + reference.cc := cc1; + start_ref; + wait_on_ref; + + Log("RTPS Operation ACK_CACHE_CHANGE SN 14", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := ACK_CACHE_CHANGE; + reference.cc := cc3; + start_ref; + wait_on_ref; + + -- TEST: DISPOSE ON PAYLOAD MEMORY FULL [WITH ACKed SAMPLES] + -- TEST: ADD SAMPLE ON PAYLOAD FULL & MAX_INSTANCES [UNKNOWN INSTANCE,WITH ACKed SAMPLES,WITH STALE INSTANCE (>= 1 SAMPLE)] (Induce Double Remove) + -- TEST: REMOVE STALE INSTANCE WITH 1 SAMPLES + + Log("DDS Operation DISPOSE [TS 17s, Instance 3] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := DISPOSE; + stimulus.cc := cc; + stimulus.cc.instance:= HANDLE_NIL; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc1 := cc; + -- Stored CC: I3S17, I1S16, 0, I4S15 + + -- VALIDATE STATE + + Log("RTPS Operation GET_MIN_SN (Expected SN 15)", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_MIN_SN; + reference.cc.seq_nr := gen_sn(15); + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_MAX_SN (Expected SN 17)", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_MAX_SN; + reference.cc.seq_nr := gen_sn(17); + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_CACHE_CHANGE SN 15", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_CACHE_CHANGE; + reference.cc := cc4; + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_CACHE_CHANGE SN 16", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_CACHE_CHANGE; + reference.cc := cc2; + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_CACHE_CHANGE SN 17", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_CACHE_CHANGE; + reference.cc := cc1; + start_ref; + wait_on_ref; + + Log("RTPS Operation REMOVE_CACHE_CHANGE SN 15", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := REMOVE_CACHE_CHANGE; + reference.cc := cc4; + start_ref; + wait_on_ref; + -- Stored CC: I3S17, I1S16, 0, 0 + + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh3; + cc.payload := gen_payload(kh3,10); + cc.seq_nr := gen_sn(18); + cc.src_timestamp := gen_duration(18,0); + + -- TEST: WRITE ON DISPOSED INSTANCE + + Log("DDS Operation WRITE [TS 18s, Instance 3, Aligned Payload] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc3 := cc; + -- Stored CC: I3S17, I1S16, I3S18, 0 + + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh4; + cc.payload := gen_payload(kh4,10); + cc.seq_nr := gen_sn(19); + cc.src_timestamp := gen_duration(19,0); + + Log("DDS Operation WRITE [TS 19s, Instance 4, Aligned Payload] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc4 := cc; + -- Stored CC: I3S17, I1S16, I3S18, I4S19 + + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh2; + cc.payload := gen_payload(kh2,10); + cc.seq_nr := gen_sn(20); + cc.src_timestamp := gen_duration(20,0); + + -- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE,WITHOUT STALE INSTANCES,WITHOUT ACKed SAMPLES] + + Log("DDS Operation WRITE [TS 20s, Instance 2, Aligned Payload] (REJECTED: MAX_SAMPLES exceeded, MAX_INSTANCES exceeded)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.cc.instance:= HANDLE_NIL; + stimulus.ret_code := RETCODE_OUT_OF_RESOURCES; + start_stim; + wait_on_stim; + + Log("RTPS Operation ACK_CACHE_CHANGE SN 16", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := ACK_CACHE_CHANGE; + reference.cc := cc2; + start_ref; + wait_on_ref; + + -- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE,WITH STALE INSTANCE (>0 SAMPLES)] + + Log("DDS Operation WRITE [TS 20s, Instance 2, Aligned Payload] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.cc.instance:= HANDLE_NIL; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc2 := cc; + -- Stored CC: I3S17, I2S20, I3S18, I4S19 + + Log("RTPS Operation ACK_CACHE_CHANGE SN 17", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := ACK_CACHE_CHANGE; + reference.cc := cc1; + start_ref; + wait_on_ref; + + cc.serialized_key := FALSE; + cc.kind := NOT_ALIVE_UNREGISTERED; + cc.instance := kh4; + cc.payload := gen_payload(kh4,5); + cc.seq_nr := gen_sn(21); + cc.src_timestamp := gen_duration(21,0); + + Log("DDS Operation UNREGISTER_INSTANCE [TS 21s, Instance 4] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := UNREGISTER_INSTANCE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc1 := cc; + -- Stored CC: I4S21, I2S20, I3S18, I4S19 + + Log("RTPS Operation ACK_CACHE_CHANGE SN 19", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := ACK_CACHE_CHANGE; + reference.cc := cc4; + start_ref; + wait_on_ref; + + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh1; + cc.payload := gen_payload(kh1,10); + cc.seq_nr := gen_sn(22); + cc.src_timestamp := gen_duration(22,0); + + -- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE,WITHOUT STALE INSTANCE, WITH ACKed SAMPLE] + + Log("DDS Operation WRITE [TS 22s, Instance 1, Aligned Payload] (REJECTED: MAX_SAMPLES exceeded, MAX_INSTANCES exceeded)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.cc.instance:= HANDLE_NIL; + stimulus.ret_code := RETCODE_OUT_OF_RESOURCES; + start_stim; + wait_on_stim; + + Log("RTPS Operation REMOVE_CACHE_CHANGE SN 19", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := REMOVE_CACHE_CHANGE; + reference.cc := cc4; + start_ref; + wait_on_ref; + -- Stored CC: I4S21, I2S20, I3S18, 0 + + Log("RTPS Operation REMOVE_CACHE_CHANGE SN 21", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := REMOVE_CACHE_CHANGE; + reference.cc := cc1; + start_ref; + wait_on_ref; + -- Stored CC: 0, I2S20, I3S18, 0 + + cc.serialized_key := FALSE; + cc.kind := NOT_ALIVE_UNREGISTERED; + cc.instance := kh2; + cc.payload := gen_payload(kh2,5); + cc.seq_nr := gen_sn(22); + cc.src_timestamp := gen_duration(22,0); + + Log("DDS Operation UNREGISTER_INSTANCE [TS 22s, Instance 2] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := UNREGISTER_INSTANCE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc1 := cc; + -- Stored CC: I2S22, I2S20, I3S18, 0 + + cc.serialized_key := FALSE; + cc.kind := NOT_ALIVE_UNREGISTERED; + cc.instance := kh3; + cc.payload := gen_payload(kh3,5); + cc.seq_nr := gen_sn(23); + cc.src_timestamp := gen_duration(23,0); + + Log("DDS Operation UNREGISTER_INSTANCE [TS 23s, Instance 3] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := UNREGISTER_INSTANCE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc4 := cc; + -- Stored CC: I2S22, I2S20, I3S18, I3S23 + + -- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE,WITH STALE INSTANCE, WITHOUT ACKed SAMPLE] + + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh1; + cc.payload := gen_payload(kh1,10); + cc.seq_nr := gen_sn(24); + cc.src_timestamp := gen_duration(24,0); + + Log("DDS Operation WRITE [TS 24s, Instance 1, Aligned Payload] (REJECTED: MAX_SAMPLES exceeded, MAX_INSTANCES exceeded)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.cc.instance:= HANDLE_NIL; + stimulus.ret_code := RETCODE_OUT_OF_RESOURCES; + start_stim; + wait_on_stim; + + Log("RTPS Operation ACK_CACHE_CHANGE SN 20", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := ACK_CACHE_CHANGE; + reference.cc := cc2; + start_ref; + wait_on_ref; + + -- TEST: REMOVE STALE INSTANCE WITH 0 SAMPLES + -- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE,WITH STALE INSTANCE, WITH ACKed SAMPLE] + + Log("DDS Operation WRITE [TS 24s, Instance 1, Aligned Payload] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.cc.instance:= HANDLE_NIL; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc2 := cc; + -- Stored CC: I2S22, I1S24, I3S18, I3S23 + + Log("RTPS Operation ACK_CACHE_CHANGE SN 22", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := ACK_CACHE_CHANGE; + reference.cc := cc1; + start_ref; + wait_on_ref; + + -- TEST: NORMAL NACK_CACHE_CHANGE + + Log("RTPS Operation NACK_CACHE_CHANGE SN 22", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := NACK_CACHE_CHANGE; + reference.cc := cc1; + start_ref; + wait_on_ref; + + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh4; + cc.payload := gen_payload(kh4,10); + cc.seq_nr := gen_sn(25); + cc.src_timestamp := gen_duration(25,0); + + Log("DDS Operation REGISTER_INSTANCE 4 (REJECTED: MAX_INSTANCES exceeded)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := REGISTER_INSTANCE; + stimulus.cc := cc; + stimulus.cc.instance:= HANDLE_NIL; + start_stim; + wait_on_stim; + + Log("RTPS Operation ACK_CACHE_CHANGE SN 22", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := ACK_CACHE_CHANGE; + reference.cc := cc1; + start_ref; + wait_on_ref; + + -- TEST: REGISTER ON UNREGISTERED INSTANCE + + Log("DDS Operation REGISTER_INSTANCE 2 (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := REGISTER_INSTANCE; + stimulus.cc := cc1; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + + Log("DDS Operation REGISTER_INSTANCE 4 (REJECTED: MAX_INSTANCES exceeded)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := REGISTER_INSTANCE; + stimulus.cc := cc; + stimulus.cc.instance:= HANDLE_NIL; + start_stim; + wait_on_stim; + + Log("RTPS Operation ACK_CACHE_CHANGE SN 18", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := ACK_CACHE_CHANGE; + reference.cc := cc3; + start_ref; + wait_on_ref; + + Log("RTPS Operation ACK_CACHE_CHANGE SN 23", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := ACK_CACHE_CHANGE; + reference.cc := cc4; + start_ref; + wait_on_ref; + + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh3; + cc.payload := gen_payload(kh3,10); + cc.seq_nr := gen_sn(25); + cc.src_timestamp := gen_duration(25,0); + + -- TEST: WRITE ON UNREGISTERED INSTANCE + + Log("DDS Operation WRITE [TS 25s, Instance 3, Aligned Payload] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.cc.instance:= HANDLE_NIL; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc3 := cc; + -- Stored CC: I2S22, I1S24, I3S25, I3S23 + + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh4; + cc.payload := gen_payload(kh4,10); + cc.seq_nr := gen_sn(26); + cc.src_timestamp := gen_duration(26,0); + + Log("DDS Operation REGISTER_INSTANCE 4 (REJECTED: MAX_INSTANCES exceeded)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := REGISTER_INSTANCE; + stimulus.cc := cc; + stimulus.cc.instance:= HANDLE_NIL; + start_stim; + wait_on_stim; + + cc.serialized_key := FALSE; + cc.kind := NOT_ALIVE_UNREGISTERED; + cc.instance := kh4; + cc.payload := gen_payload(kh4,5); + cc.seq_nr := gen_sn(26); + cc.src_timestamp := gen_duration(26,0); + + -- TEST: UNREGISTER UNKNOWN INSTANCE + + Log("DDS Operation UNREGISTER_INSTANCE [TS 26s, HANDLE_NIL, Instance 4] (IGNORED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := UNREGISTER_INSTANCE; + stimulus.cc := cc; + stimulus.cc.instance:= HANDLE_NIL; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + + Log("RTPS Operation NACK_CACHE_CHANGE SN 22", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := NACK_CACHE_CHANGE; + reference.cc := cc1; + start_ref; + wait_on_ref; + + Log("RTPS Operation NACK_CACHE_CHANGE SN 23", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := NACK_CACHE_CHANGE; + reference.cc := cc4; + start_ref; + wait_on_ref; + + cc.serialized_key := TRUE; + cc.kind := NOT_ALIVE_UNREGISTERED; + cc.instance := kh3; + cc.payload := gen_payload(kh3,5); + cc.seq_nr := gen_sn(26); + cc.src_timestamp := gen_duration(26,0); + + -- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE,WITHOUT ACKed SAMPLES] + + Log("DDS Operation UNREGISTER_INSTANCE [TS 26s, Instance 3] (REJECTED: MAX_SAMPLES_PER_INSTANCE exceeded, MAX_SAMPLES exceeded)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := UNREGISTER_INSTANCE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OUT_OF_RESOURCES; + start_stim; + wait_on_stim; + + Log("RTPS Operation ACK_CACHE_CHANGE SN 22", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := ACK_CACHE_CHANGE; + reference.cc := cc1; + start_ref; + wait_on_ref; + + -- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE,WITH ACKed SAMPLES, WITHOUT ACKed INSTANCE SAMPLES] + + Log("DDS Operation UNREGISTER_INSTANCE [TS 26s, Instance 3] (REJECTED: MAX_SAMPLES_PER_INSTANCE exceeded, MAX_SAMPLES exceeded)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := UNREGISTER_INSTANCE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OUT_OF_RESOURCES; + start_stim; + wait_on_stim; + + Log("RTPS Operation ACK_CACHE_CHANGE SN 23", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := ACK_CACHE_CHANGE; + reference.cc := cc4; + start_ref; + wait_on_ref; + + -- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE,WITH ACKed INSTANCE SAMPLES] + + Log("DDS Operation UNREGISTER_INSTANCE [TS 26s, Instance 3] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := UNREGISTER_INSTANCE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc4 := cc; + -- Stored CC: I2S22, I1S24, I3S25, I3S26 + + Log("RTPS Operation ACK_CACHE_CHANGE SN 25", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := ACK_CACHE_CHANGE; + reference.cc := cc3; + start_ref; + wait_on_ref; + + cc.serialized_key := TRUE; + cc.kind := NOT_ALIVE_DISPOSED; + cc.instance := kh3; + cc.payload := gen_payload(kh3,5); + cc.seq_nr := gen_sn(27); + cc.src_timestamp := gen_duration(27,0); + + -- TEST: DISPOSE ON UNREGISTERED INSTANCE + + Log("DDS Operation DISPOSE [TS 27s, Instance 3] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := DISPOSE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc3 := cc; + -- Stored CC: I2S22, I1S24, I3S27, I3S26 + + Log("RTPS Operation ACK_CACHE_CHANGE SN 26", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := ACK_CACHE_CHANGE; + reference.cc := cc4; + start_ref; + wait_on_ref; + + Log("RTPS Operation ACK_CACHE_CHANGE SN 27", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := ACK_CACHE_CHANGE; + reference.cc := cc3; + start_ref; + wait_on_ref; + + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh4; + cc.payload := gen_payload(kh4,10); + cc.seq_nr := gen_sn(28); + cc.src_timestamp := gen_duration(28,0); + + Log("DDS Operation REGISTER_INSTANCE 4 (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := REGISTER_INSTANCE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + -- Stored CC: I2S22, I1S24, 0, 0 + + -- VALIDATE STATE + + Log("RTPS Operation GET_MIN_SN (Expected SN 22)", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_MIN_SN; + reference.cc.seq_nr := gen_sn(22); + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_MAX_SN (Expected SN 24)", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_MAX_SN; + reference.cc.seq_nr := gen_sn(24); + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_CACHE_CHANGE SN 22", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_CACHE_CHANGE; + reference.cc := cc1; + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_CACHE_CHANGE SN 24", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_CACHE_CHANGE; + reference.cc := cc2; + start_ref; + wait_on_ref; + + Log("RTPS Operation NACK_CACHE_CHANGE SN 22", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := NACK_CACHE_CHANGE; + reference.cc := cc1; + start_ref; + wait_on_ref; + + Log("RTPS Operation NACK_CACHE_CHANGE SN 24", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := NACK_CACHE_CHANGE; + reference.cc := cc2; + start_ref; + wait_on_ref; + + Log("DDS Operation WRITE [TS 28s, Instance 4, Aligned Payload] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc3 := cc; + -- Stored CC: I2S22, I1S24, I4S28, 0 + + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh2; + cc.payload := gen_payload(kh2,10); + cc.seq_nr := gen_sn(29); + cc.src_timestamp := gen_duration(29,0); + + Log("DDS Operation WRITE [TS 29s, Instance 2, Aligned Payload] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc4 := cc; + -- Stored CC: I2S22, I1S24, I4S28, I2S29 + + Log("RTPS Operation ACK_CACHE_CHANGE SN 24", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := ACK_CACHE_CHANGE; + reference.cc := cc2; + start_ref; + wait_on_ref; + + Log("RTPS Operation ACK_CACHE_CHANGE SN 28", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := ACK_CACHE_CHANGE; + reference.cc := cc3; + start_ref; + wait_on_ref; + + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh1; + cc.payload := gen_payload(kh1,10); + cc.seq_nr := gen_sn(30); + cc.src_timestamp := gen_duration(30,0); + + -- TEST: ADD SAMPLE ON MAX_SAMPLES [KNOWN INSTANCE,WITH ACKed SAMPLES (>1)] + + Log("DDS Operation WRITE [TS 30s, Instance 1, Aligned Payload] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc2 := cc; + -- Stored CC: I2S22, I1S30, I4S28, I2S29 + + Log("RTPS Operation REMOVE_CACHE_CHANGE SN 28", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := REMOVE_CACHE_CHANGE; + reference.cc := cc3; + start_ref; + wait_on_ref; + -- Stored CC: I2S22, I1S30, 0, I2S29 + + Log("RTPS Operation ACK_CACHE_CHANGE SN 22", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := ACK_CACHE_CHANGE; + reference.cc := cc1; + start_ref; + wait_on_ref; + + Log("RTPS Operation ACK_CACHE_CHANGE SN 29", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := ACK_CACHE_CHANGE; + reference.cc := cc4; + start_ref; + wait_on_ref; + + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh2; + cc.payload := gen_payload(kh2,10); + cc.seq_nr := gen_sn(31); + cc.src_timestamp := gen_duration(31,0); + + -- TEST: ADD SAMPLE ON MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE, WITH ACKed INSTANCE SAMPLES(>1)] + + Log("DDS Operation WRITE [TS 31s, Instance 2, Aligned Payload] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc1 := cc; + -- Stored CC: I2S31, I1S30, 0, I2S29 + + -- VALIDATE STATE + + Log("RTPS Operation GET_MIN_SN (Expected SN 29)", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_MIN_SN; + reference.cc.seq_nr := gen_sn(29); + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_MAX_SN (Expected SN 31)", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_MAX_SN; + reference.cc.seq_nr := gen_sn(31); + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_CACHE_CHANGE SN 29", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_CACHE_CHANGE; + reference.cc := cc4; + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_CACHE_CHANGE SN 30", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_CACHE_CHANGE; + reference.cc := cc2; + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_CACHE_CHANGE SN 31", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_CACHE_CHANGE; + reference.cc := cc1; + start_ref; + wait_on_ref; + + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh1; + cc.payload := gen_payload(kh1,10); + cc.seq_nr := gen_sn(1); + cc.src_timestamp := gen_duration(1,0); + + -- TEST: INSTANCE LOOKUP [KNOWN INSTANCE] + + Log("DDS Operation LOOKUP_INSTANCE [Instance 1]", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := LOOKUP_INSTANCE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh3; + cc.payload := gen_payload(kh3,10); + cc.seq_nr := gen_sn(1); + cc.src_timestamp := gen_duration(1,0); + + -- TEST: INSTANCE LOOKUP [UNKNOWN INSTANCE] + + Log("DDS Operation LOOKUP_INSTANCE [Unknown Instance]", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := LOOKUP_INSTANCE; + stimulus.cc := cc; + stimulus.cc.instance:= HANDLE_NIL; + start_stim; + wait_on_stim; + + wait_on_completion; + TranscriptOpen(RESULTS_FILE, APPEND_MODE); + SetTranscriptMirror; + ReportAlerts; + TranscriptClose; + std.env.stop; + wait; + end process; + + clock_prc : process + begin + clk <= '0'; + wait for 25 ns; + clk <= '1'; + wait for 25 ns; + end process; + + alert_prc : process(all) + begin + if rising_edge(clk) then + -- TODO + end if; + end process; + + stim_prc : process(all) + begin + if rising_edge(clk) then + stim_done <= '0'; + case (stim_stage) is + when IDLE => + if (stim_start = '1') then + stim_stage <= START; + else + stim_done <= '1'; + end if; + when START => + if (ack_dds = '1') then + stim_stage <= PUSH; + stim_cnt <= 0; + end if; + when PUSH => + if (ready_in_dds = '1') then + stim_cnt <= stim_cnt + 1; + if (stim_cnt = stimulus.cc.payload.length-1) then + -- DEFAULT + stim_stage <= DONE; + + case (stimulus.opcode) is + when REGISTER_INSTANCE => + stim_stage <= CHECK; + stim_cnt <= 0; + when LOOKUP_INSTANCE => + stim_stage <= CHECK; + stim_cnt <= 0; + when others => + null; + end case; + end if; + end if; + when DONE => + if (done_dds = '1') then + AffirmIfEqual(ret_id, return_code_dds, stimulus.ret_code); + stim_stage <= IDLE; + end if; + when CHECK => + if (valid_out_dds = '1') then + AffirmIfEqual(data_id, data_out_dds, stimulus.cc.instance(stim_cnt)); + stim_cnt <= stim_cnt + 1; + if (stim_cnt = 3) then + AlertIf(data_id, last_word_out_dds /= '1', "Last Word Signal not pulled High", ERROR); + stim_stage <= IDLE; + end if; + end if; + end case; + end if; + + -- DEFAULT + start_dds <= '0'; + valid_in_dds <= '0'; + last_word_in_dds <= '0'; + data_in_dds <= (others => '0'); + instance_handle_dds <= HANDLE_NIL; + source_ts_dds <= TIME_INVALID; + ready_out_dds <= '0'; + + case (stim_stage) is + when START => + start_dds <= '1'; + opcode_dds <= stimulus.opcode; + instance_handle_dds <= stimulus.cc.instance; + source_ts_dds <= stimulus.cc.src_timestamp; + when PUSH => + valid_in_dds <= '1'; + data_in_dds <= stimulus.cc.payload.data(stim_cnt); + last_word_in_dds <= stimulus.cc.payload.last(stim_cnt); + when CHECK => + ready_out_dds <= '1'; + when others => + null; + end case; + end process; + + ref_prc : process(all) + begin + if rising_edge(clk) then + ref_done <= '0'; + case (ref_stage) is + when IDLE => + if (ref_start = '1') then + ref_stage <= START; + else + ref_done <= '1'; + end if; + when START => + if (ack_rtps = '1') then + ref_stage <= DONE; + end if; + when DONE => + if (done_rtps = '1') then + -- DEFAULT + ref_stage <= IDLE; + + AffirmIfEqual(ret_id, HISTORY_CACHE_RESPONSE_TYPE'pos(ret_rtps), HISTORY_CACHE_RESPONSE_TYPE'pos(reference.ret_code)); + case (reference.opcode) is + when GET_CACHE_CHANGE => + if (reference.ret_code = OK) then + AffirmIfEqual(inst_id, cc_instance_handle(0), reference.cc.instance(0)); + AffirmIfEqual(inst_id, cc_instance_handle(1), reference.cc.instance(1)); + AffirmIfEqual(inst_id, cc_instance_handle(2), reference.cc.instance(2)); + AffirmIfEqual(inst_id, cc_instance_handle(3), reference.cc.instance(3)); + AffirmIfEqual(kind_id, CACHE_CHANGE_KIND_TYPE'pos(cc_kind), CACHE_CHANGE_KIND_TYPE'pos(reference.cc.kind)); + AffirmIfEqual(sn_id, convert_from_double_word(cc_seq_nr), convert_from_double_word(reference.cc.seq_nr)); + AffirmIfEqual(ts_id, convert_from_double_word(cc_source_timestamp), convert_from_double_word(reference.cc.src_timestamp)); + ref_stage <= CHECK; + ref_cnt <= 0; + end if; + when GET_MIN_SN => + AffirmIfEqual(sn_id, convert_from_double_word(cc_seq_nr), convert_from_double_word(reference.cc.seq_nr)); + when GET_MAX_SN => + AffirmIfEqual(sn_id, convert_from_double_word(cc_seq_nr), convert_from_double_word(reference.cc.seq_nr)); + when others => + null; + end case; + end if; + when CHECK => + if (valid_out_rtps = '1') then + AffirmIfEqual(data_id, last_word_out_rtps & data_out_rtps, reference.cc.payload.last(ref_cnt) & reference.cc.payload.data(ref_cnt)); + ref_cnt <= ref_cnt + 1; + if (ref_cnt = reference.cc.payload.length-1) then + ref_stage <= IDLE; + end if; + end if; + end case; + end if; + + -- DEFAULT + start_rtps <= '0'; + get_data_rtps <= '0'; + ready_out_rtps <= '0'; + + case (ref_stage) is + when START => + start_rtps <= '1'; + opcode_rtps <= reference.opcode; + seq_nr_rtps <= reference.cc.seq_nr; + when DONE => + if (done_rtps = '1') then + case (reference.opcode) is + when GET_CACHE_CHANGE => + get_data_rtps <= '1'; + when others => + null; + end case; + end if; + when CHECK => + ready_out_rtps <= '1'; + when others => + null; + end case; + end process; + + kh_prc : process (all) + variable tmp_key_hash : INSTANCE_HANDLE_TYPE := HANDLE_NIL; + begin + if rising_edge(clk) then + case (kh_stage) is + when IDLE => + if (start_kh = '1') then + case (opcode_kh) is + when PUSH_DATA => + kh_stage <= READ_DATA; + kh_cnt <= 0; + kh_data <= EMPTY_TEST_PACKET; + when PUSH_SERIALIZED_KEY => + kh_stage <= READ_DATA; + kh_cnt <= 0; + kh_data <= EMPTY_TEST_PACKET; + when READ_KEY_HASH => + kh_stage <= PUSH_KEY_HASH; + kh_cnt <= 0; + when others => + Alert("Unexpected Key Holder Operation", FAILURE); + end case; + end if; + when READ_DATA => + if (valid_out_kh = '1') then + kh_data.data(kh_cnt) <= data_out_kh; + kh_data.last(kh_cnt) <= last_word_out_kh; + kh_data.length <= kh_data.length + 1; + + kh_cnt <= kh_cnt + 1; + if (last_word_out_kh = '1') then + kh_stage <= IDLE; + end if; + end if; + when PUSH_KEY_HASH => + if (ready_in_kh = '1') then + kh_cnt <= kh_cnt + 1; + if (kh_cnt = INSTANCE_HANDLE_TYPE'length-1) then + kh_stage <= IDLE; + end if; + end if; + end case; + end if; + + -- DEFAULT + ack_kh <= '0'; + ready_out_kh <= '0'; + valid_in_kh <= '0'; + data_in_kh <= (others => '0'); + last_word_in_kh <= '0'; + + case (kh_stage) is + when IDLE => + if (start_kh = '1') then + ack_kh <= '1'; + end if; + when READ_DATA => + ready_out_kh <= '1'; + when PUSH_KEY_HASH => + valid_in_kh <= '1'; + tmp_key_hash := extract_key_hash(kh_data); + data_in_kh <= tmp_key_hash(kh_cnt); + if (kh_cnt = INSTANCE_HANDLE_TYPE'length-1) then + last_word_in_kh <= '1'; + end if; + end case; + end process; + + watchdog : process + begin + wait for 1 ms; + Alert("Test timeout", FAILURE); + std.env.stop; + end process; + +end architecture; \ No newline at end of file diff --git a/src/Tests/Level_0/L0_dds_writer_test1_ain.txt b/src/Tests/Level_0/L0_dds_writer_test1_ain.txt new file mode 100644 index 0000000..00e05a4 --- /dev/null +++ b/src/Tests/Level_0/L0_dds_writer_test1_ain.txt @@ -0,0 +1,69 @@ + SAMPLE MEMORY: -/0,8,16,24,32 + PAYLOAD MEMORY: -/0,11,22,33,44 +RTPS Operation GET_MIN_SN (Expected SEQUENCENUMBER_UNKNOWN) +RTPS Operation GET_MAX_SN (Expected SEQUENCENUMBER_UNKNOWN) +DDS Operation WRITE [TS 1s, Aligned Payload] (ACCEPTED) + SAMPLE MEMORY: 0(S1)/8,16,24,32 + PAYLOAD MEMORY: 0(S1)/11,22,33,44 +DDS Operation WRITE [TS 2s, Unaligned Payload (2 Slots)] (ACCEPTED) + SAMPLE MEMORY: 0(S1),8(S2)/16,24,32 + PAYLOAD MEMORY: 0(S1),11(S2),22(S2)/33,44 +DDS Operation REGISTER_INSTANCE 2 (Illegal Operation) +DDS Operation DISPOSE [TS 3s] (ACCEPTED) + SAMPLE MEMORY: 0(S1),8(S2),16(S3)/24,32 + PAYLOAD MEMORY: 0(S1),11(S2),22(S2),33(S3)/44 +RTPS Operation GET_MIN_SN (Expected SN 1) +RTPS Operation GET_MAX_SN (Expected SN 3) +RTPS Operation GET_CACHE_CHANGE SN 4 (Invalid) +RTPS Operation GET_CACHE_CHANGE SN 1 +RTPS Operation GET_CACHE_CHANGE SN 2 +RTPS Operation GET_CACHE_CHANGE SN 3 +DDS Operation WRITE [TS 2s, Aligned Payload] (ACCEPTED) + SAMPLE MEMORY: 0(S1),8(S2),16(S3),24(S4)/32 + PAYLOAD MEMORY: 0(S1),11(S2),22(S2),33(S3),44(S4)/- +DDS Operation UNREGISTER_INSTANCE [TS 5s] (REJECTED: Payload Memory Full) +RTPS Operation ACK_CACHE_CHANGE SN 1 +DDS Operation UNREGISTER_INSTANCE [TS 5s] (ACCEPTED) + SAMPLE MEMORY: 8(S2),16(S3),24(S4),32(S5)/0 + PAYLOAD MEMORY: 11(S2),22(S2),33(S3),44(S4),0(S5)/- +DDS Operation WRITE [TS 6s, Aligned Payload] (REJECTED: Payload Memory Full) +RTPS Operation ACK_CACHE_CHANGE SN 2 +RTPS Operation ACK_CACHE_CHANGE SN 3 +RTPS Operation NACK_CACHE_CHANGE SN 2 +DDS Operation WRITE [TS 6s, Aligned Payload] (ACCEPTED) + SAMPLE MEMORY: 8(S2),24(S4),32(S5),0(S6)/16 + PAYLOAD MEMORY: 11(S2),22(S2),44(S4),0(S5),33(S6)/- +DDS Operation DISPOSE [TS 7s] (REJECTED: Payload Memory Full) +RTPS Operation ACK_CACHE_CHANGE SN 2 +RTPS Operation ACK_CACHE_CHANGE SN 2 +DDS Operation DISPOSE [TS 7s] (ACCEPTED) + SAMPLE MEMORY: 24(S4),32(S5),0(S6),16(S7)/8 + PAYLOAD MEMORY: 44(S4),0(S5),33(S6),11(S7)/22 +DDS Operation UNREGISTER_INSTANCE [TS 8s] (REJECTED: MAX_SAMPLES exceeded) +RTPS Operation ACK_CACHE_CHANGE SN 5 +DDS Operation UNREGISTER_INSTANCE [TS 8s] (ACCEPTED) + SAMPLE MEMORY: 24(S4),0(S6),16(S7),8(S8)/32 + PAYLOAD MEMORY: 44(S4),33(S6),11(S7),22(S8)/0 +RTPS Operation GET_MIN_SN (Expected SN 4) +RTPS Operation GET_MAX_SN (Expected SN 8) +RTPS Operation GET_CACHE_CHANGE SN 4 +RTPS Operation GET_CACHE_CHANGE SN 6 +RTPS Operation GET_CACHE_CHANGE SN 7 +RTPS Operation GET_CACHE_CHANGE SN 8 +RTPS Operation ACK_CACHE_CHANGE SN 6 +RTPS Operation ACK_CACHE_CHANGE SN 8 +DDS Operation DISPOSE [TS 9s] (ACCEPTED) + SAMPLE MEMORY: 24(S4),16(S7),8(S8),32(S9)/0 + PAYLOAD MEMORY: 44(S4),11(S7),22(S8),0(S9)/33 +DDS Operation UNREGISTER_INSTANCE [TS 10s] (ACCEPTED) + SAMPLE MEMORY: 24(S4),16(S7),32(S9),0(S10)/8 + PAYLOAD MEMORY: 44(S4),11(S7),0(S9),33(S10)/22 +RTPS Operation ACK_CACHE_CHANGE SN 7 +DDS Operation WRITE [TS 11s, Aligned Payload (2 Slots)] (REJECTED: Payload Memory Full) +RTPS Operation REMOVE_CACHE_CHANGE SN 12 (Invalid) +RTPS Operation REMOVE_CACHE_CHANGE SN 4 + SAMPLE MEMORY: 16(S7),32(S9),0(S10)/8,24 + PAYLOAD MEMORY: 11(S7),0(S9),33(S10)/44,22 +DDS Operation WRITE [TS 11s, Aligned Payload (2 Slots)] (ACCEPTED) + SAMPLE MEMORY: 16(S7),32(S9),0(S10),8(S11)/24 + PAYLOAD MEMORY: 11(S7),0(S9),33(S10),44(S11),22(S11)/- diff --git a/src/Tests/Level_0/L0_dds_writer_test1_ain.vhd b/src/Tests/Level_0/L0_dds_writer_test1_ain.vhd new file mode 100644 index 0000000..756b469 --- /dev/null +++ b/src/Tests/Level_0/L0_dds_writer_test1_ain.vhd @@ -0,0 +1,1134 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library osvvm; -- Utility Library +context osvvm.OsvvmContext; + +use work.rtps_package.all; +use work.user_config.all; +use work.rtps_config_package.all; +use work.rtps_test_package.all; + +-- This testbench tests the General Operation of the DDS Writer. It tests the correctness of the RTPS +-- GET_MIN_SN, GET_MAX_SN, GET_CACHE_CHANGE, REMOVE_CACHE_CHANGE, ACK_CACHE_CHANGE, and NACK_CACHE_CHANGE Operations and the +-- DDS REGISTER_INSTANCE, UNREGISTER_INSTANCE, WRITE, DISPOSE, and LOOKUP_INSTANCE Operations. +-- More specifically the testbench covers following tests: +-- TEST: GET_MIN_SN/GET_MAX_SN ON EMPTY +-- TEST: GET_MIN_SN/GET_MAX_SN ON 1 SAMPLE +-- TEST: GET_MIN_SN/GET_MAX_SN ON >1 SAMPLE +-- TEST: ADD SAMPLE WITH KEY_HASH +-- TEST: ADD SAMPLE WITH HANDLE_NIL +-- TEST: NORMAL WRITE +-- TEST: WRITE ON PAYLOAD MEMORY FULL [WITHOUT ACKed SAMPLES] +-- TEST: WRITE ON PAYLOAD MEMORY FULL [WITH ACKed SAMPLES] +-- TEST: WRITE ON DISPOSED INSTANCE +-- TEST: WRITE ON UNREGISTERED INSTANCE +-- TEST: WRITE ALIGNED PAYLOAD +-- TEST: WRITE UNALIGNED PAYLOAD [>1 SLOT] +-- TEST: WRITE UNALIGNED PAYLOAD [<1 SLOT] +-- TEST: NORMAL REGISTER +-- TEST: NORMAL DISPOSE +-- TEST: DISPOSE ON PAYLOAD MEMORY FULL [WITHOUT ACKed SAMPLES] +-- TEST: DISPOSE ON PAYLOAD MEMORY FULL [WITH ACKed SAMPLES] +-- TEST: DISPOSE ON UNREGISTERED INSTANCE +-- TEST: GET_CACHE_CHANGE [UNKNOWN SN] +-- TEST: GET_CACHE_CHANGE [KNOWN SN, ALIGNED PAYLOAD] +-- TEST: GET_CACHE_CHANGE [KNOWN SN, UNALIGNED PAYLOAD, >1 SLOT] +-- TEST: GET_CACHE_CHANGE [KNOWN SN, UNALIGNED PAYLOAD, <1 SLOT] +-- TEST: NORMAL ACK_CACHE_CHANGE +-- TEST: ACK_CACHE_CHANGE [ALREADY ACKed SN] +-- TEST: NORMAL NACK_CACHE_CHANGE +-- TEST: REMOVE_CACHE_CHANGE [UNKNOWN SN] +-- TEST: REMOVE_CACHE_CHANGE [KNOWN SN] +-- TEST: NORMAL UNREGISTER +-- TEST: UNREGISTER INSTANCE ON PAYLOAD MEMORY FULL [WITHOUT ACKed SAMPLES] +-- TEST: UNREGISTER INSTANCE ON PAYLOAD MEMORY FULL [WITH ACKed SAMPLES] +-- TEST: UNREGISTER ON DISPOSED INSTANCE +-- TEST: UNREGISTER UNKNOWN INSTANCE +-- TEST: ADD SAMPLE ON MAX_SAMPLES_PER_INSTANCE [WITHOUT ACKed SAMPLES] +-- TEST: ADD SAMPLE ON MAX_SAMPLES_PER_INSTANCE [WITH ACKed SAMPLES, WITHOUT ACKed INSTANCE SAMPLES] +-- TEST: ADD SAMPLE ON MAX_SAMPLES_PER_INSTANCE [WITH ACKed INSTANCE SAMPLE] +-- TEST: ADD SAMPLE ON MAX_SAMPLES_PER_INSTANCE [WITH ACKed INSTANCE SAMPLES(>1)] +-- TEST: ADD SAMPLE ON MAX_SAMPLES [KNOWN INSTANCE,WITHOUT ACKed SAMPLES] +-- TEST: ADD SAMPLE ON MAX_SAMPLES [WITH ACKed SAMPLE] +-- TEST: ADD SAMPLE ON MAX_SAMPLES [WITH ACKed SAMPLES (>1)] +-- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_SAMPLES_PER_INSTANCE [WITHOUT ACKed SAMPLES] +-- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_SAMPLES_PER_INSTANCE [WITH ACKed SAMPLES, WITHOUT ACKed INSTANCE SAMPLES] +-- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_SAMPLES_PER_INSTANCE [WITH ACKed INSTANCE SAMPLES] +-- TEST: ADD SAMPLE BIGGER THAN AVAILABLE MEMORY SPACE [WITH ACKed SAMPLES] +-- TEST: INSTANCE LOOKUP + +entity L0_dds_writer_test1_ain is +end entity; + +architecture testbench of L0_dds_writer_test1_ain is + + -- *CONSTANT DECLARATION* + constant MAX_REMOTE_ENDPOINTS : natural := 3; + + -- *TYPE DECLARATION* + type STIM_STAGE_TYPE is (IDLE, START, PUSH, DONE, CHECK); + type REF_STAGE_TYPE is (IDLE, START, DONE, CHECK); + type KH_STAGE_TYPE is (IDLE, READ_DATA, PUSH_KEY_HASH); + type RTPS_TEST_TYPE is record + opcode : HISTORY_CACHE_OPCODE_TYPE; + cc : CACHE_CHANGE_TYPE; + ret_code : HISTORY_CACHE_RESPONSE_TYPE; + end record; + constant DEFAULT_RTPS_TEST : RTPS_TEST_TYPE := ( + opcode => NOP, + cc => DEFAULT_CACHE_CHANGE, + ret_code => OK + ); + type DDS_TEST_TYPE is record + opcode : DDS_WRITER_OPCODE_TYPE; + cc : CACHE_CHANGE_TYPE; + ret_code : std_logic_vector(RETURN_CODE_WIDTH-1 downto 0); + end record; + constant DEFAULT_DDS_TEST : DDS_TEST_TYPE := ( + opcode => NOP, + cc => DEFAULT_CACHE_CHANGE, + ret_code => RETCODE_OK + ); + + -- *SIGNAL DECLARATION* + signal clk : std_logic := '0'; + signal reset : std_logic := '1'; + signal check_time : TIME_TYPE := TIME_ZERO; + signal start_rtps, start_dds, start_kh, ack_rtps, ack_dds, ack_kh, done_rtps, done_dds : std_logic := '0'; + signal opcode_rtps : HISTORY_CACHE_OPCODE_TYPE := NOP; + signal opcode_dds : DDS_WRITER_OPCODE_TYPE := NOP; + signal opcode_kh : KEY_HOLDER_OPCODE_TYPE := NOP; + signal ret_rtps : HISTORY_CACHE_RESPONSE_TYPE := ERROR; + signal seq_nr_rtps, cc_seq_nr : SEQUENCENUMBER_TYPE := SEQUENCENUMBER_UNKNOWN; + signal ready_out_rtps, valid_out_rtps, last_word_out_rtps : std_logic := '0'; + signal ready_in_dds, ready_out_dds, valid_in_dds, valid_out_dds, last_word_in_dds, last_word_out_dds : std_logic := '0'; + signal ready_in_kh, ready_out_kh, valid_in_kh, valid_out_kh, last_word_in_kh, last_word_out_kh : std_logic := '0'; + signal data_out_rtps, data_in_dds, data_out_dds, data_in_kh, data_out_kh : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); + signal get_data_rtps, liveliness_assertion, data_available, abort_kh : std_logic := '0'; + signal cc_source_timestamp, source_ts_dds : TIME_TYPE := TIME_INVALID; + signal cc_kind : CACHE_CHANGE_KIND_TYPE := ALIVE; + signal cc_instance_handle, instance_handle_dds : INSTANCE_HANDLE_TYPE := HANDLE_NIL; + signal max_wait_dds : DURATION_TYPE := DURATION_INFINITE; + signal return_code_dds : std_logic_vector(RETURN_CODE_WIDTH-1 downto 0) := (others => '0'); + signal status : std_logic_vector(STATUS_KIND_WIDTH-1 downto 0) := (others => '0'); + + signal stim_start, stim_done, ref_start, ref_done : std_logic := '0'; + signal stim_cnt, ref_cnt, kh_cnt : natural := 0; + signal stim_stage : STIM_STAGE_TYPE := IDLE; + signal ref_stage : REF_STAGE_TYPE := IDLE; + signal kh_stage : KH_STAGE_TYPE := IDLE; + signal kh_data : TEST_PACKET_TYPE := EMPTY_TEST_PACKET; + shared variable stimulus : DDS_TEST_TYPE := DEFAULT_DDS_TEST; + shared variable reference : RTPS_TEST_TYPE := DEFAULT_RTPS_TEST; + signal inst_id, kind_id, sn_id, ts_id, data_id, ret_id : AlertLogIDType; + + -- *FUNCTION DECLARATION* + function extract_key_hash (payload : TEST_PACKET_TYPE) return INSTANCE_HANDLE_TYPE is + variable ret : INSTANCE_HANDLE_TYPE := HANDLE_NIL; + begin + for i in 0 to 3 loop + ret(i) := not payload.data(i); + end loop; + + return ret; + end function; + + function gen_sn(input : natural) return SEQUENCENUMBER_TYPE is + variable ret : SEQUENCENUMBER_TYPE; + begin + ret(0) := (others => '0'); + ret(1) := unsigned(int(input, WORD_WIDTH)); + return ret; + end function; + +begin + + -- Unit Under Test + uut : entity work.dds_writer(arch) + generic map( + HISTORY_QOS => KEEP_ALL_HISTORY_QOS, + DEADLINE_QOS => DURATION_INFINITE, + LIFESPAN_QOS => DURATION_INFINITE, + LEASE_DURATION => DURATION_INFINITE, + WITH_KEY => FALSE, + MAX_SAMPLES => std_logic_vector(to_unsigned(4,CDR_LONG_WIDTH)), + MAX_INSTANCES => std_logic_vector(to_unsigned(3,CDR_LONG_WIDTH)), + MAX_SAMPLES_PER_INSTANCE => std_logic_vector(to_unsigned(2,CDR_LONG_WIDTH)), + PAYLOAD_FRAME_SIZE => 11 + ) + port map ( + clk => clk, + reset => reset, + time => check_time, + start_rtps => start_rtps, + opcode_rtps => opcode_rtps, + ack_rtps => ack_rtps, + done_rtps => done_rtps, + ret_rtps => ret_rtps, + seq_nr_rtps => seq_nr_rtps, + get_data_rtps => get_data_rtps, + data_out_rtps => data_out_rtps, + valid_out_rtps => valid_out_rtps, + ready_out_rtps => ready_out_rtps, + last_word_out_rtps => last_word_out_rtps, + liveliness_assertion => liveliness_assertion, + data_available => data_available, + cc_instance_handle => cc_instance_handle, + cc_kind => cc_kind, + cc_source_timestamp => cc_source_timestamp, + cc_seq_nr => cc_seq_nr, + start_kh => start_kh, + opcode_kh => opcode_kh, + ack_kh => ack_kh, + data_in_kh => data_in_kh, + valid_in_kh => valid_in_kh, + ready_in_kh => ready_in_kh, + last_word_in_kh => last_word_in_kh, + data_out_kh => data_out_kh, + valid_out_kh => valid_out_kh, + ready_out_kh => ready_out_kh, + last_word_out_kh => last_word_out_kh, + abort_kh => abort_kh, + start_dds => start_dds, + ack_dds => ack_dds, + opcode_dds => opcode_dds, + instance_handle_dds => instance_handle_dds, + source_ts_dds => source_ts_dds, + max_wait_dds => max_wait_dds, + done_dds => done_dds, + return_code_dds => return_code_dds, + ready_in_dds => ready_in_dds, + valid_in_dds => valid_in_dds, + data_in_dds => data_in_dds, + last_word_in_dds => last_word_in_dds, + ready_out_dds => ready_out_dds, + valid_out_dds => valid_out_dds, + data_out_dds => data_out_dds, + last_word_out_dds => last_word_out_dds, + status => status + ); + + stimulus_prc : process + variable RV : RandomPType; + variable kh1, kh2, kh3, kh4 : INSTANCE_HANDLE_TYPE := HANDLE_NIL; + variable cc1, cc2, cc3, cc4, cc : CACHE_CHANGE_TYPE := DEFAULT_CACHE_CHANGE; + + impure function gen_payload(key_hash : INSTANCE_HANDLE_TYPE; len : natural) return TEST_PACKET_TYPE is + variable ret : TEST_PACKET_TYPE := EMPTY_TEST_PACKET; + begin + assert (len >= 4) report "Payload length has to be at least 16 Bytes long" severity FAILURE; + + for i in 0 to len-1 loop + if (i < 4) then + -- NOTE: Beginning of payload is negated key to allow deterministic Key Hash generation from the kh_prc + ret.data(ret.length) := not key_hash(i); + else + ret.data(ret.length) := RV.RandSlv(WORD_WIDTH); + end if; + ret.length := ret.length + 1; + end loop; + ret.last(ret.length-1) := '1'; + + return ret; + end function; + + impure function gen_key_hash return KEY_HASH_TYPE is + variable ret : KEY_HASH_TYPE := (others => (others => '0')); + begin + for i in 0 to KEY_HASH_TYPE'length-1 loop + ret(i) := RV.RandSlv(WORD_WIDTH); + end loop; + return ret; + end function; + + procedure start_stim is + begin + stim_start <= '1'; + wait until rising_edge(clk); + stim_start <= '0'; + wait until rising_edge(clk); + end procedure; + + procedure start_ref is + begin + ref_start <= '1'; + wait until rising_edge(clk); + ref_start <= '0'; + wait until rising_edge(clk); + end procedure; + + procedure wait_on_stim is + begin + if (stim_done /= '1') then + wait until stim_done = '1'; + end if; + end procedure; + + procedure wait_on_ref is + begin + if (ref_done /= '1') then + wait until ref_done = '1'; + end if; + end procedure; + + procedure wait_on_completion is + begin + if (ref_done /= '1' or stim_done /= '1') then + wait until ref_done = '1' and stim_done = '1'; + end if; + end procedure; + + begin + + SetAlertLogName("dds_writer - (KEEP ALL, Infinite Lifespan, Keyless) - Level 0 - General"); + SetAlertEnable(FAILURE, TRUE); + SetAlertEnable(ERROR, TRUE); + SetAlertEnable(WARNING, TRUE); + SetLogEnable(DEBUG, FALSE); + SetLogEnable(PASSED, FALSE); + SetLogEnable(INFO, TRUE); + RV.InitSeed(RV'instance_name); + kind_id <= GetAlertLogID("Cache Change Kind", ALERTLOG_BASE_ID); + sn_id <= GetAlertLogID("SequenceNumber", ALERTLOG_BASE_ID); + ts_id <= GetAlertLogID("TimeStamp", ALERTLOG_BASE_ID); + data_id <= GetAlertLogID("Data Out", ALERTLOG_BASE_ID); + ret_id <= GetAlertLogID("Return Code", ALERTLOG_BASE_ID); + + -- Key Hashes + kh1 := gen_key_hash; + kh2 := gen_key_hash; + kh3 := gen_key_hash; + kh4 := gen_key_hash; + + + + Log("Initiating Test", INFO); + reset <= '1'; + wait until rising_edge(clk); + wait until rising_edge(clk); + reset <= '0'; + -- Stored CC: 0, 0, 0, 0 + + -- TEST: GET_MIN_SN/GET_MAX_SN ON EMPTY + + Log("RTPS Operation GET_MIN_SN (Expected SEQUENCENUMBER_UNKNOWN)", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_MIN_SN; + reference.cc.seq_nr := SEQUENCENUMBER_UNKNOWN; + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_MAX_SN (Expected SEQUENCENUMBER_UNKNOWN)", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_MAX_SN; + reference.cc.seq_nr := SEQUENCENUMBER_UNKNOWN; + start_ref; + wait_on_ref; + + -- TEST: WRITE ALIGNED PAYLOAD + -- TEST: NORMAL WRITE + -- TEST: ADD SAMPLE WITH KEY_HASH + + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh1; + cc.payload := gen_payload(kh1,10); + cc.seq_nr := gen_sn(1); + cc.src_timestamp := gen_duration(1,0); + + Log("DDS Operation WRITE [TS 1s, Aligned Payload] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc1 := cc; + -- Stored CC: S1, 0, 0, 0 + + -- TEST: GET_MIN_SN/GET_MAX_SN ON 1 SAMPLE + + Log("RTPS Operation GET_MIN_SN (Expected SN 1)", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_MIN_SN; + reference.cc.seq_nr := gen_sn(1); + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_MAX_SN (Expected SN 1)", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_MAX_SN; + reference.cc.seq_nr := gen_sn(1); + start_ref; + wait_on_ref; + + -- TEST: ADD SAMPLE WITH HANDLE_NIL + -- TEST: WRITE UNALIGNED PAYLOAD [>1 SLOT] + + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh1; + cc.payload := gen_payload(kh1,18); + cc.seq_nr := gen_sn(2); + cc.src_timestamp := gen_duration(2,0); + + Log("DDS Operation WRITE [TS 2s, Unaligned Payload (2 Slots)] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.cc.instance:= HANDLE_NIL; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc2 := cc; + -- Stored CC: S1, S2, 0, 0 + + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh2; + cc.payload := gen_payload(kh2,10); + cc.seq_nr := gen_sn(3); + cc.src_timestamp := gen_duration(3,0); + + -- TEST: NORMAL REGISTER + + Log("DDS Operation REGISTER_INSTANCE 2 (Illegal Operation)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := REGISTER_INSTANCE; + stimulus.cc := cc; + stimulus.cc.instance:= HANDLE_NIL; + start_stim; + wait_on_stim; + + -- TEST: NORMAL DISPOSE + -- TEST: WRITE UNALIGNED PAYLOAD [<1 SLOT] + + cc.serialized_key := TRUE; + cc.kind := NOT_ALIVE_DISPOSED; + cc.instance := kh1; + cc.payload := gen_payload(kh1,5); + cc.seq_nr := gen_sn(3); + cc.src_timestamp := gen_duration(3,0); + + Log("DDS Operation DISPOSE [TS 3s] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := DISPOSE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc3 := cc; + -- Stored CC: S1, S2, S3, 0 + + -- TEST: GET_MIN_SN/GET_MAX_SN ON >1 SAMPLE + + Log("RTPS Operation GET_MIN_SN (Expected SN 1)", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_MIN_SN; + reference.cc.seq_nr := gen_sn(1); + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_MAX_SN (Expected SN 3)", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_MAX_SN; + reference.cc.seq_nr := gen_sn(3); + start_ref; + wait_on_ref; + + -- TEST: GET_CACHE_CHANGE [UNKNOWN SN] + + Log("RTPS Operation GET_CACHE_CHANGE SN 4 (Invalid)", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_CACHE_CHANGE; + reference.cc.seq_nr := gen_sn(4); + reference.ret_code := INVALID; + start_ref; + wait_on_ref; + + -- TEST: GET_CACHE_CHANGE [KNOWN SN, ALIGNED PAYLOAD] + + Log("RTPS Operation GET_CACHE_CHANGE SN 1", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_CACHE_CHANGE; + reference.cc := cc1; + start_ref; + wait_on_ref; + + -- TEST: GET_CACHE_CHANGE [KNOWN SN, UNALIGNED PAYLOAD, >1 SLOT] + + Log("RTPS Operation GET_CACHE_CHANGE SN 2", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_CACHE_CHANGE; + reference.cc := cc2; + start_ref; + wait_on_ref; + + -- TEST: GET_CACHE_CHANGE [KNOWN SN, UNALIGNED PAYLOAD, <1 SLOT] + + Log("RTPS Operation GET_CACHE_CHANGE SN 3", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_CACHE_CHANGE; + reference.cc := cc3; + start_ref; + wait_on_ref; + + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh1; + cc.payload := gen_payload(kh1,10); + cc.seq_nr := gen_sn(4); + cc.src_timestamp := gen_duration(4,0); + + -- TEST: WRITE ON DISPOSED INSTANCE + + Log("DDS Operation WRITE [TS 2s, Aligned Payload] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.cc.instance:= HANDLE_NIL; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc4 := cc; + -- Stored CC: S1, S2, S3, S4 + + cc.serialized_key := TRUE; + cc.kind := NOT_ALIVE_UNREGISTERED; + cc.instance := kh1; + cc.payload := gen_payload(kh1,5); + cc.seq_nr := gen_sn(5); + cc.src_timestamp := gen_duration(5,0); + + -- TEST: UNREGISTER INSTANCE ON PAYLOAD MEMORY FULL [WITHOUT ACKed SAMPLES] + + Log("DDS Operation UNREGISTER_INSTANCE [TS 5s] (REJECTED: Payload Memory Full)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := UNREGISTER_INSTANCE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OUT_OF_RESOURCES; + start_stim; + wait_on_stim; + + -- TEST: NORMAL ACK_CACHE_CHANGE + + Log("RTPS Operation ACK_CACHE_CHANGE SN 1", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := ACK_CACHE_CHANGE; + reference.cc := cc1; + start_ref; + wait_on_ref; + + -- TEST: UNREGISTER INSTANCE ON PAYLOAD MEMORY FULL [WITH ACKed SAMPLES] + -- TEST: NORMAL UNREGISTER + + Log("DDS Operation UNREGISTER_INSTANCE [TS 5s] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := UNREGISTER_INSTANCE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc1 := cc; + -- Stored CC: S5, S2, S3, S4 + + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh1; + cc.payload := gen_payload(kh1,10); + cc.seq_nr := gen_sn(6); + cc.src_timestamp := gen_duration(6,0); + + -- TEST: WRITE ON PAYLOAD MEMORY FULL [WITHOUT ACKed SAMPLES] + + Log("DDS Operation WRITE [TS 6s, Aligned Payload] (REJECTED: Payload Memory Full)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.cc.instance:= HANDLE_NIL; + stimulus.ret_code := RETCODE_OUT_OF_RESOURCES; + start_stim; + wait_on_stim; + + Log("RTPS Operation ACK_CACHE_CHANGE SN 2", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := ACK_CACHE_CHANGE; + reference.cc := cc2; + start_ref; + wait_on_ref; + + Log("RTPS Operation ACK_CACHE_CHANGE SN 3", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := ACK_CACHE_CHANGE; + reference.cc := cc3; + start_ref; + wait_on_ref; + + -- TEST: NORMAL NACK_CACHE_CHANGE + + Log("RTPS Operation NACK_CACHE_CHANGE SN 2", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := NACK_CACHE_CHANGE; + reference.cc := cc2; + start_ref; + wait_on_ref; + + -- TEST: WRITE ON PAYLOAD MEMORY FULL [WITH ACKed SAMPLES] + -- TEST: WRITE ON UNREGISTERED INSTANCE + + Log("DDS Operation WRITE [TS 6s, Aligned Payload] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.cc.instance:= HANDLE_NIL; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc3 := cc; + -- Stored CC: S5, S2, S6, S4 + + cc.serialized_key := TRUE; + cc.kind := NOT_ALIVE_DISPOSED; + cc.instance := kh1; + cc.payload := gen_payload(kh1,5); + cc.seq_nr := gen_sn(7); + cc.src_timestamp := gen_duration(7,0); + + -- TEST: DISPOSE ON PAYLOAD MEMORY FULL [WITHOUT ACKed SAMPLES] + + Log("DDS Operation DISPOSE [TS 7s] (REJECTED: Payload Memory Full)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := DISPOSE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OUT_OF_RESOURCES; + start_stim; + wait_on_stim; + + Log("RTPS Operation ACK_CACHE_CHANGE SN 2", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := ACK_CACHE_CHANGE; + reference.cc := cc2; + start_ref; + wait_on_ref; + + -- TEST: ACK_CACHE_CHANGE [ALREADY ACKed SN] + + Log("RTPS Operation ACK_CACHE_CHANGE SN 2", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := ACK_CACHE_CHANGE; + reference.cc := cc2; + start_ref; + wait_on_ref; + + -- TEST: DISPOSE ON PAYLOAD MEMORY FULL [WITH ACKed SAMPLES] + + Log("DDS Operation DISPOSE [TS 7s] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := DISPOSE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc2 := cc; + -- Stored CC: S5, S7, S6, S4 + + cc.serialized_key := TRUE; + cc.kind := NOT_ALIVE_UNREGISTERED; + cc.instance := kh1; + cc.payload := gen_payload(kh1,5); + cc.seq_nr := gen_sn(8); + cc.src_timestamp := gen_duration(8,0); + + -- TEST: ADD SAMPLE ON MAX_SAMPLES [KNOWN INSTANCE,WITHOUT ACKed SAMPLES] + + Log("DDS Operation UNREGISTER_INSTANCE [TS 8s] (REJECTED: MAX_SAMPLES exceeded)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := UNREGISTER_INSTANCE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OUT_OF_RESOURCES; + start_stim; + wait_on_stim; + + Log("RTPS Operation ACK_CACHE_CHANGE SN 5", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := ACK_CACHE_CHANGE; + reference.cc := cc1; + start_ref; + wait_on_ref; + + -- TEST: ADD SAMPLE ON MAX_SAMPLES [KNOWN INSTANCE,WITH ACKed SAMPLES] + -- TEST: UNREGISTER ON DISPOSED INSTANCE + + Log("DDS Operation UNREGISTER_INSTANCE [TS 8s] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := UNREGISTER_INSTANCE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc1 := cc; + -- Stored CC: S8, S7, S6, S4 + + -- VALIDATE STATE + + Log("RTPS Operation GET_MIN_SN (Expected SN 4)", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_MIN_SN; + reference.cc.seq_nr := gen_sn(4); + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_MAX_SN (Expected SN 8)", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_MAX_SN; + reference.cc.seq_nr := gen_sn(8); + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_CACHE_CHANGE SN 4", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_CACHE_CHANGE; + reference.cc := cc4; + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_CACHE_CHANGE SN 6", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_CACHE_CHANGE; + reference.cc := cc3; + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_CACHE_CHANGE SN 7", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_CACHE_CHANGE; + reference.cc := cc2; + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_CACHE_CHANGE SN 8", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_CACHE_CHANGE; + reference.cc := cc1; + start_ref; + wait_on_ref; + + Log("RTPS Operation ACK_CACHE_CHANGE SN 6", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := ACK_CACHE_CHANGE; + reference.cc := cc3; + start_ref; + wait_on_ref; + + Log("RTPS Operation ACK_CACHE_CHANGE SN 8", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := ACK_CACHE_CHANGE; + reference.cc := cc1; + start_ref; + wait_on_ref; + + cc.serialized_key := TRUE; + cc.kind := NOT_ALIVE_DISPOSED; + cc.instance := kh1; + cc.payload := gen_payload(kh1,5); + cc.seq_nr := gen_sn(9); + cc.src_timestamp := gen_duration(9,0); + + -- TEST: ADD SAMPLE ON MAX_SAMPLES [KNOWN INSTANCE,WITH ACKed SAMPLES (>1)] + + Log("DDS Operation DISPOSE [TS 9s] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := DISPOSE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc3 := cc; + -- Stored CC: S8, S7, S9, S4 + + cc.serialized_key := TRUE; + cc.kind := NOT_ALIVE_UNREGISTERED; + cc.instance := kh1; + cc.payload := gen_payload(kh1,5); + cc.seq_nr := gen_sn(10); + cc.src_timestamp := gen_duration(10,0); + + -- TEST: DISPOSE ON UNREGISTERED INSTANCE + + Log("DDS Operation UNREGISTER_INSTANCE [TS 10s] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := UNREGISTER_INSTANCE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc1 := cc; + -- Stored CC: S10, S7, S9, S4 + + Log("RTPS Operation ACK_CACHE_CHANGE SN 7", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := ACK_CACHE_CHANGE; + reference.cc := cc2; + start_ref; + wait_on_ref; + + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh1; + cc.payload := gen_payload(kh1,20); + cc.seq_nr := gen_sn(11); + cc.src_timestamp := gen_duration(11,0); + + -- TEST: ADD SAMPLE BIGGER THAN AVAILABLE MEMORY SPACE [WITH ACKed SAMPLES] + + Log("DDS Operation WRITE [TS 11s, Aligned Payload (2 Slots)] (REJECTED: Payload Memory Full)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OUT_OF_RESOURCES; + start_stim; + wait_on_stim; + + -- TEST: REMOVE_CACHE_CHANGE [UNKNOWN SN] + + Log("RTPS Operation REMOVE_CACHE_CHANGE SN 12 (Invalid)", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := REMOVE_CACHE_CHANGE; + reference.cc.seq_nr := gen_sn(12); + reference.ret_code := INVALID; + start_ref; + wait_on_ref; + + -- TEST: REMOVE_CACHE_CHANGE [KNOWN SN] + + Log("RTPS Operation REMOVE_CACHE_CHANGE SN 4", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := REMOVE_CACHE_CHANGE; + reference.cc := cc4; + start_ref; + wait_on_ref; + -- Stored CC: S10, S7, S9, 0 + + Log("DDS Operation WRITE [TS 11s, Aligned Payload (2 Slots)] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.cc.instance:= HANDLE_NIL; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc4 := cc; + -- Stored CC: S10, S7, S9, S11 + + -- VALIDATE STATE + + Log("RTPS Operation GET_MIN_SN (Expected SN 7)", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_MIN_SN; + reference.cc.seq_nr := gen_sn(7); + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_MAX_SN (Expected SN 11)", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_MAX_SN; + reference.cc.seq_nr := gen_sn(11); + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_CACHE_CHANGE SN 7", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_CACHE_CHANGE; + reference.cc := cc2; + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_CACHE_CHANGE SN 9", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_CACHE_CHANGE; + reference.cc := cc3; + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_CACHE_CHANGE SN 10", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_CACHE_CHANGE; + reference.cc := cc1; + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_CACHE_CHANGE SN 11", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_CACHE_CHANGE; + reference.cc := cc4; + start_ref; + wait_on_ref; + + -- TEST: INSTANCE LOOKUP [KNOWN INSTANCE] + + Log("DDS Operation LOOKUP_INSTANCE [Illegal Operation]", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := LOOKUP_INSTANCE; + stimulus.cc := cc; + stimulus.cc.instance:= HANDLE_NIL; + start_stim; + wait_on_stim; + + wait_on_completion; + TranscriptOpen(RESULTS_FILE, APPEND_MODE); + SetTranscriptMirror; + ReportAlerts; + TranscriptClose; + std.env.stop; + wait; + end process; + + clock_prc : process + begin + clk <= '0'; + wait for 25 ns; + clk <= '1'; + wait for 25 ns; + end process; + + alert_prc : process(all) + begin + if rising_edge(clk) then + -- TODO + end if; + end process; + + stim_prc : process(all) + begin + if rising_edge(clk) then + stim_done <= '0'; + case (stim_stage) is + when IDLE => + if (stim_start = '1') then + stim_stage <= START; + else + stim_done <= '1'; + end if; + when START => + if (ack_dds = '1') then + stim_stage <= PUSH; + stim_cnt <= 0; + end if; + when PUSH => + if (ready_in_dds = '1') then + stim_cnt <= stim_cnt + 1; + if (stim_cnt = stimulus.cc.payload.length-1) then + -- DEFAULT + stim_stage <= DONE; + + case (stimulus.opcode) is + when REGISTER_INSTANCE => + stim_stage <= CHECK; + stim_cnt <= 0; + when LOOKUP_INSTANCE => + stim_stage <= CHECK; + stim_cnt <= 0; + when others => + null; + end case; + end if; + elsif (done_dds = '1') then + AffirmIfEqual(ret_id, return_code_dds, stimulus.ret_code); + stim_stage <= IDLE; + end if; + when DONE => + if (done_dds = '1') then + AffirmIfEqual(ret_id, return_code_dds, stimulus.ret_code); + stim_stage <= IDLE; + end if; + when CHECK => + if (valid_out_dds = '1') then + AffirmIfEqual(data_id, data_out_dds, stimulus.cc.instance(stim_cnt)); + stim_cnt <= stim_cnt + 1; + if (stim_cnt = 3) then + AlertIf(data_id, last_word_out_dds /= '1', "Last Word Signal not pulled High", ERROR); + stim_stage <= IDLE; + end if; + end if; + end case; + end if; + + -- DEFAULT + start_dds <= '0'; + valid_in_dds <= '0'; + last_word_in_dds <= '0'; + data_in_dds <= (others => '0'); + instance_handle_dds <= HANDLE_NIL; + source_ts_dds <= TIME_INVALID; + ready_out_dds <= '0'; + + case (stim_stage) is + when START => + start_dds <= '1'; + opcode_dds <= stimulus.opcode; + instance_handle_dds <= stimulus.cc.instance; + source_ts_dds <= stimulus.cc.src_timestamp; + when PUSH => + valid_in_dds <= '1'; + data_in_dds <= stimulus.cc.payload.data(stim_cnt); + last_word_in_dds <= stimulus.cc.payload.last(stim_cnt); + when CHECK => + ready_out_dds <= '1'; + when others => + null; + end case; + end process; + + ref_prc : process(all) + begin + if rising_edge(clk) then + ref_done <= '0'; + case (ref_stage) is + when IDLE => + if (ref_start = '1') then + ref_stage <= START; + else + ref_done <= '1'; + end if; + when START => + if (ack_rtps = '1') then + ref_stage <= DONE; + end if; + when DONE => + if (done_rtps = '1') then + -- DEFAULT + ref_stage <= IDLE; + + AffirmIfEqual(ret_id, HISTORY_CACHE_RESPONSE_TYPE'pos(ret_rtps), HISTORY_CACHE_RESPONSE_TYPE'pos(reference.ret_code)); + case (reference.opcode) is + when GET_CACHE_CHANGE => + if (reference.ret_code = OK) then + AffirmIfEqual(kind_id, CACHE_CHANGE_KIND_TYPE'pos(cc_kind), CACHE_CHANGE_KIND_TYPE'pos(reference.cc.kind)); + AffirmIfEqual(sn_id, convert_from_double_word(cc_seq_nr), convert_from_double_word(reference.cc.seq_nr)); + AffirmIfEqual(ts_id, convert_from_double_word(cc_source_timestamp), convert_from_double_word(reference.cc.src_timestamp)); + ref_stage <= CHECK; + ref_cnt <= 0; + end if; + when GET_MIN_SN => + AffirmIfEqual(sn_id, convert_from_double_word(cc_seq_nr), convert_from_double_word(reference.cc.seq_nr)); + when GET_MAX_SN => + AffirmIfEqual(sn_id, convert_from_double_word(cc_seq_nr), convert_from_double_word(reference.cc.seq_nr)); + when others => + null; + end case; + end if; + when CHECK => + if (valid_out_rtps = '1') then + AffirmIfEqual(data_id, last_word_out_rtps & data_out_rtps, reference.cc.payload.last(ref_cnt) & reference.cc.payload.data(ref_cnt)); + ref_cnt <= ref_cnt + 1; + if (ref_cnt = reference.cc.payload.length-1) then + ref_stage <= IDLE; + end if; + end if; + end case; + end if; + + -- DEFAULT + start_rtps <= '0'; + get_data_rtps <= '0'; + ready_out_rtps <= '0'; + + case (ref_stage) is + when START => + start_rtps <= '1'; + opcode_rtps <= reference.opcode; + seq_nr_rtps <= reference.cc.seq_nr; + when DONE => + if (done_rtps = '1') then + case (reference.opcode) is + when GET_CACHE_CHANGE => + get_data_rtps <= '1'; + when others => + null; + end case; + end if; + when CHECK => + ready_out_rtps <= '1'; + when others => + null; + end case; + end process; + + kh_prc : process (all) + variable tmp_key_hash : INSTANCE_HANDLE_TYPE := HANDLE_NIL; + begin + if rising_edge(clk) then + case (kh_stage) is + when IDLE => + if (start_kh = '1') then + case (opcode_kh) is + when PUSH_DATA => + kh_stage <= READ_DATA; + kh_cnt <= 0; + kh_data <= EMPTY_TEST_PACKET; + when PUSH_SERIALIZED_KEY => + kh_stage <= READ_DATA; + kh_cnt <= 0; + kh_data <= EMPTY_TEST_PACKET; + when READ_KEY_HASH => + kh_stage <= PUSH_KEY_HASH; + kh_cnt <= 0; + when others => + Alert("Unexpected Key Holder Operation", FAILURE); + end case; + end if; + when READ_DATA => + if (valid_out_kh = '1') then + kh_data.data(kh_cnt) <= data_out_kh; + kh_data.last(kh_cnt) <= last_word_out_kh; + kh_data.length <= kh_data.length + 1; + + kh_cnt <= kh_cnt + 1; + if (last_word_out_kh = '1') then + kh_stage <= IDLE; + end if; + end if; + when PUSH_KEY_HASH => + if (ready_in_kh = '1') then + kh_cnt <= kh_cnt + 1; + if (kh_cnt = INSTANCE_HANDLE_TYPE'length-1) then + kh_stage <= IDLE; + end if; + end if; + end case; + end if; + + -- DEFAULT + ack_kh <= '0'; + ready_out_kh <= '0'; + valid_in_kh <= '0'; + data_in_kh <= (others => '0'); + last_word_in_kh <= '0'; + + case (kh_stage) is + when IDLE => + if (start_kh = '1') then + ack_kh <= '1'; + end if; + when READ_DATA => + ready_out_kh <= '1'; + when PUSH_KEY_HASH => + valid_in_kh <= '1'; + tmp_key_hash := extract_key_hash(kh_data); + data_in_kh <= tmp_key_hash(kh_cnt); + if (kh_cnt = INSTANCE_HANDLE_TYPE'length-1) then + last_word_in_kh <= '1'; + end if; + end case; + end process; + + watchdog : process + begin + wait for 1 ms; + Alert("Test timeout", FAILURE); + std.env.stop; + end process; + +end architecture; \ No newline at end of file diff --git a/src/Tests/Level_0/L0_dds_writer_test1_lik.txt b/src/Tests/Level_0/L0_dds_writer_test1_lik.txt new file mode 100644 index 0000000..aafa3f5 --- /dev/null +++ b/src/Tests/Level_0/L0_dds_writer_test1_lik.txt @@ -0,0 +1,225 @@ + SAMPLE MEMORY: -/0,9,18,27,36 + PAYLOAD MEMORY: -/0,11,22,33,44 + INSTANCE MEMORY: -/0,8,16 +RTPS Operation GET_MIN_SN (Expected SEQUENCENUMBER_UNKNOWN) +RTPS Operation GET_MAX_SN (Expected SEQUENCENUMBER_UNKNOWN) +DDS Operation WRITE [TS 1s, Instance 1, Aligned Payload] (REJECTED: Instance not Registered) +DDS Operation WRITE [TS 1s, Instance 1, HANDLE_NIL, Aligned Payload] (ACCEPTED) + SAMPLE MEMORY: 0(I1S1)/9,18,27,36 + PAYLOAD MEMORY: 0(I1S1)/11,22,33,44 + INSTANCE MEMORY: 0(I1)/8,16 +RTPS Operation GET_MIN_SN (Expected SN 1) +RTPS Operation GET_MAX_SN (Expected SN 1) +DDS Operation WRITE [TS 1s, Instance 1, Unaligned Payload (2 Slots)] (ACCEPTED) + SAMPLE MEMORY: 0(I1S1),9(I1S2)/18,27,36 + PAYLOAD MEMORY: 0(I1S1),11(I1S2),22(I1S2)/33,44 + INSTANCE MEMORY: 0(I1)/8,16 +DDS Operation DISPOSE [TS 3s, Instance 2] (REJECTED: Instance not Registered) +DDS Operation REGISTER_INSTANCE 2 (ACCEPTED) + SAMPLE MEMORY: 0(I1S1),9(I1S2)/18,27,36 + PAYLOAD MEMORY: 0(I1S1),11(I1S2),22(I1S2)/33,44 + INSTANCE MEMORY: 8(I2),0(I1)/16 +DDS Operation DISPOSE [TS 3s, Instance 1] (ACCEPTED) + SAMPLE MEMORY: 0(I1S1),9(I1S2),18(I2S3)/27,36 + PAYLOAD MEMORY: 0(I1S1),11(I1S2),22(I1S2),33(I2S3)/44 + INSTANCE MEMORY: 8(I2),0(I1)/16 +RTPS Operation GET_MIN_SN (Expected SN 1) +RTPS Operation GET_MAX_SN (Expected SN 3) +RTPS Operation GET_CACHE_CHANGE SN 4 (Invalid) +RTPS Operation GET_CACHE_CHANGE SN 1 +RTPS Operation GET_CACHE_CHANGE SN 2 +RTPS Operation GET_CACHE_CHANGE SN 3 +DDS Operation WRITE [TS 4s, Instance 1, Aligned Payload] (ACCEPTED) + SAMPLE MEMORY: 0(I1S1),9(I1S2),18(I2S3),27(I2S4)/36 + PAYLOAD MEMORY: 0(I1S1),11(I1S2),22(I1S2),33(I2S3),44(I2S4)/- + INSTANCE MEMORY: 8(I2),0(I1)/16 +DDS Operation WRITE [TS 5s, Instance 3, HANDLE_NIL, Aligned Payload] (ACCEPTED) + SAMPLE MEMORY: 9(I1S2),18(I2S3),27(I2S4),36(I3S5)/0 + PAYLOAD MEMORY: 11(I1S2),22(I1S2),33(I2S3),44(I2S4),0(I3S5)/- + INSTANCE MEMORY: 16(I3),8(I2),0(I1)/- +RTPS Operation ACK_CACHE_CHANGE SN 3 +DDS Operation WRITE [TS 6s, Instance 3, Aligned Payload] (ACCEPTED) + SAMPLE MEMORY: 9(I1S2),27(I2S4),36(I3S5),0(I3S6)/18 + PAYLOAD MEMORY: 11(I1S2),22(I1S2),44(I2S4),0(I3S5),33(I3S6)/- + INSTANCE MEMORY: 16(I3),8(I2),0(I1)/- +RTPS Operation GET_MIN_SN (Expected SN 2) +RTPS Operation GET_MAX_SN (Expected SN 6) +RTPS Operation GET_CACHE_CHANGE SN 2 +RTPS Operation GET_CACHE_CHANGE SN 4 +RTPS Operation GET_CACHE_CHANGE SN 5 +RTPS Operation GET_CACHE_CHANGE SN 6 +DDS Operation DISPOSE [TS 7s, Instance 1] (ACCEPTED) + SAMPLE MEMORY: 27(I2S4),36(I3S5),0(I3S6),18(I1S7)/9 + PAYLOAD MEMORY: 44(I2S4),0(I3S5),33(I3S6),11(I1S7)/22 + INSTANCE MEMORY: 16(I3),8(I2),0(I1)/- +RTPS Operation ACK_CACHE_CHANGE SN 5 +DDS Operation WRITE [TS 8s, Instance 2, Aligned Payload (2 Slots)] (REJECTED: Payload Memory Full) +RTPS Operation REMOVE_CACHE_CHANGE SN 3 (Invalid) +RTPS Operation REMOVE_CACHE_CHANGE SN 5 + SAMPLE MEMORY: 27(I2S4),0(I3S6),18(I1S7)/9,36 + PAYLOAD MEMORY: 44(I2S4),33(I3S6),11(I1S7)/0,22 + INSTANCE MEMORY: 16(I3),8(I2),0(I1)/- +DDS Operation WRITE [TS 8s, Instance 2, Aligned Payload (2 Slots)] (ACCEPTED) + SAMPLE MEMORY: 27(I2S4),0(I3S6),18(I1S7),9(I2S8)/36 + PAYLOAD MEMORY: 44(I2S4),33(I3S6),11(I1S7),0(I2S8),22(I2S8)/- + INSTANCE MEMORY: 16(I3),8(I2),0(I1)/- +RTPS Operation ACK_CACHE_CHANGE SN 7 +DDS Operation DISPOSE [TS 9s, Instance 3] (ACCEPTED) + SAMPLE MEMORY: 27(I2S4),0(I3S6),9(I2S8),36(I3S9)/18 + PAYLOAD MEMORY: 44(I2S4),33(I3S6),0(I2S8),22(I2S8),11(I3S9)/- + INSTANCE MEMORY: 16(I3),8(I2),0(I1)/- +RTPS Operation GET_MIN_SN (Expected SN 4) +RTPS Operation GET_MAX_SN (Expected SN 9) +RTPS Operation GET_CACHE_CHANGE SN 4 +RTPS Operation GET_CACHE_CHANGE SN 6 +RTPS Operation GET_CACHE_CHANGE SN 8 +RTPS Operation GET_CACHE_CHANGE SN 9 +DDS Operation UNREGISTER_INSTANCE [TS 10s, Instance 1] (ACCEPTED) + SAMPLE MEMORY: 0(I3S6),9(I2S8),36(I3S9),18(I1S10)/27 + PAYLOAD MEMORY: 33(I3S6),0(I2S8),22(I2S8),11(I3S9),44(I1S10)/- + INSTANCE MEMORY: 16(I3),8(I2),0(I1)/- +RTPS Operation ACK_CACHE_CHANGE SN 9 +DDS Operation UNREGISTER_INSTANCE [TS 11s, Instance 2] (ACCEPTED) + SAMPLE MEMORY: 0(I3S6),9(I2S8),18(I1S10),27(I2S11)/36 + PAYLOAD MEMORY: 33(I3S6),0(I2S8),22(I2S8),44(I1S10),11(I2S11)/- + INSTANCE MEMORY: 16(I3),8(I2),0(I1)/- +RTPS Operation ACK_CACHE_CHANGE SN 6 +RTPS Operation ACK_CACHE_CHANGE SN 8 +RTPS Operation ACK_CACHE_CHANGE SN 11 +DDS Operation WRITE [TS 12s, Instance 4, HANDLE_NIL, Aligned Payload] (ACCEPTED) + SAMPLE MEMORY: 18(I1S10),36(I4S12)/0,9,27 + PAYLOAD MEMORY: 44(I1S10),33(I4S12)/11,0,22 + INSTANCE MEMORY: 8(I4),16(I3),0(I1)/- +RTPS Operation GET_MIN_SN (Expected SN 10) +RTPS Operation GET_MAX_SN (Expected SN 12) +RTPS Operation GET_CACHE_CHANGE SN 10 +RTPS Operation GET_CACHE_CHANGE SN 12 +DDS Operation REGISTER_INSTANCE 2 (REJECTED: MAX_INSTANCES exceeded) +RTPS Operation ACK_CACHE_CHANGE SN 10 +DDS Operation REGISTER_INSTANCE 2 (ACCEPTED) + SAMPLE MEMORY: 36(I4S12)/0,9,27,18 + PAYLOAD MEMORY: 33(I4S12)/44,11,0,22 + INSTANCE MEMORY: 0(I2),8(I4),16(I3)/- +DDS Operation WRITE [TS 13s, Instance 2, Aligned Payload] (ACCEPTED) + SAMPLE MEMORY: 36(I4S12),0(I2S13)/9,27,18 + PAYLOAD MEMORY: 33(I4S12),44(I2S13)/11,0,22 + INSTANCE MEMORY: 0(I2),8(I4),16(I3)/- +DDS Operation REGISTER_INSTANCE 2 (ACCEPTED) +DDS Operation WRITE [TS 14s, Instance 2, Aligned Payload] (ACCEPTED) + SAMPLE MEMORY: 36(I4S12),0(I2S13),9(I2S14)/27,18 + PAYLOAD MEMORY: 33(I4S12),44(I2S13),11(I2S14)/0,22 + INSTANCE MEMORY: 0(I2),8(I4),16(I3)/- +DDS Operation WRITE [TS 15s, Instance 2, Aligned Payload] (ACCEPTED) + SAMPLE MEMORY: 36(I4S12),9(I2S14),27(I2S15)/18,0 + PAYLOAD MEMORY: 33(I4S12),11(I2S14),0(I2S15)/44,22 + INSTANCE MEMORY: 0(I2),8(I4),16(I3)/- +RTPS Operation ACK_CACHE_CHANGE SN 15 +DDS Operation WRITE [TS 16s, Instance 2, Aligned Payload] (ACCEPTED) + SAMPLE MEMORY: 36(I4S12),9(I2S14),18(I2S16)/0,27 + PAYLOAD MEMORY: 33(I4S12),11(I2S14),44(I2S16)/0,22 + INSTANCE MEMORY: 0(I2),8(I4),16(I3)/- +RTPS Operation ACK_CACHE_CHANGE SN 12 +DDS Operation UNREGISTER_INSTANCE [TS 17s, Instance 2] (ACCEPTED) + SAMPLE MEMORY: 36(I4S12),18(I2S16),0(I2S17)/27,9 + PAYLOAD MEMORY: 33(I4S12),44(I2S16),0(I2S17)/11,22 + INSTANCE MEMORY: 0(I2),8(I4),16(I3)/- +RTPS Operation GET_MIN_SN (Expected SN 12) +RTPS Operation GET_MAX_SN (Expected SN 17) +RTPS Operation GET_CACHE_CHANGE SN 12 +RTPS Operation GET_CACHE_CHANGE SN 16 +RTPS Operation GET_CACHE_CHANGE SN 17 +DDS Operation UNREGISTER_INSTANCE [TS 18s, Instance 4] (ACCEPTED) + SAMPLE MEMORY: 36(I4S12),18(I2S16),0(I2S17),27(I4S18)/9 + PAYLOAD MEMORY: 33(I4S12),44(I2S16),0(I2S17),11(I4S178)/22 + INSTANCE MEMORY: 0(I2),8(I4),16(I3)/- +RTPS Operation NACK_CACHE_CHANGE SN 12 +RTPS Operation ACK_CACHE_CHANGE SN 18 +DDS Operation UNREGISTER_INSTANCE [TS 19s, Instance 3] (ACCEPTED) + SAMPLE MEMORY: 36(I4S12),18(I2S16),0(I2S17),9(I3S19)/27 + PAYLOAD MEMORY: 33(I4S12),44(I2S16),0(I2S17),22(I3S19)/11 + INSTANCE MEMORY: 0(I2),8(I4),16(I3)/- +DDS Operation WRITE [TS 20s, Instance 3, Aligned Payload] (ACCEPTED) + SAMPLE MEMORY: 18(I2S16),0(I2S17),9(I3S19),27(I3S20)/36 + PAYLOAD MEMORY: 44(I2S16),0(I2S17),22(I3S19),11(I3S20)/33 + INSTANCE MEMORY: 0(I2),8(I4),16(I3)/- +DDS Operation WRITE [TS 21s, Instance 3, Aligned Payload] (ACCEPTED) + SAMPLE MEMORY: 18(I2S16),0(I2S17),27(I3S20),36(I3S21)/9 + PAYLOAD MEMORY: 44(I2S16),0(I2S17),11(I3S20),33(I3S21)/22 + INSTANCE MEMORY: 0(I2),8(I4),16(I3)/- +RTPS Operation ACK_CACHE_CHANGE SN 16 +DDS Operation WRITE [TS 22s, Instance 3, Aligned Payload] (ACCEPTED) + SAMPLE MEMORY: 18(I2S16),0(I2S17),36(I3S21),9(I3S22)/27 + PAYLOAD MEMORY: 44(I2S16),0(I2S17),33(I3S21),22(I3S22)/11 + INSTANCE MEMORY: 0(I2),8(I4),16(I3)/- +RTPS Operation ACK_CACHE_CHANGE SN 22 +DDS Operation WRITE [TS 23s, Instance 3, Aligned Payload] (ACCEPTED) + SAMPLE MEMORY: 18(I2S16),0(I2S17),36(I3S21),27(I3S23)/9 + PAYLOAD MEMORY: 44(I2S16),0(I2S17),33(I3S21),11(I3S23)/22 + INSTANCE MEMORY: 0(I2),8(I4),16(I3)/- +RTPS Operation GET_MIN_SN (Expected SN 16) +RTPS Operation GET_MAX_SN (Expected SN 23) +RTPS Operation GET_CACHE_CHANGE SN 21 +RTPS Operation GET_CACHE_CHANGE SN 22 +RTPS Operation GET_CACHE_CHANGE SN 23 +DDS Operation UNREGISTER_INSTANCE [TS 24s, HANDLE_NIL, Instance 1] (REJECTED: Instance not Registered) +DDS Operation WRITE [TS 24s, Instance 1, HANDLE_NIL, Aligned Payload] (ACCEPTED) + SAMPLE MEMORY: 0(I2S17),36(I3S21),27(I3S23),9(I1S24)/18 + PAYLOAD MEMORY: 0(I2S17),33(I3S21),11(I3S23),22(I1S24)/44 + INSTANCE MEMORY: 8(I1),0(I2),16(I3)/- +DDS Operation WRITE [TS 25s, Instance 4, HANDLE_NIL Aligned Payload] (REJECTED: MAX_INSTANCES exceeded) +RTPS Operation ACK_CACHE_CHANGE SN 21 +DDS Operation WRITE [TS 25s, Instance 4, HANDLE_NIL Aligned Payload] (REJECTED: MAX_INSTANCES exceeded) +RTPS Operation ACK_CACHE_CHANGE SN 17 +DDS Operation WRITE [TS 25s, Instance 4, HANDLE_NIL, Aligned Payload] (ACCEPTED) + SAMPLE MEMORY: 36(I3S21),27(I3S23),9(I1S24),18(I4S25)/0 + PAYLOAD MEMORY: 33(I3S21),11(I3S23),22(I1S24),22(I4S25)/0 + INSTANCE MEMORY: 0(I4),8(I1),16(I3)/- +RTPS Operation ACK_CACHE_CHANGE SN 21 +DDS Operation WRITE [TS 26s, Instance 2, HANDLE_NIL, Aligned Payload] (REJECTED: MAX_INSTANCES exceeded) +RTPS Operation ACK_CACHE_CHANGE SN 24 +DDS Operation WRITE [TS 26s, Instance 2, HANDLE_NIL, Aligned Payload] (REJECTED: MAX_INSTANCES exceeded) +DDS Operation UNREGISTER_INSTANCE [TS 26s, Instance 1] (ACCEPTED) + SAMPLE MEMORY: 27(I3S23),9(I1S24),18(I4S25),0(I1S26)/36 + PAYLOAD MEMORY: 11(I3S23),22(I1S24),22(I4S25),0(I1S26)/33 + INSTANCE MEMORY: 0(I4),8(I1),16(I3)/- +DDS Operation REGISTER_INSTANCE 1 (ACCEPTED) +DDS Operation WRITE [TS 27s, Instance 2, HANDLE_NIL, Aligned Payload] (REJECTED: MAX_INSTANCES exceeded) +DDS Operation UNREGISTER_INSTANCE [TS 27s, Instance 3] (ACCEPTED) + SAMPLE MEMORY: 27(I3S23),18(I4S25),0(I1S26),36(I3S27)/9 + PAYLOAD MEMORY: 11(I3S23),22(I4S25),0(I1S26),33(I3S27)/22 + INSTANCE MEMORY: 0(I4),8(I1),16(I3)/- +DDS Operation DISPOSE [TS 28s, Instance 3] (ACCEPTED) + SAMPLE MEMORY: 18(I4S25),0(I1S26),36(I3S27),9(I3S28)/27 + PAYLOAD MEMORY: 22(I4S25),0(I1S26),33(I3S27),22(I3S28)/11 + INSTANCE MEMORY: 0(I4),8(I1),16(I3)/- +RTPS Operation ACK_CACHE_CHANGE SN 27 +RTPS Operation ACK_CACHE_CHANGE SN 28 +DDS Operation WRITE [TS 29s, Instance 2, HANDLE_NIL, Aligned Payload] (ACCEPTED) + SAMPLE MEMORY: 18(I4S25),0(I1S26),27(I2S29)/36,9 + PAYLOAD MEMORY: 22(I4S25),0(I1S26),11(I2S29)/22,33 + INSTANCE MEMORY: 16(I2),0(I4),8(I1)/- +RTPS Operation GET_MIN_SN (Expected SN 25) +RTPS Operation GET_MAX_SN (Expected SN 29) +RTPS Operation GET_CACHE_CHANGE SN 25 +RTPS Operation GET_CACHE_CHANGE SN 26 +RTPS Operation GET_CACHE_CHANGE SN 29 +DDS Operation WRITE [TS 30s, Instance 2, Aligned Payload] (ACCEPTED) + SAMPLE MEMORY: 18(I4S25),0(I1S26),27(I2S29),36(I2S30)/9 + PAYLOAD MEMORY: 22(I4S25),0(I1S26),11(I2S29),22(I2S30)/33 + INSTANCE MEMORY: 16(I2),0(I4),8(I1)/- +RTPS Operation ACK_CACHE_CHANGE SN 25 +RTPS Operation ACK_CACHE_CHANGE SN 26 +DDS Operation WRITE [TS 31s, Instance 4, Aligned Payload] (ACCEPTED) + SAMPLE MEMORY: 0(I1S26),27(I2S29),36(I2S30),9(I4S31)/18 + PAYLOAD MEMORY: 0(I1S26),11(I2S29),22(I2S30),33(I4S31)/22 + INSTANCE MEMORY: 16(I2),0(I4),8(I1)/- +RTPS Operation REMOVE_CACHE_CHANGE SN 31 + SAMPLE MEMORY: 0(I1S26),27(I2S29),36(I2S30)/18,9 + PAYLOAD MEMORY: 0(I1S26),11(I2S29),22(I2S30)/33,22 + INSTANCE MEMORY: 16(I2),0(I4),8(I1)/- +RTPS Operation ACK_CACHE_CHANGE SN 29 +RTPS Operation ACK_CACHE_CHANGE SN 30 +DDS Operation WRITE [TS 32s, Instance 2, Aligned Payload] (ACCEPTED) + SAMPLE MEMORY: 0(I1S26),36(I2S30),18(I2S32)/9,27 + PAYLOAD MEMORY: 0(I1S26),22(I2S30),33(I2S32)/11,22 + INSTANCE MEMORY: 16(I2),0(I4),8(I1)/- \ No newline at end of file diff --git a/src/Tests/Level_0/L0_dds_writer_test1_lik.vhd b/src/Tests/Level_0/L0_dds_writer_test1_lik.vhd new file mode 100644 index 0000000..22a6cd4 --- /dev/null +++ b/src/Tests/Level_0/L0_dds_writer_test1_lik.vhd @@ -0,0 +1,1953 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library osvvm; -- Utility Library +context osvvm.OsvvmContext; + +use work.rtps_package.all; +use work.user_config.all; +use work.rtps_config_package.all; +use work.rtps_test_package.all; + +-- This testbench tests the General Operation of the DDS Writer. It tests the correctness of the RTPS +-- GET_MIN_SN, GET_MAX_SN, GET_CACHE_CHANGE, REMOVE_CACHE_CHANGE, ACK_CACHE_CHANGE, and NACK_CACHE_CHANGE Operations and the +-- DDS REGISTER_INSTANCE, UNREGISTER_INSTANCE, WRITE, DISPOSE, and LOOKUP_INSTANCE Operations. +-- More specifically the testbench covers following tests: +-- TEST: GET_MIN_SN/GET_MAX_SN ON EMPTY +-- TEST: GET_MIN_SN/GET_MAX_SN ON 1 SAMPLE +-- TEST: GET_MIN_SN/GET_MAX_SN ON >1 SAMPLE +-- TEST: ADD SAMPLE WITH KEY_HASH [UNKNOWN INSTANCE] +-- TEST: ADD SAMPLE WITH KEY_HASH [KNOWN INSTANCE] +-- TEST: ADD SAMPLE WITH HANDLE_NIL [UNKNOWN INSTANCE] +-- TEST: ADD SAMPLE WITH HANDLE_NIL [KNOWN INSTANCE] +-- TEST: NORMAL WRITE +-- TEST: WRITE ON PAYLOAD MEMORY FULL [WITHOUT ACKed SAMPLES] +-- TEST: WRITE ON PAYLOAD MEMORY FULL [WITH ACKed SAMPLES] +-- TEST: WRITE ON DISPOSED INSTANCE +-- TEST: WRITE ON UNREGISTERED INSTANCE +-- TEST: WRITE ALIGNED PAYLOAD +-- TEST: WRITE UNALIGNED PAYLOAD [>1 SLOT] +-- TEST: WRITE UNALIGNED PAYLOAD [<1 SLOT] +-- TEST: NORMAL REGISTER +-- TEST: REGISTER INSTANCE [KNOWN INSTANCE] +-- TEST: REGISTER INSTANCE ON MAX_INSTANCES [UNKNOWN INSTANCE, WITHOUT STALE INSTANCE] +-- TEST: REGISTER INSTANCE ON MAX_INSTANCES [UNKNOWN INSTANCE, WITH STALE INSTANCE] +-- TEST: REGISTER ON UNREGISTERED INSTANCE +-- TEST: NORMAL DISPOSE +-- TEST: DISPOSE ON PAYLOAD MEMORY FULL [WITHOUT ACKed SAMPLES] +-- TEST: DISPOSE ON PAYLOAD MEMORY FULL [WITH ACKed SAMPLES] +-- TEST: DISPOSE ON UNREGISTERED INSTANCE +-- TEST: GET_CACHE_CHANGE [UNKNOWN SN] +-- TEST: GET_CACHE_CHANGE [KNOWN SN, ALIGNED PAYLOAD] +-- TEST: GET_CACHE_CHANGE [KNOWN SN, UNALIGNED PAYLOAD, >1 SLOT] +-- TEST: GET_CACHE_CHANGE [KNOWN SN, UNALIGNED PAYLOAD, <1 SLOT] +-- TEST: NORMAL ACK_CACHE_CHANGE +-- TEST: ACK_CACHE_CHANGE [ALREADY ACKed SN] +-- TEST: NORMAL NACK_CACHE_CHANGE +-- TEST: REMOVE_CACHE_CHANGE [UNKNOWN SN] +-- TEST: REMOVE_CACHE_CHANGE [KNOWN SN] +-- TEST: NORMAL UNREGISTER +-- TEST: UNREGISTER INSTANCE ON PAYLOAD MEMORY FULL [WITHOUT ACKed SAMPLES] +-- TEST: UNREGISTER INSTANCE ON PAYLOAD MEMORY FULL [WITH ACKed SAMPLES] +-- TEST: UNREGISTER ON DISPOSED INSTANCE +-- TEST: UNREGISTER UNKNOWN INSTANCE +-- TEST: REMOVE STALE INSTANCE WITH 0 SAMPLES +-- TEST: REMOVE STALE INSTANCE WITH 1 SAMPLES +-- TEST: REMOVE STALE INSTANCE WITH >1 SAMPLES +-- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKNOWN INSTANCE, WITH STALE INSTANCE] +-- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKNOWN INSTANCE, WITHOUT STALE INSTANCES] +-- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKNOWN INSTANCE, WITH FULLY ACKed INSTANCE, WITHOUT STALE INSTANCE] +-- TEST: ADD SAMPLE ON MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE, WITHOUT ACKed SAMPLES] +-- TEST: ADD SAMPLE ON MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE, WITH ACKed SAMPLES, WITHOUT ACKed INSTANCE SAMPLES] +-- TEST: ADD SAMPLE ON MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE, WITH ACKed INSTANCE SAMPLE] +-- TEST: ADD SAMPLE ON MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE, WITH ACKed INSTANCE SAMPLES(>1)] +-- TEST: ADD SAMPLE ON MAX_SAMPLES [KNOWN INSTANCE,WITHOUT ACKed SAMPLES] +-- TEST: ADD SAMPLE ON MAX_SAMPLES [KNOWN INSTANCE,WITH ACKed SAMPLE] +-- TEST: ADD SAMPLE ON MAX_SAMPLES [KNOWN INSTANCE,WITH ACKed SAMPLES (>1)] +-- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE,WITHOUT ACKed SAMPLES] +-- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE,WITH ACKed SAMPLES, WITHOUT ACKed INSTANCE SAMPLES] +-- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE,WITH ACKed INSTANCE SAMPLES] +-- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE,WITH STALE INSTANCE, WITHOUT ACKed SAMPLE] +-- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE,WITHOUT STALE INSTANCES,WITHOUT ACKed SAMPLES] +-- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE,WITHOUT STALE INSTANCE, WITH ACKed SAMPLE] +-- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE,WITH STALE INSTANCE (>0 SAMPLES)] +-- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE,WITH STALE INSTANCE, WITH ACKed SAMPLE] +-- TEST: ADD SAMPLE ON PAYLOAD FULL & MAX_INSTANCES [UNKNOWN INSTANCE,WITH ACKed SAMPLES,WITH STALE INSTANCE (>= 1 SAMPLE)] (Induce Double Remove) +-- TEST: ADD SAMPLE BIGGER THAN AVAILABLE MEMORY SPACE [WITH ACKed SAMPLES] +-- TEST: INSTANCE LOOKUP [KNOWN INSTANCE] +-- TEST: INSTANCE LOOKUP [UNKNOWN INSTANCE] + +entity L0_dds_writer_test1_lik is +end entity; + +architecture testbench of L0_dds_writer_test1_lik is + + -- *CONSTANT DECLARATION* + constant MAX_REMOTE_ENDPOINTS : natural := 3; + + -- *TYPE DECLARATION* + type STIM_STAGE_TYPE is (IDLE, START, PUSH, DONE, CHECK); + type REF_STAGE_TYPE is (IDLE, START, DONE, CHECK); + type KH_STAGE_TYPE is (IDLE, READ_DATA, PUSH_KEY_HASH); + type RTPS_TEST_TYPE is record + opcode : HISTORY_CACHE_OPCODE_TYPE; + cc : CACHE_CHANGE_TYPE; + ret_code : HISTORY_CACHE_RESPONSE_TYPE; + end record; + constant DEFAULT_RTPS_TEST : RTPS_TEST_TYPE := ( + opcode => NOP, + cc => DEFAULT_CACHE_CHANGE, + ret_code => OK + ); + type DDS_TEST_TYPE is record + opcode : DDS_WRITER_OPCODE_TYPE; + cc : CACHE_CHANGE_TYPE; + ret_code : std_logic_vector(RETURN_CODE_WIDTH-1 downto 0); + end record; + constant DEFAULT_DDS_TEST : DDS_TEST_TYPE := ( + opcode => NOP, + cc => DEFAULT_CACHE_CHANGE, + ret_code => RETCODE_OK + ); + + -- *SIGNAL DECLARATION* + signal clk : std_logic := '0'; + signal reset : std_logic := '1'; + signal check_time : TIME_TYPE := TIME_ZERO; + signal start_rtps, start_dds, start_kh, ack_rtps, ack_dds, ack_kh, done_rtps, done_dds : std_logic := '0'; + signal opcode_rtps : HISTORY_CACHE_OPCODE_TYPE := NOP; + signal opcode_dds : DDS_WRITER_OPCODE_TYPE := NOP; + signal opcode_kh : KEY_HOLDER_OPCODE_TYPE := NOP; + signal ret_rtps : HISTORY_CACHE_RESPONSE_TYPE := ERROR; + signal seq_nr_rtps, cc_seq_nr : SEQUENCENUMBER_TYPE := SEQUENCENUMBER_UNKNOWN; + signal ready_out_rtps, valid_out_rtps, last_word_out_rtps : std_logic := '0'; + signal ready_in_dds, ready_out_dds, valid_in_dds, valid_out_dds, last_word_in_dds, last_word_out_dds : std_logic := '0'; + signal ready_in_kh, ready_out_kh, valid_in_kh, valid_out_kh, last_word_in_kh, last_word_out_kh : std_logic := '0'; + signal data_out_rtps, data_in_dds, data_out_dds, data_in_kh, data_out_kh : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); + signal get_data_rtps, liveliness_assertion, data_available, abort_kh : std_logic := '0'; + signal cc_source_timestamp, source_ts_dds : TIME_TYPE := TIME_INVALID; + signal cc_kind : CACHE_CHANGE_KIND_TYPE := ALIVE; + signal cc_instance_handle, instance_handle_dds : INSTANCE_HANDLE_TYPE := HANDLE_NIL; + signal max_wait_dds : DURATION_TYPE := DURATION_INFINITE; + signal return_code_dds : std_logic_vector(RETURN_CODE_WIDTH-1 downto 0) := (others => '0'); + signal status : std_logic_vector(STATUS_KIND_WIDTH-1 downto 0) := (others => '0'); + + signal stim_start, stim_done, ref_start, ref_done : std_logic := '0'; + signal stim_cnt, ref_cnt, kh_cnt : natural := 0; + signal stim_stage : STIM_STAGE_TYPE := IDLE; + signal ref_stage : REF_STAGE_TYPE := IDLE; + signal kh_stage : KH_STAGE_TYPE := IDLE; + signal kh_data : TEST_PACKET_TYPE := EMPTY_TEST_PACKET; + shared variable stimulus : DDS_TEST_TYPE := DEFAULT_DDS_TEST; + shared variable reference : RTPS_TEST_TYPE := DEFAULT_RTPS_TEST; + signal inst_id, kind_id, sn_id, ts_id, data_id, ret_id : AlertLogIDType; + + -- *FUNCTION DECLARATION* + function extract_key_hash (payload : TEST_PACKET_TYPE) return INSTANCE_HANDLE_TYPE is + variable ret : INSTANCE_HANDLE_TYPE := HANDLE_NIL; + begin + for i in 0 to 3 loop + ret(i) := not payload.data(i); + end loop; + + return ret; + end function; + + function gen_sn(input : natural) return SEQUENCENUMBER_TYPE is + variable ret : SEQUENCENUMBER_TYPE; + begin + ret(0) := (others => '0'); + ret(1) := unsigned(int(input, WORD_WIDTH)); + return ret; + end function; + +begin + + -- Unit Under Test + uut : entity work.dds_writer(arch) + generic map( + HISTORY_QOS => KEEP_LAST_HISTORY_QOS, + DEADLINE_QOS => DURATION_INFINITE, + LIFESPAN_QOS => DURATION_INFINITE, + LEASE_DURATION => DURATION_INFINITE, + WITH_KEY => TRUE, + MAX_SAMPLES => std_logic_vector(to_unsigned(4,CDR_LONG_WIDTH)), + MAX_INSTANCES => std_logic_vector(to_unsigned(3,CDR_LONG_WIDTH)), + MAX_SAMPLES_PER_INSTANCE => std_logic_vector(to_unsigned(2,CDR_LONG_WIDTH)), + PAYLOAD_FRAME_SIZE => 11 + ) + port map ( + clk => clk, + reset => reset, + time => check_time, + start_rtps => start_rtps, + opcode_rtps => opcode_rtps, + ack_rtps => ack_rtps, + done_rtps => done_rtps, + ret_rtps => ret_rtps, + seq_nr_rtps => seq_nr_rtps, + get_data_rtps => get_data_rtps, + data_out_rtps => data_out_rtps, + valid_out_rtps => valid_out_rtps, + ready_out_rtps => ready_out_rtps, + last_word_out_rtps => last_word_out_rtps, + liveliness_assertion => liveliness_assertion, + data_available => data_available, + cc_instance_handle => cc_instance_handle, + cc_kind => cc_kind, + cc_source_timestamp => cc_source_timestamp, + cc_seq_nr => cc_seq_nr, + start_kh => start_kh, + opcode_kh => opcode_kh, + ack_kh => ack_kh, + data_in_kh => data_in_kh, + valid_in_kh => valid_in_kh, + ready_in_kh => ready_in_kh, + last_word_in_kh => last_word_in_kh, + data_out_kh => data_out_kh, + valid_out_kh => valid_out_kh, + ready_out_kh => ready_out_kh, + last_word_out_kh => last_word_out_kh, + abort_kh => abort_kh, + start_dds => start_dds, + ack_dds => ack_dds, + opcode_dds => opcode_dds, + instance_handle_dds => instance_handle_dds, + source_ts_dds => source_ts_dds, + max_wait_dds => max_wait_dds, + done_dds => done_dds, + return_code_dds => return_code_dds, + ready_in_dds => ready_in_dds, + valid_in_dds => valid_in_dds, + data_in_dds => data_in_dds, + last_word_in_dds => last_word_in_dds, + ready_out_dds => ready_out_dds, + valid_out_dds => valid_out_dds, + data_out_dds => data_out_dds, + last_word_out_dds => last_word_out_dds, + status => status + ); + + stimulus_prc : process + variable RV : RandomPType; + variable kh1, kh2, kh3, kh4 : INSTANCE_HANDLE_TYPE := HANDLE_NIL; + variable cc1, cc2, cc3, cc4, cc : CACHE_CHANGE_TYPE := DEFAULT_CACHE_CHANGE; + + impure function gen_payload(key_hash : INSTANCE_HANDLE_TYPE; len : natural) return TEST_PACKET_TYPE is + variable ret : TEST_PACKET_TYPE := EMPTY_TEST_PACKET; + begin + assert (len >= 4) report "Payload length has to be at least 16 Bytes long" severity FAILURE; + + for i in 0 to len-1 loop + if (i < 4) then + -- NOTE: Beginning of payload is negated key to allow deterministic Key Hash generation from the kh_prc + ret.data(ret.length) := not key_hash(i); + else + ret.data(ret.length) := RV.RandSlv(WORD_WIDTH); + end if; + ret.length := ret.length + 1; + end loop; + ret.last(ret.length-1) := '1'; + + return ret; + end function; + + impure function gen_key_hash return KEY_HASH_TYPE is + variable ret : KEY_HASH_TYPE := (others => (others => '0')); + begin + for i in 0 to KEY_HASH_TYPE'length-1 loop + ret(i) := RV.RandSlv(WORD_WIDTH); + end loop; + return ret; + end function; + + procedure start_stim is + begin + stim_start <= '1'; + wait until rising_edge(clk); + stim_start <= '0'; + wait until rising_edge(clk); + end procedure; + + procedure start_ref is + begin + ref_start <= '1'; + wait until rising_edge(clk); + ref_start <= '0'; + wait until rising_edge(clk); + end procedure; + + procedure wait_on_stim is + begin + if (stim_done /= '1') then + wait until stim_done = '1'; + end if; + end procedure; + + procedure wait_on_ref is + begin + if (ref_done /= '1') then + wait until ref_done = '1'; + end if; + end procedure; + + procedure wait_on_completion is + begin + if (ref_done /= '1' or stim_done /= '1') then + wait until ref_done = '1' and stim_done = '1'; + end if; + end procedure; + + begin + + SetAlertLogName("dds_writer - (KEEP ALL, Infinite Lifespan, Keyed) - Level 0 - General"); + SetAlertEnable(FAILURE, TRUE); + SetAlertEnable(ERROR, TRUE); + SetAlertEnable(WARNING, TRUE); + SetLogEnable(DEBUG, FALSE); + SetLogEnable(PASSED, FALSE); + SetLogEnable(INFO, TRUE); + RV.InitSeed(RV'instance_name); + inst_id <= GetAlertLogID("Instance", ALERTLOG_BASE_ID); + kind_id <= GetAlertLogID("Cache Change Kind", ALERTLOG_BASE_ID); + sn_id <= GetAlertLogID("SequenceNumber", ALERTLOG_BASE_ID); + ts_id <= GetAlertLogID("TimeStamp", ALERTLOG_BASE_ID); + data_id <= GetAlertLogID("Data Out", ALERTLOG_BASE_ID); + ret_id <= GetAlertLogID("Return Code", ALERTLOG_BASE_ID); + + -- Key Hashes + kh1 := gen_key_hash; + kh2 := gen_key_hash; + kh3 := gen_key_hash; + kh4 := gen_key_hash; + + + + Log("Initiating Test", INFO); + reset <= '1'; + wait until rising_edge(clk); + wait until rising_edge(clk); + reset <= '0'; + -- Stored CC: 0, 0, 0, 0 + + -- TEST: GET_MIN_SN/GET_MAX_SN ON EMPTY + + Log("RTPS Operation GET_MIN_SN (Expected SEQUENCENUMBER_UNKNOWN)", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_MIN_SN; + reference.cc.seq_nr := SEQUENCENUMBER_UNKNOWN; + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_MAX_SN (Expected SEQUENCENUMBER_UNKNOWN)", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_MAX_SN; + reference.cc.seq_nr := SEQUENCENUMBER_UNKNOWN; + start_ref; + wait_on_ref; + + -- TEST: ADD SAMPLE WITH KEY_HASH [UNKNOWN INSTANCE] + + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh1; + cc.payload := gen_payload(kh1,10); + cc.seq_nr := gen_sn(1); + cc.src_timestamp := gen_duration(1,0); + + Log("DDS Operation WRITE [TS 1s, Instance 1, Aligned Payload] (REJECTED: Instance not Registered)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_BAD_PARAMETER; + start_stim; + wait_on_stim; + + -- TEST: ADD SAMPLE WITH HANDLE_NIL [UNKNOWN INSTANCE] + -- TEST: NORMAL WRITE + -- TEST: WRITE ALIGNED PAYLOAD + + Log("DDS Operation WRITE [TS 1s, Instance 1, HANDLE_NIL, Aligned Payload] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.cc.instance:= HANDLE_NIL; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc1 := cc; + -- Stored CC: I1S1, 0, 0, 0 + + -- TEST: GET_MIN_SN/GET_MAX_SN ON 1 SAMPLE + + Log("RTPS Operation GET_MIN_SN (Expected SN 1)", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_MIN_SN; + reference.cc.seq_nr := gen_sn(1); + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_MAX_SN (Expected SN 1)", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_MAX_SN; + reference.cc.seq_nr := gen_sn(1); + start_ref; + wait_on_ref; + + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh1; + cc.payload := gen_payload(kh1,18); + cc.seq_nr := gen_sn(2); + cc.src_timestamp := gen_duration(2,0); + + -- TEST: ADD SAMPLE WITH KEY_HASH [KNOWN INSTANCE] + -- TEST: WRITE UNALIGNED PAYLOAD [>1 SLOT] + + Log("DDS Operation WRITE [TS 2s, Instance 1, Unaligned Payload (2 Slot)] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc2 := cc; + -- Stored CC: I1S1, I1S2, 0, 0 + + cc.serialized_key := TRUE; + cc.kind := NOT_ALIVE_DISPOSED; + cc.instance := kh2; + cc.payload := gen_payload(kh2,5); + cc.seq_nr := gen_sn(3); + cc.src_timestamp := gen_duration(3,0); + + Log("DDS Operation DISPOSE [TS 3s, Instance 2] (REJECTED: Instance not Registered)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := DISPOSE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_BAD_PARAMETER; + start_stim; + wait_on_stim; + + -- TEST: NORMAL REGISTER + + Log("DDS Operation REGISTER_INSTANCE 2 (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := REGISTER_INSTANCE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + + -- TEST: NORMAL DISPOSE + -- TEST: WRITE UNALIGNED PAYLOAD [<1 SLOT] + + Log("DDS Operation DISPOSE [TS 3s, Instance 2] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := DISPOSE; + stimulus.cc := cc; + stimulus.cc.instance:= HANDLE_NIL; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc3 := cc; + -- Stored CC: I1S1, I1S2, I2S3, 0 + + -- TEST: GET_MIN_SN/GET_MAX_SN ON >1 SAMPLE + -- VALIDATE STATE + + Log("RTPS Operation GET_MIN_SN (Expected SN 1)", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_MIN_SN; + reference.cc.seq_nr := gen_sn(1); + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_MAX_SN (Expected SN 3)", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_MAX_SN; + reference.cc.seq_nr := gen_sn(3); + start_ref; + wait_on_ref; + + -- TEST: GET_CACHE_CHANGE [UNKNOWN SN] + + Log("RTPS Operation GET_CACHE_CHANGE SN 4 (Invalid)", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_CACHE_CHANGE; + reference.cc.seq_nr := gen_sn(4); + reference.ret_code := INVALID; + start_ref; + wait_on_ref; + + -- TEST: GET_CACHE_CHANGE [KNOWN SN, ALIGNED PAYLOAD] + + Log("RTPS Operation GET_CACHE_CHANGE SN 1", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_CACHE_CHANGE; + reference.cc := cc1; + start_ref; + wait_on_ref; + + -- TEST: GET_CACHE_CHANGE [KNOWN SN, UNALIGNED PAYLOAD, >1 SLOT] + + Log("RTPS Operation GET_CACHE_CHANGE SN 2", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_CACHE_CHANGE; + reference.cc := cc2; + start_ref; + wait_on_ref; + + -- TEST: GET_CACHE_CHANGE [KNOWN SN, UNALIGNED PAYLOAD, <1 SLOT] + + Log("RTPS Operation GET_CACHE_CHANGE SN 3", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_CACHE_CHANGE; + reference.cc := cc3; + start_ref; + wait_on_ref; + + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh2; + cc.payload := gen_payload(kh2,10); + cc.seq_nr := gen_sn(4); + cc.src_timestamp := gen_duration(4,0); + + -- TEST: WRITE ON DISPOSED INSTANCE + -- TEST: ADD SAMPLE WITH HANDLE_NIL [KNOWN INSTANCE] + + Log("DDS Operation WRITE [TS 4s, Instance 2, Aligned Payload] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.cc.instance:= HANDLE_NIL; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc4 := cc; + -- Stored CC: I1S1, I1S2, I2S3, I2S4 + + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh3; + cc.payload := gen_payload(kh3,10); + cc.seq_nr := gen_sn(5); + cc.src_timestamp := gen_duration(5,0); + + -- TEST: WRITE ON PAYLOAD MEMORY FULL [WITHOUT ACKed SAMPLES] + + Log("DDS Operation WRITE [TS 5s, Instance 3, HANDLE_NIL, Aligned Payload] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.cc.instance:= HANDLE_NIL; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc1 := cc; + -- Stored CC: I3S5, I1S2, I2S3, I2S4 + + -- TEST: NORMAL ACK_CACHE_CHANGE + + Log("RTPS Operation ACK_CACHE_CHANGE SN 3", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := ACK_CACHE_CHANGE; + reference.cc := cc3; + start_ref; + wait_on_ref; + + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh3; + cc.payload := gen_payload(kh3,10); + cc.seq_nr := gen_sn(6); + cc.src_timestamp := gen_duration(6,0); + + -- TEST: WRITE ON PAYLOAD MEMORY FULL [WITH ACKed SAMPLES] + + Log("DDS Operation WRITE [TS 6s, Instance 3, Aligned Payload] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc3 := cc; + -- Stored CC: I3S5, I1S2, I3S6, I2S4 + + -- VALIDATE STATE + + Log("RTPS Operation GET_MIN_SN (Expected SN 2)", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_MIN_SN; + reference.cc.seq_nr := gen_sn(2); + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_MAX_SN (Expected SN 6)", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_MAX_SN; + reference.cc.seq_nr := gen_sn(6); + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_CACHE_CHANGE SN 2", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_CACHE_CHANGE; + reference.cc := cc2; + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_CACHE_CHANGE SN 4", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_CACHE_CHANGE; + reference.cc := cc4; + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_CACHE_CHANGE SN 5", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_CACHE_CHANGE; + reference.cc := cc1; + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_CACHE_CHANGE SN 6", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_CACHE_CHANGE; + reference.cc := cc3; + start_ref; + wait_on_ref; + + cc.serialized_key := TRUE; + cc.kind := NOT_ALIVE_DISPOSED; + cc.instance := kh1; + cc.payload := gen_payload(kh1,5); + cc.seq_nr := gen_sn(7); + cc.src_timestamp := gen_duration(7,0); + + -- TEST: DISPOSE ON PAYLOAD MEMORY FULL [WITHOUT ACKed SAMPLES] + + Log("DDS Operation DISPOSE [TS 7s, Instance 1] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := DISPOSE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc2 := cc; + -- Stored CC: I3S5, I1S7, I3S6, I2S4 + + Log("RTPS Operation ACK_CACHE_CHANGE SN 5", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := ACK_CACHE_CHANGE; + reference.cc := cc1; + start_ref; + wait_on_ref; + + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh2; + cc.payload := gen_payload(kh2,20); + cc.seq_nr := gen_sn(8); + cc.src_timestamp := gen_duration(8,0); + + -- TEST: ADD SAMPLE BIGGER THAN AVAILABLE MEMORY SPACE [WITH ACKed SAMPLES] + + Log("DDS Operation WRITE [TS 8s, Instance 2, Aligned Payload (2 Slots)] (REJECTED: Payload Memory Full)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OUT_OF_RESOURCES; + start_stim; + wait_on_stim; + + -- TEST: REMOVE_CACHE_CHANGE [UNKNOWN SN] + + Log("RTPS Operation REMOVE_CACHE_CHANGE SN 3 (Invalid)", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := REMOVE_CACHE_CHANGE; + reference.cc.seq_nr := gen_sn(3); + reference.ret_code := INVALID; + start_ref; + wait_on_ref; + + -- TEST: REMOVE_CACHE_CHANGE [KNOWN SN] + + Log("RTPS Operation REMOVE_CACHE_CHANGE SN 5", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := REMOVE_CACHE_CHANGE; + reference.cc := cc1; + start_ref; + wait_on_ref; + -- Stored CC: 0, I1S7, I3S6, I2S4 + + Log("DDS Operation WRITE [TS 8s, Instance 2, Aligned Payload (2 Slots)] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc1 := cc; + -- Stored CC: I2S8, I1S7, I3S6, I2S4 + + Log("RTPS Operation ACK_CACHE_CHANGE SN 7", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := ACK_CACHE_CHANGE; + reference.cc := cc2; + start_ref; + wait_on_ref; + + cc.serialized_key := TRUE; + cc.kind := NOT_ALIVE_DISPOSED; + cc.instance := kh3; + cc.payload := gen_payload(kh3,5); + cc.seq_nr := gen_sn(9); + cc.src_timestamp := gen_duration(9,0); + + -- TEST: DISPOSE ON PAYLOAD MEMORY FULL [WITH ACKed SAMPLES] + + Log("DDS Operation DISPOSE [TS 9s, Instance 3] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := DISPOSE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc2 := cc; + -- Stored CC: I2S8, I3S9, I3S6, I2S4 + + -- VALIDATE STATE + + Log("RTPS Operation GET_MIN_SN (Expected SN 4)", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_MIN_SN; + reference.cc.seq_nr := gen_sn(4); + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_MAX_SN (Expected SN 9)", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_MAX_SN; + reference.cc.seq_nr := gen_sn(9); + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_CACHE_CHANGE SN 4", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_CACHE_CHANGE; + reference.cc := cc4; + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_CACHE_CHANGE SN 6", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_CACHE_CHANGE; + reference.cc := cc3; + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_CACHE_CHANGE SN 8", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_CACHE_CHANGE; + reference.cc := cc1; + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_CACHE_CHANGE SN 9", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_CACHE_CHANGE; + reference.cc := cc2; + start_ref; + wait_on_ref; + + cc.serialized_key := TRUE; + cc.kind := NOT_ALIVE_UNREGISTERED; + cc.instance := kh1; + cc.payload := gen_payload(kh1,5); + cc.seq_nr := gen_sn(10); + cc.src_timestamp := gen_duration(10,0); + + -- TEST: UNREGISTER ON DISPOSED INSTANCE + -- TEST: UNREGISTER INSTANCE ON PAYLOAD MEMORY FULL [WITHOUT ACKed SAMPLES] + + Log("DDS Operation UNREGISTER_INSTANCE [TS 10s, Instance 1] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := UNREGISTER_INSTANCE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc4 := cc; + -- Stored CC: I2S8, I3S9, I3S6, I1S10 + + Log("RTPS Operation ACK_CACHE_CHANGE SN 9", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := ACK_CACHE_CHANGE; + reference.cc := cc2; + start_ref; + wait_on_ref; + + cc.serialized_key := TRUE; + cc.kind := NOT_ALIVE_UNREGISTERED; + cc.instance := kh2; + cc.payload := gen_payload(kh2,5); + cc.seq_nr := gen_sn(11); + cc.src_timestamp := gen_duration(11,0); + + -- TEST: UNREGISTER INSTANCE ON PAYLOAD MEMORY FULL [WITH ACKed SAMPLES] + + Log("DDS Operation UNREGISTER_INSTANCE [TS 11s, Instance 2] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := UNREGISTER_INSTANCE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc2 := cc; + -- Stored CC: I2S8, I2S11, I3S6, I1S10 + + Log("RTPS Operation ACK_CACHE_CHANGE SN 6", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := ACK_CACHE_CHANGE; + reference.cc := cc3; + start_ref; + wait_on_ref; + + Log("RTPS Operation ACK_CACHE_CHANGE SN 8", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := ACK_CACHE_CHANGE; + reference.cc := cc1; + start_ref; + wait_on_ref; + + Log("RTPS Operation ACK_CACHE_CHANGE SN 11", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := ACK_CACHE_CHANGE; + reference.cc := cc2; + start_ref; + wait_on_ref; + + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh4; + cc.payload := gen_payload(kh4,10); + cc.seq_nr := gen_sn(12); + cc.src_timestamp := gen_duration(12,0); + + -- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKNOWN INSTANCE, WITH STALE INSTANCE] + -- TEST: ADD SAMPLE ON PAYLOAD FULL & MAX_INSTANCES [UNKNOWN INSTANCE,WITH ACKed SAMPLES,WITH STALE INSTANCE (>= 1 SAMPLE)] (Induce Double Remove) + -- TEST: REMOVE STALE INSTANCE WITH >1 SAMPLES + + Log("DDS Operation WRITE [TS 12s, Instance 4, HANDLE_NIL, Aligned Payload] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.cc.instance:= HANDLE_NIL; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc1 := cc; + -- Stored CC: I4S12, 0, 0, I1S10 + + -- VALIDATE STATE + + Log("RTPS Operation GET_MIN_SN (Expected SN 10)", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_MIN_SN; + reference.cc.seq_nr := gen_sn(10); + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_MAX_SN (Expected SN 12)", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_MAX_SN; + reference.cc.seq_nr := gen_sn(12); + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_CACHE_CHANGE SN 10", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_CACHE_CHANGE; + reference.cc := cc4; + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_CACHE_CHANGE SN 12", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_CACHE_CHANGE; + reference.cc := cc1; + start_ref; + wait_on_ref; + + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh2; + cc.payload := gen_payload(kh2,10); + cc.seq_nr := gen_sn(13); + cc.src_timestamp := gen_duration(13,0); + + -- TEST: REGISTER INSTANCE ON MAX_INSTANCES [UNKNOWN INSTANCE, WITHOUT STALE INSTANCE] + + Log("DDS Operation REGISTER_INSTANCE 2 (REJECTED: MAX_INSTANCES exceeded)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := REGISTER_INSTANCE; + stimulus.cc := cc; + stimulus.cc.instance:= HANDLE_NIL; + start_stim; + wait_on_stim; + + Log("RTPS Operation ACK_CACHE_CHANGE SN 10", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := ACK_CACHE_CHANGE; + reference.cc := cc4; + start_ref; + wait_on_ref; + + -- TEST: REGISTER INSTANCE ON MAX_INSTANCES [UNKNOWN INSTANCE, WITH STALE INSTANCE] + -- TEST: REMOVE STALE INSTANCE WITH 1 SAMPLES + + Log("DDS Operation REGISTER_INSTANCE 2 (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := REGISTER_INSTANCE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + -- Stored CC: I4S12, 0, 0, 0 + + Log("DDS Operation WRITE [TS 13s, Instance 2, Aligned Payload] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc2 := cc; + -- Stored CC: I4S12, I2S13, 0, 0 + + -- TEST: REGISTER INSTANCE [KNOWN INSTANCE] + + Log("DDS Operation REGISTER_INSTANCE 2 (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := REGISTER_INSTANCE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh2; + cc.payload := gen_payload(kh2,10); + cc.seq_nr := gen_sn(14); + cc.src_timestamp := gen_duration(14,0); + + Log("DDS Operation WRITE [TS 14s, Instance 2, Aligned Payload] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc3 := cc; + -- Stored CC: I4S12, I2S13, I2S14, 0 + + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh2; + cc.payload := gen_payload(kh2,10); + cc.seq_nr := gen_sn(15); + cc.src_timestamp := gen_duration(15,0); + + -- TEST: ADD SAMPLE ON MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE, WITHOUT ACKed SAMPLES] + + Log("DDS Operation WRITE [TS 15s, Instance 2, Aligned Payload] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc2 := cc; + -- Stored CC: I4S12, I2S15, I2S14, 0 + + Log("RTPS Operation ACK_CACHE_CHANGE SN 15", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := ACK_CACHE_CHANGE; + reference.cc := cc2; + start_ref; + wait_on_ref; + + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh2; + cc.payload := gen_payload(kh2,10); + cc.seq_nr := gen_sn(16); + cc.src_timestamp := gen_duration(16,0); + + -- TEST: ADD SAMPLE ON MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE, WITH ACKed INSTANCE SAMPLE] + + Log("DDS Operation WRITE [TS 16s, Instance 2, Aligned Payload] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc2 := cc; + -- Stored CC: I4S12, I2S16, I2S14, 0 + + Log("RTPS Operation ACK_CACHE_CHANGE SN 12", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := ACK_CACHE_CHANGE; + reference.cc := cc1; + start_ref; + wait_on_ref; + + cc.serialized_key := TRUE; + cc.kind := NOT_ALIVE_UNREGISTERED; + cc.instance := kh2; + cc.payload := gen_payload(kh2,5); + cc.seq_nr := gen_sn(17); + cc.src_timestamp := gen_duration(17,0); + + -- TEST: NORMAL UNREGISTER + -- TEST: ADD SAMPLE ON MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE, WITH ACKed SAMPLES, WITHOUT ACKed INSTANCE SAMPLES] + + Log("DDS Operation UNREGISTER_INSTANCE [TS 17s, Instance 2] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := UNREGISTER_INSTANCE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc3 := cc; + -- Stored CC: I4S12, I2S16, I2S17, 0 + + -- VALIDATE STATE + + Log("RTPS Operation GET_MIN_SN (Expected SN 12)", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_MIN_SN; + reference.cc.seq_nr := gen_sn(12); + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_MAX_SN (Expected SN 17)", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_MAX_SN; + reference.cc.seq_nr := gen_sn(17); + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_CACHE_CHANGE SN 12", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_CACHE_CHANGE; + reference.cc := cc1; + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_CACHE_CHANGE SN 16", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_CACHE_CHANGE; + reference.cc := cc2; + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_CACHE_CHANGE SN 17", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_CACHE_CHANGE; + reference.cc := cc3; + start_ref; + wait_on_ref; + + cc.serialized_key := TRUE; + cc.kind := NOT_ALIVE_UNREGISTERED; + cc.instance := kh4; + cc.payload := gen_payload(kh4,5); + cc.seq_nr := gen_sn(18); + cc.src_timestamp := gen_duration(18,0); + + Log("DDS Operation UNREGISTER_INSTANCE [TS 18s, Instance 4] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := UNREGISTER_INSTANCE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc4 := cc; + -- Stored CC: I4S12, I2S16, I2S17, I4S18 + + cc.serialized_key := TRUE; + cc.kind := NOT_ALIVE_UNREGISTERED; + cc.instance := kh3; + cc.payload := gen_payload(kh3,5); + cc.seq_nr := gen_sn(19); + cc.src_timestamp := gen_duration(19,0); + + -- TEST: NORMAL NACK_CACHE_CHANGE + + Log("RTPS Operation NACK_CACHE_CHANGE SN 12", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := NACK_CACHE_CHANGE; + reference.cc := cc1; + start_ref; + wait_on_ref; + + Log("RTPS Operation ACK_CACHE_CHANGE SN 18", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := ACK_CACHE_CHANGE; + reference.cc := cc4; + start_ref; + wait_on_ref; + + -- TEST: ADD SAMPLE ON MAX_SAMPLES [KNOWN INSTANCE,WITH ACKed SAMPLE] + + Log("DDS Operation UNREGISTER_INSTANCE [TS 19s, Instance 3] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := UNREGISTER_INSTANCE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc4 := cc; + -- Stored CC: I4S12, I2S16, I2S17, I3S19 + + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh3; + cc.payload := gen_payload(kh3,10); + cc.seq_nr := gen_sn(20); + cc.src_timestamp := gen_duration(20,0); + + -- TEST: ADD SAMPLE ON MAX_SAMPLES [KNOWN INSTANCE,WITHOUT ACKed SAMPLES] + -- TEST: WRITE ON UNREGISTERED INSTANCE + + Log("DDS Operation WRITE [TS 20s, Instance 3, Aligned Payload] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc1 := cc; + -- Stored CC: I3S20, I2S16, I2S17, I3S19 + + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh3; + cc.payload := gen_payload(kh3,10); + cc.seq_nr := gen_sn(21); + cc.src_timestamp := gen_duration(21,0); + + -- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE,WITHOUT ACKed SAMPLES] + + Log("DDS Operation WRITE [TS 21s, Instance 3, Aligned Payload] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc4 := cc; + -- Stored CC: I3S20, I2S16, I2S17, I3S21 + + Log("RTPS Operation ACK_CACHE_CHANGE SN 16", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := ACK_CACHE_CHANGE; + reference.cc := cc2; + start_ref; + wait_on_ref; + + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh3; + cc.payload := gen_payload(kh3,10); + cc.seq_nr := gen_sn(22); + cc.src_timestamp := gen_duration(22,0); + + -- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE,WITH ACKed SAMPLES, WITHOUT ACKed INSTANCE SAMPLES] + + Log("DDS Operation WRITE [TS 22s, Instance 3, Aligned Payload] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc1 := cc; + -- Stored CC: I3S22, I2S16, I2S17, I3S21 + + Log("RTPS Operation ACK_CACHE_CHANGE SN 22", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := ACK_CACHE_CHANGE; + reference.cc := cc1; + start_ref; + wait_on_ref; + + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh3; + cc.payload := gen_payload(kh3,10); + cc.seq_nr := gen_sn(23); + cc.src_timestamp := gen_duration(23,0); + + -- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE,WITH ACKed INSTANCE SAMPLES] + + Log("DDS Operation WRITE [TS 23s, Instance 3, Aligned Payload] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc1 := cc; + -- Stored CC: I3S23, I2S16, I2S17, I3S21 + + -- VALIDATE STATE + + Log("RTPS Operation GET_MIN_SN (Expected SN 16)", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_MIN_SN; + reference.cc.seq_nr := gen_sn(16); + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_MAX_SN (Expected SN 23)", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_MAX_SN; + reference.cc.seq_nr := gen_sn(23); + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_CACHE_CHANGE SN 21", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_CACHE_CHANGE; + reference.cc := cc4; + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_CACHE_CHANGE SN 22", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_CACHE_CHANGE; + reference.cc.seq_nr := gen_sn(22); + reference.ret_code := INVALID; + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_CACHE_CHANGE SN 23", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_CACHE_CHANGE; + reference.cc := cc1; + start_ref; + wait_on_ref; + + cc.serialized_key := TRUE; + cc.kind := NOT_ALIVE_UNREGISTERED; + cc.instance := kh1; + cc.payload := gen_payload(kh1,5); + cc.seq_nr := gen_sn(24); + cc.src_timestamp := gen_duration(24,0); + + -- TEST: UNREGISTER UNKNOWN INSTANCE + + Log("DDS Operation UNREGISTER_INSTANCE [TS 24s, HANDLE_NIL, Instance 1] (IGNORED: Instance not Registered)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := UNREGISTER_INSTANCE; + stimulus.cc := cc; + stimulus.cc.instance:= HANDLE_NIL; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh1; + cc.payload := gen_payload(kh1,10); + cc.seq_nr := gen_sn(24); + cc.src_timestamp := gen_duration(24,0); + + -- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE,WITH STALE INSTANCE, WITHOUT ACKed SAMPLE] + -- TEST: REMOVE STALE INSTANCE WITH 0 SAMPLES + + Log("DDS Operation WRITE [TS 24s, Instance 1, HANDLE_NIL, Aligned Payload] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.cc.instance:= HANDLE_NIL; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc2 := cc; + -- Stored CC: I3S23, I1S24, I2S17, I3S21 + + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh4; + cc.payload := gen_payload(kh4,10); + cc.seq_nr := gen_sn(25); + cc.src_timestamp := gen_duration(25,0); + + -- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE,WITHOUT STALE INSTANCES,WITHOUT ACKed SAMPLES] + + Log("DDS Operation WRITE [TS 25s, Instance 4, HANDLE_NIL Aligned Payload] (REJECTED: MAX_INSTANCES exceeded)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.cc.instance:= HANDLE_NIL; + stimulus.ret_code := RETCODE_OUT_OF_RESOURCES; + start_stim; + wait_on_stim; + + Log("RTPS Operation ACK_CACHE_CHANGE SN 21", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := ACK_CACHE_CHANGE; + reference.cc := cc4; + start_ref; + wait_on_ref; + + -- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE,WITHOUT STALE INSTANCE, WITH ACKed SAMPLE] + + Log("DDS Operation WRITE [TS 25s, Instance 4, HANDLE_NIL, Aligned Payload] (REJECTED: MAX_INSTANCES exceeded)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.cc.instance:= HANDLE_NIL; + stimulus.ret_code := RETCODE_OUT_OF_RESOURCES; + start_stim; + wait_on_stim; + + Log("RTPS Operation ACK_CACHE_CHANGE SN 17", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := ACK_CACHE_CHANGE; + reference.cc := cc3; + start_ref; + wait_on_ref; + + -- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE,WITH STALE INSTANCE (>0 SAMPLES)] + -- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE,WITH STALE INSTANCE, WITH ACKed SAMPLE] + + Log("DDS Operation WRITE [TS 25s, Instance 4, HANDLE_NIL, Aligned Payload] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.cc.instance:= HANDLE_NIL; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc3 := cc; + -- Stored CC: I3S23, I1S24, I4S25, I3S21 + + -- TEST: ACK_CACHE_CHANGE [ALREADY ACKed SN] + + Log("RTPS Operation ACK_CACHE_CHANGE SN 21", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := ACK_CACHE_CHANGE; + reference.cc := cc4; + start_ref; + wait_on_ref; + + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh2; + cc.payload := gen_payload(kh2,10); + cc.seq_nr := gen_sn(26); + cc.src_timestamp := gen_duration(26,0); + + -- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKNOWN INSTANCE, WITHOUT STALE INSTANCES] + + Log("DDS Operation WRITE [TS 26s, Instance 2, HANDLE_NIL, Aligned Payload] (REJECTED: MAX_INSTANCES exceeded)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.cc.instance:= HANDLE_NIL; + stimulus.ret_code := RETCODE_OUT_OF_RESOURCES; + start_stim; + wait_on_stim; + + Log("RTPS Operation ACK_CACHE_CHANGE SN 24", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := ACK_CACHE_CHANGE; + reference.cc := cc2; + start_ref; + wait_on_ref; + + -- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKNOWN INSTANCE, WITH FULLY ACKed INSTANCE, WITHOUT STALE INSTANCE] + + Log("DDS Operation WRITE [TS 26s, Instance 2, HANDLE_NIL, Aligned Payload] (REJECTED: MAX_INSTANCES exceeded)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.cc.instance:= HANDLE_NIL; + stimulus.ret_code := RETCODE_OUT_OF_RESOURCES; + start_stim; + wait_on_stim; + + cc.serialized_key := TRUE; + cc.kind := NOT_ALIVE_UNREGISTERED; + cc.instance := kh1; + cc.payload := gen_payload(kh1,5); + cc.seq_nr := gen_sn(26); + cc.src_timestamp := gen_duration(26,0); + + Log("DDS Operation UNREGISTER_INSTANCE [TS 26s, Instance 1] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := UNREGISTER_INSTANCE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc4 := cc; + -- Stored CC: I3S23, I1S24, I4S25, I1S26 + + Log("RTPS Operation ACK_CACHE_CHANGE SN 26", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := ACK_CACHE_CHANGE; + reference.cc := cc2; + start_ref; + wait_on_ref; + + -- TEST: REGISTER ON UNREGISTERED INSTANCE + + Log("DDS Operation REGISTER_INSTANCE 1 (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := REGISTER_INSTANCE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh2; + cc.payload := gen_payload(kh2,10); + cc.seq_nr := gen_sn(27); + cc.src_timestamp := gen_duration(27,0); + + Log("DDS Operation WRITE [TS 27s, Instance 2, HANDLE_NIL, Aligned Payload] (REJECTED: MAX_INSTANCES exceeded)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.cc.instance:= HANDLE_NIL; + stimulus.ret_code := RETCODE_OUT_OF_RESOURCES; + start_stim; + wait_on_stim; + + cc.serialized_key := TRUE; + cc.kind := NOT_ALIVE_UNREGISTERED; + cc.instance := kh3; + cc.payload := gen_payload(kh3,5); + cc.seq_nr := gen_sn(27); + cc.src_timestamp := gen_duration(27,0); + + Log("DDS Operation UNREGISTER_INSTANCE [TS 27s, Instance 3] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := UNREGISTER_INSTANCE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc2 := cc; + -- Stored CC: I3S23, I3S27, I4S25, I1S26 + + cc.serialized_key := TRUE; + cc.kind := NOT_ALIVE_DISPOSED; + cc.instance := kh3; + cc.payload := gen_payload(kh3,5); + cc.seq_nr := gen_sn(28); + cc.src_timestamp := gen_duration(28,0); + + -- TEST: DISPOSE ON UNREGISTERED INSTANCE + + Log("DDS Operation DISPOSE [TS 28s, Instance 3] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := DISPOSE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc1 := cc; + -- Stored CC: I3S28, I3S27, I4S25, I1S26 + + Log("RTPS Operation ACK_CACHE_CHANGE SN 27", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := ACK_CACHE_CHANGE; + reference.cc := cc2; + start_ref; + wait_on_ref; + + Log("RTPS Operation ACK_CACHE_CHANGE SN 28", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := ACK_CACHE_CHANGE; + reference.cc := cc1; + start_ref; + wait_on_ref; + + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh2; + cc.payload := gen_payload(kh2,10); + cc.seq_nr := gen_sn(29); + cc.src_timestamp := gen_duration(29,0); + + Log("DDS Operation WRITE [TS 29s, Instance 2, HANDLE_NIL, Aligned Payload] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.cc.instance:= HANDLE_NIL; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc1 := cc; + -- Stored CC: I2S29, 0, I4S25, I1S26 + + -- VALIDATE STATE + + Log("RTPS Operation GET_MIN_SN (Expected SN 25)", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_MIN_SN; + reference.cc.seq_nr := gen_sn(25); + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_MAX_SN (Expected SN 28)", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_MAX_SN; + reference.cc.seq_nr := gen_sn(29); + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_CACHE_CHANGE SN 25", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_CACHE_CHANGE; + reference.cc := cc3; + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_CACHE_CHANGE SN 26", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_CACHE_CHANGE; + reference.cc := cc4; + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_CACHE_CHANGE SN 29", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_CACHE_CHANGE; + reference.cc := cc1; + start_ref; + wait_on_ref; + + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh2; + cc.payload := gen_payload(kh2,10); + cc.seq_nr := gen_sn(30); + cc.src_timestamp := gen_duration(30,0); + + Log("DDS Operation WRITE [TS 30s, Instance 2, Aligned Payload] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc2 := cc; + -- Stored CC: I2S29, I2S30, I4S25, I1S26 + + Log("RTPS Operation ACK_CACHE_CHANGE SN 25", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := ACK_CACHE_CHANGE; + reference.cc := cc3; + start_ref; + wait_on_ref; + + Log("RTPS Operation ACK_CACHE_CHANGE SN 26", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := ACK_CACHE_CHANGE; + reference.cc := cc4; + start_ref; + wait_on_ref; + + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh4; + cc.payload := gen_payload(kh4,10); + cc.seq_nr := gen_sn(31); + cc.src_timestamp := gen_duration(31,0); + + -- TEST: ADD SAMPLE ON MAX_SAMPLES [KNOWN INSTANCE,WITH ACKed SAMPLES (>1)] + + Log("DDS Operation WRITE [TS 31s, Instance 4, Aligned Payload] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc3 := cc; + -- Stored CC: I2S29, I2S30, I4S31, I1S26 + + Log("RTPS Operation REMOVE_CACHE_CHANGE SN 31", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := REMOVE_CACHE_CHANGE; + reference.cc := cc3; + start_ref; + wait_on_ref; + -- Stored CC: I2S29, I2S30, 0, I1S26 + + Log("RTPS Operation ACK_CACHE_CHANGE SN 29", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := ACK_CACHE_CHANGE; + reference.cc := cc1; + start_ref; + wait_on_ref; + + Log("RTPS Operation ACK_CACHE_CHANGE SN 30", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := ACK_CACHE_CHANGE; + reference.cc := cc2; + start_ref; + wait_on_ref; + + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh2; + cc.payload := gen_payload(kh2,10); + cc.seq_nr := gen_sn(32); + cc.src_timestamp := gen_duration(32,0); + + -- TEST: ADD SAMPLE ON MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE, WITH ACKed INSTANCE SAMPLES(>1)] + + Log("DDS Operation WRITE [TS 32s, Instance 2, Aligned Payload] (ACCEPTED)", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := WRITE; + stimulus.cc := cc; + stimulus.ret_code := RETCODE_OK; + start_stim; + wait_on_stim; + cc1 := cc; + -- Stored CC: I2S32, I2S30, 0, I1S26 + + -- VALIDATE STATE + + Log("RTPS Operation GET_MIN_SN (Expected SN 26)", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_MIN_SN; + reference.cc.seq_nr := gen_sn(26); + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_MAX_SN (Expected SN 32)", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_MAX_SN; + reference.cc.seq_nr := gen_sn(32); + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_CACHE_CHANGE SN 26", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_CACHE_CHANGE; + reference.cc := cc4; + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_CACHE_CHANGE SN 30", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_CACHE_CHANGE; + reference.cc := cc2; + start_ref; + wait_on_ref; + + Log("RTPS Operation GET_CACHE_CHANGE SN 32", INFO); + reference := DEFAULT_RTPS_TEST; + reference.opcode := GET_CACHE_CHANGE; + reference.cc := cc1; + start_ref; + wait_on_ref; + + -- TEST: INSTANCE LOOKUP [KNOWN INSTANCE] + + Log("DDS Operation LOOKUP_INSTANCE [Instance 2]", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := LOOKUP_INSTANCE; + stimulus.cc := cc; + start_stim; + wait_on_stim; + + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh3; + cc.payload := gen_payload(kh3,10); + + -- TEST: INSTANCE LOOKUP [UNKNOWN INSTANCE] + + Log("DDS Operation LOOKUP_INSTANCE [Unknown Instance]", INFO); + stimulus := DEFAULT_DDS_TEST; + stimulus.opcode := LOOKUP_INSTANCE; + stimulus.cc := cc; + stimulus.cc.instance:= HANDLE_NIL; + start_stim; + wait_on_stim; + + wait_on_completion; + TranscriptOpen(RESULTS_FILE, APPEND_MODE); + SetTranscriptMirror; + ReportAlerts; + TranscriptClose; + std.env.stop; + wait; + end process; + + clock_prc : process + begin + clk <= '0'; + wait for 25 ns; + clk <= '1'; + wait for 25 ns; + end process; + + alert_prc : process(all) + begin + if rising_edge(clk) then + -- TODO + end if; + end process; + + stim_prc : process(all) + begin + if rising_edge(clk) then + stim_done <= '0'; + case (stim_stage) is + when IDLE => + if (stim_start = '1') then + stim_stage <= START; + else + stim_done <= '1'; + end if; + when START => + if (ack_dds = '1') then + stim_stage <= PUSH; + stim_cnt <= 0; + end if; + when PUSH => + if (ready_in_dds = '1') then + stim_cnt <= stim_cnt + 1; + if (stim_cnt = stimulus.cc.payload.length-1) then + -- DEFAULT + stim_stage <= DONE; + + case (stimulus.opcode) is + when REGISTER_INSTANCE => + stim_stage <= CHECK; + stim_cnt <= 0; + when LOOKUP_INSTANCE => + stim_stage <= CHECK; + stim_cnt <= 0; + when others => + null; + end case; + end if; + end if; + when DONE => + if (done_dds = '1') then + AffirmIfEqual(ret_id, return_code_dds, stimulus.ret_code); + stim_stage <= IDLE; + end if; + when CHECK => + if (valid_out_dds = '1') then + AffirmIfEqual(data_id, data_out_dds, stimulus.cc.instance(stim_cnt)); + stim_cnt <= stim_cnt + 1; + if (stim_cnt = 3) then + AlertIf(data_id, last_word_out_dds /= '1', "Last Word Signal not pulled High", ERROR); + stim_stage <= IDLE; + end if; + end if; + end case; + end if; + + -- DEFAULT + start_dds <= '0'; + valid_in_dds <= '0'; + last_word_in_dds <= '0'; + data_in_dds <= (others => '0'); + instance_handle_dds <= HANDLE_NIL; + source_ts_dds <= TIME_INVALID; + ready_out_dds <= '0'; + + case (stim_stage) is + when START => + start_dds <= '1'; + opcode_dds <= stimulus.opcode; + instance_handle_dds <= stimulus.cc.instance; + source_ts_dds <= stimulus.cc.src_timestamp; + when PUSH => + valid_in_dds <= '1'; + data_in_dds <= stimulus.cc.payload.data(stim_cnt); + last_word_in_dds <= stimulus.cc.payload.last(stim_cnt); + when CHECK => + ready_out_dds <= '1'; + when others => + null; + end case; + end process; + + ref_prc : process(all) + begin + if rising_edge(clk) then + ref_done <= '0'; + case (ref_stage) is + when IDLE => + if (ref_start = '1') then + ref_stage <= START; + else + ref_done <= '1'; + end if; + when START => + if (ack_rtps = '1') then + ref_stage <= DONE; + end if; + when DONE => + if (done_rtps = '1') then + -- DEFAULT + ref_stage <= IDLE; + + AffirmIfEqual(ret_id, HISTORY_CACHE_RESPONSE_TYPE'pos(ret_rtps), HISTORY_CACHE_RESPONSE_TYPE'pos(reference.ret_code)); + case (reference.opcode) is + when GET_CACHE_CHANGE => + if (reference.ret_code = OK) then + AffirmIfEqual(inst_id, cc_instance_handle(0), reference.cc.instance(0)); + AffirmIfEqual(inst_id, cc_instance_handle(1), reference.cc.instance(1)); + AffirmIfEqual(inst_id, cc_instance_handle(2), reference.cc.instance(2)); + AffirmIfEqual(inst_id, cc_instance_handle(3), reference.cc.instance(3)); + AffirmIfEqual(kind_id, CACHE_CHANGE_KIND_TYPE'pos(cc_kind), CACHE_CHANGE_KIND_TYPE'pos(reference.cc.kind)); + AffirmIfEqual(sn_id, convert_from_double_word(cc_seq_nr), convert_from_double_word(reference.cc.seq_nr)); + AffirmIfEqual(ts_id, convert_from_double_word(cc_source_timestamp), convert_from_double_word(reference.cc.src_timestamp)); + ref_stage <= CHECK; + ref_cnt <= 0; + end if; + when GET_MIN_SN => + AffirmIfEqual(sn_id, convert_from_double_word(cc_seq_nr), convert_from_double_word(reference.cc.seq_nr)); + when GET_MAX_SN => + AffirmIfEqual(sn_id, convert_from_double_word(cc_seq_nr), convert_from_double_word(reference.cc.seq_nr)); + when others => + null; + end case; + end if; + when CHECK => + if (valid_out_rtps = '1') then + AffirmIfEqual(data_id, last_word_out_rtps & data_out_rtps, reference.cc.payload.last(ref_cnt) & reference.cc.payload.data(ref_cnt)); + ref_cnt <= ref_cnt + 1; + if (ref_cnt = reference.cc.payload.length-1) then + ref_stage <= IDLE; + end if; + end if; + end case; + end if; + + -- DEFAULT + start_rtps <= '0'; + get_data_rtps <= '0'; + ready_out_rtps <= '0'; + + case (ref_stage) is + when START => + start_rtps <= '1'; + opcode_rtps <= reference.opcode; + seq_nr_rtps <= reference.cc.seq_nr; + when DONE => + if (done_rtps = '1') then + case (reference.opcode) is + when GET_CACHE_CHANGE => + get_data_rtps <= '1'; + when others => + null; + end case; + end if; + when CHECK => + ready_out_rtps <= '1'; + when others => + null; + end case; + end process; + + kh_prc : process (all) + variable tmp_key_hash : INSTANCE_HANDLE_TYPE := HANDLE_NIL; + begin + if rising_edge(clk) then + case (kh_stage) is + when IDLE => + if (start_kh = '1') then + case (opcode_kh) is + when PUSH_DATA => + kh_stage <= READ_DATA; + kh_cnt <= 0; + kh_data <= EMPTY_TEST_PACKET; + when PUSH_SERIALIZED_KEY => + kh_stage <= READ_DATA; + kh_cnt <= 0; + kh_data <= EMPTY_TEST_PACKET; + when READ_KEY_HASH => + kh_stage <= PUSH_KEY_HASH; + kh_cnt <= 0; + when others => + Alert("Unexpected Key Holder Operation", FAILURE); + end case; + end if; + when READ_DATA => + if (valid_out_kh = '1') then + kh_data.data(kh_cnt) <= data_out_kh; + kh_data.last(kh_cnt) <= last_word_out_kh; + kh_data.length <= kh_data.length + 1; + + kh_cnt <= kh_cnt + 1; + if (last_word_out_kh = '1') then + kh_stage <= IDLE; + end if; + end if; + when PUSH_KEY_HASH => + if (ready_in_kh = '1') then + kh_cnt <= kh_cnt + 1; + if (kh_cnt = INSTANCE_HANDLE_TYPE'length-1) then + kh_stage <= IDLE; + end if; + end if; + end case; + end if; + + -- DEFAULT + ack_kh <= '0'; + ready_out_kh <= '0'; + valid_in_kh <= '0'; + data_in_kh <= (others => '0'); + last_word_in_kh <= '0'; + + case (kh_stage) is + when IDLE => + if (start_kh = '1') then + ack_kh <= '1'; + end if; + when READ_DATA => + ready_out_kh <= '1'; + when PUSH_KEY_HASH => + valid_in_kh <= '1'; + tmp_key_hash := extract_key_hash(kh_data); + data_in_kh <= tmp_key_hash(kh_cnt); + if (kh_cnt = INSTANCE_HANDLE_TYPE'length-1) then + last_word_in_kh <= '1'; + end if; + end case; + end process; + + watchdog : process + begin + wait for 1 ms; + Alert("Test timeout", FAILURE); + std.env.stop; + end process; + +end architecture; \ No newline at end of file diff --git a/src/Tests/Level_0/dds_writer_tests.txt b/src/Tests/Level_0/dds_writer_tests.txt new file mode 100644 index 0000000..e3cee7e --- /dev/null +++ b/src/Tests/Level_0/dds_writer_tests.txt @@ -0,0 +1,81 @@ +-- TEST: GET_MIN_SN/GET_MAX_SN ON EMPTY +-- TEST: GET_MIN_SN/GET_MAX_SN ON 1 SAMPLE +-- TEST: GET_MIN_SN/GET_MAX_SN ON >1 SAMPLE + +-- TEST: ADD SAMPLE WITH KEY_HASH [UNKNOWN INSTANCE] +-- TEST: ADD SAMPLE WITH KEY_HASH [KNOWN INSTANCE] +-- TEST: ADD SAMPLE WITH HANDLE_NIL [UNKNOWN INSTANCE] +-- TEST: ADD SAMPLE WITH HANDLE_NIL [KNOWN INSTANCE] + +-- TEST: NORMAL WRITE +-- TEST: WRITE ON PAYLOAD MEMORY FULL [WITHOUT ACKed SAMPLES] +-- TEST: WRITE ON PAYLOAD MEMORY FULL [WITH ACKed SAMPLES] +-- TEST: WRITE ON DISPOSED INSTANCE +-- TEST: WRITE ON UNREGISTERED INSTANCE + +-- TEST: WRITE ALIGNED PAYLOAD +-- TEST: WRITE UNALIGNED PAYLOAD [>1 SLOT] +-- TEST: WRITE UNALIGNED PAYLOAD [<1 SLOT] + +-- TEST: NORMAL REGISTER +-- TEST: REGISTER INSTANCE [KNOWN INSTANCE] +-- TEST: REGISTER INSTANCE ON MAX_INSTANCES [UNKNOWN INSTANCE, WITHOUT STALE INSTANCE] +-- TEST: REGISTER INSTANCE ON MAX_INSTANCES [UNKNOWN INSTANCE, WITH STALE INSTANCE] +-- TEST: REGISTER ON UNREGISTERED INSTANCE + +-- TEST: NORMAL DISPOSE +-- TEST: DISPOSE ON PAYLOAD MEMORY FULL [WITHOUT ACKed SAMPLES] +-- TEST: DISPOSE ON PAYLOAD MEMORY FULL [WITH ACKed SAMPLES] +-- TEST: DISPOSE ON UNREGISTERED INSTANCE + +-- TEST: GET_CACHE_CHANGE [UNKNOWN SN] +-- TEST: GET_CACHE_CHANGE [KNOWN SN, ALIGNED PAYLOAD] +-- TEST: GET_CACHE_CHANGE [KNOWN SN, UNALIGNED PAYLOAD, >1 SLOT] +-- TEST: GET_CACHE_CHANGE [KNOWN SN, UNALIGNED PAYLOAD, <1 SLOT] + +-- TEST: NORMAL ACK_CACHE_CHANGE +-- TEST: ACK_CACHE_CHANGE [ALREADY ACKed SN] +-- TEST: NORMAL NACK_CACHE_CHANGE + +-- TEST: REMOVE_CACHE_CHANGE [UNKNOWN SN] +-- TEST: REMOVE_CACHE_CHANGE [KNOWN SN] + +-- TEST: NORMAL UNREGISTER +-- TEST: UNREGISTER INSTANCE ON PAYLOAD MEMORY FULL [WITHOUT ACKed SAMPLES] +-- TEST: UNREGISTER INSTANCE ON PAYLOAD MEMORY FULL [WITH ACKed SAMPLES] +-- TEST: UNREGISTER ON DISPOSED INSTANCE +-- TEST: UNREGISTER UNKNOWN INSTANCE + +-- TEST: REMOVE STALE INSTANCE WITH 0 SAMPLES +-- TEST: REMOVE STALE INSTANCE WITH 1 SAMPLES +-- TEST: REMOVE STALE INSTANCE WITH >1 SAMPLES + +-- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKNOWN INSTANCE, WITH STALE INSTANCE] +-- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKNOWN INSTANCE, WITHOUT STALE INSTANCES] +-- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKNOWN INSTANCE, WITH FULLY ACKed INSTANCE, WITHOUT STALE INSTANCE] + +-- TEST: ADD SAMPLE ON MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE, WITHOUT ACKed SAMPLES] +-- TEST: ADD SAMPLE ON MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE, WITH ACKed SAMPLES, WITHOUT ACKed INSTANCE SAMPLES] +-- TEST: ADD SAMPLE ON MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE, WITH ACKed INSTANCE SAMPLE] +-- TEST: ADD SAMPLE ON MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE, WITH ACKed INSTANCE SAMPLES(>1)] + +-- TEST: ADD SAMPLE ON MAX_SAMPLES [KNOWN INSTANCE,WITHOUT ACKed SAMPLES] +-- TEST: ADD SAMPLE ON MAX_SAMPLES [KNOWN INSTANCE,WITH ACKed SAMPLE] +-- TEST: ADD SAMPLE ON MAX_SAMPLES [KNOWN INSTANCE,WITH ACKed SAMPLES (>1)] + +-- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE,WITHOUT ACKed SAMPLES] +-- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE,WITH ACKed SAMPLES, WITHOUT ACKed INSTANCE SAMPLES] +-- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE,WITH ACKed INSTANCE SAMPLES] + +-- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE,WITH STALE INSTANCE, WITHOUT ACKed SAMPLE] +-- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE,WITHOUT STALE INSTANCES,WITHOUT ACKed SAMPLES] +-- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE,WITHOUT STALE INSTANCE, WITH ACKed SAMPLE] +-- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE,WITH STALE INSTANCE (>0 SAMPLES)] +-- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE,WITH STALE INSTANCE, WITH ACKed SAMPLE] + +-- TEST: ADD SAMPLE ON PAYLOAD FULL & MAX_INSTANCES [UNKNOWN INSTANCE,WITH ACKed SAMPLES,WITH STALE INSTANCE (>= 1 SAMPLE)] (Induce Double Remove) + +-- TEST: ADD SAMPLE BIGGER THAN AVAILABLE MEMORY SPACE [WITH ACKed SAMPLES] + +-- TEST: INSTANCE LOOKUP [KNOWN INSTANCE] +-- TEST: INSTANCE LOOKUP [UNKNOWN INSTANCE] \ No newline at end of file diff --git a/src/Tests/testbench.pro b/src/Tests/testbench.pro index 61d86fa..852e519 100644 --- a/src/Tests/testbench.pro +++ b/src/Tests/testbench.pro @@ -18,6 +18,7 @@ analyze ../rtps_builtin_endpoint.vhd analyze ../rtps_out.vhd analyze ../rtps_reader.vhd analyze ../rtps_writer.vhd +analyze ../dds_writer.vhd analyze Level_0/L0_rtps_handler_test1.vhd analyze Level_0/L0_rtps_handler_test2.vhd analyze Level_0/L0_rtps_builtin_endpoint_test1.vhd @@ -53,6 +54,10 @@ analyze Level_1/L1_rtps_writer_test1_vrkdn.vhd analyze Level_1/L1_rtps_writer_test1_trkdn.vhd analyze Level_1/L1_rtps_writer_test2_vrkdn.vhd analyze Level_0/L0_rtps_writer_test2_vrkdp.vhd +analyze Level_0/L0_dds_writer_test1_aik.vhd +analyze Level_0/L0_dds_writer_test1_ain.vhd +analyze Level_0/L0_dds_writer_test1_lik.vhd +analyze Level_0/L0_dds_writer_test1_afk.vhd #simulate L0_rtps_handler_test1 #simulate L0_rtps_handler_test2 @@ -88,4 +93,8 @@ analyze Level_0/L0_rtps_writer_test2_vrkdp.vhd #simulate L1_rtps_writer_test1_vrkdn #simulate L1_rtps_writer_test1_trkdn #simulate L1_rtps_writer_test2_vrkdn -simulate L0_rtps_writer_test2_vrkdp \ No newline at end of file +#simulate L0_rtps_writer_test2_vrkdp +simulate L0_dds_writer_test1_aik +#simulate L0_dds_writer_test1_ain +#simulate L0_dds_writer_test1_lik +#simulate L0_dds_writer_test1_afk \ No newline at end of file diff --git a/src/dds_writer.vhd b/src/dds_writer.vhd index 37c9217..f560f0b 100644 --- a/src/dds_writer.vhd +++ b/src/dds_writer.vhd @@ -12,15 +12,9 @@ use work.rtps_config_package.all; entity dds_writer is generic ( HISTORY_QOS : std_logic_vector(CDR_ENUMERATION_WIDTH-1 downto 0); - RELIABILITY_QOS : std_logic_vector(CDR_ENUMERATION_WIDTH-1 downto 0); - PRESENTATION_QOS : std_logic_vector(CDR_ENUMERATION_WIDTH-1 downto 0); - DESTINATION_ORDER_QOS : std_logic_vector(CDR_ENUMERATION_WIDTH-1 downto 0); DEADLINE_QOS : DURATION_TYPE; - TIME_BASED_FILTER_QOS : DURATION_TYPE; LIFESPAN_QOS : DURATION_TYPE; LEASE_DURATION : DURATION_TYPE; - COHERENT_ACCESS : boolean; - ORDERED_ACCESS : boolean; WITH_KEY : boolean; MAX_SAMPLES : std_logic_vector(CDR_LONG_WIDTH-1 downto 0); MAX_INSTANCES : std_logic_vector(CDR_LONG_WIDTH-1 downto 0); @@ -53,7 +47,7 @@ entity dds_writer is cc_seq_nr : out SEQUENCENUMBER_TYPE; -- TO/FROM KEY_HOLDER start_kh : out std_logic; - opcode_kh : out KEY_HOLDER_TYPE; + opcode_kh : out KEY_HOLDER_OPCODE_TYPE; ack_kh : in std_logic; data_in_kh : in std_logic_vector(WORD_WIDTH-1 downto 0); valid_in_kh : in std_logic; @@ -91,31 +85,42 @@ architecture arch of dds_writer is --*****CONSTANT DECLARATION***** -- *SAMPLE MEMORY* -- 4-Byte Word Size of a Remote Endpoint Entry in Memory - function gen_frame_size(lifespan : DURATION_TYPE) return natural is + function gen_frame_size(lifespan : DURATION_TYPE; WITH_KEY : boolean) return natural is variable ret : natural := 0; begin - ret := 11 when (lifespan /= DURATION_INFINITE) else 9; - return ret; + if (lifespan /= DURATION_INFINITE and WITH_KEY) then + return 11; + elsif (lifespan /= DURATION_INFINITE and (not WITH_KEY)) then + return 10; + elsif (lifespan = DURATION_INFINITE and WITH_KEY) then + return 9; + else --lifespan = DURATION_INFINITE and (not WITH_KEY) + return 8; + end if; end function; - constant SAMPLE_FRAME_SIZE : natural := gen_frame_size(LIFESPAN_QOS); + constant SAMPLE_FRAME_SIZE : natural := gen_frame_size(LIFESPAN_QOS,WITH_KEY); -- Sample Info Memory Size in 4-Byte Words - constant SAMPLE_MEMORY_SIZE : natural := to_integer(unsigned(MAX_SAMPLES)) * SAMPLE_FRAME_SIZE; + constant SAMPLE_MEMORY_SIZE : natural := to_integer(unsigned(MAX_SAMPLES)+1) * SAMPLE_FRAME_SIZE; -- Sample Info Memory Address Width constant SAMPLE_MEMORY_ADDR_WIDTH : natural := log2c(SAMPLE_MEMORY_SIZE); -- Highest Sample Info Memory Address constant SAMPLE_MEMORY_MAX_ADDRESS : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) := to_unsigned(SAMPLE_MEMORY_SIZE-1, SAMPLE_MEMORY_ADDR_WIDTH); -- Highest Sample Info Frame Address constant MAX_SAMPLE_ADDRESS : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) := SAMPLE_MEMORY_MAX_ADDRESS - SAMPLE_FRAME_SIZE + 1; + -- Address pointing to the beginning of the first Sample Data Frame + constant FIRST_SAMPLE_ADDRESS : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); -- *PAYLOAD MEMORY* -- Payload Memory Size in 4-Byte Words - constant PAYLOAD_MEMORY_SIZE : natural := to_integer(unsigned(MAX_SAMPLES)) * PAYLOAD_FRAME_SIZE; + constant PAYLOAD_MEMORY_SIZE : natural := to_integer(unsigned(MAX_SAMPLES)+1) * PAYLOAD_FRAME_SIZE; -- Payload Memory Address Width constant PAYLOAD_MEMORY_ADDR_WIDTH : natural := log2c(PAYLOAD_MEMORY_SIZE); -- Highest Payload Memory Address constant PAYLOAD_MEMORY_MAX_ADDRESS : unsigned(PAYLOAD_MEMORY_ADDR_WIDTH-1 downto 0) := to_unsigned(PAYLOAD_MEMORY_SIZE-1, PAYLOAD_MEMORY_ADDR_WIDTH); -- Highest Payload Frame Address constant MAX_PAYLOAD_ADDRESS : unsigned(PAYLOAD_MEMORY_ADDR_WIDTH-1 downto 0) := PAYLOAD_MEMORY_MAX_ADDRESS - PAYLOAD_FRAME_SIZE + 1; + -- Address pointing to the beginning of the first Payload Data Frame + constant FIRST_PAYLOAD_ADDRESS : unsigned(PAYLOAD_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); -- *INSTANCE MEMORY* -- 4-Byte Word Size of a Remote Endpoint Entry in Memory @@ -140,11 +145,17 @@ architecture arch of dds_writer is function gen_smf_payload_addr_offset(lifespan : DURATION_TYPE) return natural is variable ret : natural := 0; begin - ret := (SMF_LIFESPAN_DEADLINE_OFFSET + 2) when (lifespan /= DURATION_INFINITE) else (SMF_TIMESTAMP_OFFSET + 2); + ret := (SMF_LIFESPAN_DEADLINE_OFFSET + 2) when (lifespan /= DURATION_INFINITE) else SMF_LIFESPAN_DEADLINE_OFFSET; return ret; end function; constant SMF_PAYLOAD_ADDR_OFFSET : natural := gen_smf_payload_addr_offset(LIFESPAN_QOS); - constant SMF_INSTANCE_ADDR_OFFSET : natural := SMF_PAYLOAD_ADDR_OFFSET + 1; + function gen_smf_instance_addr_offset(WITH_KEY : boolean) return natural is + variable ret : natural := 0; + begin + ret := (SMF_PAYLOAD_ADDR_OFFSET + 1) when WITH_KEY else SMF_PAYLOAD_ADDR_OFFSET; + return ret; + end function; + constant SMF_INSTANCE_ADDR_OFFSET : natural := gen_smf_instance_addr_offset(WITH_KEY); constant SMF_PREV_ADDR_OFFSET : natural := SMF_INSTANCE_ADDR_OFFSET + 1; constant SMF_NEXT_ADDR_OFFSET : natural := SMF_PREV_ADDR_OFFSET + 1; @@ -173,11 +184,11 @@ architecture arch of dds_writer is -- FSM states. Explained below in detail type STAGE_TYPE is (IDLE, UNKNOWN_OPERATION_DDS, UNKNOWN_OPERATION_RTPS, UNKNOWN_SEQ_NR, ASSERT_LIVELINESS, ADD_SAMPLE_INFO, ADD_PAYLOAD, NEXT_PAYLOAD_SLOT, ALIGN_PAYLOAD, GET_KEY_HASH, INITIATE_INSTANCE_SEARCH, REGISTER_OPERATION, LOOKUP_OPERATION, PUSH_KEY_HASH, FILTER_STAGE, UPDATE_INSTANCE, - FINALIZE_PAYLOAD, FIX_POINTERS, FINALIZE_SAMPLE, GET_OLDEST_SAMPLE_INSTANCE, FIND_OLDEST_INST_SAMPLE, REMOVE_ORPHAN_SAMPLES, REMOVE_SAMPLE, - POST_SAMPLE_REMOVE, SKIP_ADD_REJECT, REMOVE_STALE_INSTANCE, GET_SEQ_NR, FIND_SEQ_NR, ACKNACK_SAMPLE, GET_SAMPLE, GET_PAYLOAD, GET_SERIALIZED_KEY, + FINALIZE_PAYLOAD, FINALIZE_SAMPLE, GET_OLDEST_SAMPLE_INSTANCE, FIND_SAMPLE, REMOVE_ORPHAN_SAMPLES, REMOVE_SAMPLE, + POST_SAMPLE_REMOVE, SKIP_AND_RETURN, SKIP, REMOVE_STALE_INSTANCE, GET_SEQ_NR, FIND_SEQ_NR, ACKNACK_SAMPLE, GET_SAMPLE, GET_PAYLOAD, GET_SERIALIZED_KEY, CHECK_LIFESPAN, GET_LIVELINESS_LOST_STATUS, GET_OFFERED_DEADLINE_MISSED_STATUS, CHECK_DEADLINE, RESET_SAMPLE_MEMORY, RESET_PAYLOAD_MEMORY); -- Instance Memory FSM states. Explained below in detail - type INST_STAGE_TYPE is (IDLE, SEARCH_INSTANCE_HASH, SEARCH_INSTANCE_ADDR, GET_NEXT_INSTANCE, GET_INSTANCE_DATA, FIND_POS, INSERT_INSTANCE, UPDATE_INSTANCE, + type INST_STAGE_TYPE is (IDLE, SEARCH_INSTANCE_HASH, SEARCH_INSTANCE_ADDR, GET_NEXT_INSTANCE, GET_INSTANCE_DATA, INSERT_INSTANCE, UPDATE_INSTANCE, REMOVE_INSTANCE, RESET_MEMORY); -- *Instance Memory Opcodes* -- OPCODE DESCRIPTION @@ -242,7 +253,7 @@ architecture arch of dds_writer is signal payload_abort_read : std_logic := '0'; -- *INSTANCE MEMORY CONNECTION SIGNALS* - signal inst_addr : unsigned(PAYLOAD_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); + signal inst_addr : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); signal inst_read : std_logic := '0'; signal inst_read_data, inst_write_data : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); signal inst_ready_in, inst_valid_in : std_logic := '0'; @@ -257,7 +268,7 @@ architecture arch of dds_writer is -- General Purpose Counter signal cnt, cnt_next : natural range 0 to 14 := 0; -- Counter used to read/write Payload Fames - signal cnt2, cnt2_next : natural range 0 to PAYLOAD_FRAME_SIZE := 0; + signal cnt2, cnt2_next : natural range 0 to max(PAYLOAD_FRAME_SIZE, INSTANCE_HANDLE_TYPE'length-1) := 0; -- Counter used to read/write Payload Fames signal cnt3, cnt3_next : natural range 0 to PAYLOAD_FRAME_SIZE := 0; -- Head of Empty Sample List @@ -274,10 +285,14 @@ architecture arch of dds_writer is signal remove_oldest_sample, remove_oldest_sample_next : std_logic := '0'; -- Denotes if the oldest sample of the Instance with 'key_hash' should be removed signal remove_oldest_inst_sample, remove_oldest_inst_sample_next : std_logic := '0'; + -- Denotes if the Sample tobe removed should be ACKed + signal remove_ack_sample, remove_ack_sample_next : std_logic := '0'; -- Lifespan Latch signal lifespan, lifespan_next : TIME_TYPE := TIME_INVALID; -- Key hash Latch signal key_hash, key_hash_next : KEY_HASH_TYPE := (others => (others => '0')); + -- Return Code Latch + signal return_code_latch, return_code_latch_next : std_logic_vector(RETURN_CODE_WIDTH-1 downto 0) := (others => '0'); -- Instance Handle Latch signal instance_handle, instance_handle_next : INSTANCE_HANDLE_TYPE := HANDLE_NIL; -- Source Timestamp Latch @@ -330,9 +345,9 @@ architecture arch of dds_writer is -- It contains the next applicable Sequence Number signal global_seq_nr, global_seq_nr_next : SEQUENCENUMBER_TYPE := SEQUENCENUMBER_UNKNOWN; -- Signal containing the current number of stored samples - signal global_sample_cnt, global_sample_cnt_next : natural range 0 to to_integer(unsigned(MAX_SAMPLES)) := 0; + signal global_sample_cnt, global_sample_cnt_next : natural range 0 to to_integer(unsigned(MAX_SAMPLES)+1) := 0; -- Signal containing the current number of ACKed stored samples - signal global_ack_cnt, global_ack_cnt_next : natural range 0 to to_integer(unsigned(MAX_SAMPLES)) := 0; + signal global_ack_cnt, global_ack_cnt_next : natural range 0 to to_integer(unsigned(MAX_SAMPLES)+1) := 0; -- Signal containing the number of currently stale Instances signal stale_inst_cnt, stale_inst_cnt_next : natural range 0 to to_integer(unsigned(MAX_INSTANCES)) := 0; -- Signifies if a Instance Register Operation is in progress @@ -393,8 +408,10 @@ architecture arch of dds_writer is signal inst_occupied_head, inst_occupied_head_next : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); -- Latch for Instance Data from main process signal inst_latch_data, inst_latch_data_next : INST_LATCH_DATA_TYPE := ZERO_INST_LATCH_DATA; + -- NOTE: The next signal is driven by the inst_ctrl_prc. In case WITH_KEY is FALSE, no inst_ctrl_prc is generated and the inst_data is + -- set by the main process directly by drivng the next2 signal. The sync_prc is responsible for latching the corrct next signal. -- Latch for Instance Data from memory - signal inst_data, inst_data_next : INSTANCE_DATA_TYPE := ZERO_INSTANCE_DATA; + signal inst_data, inst_data_next, inst_data_next2 : INSTANCE_DATA_TYPE := ZERO_INSTANCE_DATA; -- General Purpose Counter signal inst_cnt, inst_cnt_next : natural range 0 to 13 := 0; -- Counter used to read/write the Writer Bitmap @@ -403,26 +420,26 @@ architecture arch of dds_writer is signal inst_long_latch, inst_long_latch_next : std_logic_vector(CDR_LONG_WIDTH-1 downto 0) := (others => '0'); --*****ALIAS DECLARATION***** - alias prev_sample : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) is sample_addr_latch_1; - alias prev_sample_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) is sample_addr_latch_1_next; - alias first_sample : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) is sample_addr_latch_1; - alias first_sample_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) is sample_addr_latch_1_next; - alias next_sample : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) is sample_addr_latch_2; - alias next_sample_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) is sample_addr_latch_2_next; - alias cur_sample : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) is sample_addr_latch_3; - alias cur_sample_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) is sample_addr_latch_3_next; - alias second_sample : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) is sample_addr_latch_4; - alias second_sample_next: unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) is sample_addr_latch_4_next; - alias cur_payload : unsigned(PAYLOAD_MEMORY_ADDR_WIDTH-1 downto 0) is payload_addr_latch_1; - alias cur_payload_next : unsigned(PAYLOAD_MEMORY_ADDR_WIDTH-1 downto 0) is payload_addr_latch_1_next; - alias next_payload : unsigned(PAYLOAD_MEMORY_ADDR_WIDTH-1 downto 0) is payload_addr_latch_2; - alias next_payload_next : unsigned(PAYLOAD_MEMORY_ADDR_WIDTH-1 downto 0) is payload_addr_latch_2_next; - alias cur_inst : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0) is inst_addr_latch_1; - alias cur_inst_next : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0) is inst_addr_latch_1_next; - alias next_inst : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0) is inst_addr_latch_2; - alias next_inst_next : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0) is inst_addr_latch_2_next; - alias dead_inst : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0) is inst_addr_latch_2; - alias dead_inst_next : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0) is inst_addr_latch_2_next; + alias prev_sample : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) is sample_addr_latch_1; + alias prev_sample_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) is sample_addr_latch_1_next; + alias next_sample : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) is sample_addr_latch_2; + alias next_sample_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) is sample_addr_latch_2_next; + alias cur_sample : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) is sample_addr_latch_3; + alias cur_sample_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) is sample_addr_latch_3_next; + alias new_sample : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) is sample_addr_latch_4; + alias new_sample_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) is sample_addr_latch_4_next; + alias cur_payload : unsigned(PAYLOAD_MEMORY_ADDR_WIDTH-1 downto 0) is payload_addr_latch_1; + alias cur_payload_next : unsigned(PAYLOAD_MEMORY_ADDR_WIDTH-1 downto 0) is payload_addr_latch_1_next; + alias next_payload : unsigned(PAYLOAD_MEMORY_ADDR_WIDTH-1 downto 0) is payload_addr_latch_2; + alias next_payload_next : unsigned(PAYLOAD_MEMORY_ADDR_WIDTH-1 downto 0) is payload_addr_latch_2_next; + alias first_payload : unsigned(PAYLOAD_MEMORY_ADDR_WIDTH-1 downto 0) is payload_addr_latch_2; + alias first_payload_next : unsigned(PAYLOAD_MEMORY_ADDR_WIDTH-1 downto 0) is payload_addr_latch_2_next; + alias cur_inst : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0) is inst_addr_latch_1; + alias cur_inst_next : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0) is inst_addr_latch_1_next; + alias next_inst : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0) is inst_addr_latch_2; + alias next_inst_next : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0) is inst_addr_latch_2_next; + alias dead_inst : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0) is inst_addr_latch_2; + alias dead_inst_next : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0) is inst_addr_latch_2_next; -- *FUNCTION DECLARATION* function to_unsigned(input : KEY_HASH_TYPE) return unsigned is @@ -467,8 +484,8 @@ begin ) port map ( clk => clk, - reset => reset or sample_abort_read, - addr => std_logic_vector(sample_addr), + reset => reset or payload_abort_read, + addr => std_logic_vector(payload_addr), read => payload_read, ready_in => payload_ready_in, valid_in => payload_valid_in, @@ -488,8 +505,8 @@ begin ) port map ( clk => clk, - reset => reset or sample_abort_read, - addr => std_logic_vector(sample_addr), + reset => reset or inst_abort_read, + addr => std_logic_vector(inst_addr), read => inst_read, ready_in => inst_ready_in, valid_in => inst_valid_in, @@ -506,6 +523,7 @@ begin cc_instance_handle <= cc_instance_handle_sig; cc_kind <= cc_kind_sig; cc_source_timestamp <= cc_source_timestamp_sig; + cc_seq_nr <= cc_seq_nr_sig; -- *Main State Machine* -- STATE DESCRIPTION @@ -526,14 +544,14 @@ begin -- FILTER_STAGE This state decides if the Cache Change is accepted, or rejected. It also decides what sample (if any) has to be removed. -- UPDATE_INSTANCE Update the Data of the Instance of the received saample (Cache Change) -- FINALIZE_PAYLOAD Finalize the payload addition (Update pointers). - -- FIX_POINTERS Update the List Pointers of the inserted Sample neighbours (First Step of Sample Addition Finalization) -- FINALIZE_SAMPLE Update inserted sample and list pointers. (Second Step of Sample Addition Finalization) -- GET_OLDEST_SAMPLE_INSTANCE Fetch the Instance Data of the oldest sample - -- FIND_OLDEST_INST_SAMPLE Find the oldest sample of a specific Instance + -- FIND_SAMPLE Find the specified Sample (Oldest ACKed Sample, Oldest Sample of specific Instance, Oldest ACKed Sample of specific Instance) -- REMOVE_ORPHAN_SAMPLES Remove all Samples of the removed Instance (dead_inst) -- REMOVE_SAMPLE Remove sample and linked payload -- POST_SAMPLE_REMOVE Update Instance Data of removed sample. If Instance Memory is full, and Instance is now eligible for removal, it is removed. - -- SKIP_ADD_REJECT Skip RTPS Cache Change and signal rejection to RTPS. + -- SKIP_AND_RETURN Skip DDS Input and return latched Return Code + -- SKIP Skip DDS Input and return to latched stage. -- REMOVE_STALE_INSTANCE Find and remove the first eligible Instance in the memory -- GET_SEQ_NR Push Sequence Number of specified Sample to RTPS output. -- FIND_SEQ_NR Find Sample with specified Sequence Number. @@ -572,6 +590,7 @@ begin sample_status_info_next <= sample_status_info; remove_oldest_sample_next <= remove_oldest_sample; remove_oldest_inst_sample_next <= remove_oldest_inst_sample; + remove_ack_sample_next <= remove_ack_sample; instance_handle_next <= instance_handle; sample_rej_cnt_next <= sample_rej_cnt; sample_rej_cnt_change_next <= sample_rej_cnt_change; @@ -605,11 +624,14 @@ begin cc_instance_handle_sig_next <= cc_instance_handle_sig; cc_kind_sig_next <= cc_kind_sig; cc_source_timestamp_sig_next <= cc_source_timestamp_sig; + cc_seq_nr_sig_next <= cc_seq_nr_sig; is_ack_next <= is_ack; is_rtps_next <= is_rtps; data_available_sig_next <= data_available_sig; orphan_samples_next <= orphan_samples; key_hash_next <= key_hash; + inst_data_next2 <= inst_data; + return_code_latch_next <= return_code_latch; -- DEFAULT Unregistered inst_opcode <= NOP; ret_rtps <= ERROR; @@ -638,6 +660,7 @@ begin ready_in_kh <= '0'; valid_out_kh <= '0'; last_word_out_kh <= '0'; + abort_kh <= '0'; data_out_kh <= (others => '0'); inst_addr_update <= (others => '0'); sample_addr <= (others => '0'); @@ -651,8 +674,9 @@ begin case (stage) is when IDLE => -- Reset - remove_oldest_inst_sample_next <= '0'; remove_oldest_sample_next <= '0'; + remove_oldest_inst_sample_next <= '0'; + remove_ack_sample_next <= '0'; lookup_op_next <= '0'; register_op_next <= '0'; is_rtps_next <= '0'; @@ -675,7 +699,7 @@ begin else if (inst_data.status_info(ISI_LIVELINESS_FLAG) = '1') then -- Reset Liveliness Flag - inst_data_next.status_info(ISI_LIVELINESS_FLAG) <= '0'; + inst_data_next2.status_info(ISI_LIVELINESS_FLAG) <= '0'; else -- Update Requested Deadline Missed Status status_sig_next <= status_sig and REQUESTED_DEADLINE_MISSED_STATUS; @@ -714,13 +738,15 @@ begin -- Samples Available if (oldest_sample /= SAMPLE_MEMORY_MAX_ADDRESS) then - cur_sample <= oldest_sample; + cur_sample_next <= oldest_sample; stage_next <= CHECK_LIFESPAN; cnt_next <= 0; end if; -- RTPS Operation elsif (start_rtps = '1') then is_rtps_next <= '1'; + -- Latch Input Signal + seq_nr_next <= seq_nr_rtps; -- Reset is_ack_next <= '0'; @@ -761,7 +787,6 @@ begin stage_next <= UNKNOWN_SEQ_NR; cc_seq_nr_sig_next <= SEQUENCENUMBER_UNKNOWN; else - seq_nr_next <= seq_nr_rtps; cc_seq_nr_sig_next <= seq_nr_rtps; cur_sample_next <= newest_sample; stage_next <= FIND_SEQ_NR; @@ -813,7 +838,7 @@ begin stage_next <= UNKNOWN_OPERATION_RTPS; end case; - -- DDS Operation + -- DDS Operation (Stall DDS Operation if a wait Operation is in progress) elsif (ack_wait = '0' and start_dds = '1') then -- Reset register_op_next <= '0'; @@ -821,17 +846,27 @@ begin source_ts_next <= TIME_INVALID; sample_status_info_next <= (others => '0'); key_hash_next <= HANDLE_NIL; + new_sample_next <= SAMPLE_MEMORY_MAX_ADDRESS; + return_code_latch_next <= RETCODE_UNSUPPORTED; case (opcode_dds) is when REGISTER_INSTANCE => - ack_dds <= '1'; -- Synthesis Guard if (WITH_KEY) then - register_op_next <= '1'; - stage_next <= ADD_PAYLOAD; - cnt_next <= 1; + start_kh <= '1'; + opcode_kh <= PUSH_DATA; + + if (ack_kh = '1') then + ack_dds <= '1'; + register_op_next <= '1'; + stage_next <= ADD_PAYLOAD; + cnt_next <= 1; + end if; else - stage_next <= UNKNOWN_OPERATION_DDS; + ack_dds <= '1'; + key_hash_next <= HANDLE_NIL; + stage_next <= SKIP; + return_stage_next <= PUSH_KEY_HASH; end if; when WRITE => ack_dds <= '1'; @@ -847,14 +882,48 @@ begin sample_status_info_next <= (SSI_PAYLOAD_FLAG => '1', SSI_ALIGNED_FLAG => '1', others => '0'); cur_sample_next <= empty_sample_list_head; - -- Instance Handle provided - if (WITH_KEY and instance_handle_dds /= HANDLE_NIL) then - key_hash_next <= instance_handle_dds; - stage_next <= INITIATE_INSTANCE_SEARCH; - cnt_next <= 0; + -- NOTE: We have to explicitly check the Payload Memory, as it may be "unaligned" with our Sample Memory + -- (Sample Memory has available Slot, but Payload Memory not) + -- Payload Memory Full + if (empty_payload_list_head = PAYLOAD_MEMORY_MAX_ADDRESS) then + if (global_ack_cnt = 0 and HISTORY_QOS = KEEP_ALL_HISTORY_QOS) then + -- Reject Change + stage_next <= SKIP_AND_RETURN; + cnt_next <= 0; + return_code_latch_next <= RETCODE_OUT_OF_RESOURCES; + else + assert (oldest_sample /= SAMPLE_MEMORY_MAX_ADDRESS) severity FAILURE; + -- Do not ACK Operation + ack_dds <= '0'; + + + if (global_ack_cnt /= 0) then + -- Accept Change (Remove Oldest ACKed Sample) + remove_oldest_sample_next <= '1'; + remove_ack_sample_next <= '1'; + + cur_sample_next <= oldest_sample; + stage_next <= FIND_SAMPLE; + cnt_next <= 0; + elsif (WITH_KEY) then + stage_next <= GET_OLDEST_SAMPLE_INSTANCE; + cnt_next <= 0; + else + cur_sample_next <= oldest_sample; + stage_next <= REMOVE_SAMPLE; + cnt_next <= 0; + end if; + end if; else - stage_next <= ADD_SAMPLE_INFO; - cnt_next <= 0; + -- Instance Handle provided + if (WITH_KEY and instance_handle_dds /= HANDLE_NIL) then + key_hash_next <= instance_handle_dds; + stage_next <= INITIATE_INSTANCE_SEARCH; + cnt_next <= 0; + else + stage_next <= ADD_SAMPLE_INFO; + cnt_next <= 0; + end if; end if; when DISPOSE => ack_dds <= '1'; @@ -870,14 +939,46 @@ begin sample_status_info_next <= (SSI_PAYLOAD_FLAG => '1', SSI_ALIGNED_FLAG => '1', SSI_DISPOSED_FLAG => '1', others => '0'); cur_sample_next <= empty_sample_list_head; - -- Instance Handle provided - if (WITH_KEY and instance_handle_dds /= HANDLE_NIL) then - key_hash_next <= instance_handle_dds; - stage_next <= INITIATE_INSTANCE_SEARCH; - cnt_next <= 0; + -- NOTE: We always expect a Serialized Key as Input of this Opration, so we also check the Payload memory + -- Payload Memory Full + if (empty_payload_list_head = PAYLOAD_MEMORY_MAX_ADDRESS) then + if (global_ack_cnt = 0 and HISTORY_QOS = KEEP_ALL_HISTORY_QOS) then + -- Reject Change + stage_next <= SKIP_AND_RETURN; + cnt_next <= 0; + return_code_latch_next <= RETCODE_OUT_OF_RESOURCES; + else + assert (oldest_sample /= SAMPLE_MEMORY_MAX_ADDRESS) severity FAILURE; + -- Do not ACK Operation + ack_dds <= '0'; + + if (global_ack_cnt /= 0) then + -- Accept Change (Remove Oldest ACKed Sample) + remove_oldest_sample_next <= '1'; + remove_ack_sample_next <= '1'; + + cur_sample_next <= oldest_sample; + stage_next <= FIND_SAMPLE; + cnt_next <= 0; + elsif (WITH_KEY) then + stage_next <= GET_OLDEST_SAMPLE_INSTANCE; + cnt_next <= 0; + else + cur_sample_next <= oldest_sample; + stage_next <= REMOVE_SAMPLE; + cnt_next <= 0; + end if; + end if; else - stage_next <= ADD_SAMPLE_INFO; - cnt_next <= 0; + -- Instance Handle provided + if (WITH_KEY and instance_handle_dds /= HANDLE_NIL) then + key_hash_next <= instance_handle_dds; + stage_next <= INITIATE_INSTANCE_SEARCH; + cnt_next <= 0; + else + stage_next <= ADD_SAMPLE_INFO; + cnt_next <= 0; + end if; end if; when UNREGISTER_INSTANCE => ack_dds <= '1'; @@ -893,24 +994,64 @@ begin sample_status_info_next <= (SSI_PAYLOAD_FLAG => '1', SSI_ALIGNED_FLAG => '1', SSI_UNREGISTERED_FLAG => '1', others => '0'); cur_sample_next <= empty_sample_list_head; - -- Instance Handle provided - if (WITH_KEY and instance_handle_dds /= HANDLE_NIL) then - key_hash_next <= instance_handle_dds; - stage_next <= INITIATE_INSTANCE_SEARCH; - cnt_next <= 0; + -- NOTE: We always expect a Serialized Key as Input of this Opration, so we also check the Payload memory + -- Payload Memory Full + if (empty_payload_list_head = PAYLOAD_MEMORY_MAX_ADDRESS) then + if (global_ack_cnt = 0 and HISTORY_QOS = KEEP_ALL_HISTORY_QOS) then + -- Reject Change + stage_next <= SKIP_AND_RETURN; + cnt_next <= 0; + return_code_latch_next <= RETCODE_OUT_OF_RESOURCES; + else + assert (oldest_sample /= SAMPLE_MEMORY_MAX_ADDRESS) severity FAILURE; + -- Do not ACK Operation + ack_dds <= '0'; + + if (global_ack_cnt /= 0) then + -- Accept Change (Remove Oldest ACKed Sample) + remove_oldest_sample_next <= '1'; + remove_ack_sample_next <= '1'; + + cur_sample_next <= oldest_sample; + stage_next <= FIND_SAMPLE; + cnt_next <= 0; + elsif (WITH_KEY) then + stage_next <= GET_OLDEST_SAMPLE_INSTANCE; + cnt_next <= 0; + else + cur_sample_next <= oldest_sample; + stage_next <= REMOVE_SAMPLE; + cnt_next <= 0; + end if; + end if; else - stage_next <= ADD_SAMPLE_INFO; - cnt_next <= 0; + -- Instance Handle provided + if (WITH_KEY and instance_handle_dds /= HANDLE_NIL) then + key_hash_next <= instance_handle_dds; + stage_next <= INITIATE_INSTANCE_SEARCH; + cnt_next <= 0; + else + stage_next <= ADD_SAMPLE_INFO; + cnt_next <= 0; + end if; end if; when LOOKUP_INSTANCE => - ack_dds <= '1'; -- Synthesis Guard if (WITH_KEY) then - lookup_op_next <= '1'; - stage_next <= ADD_PAYLOAD; - cnt_next <= 1; + start_kh <= '1'; + opcode_kh <= PUSH_DATA; + + if (ack_kh = '1') then + ack_dds <= '1'; + lookup_op_next <= '1'; + stage_next <= ADD_PAYLOAD; + cnt_next <= 1; + end if; else - stage_next <= UNKNOWN_OPERATION_DDS; + ack_dds <= '1'; + key_hash_next <= HANDLE_NIL; + stage_next <= SKIP; + return_stage_next <= PUSH_KEY_HASH; end if; when WAIT_FOR_ACKNOWLEDGEMENTS => -- NOTE: In case of BEST_EFFORT the RTPS Writer still manually ACKs the Samples, so we do not handle this case differently here. @@ -1045,6 +1186,7 @@ begin end if; -- Payload Address when 7 => + assert (empty_payload_list_head /= PAYLOAD_MEMORY_MAX_ADDRESS) severity FAILURE; sample_valid_in <= '1'; sample_addr <= cur_sample + SMF_PAYLOAD_ADDR_OFFSET; sample_write_data <= std_logic_vector(resize(empty_payload_list_head, WORD_WIDTH)); @@ -1142,6 +1284,7 @@ begin -- Fetch the Key Hash stage_next <= GET_KEY_HASH; cnt_next <= 0; + cnt2_next <= 0; else -- Next Word cnt_next <= 1; -- Same Sub-state @@ -1149,18 +1292,20 @@ begin else -- End of Payload if (last_word_in_dds = '1') then + last_word_out_kh <= '1'; -- End of Payload Slot - if (cnt2 = PAYLOAD_FRAME_SIZE) then + if (cnt2 = PAYLOAD_FRAME_SIZE-1) then -- Fetch the Key Hash stage_next <= GET_KEY_HASH; cnt_next <= 0; + cnt2_next <= 0; else stage_next <= ALIGN_PAYLOAD; cnt_next <= 0; end if; else -- End of Payload Slot - if (cnt2 = PAYLOAD_FRAME_SIZE) then + if (cnt2 = PAYLOAD_FRAME_SIZE-1) then stage_next <= NEXT_PAYLOAD_SLOT; cnt_next <= 0; else @@ -1199,8 +1344,9 @@ begin -- No Empty Payload Slots available if (unsigned(payload_read_data) = PAYLOAD_MEMORY_MAX_ADDRESS) then -- Reject Change - stage_next <= SKIP_ADD_REJECT; - cnt_next <= 0; + stage_next <= SKIP_AND_RETURN; + cnt_next <= 0; + return_code_latch_next <= RETCODE_OUT_OF_RESOURCES; -- Abort Key Hash Generation abort_kh <= '1'; else @@ -1236,10 +1382,11 @@ begin -- Memory Control Flow Guard if (payload_ready_in = '1') then if (WITH_KEY and instance_handle = HANDLE_NIL) then - stage_next <= GET_KEY_HASH; - cnt_next <= 0; + stage_next <= GET_KEY_HASH; + cnt_next <= 0; + cnt2_next <= 0; else - stage_next <= FILTER_STAGE; + stage_next <= FILTER_STAGE; end if; end if; when others => @@ -1248,20 +1395,34 @@ begin when GET_KEY_HASH => -- Synthesis Guard if (WITH_KEY) then - ready_in_kh <= '1'; + case (cnt) is + -- Initiate READ Operation + when 0 => + start_kh <= '1'; + opcode_kh <= READ_KEY_HASH; + + if (ack_kh = '1') then + cnt_next <= cnt + 1; + end if; + -- READ Key Hash + when 1 => + ready_in_kh <= '1'; - if (valid_in_kh = '1') then - cnt_next <= cnt + 1; - - -- Latch Key Hash - key_hash_next(cnt) <= data_in_kh; - - -- Exit Condition - if (last_word_in_kh = '1') then - -- DONE - stage_next <= INITIATE_INSTANCE_SEARCH; - end if; - end if; + if (valid_in_kh = '1') then + cnt2_next <= cnt2 + 1; + + -- Latch Key Hash + key_hash_next(cnt2) <= data_in_kh; + + -- Exit Condition + if (last_word_in_kh = '1') then + -- DONE + stage_next <= INITIATE_INSTANCE_SEARCH; + end if; + end if; + when others => + null; + end case; end if; when INITIATE_INSTANCE_SEARCH => -- Synthesis Guard @@ -1294,9 +1455,7 @@ begin if (inst_op_done = '1') then -- Instance already in Memory if (inst_addr_base /= INSTANCE_MEMORY_MAX_ADDRESS) then - -- Accept Change - done_dds <= '1'; - return_code_dds <= RETCODE_OK; + -- Accept Registration stage_next <= PUSH_KEY_HASH; cnt_next <= 0; @@ -1326,15 +1485,13 @@ begin stage_next <= REMOVE_STALE_INSTANCE; cnt_next <= 0; else - -- Reject Change - done_dds <= '1'; - return_code_dds <= RETCODE_OUT_OF_RESOURCES; - stage_next <= IDLE; + -- Reject Registration + key_hash_next <= HANDLE_NIL; + stage_next <= PUSH_KEY_HASH; + cnt_next <= 0; end if; else - -- Accept Change - done_dds <= '1'; - return_code_dds <= RETCODE_OK; + -- Accept Registration stage_next <= PUSH_KEY_HASH; cnt_next <= 0; @@ -1366,56 +1523,48 @@ begin end if; end if; when PUSH_KEY_HASH => - -- Synthesis Guard - if (WITH_KEY) then - case (cnt) is - -- Key Hash 1/4 - when 0 => - valid_out_dds <= '1'; - data_out_dds <= key_hash(0); - - -- Output Guard - if (ready_out_dds = '1') then - cnt_next <= cnt + 1; - end if; - -- Key Hash 2/4 - when 1 => - valid_out_dds <= '1'; - data_out_dds <= key_hash(1); - - -- Output Guard - if (ready_out_dds = '1') then - cnt_next <= cnt + 1; - end if; - -- Key Hash 3/4 - when 2 => - valid_out_dds <= '1'; - data_out_dds <= key_hash(2); - - -- Output Guard - if (ready_out_dds = '1') then - cnt_next <= cnt + 1; - end if; - -- Key Hash 4/4 - when 3 => - valid_out_dds <= '1'; - data_out_dds <= key_hash(3); - - -- Output Guard - if (ready_out_dds = '1') then - cnt_next <= cnt + 1; - end if; - -- Return Code - when 4 => - done_dds <= '1'; - return_code_dds <= RETCODE_OK; - + case (cnt) is + -- Key Hash 1/4 + when 0 => + valid_out_dds <= '1'; + data_out_dds <= key_hash(0); + + -- Output Guard + if (ready_out_dds = '1') then + cnt_next <= cnt + 1; + end if; + -- Key Hash 2/4 + when 1 => + valid_out_dds <= '1'; + data_out_dds <= key_hash(1); + + -- Output Guard + if (ready_out_dds = '1') then + cnt_next <= cnt + 1; + end if; + -- Key Hash 3/4 + when 2 => + valid_out_dds <= '1'; + data_out_dds <= key_hash(2); + + -- Output Guard + if (ready_out_dds = '1') then + cnt_next <= cnt + 1; + end if; + -- Key Hash 4/4 + when 3 => + valid_out_dds <= '1'; + data_out_dds <= key_hash(3); + last_word_out_dds <= '1'; + + -- Output Guard + if (ready_out_dds = '1') then -- DONE stage_next <= IDLE; - when others => - null; - end case; - end if; + end if; + when others => + null; + end case; when FILTER_STAGE => -- Precondition: cur_sample set @@ -1429,28 +1578,52 @@ begin -- RESOURCE_LIMITS_QOS (MAX_SAMPLES_PER_INSTANCE) if (WITH_KEY and MAX_SAMPLES_PER_INSTANCE /= LENGTH_UNLIMITED and inst_data.sample_cnt = unsigned(MAX_SAMPLES_PER_INSTANCE)) then - if (inst_data.ack_cnt = 0 and HISTORY_QOS = KEEP_ALL_HISTORY_QOS) then - -- Reject Change - done_dds <= '1'; - return_code_dds <= RETCODE_OUT_OF_RESOURCES; - stage_next <= IDLE; - else - -- Accept Change (Remove Oldest ACKed Instance Sample) + -- Synthesis Guard + if (HISTORY_QOS = KEEP_ALL_HISTORY_QOS) then + -- No ACKed Instance Samples exist + if (inst_data.ack_cnt = 0) then + -- Reject Change + done_dds <= '1'; + return_code_dds <= RETCODE_OUT_OF_RESOURCES; + stage_next <= IDLE; + else + -- Accept Change (Remove Oldest ACKed Instance Sample) + remove_oldest_inst_sample_next <= '1'; + remove_ack_sample_next <= '1'; + done_dds <= '1'; + return_code_dds <= RETCODE_OK; + stage_next <= UPDATE_INSTANCE; + end if; + else -- HISTORY_QOS = KEEP_LAST_HISTORY_QOS + -- Accept Change (Remove Oldest (ACKed) Instance Sample) remove_oldest_inst_sample_next <= '1'; + remove_ack_sample_next <= '1' when (inst_data.ack_cnt /= 0) else '0'; done_dds <= '1'; return_code_dds <= RETCODE_OK; stage_next <= UPDATE_INSTANCE; end if; -- RESOURCE_LIMITS_QOS (MAX_SAMPLES) elsif (empty_sample_list_head = empty_sample_list_tail) then - if (global_ack_cnt = 0 and HISTORY_QOS = KEEP_ALL_HISTORY_QOS) then - -- Reject Change - done_dds <= '1'; - return_code_dds <= RETCODE_OUT_OF_RESOURCES; - stage_next <= IDLE; - else - -- Accept Change (Remove Oldest ACKed Sample) + -- Synthesis Guard + if (HISTORY_QOS = KEEP_ALL_HISTORY_QOS) then + -- No ACKed Samples exist + if (global_ack_cnt = 0) then + -- Reject Change + done_dds <= '1'; + return_code_dds <= RETCODE_OUT_OF_RESOURCES; + stage_next <= IDLE; + else + -- Accept Change (Remove Oldest ACKed Sample) + remove_oldest_sample_next <= '1'; + remove_ack_sample_next <= '1'; + done_dds <= '1'; + return_code_dds <= RETCODE_OK; + stage_next <= UPDATE_INSTANCE; + end if; + else -- HISTORY_QOS = KEEP_LAST_HISTORY_QOS + -- Accept Change (Remove Oldest (ACKed) Sample) remove_oldest_sample_next <= '1'; + remove_ack_sample_next <= '1' when (global_ack_cnt /= 0) else '0'; done_dds <= '1'; return_code_dds <= RETCODE_OK; stage_next <= UPDATE_INSTANCE; @@ -1473,32 +1646,34 @@ begin -- DONE stage_next <= IDLE; -- Ignore Unregister Operation on Unknown Instance - elsif (sample_status_info(SSI_UNREGISTERED_FLAG) /= '1') then + elsif (sample_status_info(SSI_UNREGISTERED_FLAG) = '1') then -- Drop Change done_dds <= '1'; return_code_dds <= RETCODE_OK; -- DONE stage_next <= IDLE; - -- RESOURCE_LIMITS_QOS (MAX_SAMPLES) - elsif (empty_sample_list_head = empty_sample_list_tail) then - -- ACKed Samples exist - if (global_ack_cnt = 0 and HISTORY_QOS = KEEP_ALL_HISTORY_QOS) then + -- RESOURCE_LIMITS_QOS (MAX_INSTANCES) (Instance Memory Full) + elsif (inst_empty_head = INSTANCE_MEMORY_MAX_ADDRESS) then + -- No Stale Instances available + if (stale_inst_cnt = 0) then -- Reject Change done_dds <= '1'; return_code_dds <= RETCODE_OUT_OF_RESOURCES; stage_next <= IDLE; - else - -- RESOURCE_LIMITS_QOS (MAX_INSTANCES) (Instance Memory Full) - if (inst_empty_head = INSTANCE_MEMORY_MAX_ADDRESS) then - -- No Stale Instances available - if (stale_inst_cnt = 0) then + -- RESOURCE_LIMITS_QOS (MAX_SAMPLES) + elsif (empty_sample_list_head = empty_sample_list_tail) then + -- Synthesis Guard + if (HISTORY_QOS = KEEP_ALL_HISTORY_QOS) then + -- No ACKed Samples exist + if (global_ack_cnt = 0) then -- Reject Change done_dds <= '1'; return_code_dds <= RETCODE_OUT_OF_RESOURCES; stage_next <= IDLE; else - -- Accept Change (Remove Oldest Sample) + -- Accept Change (Remove Oldest ACKed Sample) remove_oldest_sample_next <= '1'; + remove_ack_sample_next <= '1'; done_dds <= '1'; return_code_dds <= RETCODE_OK; @@ -1509,34 +1684,10 @@ begin stage_next <= REMOVE_STALE_INSTANCE; cnt_next <= 0; end if; - else - -- Accept Change (Remove Oldest Sample) + else -- HISTORY_QOS = KEEP_LAST_HISTORY_QOS + -- Accept Change (Remove Oldest (ACKed) Sample) remove_oldest_sample_next <= '1'; - done_dds <= '1'; - return_code_dds <= RETCODE_OK; - - -- Insert New Instance - inst_op_start <= '1'; - inst_opcode <= INSERT_INSTANCE; - status_info_update <= (ISI_LIVELINESS_FLAG => '1', others => '0'); - sample_cnt <= to_unsigned(1, WORD_WIDTH); - ack_cnt <= (others => '0'); - - stage_next <= FINALIZE_PAYLOAD; - cnt_next <= 0; - end if; - end if; - else - -- RESOURCE_LIMITS_QOS (MAX_INSTANCES) (Instance Memory Full) - if (inst_empty_head = INSTANCE_MEMORY_MAX_ADDRESS) then - -- No Stale Instances available - if (stale_inst_cnt = 0) then - -- Reject Change - done_dds <= '1'; - return_code_dds <= RETCODE_OUT_OF_RESOURCES; - stage_next <= IDLE; - else - -- Accept Change + remove_ack_sample_next <= '1' when (global_ack_cnt /= 0) else '0'; done_dds <= '1'; return_code_dds <= RETCODE_OK; @@ -1552,6 +1703,63 @@ begin done_dds <= '1'; return_code_dds <= RETCODE_OK; + -- Remove Stale and insert new Instance + inst_op_start <= '1'; + inst_opcode <= GET_FIRST_INSTANCE; + inst_mem_fields <= IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_ACK_CNT_FLAG; + stage_next <= REMOVE_STALE_INSTANCE; + cnt_next <= 0; + end if; + else + -- RESOURCE_LIMITS_QOS (MAX_SAMPLES) + if (empty_sample_list_head = empty_sample_list_tail) then + -- Synthesis Guard + if (HISTORY_QOS = KEEP_ALL_HISTORY_QOS) then + -- No ACKed Samples exist + if (global_ack_cnt = 0) then + -- Reject Change + done_dds <= '1'; + return_code_dds <= RETCODE_OUT_OF_RESOURCES; + stage_next <= IDLE; + else + -- Accept Change (Remove Oldest ACKed Sample) + remove_oldest_sample_next <= '1'; + remove_ack_sample_next <= '1'; + done_dds <= '1'; + return_code_dds <= RETCODE_OK; + + -- Insert New Instance + inst_op_start <= '1'; + inst_opcode <= INSERT_INSTANCE; + status_info_update <= (ISI_LIVELINESS_FLAG => '1', others => '0'); + sample_cnt <= to_unsigned(1, WORD_WIDTH); + ack_cnt <= (others => '0'); + + stage_next <= FINALIZE_PAYLOAD; + cnt_next <= 0; + end if; + else -- HISTORY_QOS = KEEP_LAST_HISTORY_QOS + -- Accept Change (Remove Oldest (ACKed) Sample) + remove_oldest_sample_next <= '1'; + remove_ack_sample_next <= '1' when (global_ack_cnt /= 0) else '0'; + done_dds <= '1'; + return_code_dds <= RETCODE_OK; + + -- Insert New Instance + inst_op_start <= '1'; + inst_opcode <= INSERT_INSTANCE; + status_info_update <= (ISI_LIVELINESS_FLAG => '1', others => '0'); + sample_cnt <= to_unsigned(1, WORD_WIDTH); + ack_cnt <= (others => '0'); + + stage_next <= FINALIZE_PAYLOAD; + cnt_next <= 0; + end if; + else + -- Accept Change + done_dds <= '1'; + return_code_dds <= RETCODE_OK; + -- Insert New Instance inst_op_start <= '1'; inst_opcode <= INSERT_INSTANCE; @@ -1560,7 +1768,7 @@ begin ack_cnt <= (others => '0'); stage_next <= FINALIZE_PAYLOAD; - cnt_next <= 0; + cnt_next <= 0; end if; end if; end if; @@ -1574,9 +1782,15 @@ begin inst_opcode <= UPDATE_INSTANCE; inst_mem_fields <= IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG; status_info_update <= inst_data.status_info; - status_info_update(ISI_DISPOSED_FLAG) <= sample_status_info(SSI_DISPOSED_FLAG); - status_info_update(ISI_UNREGISTERED_FLAG) <= sample_status_info(SSI_UNREGISTERED_FLAG); status_info_update(ISI_LIVELINESS_FLAG) <= '1'; + if (sample_status_info(SSI_DISPOSED_FLAG) = '0' and sample_status_info(SSI_UNREGISTERED_FLAG) = '0') then + status_info_update(ISI_DISPOSED_FLAG) <= '0'; + status_info_update(ISI_UNREGISTERED_FLAG) <= '0'; + elsif (sample_status_info(SSI_DISPOSED_FLAG) = '1') then + status_info_update(ISI_DISPOSED_FLAG) <= '1'; + elsif (sample_status_info(SSI_UNREGISTERED_FLAG) = '1') then + status_info_update(ISI_UNREGISTERED_FLAG) <= '1'; + end if; sample_cnt <= inst_data.sample_cnt + 1; -- Update Stale Instance Count @@ -1586,10 +1800,16 @@ begin stale_inst_cnt_next <= stale_inst_cnt - 1; end if; else - inst_data_next.status_info(ISI_DISPOSED_FLAG) <= sample_status_info(SSI_DISPOSED_FLAG); - inst_data_next.status_info(ISI_UNREGISTERED_FLAG) <= sample_status_info(SSI_UNREGISTERED_FLAG); - inst_data_next.status_info(ISI_LIVELINESS_FLAG) <= '1'; - inst_data_next.sample_cnt <= inst_data.sample_cnt + 1; + if (sample_status_info(SSI_DISPOSED_FLAG) = '0' and sample_status_info(SSI_UNREGISTERED_FLAG) = '0') then + inst_data_next2.status_info(ISI_DISPOSED_FLAG) <= '0'; + inst_data_next2.status_info(ISI_UNREGISTERED_FLAG) <= '0'; + elsif (sample_status_info(SSI_DISPOSED_FLAG) = '1') then + inst_data_next2.status_info(ISI_DISPOSED_FLAG) <= '1'; + elsif (sample_status_info(SSI_UNREGISTERED_FLAG) = '1') then + inst_data_next2.status_info(ISI_UNREGISTERED_FLAG) <= '1'; + end if; + inst_data_next2.status_info(ISI_LIVELINESS_FLAG) <= '1'; + inst_data_next2.sample_cnt <= inst_data.sample_cnt + 1; end if; stage_next <= FINALIZE_PAYLOAD; @@ -1629,57 +1849,6 @@ begin -- Fix New Empty List Head empty_payload_list_head_next <= resize(unsigned(payload_read_data), PAYLOAD_MEMORY_ADDR_WIDTH); - -- First Sample - if (newest_sample = SAMPLE_MEMORY_MAX_ADDRESS) then - stage_next <= FINALIZE_SAMPLE; - cur_sample_next <= empty_sample_list_head; - next_sample_next <= SAMPLE_MEMORY_MAX_ADDRESS; - prev_sample_next <= SAMPLE_MEMORY_MAX_ADDRESS; - cnt_next <= 0; - else - stage_next <= FIX_POINTERS; - next_sample_next <= SAMPLE_MEMORY_MAX_ADDRESS; - prev_sample_next <= newest_sample; - cur_sample_next <= newest_sample; - cnt_next <= 0; - end if; - end if; - when others => - null; - end case; - when FIX_POINTERS => - -- Precondition: prev_sample set, next_sample set - - case (cnt) is - -- Next Pointer (Previous Sample) - when 0 => - -- Fix Next Pointer - sample_valid_in <= '1'; - sample_addr <= prev_sample + SMF_NEXT_ADDR_OFFSET; - sample_write_data <= std_logic_vector(resize(empty_sample_list_head, WORD_WIDTH)); - - -- Memory Flow Control Guard - if (sample_ready_in = '1') then - -- No next Slot (Newest Sample) - if (next_sample = SAMPLE_MEMORY_MAX_ADDRESS) then - assert (prev_sample = newest_sample) report "Next Sample is MAX_ADDRESS, but sample is not NEWEST (TAIL)" severity FAILURE; - - stage_next <= FINALIZE_SAMPLE; - cur_sample_next <= empty_sample_list_head; - cnt_next <= 0; - else - cnt_next <= 1; - end if; - end if; - -- Previous Pointer (Next Sample) - when 1 => - -- Fix Previous Pointer - sample_valid_in <= '1'; - sample_addr <= next_sample + SMF_PREV_ADDR_OFFSET; - sample_write_data <= std_logic_vector(resize(empty_sample_list_head, WORD_WIDTH)); - - -- Memory Flow Control Guard - if (sample_ready_in = '1') then stage_next <= FINALIZE_SAMPLE; cur_sample_next <= empty_sample_list_head; cnt_next <= 0; @@ -1688,54 +1857,79 @@ begin null; end case; when FINALIZE_SAMPLE => - -- Precondition: prev_sample set, next_sample set, cur_sample set + -- Precondition: cur_sample set, cur_inst set case (cnt) is - -- GET Next (Empty) Sample + -- GET Next Pointer when 0 => sample_valid_in <= '1'; sample_addr <= cur_sample + SMF_NEXT_ADDR_OFFSET; sample_read <= '1'; -- Memory Flow Control Guard if (sample_ready_in = '1') then - cnt_next <= cnt + 1; + -- Sample Memory Empty (No previous Sample) + if (newest_sample = SAMPLE_MEMORY_MAX_ADDRESS) then + assert (oldest_sample = SAMPLE_MEMORY_MAX_ADDRESS) severity FAILURE; + if (WITH_KEY) then + cnt_next <= cnt + 2; -- Skip Next Step + else + cnt_next <= cnt + 3; -- Skip Next 2 Steps + end if; + else + cnt_next <= cnt + 1; + end if; end if; - -- Instance Pointer + -- SET Next Pointer (Previous Sample) when 1 => - -- Write Instance Pointer sample_valid_in <= '1'; - sample_addr <= cur_sample + SMF_INSTANCE_ADDR_OFFSET; - sample_write_data <= std_logic_vector(resize(cur_inst, WORD_WIDTH)); + sample_addr <= newest_sample + SMF_NEXT_ADDR_OFFSET; + sample_write_data <= std_logic_vector(resize(cur_sample, WORD_WIDTH)); -- Memory Flow Control Guard if (sample_ready_in = '1') then - cnt_next <= cnt + 1; + if (WITH_KEY) then + cnt_next <= cnt + 1; + else + cnt_next <= cnt + 2; --Skip Next Step + end if; end if; - -- Previous Pointer + -- SET Instance Pointer when 2 => - -- Write Previous Pointer + -- Synthesis Guard + if (WITH_KEY) then + sample_valid_in <= '1'; + sample_addr <= cur_sample + SMF_INSTANCE_ADDR_OFFSET; + sample_write_data <= std_logic_vector(resize(cur_inst, WORD_WIDTH)); + + -- Memory Flow Control Guard + if (sample_ready_in = '1') then + cnt_next <= cnt + 1; + end if; + end if; + -- SET Previous Pointer + when 3 => sample_valid_in <= '1'; sample_addr <= cur_sample + SMF_PREV_ADDR_OFFSET; - sample_write_data <= std_logic_vector(resize(prev_sample, WORD_WIDTH)); + sample_write_data <= std_logic_vector(resize(newest_sample, WORD_WIDTH)); -- Memory Flow Control Guard if (sample_ready_in = '1') then cnt_next <= cnt + 1; end if; - -- Next Pointer - when 3 => + -- SET Next Pointer + when 4 => -- Write Next Pointer sample_valid_in <= '1'; sample_addr <= cur_sample + SMF_NEXT_ADDR_OFFSET; - sample_write_data <= std_logic_vector(resize(next_sample, WORD_WIDTH)); + sample_write_data <= std_logic_vector(resize(SAMPLE_MEMORY_MAX_ADDRESS, WORD_WIDTH)); -- Memory Flow Control Guard if (sample_ready_in = '1') then cnt_next <= cnt + 1; end if; - -- READ Next (Empty) Sample - when 4 => + -- READ Next Pointer + when 5 => sample_ready_out <= '1'; -- Memory Flow Control Guard @@ -1744,9 +1938,10 @@ begin -- Fix new Empty List Head empty_sample_list_head_next <= resize(unsigned(sample_read_data), SAMPLE_MEMORY_ADDR_WIDTH); - -- If newest Sample is now previous, select current sample as new newest - if (newest_sample = prev_sample) then - newest_sample_next <= cur_sample; + -- Fix List Pointers + newest_sample_next <= cur_sample; + if (oldest_sample = SAMPLE_MEMORY_MAX_ADDRESS) then + oldest_sample_next <= cur_sample; end if; -- Increment Global Sequence Number @@ -1758,16 +1953,25 @@ begin -- Signal Data Available data_available_sig_next <= '1'; + -- NOTE: This is needed to prevent the new Sample to be selected during an Orphan Sample + -- Search, since the Dead Instance Address is the same as the new Sample Instance Address. + -- Latch Sample Address + new_sample_next <= cur_sample; + -- Update Lifespan Check Time if (LIFESPAN_QOS /= DURATION_INFINITE and lifespan < lifespan_time) then lifespan_next <= lifespan; end if; - if (WITH_KEY and remove_oldest_inst_sample = '1') then - cur_sample <= oldest_sample; - stage_next <= FIND_OLDEST_INST_SAMPLE; - cnt_next <= 0; + if (remove_oldest_inst_sample = '1' or (remove_oldest_sample = '1' and remove_ack_sample = '1')) then + assert (oldest_sample /= SAMPLE_MEMORY_MAX_ADDRESS) severity FAILURE; + + cur_sample_next <= oldest_sample; + stage_next <= FIND_SAMPLE; + cnt_next <= 0; elsif (remove_oldest_sample = '1') then + assert (oldest_sample /= SAMPLE_MEMORY_MAX_ADDRESS) severity FAILURE; + -- Synthesis Guard if (WITH_KEY) then stage_next <= GET_OLDEST_SAMPLE_INSTANCE; @@ -1807,11 +2011,8 @@ begin -- Memory Flow Control Guard if (sample_valid_out = '1') then - -- NOTE: We have to initiate an instance "search" despite having direct access to the instance - -- in order to set up the 'previous' instance pointer required by the removal procedure - -- (Since we do not store previous pointers in the memory frame format) inst_op_start <= '1'; - inst_opcode <= SEARCH_INSTANCE_ADDR; + inst_opcode <= GET_INSTANCE; inst_mem_fields <= IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_ACK_CNT_FLAG; inst_addr_update <= resize(unsigned(sample_read_data), INSTANCE_MEMORY_ADDR_WIDTH); @@ -1824,28 +2025,141 @@ begin null; end case; end if; - when FIND_OLDEST_INST_SAMPLE => + when FIND_SAMPLE => -- Precondition: cur_sample set - -- Synthesis Guard - if (WITH_KEY) then - case (cnt) is - -- GET Instance Pointer - when 0 => - sample_ready_in <= '1'; + case (cnt) is + -- GET Next Sample + when 0 => + sample_valid_in <= '1'; + sample_addr <= cur_sample + SMF_NEXT_ADDR_OFFSET; + sample_read <= '1'; + + -- Memory Flow Control Guard + if (sample_ready_in = '1') then + if (remove_ack_sample = '1') then + cnt_next <= cnt + 1; + else + assert(remove_oldest_inst_sample = '1') severity FAILURE; + + cnt_next <= cnt + 2; -- Skip Next Step + end if; + end if; + -- GET Status Info + when 1 => + sample_valid_in <= '1'; + sample_addr <= cur_sample + SMF_STATUS_INFO_OFFSET; + sample_read <= '1'; + + -- Memory Flow Control Guard + if (sample_ready_in = '1') then + -- Synthesis Guard + if (WITH_KEY) then + cnt_next <= cnt + 1; + else + cnt_next <= cnt + 2; -- Skip Next Step + end if; + end if; + -- GET Instance Pointer + when 2 => + -- Synthesis Guard + if (WITH_KEY) then + sample_valid_in <= '1'; sample_addr <= cur_sample + SMF_INSTANCE_ADDR_OFFSET; sample_read <= '1'; + -- Memory Flow Control Guard + if (sample_ready_in = '1') then + cnt_next <= cnt + 1; + end if; + end if; + -- READ Next Sample + when 3 => + sample_ready_out <= '1'; + + -- Memory Flow Control Guard + if (sample_valid_out = '1') then + next_sample_next <= resize(unsigned(sample_read_data), SAMPLE_MEMORY_ADDR_WIDTH); + + if (remove_ack_sample = '1') then + cnt_next <= cnt + 1; + else + assert(remove_oldest_inst_sample = '1') severity FAILURE; + assert(WITH_KEY) severity FAILURE; + + cnt_next <= cnt + 2; -- Skip Next Step + end if; + end if; + -- READ Status Info + when 4 => + sample_ready_out <= '1'; + + -- Memory Flow Control Guard + if (sample_valid_out = '1') then + -- Sample is ACKed + if (sample_read_data(SSI_ACK_FLAG) = '1') then + if (WITH_KEY) then + cnt_next <= cnt + 1; + else + stage_next <= REMOVE_SAMPLE; + cnt_next <= 0; + end if; + else + -- Continue + sample_abort_read <= '1'; + cur_sample_next <= next_sample; + cnt_next <= 0; + end if; + end if; + -- READ Instance Pointer + when 5 => + -- Synthesis Guard + if (WITH_KEY) then + sample_ready_out <= '1'; + + -- Memory Flow Control Guard + if (sample_valid_out = '1') then + if (remove_oldest_sample = '1') then + inst_op_start <= '1'; + inst_opcode <= GET_INSTANCE; + inst_mem_fields <= IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_ACK_CNT_FLAG; + inst_addr_update <= resize(unsigned(sample_read_data), INSTANCE_MEMORY_ADDR_WIDTH); + + stage_next <= REMOVE_SAMPLE; + cnt_next <= 0; + -- Oldest Instance Sample Found + elsif (resize(unsigned(sample_read_data),INSTANCE_MEMORY_ADDR_WIDTH) = cur_inst) then + -- NOTE: Instance Data already valid + stage_next <= REMOVE_SAMPLE; + cnt_next <= 0; + else + -- Continue + cur_sample_next <= next_sample; + cnt_next <= 0; + end if; + end if; + end if; + when others => + null; + end case; + when REMOVE_ORPHAN_SAMPLES => + -- Synthesis Guard + if (WITH_KEY) then + case (cnt) is + -- GET Instance Pointer + when 0 => + sample_valid_in <= '1'; + sample_addr <= cur_sample + SMF_INSTANCE_ADDR_OFFSET; + sample_read <= '1'; -- Memory Flow Control Guard if (sample_ready_in = '1') then cnt_next <= cnt + 1; end if; -- GET Next Sample when 1 => - sample_ready_in <= '1'; + sample_valid_in <= '1'; sample_addr <= cur_sample + SMF_NEXT_ADDR_OFFSET; sample_read <= '1'; - -- Memory Flow Control Guard if (sample_ready_in = '1') then cnt_next <= cnt + 1; @@ -1853,11 +2167,11 @@ begin -- READ Instance Pointer when 2 => sample_ready_out <= '1'; - -- Memory Flow Control Guard if (sample_valid_out = '1') then - -- Oldest Instance Sample Found - if (resize(unsigned(sample_read_data),INSTANCE_MEMORY_ADDR_WIDTH) = cur_inst) then + -- Sample is Orphan (And not newly added sample of new instance) + if (resize(unsigned(sample_read_data),INSTANCE_MEMORY_ADDR_WIDTH) = dead_inst and cur_sample /= new_sample) then + -- Remove Orphan Sample stage_next <= REMOVE_SAMPLE; cnt_next <= 0; sample_abort_read <= '1'; @@ -1868,70 +2182,23 @@ begin -- READ Next Sample when 3 => sample_ready_out <= '1'; - -- Memory Flow Control Guard if (sample_valid_out = '1') then - cur_sample_next <= resize(unsigned(sample_read_data), SAMPLE_MEMORY_ADDR_WIDTH); - cnt_next <= 0; + -- End of Samples + if (resize(unsigned(sample_read_data),SAMPLE_MEMORY_ADDR_WIDTH) = SAMPLE_MEMORY_MAX_ADDRESS) then + -- DONE + orphan_samples_next <= '0'; + stage_next <= IDLE; + else + -- Continue + cur_sample_next <= resize(unsigned(sample_read_data),SAMPLE_MEMORY_ADDR_WIDTH); + cnt_next <= 0; + end if; end if; when others => null; end case; end if; - when REMOVE_ORPHAN_SAMPLES => - case (cnt) is - -- GET Instance Pointer - when 0 => - sample_valid_in <= '1'; - sample_addr <= cur_sample + SMF_INSTANCE_ADDR_OFFSET; - sample_read <= '1'; - -- Memory Flow Control Guard - if (sample_ready_in = '1') then - cnt_next <= cnt + 1; - end if; - -- GET Next Sample - when 1 => - sample_valid_in <= '1'; - sample_addr <= cur_sample + SMF_NEXT_ADDR_OFFSET; - sample_read <= '1'; - -- Memory Flow Control Guard - if (sample_ready_in = '1') then - cnt_next <= cnt + 1; - end if; - -- READ Instance Pointer - when 2 => - sample_ready_out <= '1'; - -- Memory Flow Control Guard - if (sample_valid_out = '1') then - -- Sample is Orphan - if (resize(unsigned(sample_read_data),INSTANCE_MEMORY_ADDR_WIDTH) = dead_inst) then - -- Remove Orphan Sample - stage_next <= REMOVE_SAMPLE; - cnt_next <= 0; - sample_abort_read <= '1'; - else - cnt_next <= cnt + 1; - end if; - end if; - -- READ Next Sample - when 3 => - sample_ready_out <= '1'; - -- Memory Flow Control Guard - if (sample_valid_out = '1') then - -- End of Samples - if (resize(unsigned(sample_read_data),SAMPLE_MEMORY_ADDR_WIDTH) = SAMPLE_MEMORY_MAX_ADDRESS) then - -- DONE - orphan_samples_next <= '0'; - stage_next <= IDLE; - else - -- Continue - cur_sample_next <= resize(unsigned(sample_read_data),SAMPLE_MEMORY_ADDR_WIDTH); - cnt_next <= 0; - end if; - end if; - when others => - null; - end case; when REMOVE_SAMPLE => -- Precondition: cur_sample set @@ -1949,7 +2216,7 @@ begin if (sample_ready_in = '1') then cnt_next <= cnt + 1; end if; - -- GET Previous Sample + -- GET Previous Pointer when 1 => sample_valid_in <= '1'; sample_addr <= cur_sample + SMF_PREV_ADDR_OFFSET; @@ -1959,7 +2226,7 @@ begin if (sample_ready_in = '1') then cnt_next <= cnt + 1; end if; - -- GET Next Sample + -- GET Next Pointer when 2 => sample_valid_in <= '1'; sample_addr <= cur_sample + SMF_NEXT_ADDR_OFFSET; @@ -1988,7 +2255,7 @@ begin sample_status_info_next <= sample_read_data; cnt_next <= cnt + 1; end if; - -- READ Previous Sample + -- READ Previous Pointer when 5 => sample_ready_out <= '1'; -- Memory Flow Control Guard @@ -1996,7 +2263,7 @@ begin prev_sample_next <= resize(unsigned(sample_read_data),SAMPLE_MEMORY_ADDR_WIDTH); cnt_next <= cnt + 1; end if; - -- READ Next Sample + -- READ Next Pointer when 6 => sample_ready_out <= '1'; -- Memory Flow Control Guard @@ -2012,7 +2279,7 @@ begin cnt_next <= cnt + 1; end if; end if; - -- Next Pointer (Empty List Tail) + -- SET Next Pointer (Empty List Tail) when 7 => -- Add Current Sample after Empty List Tail sample_valid_in <= '1'; @@ -2023,12 +2290,12 @@ begin if (sample_ready_in = '1') then cnt_next <= cnt + 1; end if; - -- Next Pointer (Current Sample) + -- SET Next Pointer when 8 => -- Make Current Sample Empty List Tail sample_valid_in <= '1'; sample_addr <= cur_sample + SMF_NEXT_ADDR_OFFSET; - sample_write_data <= std_logic_vector(resize(INSTANCE_MEMORY_MAX_ADDRESS,WORD_WIDTH)); + sample_write_data <= std_logic_vector(resize(SAMPLE_MEMORY_MAX_ADDRESS,WORD_WIDTH)); -- Memory Flow Control Guard if (sample_ready_in = '1') then @@ -2037,19 +2304,19 @@ begin -- Current Sample is Newest (Occupied List Tail) if (next_sample = SAMPLE_MEMORY_MAX_ADDRESS) then - assert (cur_sample = newest_sample) report "Next Sample is MAX_ADDR, but cur_sample /= newest_sample" severity FAILURE; + assert (cur_sample = newest_sample) severity FAILURE; -- Fix Newest Pointer newest_sample_next <= prev_sample; -- Current Sample is Oldest (List Head) if (prev_sample = SAMPLE_MEMORY_MAX_ADDRESS) then - assert (cur_sample = oldest_sample) report "Previous Sample is MAX_ADDR, but cur_sample /= oldest_sample" severity FAILURE; - assert (newest_sample = oldest_sample) report "Previous and Next Sample is MAX_ADDR, but cur_sample /= newest_sample /= oldest_sample" severity FAILURE; + assert (cur_sample = oldest_sample) severity FAILURE; + assert (newest_sample = oldest_sample) severity FAILURE; + -- NOTE: Sample Memory Empty (newest_sample also set to MAX_ADDR) -- Fix Oldest Pointer oldest_sample_next <= SAMPLE_MEMORY_MAX_ADDRESS; - -- NOTE: Sample Memory Empty (newest_sample also set to MAX_ADDR) cnt_next <= cnt + 3; -- Skip next 2 steps else @@ -2059,7 +2326,7 @@ begin cnt_next <= cnt + 1; end if; end if; - -- Previous Address (Next Sample) + -- SET Previous Pointer (Next Sample) when 9 => -- Remove link to cur_sample sample_valid_in <= '1'; @@ -2073,14 +2340,14 @@ begin assert (cur_sample = oldest_sample) report "Previous Sample is MAX_ADDR, but cur_sample /= oldest_sample" severity FAILURE; -- Fix Oldest Pointer - oldest_sample_next <= SAMPLE_MEMORY_MAX_ADDRESS; + oldest_sample_next <= next_sample; cnt_next <= cnt + 2; -- Skip next step else cnt_next <= cnt + 1; end if; end if; - -- Next Address (Previous Sample) + -- SET Next Pointer (Previous Sample) when 10 => -- Remove link to cur_sample sample_valid_in <= '1'; @@ -2097,17 +2364,58 @@ begin -- Memory Flow Control Guard if (sample_valid_out = '1') then + -- Update Global Sample Count + global_sample_cnt_next <= global_sample_cnt - 1; + + -- Update Global ACK Count + -- Sample was ACKed + if (sample_status_info(SSI_ACK_FLAG) = '1') then + global_ack_cnt_next <= global_ack_cnt - 1; + end if; + cur_payload_next <= resize(unsigned(sample_read_data),PAYLOAD_MEMORY_ADDR_WIDTH); -- Sample has no Data if (resize(unsigned(sample_read_data),PAYLOAD_MEMORY_ADDR_WIDTH) = PAYLOAD_MEMORY_MAX_ADDRESS) then - stage_next <= POST_SAMPLE_REMOVE; + -- Orphan Sample Removal in progress + if (orphan_samples = '1') then + -- End of Samples + if (next_sample = SAMPLE_MEMORY_MAX_ADDRESS) then + -- DONE + orphan_samples_next <= '0'; + stage_next <= IDLE; + else + -- Continue + stage_next <= REMOVE_ORPHAN_SAMPLES; + cur_sample_next <= next_sample; + cnt_next <= 0; + end if; + else + stage_next <= POST_SAMPLE_REMOVE; + end if; -- Payload Memory Full elsif (empty_payload_list_head = PAYLOAD_MEMORY_MAX_ADDRESS) then + -- Fix Empty List Head empty_payload_list_head_next <= resize(unsigned(sample_read_data),PAYLOAD_MEMORY_ADDR_WIDTH); - stage_next <= POST_SAMPLE_REMOVE; + -- Orphan Sample Removal in progress + if (orphan_samples = '1') then + -- End of Samples + if (next_sample = SAMPLE_MEMORY_MAX_ADDRESS) then + -- DONE + orphan_samples_next <= '0'; + stage_next <= IDLE; + else + -- Continue + stage_next <= REMOVE_ORPHAN_SAMPLES; + cur_sample_next <= next_sample; + cnt_next <= 0; + end if; + else + stage_next <= POST_SAMPLE_REMOVE; + end if; else - empty_payload_list_head_next <= resize(unsigned(sample_read_data),PAYLOAD_MEMORY_ADDR_WIDTH); + -- Latch First Payload Slot for later use + first_payload_next <= resize(unsigned(sample_read_data),PAYLOAD_MEMORY_ADDR_WIDTH); cnt_next <= cnt + 1; end if; end if; @@ -2141,6 +2449,9 @@ begin payload_addr <= cur_payload + PMF_NEXT_ADDR_OFFSET; payload_write_data <= std_logic_vector(resize(empty_payload_list_head,WORD_WIDTH)); + -- Fix Empty List Head + empty_payload_list_head_next <= first_payload; + -- Memory Flow Control Guard if (payload_ready_in = '1') then -- Orphan Sample Removal in progress @@ -2187,22 +2498,13 @@ begin end if; end if; else - inst_data_next.sample_cnt <= inst_data.sample_cnt - 1; + inst_data_next2.sample_cnt <= inst_data.sample_cnt - 1; -- Sample was ACKed if (sample_status_info(SSI_ACK_FLAG) = '1') then - inst_data_next.ack_cnt <= inst_data.ack_cnt - 1; + inst_data_next2.ack_cnt <= inst_data.ack_cnt - 1; end if; end if; - -- Update Global Sample Count - global_sample_cnt_next <= global_sample_cnt - 1; - - -- Update Global ACK Count - -- Sample was ACKed - if (sample_status_info(SSI_ACK_FLAG) = '1') then - global_ack_cnt_next <= global_ack_cnt - 1; - end if; - if (is_rtps = '1') then -- DONE done_rtps <= '1'; @@ -2224,7 +2526,7 @@ begin stage_next <= IDLE; end if; end if; - when SKIP_ADD_REJECT => + when SKIP_AND_RETURN => case (cnt) is -- SKIP READ when 0 => @@ -2233,16 +2535,23 @@ begin if (last_word_in_dds = '1') then cnt_next <= cnt + 1; end if; - -- REJECT SAMPLE + -- Return Code when 1 => done_dds <= '1'; - return_code_dds <= RETCODE_OUT_OF_RESOURCES; + return_code_dds <= return_code_latch; -- DONE stage_next <= IDLE; when others => null; end case; + when SKIP => + ready_in_dds <= '1'; + -- Wait until last word from input + if (last_word_in_dds = '1') then + stage_next <= return_stage; + cnt_next <= 0; + end if; when REMOVE_STALE_INSTANCE => -- Synthesis Guard if (WITH_KEY) then @@ -2394,17 +2703,24 @@ begin -- Memory Flow Control Guard if (sample_ready_in = '1') then - cnt_next <= cnt + 1; + if (WITH_KEY) then + cnt_next <= cnt + 1; + else + cnt_next <= cnt + 2; -- Skip Next Step + end if; end if; -- GET Instance Pointer when 3 => - sample_valid_in <= '1'; - sample_addr <= cur_sample + SMF_INSTANCE_ADDR_OFFSET; - sample_read <= '1'; - - -- Memory Flow Control Guard - if (sample_ready_in = '1') then - cnt_next <= cnt + 1; + -- Synthesis Guard + if (WITH_KEY) then + sample_valid_in <= '1'; + sample_addr <= cur_sample + SMF_INSTANCE_ADDR_OFFSET; + sample_read <= '1'; + + -- Memory Flow Control Guard + if (sample_ready_in = '1') then + cnt_next <= cnt + 1; + end if; end if; -- READ Previous Sample when 4 => @@ -2458,17 +2774,24 @@ begin cnt_next <= 0; end if; else - cnt_next <= cnt + 1; + if (WITH_KEY) then + cnt_next <= cnt + 1; + else + cnt_next <= cnt + 2; -- Skip Next Step + end if; end if; end if; -- READ Instance Pointer when 7 => - sample_ready_out <= '1'; - - -- Memory Flow Control Guard - if (sample_valid_out = '1') then - cur_inst_next <= resize(unsigned(sample_read_data),INSTANCE_MEMORY_ADDR_WIDTH); - cnt_next <= cnt + 1; + -- Synthesis Guard + if (WITH_KEY) then + sample_ready_out <= '1'; + + -- Memory Flow Control Guard + if (sample_valid_out = '1') then + cur_inst_next <= resize(unsigned(sample_read_data),INSTANCE_MEMORY_ADDR_WIDTH); + cnt_next <= cnt + 1; + end if; end if; -- Check Result when 8 => @@ -2480,14 +2803,20 @@ begin -- DONE stage_next <= IDLE; else - -- Memory Operation Guard - if (inst_op_done = '1') then - -- Fetch Instance Data - inst_op_start <= '1'; - inst_opcode <= GET_INSTANCE; - inst_mem_fields <= IMF_KEY_HASH_FLAG or IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_ACK_CNT_FLAG; - inst_addr_update <= cur_inst; - + -- Synthesis Guard + if (WITH_KEY) then + -- Memory Operation Guard + if (inst_op_done = '1') then + -- Fetch Instance Data + inst_op_start <= '1'; + inst_opcode <= GET_INSTANCE; + inst_mem_fields <= IMF_KEY_HASH_FLAG or IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_ACK_CNT_FLAG; + inst_addr_update <= cur_inst; + + stage_next <= return_stage; + cnt_next <= 0; + end if; + else stage_next <= return_stage; cnt_next <= 0; end if; @@ -2523,7 +2852,7 @@ begin cnt_next <= cnt + 1; end if; end if; - -- Set Status Info + -- SET Status Info when 2 => sample_valid_in <= '1'; sample_addr <= cur_sample + SMF_STATUS_INFO_OFFSET; @@ -2534,24 +2863,33 @@ begin global_ack_cnt_next <= (global_ack_cnt + 1) when (is_ack = '1') else (global_ack_cnt - 1); cnt_next <= cnt + 1; end if; - -- Set Instance Data + -- SET Instance Data when 3 => - -- Wait for Instance Data - if (inst_op_done = '1') then - -- Update - inst_op_start <= '1'; - inst_opcode <= UPDATE_INSTANCE; - inst_mem_fields <= IMF_ACK_CNT_FLAG; - inst_addr_update <= cur_inst; - ack_cnt <= (inst_data.ack_cnt + 1) when (is_ack = '1') else (inst_data.ack_cnt - 1); - - -- Update Stale Instance Count - -- XXX: Possible Worst Case Path (Addition and Comparison in same clock) - if (is_ack = '1' and inst_data.status_info(ISI_UNREGISTERED_FLAG) = '1' and (inst_data.ack_cnt+1) = inst_data.sample_cnt) then - stale_inst_cnt_next <= stale_inst_cnt + 1; - elsif (is_ack = '0' and inst_data.status_info(ISI_UNREGISTERED_FLAG) = '1' and inst_data.ack_cnt = inst_data.sample_cnt) then - stale_inst_cnt_next <= stale_inst_cnt - 1; + if (WITH_KEY) then + -- Wait for Instance Data + if (inst_op_done = '1') then + -- Update + inst_op_start <= '1'; + inst_opcode <= UPDATE_INSTANCE; + inst_mem_fields <= IMF_ACK_CNT_FLAG; + inst_addr_update <= cur_inst; + ack_cnt <= (inst_data.ack_cnt + 1) when (is_ack = '1') else (inst_data.ack_cnt - 1); + + -- Update Stale Instance Count + -- XXX: Possible Worst Case Path (Addition and Comparison in same clock) + if (is_ack = '1' and inst_data.status_info(ISI_UNREGISTERED_FLAG) = '1' and (inst_data.ack_cnt+1) = inst_data.sample_cnt) then + stale_inst_cnt_next <= stale_inst_cnt + 1; + elsif (is_ack = '0' and inst_data.status_info(ISI_UNREGISTERED_FLAG) = '1' and inst_data.ack_cnt = inst_data.sample_cnt) then + stale_inst_cnt_next <= stale_inst_cnt - 1; + end if; + + -- DONE + done_rtps <= '1'; + ret_rtps <= OK; + stage_next <= IDLE; end if; + else + inst_data_next2.ack_cnt <= (inst_data.ack_cnt + 1) when (is_ack = '1') else (inst_data.ack_cnt - 1); -- DONE done_rtps <= '1'; @@ -2647,15 +2985,22 @@ begin if (sample_valid_out = '1') then cur_payload_next <= resize(unsigned(sample_read_data),PAYLOAD_MEMORY_ADDR_WIDTH); - cnt_next <= cnt + 1; + if (WITH_KEY) then + cnt_next <= cnt + 1; + else + cnt_next <= cnt + 2; -- Skip Next Step + end if; end if; -- Instance Handle when 8 => - -- Wait for Instance Data - if (inst_op_done = '1') then - cc_instance_handle_sig_next <= inst_data.key_hash; - - cnt_next <= cnt + 1; + -- Synthesis Guard + if (WITH_KEY) then + -- Wait for Instance Data + if (inst_op_done = '1') then + cc_instance_handle_sig_next <= inst_data.key_hash; + + cnt_next <= cnt + 1; + end if; end if; -- Present Sample when 9 => @@ -2664,7 +3009,7 @@ begin -- RTPS Requestes Payload if (get_data_rtps = '1') then - if (cur_payload /= INSTANCE_MEMORY_MAX_ADDRESS) then + if (cur_payload /= PAYLOAD_MEMORY_MAX_ADDRESS) then -- Get Payload stage_next <= GET_PAYLOAD; cnt_next <= 0; @@ -2695,13 +3040,18 @@ begin case (cnt) is -- GET Next Pointer when 0 => - payload_valid_in <= '1'; - payload_addr <= cur_payload + PMF_NEXT_ADDR_OFFSET; - payload_read <= '1'; - - -- Memory Flow Control Guard - if (payload_ready_in = '1') then - cnt_next <= cnt + 1; + -- NOTE: We have to make sure that no pending Reads are in the Memory Controler Buffer, + -- else the Next Payload Pointer cannot be read. + -- No Pending Reads + if (cnt3 = 0) then + payload_valid_in <= '1'; + payload_addr <= cur_payload + PMF_NEXT_ADDR_OFFSET; + payload_read <= '1'; + + -- Memory Flow Control Guard + if (payload_ready_in = '1') then + cnt_next <= cnt + 1; + end if; end if; -- READ Next Pointer when 1 => @@ -2772,15 +3122,16 @@ begin if (cnt3 /= 0) then -- Memory Flow Control Guard if (payload_valid_out = '1') then - valid_out_dds <= '1'; + valid_out_rtps <= '1'; + data_out_rtps <= payload_read_data; -- End of Payload - if (cnt3 = 1 and cnt = 4) then - last_word_out_dds <= '1'; + if (cnt3 = 1 and cnt = 5) then + last_word_out_rtps <= '1'; end if; -- DDS Read - if (ready_out_dds = '1') then + if (ready_out_rtps = '1') then payload_ready_out <= '1'; -- NOTE: We are using the tmp_bool variable to signal if there is an increment -- on the same clock cycle. @@ -2793,7 +3144,7 @@ begin end if; end if; -- Finished Reading - elsif (cnt = 4) then + elsif (cnt = 5) then assert (cnt3 = 0) severity FAILURE; -- DONE stage_next <= IDLE; @@ -2830,17 +3181,24 @@ begin -- Memory Control Flow Guard if (sample_ready_in = '1') then - cnt_next <= cnt + 1; + if (WITH_KEY) then + cnt_next <= cnt + 1; + else + cnt_next <= cnt + 2; --Skip Next Step + end if; end if; -- GET Instance Pointer when 3 => - sample_valid_in <= '1'; - sample_addr <= cur_sample + SMF_INSTANCE_ADDR_OFFSET; - sample_read <= '1'; - - -- Memory Control Flow Guard - if (sample_ready_in = '1') then - cnt_next <= cnt + 1; + -- Synthesis Guard + if (WITH_KEY) then + sample_valid_in <= '1'; + sample_addr <= cur_sample + SMF_INSTANCE_ADDR_OFFSET; + sample_read <= '1'; + + -- Memory Control Flow Guard + if (sample_ready_in = '1') then + cnt_next <= cnt + 1; + end if; end if; -- READ Next Sample when 4 => @@ -2870,7 +3228,13 @@ begin -- Sample Lifespan Expired if (tmp_dw /= TIME_INVALID and time >= tmp_dw) then - cnt_next <= cnt + 1; + if (WITH_KEY) then + cnt_next <= cnt + 1; + else + -- Remove Sample + stage_next <= REMOVE_SAMPLE; + cnt_next <= 0; + end if; else sample_abort_read <= '1'; @@ -2892,21 +3256,24 @@ begin end if; -- READ Instance Pointer when 7 => - -- Memory Operation Guard - if (inst_op_done = '1') then - sample_ready_out <= '1'; - - -- Memory Control Flow Guard - if (sample_valid_out = '1') then - -- Fetch Instance Data - inst_op_start <= '1'; - inst_opcode <= GET_INSTANCE; - inst_mem_fields <= IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_ACK_CNT_FLAG; - inst_addr_update <= resize(unsigned(sample_read_data),INSTANCE_MEMORY_ADDR_WIDTH); + -- Synthesis Guard + if (WITH_KEY) then + -- Memory Operation Guard + if (inst_op_done = '1') then + sample_ready_out <= '1'; - -- Remove Sample - stage_next <= REMOVE_SAMPLE; - cnt_next <= 0; + -- Memory Control Flow Guard + if (sample_valid_out = '1') then + -- Fetch Instance Data + inst_op_start <= '1'; + inst_opcode <= GET_INSTANCE; + inst_mem_fields <= IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_ACK_CNT_FLAG; + inst_addr_update <= resize(unsigned(sample_read_data),INSTANCE_MEMORY_ADDR_WIDTH); + + -- Remove Sample + stage_next <= REMOVE_SAMPLE; + cnt_next <= 0; + end if; end if; end if; when others => @@ -3067,7 +3434,7 @@ begin prev_sample_next <= SAMPLE_MEMORY_MAX_ADDRESS; cur_sample_next <= (others => '0'); cnt_next <= cnt + 1; - -- Set Previous Pointer + -- SET Previous Pointer when 1 => sample_valid_in <= '1'; sample_addr <= cur_sample + SMF_PREV_ADDR_OFFSET; @@ -3077,7 +3444,7 @@ begin if (sample_ready_in = '1') then cnt_next <= cnt + 1; end if; - -- Set Next Pointer + -- SET Next Pointer when 2 => sample_valid_in <= '1'; sample_addr <= cur_sample + SMF_NEXT_ADDR_OFFSET; @@ -3104,12 +3471,12 @@ begin null; end case; when RESET_PAYLOAD_MEMORY => - case (inst_cnt) is + case (cnt) is -- Initialize when 0 => cur_payload_next <= (others => '0'); cnt_next <= cnt + 1; - -- Set Next Pointer + -- SET Next Pointer when 1 => payload_valid_in <= '1'; payload_addr <= cur_payload + PMF_NEXT_ADDR_OFFSET; @@ -3145,7 +3512,6 @@ begin -- SEARCH_INSTANCE_ADDR See Memory OPCODE Description -- GET_NEXT_INSTANCE See Memory OPCODE Description -- GET_INSTANCE_DATA Latch specified Instance Data for use by main process - -- FIND_POS Find List position of Instance to be added -- INSERT_INSTANCE See Memory OPCODE Description -- UPDATE_INSTANCE See Memory OPCODE Description -- REMOVE_INSTANCE See Memory OPCODE Description @@ -3169,6 +3535,7 @@ begin inst_valid_in <= '0'; inst_read <= '0'; inst_op_done <= '0'; + inst_abort_read <= '0'; inst_addr <= (others => '0'); inst_write_data <= (others => '0'); @@ -3193,14 +3560,14 @@ begin -- Reset Data inst_data_next <= ZERO_INSTANCE_DATA; - -- No Instances avialable + -- No Instances available if (inst_occupied_head = INSTANCE_MEMORY_MAX_ADDRESS) then inst_addr_base_next <= INSTANCE_MEMORY_MAX_ADDRESS; else - inst_prev_addr_base <= INSTANCE_MEMORY_MAX_ADDRESS; - inst_addr_base_next <= inst_occupied_head; - inst_stage_next <= SEARCH_INSTANCE_HASH; - inst_cnt_next <= 0; + inst_prev_addr_base_next <= INSTANCE_MEMORY_MAX_ADDRESS; + inst_addr_base_next <= inst_occupied_head; + inst_stage_next <= SEARCH_INSTANCE_HASH; + inst_cnt_next <= 0; end if; when SEARCH_INSTANCE_ADDR => -- Reset Data @@ -3210,20 +3577,21 @@ begin if (inst_occupied_head = INSTANCE_MEMORY_MAX_ADDRESS) then inst_addr_base_next <= INSTANCE_MEMORY_MAX_ADDRESS; else - inst_prev_addr_base <= INSTANCE_MEMORY_MAX_ADDRESS; - inst_addr_base_next <= inst_occupied_head; - inst_stage_next <= SEARCH_INSTANCE_ADDR; - inst_cnt_next <= 0; + inst_prev_addr_base_next <= INSTANCE_MEMORY_MAX_ADDRESS; + inst_addr_base_next <= inst_occupied_head; + inst_stage_next <= SEARCH_INSTANCE_ADDR; + inst_cnt_next <= 0; end if; when INSERT_INSTANCE => -- NOTE: Since this process has no way to communicate a failed insert to the main process, it has to be made sure -- by the main process that the operation can succeed (Memory is available) assert (inst_empty_head /= INSTANCE_MEMORY_MAX_ADDRESS) report "Instance Insertion while memory Full" severity FAILURE; - inst_addr_base_next <= inst_occupied_head; - inst_stage_next <= FIND_POS; - inst_cnt_next <= 0; - -- Set Instance Data + inst_addr_base_next <= inst_empty_head; + inst_stage_next <= INSERT_INSTANCE; + inst_cnt_next <= 0; + + -- SET Instance Data inst_data_next.key_hash <= key_hash_next; inst_data_next.status_info <= status_info_update; inst_data_next.sample_cnt <= sample_cnt; @@ -3245,23 +3613,10 @@ begin if (inst_occupied_head = INSTANCE_MEMORY_MAX_ADDRESS) then inst_addr_base_next <= INSTANCE_MEMORY_MAX_ADDRESS; else - inst_prev_addr_base_next <= INSTANCE_MEMORY_MAX_ADDRESS; - inst_addr_base_next <= inst_occupied_head; - -- Get Instance Data - inst_data_next <= ZERO_INSTANCE_DATA; - inst_stage_next <= GET_INSTANCE_DATA; - if check_mask(inst_mem_fields,IMF_KEY_HASH_FLAG) then - inst_cnt_next <= 0; - elsif check_mask(inst_mem_fields,IMF_STATUS_FLAG) then - inst_cnt_next <= 4; - elsif check_mask(inst_mem_fields,IMF_SAMPLE_CNT_FLAG) then - inst_cnt_next <= 5; - elsif check_mask(inst_mem_fields,IMF_ACK_CNT_FLAG) then - inst_cnt_next <= 6; - else - -- DONE - inst_stage_next <= IDLE; - end if; + inst_prev_addr_base_next <= INSTANCE_MEMORY_MAX_ADDRESS; + inst_addr_base_next <= inst_occupied_head; + inst_stage_next <= GET_NEXT_INSTANCE; + inst_cnt_next <= 0; end if; when GET_NEXT_INSTANCE => -- No Instances avialable @@ -3367,6 +3722,7 @@ begin if (inst_valid_out = '1') then -- No Match if (inst_read_data /= inst_latch_data.key_hash(0)) then + inst_abort_read <= '1'; -- Reached List Tail, No Match if (inst_next_addr_base = INSTANCE_MEMORY_MAX_ADDRESS) then inst_addr_base_next <= INSTANCE_MEMORY_MAX_ADDRESS; --No match @@ -3377,7 +3733,6 @@ begin inst_prev_addr_base_next <= inst_addr_base; inst_addr_base_next <= inst_next_addr_base; inst_cnt_next <= 0; - inst_abort_read <= '1'; end if; else inst_cnt_next <= inst_cnt + 1; @@ -3391,6 +3746,7 @@ begin if (inst_valid_out = '1') then -- No Match if (inst_read_data /= inst_latch_data.key_hash(1)) then + inst_abort_read <= '1'; -- Reached List Tail, No Match if (inst_next_addr_base = INSTANCE_MEMORY_MAX_ADDRESS) then inst_addr_base_next <= INSTANCE_MEMORY_MAX_ADDRESS; --No match @@ -3401,7 +3757,6 @@ begin inst_prev_addr_base_next <= inst_addr_base; inst_addr_base_next <= inst_next_addr_base; inst_cnt_next <= 0; - inst_abort_read <= '1'; end if; else inst_cnt_next <= inst_cnt + 1; @@ -3415,6 +3770,7 @@ begin if (inst_valid_out = '1') then -- No Match if (inst_read_data /= inst_latch_data.key_hash(2)) then + inst_abort_read <= '1'; -- Reached List Tail, No Match if (inst_next_addr_base = INSTANCE_MEMORY_MAX_ADDRESS) then inst_addr_base_next <= INSTANCE_MEMORY_MAX_ADDRESS; --No match @@ -3425,7 +3781,6 @@ begin inst_prev_addr_base_next <= inst_addr_base; inst_addr_base_next <= inst_next_addr_base; inst_cnt_next <= 0; - inst_abort_read <= '1'; end if; else inst_cnt_next <= inst_cnt + 1; @@ -3449,7 +3804,6 @@ begin inst_prev_addr_base_next <= inst_addr_base; inst_addr_base_next <= inst_next_addr_base; inst_cnt_next <= 0; - inst_abort_read <= '1'; end if; else -- Get Instance Data @@ -3679,7 +4033,7 @@ begin -- Memory Flow Control Guard if (inst_valid_out = '1') then - inst_latch_data_next.key_hash(0) <= inst_read_data; + inst_data_next.key_hash(0) <= inst_read_data; inst_cnt_next <= inst_cnt + 1; end if; -- READ Key Hash 2/4 @@ -3688,7 +4042,7 @@ begin -- Memory Flow Control Guard if (inst_valid_out = '1') then - inst_latch_data_next.key_hash(1) <= inst_read_data; + inst_data_next.key_hash(1) <= inst_read_data; inst_cnt_next <= inst_cnt + 1; end if; -- READ Key Hash 3/4 @@ -3697,7 +4051,7 @@ begin -- Memory Flow Control Guard if (inst_valid_out = '1') then - inst_latch_data_next.key_hash(2) <= inst_read_data; + inst_data_next.key_hash(2) <= inst_read_data; inst_cnt_next <= inst_cnt + 1; end if; -- READ Key Hash 4/4 @@ -3706,7 +4060,7 @@ begin -- Memory Flow Control Guard if (inst_valid_out = '1') then - inst_latch_data_next.key_hash(3) <= inst_read_data; + inst_data_next.key_hash(3) <= inst_read_data; if check_mask(inst_latch_data.field_flags,IMF_STATUS_FLAG) then inst_cnt_next <= 11; @@ -3725,7 +4079,7 @@ begin -- Memory Flow Control Guard if (inst_valid_out = '1') then - inst_latch_data_next.status_info <= inst_read_data; + inst_data_next.status_info <= inst_read_data; if check_mask(inst_latch_data.field_flags,IMF_SAMPLE_CNT_FLAG) then inst_cnt_next <= 12; @@ -3742,7 +4096,7 @@ begin -- Memory Flow Control Guard if (inst_valid_out = '1') then - inst_latch_data_next.sample_cnt <= unsigned(inst_read_data); + inst_data_next.sample_cnt <= unsigned(inst_read_data); if check_mask(inst_latch_data.field_flags,IMF_ACK_CNT_FLAG) then inst_cnt_next <= 13; @@ -3757,209 +4111,17 @@ begin -- Memory Flow Control Guard if (inst_valid_out = '1') then - inst_latch_data_next.ack_cnt <= unsigned(inst_read_data); + inst_data_next.ack_cnt <= unsigned(inst_read_data); -- DONE inst_stage_next <= IDLE; end if; end case; - when FIND_POS => - -- NOTE: Instances are inserted in KEY_HASH numerical order. - - -- TODO: Handle inst_next_addr_base = MAX_ADDR - - case (inst_cnt) is - -- GET Next Instance - when 0 => - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_NEXT_ADDR_OFFSET; - inst_read <= '1'; - - -- Memory Flow Control Guard - if (inst_ready_in = '1') then - inst_cnt_next <= inst_cnt + 1; - end if; - -- GET Key Hash 1/4 - when 1 => - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_KEY_HASH_OFFSET; - inst_read <= '1'; - - -- Memory Flow Control Guard - if (inst_ready_in = '1') then - inst_cnt_next <= inst_cnt + 1; - end if; - -- GET Key Hash 2/4 - when 2 => - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_KEY_HASH_OFFSET + 1; - inst_read <= '1'; - - -- Memory Flow Control Guard - if (inst_ready_in = '1') then - inst_cnt_next <= inst_cnt + 1; - end if; - -- GET Key Hash 3/4 - when 3 => - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_KEY_HASH_OFFSET + 2; - inst_read <= '1'; - - -- Memory Flow Control Guard - if (inst_ready_in = '1') then - inst_cnt_next <= inst_cnt + 1; - end if; - -- GET Key Hash 4/4 - when 4 => - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_KEY_HASH_OFFSET + 3; - inst_read <= '1'; - - -- Memory Flow Control Guard - if (inst_ready_in = '1') then - inst_cnt_next <= inst_cnt + 1; - end if; - -- READ Next Instance - when 5 => - inst_ready_out <= '1'; - - -- Memory Flow Control Guard - if (inst_valid_out = '1') then - inst_next_addr_base_next <= resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH); - inst_cnt_next <= inst_cnt + 1; - end if; - -- READ Key Hash 1/4 - when 6 => - inst_ready_out <= '1'; - - -- Memory Flow Control Guard - if (inst_valid_out = '1') then - -- Found Position (Before Current Instance) - if (inst_latch_data.key_hash(0) < inst_read_data) then - inst_next_addr_base_next <= inst_addr_base; - -- Occupied List Head - if (inst_prev_addr_base = INSTANCE_MEMORY_MAX_ADDRESS) then - assert (inst_addr_base = inst_occupied_head) severity FAILURE; - inst_occupied_head_next <= inst_empty_head; - - inst_addr_base_next <= inst_empty_head; - inst_stage_next <= INSERT_INSTANCE; - cnt_next <= 1; -- Skip First Step - else - inst_addr_base_next <= inst_prev_addr_base; - inst_stage_next <= INSERT_INSTANCE; - cnt_next <= 0; - end if; - -- BIGGER-THAN - elsif (inst_latch_data.key_hash(0) /= inst_read_data) then - -- Continue - inst_prev_addr_base_next <= inst_addr_base; - inst_addr_base_next <= inst_next_addr_base; - cnt_next <= 0; - inst_abort_read <= '1'; - end if; - end if; - -- READ Key Hash 2/4 - when 7 => - inst_ready_out <= '1'; - - -- Memory Flow Control Guard - if (inst_valid_out = '1') then - -- Found Position (Before Current Instance) - if (inst_latch_data.key_hash(1) < inst_read_data) then - inst_next_addr_base_next <= inst_addr_base; - -- Occupied List Head - if (inst_prev_addr_base = INSTANCE_MEMORY_MAX_ADDRESS) then - assert (inst_addr_base = inst_occupied_head) severity FAILURE; - inst_occupied_head_next <= inst_empty_head; - - inst_addr_base_next <= inst_empty_head; - inst_stage_next <= INSERT_INSTANCE; - cnt_next <= 1; -- Skip First Step - else - inst_addr_base_next <= inst_prev_addr_base; - inst_stage_next <= INSERT_INSTANCE; - cnt_next <= 0; - end if; - -- BIGGER-THAN - elsif (inst_latch_data.key_hash(1) /= inst_read_data) then - -- Continue - inst_prev_addr_base_next <= inst_addr_base; - inst_addr_base_next <= inst_next_addr_base; - cnt_next <= 0; - inst_abort_read <= '1'; - end if; - end if; - -- READ Key Hash 3/4 - when 8 => - inst_ready_out <= '1'; - - -- Memory Flow Control Guard - if (inst_valid_out = '1') then - -- Found Position (Before Current Instance) - if (inst_latch_data.key_hash(2) < inst_read_data) then - inst_next_addr_base_next <= inst_addr_base; - -- Occupied List Head - if (inst_prev_addr_base = INSTANCE_MEMORY_MAX_ADDRESS) then - assert (inst_addr_base = inst_occupied_head) severity FAILURE; - inst_occupied_head_next <= inst_empty_head; - - inst_addr_base_next <= inst_empty_head; - inst_stage_next <= INSERT_INSTANCE; - cnt_next <= 1; -- Skip First Step - else - inst_addr_base_next <= inst_prev_addr_base; - inst_stage_next <= INSERT_INSTANCE; - cnt_next <= 0; - end if; - -- BIGGER-THAN - elsif (inst_latch_data.key_hash(2) /= inst_read_data) then - -- Continue - inst_prev_addr_base_next <= inst_addr_base; - inst_addr_base_next <= inst_next_addr_base; - cnt_next <= 0; - inst_abort_read <= '1'; - end if; - end if; - -- Key Hash 4/4 - when 9 => - inst_ready_out <= '1'; - - -- Memory Flow Control Guard - if (inst_valid_out = '1') then - -- Found Position - if (inst_latch_data.key_hash(3) < inst_read_data) then - inst_next_addr_base_next <= inst_addr_base; - -- Occupied List Head - if (inst_prev_addr_base = INSTANCE_MEMORY_MAX_ADDRESS) then - assert (inst_addr_base = inst_occupied_head) severity FAILURE; - inst_occupied_head_next <= inst_empty_head; - - inst_addr_base_next <= inst_empty_head; - inst_stage_next <= INSERT_INSTANCE; - cnt_next <= 1; -- Skip First Step - else - inst_addr_base_next <= inst_prev_addr_base; - inst_stage_next <= INSERT_INSTANCE; - cnt_next <= 0; - end if; - else - assert (inst_latch_data.key_hash(3) /= inst_read_data) report "Doublicate Instance Detected" severity FAILURE; - - -- Continue - inst_prev_addr_base_next <= inst_addr_base; - inst_addr_base_next <= inst_next_addr_base; - cnt_next <= 0; - end if; - end if; - when others => - null; - end case; when INSERT_INSTANCE => - -- Precondition: inst_addr_base set, inst_prev_addr_base set + -- Precondition: inst_addr_base set case (inst_cnt) is - -- GET Next Pointer + -- GET Next Instance Pointer when 0 => inst_valid_in <= '1'; inst_addr <= inst_addr_base + IMF_NEXT_ADDR_OFFSET; @@ -3967,24 +4129,22 @@ begin -- Memory Flow Control Guard if (inst_ready_in = '1') then - -- Insert to Occupied List Head - if (inst_prev_addr_base = INSTANCE_MEMORY_MAX_ADDRESS) then - inst_cnt_next <= inst_cnt + 2; - else - inst_cnt_next <= inst_cnt + 1; - end if; + inst_cnt_next <= inst_cnt + 1; end if; - -- Next Pointer (Previous Instance) + -- SET Next Instance Pointer when 1 => - inst_valid_in <= '1'; - inst_addr <= inst_prev_addr_base + IMF_NEXT_ADDR_OFFSET; - inst_write_data <= std_logic_vector(resize(inst_addr_base,WORD_WIDTH)); + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_NEXT_ADDR_OFFSET; + inst_write_data <= std_logic_vector(resize(inst_occupied_head,WORD_WIDTH)); -- Memory Flow Control Guard if (inst_ready_in = '1') then - inst_cnt_next <= inst_cnt + 1; + -- Fix Occupied List Head + inst_occupied_head_next <= inst_addr_base; + + inst_cnt_next <= inst_cnt + 1; end if; - -- READ Next Pointer + -- READ Next Instance Pointer when 2 => inst_ready_out <= '1'; @@ -3995,7 +4155,7 @@ begin inst_cnt_next <= inst_cnt + 1; end if; - -- Key Hash 1/4 + -- SET Key Hash 1/4 when 3 => inst_valid_in <= '1'; inst_addr <= inst_addr_base + IMF_KEY_HASH_OFFSET; @@ -4005,7 +4165,7 @@ begin if (inst_ready_in = '1') then inst_cnt_next <= inst_cnt + 1; end if; - -- Key Hash 2/4 + -- SET Key Hash 2/4 when 4 => inst_valid_in <= '1'; inst_addr <= inst_addr_base + IMF_KEY_HASH_OFFSET + 1; @@ -4015,7 +4175,7 @@ begin if (inst_ready_in = '1') then inst_cnt_next <= inst_cnt + 1; end if; - -- Key Hash 3/4 + -- SET Key Hash 3/4 when 5 => inst_valid_in <= '1'; inst_addr <= inst_addr_base + IMF_KEY_HASH_OFFSET + 2; @@ -4025,7 +4185,7 @@ begin if (inst_ready_in = '1') then inst_cnt_next <= inst_cnt + 1; end if; - -- Key Hash 4/4 + -- SET Key Hash 4/4 when 6 => inst_valid_in <= '1'; inst_addr <= inst_addr_base + IMF_KEY_HASH_OFFSET + 3; @@ -4035,7 +4195,7 @@ begin if (inst_ready_in = '1') then inst_cnt_next <= inst_cnt + 1; end if; - -- Status Info + -- SET Status Info when 7 => inst_valid_in <= '1'; inst_addr <= inst_addr_base + IMF_STATUS_INFO_OFFSET; @@ -4045,7 +4205,7 @@ begin if (inst_ready_in = '1') then inst_cnt_next <= inst_cnt + 1; end if; - -- Sample Count + -- SET Sample Count when 8 => inst_valid_in <= '1'; inst_addr <= inst_addr_base + IMF_SAMPLE_CNT_OFFSET; @@ -4055,7 +4215,7 @@ begin if (inst_ready_in = '1') then inst_cnt_next <= inst_cnt + 1; end if; - -- ACK Count + -- SET ACK Count when 9 => inst_valid_in <= '1'; inst_addr <= inst_addr_base + IMF_ACK_CNT_OFFSET; @@ -4138,9 +4298,20 @@ begin -- Memory Flow Control Guard if (inst_valid_out = '1') then inst_next_addr_base_next <= resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH); - inst_cnt_next <= inst_cnt + 1; + + -- Removed Instance is List Head + if (inst_prev_addr_base = INSTANCE_MEMORY_MAX_ADDRESS) then + assert (inst_addr_base = inst_occupied_head) severity FAILURE; + + -- Fix Occupied Head + inst_occupied_head_next <= resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH); + + inst_cnt_next <= inst_cnt + 2; -- Skip Next Step + else + inst_cnt_next <= inst_cnt + 1; + end if; end if; - -- Next Pointer (Previous Instance) + -- SET Next Pointer (Previous Instance) when 2 => -- Point Previous instance to Next Instance (Remove current Instance from inbetween) inst_valid_in <= '1'; @@ -4151,7 +4322,7 @@ begin if (inst_ready_in = '1') then inst_cnt_next <= inst_cnt + 1; end if; - -- Next Pointer (Current/Removed Instance) + -- SET Next Pointer (Current/Removed Instance) when 3 => -- Point Current Instance to Empty List Head (Make Removed Instance Head of the Empty List) inst_valid_in <= '1'; @@ -4179,7 +4350,7 @@ begin when 0 => inst_addr_base_next <= FIRST_INSTANCE_ADDRESS; inst_cnt_next <= inst_cnt + 1; - -- Set Next Pointer + -- SET Next Pointer when 1 => inst_valid_in <= '1'; inst_addr <= inst_addr_base + IMF_NEXT_ADDR_OFFSET; @@ -4211,141 +4382,147 @@ begin begin if rising_edge(clk) then if (reset = '1') then - stage <= RESET_SAMPLE_MEMORY; - return_stage <= IDLE; - inst_stage <= RESET_MEMORY; - instance_handle <= HANDLE_NIL; - cc_instance_handle_sig <= HANDLE_NIL; - sample_rej_last_inst <= HANDLE_NIL; - deadline_miss_last_inst <= HANDLE_NIL; - key_hash <= HANDLE_NIL; - deadline_time <= TIME_INVALID; - lifespan_time <= TIME_INVALID; - source_ts <= TIME_INVALID; - timeout_time <= TIME_INVALID; - lease_deadline <= TIME_INVALID; - cc_source_timestamp_sig <= TIME_INVALID; - lifespan <= DURATION_INFINITE; - global_seq_nr <= SEQUENCENUMBER_UNKNOWN; - seq_nr <= SEQUENCENUMBER_UNKNOWN; - cc_kind_sig <= ALIVE; - inst_data <= ZERO_INSTANCE_DATA; - inst_latch_data <= ZERO_INST_LATCH_DATA; - cnt <= 0; - cnt2 <= 0; - cnt3 <= 0; - global_sample_cnt <= 0; - global_ack_cnt <= 0; - stale_inst_cnt <= 0; - inst_cnt <= 0; - inst_cnt2 <= 0; - remove_oldest_sample <= '0'; - remove_oldest_inst_sample <= '0'; - is_lifespan_check <= '0'; - register_op <= '0'; - lookup_op <= '0'; - ack_wait <= '0'; - is_ack <= '0'; - is_rtps <= '0'; - data_available_sig <= '0'; - orphan_samples <= '0'; - newest_sample <= (others => '0'); - oldest_sample <= (others => '0'); - empty_payload_list_head <= (others => '0'); - empty_sample_list_head <= (others => '0'); - empty_sample_list_tail <= (others => '0'); - payload_addr_latch_1 <= (others => '0'); - payload_addr_latch_2 <= (others => '0'); - long_latch <= (others => '0'); - sample_addr_latch_1 <= (others => '0'); - sample_addr_latch_2 <= (others => '0'); - sample_addr_latch_3 <= (others => '0'); - sample_addr_latch_4 <= (others => '0'); - inst_addr_latch_1 <= (others => '0'); - inst_addr_latch_2 <= (others => '0'); - sample_status_info <= (others => '0'); - sample_rej_cnt <= (others => '0'); - sample_rej_cnt_change <= (others => '0'); - sample_rej_last_reason <= (others => '0'); - deadline_miss_cnt <= (others => '0'); - deadline_miss_cnt_change <= (others => '0'); - liveliness_lost_cnt <= (others => '0'); - liveliness_lost_cnt_change <= (others => '0'); - status_sig <= (others => '0'); - inst_addr_base <= (others => '0'); - inst_empty_head <= (others => '0'); - inst_occupied_head <= (others => '0'); - inst_long_latch <= (others => '0'); - inst_next_addr_base <= (others => '0'); - inst_prev_addr_base <= (others => '0'); + stage <= RESET_SAMPLE_MEMORY; + return_stage <= IDLE; + inst_stage <= RESET_MEMORY; + instance_handle <= HANDLE_NIL; + cc_instance_handle_sig <= HANDLE_NIL; + sample_rej_last_inst <= HANDLE_NIL; + deadline_miss_last_inst <= HANDLE_NIL; + key_hash <= HANDLE_NIL; + deadline_time <= TIME_INVALID; + lifespan_time <= TIME_INVALID; + source_ts <= TIME_INVALID; + timeout_time <= TIME_INVALID; + lease_deadline <= TIME_INVALID; + cc_source_timestamp_sig <= TIME_INVALID; + lifespan <= DURATION_INFINITE; + global_seq_nr <= FIRST_SEQUENCENUMBER; + seq_nr <= SEQUENCENUMBER_UNKNOWN; + cc_seq_nr_sig <= SEQUENCENUMBER_UNKNOWN; + cc_kind_sig <= ALIVE; + inst_data <= ZERO_INSTANCE_DATA; + inst_latch_data <= ZERO_INST_LATCH_DATA; + cnt <= 0; + cnt2 <= 0; + cnt3 <= 0; + global_sample_cnt <= 0; + global_ack_cnt <= 0; + stale_inst_cnt <= 0; + inst_cnt <= 0; + inst_cnt2 <= 0; + remove_oldest_sample <= '0'; + remove_oldest_inst_sample <= '0'; + remove_ack_sample <= '0'; + is_lifespan_check <= '0'; + register_op <= '0'; + lookup_op <= '0'; + ack_wait <= '0'; + is_ack <= '0'; + is_rtps <= '0'; + data_available_sig <= '0'; + orphan_samples <= '0'; + newest_sample <= SAMPLE_MEMORY_MAX_ADDRESS; + oldest_sample <= SAMPLE_MEMORY_MAX_ADDRESS; + empty_payload_list_head <= FIRST_PAYLOAD_ADDRESS; + empty_sample_list_head <= FIRST_SAMPLE_ADDRESS; + empty_sample_list_tail <= MAX_SAMPLE_ADDRESS; + payload_addr_latch_1 <= (others => '0'); + payload_addr_latch_2 <= (others => '0'); + long_latch <= (others => '0'); + sample_addr_latch_1 <= (others => '0'); + sample_addr_latch_2 <= (others => '0'); + sample_addr_latch_3 <= (others => '0'); + sample_addr_latch_4 <= (others => '0'); + inst_addr_latch_1 <= (others => '0'); + inst_addr_latch_2 <= (others => '0'); + sample_status_info <= (others => '0'); + sample_rej_cnt <= (others => '0'); + sample_rej_cnt_change <= (others => '0'); + sample_rej_last_reason <= (others => '0'); + deadline_miss_cnt <= (others => '0'); + deadline_miss_cnt_change <= (others => '0'); + liveliness_lost_cnt <= (others => '0'); + liveliness_lost_cnt_change <= (others => '0'); + status_sig <= (others => '0'); + inst_addr_base <= (others => '0'); + inst_empty_head <= FIRST_INSTANCE_ADDRESS; + inst_occupied_head <= INSTANCE_MEMORY_MAX_ADDRESS; + inst_long_latch <= (others => '0'); + inst_next_addr_base <= (others => '0'); + inst_prev_addr_base <= (others => '0'); + return_code_latch <= RETCODE_UNSUPPORTED; else - stage <= stage_next; - return_stage <= return_stage_next; - inst_stage <= inst_stage_next; - instance_handle <= instance_handle_next; - cc_instance_handle_sig <= cc_instance_handle_sig_next; - sample_rej_last_inst <= sample_rej_last_inst_next; - deadline_miss_last_inst <= deadline_miss_last_inst_next; - key_hash <= key_hash_next; - deadline_time <= deadline_time_next; - lifespan_time <= lifespan_time_next; - source_ts <= source_ts_next; - timeout_time <= timeout_time_next; - lease_deadline <= lease_deadline_next; - cc_source_timestamp_sig <= cc_source_timestamp_sig; - lifespan <= lifespan_next; - global_seq_nr <= global_seq_nr_next; - seq_nr <= seq_nr_next; - cc_kind_sig <= cc_kind_sig_next; - inst_data <= inst_data_next; - inst_latch_data <= inst_latch_data_next; - cnt <= cnt_next; - cnt2 <= cnt2_next; - cnt3 <= cnt3_next; - global_sample_cnt <= global_sample_cnt_next; - global_ack_cnt <= global_ack_cnt_next; - stale_inst_cnt <= stale_inst_cnt_next; - inst_cnt <= inst_cnt_next; - inst_cnt2 <= inst_cnt2_next; - remove_oldest_sample <= remove_oldest_sample_next; - remove_oldest_inst_sample <= remove_oldest_inst_sample_next; - is_lifespan_check <= is_lifespan_check_next; - register_op <= register_op_next; - lookup_op <= lookup_op_next; - ack_wait <= ack_wait_next; - is_ack <= is_ack_next; - is_rtps <= is_rtps_next; - data_available_sig <= data_available_sig_next; - orphan_samples <= orphan_samples_next; - newest_sample <= newest_sample_next; - oldest_sample <= oldest_sample_next; - empty_payload_list_head <= empty_payload_list_head_next; - empty_sample_list_head <= empty_sample_list_head_next; - empty_sample_list_tail <= empty_sample_list_tail_next; - payload_addr_latch_1 <= payload_addr_latch_1_next; - payload_addr_latch_2 <= payload_addr_latch_2_next; - long_latch <= long_latch_next; - sample_addr_latch_1 <= sample_addr_latch_1_next; - sample_addr_latch_2 <= sample_addr_latch_2_next; - sample_addr_latch_3 <= sample_addr_latch_3_next; - sample_addr_latch_4 <= sample_addr_latch_4_next; - inst_addr_latch_1 <= inst_addr_latch_1_next; - inst_addr_latch_2 <= inst_addr_latch_2_next; - sample_status_info <= sample_status_info_next; - sample_rej_cnt <= sample_rej_cnt_next; - sample_rej_cnt_change <= sample_rej_cnt_change_next; - sample_rej_last_reason <= sample_rej_last_reason_next; - deadline_miss_cnt <= deadline_miss_cnt_next; - deadline_miss_cnt_change <= deadline_miss_cnt_change_next; - liveliness_lost_cnt <= liveliness_lost_cnt_next; - liveliness_lost_cnt_change <= liveliness_lost_cnt_change_next; - status_sig <= status_sig_next; - inst_addr_base <= inst_addr_base_next; - inst_empty_head <= inst_empty_head_next; - inst_occupied_head <= inst_occupied_head_next; - inst_long_latch <= inst_long_latch_next; - inst_next_addr_base <= inst_next_addr_base_next; - inst_prev_addr_base <= inst_prev_addr_base_next; + stage <= stage_next; + return_stage <= return_stage_next; + inst_stage <= inst_stage_next; + instance_handle <= instance_handle_next; + cc_instance_handle_sig <= cc_instance_handle_sig_next; + sample_rej_last_inst <= sample_rej_last_inst_next; + deadline_miss_last_inst <= deadline_miss_last_inst_next; + key_hash <= key_hash_next; + deadline_time <= deadline_time_next; + lifespan_time <= lifespan_time_next; + source_ts <= source_ts_next; + timeout_time <= timeout_time_next; + lease_deadline <= lease_deadline_next; + cc_source_timestamp_sig <= cc_source_timestamp_sig_next; + lifespan <= lifespan_next; + global_seq_nr <= global_seq_nr_next; + seq_nr <= seq_nr_next; + cc_seq_nr_sig <= cc_seq_nr_sig_next; + cc_kind_sig <= cc_kind_sig_next; + inst_data <= inst_data_next when WITH_KEY else inst_data_next2; + inst_latch_data <= inst_latch_data_next; + cnt <= cnt_next; + cnt2 <= cnt2_next; + cnt3 <= cnt3_next; + global_sample_cnt <= global_sample_cnt_next; + global_ack_cnt <= global_ack_cnt_next; + stale_inst_cnt <= stale_inst_cnt_next; + inst_cnt <= inst_cnt_next; + inst_cnt2 <= inst_cnt2_next; + remove_oldest_sample <= remove_oldest_sample_next; + remove_oldest_inst_sample <= remove_oldest_inst_sample_next; + remove_ack_sample <= remove_ack_sample_next; + is_lifespan_check <= is_lifespan_check_next; + register_op <= register_op_next; + lookup_op <= lookup_op_next; + ack_wait <= ack_wait_next; + is_ack <= is_ack_next; + is_rtps <= is_rtps_next; + data_available_sig <= data_available_sig_next; + orphan_samples <= orphan_samples_next; + newest_sample <= newest_sample_next; + oldest_sample <= oldest_sample_next; + empty_payload_list_head <= empty_payload_list_head_next; + empty_sample_list_head <= empty_sample_list_head_next; + empty_sample_list_tail <= empty_sample_list_tail_next; + payload_addr_latch_1 <= payload_addr_latch_1_next; + payload_addr_latch_2 <= payload_addr_latch_2_next; + long_latch <= long_latch_next; + sample_addr_latch_1 <= sample_addr_latch_1_next; + sample_addr_latch_2 <= sample_addr_latch_2_next; + sample_addr_latch_3 <= sample_addr_latch_3_next; + sample_addr_latch_4 <= sample_addr_latch_4_next; + inst_addr_latch_1 <= inst_addr_latch_1_next; + inst_addr_latch_2 <= inst_addr_latch_2_next; + sample_status_info <= sample_status_info_next; + sample_rej_cnt <= sample_rej_cnt_next; + sample_rej_cnt_change <= sample_rej_cnt_change_next; + sample_rej_last_reason <= sample_rej_last_reason_next; + deadline_miss_cnt <= deadline_miss_cnt_next; + deadline_miss_cnt_change <= deadline_miss_cnt_change_next; + liveliness_lost_cnt <= liveliness_lost_cnt_next; + liveliness_lost_cnt_change <= liveliness_lost_cnt_change_next; + status_sig <= status_sig_next; + inst_addr_base <= inst_addr_base_next; + inst_empty_head <= inst_empty_head_next; + inst_occupied_head <= inst_occupied_head_next; + inst_long_latch <= inst_long_latch_next; + inst_next_addr_base <= inst_next_addr_base_next; + inst_prev_addr_base <= inst_prev_addr_base_next; + return_code_latch <= return_code_latch_next; end if; end if; end process; diff --git a/src/rtps_config_package.vhd b/src/rtps_config_package.vhd index 2d19267..a7035a4 100644 --- a/src/rtps_config_package.vhd +++ b/src/rtps_config_package.vhd @@ -42,7 +42,7 @@ package rtps_config_package is constant OPCODE_LIVELINESS_UPDATE : std_logic_vector(ENDPOINT_MATCH_OPCODE_WIDTH-1 downto 0) := x"55000003"; type HISTORY_CACHE_OPCODE_TYPE is (NOP, ADD_CACHE_CHANGE, GET_CACHE_CHANGE, ACK_CACHE_CHANGE, NACK_CACHE_CHANGE, REMOVE_CACHE_CHANGE, REMOVE_WRITER, GET_MIN_SN, GET_MAX_SN); - type KEY_HOLDER_TYPE is (NOP, PUSH_DATA, PUSH_SERIALIZED_KEY, READ_KEY_HASH, READ_SERIALIZED_KEY); + type KEY_HOLDER_OPCODE_TYPE is (NOP, PUSH_DATA, PUSH_SERIALIZED_KEY, READ_KEY_HASH, READ_SERIALIZED_KEY); type KEY_GENERATOR_OPCODE_TYPE is (NOP, WRITE_PAYLOAD, READ_KEY, READ_SIZE); type HISTORY_CACHE_RESPONSE_TYPE is (OK, REJECTED, INVALID, ERROR); type DDS_WRITER_OPCODE_TYPE is (NOP, REGISTER_INSTANCE, WRITE, DISPOSE, UNREGISTER_INSTANCE, LOOKUP_INSTANCE, WAIT_FOR_ACKNOWLEDGEMENTS, GET_OFFERED_DEADLINE_MISSED_STATUS, ASSERT_LIVELINESS, GET_LIVELINESS_LOST_STATUS); diff --git a/src/rtps_test_package.vhd b/src/rtps_test_package.vhd index e7e401c..b576280 100644 --- a/src/rtps_test_package.vhd +++ b/src/rtps_test_package.vhd @@ -14,11 +14,11 @@ package rtps_test_package is constant RESULTS_FILE : string := "./Test_Results.txt"; - constant PARTICIPANT_FRAME_SIZE : natural := 23; - constant WRITER_ENDPOINT_FRAME_SIZE_A : natural := 12; - constant WRITER_ENDPOINT_FRAME_SIZE_B : natural := 8; - constant READER_ENDPOINT_FRAME_SIZE_A : natural := 15; - constant READER_ENDPOINT_FRAME_SIZE_B : natural := 6; + constant PARTICIPANT_FRAME_SIZE : natural := 23; + constant WRITER_ENDPOINT_FRAME_SIZE_A : natural := 12; + constant WRITER_ENDPOINT_FRAME_SIZE_B : natural := 8; + constant READER_ENDPOINT_FRAME_SIZE_A : natural := 15; + constant READER_ENDPOINT_FRAME_SIZE_B : natural := 6; constant DEFAULT_GUIDPREFIX : GUIDPREFIX_TYPE; -- Deferred to Package Body constant DEFAULT_READER_ENTITYID : std_logic_vector(ENTITYID_WIDTH-1 downto 0); -- Deferred to Package Body @@ -48,6 +48,7 @@ package rtps_test_package is subtype TEST_READER_ENDPOINT_MEMORY_FRAME_TYPE_A is TEST_MEMORY_TYPE(0 to READER_ENDPOINT_FRAME_SIZE_A-1); subtype TEST_READER_ENDPOINT_MEMORY_FRAME_TYPE_B is TEST_MEMORY_TYPE(0 to READER_ENDPOINT_FRAME_SIZE_B-1); + constant LOCATOR_PORT_WIDTH : natural := CDR_LONG_WIDTH; constant LOCATOR_ADDR_WIDTH : natural := 4*CDR_LONG_WIDTH; @@ -2251,7 +2252,7 @@ package body rtps_test_package is output.data(output.length)(READER_EXPECTS_HISTORICAL_DATA_FLAG) := '0' when (ref.durability = VOLATILE_DURABILITY_QOS) else '1'; output.data(output.length)(READER_IS_BEST_EFFORT_FLAG) := '1' when (ref.reliability = BEST_EFFORT_RELIABILITY_QOS) else '0'; end if; - output.length := output.length + 1; + output.length := output.length + 1; end if; -- Mark Last Word