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Change HC Operation Handshake Behaviour

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This commit is contained in:
Greek 2021-03-02 13:57:22 +01:00
parent b5206f66f1
commit a9eb56d6e5
10 changed files with 200 additions and 154 deletions
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27
src/Tests/Level_0/L0_rtps_reader_test1_vbk.vhd
View File

@ -30,6 +30,7 @@ architecture testbench of L0_rtps_reader_test1_vbk is
-- *TYPE DECLARATION* -- *TYPE DECLARATION*
type TEST_STAGE_TYPE is (IDLE, BUSY); type TEST_STAGE_TYPE is (IDLE, BUSY);
type CHECK_STAGE_TYPE is (IDLE, RESPONSE);
type TEST_RAM_TYPE is array (0 to (MAX_REMOTE_ENDPOINTS*WRITER_ENDPOINT_FRAME_SIZE_B)-1) of std_logic_vector(WORD_WIDTH-1 downto 0); type TEST_RAM_TYPE is array (0 to (MAX_REMOTE_ENDPOINTS*WRITER_ENDPOINT_FRAME_SIZE_B)-1) of std_logic_vector(WORD_WIDTH-1 downto 0);
-- *SIGNAL DECLARATION* -- *SIGNAL DECLARATION*
@ -40,6 +41,7 @@ architecture testbench of L0_rtps_reader_test1_vbk is
signal opcode_hc : HISTORY_CACHE_OPCODE_TYPE := NOP; signal opcode_hc : HISTORY_CACHE_OPCODE_TYPE := NOP;
signal ret_hc : HISTORY_CACHE_RESPONSE_TYPE := OK; signal ret_hc : HISTORY_CACHE_RESPONSE_TYPE := OK;
signal stim_stage : TEST_STAGE_TYPE := IDLE; signal stim_stage : TEST_STAGE_TYPE := IDLE;
signal check_stage : CHECK_STAGE_TYPE := IDLE;
shared variable stimulus, reference : TEST_PACKET_TYPE := EMPTY_TEST_PACKET; shared variable stimulus, reference : TEST_PACKET_TYPE := EMPTY_TEST_PACKET;
signal packet_sent : std_logic := '0'; signal packet_sent : std_logic := '0';
signal cnt_stim : natural := 0; signal cnt_stim : natural := 0;
@ -424,21 +426,34 @@ begin
out_check_prc : process(all) out_check_prc : process(all)
begin begin
if rising_edge(clk) then if rising_edge(clk) then
done_hc <= done_hc_delay; case (check_stage) is
when IDLE =>
if (start_hc = '1') then if (start_hc = '1') then
ack_hc <= '1';
done_hc_delay <= '1';
case (opcode_hc) is case (opcode_hc) is
when REMOVE_WRITER => when REMOVE_WRITER =>
SB_out.check(data_out_hc); SB_out.check(data_out_hc);
when others => when others =>
Alert("Unexpected HC Opcode", ERROR); Alert("Unexpected HC Opcode", ERROR);
end case; end case;
else check_stage <= RESPONSE;
end if;
when RESPONSE =>
check_stage <= IDLE;
end case;
end if;
-- DEFAULT
ack_hc <= '0'; ack_hc <= '0';
done_hc_delay <= '0'; done_hc <= '0';
end if; ret_hc <= ERROR;
case (check_stage) is
when IDLE =>
if (start_hc = '1') then
ack_hc <= '1';
end if; end if;
when RESPONSE =>
done_hc <= '1';
ret_hc <= OK;
end case;
end process; end process;
mem_check_prc : process mem_check_prc : process

31
src/Tests/Level_0/L0_rtps_reader_test1_vrk.vhd
View File

@ -29,7 +29,8 @@ architecture testbench of L0_rtps_reader_test1_vrk is
constant MAX_REMOTE_ENDPOINTS : natural := 3; constant MAX_REMOTE_ENDPOINTS : natural := 3;
-- *TYPE DECLARATION* -- *TYPE DECLARATION*
type TEST_STAGE_TYPE is (IDLE, BUSY); type SEND_STAGE_TYPE is (IDLE, BUSY);
type CHECK_STAGE_TYPE is (IDLE, RESPONSE);
type TEST_RAM_TYPE is array (0 to (MAX_REMOTE_ENDPOINTS*WRITER_ENDPOINT_FRAME_SIZE_A)-1) of std_logic_vector(WORD_WIDTH-1 downto 0); type TEST_RAM_TYPE is array (0 to (MAX_REMOTE_ENDPOINTS*WRITER_ENDPOINT_FRAME_SIZE_A)-1) of std_logic_vector(WORD_WIDTH-1 downto 0);
-- *SIGNAL DECLARATION* -- *SIGNAL DECLARATION*
@ -39,7 +40,8 @@ architecture testbench of L0_rtps_reader_test1_vrk is
signal start_hc, ack_hc, done_hc, done_hc_delay : std_logic := '0'; signal start_hc, ack_hc, done_hc, done_hc_delay : std_logic := '0';
signal opcode_hc : HISTORY_CACHE_OPCODE_TYPE := NOP; signal opcode_hc : HISTORY_CACHE_OPCODE_TYPE := NOP;
signal ret_hc : HISTORY_CACHE_RESPONSE_TYPE := OK; signal ret_hc : HISTORY_CACHE_RESPONSE_TYPE := OK;
signal stim_stage : TEST_STAGE_TYPE := IDLE; signal stim_stage : SEND_STAGE_TYPE := IDLE;
signal check_stage : CHECK_STAGE_TYPE := IDLE;
shared variable stimulus, reference : TEST_PACKET_TYPE := EMPTY_TEST_PACKET; shared variable stimulus, reference : TEST_PACKET_TYPE := EMPTY_TEST_PACKET;
signal packet_sent : std_logic := '0'; signal packet_sent : std_logic := '0';
signal cnt_stim : natural := 0; signal cnt_stim : natural := 0;
@ -424,21 +426,34 @@ begin
out_check_prc : process(all) out_check_prc : process(all)
begin begin
if rising_edge(clk) then if rising_edge(clk) then
done_hc <= done_hc_delay; case (check_stage) is
when IDLE =>
if (start_hc = '1') then if (start_hc = '1') then
ack_hc <= '1';
done_hc_delay <= '1';
case (opcode_hc) is case (opcode_hc) is
when REMOVE_WRITER => when REMOVE_WRITER =>
SB_out.check(data_out_hc); SB_out.check(data_out_hc);
when others => when others =>
Alert("Unexpected HC Opcode", ERROR); Alert("Unexpected HC Opcode", ERROR);
end case; end case;
else check_stage <= RESPONSE;
end if;
when RESPONSE =>
check_stage <= IDLE;
end case;
end if;
-- DEFAULT
ack_hc <= '0'; ack_hc <= '0';
done_hc_delay <= '0'; done_hc <= '0';
end if; ret_hc <= ERROR;
case (check_stage) is
when IDLE =>
if (start_hc = '1') then
ack_hc <= '1';
end if; end if;
when RESPONSE =>
done_hc <= '1';
ret_hc <= OK;
end case;
end process; end process;
mem_check_prc : process mem_check_prc : process

27
src/Tests/Level_0/L0_rtps_reader_test2_tbk.vhd
View File

@ -1296,13 +1296,8 @@ begin
if rising_edge(clk) then if rising_edge(clk) then
case (check_stage) is case (check_stage) is
when IDLE => when IDLE =>
ack_hc <= '0';
done_hc <= '0';
ready_out_hc <= '0';
ret_hc <= ERROR;
out_check_done <= '0'; out_check_done <= '0';
if (start_hc = '1') then if (start_hc = '1') then
ack_hc <= '1';
check_stage <= CHECK; check_stage <= CHECK;
case (opcode_hc) is case (opcode_hc) is
when ADD_CACHE_CHANGE => when ADD_CACHE_CHANGE =>
@ -1313,30 +1308,38 @@ begin
end case; end case;
end if; end if;
when CHECK => when CHECK =>
ack_hc <= '0';
ready_out_hc <= '1';
out_check_done <= '0';
if (valid_out_hc = '1') then if (valid_out_hc = '1') then
SB_out.Check(last_word_out_hc & data_out_hc); SB_out.Check(last_word_out_hc & data_out_hc);
if (last_word_out_hc = '1') then if (last_word_out_hc = '1') then
ready_out_hc <= '0';
check_stage <= RESPONSE; check_stage <= RESPONSE;
end if; end if;
end if; end if;
when RESPONSE => when RESPONSE =>
check_stage <= IDLE;
out_check_done <= '1';
end case;
end if;
-- DEFAULT
ack_hc <= '0'; ack_hc <= '0';
done_hc <= '0';
ret_hc <= ERROR;
ready_out_hc <= '0'; ready_out_hc <= '0';
case (check_stage) is
when IDLE =>
if (start_hc = '1') then
ack_hc <= '1';
end if;
when CHECK =>
ready_out_hc <= '1';
when RESPONSE =>
done_hc <= '1'; done_hc <= '1';
if (accept = ACCEPT_RES) then if (accept = ACCEPT_RES) then
ret_hc <= OK; ret_hc <= OK;
else else
ret_hc <= REJECTED; ret_hc <= REJECTED;
end if; end if;
check_stage <= IDLE;
out_check_done <= '1';
end case; end case;
end if;
end process; end process;
watchdog : process watchdog : process

27
src/Tests/Level_0/L0_rtps_reader_test2_trk.vhd
View File

@ -1305,13 +1305,8 @@ begin
if rising_edge(clk) then if rising_edge(clk) then
case (check_stage) is case (check_stage) is
when IDLE => when IDLE =>
ack_hc <= '0';
done_hc <= '0';
ready_out_hc <= '0';
ret_hc <= ERROR;
out_check_done <= '0'; out_check_done <= '0';
if (start_hc = '1') then if (start_hc = '1') then
ack_hc <= '1';
check_stage <= CHECK; check_stage <= CHECK;
case (opcode_hc) is case (opcode_hc) is
when ADD_CACHE_CHANGE => when ADD_CACHE_CHANGE =>
@ -1322,30 +1317,38 @@ begin
end case; end case;
end if; end if;
when CHECK => when CHECK =>
ack_hc <= '0';
ready_out_hc <= '1';
out_check_done <= '0';
if (valid_out_hc = '1') then if (valid_out_hc = '1') then
SB_out.Check(last_word_out_hc & data_out_hc); SB_out.Check(last_word_out_hc & data_out_hc);
if (last_word_out_hc = '1') then if (last_word_out_hc = '1') then
ready_out_hc <= '0';
check_stage <= RESPONSE; check_stage <= RESPONSE;
end if; end if;
end if; end if;
when RESPONSE => when RESPONSE =>
check_stage <= IDLE;
out_check_done <= '1';
end case;
end if;
-- DEFAULT
ack_hc <= '0'; ack_hc <= '0';
done_hc <= '0';
ret_hc <= ERROR;
ready_out_hc <= '0'; ready_out_hc <= '0';
case (check_stage) is
when IDLE =>
if (start_hc = '1') then
ack_hc <= '1';
end if;
when CHECK =>
ready_out_hc <= '1';
when RESPONSE =>
done_hc <= '1'; done_hc <= '1';
if (accept = ACCEPT_RES) then if (accept = ACCEPT_RES) then
ret_hc <= OK; ret_hc <= OK;
else else
ret_hc <= REJECTED; ret_hc <= REJECTED;
end if; end if;
check_stage <= IDLE;
out_check_done <= '1';
end case; end case;
end if;
end process; end process;
watchdog : process watchdog : process

27
src/Tests/Level_0/L0_rtps_reader_test2_vbk.vhd
View File

@ -1277,13 +1277,8 @@ begin
if rising_edge(clk) then if rising_edge(clk) then
case (check_stage) is case (check_stage) is
when IDLE => when IDLE =>
ack_hc <= '0';
done_hc <= '0';
ready_out_hc <= '0';
ret_hc <= ERROR;
out_check_done <= '0'; out_check_done <= '0';
if (start_hc = '1') then if (start_hc = '1') then
ack_hc <= '1';
check_stage <= CHECK; check_stage <= CHECK;
case (opcode_hc) is case (opcode_hc) is
when ADD_CACHE_CHANGE => when ADD_CACHE_CHANGE =>
@ -1294,30 +1289,38 @@ begin
end case; end case;
end if; end if;
when CHECK => when CHECK =>
ack_hc <= '0';
ready_out_hc <= '1';
out_check_done <= '0';
if (valid_out_hc = '1') then if (valid_out_hc = '1') then
SB_out.Check(last_word_out_hc & data_out_hc); SB_out.Check(last_word_out_hc & data_out_hc);
if (last_word_out_hc = '1') then if (last_word_out_hc = '1') then
ready_out_hc <= '0';
check_stage <= RESPONSE; check_stage <= RESPONSE;
end if; end if;
end if; end if;
when RESPONSE => when RESPONSE =>
check_stage <= IDLE;
out_check_done <= '1';
end case;
end if;
-- DEFAULT
ack_hc <= '0'; ack_hc <= '0';
done_hc <= '0';
ret_hc <= ERROR;
ready_out_hc <= '0'; ready_out_hc <= '0';
case (check_stage) is
when IDLE =>
if (start_hc = '1') then
ack_hc <= '1';
end if;
when CHECK =>
ready_out_hc <= '1';
when RESPONSE =>
done_hc <= '1'; done_hc <= '1';
if (accept = ACCEPT_RES) then if (accept = ACCEPT_RES) then
ret_hc <= OK; ret_hc <= OK;
else else
ret_hc <= REJECTED; ret_hc <= REJECTED;
end if; end if;
check_stage <= IDLE;
out_check_done <= '1';
end case; end case;
end if;
end process; end process;
watchdog : process watchdog : process

27
src/Tests/Level_0/L0_rtps_reader_test2_vrk.vhd
View File

@ -1291,13 +1291,8 @@ begin
if rising_edge(clk) then if rising_edge(clk) then
case (check_stage) is case (check_stage) is
when IDLE => when IDLE =>
ack_hc <= '0';
done_hc <= '0';
ready_out_hc <= '0';
ret_hc <= ERROR;
out_check_done <= '0'; out_check_done <= '0';
if (start_hc = '1') then if (start_hc = '1') then
ack_hc <= '1';
check_stage <= CHECK; check_stage <= CHECK;
case (opcode_hc) is case (opcode_hc) is
when ADD_CACHE_CHANGE => when ADD_CACHE_CHANGE =>
@ -1308,30 +1303,38 @@ begin
end case; end case;
end if; end if;
when CHECK => when CHECK =>
ack_hc <= '0';
ready_out_hc <= '1';
out_check_done <= '0';
if (valid_out_hc = '1') then if (valid_out_hc = '1') then
SB_out.Check(last_word_out_hc & data_out_hc); SB_out.Check(last_word_out_hc & data_out_hc);
if (last_word_out_hc = '1') then if (last_word_out_hc = '1') then
ready_out_hc <= '0';
check_stage <= RESPONSE; check_stage <= RESPONSE;
end if; end if;
end if; end if;
when RESPONSE => when RESPONSE =>
check_stage <= IDLE;
out_check_done <= '1';
end case;
end if;
-- DEFAULT
ack_hc <= '0'; ack_hc <= '0';
done_hc <= '0';
ret_hc <= ERROR;
ready_out_hc <= '0'; ready_out_hc <= '0';
case (check_stage) is
when IDLE =>
if (start_hc = '1') then
ack_hc <= '1';
end if;
when CHECK =>
ready_out_hc <= '1';
when RESPONSE =>
done_hc <= '1'; done_hc <= '1';
if (accept = ACCEPT_RES) then if (accept = ACCEPT_RES) then
ret_hc <= OK; ret_hc <= OK;
else else
ret_hc <= REJECTED; ret_hc <= REJECTED;
end if; end if;
check_stage <= IDLE;
out_check_done <= '1';
end case; end case;
end if;
end process; end process;
watchdog : process watchdog : process

27
src/Tests/Level_0/L0_rtps_reader_test2_vrn.vhd
View File

@ -1301,13 +1301,8 @@ begin
if rising_edge(clk) then if rising_edge(clk) then
case (check_stage) is case (check_stage) is
when IDLE => when IDLE =>
ack_hc <= '0';
done_hc <= '0';
ready_out_hc <= '0';
ret_hc <= ERROR;
out_check_done <= '0'; out_check_done <= '0';
if (start_hc = '1') then if (start_hc = '1') then
ack_hc <= '1';
check_stage <= CHECK; check_stage <= CHECK;
case (opcode_hc) is case (opcode_hc) is
when ADD_CACHE_CHANGE => when ADD_CACHE_CHANGE =>
@ -1318,30 +1313,38 @@ begin
end case; end case;
end if; end if;
when CHECK => when CHECK =>
ack_hc <= '0';
ready_out_hc <= '1';
out_check_done <= '0';
if (valid_out_hc = '1') then if (valid_out_hc = '1') then
SB_out.Check(last_word_out_hc & data_out_hc); SB_out.Check(last_word_out_hc & data_out_hc);
if (last_word_out_hc = '1') then if (last_word_out_hc = '1') then
ready_out_hc <= '0';
check_stage <= RESPONSE; check_stage <= RESPONSE;
end if; end if;
end if; end if;
when RESPONSE => when RESPONSE =>
check_stage <= IDLE;
out_check_done <= '1';
end case;
end if;
-- DEFAULT
ack_hc <= '0'; ack_hc <= '0';
done_hc <= '0';
ret_hc <= ERROR;
ready_out_hc <= '0'; ready_out_hc <= '0';
case (check_stage) is
when IDLE =>
if (start_hc = '1') then
ack_hc <= '1';
end if;
when CHECK =>
ready_out_hc <= '1';
when RESPONSE =>
done_hc <= '1'; done_hc <= '1';
if (accept = ACCEPT_RES) then if (accept = ACCEPT_RES) then
ret_hc <= OK; ret_hc <= OK;
else else
ret_hc <= REJECTED; ret_hc <= REJECTED;
end if; end if;
check_stage <= IDLE;
out_check_done <= '1';
end case; end case;
end if;
end process; end process;
watchdog : process watchdog : process

27
src/Tests/Level_0/L0_rtps_reader_test3_a.vhd
View File

@ -550,13 +550,8 @@ begin
if rising_edge(clk) then if rising_edge(clk) then
case (check_stage) is case (check_stage) is
when IDLE => when IDLE =>
ack_hc <= '0';
done_hc <= '0';
ready_out_hc <= '0';
ret_hc <= ERROR;
out_check_done <= '0'; out_check_done <= '0';
if (start_hc = '1') then if (start_hc = '1') then
ack_hc <= '1';
check_stage <= CHECK; check_stage <= CHECK;
case (opcode_hc) is case (opcode_hc) is
when REMOVE_WRITER => when REMOVE_WRITER =>
@ -571,30 +566,38 @@ begin
end case; end case;
end if; end if;
when CHECK => when CHECK =>
ack_hc <= '0';
ready_out_hc <= '1';
out_check_done <= '0';
if (valid_out_hc = '1') then if (valid_out_hc = '1') then
SB_out.Check(last_word_out_hc & data_out_hc); SB_out.Check(last_word_out_hc & data_out_hc);
if (last_word_out_hc = '1') then if (last_word_out_hc = '1') then
ready_out_hc <= '0';
check_stage <= RESPONSE; check_stage <= RESPONSE;
end if; end if;
end if; end if;
when RESPONSE => when RESPONSE =>
check_stage <= IDLE;
out_check_done <= '1';
end case;
end if;
-- DEFAULT
ack_hc <= '0'; ack_hc <= '0';
done_hc <= '0';
ret_hc <= ERROR;
ready_out_hc <= '0'; ready_out_hc <= '0';
case (check_stage) is
when IDLE =>
if (start_hc = '1') then
ack_hc <= '1';
end if;
when CHECK =>
ready_out_hc <= '1';
when RESPONSE =>
done_hc <= '1'; done_hc <= '1';
if (accept = ACCEPT_RES) then if (accept = ACCEPT_RES) then
ret_hc <= OK; ret_hc <= OK;
else else
ret_hc <= REJECTED; ret_hc <= REJECTED;
end if; end if;
check_stage <= IDLE;
out_check_done <= '1';
end case; end case;
end if;
end process; end process;
mem_check_prc : process mem_check_prc : process

27
src/Tests/Level_0/L0_rtps_reader_test3_m.vhd
View File

@ -571,13 +571,8 @@ begin
if rising_edge(clk) then if rising_edge(clk) then
case (check_stage) is case (check_stage) is
when IDLE => when IDLE =>
ack_hc <= '0';
done_hc <= '0';
ready_out_hc <= '0';
ret_hc <= ERROR;
out_check_done <= '0'; out_check_done <= '0';
if (start_hc = '1') then if (start_hc = '1') then
ack_hc <= '1';
check_stage <= CHECK; check_stage <= CHECK;
case (opcode_hc) is case (opcode_hc) is
when REMOVE_WRITER => when REMOVE_WRITER =>
@ -592,30 +587,38 @@ begin
end case; end case;
end if; end if;
when CHECK => when CHECK =>
ack_hc <= '0';
ready_out_hc <= '1';
out_check_done <= '0';
if (valid_out_hc = '1') then if (valid_out_hc = '1') then
SB_out.Check(last_word_out_hc & data_out_hc); SB_out.Check(last_word_out_hc & data_out_hc);
if (last_word_out_hc = '1') then if (last_word_out_hc = '1') then
ready_out_hc <= '0';
check_stage <= RESPONSE; check_stage <= RESPONSE;
end if; end if;
end if; end if;
when RESPONSE => when RESPONSE =>
check_stage <= IDLE;
out_check_done <= '1';
end case;
end if;
-- DEFAULT
ack_hc <= '0'; ack_hc <= '0';
done_hc <= '0';
ret_hc <= ERROR;
ready_out_hc <= '0'; ready_out_hc <= '0';
case (check_stage) is
when IDLE =>
if (start_hc = '1') then
ack_hc <= '1';
end if;
when CHECK =>
ready_out_hc <= '1';
when RESPONSE =>
done_hc <= '1'; done_hc <= '1';
if (accept = ACCEPT_RES) then if (accept = ACCEPT_RES) then
ret_hc <= OK; ret_hc <= OK;
else else
ret_hc <= REJECTED; ret_hc <= REJECTED;
end if; end if;
check_stage <= IDLE;
out_check_done <= '1';
end case; end case;
end if;
end process; end process;
mem_check_prc : process mem_check_prc : process

5
src/rtps_reader.vhd
View File

@ -706,7 +706,6 @@ begin
data_out_hc <= std_logic_vector(to_unsigned(mem_pos, WORD_WIDTH)); data_out_hc <= std_logic_vector(to_unsigned(mem_pos, WORD_WIDTH));
-- Wait for Operation Acknowledgement -- Wait for Operation Acknowledgement
if (ack_hc = '1') then if (ack_hc = '1') then
start_hc <= '0';
-- Remove Unmatched Remote Endpoint -- Remove Unmatched Remote Endpoint
mem_op_start <= '1'; mem_op_start <= '1';
mem_opcode <= REMOVE_ENDPOINT; mem_opcode <= REMOVE_ENDPOINT;
@ -730,7 +729,6 @@ begin
data_out_hc <= std_logic_vector(to_unsigned(mem_pos, WORD_WIDTH)); data_out_hc <= std_logic_vector(to_unsigned(mem_pos, WORD_WIDTH));
-- Wait for Operation Acknowledgement -- Wait for Operation Acknowledgement
if (ack_hc = '1') then if (ack_hc = '1') then
start_hc <= '0';
-- Remove Unmatched Remote Endpoint -- Remove Unmatched Remote Endpoint
mem_op_start <= '1'; mem_op_start <= '1';
mem_opcode <= REMOVE_ENDPOINT; mem_opcode <= REMOVE_ENDPOINT;
@ -1225,7 +1223,6 @@ begin
opcode_hc <= ADD_CACHE_CHANGE; opcode_hc <= ADD_CACHE_CHANGE;
-- Wait until History Cache acknowledges request -- Wait until History Cache acknowledges request
if (ack_hc = '1') then if (ack_hc = '1') then
start_hc <= '0';
stage_next <= ADD_CACHE_CHANGE; stage_next <= ADD_CACHE_CHANGE;
cnt_next <= 0; cnt_next <= 0;
end if; end if;
@ -1423,7 +1420,6 @@ begin
data_out_hc <= std_logic_vector(to_unsigned(mem_pos, WORD_WIDTH)); data_out_hc <= std_logic_vector(to_unsigned(mem_pos, WORD_WIDTH));
-- Wait for Operation Acknowledgement -- Wait for Operation Acknowledgement
if (ack_hc = '1') then if (ack_hc = '1') then
start_hc <= '0';
-- Remove Endpoint -- Remove Endpoint
mem_op_start <= '1'; mem_op_start <= '1';
mem_opcode <= REMOVE_ENDPOINT; mem_opcode <= REMOVE_ENDPOINT;
@ -2873,7 +2869,6 @@ begin
bitmap_pos <= 0; bitmap_pos <= 0;
mem_cnt <= 0; mem_cnt <= 0;
mem_pos <= 0; mem_pos <= 0;
is_meta <= '0'; is_meta <= '0';
key_hash_rcvd <= '0'; key_hash_rcvd <= '0';
last_word_in_latch <= '0'; last_word_in_latch <= '0';