From ad03ae6ecdfdb489dea094c0f5373763783d126c Mon Sep 17 00:00:00 2001 From: Greek64 Date: Sat, 19 Mar 2022 15:37:20 +0100 Subject: [PATCH] Remove RTPS_OUT_DATA_TYPE and modify rtps_out with generic --- src/TEMPLATE_dds_top.vhd | 2 +- src/Tests/Level_0/L0_rtps_out_test1.vhd | 2 +- .../L1_rtps_discovery_module_test1.vhd | 2 +- .../Level_1/L1_rtps_reader_test1_trk.vhd | 2 +- .../Level_1/L1_rtps_reader_test1_vrk.vhd | 2 +- .../Level_1/L1_rtps_writer_test1_tbkdp.vhd | 2 +- .../Level_1/L1_rtps_writer_test1_trkdn.vhd | 2 +- .../Level_1/L1_rtps_writer_test1_trkdp.vhd | 2 +- .../Level_1/L1_rtps_writer_test1_vbkdp.vhd | 2 +- .../Level_1/L1_rtps_writer_test1_vrkdn.vhd | 2 +- .../Level_1/L1_rtps_writer_test1_vrkdp.vhd | 2 +- .../Level_1/L1_rtps_writer_test1_vrksp.vhd | 2 +- .../Level_1/L1_rtps_writer_test1_vrndp.vhd | 2 +- .../Level_1/L1_rtps_writer_test2_vrkdn.vhd | 2 +- .../Level_1/L1_rtps_writer_test2_vrksn.vhd | 2 +- .../Level_1/L1_rtps_writer_test3_vrkdn.vhd | 2 +- src/Tests/Level_2/L2_Testbench_Lib2.vhd | 2 +- src/Tests/Level_2/L2_Testbench_Lib3.vhd | 2 +- src/Tests/Level_2/L2_testbench_Lib4.vhd | 2 +- src/Tests/Level_2/L2_testbench_Lib5.vhd | 2 +- .../Tests/Level_2/L2_Testbench_ROS_Lib2.vhd | 2 +- .../Tests/Level_2/L2_Testbench_ROS_Lib3.vhd | 2 +- .../Tests/Level_2/L2_Testbench_ROS_Lib4.vhd | 2 +- .../Tests/Level_2/L2_Testbench_ROS_Lib5.vhd | 2 +- src/rtps_config_package.vhd | 2 -- src/rtps_out.vhd | 23 ++++++++++--------- 26 files changed, 36 insertions(+), 37 deletions(-) diff --git a/src/TEMPLATE_dds_top.vhd b/src/TEMPLATE_dds_top.vhd index e9e99fb..b490f5c 100644 --- a/src/TEMPLATE_dds_top.vhd +++ b/src/TEMPLATE_dds_top.vhd @@ -106,7 +106,7 @@ architecture arch of dds_top is signal data_dw_wi, data_wi_dw : WARRAY_DATA_TYPE; signal status_dw_wi : STATUS_KIND_WARRAY_TYPE; signal empty_firo_ro, read_ro_firo, last_word_firo_ro : std_logic_vector(0 to NUM_ENDPOINTS); - signal data_firo_ro : RTPS_OUT_DATA_TYPE; + signal data_firo_ro : WORD_ARRAY_TYPE(0 to NUM_ENDPOINTS); -- ###GENERATED START### -- INTERFACE-USER SIGNALS -- ###GENERATED END### diff --git a/src/Tests/Level_0/L0_rtps_out_test1.vhd b/src/Tests/Level_0/L0_rtps_out_test1.vhd index 7320567..70a4190 100644 --- a/src/Tests/Level_0/L0_rtps_out_test1.vhd +++ b/src/Tests/Level_0/L0_rtps_out_test1.vhd @@ -40,7 +40,7 @@ architecture testbench of L0_rtps_out_test1 is signal clk, wr_sig, full : std_logic := '0'; signal reset : std_logic := '1'; signal data_out : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); - signal data_in : RTPS_OUT_DATA_TYPE := (others => (others => '0')); + signal data_in : WORD_ARRAY_TYPE(0 to NUM_ENDPOINTS) := (others => (others => '0')); signal last_word_in, rd_sig, empty : std_logic_vector(0 to NUM_ENDPOINTS) := (others => '0'); signal stim_stage : TEST_STAGE_ARRAY_TYPE := (others => IDLE); diff --git a/src/Tests/Level_1/L1_rtps_discovery_module_test1.vhd b/src/Tests/Level_1/L1_rtps_discovery_module_test1.vhd index 4f01298..f09ae63 100644 --- a/src/Tests/Level_1/L1_rtps_discovery_module_test1.vhd +++ b/src/Tests/Level_1/L1_rtps_discovery_module_test1.vhd @@ -96,7 +96,7 @@ architecture testbench of L1_rtps_discovery_module_test1 is signal test_time : TIME_TYPE := TIME_ZERO; signal fifo_in, fifo_out : std_logic_vector(WORD_WIDTH downto 0) := (others => '0'); signal fifo_wr, fifo_empty, fifo_full : std_logic := '0'; - signal rtps_out_data : RTPS_OUT_DATA_TYPE := (others => (others => '0')); + signal rtps_out_data : WORD_ARRAY_TYPE(0 to NUM_ENDPOINTS) := (others => (others => '0')); signal rtps_out_rd, rtps_out_last_word_in, rtps_out_empty : std_logic_vector(0 to NUM_ENDPOINTS) := (others => '0'); signal alive : std_logic_vector (0 to NUM_ENDPOINTS-1) := (others => '0'); diff --git a/src/Tests/Level_1/L1_rtps_reader_test1_trk.vhd b/src/Tests/Level_1/L1_rtps_reader_test1_trk.vhd index 86ac50b..aa65077 100644 --- a/src/Tests/Level_1/L1_rtps_reader_test1_trk.vhd +++ b/src/Tests/Level_1/L1_rtps_reader_test1_trk.vhd @@ -65,7 +65,7 @@ architecture testbench of L1_rtps_reader_test1_trk is signal test_time : TIME_TYPE := TIME_ZERO; signal fifo_in, fifo_out : std_logic_vector(WORD_WIDTH downto 0) := (others => '0'); signal fifo_wr, fifo_empty, fifo_full : std_logic := '0'; - signal rtps_out_data : RTPS_OUT_DATA_TYPE := (others => (others => '0')); + signal rtps_out_data : WORD_ARRAY_TYPE(0 to NUM_ENDPOINTS) := (others => (others => '0')); signal rtps_out_rd, rtps_out_last_word_in, rtps_out_empty : std_logic_vector(0 to NUM_ENDPOINTS) := (others => '0'); -- *FUNCTION DECLARATION* diff --git a/src/Tests/Level_1/L1_rtps_reader_test1_vrk.vhd b/src/Tests/Level_1/L1_rtps_reader_test1_vrk.vhd index edd7fb9..fec1a9e 100644 --- a/src/Tests/Level_1/L1_rtps_reader_test1_vrk.vhd +++ b/src/Tests/Level_1/L1_rtps_reader_test1_vrk.vhd @@ -66,7 +66,7 @@ architecture testbench of L1_rtps_reader_test1_vrk is signal test_time : TIME_TYPE := TIME_ZERO; signal fifo_in, fifo_out : std_logic_vector(WORD_WIDTH downto 0) := (others => '0'); signal fifo_wr, fifo_empty, fifo_full : std_logic := '0'; - signal rtps_out_data : RTPS_OUT_DATA_TYPE := (others => (others => '0')); + signal rtps_out_data : WORD_ARRAY_TYPE(0 to NUM_ENDPOINTS) := (others => (others => '0')); signal rtps_out_rd, rtps_out_last_word_in, rtps_out_empty : std_logic_vector(0 to NUM_ENDPOINTS) := (others => '0'); -- *FUNCTION DECLARATION* diff --git a/src/Tests/Level_1/L1_rtps_writer_test1_tbkdp.vhd b/src/Tests/Level_1/L1_rtps_writer_test1_tbkdp.vhd index 5509da3..66d1a77 100644 --- a/src/Tests/Level_1/L1_rtps_writer_test1_tbkdp.vhd +++ b/src/Tests/Level_1/L1_rtps_writer_test1_tbkdp.vhd @@ -53,7 +53,7 @@ architecture testbench of L1_rtps_writer_test1_tbkdp is signal test_time : TIME_TYPE := TIME_ZERO; signal fifo_in, fifo_out : std_logic_vector(WORD_WIDTH downto 0) := (others => '0'); signal fifo_wr, fifo_empty, fifo_full : std_logic := '0'; - signal rtps_out_data : RTPS_OUT_DATA_TYPE := (others => (others => '0')); + signal rtps_out_data : WORD_ARRAY_TYPE(0 to NUM_ENDPOINTS) := (others => (others => '0')); signal rtps_out_rd, rtps_out_last_word_in, rtps_out_empty : std_logic_vector(0 to NUM_ENDPOINTS) := (others => '0'); signal test_cc : TEST_CC_ARRAY_TYPE := (others => DEFAULT_CACHE_CHANGE); -- Signal containing the current fill level of the test_cc array diff --git a/src/Tests/Level_1/L1_rtps_writer_test1_trkdn.vhd b/src/Tests/Level_1/L1_rtps_writer_test1_trkdn.vhd index ef545fc..aa782f0 100644 --- a/src/Tests/Level_1/L1_rtps_writer_test1_trkdn.vhd +++ b/src/Tests/Level_1/L1_rtps_writer_test1_trkdn.vhd @@ -54,7 +54,7 @@ architecture testbench of L1_rtps_writer_test1_trkdn is signal test_time : TIME_TYPE := TIME_ZERO; signal fifo_in, fifo_out : std_logic_vector(WORD_WIDTH downto 0) := (others => '0'); signal fifo_wr, fifo_empty, fifo_full : std_logic := '0'; - signal rtps_out_data : RTPS_OUT_DATA_TYPE := (others => (others => '0')); + signal rtps_out_data : WORD_ARRAY_TYPE(0 to NUM_ENDPOINTS) := (others => (others => '0')); signal rtps_out_rd, rtps_out_last_word_in, rtps_out_empty : std_logic_vector(0 to NUM_ENDPOINTS) := (others => '0'); signal test_cc : TEST_CC_ARRAY_TYPE := (others => DEFAULT_CACHE_CHANGE); -- Signal containing the current fill level of the test_cc array diff --git a/src/Tests/Level_1/L1_rtps_writer_test1_trkdp.vhd b/src/Tests/Level_1/L1_rtps_writer_test1_trkdp.vhd index 4b3f084..de545dd 100644 --- a/src/Tests/Level_1/L1_rtps_writer_test1_trkdp.vhd +++ b/src/Tests/Level_1/L1_rtps_writer_test1_trkdp.vhd @@ -53,7 +53,7 @@ architecture testbench of L1_rtps_writer_test1_trkdp is signal test_time : TIME_TYPE := TIME_ZERO; signal fifo_in, fifo_out : std_logic_vector(WORD_WIDTH downto 0) := (others => '0'); signal fifo_wr, fifo_empty, fifo_full : std_logic := '0'; - signal rtps_out_data : RTPS_OUT_DATA_TYPE := (others => (others => '0')); + signal rtps_out_data : WORD_ARRAY_TYPE(0 to NUM_ENDPOINTS) := (others => (others => '0')); signal rtps_out_rd, rtps_out_last_word_in, rtps_out_empty : std_logic_vector(0 to NUM_ENDPOINTS) := (others => '0'); signal test_cc : TEST_CC_ARRAY_TYPE := (others => DEFAULT_CACHE_CHANGE); -- Signal containing the current fill level of the test_cc array diff --git a/src/Tests/Level_1/L1_rtps_writer_test1_vbkdp.vhd b/src/Tests/Level_1/L1_rtps_writer_test1_vbkdp.vhd index fbf8303..7bc091f 100644 --- a/src/Tests/Level_1/L1_rtps_writer_test1_vbkdp.vhd +++ b/src/Tests/Level_1/L1_rtps_writer_test1_vbkdp.vhd @@ -53,7 +53,7 @@ architecture testbench of L1_rtps_writer_test1_vbkdp is signal test_time : TIME_TYPE := TIME_ZERO; signal fifo_in, fifo_out : std_logic_vector(WORD_WIDTH downto 0) := (others => '0'); signal fifo_wr, fifo_empty, fifo_full : std_logic := '0'; - signal rtps_out_data : RTPS_OUT_DATA_TYPE := (others => (others => '0')); + signal rtps_out_data : WORD_ARRAY_TYPE(0 to NUM_ENDPOINTS) := (others => (others => '0')); signal rtps_out_rd, rtps_out_last_word_in, rtps_out_empty : std_logic_vector(0 to NUM_ENDPOINTS) := (others => '0'); signal test_cc : TEST_CC_ARRAY_TYPE := (others => DEFAULT_CACHE_CHANGE); -- Signal containing the current fill level of the test_cc array diff --git a/src/Tests/Level_1/L1_rtps_writer_test1_vrkdn.vhd b/src/Tests/Level_1/L1_rtps_writer_test1_vrkdn.vhd index 89ae70f..bb26224 100644 --- a/src/Tests/Level_1/L1_rtps_writer_test1_vrkdn.vhd +++ b/src/Tests/Level_1/L1_rtps_writer_test1_vrkdn.vhd @@ -53,7 +53,7 @@ architecture testbench of L1_rtps_writer_test1_vrkdn is signal test_time : TIME_TYPE := TIME_ZERO; signal fifo_in, fifo_out : std_logic_vector(WORD_WIDTH downto 0) := (others => '0'); signal fifo_wr, fifo_empty, fifo_full : std_logic := '0'; - signal rtps_out_data : RTPS_OUT_DATA_TYPE := (others => (others => '0')); + signal rtps_out_data : WORD_ARRAY_TYPE(0 to NUM_ENDPOINTS) := (others => (others => '0')); signal rtps_out_rd, rtps_out_last_word_in, rtps_out_empty : std_logic_vector(0 to NUM_ENDPOINTS) := (others => '0'); signal test_cc : TEST_CC_ARRAY_TYPE := (others => DEFAULT_CACHE_CHANGE); -- Signal containing the current fill level of the test_cc array diff --git a/src/Tests/Level_1/L1_rtps_writer_test1_vrkdp.vhd b/src/Tests/Level_1/L1_rtps_writer_test1_vrkdp.vhd index 8da433f..9ec6214 100644 --- a/src/Tests/Level_1/L1_rtps_writer_test1_vrkdp.vhd +++ b/src/Tests/Level_1/L1_rtps_writer_test1_vrkdp.vhd @@ -53,7 +53,7 @@ architecture testbench of L1_rtps_writer_test1_vrkdp is signal test_time : TIME_TYPE := TIME_ZERO; signal fifo_in, fifo_out : std_logic_vector(WORD_WIDTH downto 0) := (others => '0'); signal fifo_wr, fifo_empty, fifo_full : std_logic := '0'; - signal rtps_out_data : RTPS_OUT_DATA_TYPE := (others => (others => '0')); + signal rtps_out_data : WORD_ARRAY_TYPE(0 to NUM_ENDPOINTS) := (others => (others => '0')); signal rtps_out_rd, rtps_out_last_word_in, rtps_out_empty : std_logic_vector(0 to NUM_ENDPOINTS) := (others => '0'); signal test_cc : TEST_CC_ARRAY_TYPE := (others => DEFAULT_CACHE_CHANGE); -- Signal containing the current fill level of the test_cc array diff --git a/src/Tests/Level_1/L1_rtps_writer_test1_vrksp.vhd b/src/Tests/Level_1/L1_rtps_writer_test1_vrksp.vhd index c20c954..b08e57f 100644 --- a/src/Tests/Level_1/L1_rtps_writer_test1_vrksp.vhd +++ b/src/Tests/Level_1/L1_rtps_writer_test1_vrksp.vhd @@ -53,7 +53,7 @@ architecture testbench of L1_rtps_writer_test1_vrksp is signal test_time : TIME_TYPE := TIME_ZERO; signal fifo_in, fifo_out : std_logic_vector(WORD_WIDTH downto 0) := (others => '0'); signal fifo_wr, fifo_empty, fifo_full : std_logic := '0'; - signal rtps_out_data : RTPS_OUT_DATA_TYPE := (others => (others => '0')); + signal rtps_out_data : WORD_ARRAY_TYPE(0 to NUM_ENDPOINTS) := (others => (others => '0')); signal rtps_out_rd, rtps_out_last_word_in, rtps_out_empty : std_logic_vector(0 to NUM_ENDPOINTS) := (others => '0'); signal test_cc : TEST_CC_ARRAY_TYPE := (others => DEFAULT_CACHE_CHANGE); -- Signal containing the current fill level of the test_cc array diff --git a/src/Tests/Level_1/L1_rtps_writer_test1_vrndp.vhd b/src/Tests/Level_1/L1_rtps_writer_test1_vrndp.vhd index 0ccb861..e063a2d 100644 --- a/src/Tests/Level_1/L1_rtps_writer_test1_vrndp.vhd +++ b/src/Tests/Level_1/L1_rtps_writer_test1_vrndp.vhd @@ -53,7 +53,7 @@ architecture testbench of L1_rtps_writer_test1_vrndp is signal test_time : TIME_TYPE := TIME_ZERO; signal fifo_in, fifo_out : std_logic_vector(WORD_WIDTH downto 0) := (others => '0'); signal fifo_wr, fifo_empty, fifo_full : std_logic := '0'; - signal rtps_out_data : RTPS_OUT_DATA_TYPE := (others => (others => '0')); + signal rtps_out_data : WORD_ARRAY_TYPE(0 to NUM_ENDPOINTS) := (others => (others => '0')); signal rtps_out_rd, rtps_out_last_word_in, rtps_out_empty : std_logic_vector(0 to NUM_ENDPOINTS) := (others => '0'); signal test_cc : TEST_CC_ARRAY_TYPE := (others => DEFAULT_CACHE_CHANGE); -- Signal containing the current fill level of the test_cc array diff --git a/src/Tests/Level_1/L1_rtps_writer_test2_vrkdn.vhd b/src/Tests/Level_1/L1_rtps_writer_test2_vrkdn.vhd index 5f2d626..1ad520c 100644 --- a/src/Tests/Level_1/L1_rtps_writer_test2_vrkdn.vhd +++ b/src/Tests/Level_1/L1_rtps_writer_test2_vrkdn.vhd @@ -52,7 +52,7 @@ architecture testbench of L1_rtps_writer_test2_vrkdn is signal test_time : TIME_TYPE := TIME_ZERO; signal fifo_in, fifo_out : std_logic_vector(WORD_WIDTH downto 0) := (others => '0'); signal fifo_wr, fifo_empty, fifo_full : std_logic := '0'; - signal rtps_out_data : RTPS_OUT_DATA_TYPE := (others => (others => '0')); + signal rtps_out_data : WORD_ARRAY_TYPE(0 to NUM_ENDPOINTS) := (others => (others => '0')); signal rtps_out_rd, rtps_out_last_word_in, rtps_out_empty : std_logic_vector(0 to NUM_ENDPOINTS) := (others => '0'); signal test_cc : TEST_CC_ARRAY_TYPE := (others => DEFAULT_CACHE_CHANGE); -- Signal containing the current fill level of the test_cc array diff --git a/src/Tests/Level_1/L1_rtps_writer_test2_vrksn.vhd b/src/Tests/Level_1/L1_rtps_writer_test2_vrksn.vhd index ec00690..1464c9f 100644 --- a/src/Tests/Level_1/L1_rtps_writer_test2_vrksn.vhd +++ b/src/Tests/Level_1/L1_rtps_writer_test2_vrksn.vhd @@ -52,7 +52,7 @@ architecture testbench of L1_rtps_writer_test2_vrksn is signal test_time : TIME_TYPE := TIME_ZERO; signal fifo_in, fifo_out : std_logic_vector(WORD_WIDTH downto 0) := (others => '0'); signal fifo_wr, fifo_empty, fifo_full : std_logic := '0'; - signal rtps_out_data : RTPS_OUT_DATA_TYPE := (others => (others => '0')); + signal rtps_out_data : WORD_ARRAY_TYPE(0 to NUM_ENDPOINTS) := (others => (others => '0')); signal rtps_out_rd, rtps_out_last_word_in, rtps_out_empty : std_logic_vector(0 to NUM_ENDPOINTS) := (others => '0'); signal test_cc : TEST_CC_ARRAY_TYPE := (others => DEFAULT_CACHE_CHANGE); -- Signal containing the current fill level of the test_cc array diff --git a/src/Tests/Level_1/L1_rtps_writer_test3_vrkdn.vhd b/src/Tests/Level_1/L1_rtps_writer_test3_vrkdn.vhd index 94b44aa..2fc2de3 100644 --- a/src/Tests/Level_1/L1_rtps_writer_test3_vrkdn.vhd +++ b/src/Tests/Level_1/L1_rtps_writer_test3_vrkdn.vhd @@ -54,7 +54,7 @@ architecture testbench of L1_rtps_writer_test3_vrkdn is signal test_time : TIME_TYPE := TIME_ZERO; signal fifo_in, fifo_out : std_logic_vector(WORD_WIDTH downto 0) := (others => '0'); signal fifo_wr, fifo_empty, fifo_full : std_logic := '0'; - signal rtps_out_data : RTPS_OUT_DATA_TYPE := (others => (others => '0')); + signal rtps_out_data : WORD_ARRAY_TYPE(0 to NUM_ENDPOINTS) := (others => (others => '0')); signal rtps_out_rd, rtps_out_last_word_in, rtps_out_empty : std_logic_vector(0 to NUM_ENDPOINTS) := (others => '0'); signal test_cc : TEST_CC_ARRAY_TYPE := (others => DEFAULT_CACHE_CHANGE); -- Signal containing the current fill level of the test_cc array diff --git a/src/Tests/Level_2/L2_Testbench_Lib2.vhd b/src/Tests/Level_2/L2_Testbench_Lib2.vhd index 0fdb9ae..e12e5ea 100644 --- a/src/Tests/Level_2/L2_Testbench_Lib2.vhd +++ b/src/Tests/Level_2/L2_Testbench_Lib2.vhd @@ -80,7 +80,7 @@ architecture arch of L2_Testbench_Lib2 is signal data_out_rbe : std_logic_vector(WORD_WIDTH-1 downto 0); signal last_word_out_rh_be_s, last_word_out_rh_ue_s : std_logic; signal data_out_rh_be_s, data_out_rh_ue_s : std_logic_vector(WORD_WIDTH-1 downto 0); - signal data_rtps_out_s : RTPS_OUT_DATA_TYPE; + signal data_rtps_out_s : WORD_ARRAY_TYPE(0 to NUM_ENDPOINTS); signal last_word_rtps_out_s : std_logic_vector(0 to NUM_ENDPOINTS); begin diff --git a/src/Tests/Level_2/L2_Testbench_Lib3.vhd b/src/Tests/Level_2/L2_Testbench_Lib3.vhd index 20b4269..c1c874a 100644 --- a/src/Tests/Level_2/L2_Testbench_Lib3.vhd +++ b/src/Tests/Level_2/L2_Testbench_Lib3.vhd @@ -89,7 +89,7 @@ architecture arch of L2_Testbench_Lib3 is signal data_out_rbe : std_logic_vector(WORD_WIDTH-1 downto 0); signal last_word_out_rh_be_s, last_word_out_rh_ue_s : std_logic; signal data_out_rh_be_s, data_out_rh_ue_s : std_logic_vector(WORD_WIDTH-1 downto 0); - signal data_rtps_out_s : RTPS_OUT_DATA_TYPE; + signal data_rtps_out_s : WORD_ARRAY_TYPE(0 to NUM_ENDPOINTS); signal last_word_rtps_out_s : std_logic_vector(0 to NUM_ENDPOINTS); diff --git a/src/Tests/Level_2/L2_testbench_Lib4.vhd b/src/Tests/Level_2/L2_testbench_Lib4.vhd index 3ccc96a..ddc9144 100644 --- a/src/Tests/Level_2/L2_testbench_Lib4.vhd +++ b/src/Tests/Level_2/L2_testbench_Lib4.vhd @@ -101,7 +101,7 @@ architecture arch of L2_Testbench_Lib4 is signal data_dw_wi, data_wi_dw : WARRAY_DATA_TYPE; signal status_dw_wi : STATUS_KIND_WARRAY_TYPE; signal empty_firo_ro, read_ro_firo, last_word_firo_ro : std_logic_vector(0 to NUM_ENDPOINTS); - signal data_firo_ro : RTPS_OUT_DATA_TYPE; + signal data_firo_ro : WORD_ARRAY_TYPE(0 to NUM_ENDPOINTS); signal sample_info_ri_user : SAMPLE_INFO_TYPE; signal start_user_ri, ack_ri_user, get_data_user_ri, done_ri_user, sample_info_valid_ri_user, sample_info_ack_user_ri, eoc_ri_user, decode_error_ri_user, valid_ri_user : std_logic; signal opcode_user_ri : DDS_READER_OPCODE_TYPE; diff --git a/src/Tests/Level_2/L2_testbench_Lib5.vhd b/src/Tests/Level_2/L2_testbench_Lib5.vhd index b815fa8..9020ef7 100644 --- a/src/Tests/Level_2/L2_testbench_Lib5.vhd +++ b/src/Tests/Level_2/L2_testbench_Lib5.vhd @@ -137,7 +137,7 @@ architecture arch of L2_Testbench_Lib5 is signal data_dw_wi, data_wi_dw : WARRAY_DATA_TYPE; signal status_dw_wi : STATUS_KIND_WARRAY_TYPE; signal empty_firo_ro, read_ro_firo, last_word_firo_ro : std_logic_vector(0 to NUM_ENDPOINTS); - signal data_firo_ro : RTPS_OUT_DATA_TYPE; + signal data_firo_ro : WORD_ARRAY_TYPE(0 to NUM_ENDPOINTS); begin diff --git a/src/ros2/Tests/Level_2/L2_Testbench_ROS_Lib2.vhd b/src/ros2/Tests/Level_2/L2_Testbench_ROS_Lib2.vhd index 779e828..0b69139 100644 --- a/src/ros2/Tests/Level_2/L2_Testbench_ROS_Lib2.vhd +++ b/src/ros2/Tests/Level_2/L2_Testbench_ROS_Lib2.vhd @@ -101,7 +101,7 @@ architecture arch of L2_Testbench_ROS_Lib2 is signal data_dw_wi, data_wi_dw : WARRAY_DATA_TYPE; signal status_dw_wi : STATUS_KIND_WARRAY_TYPE; signal empty_firo_ro, read_ro_firo, last_word_firo_ro : std_logic_vector(0 to NUM_ENDPOINTS); - signal data_firo_ro : RTPS_OUT_DATA_TYPE; + signal data_firo_ro : WORD_ARRAY_TYPE(0 to NUM_ENDPOINTS); signal service_if : SERVICE_INTERFACE_ARRAY_TYPE(0 to NUM_SERVICES-1); -- ###GENERATED START### diff --git a/src/ros2/Tests/Level_2/L2_Testbench_ROS_Lib3.vhd b/src/ros2/Tests/Level_2/L2_Testbench_ROS_Lib3.vhd index c2a799e..039f9c4 100644 --- a/src/ros2/Tests/Level_2/L2_Testbench_ROS_Lib3.vhd +++ b/src/ros2/Tests/Level_2/L2_Testbench_ROS_Lib3.vhd @@ -118,7 +118,7 @@ architecture arch of L2_Testbench_ROS_Lib3 is signal data_dw_wi, data_wi_dw : WARRAY_DATA_TYPE; signal status_dw_wi : STATUS_KIND_WARRAY_TYPE; signal empty_firo_ro, read_ro_firo, last_word_firo_ro : std_logic_vector(0 to NUM_ENDPOINTS); - signal data_firo_ro : RTPS_OUT_DATA_TYPE; + signal data_firo_ro : WORD_ARRAY_TYPE(0 to NUM_ENDPOINTS); signal service_if : SERVICE_INTERFACE_ARRAY_TYPE(0 to NUM_SERVICES-1); -- ###GENERATED START### -- INTERFACE-USER SIGNALS diff --git a/src/ros2/Tests/Level_2/L2_Testbench_ROS_Lib4.vhd b/src/ros2/Tests/Level_2/L2_Testbench_ROS_Lib4.vhd index a88199d..e7923e6 100644 --- a/src/ros2/Tests/Level_2/L2_Testbench_ROS_Lib4.vhd +++ b/src/ros2/Tests/Level_2/L2_Testbench_ROS_Lib4.vhd @@ -103,7 +103,7 @@ architecture arch of L2_Testbench_ROS_Lib4 is signal data_dw_wi, data_wi_dw : WARRAY_DATA_TYPE; signal status_dw_wi : STATUS_KIND_WARRAY_TYPE; signal empty_firo_ro, read_ro_firo, last_word_firo_ro : std_logic_vector(0 to NUM_ENDPOINTS); - signal data_firo_ro : RTPS_OUT_DATA_TYPE; + signal data_firo_ro : WORD_ARRAY_TYPE(0 to NUM_ENDPOINTS); signal action_if : ACTION_INTERFACE_ARRAY_TYPE(0 to NUM_ACTIONS-1); -- ###GENERATED START### signal start_s, ack_s, done_s : std_logic; diff --git a/src/ros2/Tests/Level_2/L2_Testbench_ROS_Lib5.vhd b/src/ros2/Tests/Level_2/L2_Testbench_ROS_Lib5.vhd index 7dda904..14274a3 100644 --- a/src/ros2/Tests/Level_2/L2_Testbench_ROS_Lib5.vhd +++ b/src/ros2/Tests/Level_2/L2_Testbench_ROS_Lib5.vhd @@ -149,7 +149,7 @@ architecture arch of L2_Testbench_ROS_Lib5 is signal data_dw_wi, data_wi_dw : WARRAY_DATA_TYPE; signal status_dw_wi : STATUS_KIND_WARRAY_TYPE; signal empty_firo_ro, read_ro_firo, last_word_firo_ro : std_logic_vector(0 to NUM_ENDPOINTS); - signal data_firo_ro : RTPS_OUT_DATA_TYPE; + signal data_firo_ro : WORD_ARRAY_TYPE(0 to NUM_ENDPOINTS); signal action_if : ACTION_INTERFACE_ARRAY_TYPE(0 to NUM_ACTIONS-1); begin diff --git a/src/rtps_config_package.vhd b/src/rtps_config_package.vhd index 3cebc02..9ead6ba 100644 --- a/src/rtps_config_package.vhd +++ b/src/rtps_config_package.vhd @@ -121,8 +121,6 @@ package rtps_config_package is constant READER_DEFAULT_QOS_MATCH : DEFAULT_QOS_MATCH_TYPE; -- Deferred to Package Body constant WRITER_DEFAULT_QOS_MATCH : DEFAULT_QOS_MATCH_TYPE; -- Deferred to Package Body - type RTPS_OUT_DATA_TYPE is array (0 to NUM_ENDPOINTS) of std_logic_vector(WORD_WIDTH-1 downto 0); - constant CLOCK_DURATION : DURATION_TYPE := gen_duration(CLOCK_PERIOD); -- Swap "data" to Big Endian representation. diff --git a/src/rtps_out.vhd b/src/rtps_out.vhd index 10b5e90..758e392 100644 --- a/src/rtps_out.vhd +++ b/src/rtps_out.vhd @@ -12,6 +12,7 @@ use work.rtps_config_package.all; entity rtps_out is generic ( + RTPS_OUT_WIDTH : natural := NUM_ENDPOINTS+1; -- Max Serialized Payload Size in a UDP Stream (Bytes) [MAX_PAYLOAD(65536) - IPv4_HEADER(20) - UDP_HEADER(8) + FORMAT_HEADER(16)] MAX_BUFFER_SIZE : natural := 65524/(WORD_WIDTH/BYTE_WIDTH) ); @@ -20,10 +21,10 @@ entity rtps_out is clk : in std_logic; reset : in std_logic; -- INPUT - empty : in std_logic_vector(0 to NUM_ENDPOINTS); - rd : out std_logic_vector(0 to NUM_ENDPOINTS); - data_in : in RTPS_OUT_DATA_TYPE; - last_word_in: in std_logic_vector(0 to NUM_ENDPOINTS); + empty : in std_logic_vector(0 to RTPS_OUT_WIDTH-1); + rd : out std_logic_vector(0 to RTPS_OUT_WIDTH-1); + data_in : in WORD_ARRAY_TYPE(0 to RTPS_OUT_WIDTH-1); + last_word_in: in std_logic_vector(0 to RTPS_OUT_WIDTH-1); -- OUTPUT full : in std_logic; wr : out std_logic; @@ -42,7 +43,7 @@ architecture arch of rtps_out is type OUTPUT_STAGE_TYPE is (IDLE, SRC_ADDR_HEADER, DEST_ADDR_HEADER, PORT_HEADER, PACKET_LENGTH, WRITE_PRIMER, WRITE, FINALIZE_WRITE); -- *SIGNAL DECLARATION* - signal selector, selector_next : natural range 0 to NUM_ENDPOINTS; + signal selector, selector_next : natural range 0 to RTPS_OUT_WIDTH-1; signal buff, buff_next : BUFFER_TYPE; signal in_pntr, in_pntr_next : unsigned(BUFFER_ADDR_WIDTH downto 0); signal out_pntr, out_pntr_next : unsigned(BUFFER_ADDR_WIDTH downto 0); @@ -107,7 +108,7 @@ begin -- Currently Selected Input FIFO is empty if (empty(selector) = '1') then -- Wrap from End to BEgining (Circular selection) - if (selector = NUM_ENDPOINTS) then + if (selector = RTPS_OUT_WIDTH-1) then selector_next <= 0; else -- Select next input FIFO @@ -134,7 +135,7 @@ begin input_stage_next <= IDLE; in_pntr_next <= to_unsigned(MAX_BUFFER_SIZE, in_pntr'length); -- Select next input FIFO (Prevent lifelock) - if (selector = NUM_ENDPOINTS) then + if (selector = RTPS_OUT_WIDTH-1) then selector_next <= 0; else selector_next <= selector + 1; @@ -154,7 +155,7 @@ begin input_stage_next <= IDLE; in_pntr_next <= to_unsigned(MAX_BUFFER_SIZE, in_pntr'length); -- Select next input FIFO (Prevent lifelock) - if (selector = NUM_ENDPOINTS) then + if (selector = RTPS_OUT_WIDTH-1) then selector_next <= 0; else selector_next <= selector + 1; @@ -174,7 +175,7 @@ begin input_stage_next <= IDLE; in_pntr_next <= to_unsigned(MAX_BUFFER_SIZE, in_pntr'length); -- Select next input FIFO (Prevent lifelock) - if (selector = NUM_ENDPOINTS) then + if (selector = RTPS_OUT_WIDTH-1) then selector_next <= 0; else selector_next <= selector + 1; @@ -204,7 +205,7 @@ begin input_stage_next <= IDLE; in_pntr_next <= to_unsigned(MAX_BUFFER_SIZE, in_pntr'length); -- Select next input FIFO (Prevent lifelock) - if (selector = NUM_ENDPOINTS) then + if (selector = RTPS_OUT_WIDTH-1) then selector_next <= 0; else selector_next <= selector + 1; @@ -228,7 +229,7 @@ begin input_stage_next <= IDLE; in_pntr_next <= to_unsigned(MAX_BUFFER_SIZE, in_pntr'length); -- Select next input FIFO (Prevent lifelock) - if (selector = NUM_ENDPOINTS) then + if (selector = RTPS_OUT_WIDTH-1) then selector_next <= 0; else selector_next <= selector + 1;