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BUG FIX: Decoder may not read last byte of payload

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The SKIP_PAYLOAD stage of decoders would not read the last word
(last_word_in = '1').
The <NAME>_MEMBER_END stage was removed from encoders/decoders, since it
could happen that the last aggregated member of a last collection entry
could also be the last type member overall, which would miss toggling
the "last_word_out" correctly. The logic was instead put inside the last
member stage (instead of defining a separate MEMEBR_END stage).
This commit is contained in:
John Ring 2022-02-03 15:05:10 +01:00
parent a26faff89a
commit b7fd9bfcfe
11 changed files with 131 additions and 111 deletions
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8
src/IDL-VHDL_Ref.txt
View File

@ -145,12 +145,12 @@ AGGREGATED TYPES
STRUCTURE STRUCTURE
--------- ---------
If a type member is in itself another structure, the generated <NAME> ports,signals,memories.stages,etc If a type member is in itself another structure, the generated <NAME> ports,signals,memories,stages,etc
are split into <NAME>_<SUB-NAME> signals,ports,memories,stages,etc. are split into <NAME>_<SUB-NAME> signals,ports,memories,stages,etc.
In case the element type of a collection type is an aggregated type, a new decode_stage called In case the element type of a collection type is an aggregated type, the stage of the last memebr is
<NAME>_MEMBER_END is generated, which handles the <NAME>_cnt increment and check which responsible for handling the <NAME>_cnt increment and check which normally be handled in the GET_<NAME>
normally be handled in the GET_<NAME> decode_stage. The <NAME>_ready and <NAME>_valid decode_stage. The <NAME>_ready and <NAME>_valid
port signals are generated by ANDing the respective memory signals of all sub-elements. port signals are generated by ANDing the respective memory signals of all sub-elements.
UNION UNION

2
src/TEMPLATE_reader_interface.vhd
View File

@ -267,7 +267,7 @@ begin
end if; end if;
end if; end if;
when SKIP_PAYLOAD => when SKIP_PAYLOAD =>
if (last_word_in_latch = '0' and last_word_in_dds = '0') then if (last_word_in_latch = '0') then
-- Skip Read -- Skip Read
ready_in_dds_sig <= '1'; ready_in_dds_sig <= '1';
else else

2
src/Tests/Type1_reader_interface.vhd
View File

@ -265,7 +265,7 @@ begin
end if; end if;
end if; end if;
when SKIP_PAYLOAD => when SKIP_PAYLOAD =>
if (last_word_in_latch = '0' and last_word_in_dds = '0') then if (last_word_in_latch = '0') then
-- Skip Read -- Skip Read
ready_in_dds_sig <= '1'; ready_in_dds_sig <= '1';
else else

71
src/Tests/Type2_key_holder.vhd
View File

@ -34,8 +34,8 @@ architecture TYPE2 of key_holder is
-- FSM states. Explained below in detail -- FSM states. Explained below in detail
type STAGE_TYPE is (IDLE,START_KEY_HASH_GENERATION,GET_PAYLOAD_HEADER,FETCH,ALIGN_IN_STREAM,SKIP_PAYLOAD,DECODE_PAYLOAD, WRITE_PAYLOAD_HEADER, PUSH,ALIGN_OUT_STREAM,ENCODE_PAYLOAD,GET_KEY_HASH,PUSH_KEY_HASH); type STAGE_TYPE is (IDLE,START_KEY_HASH_GENERATION,GET_PAYLOAD_HEADER,FETCH,ALIGN_IN_STREAM,SKIP_PAYLOAD,DECODE_PAYLOAD, WRITE_PAYLOAD_HEADER, PUSH,ALIGN_OUT_STREAM,ENCODE_PAYLOAD,GET_KEY_HASH,PUSH_KEY_HASH);
-- ###GENERATED START### -- ###GENERATED START###
type DECODE_STAGE_TYPE is (GET_ID,GET_TESTSEQUENCE_LENGTH,GET_TESTSEQUENCE_TESTARRAY,GET_TESTSEQUENCE_TESTCHAR,GET_TESTSEQUENCE_TESTWCHAR,GET_TESTSEQUENCE_TESTLONGLONG,GET_TESTSEQUENCE_TESTLONGDOUBLE,TESTSEQUENCE_MEMBER_END,GET_OPTIONAL_HEADER); type DECODE_STAGE_TYPE is (GET_ID,GET_TESTSEQUENCE_LENGTH,GET_TESTSEQUENCE_TESTARRAY,GET_TESTSEQUENCE_TESTCHAR,GET_TESTSEQUENCE_TESTWCHAR,GET_TESTSEQUENCE_TESTLONGLONG,GET_TESTSEQUENCE_TESTLONGDOUBLE,GET_OPTIONAL_HEADER);
type ENCODE_STAGE_TYPE is (WRITE_ID,WRITE_TESTSEQUENCE_LENGTH,WRITE_TESTSEQUENCE_TESTARRAY,TESTSEQUENCE_MEMBER_END); type ENCODE_STAGE_TYPE is (WRITE_ID,WRITE_TESTSEQUENCE_LENGTH,WRITE_TESTSEQUENCE_TESTARRAY);
type TESTSEQUENCE_TESTARRAY_ADDR_TYPE is array (0 to TESTSEQUENCE_MAX_DEPTH-1) of std_logic_vector(TESTSEQUENCE_TESTARRAY_ADDR_WIDTH-1 downto 0); type TESTSEQUENCE_TESTARRAY_ADDR_TYPE is array (0 to TESTSEQUENCE_MAX_DEPTH-1) of std_logic_vector(TESTSEQUENCE_TESTARRAY_ADDR_WIDTH-1 downto 0);
type TESTSEQUENCE_TESTARRAY_DATA_TYPE is array (0 to TESTSEQUENCE_MAX_DEPTH-1) of std_logic_vector(CDR_OCTET_WIDTH-1 downto 0); type TESTSEQUENCE_TESTARRAY_DATA_TYPE is array (0 to TESTSEQUENCE_MAX_DEPTH-1) of std_logic_vector(CDR_OCTET_WIDTH-1 downto 0);
-- ###GENERATED END### -- ###GENERATED END###
@ -367,7 +367,15 @@ begin
-- DES: The decoding stages are used for both PUSH_DATA and PUSH_SERIALIZED_KEY. -- DES: The decoding stages are used for both PUSH_DATA and PUSH_SERIALIZED_KEY.
-- We us the latched opcode to differentiate between them. -- We us the latched opcode to differentiate between them.
if (opcode_latch = PUSH_SERIALIZED_KEY) then if (opcode_latch = PUSH_SERIALIZED_KEY) then
decode_stage_next <= TESTSEQUENCE_MEMBER_END; -- All Elements processed
if (TestSequence_cnt = TestSequence_len_latch-1) then
-- Next Member
stage_next <= SKIP_PAYLOAD;
else
TestSequence_cnt_next <= TestSequence_cnt + 1;
decode_stage_next <= GET_TESTSEQUENCE_TESTARRAY;
TestSequence_TestArray_cnt_next <= 0;
end if;
else else
decode_stage_next <= GET_TESTSEQUENCE_TESTCHAR; decode_stage_next <= GET_TESTSEQUENCE_TESTCHAR;
end if; end if;
@ -440,7 +448,15 @@ begin
when GET_TESTSEQUENCE_TESTLONGDOUBLE => when GET_TESTSEQUENCE_TESTLONGDOUBLE =>
-- Optional Omitted -- Optional Omitted
if (optional = '0') then if (optional = '0') then
decode_stage_next <= TESTSEQUENCE_MEMBER_END; -- All Elements processed
if (TestSequence_cnt = TestSequence_len_latch-1) then
-- Next Member
stage_next <= SKIP_PAYLOAD;
else
TestSequence_cnt_next <= TestSequence_cnt + 1;
decode_stage_next <= GET_TESTSEQUENCE_TESTARRAY;
TestSequence_TestArray_cnt_next <= 0;
end if;
-- ALIGN GUARD -- ALIGN GUARD
elsif (not check_align(align_offset, ALIGN_8)) then elsif (not check_align(align_offset, ALIGN_8)) then
target_align_next <= ALIGN_8; target_align_next <= ALIGN_8;
@ -466,22 +482,20 @@ begin
-- Push Quad Word -- Push Quad Word
when 4 => when 4 =>
align_offset_next <= align_offset + 16; align_offset_next <= align_offset + 16;
decode_stage_next <= TESTSEQUENCE_MEMBER_END;
-- All Elements processed
if (TestSequence_cnt = TestSequence_len_latch-1) then
-- Next Member
stage_next <= SKIP_PAYLOAD;
else
TestSequence_cnt_next <= TestSequence_cnt + 1;
decode_stage_next <= GET_TESTSEQUENCE_TESTARRAY;
TestSequence_TestArray_cnt_next <= 0;
end if;
when others => when others =>
null; null;
end case; end case;
end if; end if;
-- DES: If the elements of an array/sequence are of a complex/nested type, the array/sequence iteration check is done in a seperate *_MEMBER_END stage.
when TESTSEQUENCE_MEMBER_END =>
-- All Elements processed
if (TestSequence_cnt = TestSequence_len_latch-1) then
-- Next Member
stage_next <= SKIP_PAYLOAD;
else
TestSequence_cnt_next <= TestSequence_cnt + 1;
decode_stage_next <= GET_TESTSEQUENCE_TESTARRAY;
TestSequence_TestArray_cnt_next <= 0;
end if;
-- ###GENERATED END### -- ###GENERATED END###
when GET_OPTIONAL_HEADER => when GET_OPTIONAL_HEADER =>
-- ALIGN GUARD -- ALIGN GUARD
@ -693,8 +707,17 @@ begin
-- All Elements processed -- All Elements processed
if (TestSequence_TestArray_cnt = TESTSEQUENCE_TESTARRAY_MAX_DEPTH-1) then if (TestSequence_TestArray_cnt = TESTSEQUENCE_TESTARRAY_MAX_DEPTH-1) then
-- DONE -- All Elements processed
encode_stage_next <= TESTSEQUENCE_MEMBER_END; if (TestSequence_cnt = unsigned(TestSequence_len_latch)-1) then
-- DONE
stage_next <= PUSH;
finalize_payload_next <= '1';
else
TestSequence_cnt_next <= TestSequence_cnt + 1;
encode_stage_next <= WRITE_TESTSEQUENCE_TESTARRAY;
TestSequence_TestArray_cnt_next <= 0;
cnt_next <= 0;
end if;
else else
TestSequence_TestArray_cnt_next <= TestSequence_TestArray_cnt + 1; TestSequence_TestArray_cnt_next <= TestSequence_TestArray_cnt + 1;
end if; end if;
@ -708,18 +731,6 @@ begin
when others => when others =>
end case; end case;
end if; end if;
when TESTSEQUENCE_MEMBER_END =>
-- All Elements processed
if (TestSequence_cnt = unsigned(TestSequence_len_latch)-1) then
-- DONE
stage_next <= PUSH;
finalize_payload_next <= '1';
else
TestSequence_cnt_next <= TestSequence_cnt + 1;
encode_stage_next <= WRITE_TESTSEQUENCE_TESTARRAY;
TestSequence_TestArray_cnt_next <= 0;
cnt_next <= 0;
end if;
-- ###GENERATED END### -- ###GENERATED END###
end case; end case;
when GET_KEY_HASH => when GET_KEY_HASH =>

91
src/Tests/Type2_reader_interface.vhd
View File

@ -132,7 +132,7 @@ architecture arch of Type2_reader_interface is
-- FSM states. Explained below in detail -- FSM states. Explained below in detail
type STAGE_TYPE is (IDLE,GET_PAYLOAD_HEADER,FETCH,ALIGN_STREAM,SKIP_PAYLOAD,DECODE_PAYLOAD); type STAGE_TYPE is (IDLE,GET_PAYLOAD_HEADER,FETCH,ALIGN_STREAM,SKIP_PAYLOAD,DECODE_PAYLOAD);
-- ###GENERATED START### -- ###GENERATED START###
type DECODE_STAGE_TYPE is (GET_ID,GET_TESTSEQUENCE_LENGTH,GET_TESTSEQUENCE_TESTARRAY,GET_TESTSEQUENCE_TESTCHAR,GET_TESTSEQUENCE_TESTWCHAR,GET_TESTSEQUENCE_TESTLONGLONG,GET_TESTSEQUENCE_TESTLONGDOUBLE,TESTSEQUENCE_MEMBER_END,GET_TESTMAP_LENGTH,GET_TESTMAP_KEY,GET_TESTMAP_VALUE,TESTMAP_MEMBER_END,GET_TESTENUM,GET_TESTUNION_D,GET_TESTUNION_LONGU,GET_TESTUNION_OCTETU,GET_TESTBITMASK,GET_TESTSTRING_LENGTH,GET_TESTSTRING,GET_OPTIONAL_HEADER); type DECODE_STAGE_TYPE is (GET_ID,GET_TESTSEQUENCE_LENGTH,GET_TESTSEQUENCE_TESTARRAY,GET_TESTSEQUENCE_TESTCHAR,GET_TESTSEQUENCE_TESTWCHAR,GET_TESTSEQUENCE_TESTLONGLONG,GET_TESTSEQUENCE_TESTLONGDOUBLE,GET_TESTMAP_LENGTH,GET_TESTMAP_KEY,GET_TESTMAP_VALUE,GET_TESTENUM,GET_TESTUNION_D,GET_TESTUNION_LONGU,GET_TESTUNION_OCTETU,GET_TESTBITMASK,GET_TESTSTRING_LENGTH,GET_TESTSTRING,GET_OPTIONAL_HEADER);
type TESTSEQUENCE_TESTARRAY_ADDR_TYPE is array (0 to TESTSEQUENCE_MAX_DEPTH-1) of std_logic_vector(TESTSEQUENCE_TESTARRAY_ADDR_WIDTH-1 downto 0); type TESTSEQUENCE_TESTARRAY_ADDR_TYPE is array (0 to TESTSEQUENCE_MAX_DEPTH-1) of std_logic_vector(TESTSEQUENCE_TESTARRAY_ADDR_WIDTH-1 downto 0);
type TESTSEQUENCE_TESTARRAY_DATA_TYPE is array (0 to TESTSEQUENCE_MAX_DEPTH-1) of std_logic_vector(CDR_OCTET_WIDTH-1 downto 0); type TESTSEQUENCE_TESTARRAY_DATA_TYPE is array (0 to TESTSEQUENCE_MAX_DEPTH-1) of std_logic_vector(CDR_OCTET_WIDTH-1 downto 0);
-- ###GENERATED END### -- ###GENERATED END###
@ -639,7 +639,7 @@ begin
end if; end if;
end if; end if;
when SKIP_PAYLOAD => when SKIP_PAYLOAD =>
if (last_word_in_latch = '0' and last_word_in_dds = '0') then if (last_word_in_latch = '0') then
-- Skip Read -- Skip Read
ready_in_dds_sig <= '1'; ready_in_dds_sig <= '1';
else else
@ -774,14 +774,14 @@ begin
case (cnt) is case (cnt) is
-- Double Word 1/2 -- Double Word 1/2
when 0 => when 0 =>
dw_latch_next(CDR_LONG_LONG_WIDTH-1 downto CDR_LONG_LONG_WIDTH/2) <= data_in_latch; dw_latch_next <= write_sub_vector(dw_latch_next, data_in_latch, 0, TRUE);
stage_next <= FETCH; stage_next <= FETCH;
cnt_next <= cnt + 1; cnt_next <= cnt + 1;
-- Double Word 2/2 -- Double Word 2/2
when 1 => when 1 =>
dw_latch_next((CDR_LONG_LONG_WIDTH/2)-1 downto 0) <= data_in_latch; dw_latch_next <= write_sub_vector(dw_latch_next, data_in_latch, 1, TRUE);
stage_next <= FETCH; stage_next <= FETCH;
cnt_next <= cnt + 1; cnt_next <= cnt + 1;
-- Push Double Word -- Push Double Word
when 2 => when 2 =>
TestSequence_TestLongLong_mem_addr <= std_logic_vector(to_unsigned(TestSequence_cnt,TESTSEQUENCE_ADDR_WIDTH)); TestSequence_TestLongLong_mem_addr <= std_logic_vector(to_unsigned(TestSequence_cnt,TESTSEQUENCE_ADDR_WIDTH));
@ -808,7 +808,15 @@ begin
TestSequence_TestLongDouble_mem_valid_in <= '1'; TestSequence_TestLongDouble_mem_valid_in <= '1';
-- Memory Operation Guard -- Memory Operation Guard
if (TestSequence_TestLongLong_mem_ready_in = '1') then if (TestSequence_TestLongLong_mem_ready_in = '1') then
decode_stage_next <= TESTSEQUENCE_MEMBER_END; -- All Elements processed
if (TestSequence_cnt = TestSequence_len_latch-1) then
-- Next Member
decode_stage_next <= GET_TESTMAP_LENGTH;
else
TestSequence_cnt_next <= TestSequence_cnt + 1;
decode_stage_next <= GET_TESTSEQUENCE_TESTARRAY;
TestSequence_TestArray_cnt_next <= 0;
end if;
end if; end if;
-- ALIGN GUARD -- ALIGN GUARD
elsif (not check_align(align_offset, ALIGN_8)) then elsif (not check_align(align_offset, ALIGN_8)) then
@ -818,24 +826,24 @@ begin
case (cnt) is case (cnt) is
-- Quad Word 1/4 -- Quad Word 1/4
when 0 => when 0 =>
qw_latch_next(CDR_LONG_DOUBLE_WIDTH-1 downto CDR_LONG_DOUBLE_WIDTH-WORD_WIDTH) <= data_in_latch; qw_latch_next <= write_sub_vector(qw_latch_next, data_in_latch, 0, TRUE);
stage_next <= FETCH; stage_next <= FETCH;
cnt_next <= cnt + 1; cnt_next <= cnt + 1;
-- Quad Word 2/4 -- Quad Word 2/4
when 1 => when 1 =>
qw_latch_next(CDR_LONG_DOUBLE_WIDTH-WORD_WIDTH-1 downto CDR_LONG_DOUBLE_WIDTH-(2*WORD_WIDTH)) <= data_in_latch; qw_latch_next <= write_sub_vector(qw_latch_next, data_in_latch, 1, TRUE);
stage_next <= FETCH; stage_next <= FETCH;
cnt_next <= cnt + 1; cnt_next <= cnt + 1;
-- Quad Word 3/4 -- Quad Word 3/4
when 2 => when 2 =>
qw_latch_next(CDR_LONG_DOUBLE_WIDTH-(2*WORD_WIDTH)-1 downto CDR_LONG_DOUBLE_WIDTH-(3*WORD_WIDTH)) <= data_in_latch; qw_latch_next <= write_sub_vector(qw_latch_next, data_in_latch, 2, TRUE);
stage_next <= FETCH; stage_next <= FETCH;
cnt_next <= cnt + 1; cnt_next <= cnt + 1;
-- Quad Word 4/4 -- Quad Word 4/4
when 3 => when 3 =>
qw_latch_next(WORD_WIDTH-1 downto 0) <= data_in_latch; qw_latch_next <= write_sub_vector(qw_latch_next, data_in_latch, 3, TRUE);
stage_next <= FETCH; stage_next <= FETCH;
cnt_next <= cnt + 1; cnt_next <= cnt + 1;
-- Push Quad Word -- Push Quad Word
when 4 => when 4 =>
TestSequence_TestLongDouble_mem_addr <= std_logic_vector(to_unsigned(TestSequence_cnt,TESTSEQUENCE_ADDR_WIDTH)); TestSequence_TestLongDouble_mem_addr <= std_logic_vector(to_unsigned(TestSequence_cnt,TESTSEQUENCE_ADDR_WIDTH));
@ -845,23 +853,21 @@ begin
-- Memory Operation Guard -- Memory Operation Guard
if (TestSequence_TestLongLong_mem_ready_in = '1') then if (TestSequence_TestLongLong_mem_ready_in = '1') then
align_offset_next <= align_offset + 16; align_offset_next <= align_offset + 16;
decode_stage_next <= TESTSEQUENCE_MEMBER_END;
-- All Elements processed
if (TestSequence_cnt = TestSequence_len_latch-1) then
-- Next Member
decode_stage_next <= GET_TESTMAP_LENGTH;
else
TestSequence_cnt_next <= TestSequence_cnt + 1;
decode_stage_next <= GET_TESTSEQUENCE_TESTARRAY;
TestSequence_TestArray_cnt_next <= 0;
end if;
end if; end if;
when others => when others =>
null; null;
end case; end case;
end if; end if;
-- DES: If the elements of an array/sequence are of a complex/nested type, the array/sequence iteration check is done in a seperate *_MEMBER_END stage.
when TESTSEQUENCE_MEMBER_END =>
-- All Elements processed
if (TestSequence_cnt = TestSequence_len_latch-1) then
-- Next Member
decode_stage_next <= GET_TESTMAP_LENGTH;
else
TestSequence_cnt_next <= TestSequence_cnt + 1;
decode_stage_next <= GET_TESTSEQUENCE_TESTARRAY;
TestSequence_TestArray_cnt_next <= 0;
end if;
when GET_TESTMAP_LENGTH => when GET_TESTMAP_LENGTH =>
-- ALIGN GUARD -- ALIGN GUARD
if (not check_align(align_offset, ALIGN_4)) then if (not check_align(align_offset, ALIGN_4)) then
@ -920,7 +926,15 @@ begin
-- Memory Operation Guard -- Memory Operation Guard
if (TestMap_value_mem_ready_in = '1') then if (TestMap_value_mem_ready_in = '1') then
align_offset_next <= align_offset + 2; align_offset_next <= align_offset + 2;
decode_stage_next <= TESTMAP_MEMBER_END;
-- All Elements processed
if (TestMap_cnt = TestMap_len_latch-1) then
-- Next Member
decode_stage_next <= GET_TESTENUM;
else
TestMap_cnt_next <= TestMap_cnt + 1;
decode_stage_next <= GET_TESTMAP_KEY;
end if;
-- Need to fetch next Word -- Need to fetch next Word
if(align_offset(1 downto 1) = "1") then if(align_offset(1 downto 1) = "1") then
@ -928,15 +942,6 @@ begin
end if; end if;
end if; end if;
end if; end if;
when TESTMAP_MEMBER_END =>
-- All Elements processed
if (TestMap_cnt = TestMap_len_latch-1) then
-- Next Member
decode_stage_next <= GET_TESTENUM;
else
TestMap_cnt_next <= TestMap_cnt + 1;
decode_stage_next <= GET_TESTMAP_KEY;
end if;
when GET_TESTENUM => when GET_TESTENUM =>
-- ALIGN GUARD -- ALIGN GUARD
if (not check_align(align_offset, ALIGN_1)) then if (not check_align(align_offset, ALIGN_1)) then

58
src/Tests/Type2_writer_interface.vhd
View File

@ -116,7 +116,7 @@ architecture arch of Type2_writer_interface is
-- FSM states. Explained below in detail -- FSM states. Explained below in detail
type STAGE_TYPE is (IDLE,WRITE_PAYLOAD_HEADER,PUSH,ALIGN_STREAM,ENCODE_PAYLOAD); type STAGE_TYPE is (IDLE,WRITE_PAYLOAD_HEADER,PUSH,ALIGN_STREAM,ENCODE_PAYLOAD);
-- ###GENERATED START### -- ###GENERATED START###
type ENCODE_STAGE_TYPE is (WRITE_ID,WRITE_TESTSEQUENCE_LENGTH,WRITE_TESTSEQUENCE_TESTARRAY,WRITE_TESTSEQUENCE_TESTCHAR,WRITE_TESTSEQUENCE_TESTWCHAR,WRITE_TESTSEQUENCE_TESTLONGLONG,WRITE_TESTSEQUENCE_TESTLONGDOUBLE,TESTSEQUENCE_MEMBER_END,WRITE_TESTMAP_LENGTH,WRITE_TESTMAP_KEY,WRITE_TESTMAP_VALUE,TESTMAP_MEMBER_END,WRITE_TESTENUM,WRITE_TESTUNION_D,WRITE_TESTUNION_LONGU,WRITE_TESTUNION_OCTETU,WRITE_TESTBITMASK,WRITE_TESTSTRING_LENGTH,WRITE_TESTSTRING); type ENCODE_STAGE_TYPE is (WRITE_ID,WRITE_TESTSEQUENCE_LENGTH,WRITE_TESTSEQUENCE_TESTARRAY,WRITE_TESTSEQUENCE_TESTCHAR,WRITE_TESTSEQUENCE_TESTWCHAR,WRITE_TESTSEQUENCE_TESTLONGLONG,WRITE_TESTSEQUENCE_TESTLONGDOUBLE,WRITE_TESTMAP_LENGTH,WRITE_TESTMAP_KEY,WRITE_TESTMAP_VALUE,WRITE_TESTENUM,WRITE_TESTUNION_D,WRITE_TESTUNION_LONGU,WRITE_TESTUNION_OCTETU,WRITE_TESTBITMASK,WRITE_TESTSTRING_LENGTH,WRITE_TESTSTRING);
type TESTSEQUENCE_TESTARRAY_ADDR_TYPE is array (0 to TESTSEQUENCE_MAX_DEPTH-1) of std_logic_vector(TESTSEQUENCE_TESTARRAY_ADDR_WIDTH-1 downto 0); type TESTSEQUENCE_TESTARRAY_ADDR_TYPE is array (0 to TESTSEQUENCE_MAX_DEPTH-1) of std_logic_vector(TESTSEQUENCE_TESTARRAY_ADDR_WIDTH-1 downto 0);
type TESTSEQUENCE_TESTARRAY_DATA_TYPE is array (0 to TESTSEQUENCE_MAX_DEPTH-1) of std_logic_vector(CDR_OCTET_WIDTH-1 downto 0); type TESTSEQUENCE_TESTARRAY_DATA_TYPE is array (0 to TESTSEQUENCE_MAX_DEPTH-1) of std_logic_vector(CDR_OCTET_WIDTH-1 downto 0);
-- ###GENERATED END### -- ###GENERATED END###
@ -785,7 +785,16 @@ begin
-- Member ID 4, Length 0 -- Member ID 4, Length 0
data_out_latch_next <= x"0004" & x"0000"; data_out_latch_next <= x"0004" & x"0000";
encode_stage_next <= TESTSEQUENCE_MEMBER_END; -- All Elements processed
if (TestSequence_cnt = unsigned(TestSequence_len)-1) then
-- Next Member
encode_stage_next <= WRITE_TESTMAP_LENGTH;
else
TestSequence_cnt_next <= TestSequence_cnt + 1;
encode_stage_next <= WRITE_TESTSEQUENCE_TESTARRAY;
TestSequence_TestArray_cnt_next <= 0;
cnt_next <= 0;
end if;
-- "Comsume" input word -- "Comsume" input word
TestSequence_TestLongDouble_mem_ready_out <= '1'; TestSequence_TestLongDouble_mem_ready_out <= '1';
end if; end if;
@ -825,24 +834,21 @@ begin
data_out_latch_next <= get_sub_vector(endian_swap(LITTLE_ENDIAN, TestSequence_TestLongDouble_mem_data_out(CDR_LONG_DOUBLE_WIDTH-1 downto 0)), 3, WORD_WIDTH, TRUE); data_out_latch_next <= get_sub_vector(endian_swap(LITTLE_ENDIAN, TestSequence_TestLongDouble_mem_data_out(CDR_LONG_DOUBLE_WIDTH-1 downto 0)), 3, WORD_WIDTH, TRUE);
stage_next <= PUSH; stage_next <= PUSH;
align_offset_next <= align_offset + 16; align_offset_next <= align_offset + 16;
encode_stage_next <= TESTSEQUENCE_MEMBER_END;
cnt_next <= 0; -- All Elements processed
if (TestSequence_cnt = unsigned(TestSequence_len)-1) then
-- Next Member
encode_stage_next <= WRITE_TESTMAP_LENGTH;
else
TestSequence_cnt_next <= TestSequence_cnt + 1;
encode_stage_next <= WRITE_TESTSEQUENCE_TESTARRAY;
TestSequence_TestArray_cnt_next <= 0;
cnt_next <= 0;
end if;
end if; end if;
when others => when others =>
end case; end case;
end if; end if;
-- DES: If the elements of an array/sequence are of a complex/nested type, the array/sequence iteration check is done in a seperate *_MEMBER_END stage.
when TESTSEQUENCE_MEMBER_END =>
-- All Elements processed
if (TestSequence_cnt = unsigned(TestSequence_len)-1) then
-- Next Member
encode_stage_next <= WRITE_TESTMAP_LENGTH;
else
TestSequence_cnt_next <= TestSequence_cnt + 1;
encode_stage_next <= WRITE_TESTSEQUENCE_TESTARRAY;
TestSequence_TestArray_cnt_next <= 0;
cnt_next <= 0;
end if;
when WRITE_TESTMAP_LENGTH => when WRITE_TESTMAP_LENGTH =>
-- ALIGN GUARD -- ALIGN GUARD
if (not check_align(align_offset, ALIGN_4)) then if (not check_align(align_offset, ALIGN_4)) then
@ -923,7 +929,15 @@ begin
data_out_latch_next <= write_sub_vector(data_out_latch, endian_swap(LITTLE_ENDIAN, TestMap_value_mem_data_out), to_integer(align_offset(1 downto 1)), TRUE); data_out_latch_next <= write_sub_vector(data_out_latch, endian_swap(LITTLE_ENDIAN, TestMap_value_mem_data_out), to_integer(align_offset(1 downto 1)), TRUE);
align_offset_next <= align_offset + 2; align_offset_next <= align_offset + 2;
encode_stage_next <= TESTMAP_MEMBER_END; -- All Elements processed
if (TestMap_cnt = unsigned(TestMap_len)-1) then
-- Next Member
encode_stage_next <= WRITE_TESTENUM;
else
TestMap_cnt_next <= TestMap_cnt + 1;
encode_stage_next <= WRITE_TESTMAP_KEY;
cnt_next <= 0;
end if;
-- Need to fetch next Word -- Need to fetch next Word
if(align_offset(1 downto 1) = "1") then if(align_offset(1 downto 1) = "1") then
@ -933,16 +947,6 @@ begin
when others => when others =>
end case; end case;
end if; end if;
when TESTMAP_MEMBER_END =>
-- All Elements processed
if (TestMap_cnt = unsigned(TestMap_len)-1) then
-- Next Member
encode_stage_next <= WRITE_TESTENUM;
else
TestMap_cnt_next <= TestMap_cnt + 1;
encode_stage_next <= WRITE_TESTMAP_KEY;
cnt_next <= 0;
end if;
when WRITE_TESTENUM => when WRITE_TESTENUM =>
-- ALIGN GUARD -- ALIGN GUARD
if (not check_align(align_offset, ALIGN_1)) then if (not check_align(align_offset, ALIGN_1)) then

2
src/ros2/TEMPLATE_srv_client.vhd
View File

@ -463,7 +463,7 @@ begin
null; null;
end case; end case;
when SKIP_PAYLOAD => when SKIP_PAYLOAD =>
if (last_word_in_latch = '0' and last_word_in_r = '0') then if (last_word_in_latch = '0') then
-- Skip Read -- Skip Read
ready_in_r_sig <= '1'; ready_in_r_sig <= '1';
else else

2
src/ros2/TEMPLATE_srv_server.vhd
View File

@ -458,7 +458,7 @@ begin
null; null;
end case; end case;
when SKIP_PAYLOAD => when SKIP_PAYLOAD =>
if (last_word_in_latch = '0' and last_word_in_r = '0') then if (last_word_in_latch = '0') then
-- Skip Read -- Skip Read
ready_in_r_sig <= '1'; ready_in_r_sig <= '1';
else else

2
src/ros2/example_interfaces/AddTwoInts_srv_client.vhd
View File

@ -487,7 +487,7 @@ begin
null; null;
end case; end case;
when SKIP_PAYLOAD => when SKIP_PAYLOAD =>
if (last_word_in_latch = '0' and last_word_in_r = '0') then if (last_word_in_latch = '0') then
-- Skip Read -- Skip Read
ready_in_r_sig <= '1'; ready_in_r_sig <= '1';
else else

2
src/ros2/example_interfaces/AddTwoInts_srv_server.vhd
View File

@ -512,7 +512,7 @@ begin
null; null;
end case; end case;
when SKIP_PAYLOAD => when SKIP_PAYLOAD =>
if (last_word_in_latch = '0' and last_word_in_r = '0') then if (last_word_in_latch = '0') then
-- Skip Read -- Skip Read
ready_in_r_sig <= '1'; ready_in_r_sig <= '1';
else else

2
src/ros2/example_interfaces/Fibonacci_action_feedback_sub.vhd
View File

@ -510,7 +510,7 @@ begin
null; null;
end case; end case;
when SKIP_PAYLOAD => when SKIP_PAYLOAD =>
if (last_word_in_latch = '0' and last_word_in_dds = '0') then if (last_word_in_latch = '0') then
-- Skip Read -- Skip Read
ready_in_dds_sig <= '1'; ready_in_dds_sig <= '1';
else else