Insert Instances in KEY_HASH numerical order
in order to support the read_next_instance/take_next_instance operations, the instances have to have a a logical order. Whie the previous implementation did have a logical order for inserted instances (Since they are added in a linked list), we need to support relative ordering also for non-inserted instances (acording to DDS Spec), so we just order them in ascending order.
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f152abc373
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@ -196,7 +196,7 @@ architecture arch of history_cache is
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signal inst_next_addr_base, inst_next_addr_base_next : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0');
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signal inst_prev_addr_base, inst_prev_addr_base_next : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0');
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signal inst_empty_head, inst_empty_head_next : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0');
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signal inst_occupied_tail, inst_occupied_tail_next : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0');
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signal inst_occupied_head, inst_occupied_head_next : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0');
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signal inst_latch_data, inst_latch_data_next : INST_LATCH_DATA_TYPE := ZERO_INST_LATCH_DATA;
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signal update_inst_flags : std_logic_vector(0 to UPDATE_INSTANCE_FLAG_WIDTH-1) := (others => '0');
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signal inst_cnt, inst_cnt_next : natural range TODO := 0;
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@ -1337,9 +1337,9 @@ begin
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-- by the main process that the operation can succeed (Memory is available)
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assert (inst_empty_head /= INSTANCE_MEMORY_MAX_ADDRESS) report "Instance Insertion while memory Full" severity FAILURE;
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inst_addr_next <= inst_empty_head;
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inst_addr_base_next <= inst_empty_head;
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inst_stage_next <= INSERT_INSTANCE;
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inst_addr_next <= inst_occupied_head;
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inst_addr_base_next <= inst_occupied_head;
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inst_stage_next <= FIND_POS;
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inst_cnt_next <= 0;
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when UPDATE_INSTANCE =>
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inst_addr_base_next <= inst_addr_update;
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@ -1578,65 +1578,212 @@ begin
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-- DONE
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inst_stage_next <= IDLE;
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end if;
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when INSERT_INSTANCE =>
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when FIND_POS =>
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inst_cnt_next <= inst_cnt + 1;
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inst_addr_next <= inst_addr + 1;
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inst_ren <= '1';
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inst_wen <= '1';
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-- NOTE: Instances are inserted in KEY_HASH numerical order.
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case (inst_cnt) is
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-- Preload
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when 0 =>
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null;
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-- Next Instance
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when 1 =>
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inst_next_addr_base_next <= inst_read_data;
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-- Key Hash 1/4
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when 2 =>
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-- Found Position
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if (inst_latch_data.key_hash(0) < inst_read_data) then
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inst_next_addr_base_next <= inst_addr_base;
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-- Occupied List Head
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if (inst_prev_addr_base = INSTANCE_MEMORY_MAX_ADDRESS) then
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assert (inst_addr_base = inst_occupied_head)
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inst_occupied_head_next <= inst_empty_head;
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inst_addr_base_next <= inst_empty_head;
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inst_addr_next <= inst_empty_head + IMF_NEXT_ADDR_OFFSET;
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inst_stage_next <= INSERT_INSTANCE;
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cnt_next <= 1; -- Skip First Step
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else
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inst_addr_base_next <= inst_prev_addr_base;
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inst_addr_next <= inst_prev_addr_base + IMF_NEXT_ADDR_OFFSET;
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inst_stage_next <= INSERT_INSTANCE;
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cnt_next <= 0;
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end if;
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-- BIGGER-THAN
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elsif (inst_latch_data.key_hash /= inst_read_data) then
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-- Continue
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inst_prev_addr_base_next <= inst_addr_base;
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inst_addr_next <= inst_next_addr_base;
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inst_addr_base_next <= inst_next_addr_base;
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cnt_next <= 0;
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end if;
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-- Key Hash 2/4
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when 3 =>
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-- Found Position
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if (inst_latch_data.key_hash < inst_read_data) then
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inst_next_addr_base_next <= inst_addr_base;
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-- Occupied List Head
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if (inst_prev_addr_base = INSTANCE_MEMORY_MAX_ADDRESS) then
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assert (inst_addr_base = inst_occupied_head)
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inst_occupied_head_next <= inst_empty_head;
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inst_addr_base_next <= inst_empty_head;
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inst_addr_next <= inst_empty_head + IMF_NEXT_ADDR_OFFSET;
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inst_stage_next <= INSERT_INSTANCE;
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cnt_next <= 1; -- Skip First Step
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else
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inst_addr_base_next <= inst_prev_addr_base;
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inst_addr_next <= inst_prev_addr_base + IMF_NEXT_ADDR_OFFSET;
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inst_stage_next <= INSERT_INSTANCE;
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cnt_next <= 0;
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end if;
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-- BIGGER-THAN
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elsif (inst_latch_data.key_hash(1) /= inst_read_data) then
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-- Continue
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inst_prev_addr_base_next <= inst_addr_base;
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inst_addr_next <= inst_next_addr_base;
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inst_addr_base_next <= inst_next_addr_base;
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cnt_next <= 0;
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end if;
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-- Key Hash 3/4
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when 4 =>
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-- Found Position
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if (inst_latch_data.key_hash(2) < inst_read_data) then
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inst_next_addr_base_next <= inst_addr_base;
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-- Occupied List Head
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if (inst_prev_addr_base = INSTANCE_MEMORY_MAX_ADDRESS) then
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assert (inst_addr_base = inst_occupied_head)
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inst_occupied_head_next <= inst_empty_head;
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inst_addr_base_next <= inst_empty_head;
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inst_addr_next <= inst_empty_head + IMF_NEXT_ADDR_OFFSET;
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inst_stage_next <= INSERT_INSTANCE;
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cnt_next <= 1; -- Skip First Step
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else
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inst_addr_base_next <= inst_prev_addr_base;
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inst_addr_next <= inst_prev_addr_base + IMF_NEXT_ADDR_OFFSET;
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inst_stage_next <= INSERT_INSTANCE;
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cnt_next <= 0;
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end if;
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-- BIGGER-THAN
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elsif (inst_latch_data.key_hash /= inst_read_data) then
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-- Continue
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inst_prev_addr_base_next <= inst_addr_base;
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inst_addr_next <= inst_next_addr_base;
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inst_addr_base_next <= inst_next_addr_base;
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cnt_next <= 0;
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end if;
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-- Key Hash 4/4
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when 5 =>
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-- Found Position
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if (inst_latch_data.key_hash(3) < inst_read_data) then
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inst_next_addr_base_next <= inst_addr_base;
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-- Occupied List Head
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if (inst_prev_addr_base = INSTANCE_MEMORY_MAX_ADDRESS) then
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assert (inst_addr_base = inst_occupied_head)
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inst_occupied_head_next <= inst_empty_head;
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inst_addr_base_next <= inst_empty_head;
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inst_addr_next <= inst_empty_head + IMF_NEXT_ADDR_OFFSET;
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inst_stage_next <= INSERT_INSTANCE;
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cnt_next <= 1; -- Skip First Step
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else
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inst_addr_base_next <= inst_prev_addr_base;
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inst_addr_next <= inst_prev_addr_base + IMF_NEXT_ADDR_OFFSET;
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inst_stage_next <= INSERT_INSTANCE;
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cnt_next <= 0;
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end if;
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else
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assert (inst_latch_data.key_hash(3) /= inst_read_data) report "Doublicate Instance Detected" severity FAILURE;
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-- Continue
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inst_prev_addr_base_next <= inst_addr_base;
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inst_addr_next <= inst_next_addr_base;
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inst_addr_base_next <= inst_next_addr_base;
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cnt_next <= 0;
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end if;
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when others =>
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null;
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end case;
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when INSERT_INSTANCE =>
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inst_addr_next <= inst_addr + 1;
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inst_cnt_next <= inst_cnt + 1;
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case (inst_cnt) is
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-- Preload
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-- Next Pointer (Previous Instance)
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when 0 =>
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inst_ren <= '1';
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-- Next Instance Address
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inst_write_data <= inst_empty_head;
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inst_wen <= '1';
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inst_addr_next <= inst_empty_head;
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inst_addr_base_next <= inst_empty_head;
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-- Preload
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when 1 =>
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inst_empty_head_next <= inst_read_data;
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-- Make New Occupied Head
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inst_write_data <= inst_occupied_head;
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inst_occupied_head_next <= inst_empty_head;
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-- Key Hash 1/4
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inst_ren <= '1';
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inst_addr_next <= inst_addr; -- Keep Addr
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-- Next Pointer (New Instance)
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when 2 =>
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inst_write_data <= inst_latch_data.key_hash(0);
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-- Key Hash 2/4
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-- Fix Empty List Head
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inst_empty_head_next <= inst_read_data;
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inst_write_data <= inst_next_addr_base;
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inst_wen <= '1';
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-- Key Hash 1/4
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when 3 =>
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inst_write_data <= inst_latch_data.key_hash(1);
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-- Key Hash 3/4
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inst_write_data <= inst_latch_data.key_hash(0);
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inst_wen <= '1';
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-- Key Hash 2/4
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when 4 =>
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inst_write_data <= inst_latch_data.key_hash(2);
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-- Key Hash 4/4
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inst_write_data <= inst_latch_data.key_hash(1);
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inst_wen <= '1';
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-- Key Hash 3/4
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when 5 =>
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inst_write_data <= inst_latch_data.key_hash(3);
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-- Status Info
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inst_write_data <= inst_latch_data.key_hash(2);
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inst_wen <= '1';
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-- Key Hash 4/4
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when 6 =>
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inst_write_data <= inst_latch_data.status_info;
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-- Sample Count
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inst_write_data <= inst_latch_data.key_hash(3);
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inst_wen <= '1';
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-- Status Info
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when 7 =>
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inst_write_data <= std_logic_vector(to_unsigned(1, WORD_WIDTH));
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-- Disposed Generation Count
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inst_write_data <= inst_latch_data.status_info;
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inst_wen <= '1';
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-- Sample Count
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when 8 =>
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inst_write_data <= (others => '0');
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-- No Writers Generation Count
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inst_write_data <= std_logic_vector(to_unsigned(1, WORD_WIDTH));
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inst_wen <= '1';
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-- Disposed Generation Count
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when 9 =>
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inst_write_data <= (others => '0');
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inst_write_data <= (others => '0');
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inst_wen <= '1';
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-- No Writers Generation Count
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when 10 =>
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inst_write_data <= (others => '0');
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inst_wen <= '1';
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if (TIME_BASED_FILTER_QOS /= DURATION_ZERO) then
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inst_cnt <= 10;
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inst_cnt <= 11;
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else
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inst_stage_next <= SET_WRITER_BITMAP;
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inst_cnt_next <= 0;
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end if;
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-- Ignore Deadline 1/2
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when 10 =>
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if (TIME_BASED_FILTER_QOS /= DURATION_ZERO) then
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inst_write_data <= inst_latch_data.deadline(0);
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end if;
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-- Ignore Deadline 1/2
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when 11 =>
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if (TIME_BASED_FILTER_QOS /= DURATION_ZERO) then
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inst_write_data <= inst_latch_data.deadline(1);
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inst_write_data <= inst_latch_data.deadline(0);
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inst_wen <= '1';
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end if;
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-- Ignore Deadline 1/2
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when 12 =>
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if (TIME_BASED_FILTER_QOS /= DURATION_ZERO) then
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inst_write_data <= inst_latch_data.deadline(1);
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inst_wen <= '1';
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inst_stage_next <= SET_WRITER_BITMAP;
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inst_cnt_next <= 0;
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inst_stage_next <= SET_WRITER_BITMAP;
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inst_cnt_next <= 0;
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end if;
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when others =>
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null;
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