diff --git a/src/IDL-VHDL_Ref.txt b/src/IDL-VHDL_Ref.txt index b796c10..2c5c4b9 100644 --- a/src/IDL-VHDL_Ref.txt +++ b/src/IDL-VHDL_Ref.txt @@ -261,6 +261,9 @@ SEQUENCE/MAP ------------ In case the nested collection is a sequence/map, a _len_mem memory is again needed for storing the individual sequence lengths, similar to the reader_interface. +The _len signal is split into 2 signals named _len_r and +_len_w and connected to the _len_mem_data_out and +_len_mem_data_in memory signals (similar to the _r and _w ports described above). The memory signal connections are similar to the normal write_interface collection case, allowing the length to be stored when a write to the outer collection happens. The WRITE__LENGTH stage has to be implemented, similar to the normal collection diff --git a/src/ros2/Tests/Fibonacci.vhd b/src/ros2/Tests/Fibonacci.vhd index dee5acf..128206d 100644 --- a/src/ros2/Tests/Fibonacci.vhd +++ b/src/ros2/Tests/Fibonacci.vhd @@ -49,7 +49,8 @@ entity Fibonacci is result_wen : out std_logic; result_valid : in std_logic; result_ack : out std_logic; - result_seq_len : out std_logic_vector(R_RR_SEQ_ADDR_WIDTH-1 downto 0); + result_seq_len_r : in std_logic_vector(R_RR_SEQ_ADDR_WIDTH-1 downto 0); + result_seq_len_w : out std_logic_vector(R_RR_SEQ_ADDR_WIDTH-1 downto 0); result_seq_addr : out std_logic_vector(R_RR_SEQ_ADDR_WIDTH-1 downto 0); result_seq_ready : in std_logic; result_seq_ren : out std_logic; @@ -91,7 +92,7 @@ begin result_ren <= '0'; result_ack <= '0'; feedback_seq_len <= std_logic_vector(i); - result_seq_len <= std_logic_vector(i); + result_seq_len_w <= std_logic_vector(i); main_prc : process(all) begin diff --git a/src/ros2/Tests/Level_1/L1_Fibonacci_ros_action_test1.vhd b/src/ros2/Tests/Level_1/L1_Fibonacci_ros_action_test1.vhd index 24bffe7..2ab85a4 100644 --- a/src/ros2/Tests/Level_1/L1_Fibonacci_ros_action_test1.vhd +++ b/src/ros2/Tests/Level_1/L1_Fibonacci_ros_action_test1.vhd @@ -59,7 +59,7 @@ architecture testbench of L1_Fibonacci_ros_action_test1 is signal return_code_c, return_code_s : std_logic_vector(ROS_RETCODE_WIDTH-1 downto 0) := (others => '0'); -- ###GENERATED START### signal goal_order_c, new_goal_order_s : std_logic_vector(CDR_LONG_WIDTH-1 downto 0) := (others => '0'); - signal result_seq_len_c, result_seq_len_s, result_seq_addr_c, result_seq_addr_s : std_logic_vector(R_RR_SEQ_ADDR_WIDTH-1 downto 0) := (others => '0'); + signal result_seq_len_c, result_seq_len_w_s, result_seq_len_r_s, result_seq_addr_c, result_seq_addr_s : std_logic_vector(R_RR_SEQ_ADDR_WIDTH-1 downto 0) := (others => '0'); signal result_seq_ready_c, result_seq_ready_s, result_seq_ren_c, result_seq_ren_s, result_seq_wen_s, result_seq_valid_c, result_seq_valid_s, result_seq_ack_c, result_seq_ack_s : std_logic := '0'; signal result_seq_c, result_seq_r_s, result_seq_w_s : std_logic_vector(CDR_LONG_WIDTH-1 downto 0) := (others => '0'); signal feedback_seq_len_c, feedback_seq_len_s, feedback_seq_addr_c, feedback_seq_addr_s : std_logic_vector(F_SEQ_ADDR_WIDTH-1 downto 0) := (others => '0'); @@ -461,7 +461,8 @@ begin result_valid => result_valid_s, result_ack => result_ack_s, -- ###GENERATED START### - result_seq_len => result_seq_len_s, + result_seq_len_r => result_seq_len_r_s, + result_seq_len_w => result_seq_len_w_s, result_seq_addr => result_seq_addr_s, result_seq_ready => result_seq_ready_s, result_seq_ren => result_seq_ren_s, @@ -683,7 +684,7 @@ begin Log("SERVER: Set RESULT (Goal " & integer'image(j) & ")", INFO); result_addr_s <= int(j,result_addr_s'length); for i in 0 to RV.RandInt(1,10) loop - result_seq_len_s <= int(i+1,result_seq_len_s'length); + result_seq_len_w_s <= int(i+1,result_seq_len_w_s'length); result_seq_addr_s <= int(i,result_seq_addr_s'length); result_seq_w_s <= RV.RandSlv(result_seq_w_s'length); wait_on_sig(result_seq_ready_s); @@ -705,7 +706,7 @@ begin client_op(TAKE_RESULT_RESPONSE,ROS_RET_OK); AlertIf(to_unsigned(SEQUENCENUMBER_TYPE(service_info_c.request_id.sequence_number)) /= unsigned(sid(j)), "Request ID incorrect", FAILURE); AffirmIfEqual(RESULT, result_status_c, GoalStatus_package.STATUS_SUCCEEDED); - AffirmIfEqual(RESULT, result_seq_len_c, result_seq_len_s); + AffirmIfEqual(RESULT, result_seq_len_c, result_seq_len_w_s); for i in 0 to to_integer(unsigned(result_seq_len_c))-1 loop result_seq_addr_s <= int(i,result_seq_addr_s'length); result_seq_addr_c <= int(i,result_seq_addr_c'length); diff --git a/src/ros2/Tests/Level_1/L1_Fibonacci_ros_action_test2.vhd b/src/ros2/Tests/Level_1/L1_Fibonacci_ros_action_test2.vhd index 8395386..6758006 100644 --- a/src/ros2/Tests/Level_1/L1_Fibonacci_ros_action_test2.vhd +++ b/src/ros2/Tests/Level_1/L1_Fibonacci_ros_action_test2.vhd @@ -59,7 +59,7 @@ architecture testbench of L1_Fibonacci_ros_action_test2 is signal return_code_c, return_code_s : std_logic_vector(ROS_RETCODE_WIDTH-1 downto 0) := (others => '0'); -- ###GENERATED START### signal goal_order_c, new_goal_order_s : std_logic_vector(CDR_LONG_WIDTH-1 downto 0) := (others => '0'); - signal result_seq_len_c, result_seq_len_s, result_seq_addr_c, result_seq_addr_s : std_logic_vector(R_RR_SEQ_ADDR_WIDTH-1 downto 0) := (others => '0'); + signal result_seq_len_c, result_seq_len_r_s, result_seq_len_w_s, result_seq_addr_c, result_seq_addr_s : std_logic_vector(R_RR_SEQ_ADDR_WIDTH-1 downto 0) := (others => '0'); signal result_seq_ready_c, result_seq_ready_s, result_seq_ren_c, result_seq_ren_s, result_seq_wen_s, result_seq_valid_c, result_seq_valid_s, result_seq_ack_c, result_seq_ack_s : std_logic := '0'; signal result_seq_c, result_seq_r_s, result_seq_w_s : std_logic_vector(CDR_LONG_WIDTH-1 downto 0) := (others => '0'); signal feedback_seq_len_c, feedback_seq_len_s, feedback_seq_addr_c, feedback_seq_addr_s : std_logic_vector(F_SEQ_ADDR_WIDTH-1 downto 0) := (others => '0'); @@ -465,7 +465,8 @@ begin result_valid => result_valid_s, result_ack => result_ack_s, -- ###GENERATED START### - result_seq_len => result_seq_len_s, + result_seq_len_r => result_seq_len_r_s, + result_seq_len_w => result_seq_len_w_s, result_seq_addr => result_seq_addr_s, result_seq_ready => result_seq_ready_s, result_seq_ren => result_seq_ren_s, @@ -654,7 +655,7 @@ begin Log("SERVER: Set RESULT (Goal " & integer'image(j) & ")", INFO); result_addr_s <= int(j,result_addr_s'length); for i in 0 to RV.RandInt(1,10) loop - result_seq_len_s <= int(i+1,result_seq_len_s'length); + result_seq_len_w_s <= int(i+1,result_seq_len_w_s'length); result_seq_addr_s <= int(i,result_seq_addr_s'length); result_seq_w_s <= RV.RandSlv(result_seq_w_s'length); wait_on_sig(result_seq_ready_s); @@ -676,7 +677,7 @@ begin client_op(TAKE_RESULT_RESPONSE,ROS_RET_OK); AlertIf(to_unsigned(SEQUENCENUMBER_TYPE(service_info_c.request_id.sequence_number)) /= unsigned(sid(j)), "Request ID incorrect", FAILURE); AffirmIfEqual(RESULT, result_status_c, GoalStatus_package.STATUS_SUCCEEDED); - AffirmIfEqual(RESULT, result_seq_len_c, result_seq_len_s); + AffirmIfEqual(RESULT, result_seq_len_c, result_seq_len_w_s); for i in 0 to to_integer(unsigned(result_seq_len_c))-1 loop result_seq_addr_s <= int(i,result_seq_addr_s'length); result_seq_addr_c <= int(i,result_seq_addr_c'length); diff --git a/src/ros2/Tests/Level_2/L2_Testbench_ROS_Lib4.vhd b/src/ros2/Tests/Level_2/L2_Testbench_ROS_Lib4.vhd index 57d8d6d..f23ffa8 100644 --- a/src/ros2/Tests/Level_2/L2_Testbench_ROS_Lib4.vhd +++ b/src/ros2/Tests/Level_2/L2_Testbench_ROS_Lib4.vhd @@ -95,7 +95,7 @@ architecture arch of L2_Testbench_ROS_Lib4 is signal goal_stamp_s : ROS_TIME_TYPE; signal new_goal_request_s, new_goal_accepted_s, new_goal_response_s, cancel_request_s, cancel_accepted_s, cancel_response_s, result_ready_s, result_ren_s, result_wen_s, result_valid_s, result_ack_s : std_logic; signal new_goal_order_s : std_logic_vector(CDR_LONG_WIDTH-1 downto 0); - signal result_seq_len_s, result_seq_addr_s : std_logic_vector(R_RR_SEQ_ADDR_WIDTH-1 downto 0); + signal result_seq_len_r_s, result_seq_len_w_s, result_seq_addr_s : std_logic_vector(R_RR_SEQ_ADDR_WIDTH-1 downto 0); signal result_seq_ready_s, result_seq_ren_s, result_seq_wen_s, result_seq_valid_s, result_seq_ack_s : std_logic; signal result_seq_r_s, result_seq_w_s : std_logic_vector(CDR_LONG_WIDTH-1 downto 0); signal feedback_seq_len_s, feedback_seq_addr_s : std_logic_vector(F_SEQ_ADDR_WIDTH-1 downto 0); @@ -885,7 +885,8 @@ begin result_wen => result_wen_s, result_valid => result_valid_s, result_ack => result_ack_s, - result_seq_len => result_seq_len_s, + result_seq_len_r => result_seq_len_r_s, + result_seq_len_w => result_seq_len_w_s, result_seq_addr => result_seq_addr_s, result_seq_ready => result_seq_ready_s, result_seq_ren => result_seq_ren_s, @@ -939,7 +940,8 @@ begin result_wen => result_wen_s, result_valid => result_valid_s, result_ack => result_ack_s, - result_seq_len => result_seq_len_s, + result_seq_len_r => result_seq_len_r_s, + result_seq_len_w => result_seq_len_w_s, result_seq_addr => result_seq_addr_s, result_seq_ready => result_seq_ready_s, result_seq_ren => result_seq_ren_s, diff --git a/src/ros2/example_interfaces/Fibonacci_ros_action_server.vhd b/src/ros2/example_interfaces/Fibonacci_ros_action_server.vhd index 8030abe..1e408a7 100644 --- a/src/ros2/example_interfaces/Fibonacci_ros_action_server.vhd +++ b/src/ros2/example_interfaces/Fibonacci_ros_action_server.vhd @@ -222,7 +222,8 @@ entity Fibonacci_ros_action_server is result_valid : out std_logic; result_ack : in std_logic; -- ###GENERATED START### - result_seq_len : in std_logic_vector(R_RR_SEQ_ADDR_WIDTH-1 downto 0); + result_seq_len_r : out std_logic_vector(R_RR_SEQ_ADDR_WIDTH-1 downto 0); + result_seq_len_w : in std_logic_vector(R_RR_SEQ_ADDR_WIDTH-1 downto 0); result_seq_addr : in std_logic_vector(R_RR_SEQ_ADDR_WIDTH-1 downto 0); result_seq_ready : out std_logic; result_seq_ren : in std_logic; @@ -774,7 +775,8 @@ begin -- ###GENERATED START### result_valid <= r_seq_len_mem_valid_out; - r_seq_len_mem_data_in <= result_seq_len; + r_seq_len_mem_data_in <= result_seq_len_w; + result_seq_len_r <= r_seq_len_mem_data_out; result_seq_valid <= r_seq_mem_valid_out(to_integer(unsigned(result_addr))); result_seq_r <= r_seq_mem_data_out(to_integer(unsigned(result_addr))); r_seq_mem_data_in <= (others => result_seq_w);