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Change latching behaviour of "last_word_in" latches

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During testing a scenario arose, where a toggling in the last_word
signal lane while the rest of the signals were not valid was falsely
latched.
All entities with "last_word_in" latches were modifies to only latch
the signal when in valid state.
This commit is contained in:
John Ring 2023-06-22 08:18:23 +02:00
parent 35baf341c7
commit d2c0b37c27
27 changed files with 273 additions and 273 deletions
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14
src/TEMPLATE_key_holder.vhd
View File

@ -135,7 +135,7 @@ begin
-- ###GENERATED END###
-- Last Word Latch Setter
if (last_word_in = '1') then
if (last_word_in = '1' and valid_in = '1') then
last_word_in_latch_next <= '1';
end if;
@ -200,7 +200,7 @@ begin
when CDR_BE =>
endian_flag_next <= '0';
stage_next <= FETCH;
-- Alignment Reset
-- Alignment Reset
align_offset_next <= (others => '0');
if (opcode_latch = PUSH_DATA) then
-- ###GENERATED START###
@ -215,7 +215,7 @@ begin
when CDR_LE =>
endian_flag_next <= '1';
stage_next <= FETCH;
-- Alignment Reset
-- Alignment Reset
align_offset_next <= (others => '0');
if (opcode_latch = PUSH_DATA) then
-- ###GENERATED START###
@ -291,7 +291,7 @@ begin
stage_next <= FETCH;
decode_stage_next <= return_stage;
cnt_next <= 0;
-- Alignment Reset
-- Alignment Reset
align_offset_next <= (others => '0');
-- Optional omitted
@ -301,7 +301,7 @@ begin
optional_next <= '1';
end if;
end if;
-- eMemberHeader
-- eMemberHeader
when 1 =>
-- Ignore Parameter ID
cnt_next <= cnt + 1;
@ -311,7 +311,7 @@ begin
stage_next <= FETCH;
decode_stage_next <= return_stage;
cnt_next <= 0;
-- Alignment Reset
-- Alignment Reset
align_offset_next <= (others => '0');
-- Optional omitted
@ -337,7 +337,7 @@ begin
-- Output Guard
if (ready_out = '1') then
stage_next <= ENCODE_PAYLOAD;
-- Reset
-- Reset
align_offset_next <= (others => '0');
data_out_latch_next <= (others => '0');
-- ###GENERATED START###

12
src/TEMPLATE_reader_interface.vhd
View File

@ -161,7 +161,7 @@ begin
-- ###GENERATED END###
-- Last Word Latch Setter
if (last_word_in_dds = '1') then
if (last_word_in_dds = '1' and valid_in_dds = '1') then
last_word_in_latch_next <= '1';
end if;
@ -193,7 +193,7 @@ begin
when CDR_BE =>
endian_flag_next <= '0';
stage_next <= FETCH;
-- Alignment Reset
-- Alignment Reset
align_offset_next <= (others => '0');
-- ###GENERATED START###
decode_stage_next <= TODO;
@ -202,7 +202,7 @@ begin
when CDR_LE =>
endian_flag_next <= '1';
stage_next <= FETCH;
-- Alignment Reset
-- Alignment Reset
align_offset_next <= (others => '0');
-- ###GENERATED START###
decode_stage_next <= TODO;
@ -277,7 +277,7 @@ begin
stage_next <= FETCH;
decode_stage_next <= return_stage;
cnt_next <= 0;
-- Alignment Reset
-- Alignment Reset
align_offset_next <= (others => '0');
-- Optional omitted
@ -287,7 +287,7 @@ begin
optional_next <= '1';
end if;
end if;
-- eMemberHeader
-- eMemberHeader
when 1 =>
-- Ignore Parameter ID
cnt_next <= cnt + 1;
@ -297,7 +297,7 @@ begin
stage_next <= FETCH;
decode_stage_next <= return_stage;
cnt_next <= 0;
-- Alignment Reset
-- Alignment Reset
align_offset_next <= (others => '0');
-- Optional omitted

14
src/Tests/Type1_key_holder.vhd
View File

@ -131,7 +131,7 @@ begin
-- ###GENERATED END###
-- Last Word Latch Setter
if (last_word_in = '1') then
if (last_word_in = '1' and valid_in = '1') then
last_word_in_latch_next <= '1';
end if;
@ -196,7 +196,7 @@ begin
when CDR_BE =>
endian_flag_next <= '0';
stage_next <= FETCH;
-- Alignment Reset
-- Alignment Reset
align_offset_next <= (others => '0');
if (opcode_latch = PUSH_DATA) then
-- ###GENERATED START###
@ -211,7 +211,7 @@ begin
when CDR_LE =>
endian_flag_next <= '1';
stage_next <= FETCH;
-- Alignment Reset
-- Alignment Reset
align_offset_next <= (others => '0');
if (opcode_latch = PUSH_DATA) then
-- ###GENERATED START###
@ -298,7 +298,7 @@ begin
stage_next <= FETCH;
decode_stage_next <= return_stage;
cnt_next <= 0;
-- Alignment Reset
-- Alignment Reset
align_offset_next <= (others => '0');
-- Optional omitted
@ -308,7 +308,7 @@ begin
optional_next <= '1';
end if;
end if;
-- eMemberHeader
-- eMemberHeader
when 1 =>
-- Ignore Parameter ID
cnt_next <= cnt + 1;
@ -318,7 +318,7 @@ begin
stage_next <= FETCH;
decode_stage_next <= return_stage;
cnt_next <= 0;
-- Alignment Reset
-- Alignment Reset
align_offset_next <= (others => '0');
-- Optional omitted
@ -344,7 +344,7 @@ begin
-- Output Guard
if (ready_out = '1') then
stage_next <= ENCODE_PAYLOAD;
-- Reset
-- Reset
align_offset_next <= (others => '0');
data_out_latch_next <= (others => '0');
-- ###GENERATED START###

12
src/Tests/Type1_reader_interface.vhd
View File

@ -161,7 +161,7 @@ begin
-- ###GENERATED END###
-- Last Word Latch Setter
if (last_word_in_dds = '1') then
if (last_word_in_dds = '1' and valid_in_dds = '1') then
last_word_in_latch_next <= '1';
end if;
@ -190,7 +190,7 @@ begin
when CDR_BE =>
endian_flag_next <= '0';
stage_next <= FETCH;
-- Alignment Reset
-- Alignment Reset
align_offset_next <= (others => '0');
-- ###GENERATED START###
decode_stage_next <= GET_ID;
@ -199,7 +199,7 @@ begin
when CDR_LE =>
endian_flag_next <= '1';
stage_next <= FETCH;
-- Alignment Reset
-- Alignment Reset
align_offset_next <= (others => '0');
-- ###GENERATED START###
decode_stage_next <= GET_ID;
@ -297,7 +297,7 @@ begin
stage_next <= FETCH;
decode_stage_next <= return_stage;
cnt_next <= 0;
-- Alignment Reset
-- Alignment Reset
align_offset_next <= (others => '0');
-- Optional omitted
@ -307,7 +307,7 @@ begin
optional_next <= '1';
end if;
end if;
-- eMemberHeader
-- eMemberHeader
when 1 =>
-- Ignore Parameter ID
cnt_next <= cnt + 1;
@ -317,7 +317,7 @@ begin
stage_next <= FETCH;
decode_stage_next <= return_stage;
cnt_next <= 0;
-- Alignment Reset
-- Alignment Reset
align_offset_next <= (others => '0');
-- Optional omitted

20
src/Tests/Type2_key_holder.vhd
View File

@ -173,7 +173,7 @@ begin
-- ###GENERATED END###
-- Last Word Latch Setter
if (last_word_in = '1') then
if (last_word_in = '1' and valid_in = '1') then
last_word_in_latch_next <= '1';
end if;
@ -238,7 +238,7 @@ begin
when CDR_BE =>
endian_flag_next <= '0';
stage_next <= FETCH;
-- Alignment Reset
-- Alignment Reset
align_offset_next <= (others => '0');
if (opcode_latch = PUSH_DATA) then
-- ###GENERATED START###
@ -253,7 +253,7 @@ begin
when CDR_LE =>
endian_flag_next <= '1';
stage_next <= FETCH;
-- Alignment Reset
-- Alignment Reset
align_offset_next <= (others => '0');
if (opcode_latch = PUSH_DATA) then
-- ###GENERATED START###
@ -354,7 +354,7 @@ begin
if (not check_align(align_offset, ALIGN_1)) then
target_align_next <= ALIGN_1;
stage_next <= ALIGN_IN_STREAM;
else
else
TestSequence_TestArray_mem_addr(TestSequence_cnt) <= std_logic_vector(to_unsigned(TestSequence_TestArray_cnt,TESTSEQUENCE_TESTARRAY_ADDR_WIDTH));
TestSequence_TestArray_mem_data_in(TestSequence_cnt) <= endian_swap(endian_flag, get_sub_vector(data_in_latch, to_integer(align_offset(1 downto 0)), CDR_OCTET_WIDTH, TRUE));
TestSequence_TestArray_mem_valid_in(TestSequence_cnt) <= '1';
@ -514,7 +514,7 @@ begin
stage_next <= FETCH;
decode_stage_next <= return_stage;
cnt_next <= 0;
-- Alignment Reset
-- Alignment Reset
align_offset_next <= (others => '0');
-- Optional omitted
@ -524,7 +524,7 @@ begin
optional_next <= '1';
end if;
end if;
-- eMemberHeader
-- eMemberHeader
when 1 =>
-- Ignore Parameter ID
cnt_next <= cnt + 1;
@ -534,7 +534,7 @@ begin
stage_next <= FETCH;
decode_stage_next <= return_stage;
cnt_next <= 0;
-- Alignment Reset
-- Alignment Reset
align_offset_next <= (others => '0');
-- Optional omitted
@ -560,7 +560,7 @@ begin
-- Output Guard
if (ready_out = '1') then
stage_next <= ENCODE_PAYLOAD;
-- Reset
-- Reset
align_offset_next <= (others => '0');
data_out_latch_next <= (others => '0');
-- ###GENERATED START###
@ -685,7 +685,7 @@ begin
if (not check_align(align_offset, ALIGN_1)) then
target_align_next <= ALIGN_1;
stage_next <= ALIGN_OUT_STREAM;
else
else
case (cnt) is
-- GET
when 0 =>
@ -728,7 +728,7 @@ begin
stage_next <= PUSH;
end if;
end if;
when others =>
when others =>
end case;
end if;
-- ###GENERATED END###

18
src/Tests/Type2_reader_interface.vhd
View File

@ -490,7 +490,7 @@ begin
-- ###GENERATED END###
-- Last Word Latch Setter
if (last_word_in_dds = '1') then
if (last_word_in_dds = '1' and valid_in_dds = '1') then
last_word_in_latch_next <= '1';
end if;
@ -557,7 +557,7 @@ begin
when CDR_BE =>
endian_flag_next <= '0';
stage_next <= FETCH;
-- Alignment Reset
-- Alignment Reset
align_offset_next <= (others => '0');
-- ###GENERATED START###
decode_stage_next <= GET_ID;
@ -566,7 +566,7 @@ begin
when CDR_LE =>
endian_flag_next <= '1';
stage_next <= FETCH;
-- Alignment Reset
-- Alignment Reset
align_offset_next <= (others => '0');
-- ###GENERATED START###
decode_stage_next <= GET_ID;
@ -665,7 +665,7 @@ begin
if (not check_align(align_offset, ALIGN_1)) then
target_align_next <= ALIGN_1;
stage_next <= ALIGN_STREAM;
else
else
TestSequence_TestArray_mem_addr(TestSequence_cnt) <= std_logic_vector(to_unsigned(TestSequence_TestArray_cnt,TESTSEQUENCE_TESTARRAY_ADDR_WIDTH));
TestSequence_TestArray_mem_data_in(TestSequence_cnt) <= endian_swap(endian_flag, get_sub_vector(data_in_latch, to_integer(align_offset(1 downto 0)), CDR_OCTET_WIDTH, TRUE));
TestSequence_TestArray_mem_valid_in(TestSequence_cnt) <= '1';
@ -925,7 +925,7 @@ begin
if(align_offset(1 downto 0) = "11") then
stage_next <= FETCH;
end if;
end if;
end if;
when GET_TESTUNION_D =>
-- Optional Omitted
if (optional = '0') then
@ -1026,7 +1026,7 @@ begin
if (not check_align(align_offset, ALIGN_1)) then
target_align_next <= ALIGN_1;
stage_next <= ALIGN_STREAM;
else
else
TestString_mem_addr <= std_logic_vector(to_unsigned(TestString_cnt,TESTSTRING_ADDR_WIDTH));
TestString_mem_data_in <= endian_swap(endian_flag, get_sub_vector(data_in_latch, to_integer(align_offset(1 downto 0)), CDR_CHAR_WIDTH, TRUE));
TestString_mem_valid_in <= '1';
@ -1066,7 +1066,7 @@ begin
stage_next <= FETCH;
decode_stage_next <= return_stage;
cnt_next <= 0;
-- Alignment Reset
-- Alignment Reset
align_offset_next <= (others => '0');
-- Optional omitted
@ -1076,7 +1076,7 @@ begin
optional_next <= '1';
end if;
end if;
-- eMemberHeader
-- eMemberHeader
when 1 =>
-- Ignore Parameter ID
cnt_next <= cnt + 1;
@ -1086,7 +1086,7 @@ begin
stage_next <= FETCH;
decode_stage_next <= return_stage;
cnt_next <= 0;
-- Alignment Reset
-- Alignment Reset
align_offset_next <= (others => '0');
-- Optional omitted

2
src/key_holder.vhd
View File

@ -28,7 +28,7 @@ entity key_holder is
data_in : in std_logic_vector(WORD_WIDTH-1 downto 0);
last_word_in : in std_logic;
-- OUTPUT
ready_out : in std_logic;
ready_out : in std_logic;
valid_out : out std_logic;
data_out : out std_logic_vector(WORD_WIDTH-1 downto 0);
last_word_out : out std_logic

20
src/ros2/TEMPLATE_ros_action_goal_srv_client.vhd
View File

@ -201,7 +201,7 @@ begin
-- ###GENERATED END###
-- Last Word Latch Setter
if (last_word_in_r = '1') then
if (last_word_in_r = '1' and valid_in_r = '1') then
last_word_in_latch_next <= '1';
end if;
-- Data Available Setter
@ -289,7 +289,7 @@ begin
when CDR_BE =>
endian_flag_next <= '0';
stage_next <= FETCH;
-- Alignment Reset
-- Alignment Reset
align_offset_next <= (others => '0');
decode_stage_next <= GET_RID_WGUID;
cnt_next <= 0;
@ -297,7 +297,7 @@ begin
when CDR_LE =>
endian_flag_next <= '1';
stage_next <= FETCH;
-- Alignment Reset
-- Alignment Reset
align_offset_next <= (others => '0');
decode_stage_next <= GET_RID_WGUID;
cnt_next <= 0;
@ -462,7 +462,7 @@ begin
stage_next <= FETCH;
decode_stage_next <= return_stage;
cnt_next <= 0;
-- Alignment Reset
-- Alignment Reset
align_offset_next <= (others => '0');
-- Optional omitted
@ -472,7 +472,7 @@ begin
optional_next <= '1';
end if;
end if;
-- eMemberHeader
-- eMemberHeader
when 1 =>
-- Ignore Parameter ID
cnt_next <= cnt + 1;
@ -482,7 +482,7 @@ begin
stage_next <= FETCH;
decode_stage_next <= return_stage;
cnt_next <= 0;
-- Alignment Reset
-- Alignment Reset
align_offset_next <= (others => '0');
-- Optional omitted
@ -534,7 +534,7 @@ begin
-- Output Guard
if (ready_out_w = '1') then
stage_next <= ENCODE_PAYLOAD;
-- Reset
-- Reset
align_offset_next <= (others => '0');
data_out_latch_next <= (others => '0');
encode_stage_next <= WRITE_RID_WGUID;
@ -597,7 +597,7 @@ begin
align_offset_next <= align_offset + 8;
encode_stage_next <= WRITE_RID_SN;
cnt_next <= 0;
when others =>
when others =>
end case;
end if;
when WRITE_RID_SN =>
@ -616,7 +616,7 @@ begin
stage_next <= PUSH;
align_offset_next <= align_offset + 8;
encode_stage_next <= WRITE_RQ_GOAL_ID;
when others =>
when others =>
end case;
end if;
when WRITE_RQ_GOAL_ID =>
@ -698,7 +698,7 @@ begin
sequence_id_sig <= (others => '0');
return_code_latch <= ROS_RET_OK;
service_info_sig <= EMPTY_SERVICE_INFO;
uuid_cnt <= 0;
uuid_cnt <= 0;
accepted_latch <= '0';
stamp_latch <= (others => '0');
-- ###GENERATED START###

22
src/ros2/TEMPLATE_ros_action_goal_srv_server.vhd
View File

@ -197,7 +197,7 @@ begin
-- ###GENERATED END###
-- Last Word Latch Setter
if (last_word_in_r = '1') then
if (last_word_in_r = '1' and valid_in_r = '1') then
last_word_in_latch_next <= '1';
end if;
-- Data Available Setter
@ -283,7 +283,7 @@ begin
when CDR_BE =>
endian_flag_next <= '0';
stage_next <= FETCH;
-- Alignment Reset
-- Alignment Reset
align_offset_next <= (others => '0');
decode_stage_next <= GET_RID_WGUID;
cnt_next <= 0;
@ -291,7 +291,7 @@ begin
when CDR_LE =>
endian_flag_next <= '1';
stage_next <= FETCH;
-- Alignment Reset
-- Alignment Reset
align_offset_next <= (others => '0');
decode_stage_next <= GET_RID_WGUID;
cnt_next <= 0;
@ -401,7 +401,7 @@ begin
if (not check_align(align_offset, ALIGN_1)) then
target_align_next <= ALIGN_1;
stage_next <= ALIGN_IN_STREAM;
else
else
goal_id_latch_next <= write_sub_vector(goal_id_latch, get_sub_vector(data_in_latch, to_integer(align_offset(1 downto 0)), CDR_INT8_WIDTH, TRUE), uuid_cnt, TRUE);
align_offset_next <= align_offset + 1;
@ -440,7 +440,7 @@ begin
stage_next <= FETCH;
decode_stage_next <= return_stage;
cnt_next <= 0;
-- Alignment Reset
-- Alignment Reset
align_offset_next <= (others => '0');
-- Optional omitted
@ -450,7 +450,7 @@ begin
optional_next <= '1';
end if;
end if;
-- eMemberHeader
-- eMemberHeader
when 1 =>
-- Ignore Parameter ID
cnt_next <= cnt + 1;
@ -460,7 +460,7 @@ begin
stage_next <= FETCH;
decode_stage_next <= return_stage;
cnt_next <= 0;
-- Alignment Reset
-- Alignment Reset
align_offset_next <= (others => '0');
-- Optional omitted
@ -512,7 +512,7 @@ begin
-- Output Guard
if (ready_out_w = '1') then
stage_next <= ENCODE_PAYLOAD;
-- Reset
-- Reset
align_offset_next <= (others => '0');
data_out_latch_next <= (others => '0');
encode_stage_next <= WRITE_RID_WGUID;
@ -575,7 +575,7 @@ begin
align_offset_next <= align_offset + 8;
encode_stage_next <= WRITE_RID_SN;
cnt_next <= 0;
when others =>
when others =>
end case;
end if;
when WRITE_RID_SN =>
@ -594,7 +594,7 @@ begin
stage_next <= PUSH;
align_offset_next <= align_offset + 8;
encode_stage_next <= WRITE_RR_ACCEPTED;
when others =>
when others =>
end case;
end if;
when WRITE_RR_ACCEPTED =>
@ -635,7 +635,7 @@ begin
-- DONE
stage_next <= PUSH;
finalize_payload_next <= '1';
when others =>
when others =>
end case;
end if;
when others =>

18
src/ros2/TEMPLATE_ros_action_result_srv_client.vhd
View File

@ -197,7 +197,7 @@ begin
-- ###GENERATED END###
-- Last Word Latch Setter
if (last_word_in_r = '1') then
if (last_word_in_r = '1' and valid_in_r = '1') then
last_word_in_latch_next <= '1';
end if;
-- Data Available Setter
@ -285,7 +285,7 @@ begin
when CDR_BE =>
endian_flag_next <= '0';
stage_next <= FETCH;
-- Alignment Reset
-- Alignment Reset
align_offset_next <= (others => '0');
decode_stage_next <= GET_RID_WGUID;
cnt_next <= 0;
@ -293,7 +293,7 @@ begin
when CDR_LE =>
endian_flag_next <= '1';
stage_next <= FETCH;
-- Alignment Reset
-- Alignment Reset
align_offset_next <= (others => '0');
decode_stage_next <= GET_RID_WGUID;
cnt_next <= 0;
@ -434,7 +434,7 @@ begin
stage_next <= FETCH;
decode_stage_next <= return_stage;
cnt_next <= 0;
-- Alignment Reset
-- Alignment Reset
align_offset_next <= (others => '0');
-- Optional omitted
@ -444,7 +444,7 @@ begin
optional_next <= '1';
end if;
end if;
-- eMemberHeader
-- eMemberHeader
when 1 =>
-- Ignore Parameter ID
cnt_next <= cnt + 1;
@ -454,7 +454,7 @@ begin
stage_next <= FETCH;
decode_stage_next <= return_stage;
cnt_next <= 0;
-- Alignment Reset
-- Alignment Reset
align_offset_next <= (others => '0');
-- Optional omitted
@ -506,7 +506,7 @@ begin
-- Output Guard
if (ready_out_w = '1') then
stage_next <= ENCODE_PAYLOAD;
-- Reset
-- Reset
align_offset_next <= (others => '0');
data_out_latch_next <= (others => '0');
encode_stage_next <= WRITE_RID_WGUID;
@ -569,7 +569,7 @@ begin
align_offset_next <= align_offset + 8;
encode_stage_next <= WRITE_RID_SN;
cnt_next <= 0;
when others =>
when others =>
end case;
end if;
when WRITE_RID_SN =>
@ -588,7 +588,7 @@ begin
stage_next <= PUSH;
align_offset_next <= align_offset + 8;
encode_stage_next <= WRITE_RQ_GOAL_ID;
when others =>
when others =>
end case;
end if;
when WRITE_RQ_GOAL_ID =>

20
src/ros2/TEMPLATE_ros_action_result_srv_server.vhd
View File

@ -194,7 +194,7 @@ begin
-- ###GENERATED END###
-- Last Word Latch Setter
if (last_word_in_r = '1') then
if (last_word_in_r = '1' and valid_in_r = '1') then
last_word_in_latch_next <= '1';
end if;
-- Data Available Setter
@ -280,7 +280,7 @@ begin
when CDR_BE =>
endian_flag_next <= '0';
stage_next <= FETCH;
-- Alignment Reset
-- Alignment Reset
align_offset_next <= (others => '0');
decode_stage_next <= GET_RID_WGUID;
cnt_next <= 0;
@ -288,7 +288,7 @@ begin
when CDR_LE =>
endian_flag_next <= '1';
stage_next <= FETCH;
-- Alignment Reset
-- Alignment Reset
align_offset_next <= (others => '0');
decode_stage_next <= GET_RID_WGUID;
cnt_next <= 0;
@ -397,7 +397,7 @@ begin
if (not check_align(align_offset, ALIGN_1)) then
target_align_next <= ALIGN_1;
stage_next <= ALIGN_IN_STREAM;
else
else
goal_id_latch_next <= write_sub_vector(goal_id_latch, get_sub_vector(data_in_latch, to_integer(align_offset(1 downto 0)), CDR_INT8_WIDTH, TRUE), uuid_cnt, TRUE);
align_offset_next <= align_offset + 1;
@ -432,7 +432,7 @@ begin
stage_next <= FETCH;
decode_stage_next <= return_stage;
cnt_next <= 0;
-- Alignment Reset
-- Alignment Reset
align_offset_next <= (others => '0');
-- Optional omitted
@ -442,7 +442,7 @@ begin
optional_next <= '1';
end if;
end if;
-- eMemberHeader
-- eMemberHeader
when 1 =>
-- Ignore Parameter ID
cnt_next <= cnt + 1;
@ -452,7 +452,7 @@ begin
stage_next <= FETCH;
decode_stage_next <= return_stage;
cnt_next <= 0;
-- Alignment Reset
-- Alignment Reset
align_offset_next <= (others => '0');
-- Optional omitted
@ -504,7 +504,7 @@ begin
-- Output Guard
if (ready_out_w = '1') then
stage_next <= ENCODE_PAYLOAD;
-- Reset
-- Reset
align_offset_next <= (others => '0');
data_out_latch_next <= (others => '0');
encode_stage_next <= WRITE_RID_WGUID;
@ -567,7 +567,7 @@ begin
align_offset_next <= align_offset + 8;
encode_stage_next <= WRITE_RID_SN;
cnt_next <= 0;
when others =>
when others =>
end case;
end if;
when WRITE_RID_SN =>
@ -586,7 +586,7 @@ begin
stage_next <= PUSH;
align_offset_next <= align_offset + 8;
encode_stage_next <= WRITE_RR_STATUS;
when others =>
when others =>
end case;
end if;
when WRITE_RR_STATUS =>

18
src/ros2/TEMPLATE_ros_srv_client.vhd
View File

@ -193,7 +193,7 @@ begin
-- ###GENERATED END###
-- Last Word Latch Setter
if (last_word_in_r = '1') then
if (last_word_in_r = '1' and valid_in_r = '1') then
last_word_in_latch_next <= '1';
end if;
-- Data Available Setter
@ -281,7 +281,7 @@ begin
when CDR_BE =>
endian_flag_next <= '0';
stage_next <= FETCH;
-- Alignment Reset
-- Alignment Reset
align_offset_next <= (others => '0');
decode_stage_next <= GET_RID_WGUID;
cnt_next <= 0;
@ -289,7 +289,7 @@ begin
when CDR_LE =>
endian_flag_next <= '1';
stage_next <= FETCH;
-- Alignment Reset
-- Alignment Reset
align_offset_next <= (others => '0');
decode_stage_next <= GET_RID_WGUID;
cnt_next <= 0;
@ -414,7 +414,7 @@ begin
stage_next <= FETCH;
decode_stage_next <= return_stage;
cnt_next <= 0;
-- Alignment Reset
-- Alignment Reset
align_offset_next <= (others => '0');
-- Optional omitted
@ -424,7 +424,7 @@ begin
optional_next <= '1';
end if;
end if;
-- eMemberHeader
-- eMemberHeader
when 1 =>
-- Ignore Parameter ID
cnt_next <= cnt + 1;
@ -434,7 +434,7 @@ begin
stage_next <= FETCH;
decode_stage_next <= return_stage;
cnt_next <= 0;
-- Alignment Reset
-- Alignment Reset
align_offset_next <= (others => '0');
-- Optional omitted
@ -486,7 +486,7 @@ begin
-- Output Guard
if (ready_out_w = '1') then
stage_next <= ENCODE_PAYLOAD;
-- Reset
-- Reset
align_offset_next <= (others => '0');
data_out_latch_next <= (others => '0');
encode_stage_next <= WRITE_RID_WGUID;
@ -549,7 +549,7 @@ begin
align_offset_next <= align_offset + 8;
encode_stage_next <= WRITE_RID_SN;
cnt_next <= 0;
when others =>
when others =>
end case;
end if;
when WRITE_RID_SN =>
@ -570,7 +570,7 @@ begin
-- ###GENERATED START###
encode_stage_next <= TODO;
-- ###GENERATED END###
when others =>
when others =>
end case;
end if;
-- ###GENERATED START###

18
src/ros2/TEMPLATE_ros_srv_server.vhd
View File

@ -190,7 +190,7 @@ begin
-- ###GENERATED END###
-- Last Word Latch Setter
if (last_word_in_r = '1') then
if (last_word_in_r = '1' and valid_in_r = '1') then
last_word_in_latch_next <= '1';
end if;
-- Data Available Setter
@ -276,7 +276,7 @@ begin
when CDR_BE =>
endian_flag_next <= '0';
stage_next <= FETCH;
-- Alignment Reset
-- Alignment Reset
align_offset_next <= (others => '0');
decode_stage_next <= GET_RID_WGUID;
cnt_next <= 0;
@ -284,7 +284,7 @@ begin
when CDR_LE =>
endian_flag_next <= '1';
stage_next <= FETCH;
-- Alignment Reset
-- Alignment Reset
align_offset_next <= (others => '0');
decode_stage_next <= GET_RID_WGUID;
cnt_next <= 0;
@ -409,7 +409,7 @@ begin
stage_next <= FETCH;
decode_stage_next <= return_stage;
cnt_next <= 0;
-- Alignment Reset
-- Alignment Reset
align_offset_next <= (others => '0');
-- Optional omitted
@ -419,7 +419,7 @@ begin
optional_next <= '1';
end if;
end if;
-- eMemberHeader
-- eMemberHeader
when 1 =>
-- Ignore Parameter ID
cnt_next <= cnt + 1;
@ -429,7 +429,7 @@ begin
stage_next <= FETCH;
decode_stage_next <= return_stage;
cnt_next <= 0;
-- Alignment Reset
-- Alignment Reset
align_offset_next <= (others => '0');
-- Optional omitted
@ -481,7 +481,7 @@ begin
-- Output Guard
if (ready_out_w = '1') then
stage_next <= ENCODE_PAYLOAD;
-- Reset
-- Reset
align_offset_next <= (others => '0');
data_out_latch_next <= (others => '0');
encode_stage_next <= WRITE_RID_WGUID;
@ -544,7 +544,7 @@ begin
align_offset_next <= align_offset + 8;
encode_stage_next <= WRITE_RID_SN;
cnt_next <= 0;
when others =>
when others =>
end case;
end if;
when WRITE_RID_SN =>
@ -565,7 +565,7 @@ begin
-- ###GENERATED START###
encode_stage_next <= TODO;
-- ###GENERATED END###
when others =>
when others =>
end case;
end if;
-- ###GENERATED START###

12
src/ros2/TEMPLATE_ros_sub.vhd
View File

@ -147,7 +147,7 @@ begin
-- ###GENERATED END###
-- Last Word Latch Setter
if (last_word_in_dds = '1') then
if (last_word_in_dds = '1' and valid_in_dds = '1') then
last_word_in_latch_next <= '1';
end if;
-- Data Available Setter
@ -231,7 +231,7 @@ begin
when CDR_BE =>
endian_flag_next <= '0';
stage_next <= FETCH;
-- Alignment Reset
-- Alignment Reset
align_offset_next <= (others => '0');
-- ###GENERATED START###
decode_stage_next <= TODO;
@ -240,7 +240,7 @@ begin
when CDR_LE =>
endian_flag_next <= '1';
stage_next <= FETCH;
-- Alignment Reset
-- Alignment Reset
align_offset_next <= (others => '0');
-- ###GENERATED START###
decode_stage_next <= TODO;
@ -300,7 +300,7 @@ begin
stage_next <= FETCH;
decode_stage_next <= return_stage;
cnt_next <= 0;
-- Alignment Reset
-- Alignment Reset
align_offset_next <= (others => '0');
-- Optional omitted
@ -310,7 +310,7 @@ begin
optional_next <= '1';
end if;
end if;
-- eMemberHeader
-- eMemberHeader
when 1 =>
-- Ignore Parameter ID
cnt_next <= cnt + 1;
@ -320,7 +320,7 @@ begin
stage_next <= FETCH;
decode_stage_next <= return_stage;
cnt_next <= 0;
-- Alignment Reset
-- Alignment Reset
align_offset_next <= (others => '0');
-- Optional omitted

22
src/ros2/example_interfaces/AddTwoInts_ros_srv_client.vhd
View File

@ -190,7 +190,7 @@ begin
-- ###GENERATED END###
-- Last Word Latch Setter
if (last_word_in_r = '1') then
if (last_word_in_r = '1' and valid_in_r = '1') then
last_word_in_latch_next <= '1';
end if;
-- Data Available Setter
@ -278,7 +278,7 @@ begin
when CDR_BE =>
endian_flag_next <= '0';
stage_next <= FETCH;
-- Alignment Reset
-- Alignment Reset
align_offset_next <= (others => '0');
decode_stage_next <= GET_RID_WGUID;
cnt_next <= 0;
@ -286,7 +286,7 @@ begin
when CDR_LE =>
endian_flag_next <= '1';
stage_next <= FETCH;
-- Alignment Reset
-- Alignment Reset
align_offset_next <= (others => '0');
decode_stage_next <= GET_RID_WGUID;
cnt_next <= 0;
@ -439,7 +439,7 @@ begin
stage_next <= FETCH;
decode_stage_next <= return_stage;
cnt_next <= 0;
-- Alignment Reset
-- Alignment Reset
align_offset_next <= (others => '0');
-- Optional omitted
@ -449,7 +449,7 @@ begin
optional_next <= '1';
end if;
end if;
-- eMemberHeader
-- eMemberHeader
when 1 =>
-- Ignore Parameter ID
cnt_next <= cnt + 1;
@ -459,7 +459,7 @@ begin
stage_next <= FETCH;
decode_stage_next <= return_stage;
cnt_next <= 0;
-- Alignment Reset
-- Alignment Reset
align_offset_next <= (others => '0');
-- Optional omitted
@ -511,7 +511,7 @@ begin
-- Output Guard
if (ready_out_w = '1') then
stage_next <= ENCODE_PAYLOAD;
-- Reset
-- Reset
align_offset_next <= (others => '0');
data_out_latch_next <= (others => '0');
encode_stage_next <= WRITE_RID_WGUID;
@ -574,7 +574,7 @@ begin
align_offset_next <= align_offset + 8;
encode_stage_next <= WRITE_RID_SN;
cnt_next <= 0;
when others =>
when others =>
end case;
end if;
when WRITE_RID_SN =>
@ -596,7 +596,7 @@ begin
encode_stage_next <= WRITE_RQ_A;
cnt_next <= 0;
-- ###GENERATED END###
when others =>
when others =>
end case;
end if;
-- ###GENERATED START###
@ -618,7 +618,7 @@ begin
encode_stage_next <= WRITE_RQ_B;
cnt_next <= 0;
when others =>
when others =>
end case;
end if;
when WRITE_RQ_B =>
@ -639,7 +639,7 @@ begin
-- DONE
finalize_payload_next <= '1';
when others =>
when others =>
end case;
end if;
-- ###GENERATED END###

20
src/ros2/example_interfaces/AddTwoInts_ros_srv_server.vhd
View File

@ -190,7 +190,7 @@ begin
-- ###GENERATED END###
-- Last Word Latch Setter
if (last_word_in_r = '1') then
if (last_word_in_r = '1' and valid_in_r = '1') then
last_word_in_latch_next <= '1';
end if;
-- Data Available Setter
@ -276,7 +276,7 @@ begin
when CDR_BE =>
endian_flag_next <= '0';
stage_next <= FETCH;
-- Alignment Reset
-- Alignment Reset
align_offset_next <= (others => '0');
decode_stage_next <= GET_RID_WGUID;
cnt_next <= 0;
@ -284,7 +284,7 @@ begin
when CDR_LE =>
endian_flag_next <= '1';
stage_next <= FETCH;
-- Alignment Reset
-- Alignment Reset
align_offset_next <= (others => '0');
decode_stage_next <= GET_RID_WGUID;
cnt_next <= 0;
@ -464,7 +464,7 @@ begin
stage_next <= FETCH;
decode_stage_next <= return_stage;
cnt_next <= 0;
-- Alignment Reset
-- Alignment Reset
align_offset_next <= (others => '0');
-- Optional omitted
@ -474,7 +474,7 @@ begin
optional_next <= '1';
end if;
end if;
-- eMemberHeader
-- eMemberHeader
when 1 =>
-- Ignore Parameter ID
cnt_next <= cnt + 1;
@ -484,7 +484,7 @@ begin
stage_next <= FETCH;
decode_stage_next <= return_stage;
cnt_next <= 0;
-- Alignment Reset
-- Alignment Reset
align_offset_next <= (others => '0');
-- Optional omitted
@ -536,7 +536,7 @@ begin
-- Output Guard
if (ready_out_w = '1') then
stage_next <= ENCODE_PAYLOAD;
-- Reset
-- Reset
align_offset_next <= (others => '0');
data_out_latch_next <= (others => '0');
encode_stage_next <= WRITE_RID_WGUID;
@ -599,7 +599,7 @@ begin
align_offset_next <= align_offset + 8;
encode_stage_next <= WRITE_RID_SN;
cnt_next <= 0;
when others =>
when others =>
end case;
end if;
when WRITE_RID_SN =>
@ -621,7 +621,7 @@ begin
encode_stage_next <= WRITE_RR_SUM;
cnt_next <= 0;
-- ###GENERATED END###
when others =>
when others =>
end case;
end if;
-- ###GENERATED START###
@ -643,7 +643,7 @@ begin
-- DONE
finalize_payload_next <= '1';
when others =>
when others =>
end case;
end if;
-- ###GENERATED END###

18
src/ros2/example_interfaces/Fibonacci_ros_action_feedback_sub.vhd
View File

@ -180,7 +180,7 @@ begin
return_code_user <= ROS_RET_OK;
-- ###GENERATED START###
uuid_cnt_next <= uuid_cnt;
goal_id_latch_next <= goal_id_latch;
goal_id_latch_next <= goal_id_latch;
seq_len_latch_next <= seq_len_latch;
seq_cnt_next <= seq_cnt;
seq_mem_addr <= (others => '0');
@ -192,7 +192,7 @@ begin
-- ###GENERATED END###
-- Last Word Latch Setter
if (last_word_in_dds = '1') then
if (last_word_in_dds = '1' and valid_in_dds = '1') then
last_word_in_latch_next <= '1';
end if;
-- Data Available Setter
@ -280,7 +280,7 @@ begin
when CDR_BE =>
endian_flag_next <= '0';
stage_next <= FETCH;
-- Alignment Reset
-- Alignment Reset
align_offset_next <= (others => '0');
-- ###GENERATED START###
decode_stage_next <= GET_GOAL_ID;
@ -289,7 +289,7 @@ begin
when CDR_LE =>
endian_flag_next <= '1';
stage_next <= FETCH;
-- Alignment Reset
-- Alignment Reset
align_offset_next <= (others => '0');
-- ###GENERATED START###
decode_stage_next <= GET_GOAL_ID;
@ -336,7 +336,7 @@ begin
if (not check_align(align_offset, ALIGN_1)) then
target_align_next <= ALIGN_1;
stage_next <= ALIGN_STREAM;
else
else
goal_id_latch_next <= write_sub_vector(goal_id_latch, get_sub_vector(data_in_latch, to_integer(align_offset(1 downto 0)), CDR_INT8_WIDTH, TRUE), uuid_cnt, TRUE);
align_offset_next <= align_offset + 1;
@ -381,7 +381,7 @@ begin
if (not check_align(align_offset, ALIGN_4)) then
target_align_next <= ALIGN_4;
stage_next <= ALIGN_STREAM;
else
else
seq_mem_addr <= std_logic_vector(to_unsigned(seq_cnt,F_SEQ_ADDR_WIDTH));
seq_mem_data_in <= endian_swap(endian_flag, data_in_latch);
seq_mem_valid_in <= '1';
@ -417,7 +417,7 @@ begin
stage_next <= FETCH;
decode_stage_next <= return_stage;
cnt_next <= 0;
-- Alignment Reset
-- Alignment Reset
align_offset_next <= (others => '0');
-- Optional omitted
@ -427,7 +427,7 @@ begin
optional_next <= '1';
end if;
end if;
-- eMemberHeader
-- eMemberHeader
when 1 =>
-- Ignore Parameter ID
cnt_next <= cnt + 1;
@ -437,7 +437,7 @@ begin
stage_next <= FETCH;
decode_stage_next <= return_stage;
cnt_next <= 0;
-- Alignment Reset
-- Alignment Reset
align_offset_next <= (others => '0');
-- Optional omitted

20
src/ros2/example_interfaces/Fibonacci_ros_action_goal_srv_client.vhd
View File

@ -199,7 +199,7 @@ begin
-- ###GENERATED END###
-- Last Word Latch Setter
if (last_word_in_r = '1') then
if (last_word_in_r = '1' and valid_in_r = '1') then
last_word_in_latch_next <= '1';
end if;
-- Data Available Setter
@ -287,7 +287,7 @@ begin
when CDR_BE =>
endian_flag_next <= '0';
stage_next <= FETCH;
-- Alignment Reset
-- Alignment Reset
align_offset_next <= (others => '0');
decode_stage_next <= GET_RID_WGUID;
cnt_next <= 0;
@ -295,7 +295,7 @@ begin
when CDR_LE =>
endian_flag_next <= '1';
stage_next <= FETCH;
-- Alignment Reset
-- Alignment Reset
align_offset_next <= (others => '0');
decode_stage_next <= GET_RID_WGUID;
cnt_next <= 0;
@ -460,7 +460,7 @@ begin
stage_next <= FETCH;
decode_stage_next <= return_stage;
cnt_next <= 0;
-- Alignment Reset
-- Alignment Reset
align_offset_next <= (others => '0');
-- Optional omitted
@ -470,7 +470,7 @@ begin
optional_next <= '1';
end if;
end if;
-- eMemberHeader
-- eMemberHeader
when 1 =>
-- Ignore Parameter ID
cnt_next <= cnt + 1;
@ -480,7 +480,7 @@ begin
stage_next <= FETCH;
decode_stage_next <= return_stage;
cnt_next <= 0;
-- Alignment Reset
-- Alignment Reset
align_offset_next <= (others => '0');
-- Optional omitted
@ -532,7 +532,7 @@ begin
-- Output Guard
if (ready_out_w = '1') then
stage_next <= ENCODE_PAYLOAD;
-- Reset
-- Reset
align_offset_next <= (others => '0');
data_out_latch_next <= (others => '0');
encode_stage_next <= WRITE_RID_WGUID;
@ -595,7 +595,7 @@ begin
align_offset_next <= align_offset + 8;
encode_stage_next <= WRITE_RID_SN;
cnt_next <= 0;
when others =>
when others =>
end case;
end if;
when WRITE_RID_SN =>
@ -614,7 +614,7 @@ begin
stage_next <= PUSH;
align_offset_next <= align_offset + 8;
encode_stage_next <= WRITE_RQ_GOAL_ID;
when others =>
when others =>
end case;
end if;
when WRITE_RQ_GOAL_ID =>
@ -709,7 +709,7 @@ begin
sequence_id_sig <= (others => '0');
return_code_latch <= ROS_RET_OK;
service_info_sig <= EMPTY_SERVICE_INFO;
uuid_cnt <= 0;
uuid_cnt <= 0;
-- ###GENERATED START###
accepted_latch <= '0';
stamp_latch <= (others => '0');

22
src/ros2/example_interfaces/Fibonacci_ros_action_goal_srv_server.vhd
View File

@ -197,7 +197,7 @@ begin
-- ###GENERATED END###
-- Last Word Latch Setter
if (last_word_in_r = '1') then
if (last_word_in_r = '1' and valid_in_r = '1') then
last_word_in_latch_next <= '1';
end if;
-- Data Available Setter
@ -283,7 +283,7 @@ begin
when CDR_BE =>
endian_flag_next <= '0';
stage_next <= FETCH;
-- Alignment Reset
-- Alignment Reset
align_offset_next <= (others => '0');
decode_stage_next <= GET_RID_WGUID;
cnt_next <= 0;
@ -291,7 +291,7 @@ begin
when CDR_LE =>
endian_flag_next <= '1';
stage_next <= FETCH;
-- Alignment Reset
-- Alignment Reset
align_offset_next <= (others => '0');
decode_stage_next <= GET_RID_WGUID;
cnt_next <= 0;
@ -401,7 +401,7 @@ begin
if (not check_align(align_offset, ALIGN_1)) then
target_align_next <= ALIGN_1;
stage_next <= ALIGN_IN_STREAM;
else
else
goal_id_latch_next <= write_sub_vector(goal_id_latch, get_sub_vector(data_in_latch, to_integer(align_offset(1 downto 0)), CDR_INT8_WIDTH, TRUE), uuid_cnt, TRUE);
align_offset_next <= align_offset + 1;
@ -452,7 +452,7 @@ begin
stage_next <= FETCH;
decode_stage_next <= return_stage;
cnt_next <= 0;
-- Alignment Reset
-- Alignment Reset
align_offset_next <= (others => '0');
-- Optional omitted
@ -462,7 +462,7 @@ begin
optional_next <= '1';
end if;
end if;
-- eMemberHeader
-- eMemberHeader
when 1 =>
-- Ignore Parameter ID
cnt_next <= cnt + 1;
@ -472,7 +472,7 @@ begin
stage_next <= FETCH;
decode_stage_next <= return_stage;
cnt_next <= 0;
-- Alignment Reset
-- Alignment Reset
align_offset_next <= (others => '0');
-- Optional omitted
@ -524,7 +524,7 @@ begin
-- Output Guard
if (ready_out_w = '1') then
stage_next <= ENCODE_PAYLOAD;
-- Reset
-- Reset
align_offset_next <= (others => '0');
data_out_latch_next <= (others => '0');
encode_stage_next <= WRITE_RID_WGUID;
@ -587,7 +587,7 @@ begin
align_offset_next <= align_offset + 8;
encode_stage_next <= WRITE_RID_SN;
cnt_next <= 0;
when others =>
when others =>
end case;
end if;
when WRITE_RID_SN =>
@ -606,7 +606,7 @@ begin
stage_next <= PUSH;
align_offset_next <= align_offset + 8;
encode_stage_next <= WRITE_RR_ACCEPTED;
when others =>
when others =>
end case;
end if;
when WRITE_RR_ACCEPTED =>
@ -647,7 +647,7 @@ begin
-- DONE
stage_next <= PUSH;
finalize_payload_next <= '1';
when others =>
when others =>
end case;
end if;
when others =>

20
src/ros2/example_interfaces/Fibonacci_ros_action_result_srv_client.vhd
View File

@ -236,7 +236,7 @@ begin
-- ###GENERATED END###
-- Last Word Latch Setter
if (last_word_in_r = '1') then
if (last_word_in_r = '1' and valid_in_r = '1') then
last_word_in_latch_next <= '1';
end if;
-- Data Available Setter
@ -328,7 +328,7 @@ begin
when CDR_BE =>
endian_flag_next <= '0';
stage_next <= FETCH;
-- Alignment Reset
-- Alignment Reset
align_offset_next <= (others => '0');
decode_stage_next <= GET_RID_WGUID;
cnt_next <= 0;
@ -336,7 +336,7 @@ begin
when CDR_LE =>
endian_flag_next <= '1';
stage_next <= FETCH;
-- Alignment Reset
-- Alignment Reset
align_offset_next <= (others => '0');
decode_stage_next <= GET_RID_WGUID;
cnt_next <= 0;
@ -487,7 +487,7 @@ begin
if (not check_align(align_offset, ALIGN_4)) then
target_align_next <= ALIGN_4;
stage_next <= ALIGN_IN_STREAM;
else
else
seq_mem_addr <= std_logic_vector(to_unsigned(seq_cnt,R_RR_SEQ_ADDR_WIDTH));
seq_mem_data_in <= endian_swap(endian_flag, data_in_latch);
seq_mem_valid_in <= '1';
@ -523,7 +523,7 @@ begin
stage_next <= FETCH;
decode_stage_next <= return_stage;
cnt_next <= 0;
-- Alignment Reset
-- Alignment Reset
align_offset_next <= (others => '0');
-- Optional omitted
@ -533,7 +533,7 @@ begin
optional_next <= '1';
end if;
end if;
-- eMemberHeader
-- eMemberHeader
when 1 =>
-- Ignore Parameter ID
cnt_next <= cnt + 1;
@ -543,7 +543,7 @@ begin
stage_next <= FETCH;
decode_stage_next <= return_stage;
cnt_next <= 0;
-- Alignment Reset
-- Alignment Reset
align_offset_next <= (others => '0');
-- Optional omitted
@ -595,7 +595,7 @@ begin
-- Output Guard
if (ready_out_w = '1') then
stage_next <= ENCODE_PAYLOAD;
-- Reset
-- Reset
align_offset_next <= (others => '0');
data_out_latch_next <= (others => '0');
encode_stage_next <= WRITE_RID_WGUID;
@ -658,7 +658,7 @@ begin
align_offset_next <= align_offset + 8;
encode_stage_next <= WRITE_RID_SN;
cnt_next <= 0;
when others =>
when others =>
end case;
end if;
when WRITE_RID_SN =>
@ -677,7 +677,7 @@ begin
stage_next <= PUSH;
align_offset_next <= align_offset + 8;
encode_stage_next <= WRITE_RQ_GOAL_ID;
when others =>
when others =>
end case;
end if;
when WRITE_RQ_GOAL_ID =>

24
src/ros2/example_interfaces/Fibonacci_ros_action_result_srv_server.vhd
View File

@ -232,7 +232,7 @@ begin
-- ###GENERATED END###
-- Last Word Latch Setter
if (last_word_in_r = '1') then
if (last_word_in_r = '1' and valid_in_r = '1') then
last_word_in_latch_next <= '1';
end if;
-- Data Available Setter
@ -322,7 +322,7 @@ begin
when CDR_BE =>
endian_flag_next <= '0';
stage_next <= FETCH;
-- Alignment Reset
-- Alignment Reset
align_offset_next <= (others => '0');
decode_stage_next <= GET_RID_WGUID;
cnt_next <= 0;
@ -330,7 +330,7 @@ begin
when CDR_LE =>
endian_flag_next <= '1';
stage_next <= FETCH;
-- Alignment Reset
-- Alignment Reset
align_offset_next <= (others => '0');
decode_stage_next <= GET_RID_WGUID;
cnt_next <= 0;
@ -439,7 +439,7 @@ begin
if (not check_align(align_offset, ALIGN_1)) then
target_align_next <= ALIGN_1;
stage_next <= ALIGN_IN_STREAM;
else
else
goal_id_latch_next <= write_sub_vector(goal_id_latch, get_sub_vector(data_in_latch, to_integer(align_offset(1 downto 0)), CDR_INT8_WIDTH, TRUE), uuid_cnt, TRUE);
align_offset_next <= align_offset + 1;
@ -474,7 +474,7 @@ begin
stage_next <= FETCH;
decode_stage_next <= return_stage;
cnt_next <= 0;
-- Alignment Reset
-- Alignment Reset
align_offset_next <= (others => '0');
-- Optional omitted
@ -484,7 +484,7 @@ begin
optional_next <= '1';
end if;
end if;
-- eMemberHeader
-- eMemberHeader
when 1 =>
-- Ignore Parameter ID
cnt_next <= cnt + 1;
@ -494,7 +494,7 @@ begin
stage_next <= FETCH;
decode_stage_next <= return_stage;
cnt_next <= 0;
-- Alignment Reset
-- Alignment Reset
align_offset_next <= (others => '0');
-- Optional omitted
@ -546,7 +546,7 @@ begin
-- Output Guard
if (ready_out_w = '1') then
stage_next <= ENCODE_PAYLOAD;
-- Reset
-- Reset
align_offset_next <= (others => '0');
data_out_latch_next <= (others => '0');
encode_stage_next <= WRITE_RID_WGUID;
@ -609,7 +609,7 @@ begin
align_offset_next <= align_offset + 8;
encode_stage_next <= WRITE_RID_SN;
cnt_next <= 0;
when others =>
when others =>
end case;
end if;
when WRITE_RID_SN =>
@ -628,7 +628,7 @@ begin
stage_next <= PUSH;
align_offset_next <= align_offset + 8;
encode_stage_next <= WRITE_RR_STATUS;
when others =>
when others =>
end case;
end if;
when WRITE_RR_STATUS =>
@ -676,7 +676,7 @@ begin
if (not check_align(align_offset, ALIGN_4)) then
target_align_next <= ALIGN_4;
stage_next <= ALIGN_OUT_STREAM;
else
else
case (cnt) is
-- GET
when 0 =>
@ -706,7 +706,7 @@ begin
seq_cnt_next <= seq_cnt + 1;
end if;
end if;
when others =>
when others =>
end case;
end if;
-- ###GENERATED END###

26
src/ros2/rcl_interfaces/action_msgs/CancelGoal_ros_srv_client.vhd
View File

@ -252,9 +252,9 @@ begin
return_code_user <= ROS_RET_OK;
data_out_w <= (others => '0');
-- ###GENERATED START###
return_code_latch1_next <= return_code_latch1;
return_code_latch1_next <= return_code_latch1;
uuid_cnt_next <= uuid_cnt;
uuid <= uuid_next;
uuid <= uuid_next;
goals_canceling_ready <= '0';
goals_canceling_len_latch_next <= goals_canceling_len_latch;
goals_canceling_cnt_next <= goals_canceling_cnt;
@ -271,7 +271,7 @@ begin
-- ###GENERATED END###
-- Last Word Latch Setter
if (last_word_in_r = '1') then
if (last_word_in_r = '1' and valid_in_r = '1') then
last_word_in_latch_next <= '1';
end if;
-- Data Available Setter
@ -367,7 +367,7 @@ begin
when CDR_BE =>
endian_flag_next <= '0';
stage_next <= FETCH;
-- Alignment Reset
-- Alignment Reset
align_offset_next <= (others => '0');
decode_stage_next <= GET_RID_WGUID;
cnt_next <= 0;
@ -375,7 +375,7 @@ begin
when CDR_LE =>
endian_flag_next <= '1';
stage_next <= FETCH;
-- Alignment Reset
-- Alignment Reset
align_offset_next <= (others => '0');
decode_stage_next <= GET_RID_WGUID;
cnt_next <= 0;
@ -529,7 +529,7 @@ begin
if (not check_align(align_offset, ALIGN_1)) then
target_align_next <= ALIGN_1;
stage_next <= ALIGN_IN_STREAM;
else
else
case (cnt) is
when 0 =>
uuid_next(uuid_cnt) <= get_sub_vector(data_in_latch, to_integer(align_offset(1 downto 0)), CDR_INT8_WIDTH, TRUE);
@ -619,7 +619,7 @@ begin
stage_next <= FETCH;
decode_stage_next <= return_stage;
cnt_next <= 0;
-- Alignment Reset
-- Alignment Reset
align_offset_next <= (others => '0');
-- Optional omitted
@ -629,7 +629,7 @@ begin
optional_next <= '1';
end if;
end if;
-- eMemberHeader
-- eMemberHeader
when 1 =>
-- Ignore Parameter ID
cnt_next <= cnt + 1;
@ -639,7 +639,7 @@ begin
stage_next <= FETCH;
decode_stage_next <= return_stage;
cnt_next <= 0;
-- Alignment Reset
-- Alignment Reset
align_offset_next <= (others => '0');
-- Optional omitted
@ -691,7 +691,7 @@ begin
-- Output Guard
if (ready_out_w = '1') then
stage_next <= ENCODE_PAYLOAD;
-- Reset
-- Reset
align_offset_next <= (others => '0');
data_out_latch_next <= (others => '0');
encode_stage_next <= WRITE_RID_WGUID;
@ -754,7 +754,7 @@ begin
align_offset_next <= align_offset + 8;
encode_stage_next <= WRITE_RID_SN;
cnt_next <= 0;
when others =>
when others =>
end case;
end if;
when WRITE_RID_SN =>
@ -775,7 +775,7 @@ begin
-- ###GENERATED START###
encode_stage_next <= WRITE_RQ_GOAL_INFO_GOAL_ID;
-- ###GENERATED END###
when others =>
when others =>
end case;
end if;
-- ###GENERATED START###
@ -823,7 +823,7 @@ begin
-- DONE
stage_next <= PUSH;
finalize_payload_next <= '1';
when others =>
when others =>
end case;
end if;
-- ###GENERATED END###

24
src/ros2/rcl_interfaces/action_msgs/CancelGoal_ros_srv_server.vhd
View File

@ -270,7 +270,7 @@ begin
-- ###GENERATED END###
-- Last Word Latch Setter
if (last_word_in_r = '1') then
if (last_word_in_r = '1' and valid_in_r = '1') then
last_word_in_latch_next <= '1';
end if;
-- Data Available Setter
@ -364,7 +364,7 @@ begin
when CDR_BE =>
endian_flag_next <= '0';
stage_next <= FETCH;
-- Alignment Reset
-- Alignment Reset
align_offset_next <= (others => '0');
decode_stage_next <= GET_RID_WGUID;
cnt_next <= 0;
@ -372,7 +372,7 @@ begin
when CDR_LE =>
endian_flag_next <= '1';
stage_next <= FETCH;
-- Alignment Reset
-- Alignment Reset
align_offset_next <= (others => '0');
decode_stage_next <= GET_RID_WGUID;
cnt_next <= 0;
@ -484,7 +484,7 @@ begin
if (not check_align(align_offset, ALIGN_1)) then
target_align_next <= ALIGN_1;
stage_next <= ALIGN_IN_STREAM;
else
else
goal_info_goal_id_latch_next <= write_sub_vector(goal_info_goal_id_latch, get_sub_vector(data_in_latch, to_integer(align_offset(1 downto 0)), CDR_INT8_WIDTH, TRUE), uuid_cnt, TRUE);
align_offset_next <= align_offset + 1;
@ -544,7 +544,7 @@ begin
stage_next <= FETCH;
decode_stage_next <= return_stage;
cnt_next <= 0;
-- Alignment Reset
-- Alignment Reset
align_offset_next <= (others => '0');
-- Optional omitted
@ -554,7 +554,7 @@ begin
optional_next <= '1';
end if;
end if;
-- eMemberHeader
-- eMemberHeader
when 1 =>
-- Ignore Parameter ID
cnt_next <= cnt + 1;
@ -564,7 +564,7 @@ begin
stage_next <= FETCH;
decode_stage_next <= return_stage;
cnt_next <= 0;
-- Alignment Reset
-- Alignment Reset
align_offset_next <= (others => '0');
-- Optional omitted
@ -616,7 +616,7 @@ begin
-- Output Guard
if (ready_out_w = '1') then
stage_next <= ENCODE_PAYLOAD;
-- Reset
-- Reset
align_offset_next <= (others => '0');
data_out_latch_next <= (others => '0');
encode_stage_next <= WRITE_RID_WGUID;
@ -679,7 +679,7 @@ begin
align_offset_next <= align_offset + 8;
encode_stage_next <= WRITE_RID_SN;
cnt_next <= 0;
when others =>
when others =>
end case;
end if;
when WRITE_RID_SN =>
@ -700,7 +700,7 @@ begin
-- ###GENERATED START###
encode_stage_next <= WRITE_RR_RETURN_CODE;
-- ###GENERATED END###
when others =>
when others =>
end case;
end if;
-- ###GENERATED START###
@ -780,7 +780,7 @@ begin
stage_next <= PUSH;
end if;
end if;
when others =>
when others =>
end case;
end if;
when WRITE_RR_GOALS_CANCELING_STAMP =>
@ -828,7 +828,7 @@ begin
cnt_next <= 0;
end if;
end if;
when others =>
when others =>
end case;
end if;
-- ###GENERATED END###

16
src/ros2/rcl_interfaces/action_msgs/GoalStatusArray_ros_sub.vhd
View File

@ -232,7 +232,7 @@ begin
-- ###GENERATED START###
dw_latch_next <= dw_latch;
uuid_cnt_next <= uuid_cnt;
uuid <= uuid_next;
uuid <= uuid_next;
status_list_ready <= '0';
status_list_len_latch_next <= status_list_len_latch;
status_list_cnt_next <= status_list_cnt;
@ -254,7 +254,7 @@ begin
-- ###GENERATED END###
-- Last Word Latch Setter
if (last_word_in_dds = '1') then
if (last_word_in_dds = '1' and valid_in_dds = '1') then
last_word_in_latch_next <= '1';
end if;
-- Data Available Setter
@ -350,7 +350,7 @@ begin
when CDR_BE =>
endian_flag_next <= '0';
stage_next <= FETCH;
-- Alignment Reset
-- Alignment Reset
align_offset_next <= (others => '0');
-- ###GENERATED START###
@ -359,7 +359,7 @@ begin
when CDR_LE =>
endian_flag_next <= '1';
stage_next <= FETCH;
-- Alignment Reset
-- Alignment Reset
align_offset_next <= (others => '0');
-- ###GENERATED START###
@ -431,7 +431,7 @@ begin
if (not check_align(align_offset, ALIGN_1)) then
target_align_next <= ALIGN_1;
stage_next <= ALIGN_STREAM;
else
else
case (cnt) is
when 0 =>
uuid_next(uuid_cnt) <= get_sub_vector(data_in_latch, to_integer(align_offset(1 downto 0)), CDR_INT8_WIDTH, TRUE);
@ -542,7 +542,7 @@ begin
stage_next <= FETCH;
decode_stage_next <= return_stage;
cnt_next <= 0;
-- Alignment Reset
-- Alignment Reset
align_offset_next <= (others => '0');
-- Optional omitted
@ -552,7 +552,7 @@ begin
optional_next <= '1';
end if;
end if;
-- eMemberHeader
-- eMemberHeader
when 1 =>
-- Ignore Parameter ID
cnt_next <= cnt + 1;
@ -562,7 +562,7 @@ begin
stage_next <= FETCH;
decode_stage_next <= return_stage;
cnt_next <= 0;
-- Alignment Reset
-- Alignment Reset
align_offset_next <= (others => '0');
-- Optional omitted

40
src/rtps_discovery_module.vhd
View File

@ -299,20 +299,20 @@ architecture arch of rtps_discovery_module is
--*****TYPE DECLARATION*****
-- FSM states. Explained below in detail
type STAGE_TYPE is (IDLE, PACKET_HEADER, PACKET_SRC_ADDR, PACKET_SRC_ENTITYID, PACKET_SRC_GUIDPREFIX, PACKET_DEST_ENTITYID,
CHECK_SRC_ENTITYID, LATCH_SEQ_NR, PROCESS_DATA, PROCESS_MESSAGE_SEQUENCE_NUMBERS, PROCESS_MESSAGE, PROCESS_GAP, PROCESS_GAP_SEQUENCE_NUMBERS, FIND_NEXT_VALID_IN_BITMAP,
PROCESS_PL, CHECK_DEFAULT, SELECT_LOCATOR, LATCH_STRING_LENGTH, COMPARE_STRING, RXO_DURABILITY, RXO_DEADLINE, RXO_LIVELINESS, RXO_LEASE_DURATION, LATCH_LEASE_DURATION,
LATCH_LIFESPAN_DURATION, RXO_RELIABILITY, RXO_DESTINATION_ORDER, RXO_OWNERSHIP, RXO_PRESENTATION, RXO_PARTITION, RXO_LATENCY_BUDGET, CHECK_MAX_SIZE_SERIALIZED,
MATCH_DOMAIN_ID, MATCH_PROTOCOL_VERSION, LATCH_LOCATOR, LATCH_EXPECTS_INLINE_QOS, MATCH_GUID, CHECK_REMOTE_BUILTIN_ENDPOINTS, CHECK_STATUS_INFO,
PARTICIPANT_MATCH_STAGE, INFORM_ENDPOINTS_MATCH, INFORM_ENDPOINTS_UNMATCH, INFORM_ENDPOINTS_PARTICIPANT_UNMATCH, PARTICIPANT_STALE_CHECK,
PROCESS_HEARTBEAT, PROCESS_HEARTBEAT_SEQUENCE_NUMBERS, SEND_ACKNACK, SEND_HEARTBEAT, PROCESS_ACKNACK,
PROCESS_ACKNACK_SEQUENCE_NUMBERS, FIND_PARTICIPANT_DEST, SEND_HEADER, SEND_PARTICIPANT_ANNOUNCEMENT, SEND_PUB_DATA, SEND_SUB_DATA,
type STAGE_TYPE is (IDLE, PACKET_HEADER, PACKET_SRC_ADDR, PACKET_SRC_ENTITYID, PACKET_SRC_GUIDPREFIX, PACKET_DEST_ENTITYID,
CHECK_SRC_ENTITYID, LATCH_SEQ_NR, PROCESS_DATA, PROCESS_MESSAGE_SEQUENCE_NUMBERS, PROCESS_MESSAGE, PROCESS_GAP, PROCESS_GAP_SEQUENCE_NUMBERS, FIND_NEXT_VALID_IN_BITMAP,
PROCESS_PL, CHECK_DEFAULT, SELECT_LOCATOR, LATCH_STRING_LENGTH, COMPARE_STRING, RXO_DURABILITY, RXO_DEADLINE, RXO_LIVELINESS, RXO_LEASE_DURATION, LATCH_LEASE_DURATION,
LATCH_LIFESPAN_DURATION, RXO_RELIABILITY, RXO_DESTINATION_ORDER, RXO_OWNERSHIP, RXO_PRESENTATION, RXO_PARTITION, RXO_LATENCY_BUDGET, CHECK_MAX_SIZE_SERIALIZED,
MATCH_DOMAIN_ID, MATCH_PROTOCOL_VERSION, LATCH_LOCATOR, LATCH_EXPECTS_INLINE_QOS, MATCH_GUID, CHECK_REMOTE_BUILTIN_ENDPOINTS, CHECK_STATUS_INFO,
PARTICIPANT_MATCH_STAGE, INFORM_ENDPOINTS_MATCH, INFORM_ENDPOINTS_UNMATCH, INFORM_ENDPOINTS_PARTICIPANT_UNMATCH, PARTICIPANT_STALE_CHECK,
PROCESS_HEARTBEAT, PROCESS_HEARTBEAT_SEQUENCE_NUMBERS, SEND_ACKNACK, SEND_HEARTBEAT, PROCESS_ACKNACK,
PROCESS_ACKNACK_SEQUENCE_NUMBERS, FIND_PARTICIPANT_DEST, SEND_HEADER, SEND_PARTICIPANT_ANNOUNCEMENT, SEND_PUB_DATA, SEND_SUB_DATA,
SEND_MES_MAN_LIVE, SEND_MES_GAP, SEND_MES_AUTO_LIVE, LIVELINESS_UPDATE, SKIP_PARAMETER, SKIP_PACKET);
-- Memory FSM states. Explained below in detail
type MEM_STAGE_TYPE is (IDLE, SEARCH_PARTICIPANT, GET_NEXT_PARTICIPANT, GET_PARTICIPANT_DATA, INSERT_PARTICIPANT, UPDATE_PARTICIPANT, REMOVE_PARTICIPANT, RESET_MEMORY);
-- Memory FSM Opcodes
-- OPCODE DESCRIPTION
-- SEARCH_PARTICIPANT Search memory for Participant Entry with GUID Prefix equal to "guid" signal.
-- SEARCH_PARTICIPANT Search memory for Participant Entry with GUID Prefix equal to "guid" signal.
-- Set "participant_data.addr" to Base Address of found Participant Entry or PARTICIPANT_MEMORY_MAX_ADDRESS if nothing found.
-- "participant_data" contains memory Participant Data according to "mem_r.field_flags".
-- INSERT_PARTICIPANT Write Participant Data to next available empty slot.
@ -321,7 +321,7 @@ architecture arch of rtps_discovery_module is
-- "participant_data.addr" is set to the next Endpoint (or ENDPOINT_MEMORY_MAX_ADDRESS if no next Endpoint exists)
-- GET_NEXT_PARTICIPANT Get Participant Data of next participant (from the one pointed by "participant_data.addr") according to "mem_r.field_flags".
-- "participant_data.addr" is set to the Address of the Participant, or PARTICIPANT_MEMORY_MAX_ADDRESS if no Participant in Memory
-- GET_PARTICIPANT Get Participant Data of participant pointed by "mem_r.addr" according to "mem_r.field_flags".
-- GET_PARTICIPANT Get Participant Data of participant pointed by "mem_r.addr" according to "mem_r.field_flags".
-- Already fetched Data of the same Participant is not modified
type MEM_OPCODE_TYPE is (NOP, SEARCH_PARTICIPANT, INSERT_PARTICIPANT, UPDATE_PARTICIPANT, GET_NEXT_PARTICIPANT, REMOVE_PARTICIPANT, GET_PARTICIPANT);
-- RTPS Data Submessage Content:
@ -710,7 +710,7 @@ begin
-- STATE DESCRIPTION
-- IDLE Idle state. Initiates Participant Announcements, Heartbeat/Liveliness Assertions, Stale Participant Entry Checks, and Packet Processing, in that priority order.
-- PACKET_HEADER Read the Endpoint FIFO Packet Format Header (RTPS Submessage ID/Opcode, Submessage Flags, Source UDPv4 Port)
-- PACKET_SRC_ADDR Read Source IPv4 Address
-- PACKET_SRC_ADDR Read Source IPv4 Address
-- PACKET_SRC_GUIDPREFIX Read Source GUID Prefix
-- PACKET_SRC_ENTITYID Read Source Entity ID
-- PACKET_DEST_ENTITYID Read Destination Entity ID. Determine content of Packet (Participant Data, Publisher/Subscriber/Message Data/GAP/HEARTBEAT/ACKNACK) and initiate processing.
@ -852,7 +852,7 @@ begin
data_out_sig <= (others => '0');
-- Last Word Latch Setter
if (last_word_in = '1') then
if (last_word_in = '1' and empty = '0') then
last_word_in_latch_next <= '1';
end if;
@ -912,7 +912,7 @@ begin
-- Send Heartbeat and Liveliness Assertions to all stored Participants
mem_op_start <= '1';
mem_opcode <= GET_PARTICIPANT;
mem_r.addr <= mem_occupied_head;
mem_r.addr <= mem_occupied_head;
mem_r.field_flags <= PMF_META_IPV4_ADDR_FLAG or PMF_UDP_PORT_FLAG;
stage_next <= FIND_PARTICIPANT_DEST;
-- Increment the counter for the new Heartbeat Messages
@ -1577,8 +1577,8 @@ begin
-- Participant Message Kind
when 3 =>
-- NOTE: Rest of Participant Message is ignored
-- XXX: The Participant Message Data may contain additional data, and according to DDSI-RTPS 2.3
-- implementations must be able to support up to 128 Bytes of additional data. Due to the unnecessary
-- XXX: The Participant Message Data may contain additional data, and according to DDSI-RTPS 2.3
-- implementations must be able to support up to 128 Bytes of additional data. Due to the unnecessary
-- high complexity this would add, this is currently not supported.
case (data_in) is
-- Automatic Liveliness Assertion
@ -2525,7 +2525,7 @@ begin
null;
when PID_KEY_HASH =>
stage_next <= MATCH_GUID;
cnt_next <= 0;
cnt_next <= 0;
when PID_STATUS_INFO =>
stage_next <= CHECK_STATUS_INFO;
when PID_PAD =>
@ -2568,7 +2568,7 @@ begin
case (message_type) is
when PDP =>
-- Check Domain Tag against Default if necessary
-- Check Domain Tag against Default if necessary
if (not check_mask(rcvd, RCVD_DOMAIN_TAG_FLAG) and DOMAIN_TAG /= DEFAULT_DOMAIN_TAG) then
participant_match_next <= '0';
end if;
@ -3311,8 +3311,8 @@ begin
-- DONE
stage_next <= SKIP_PACKET;
end if;
-- NOTE: We only process the Sequences in order. This may lead to more traffic being exchanged
-- (since all Data messages with a higher sequence number than the next expected will be ignored),
-- NOTE: We only process the Sequences in order. This may lead to more traffic being exchanged
-- (since all Data messages with a higher sequence number than the next expected will be ignored),
-- but keeps the logic simple.
-- Endpoint (Next Expected Sequence Number)
elsif (message_type = EDP and mem_seq_nr = seq_nr) then
@ -5866,7 +5866,7 @@ begin
mem_stage_next <= IDLE;
end if;
when others =>
when others =>
null;
end case;
when UPDATE_PARTICIPANT =>

24
src/rtps_reader.vhd
View File

@ -207,9 +207,9 @@ architecture arch of rtps_reader is
type ENDPOINT_ADDRESS_ARRAY_TYPE is array(0 to NUM_READERS-1) of unsigned(ENDPOINT_MEMORY_ADDR_WIDTH-1 downto 0);
type ACKNACK_COUNT_ARRAY is array (0 to NUM_READERS-1) of unsigned(COUNT_WIDTH-1 downto 0);
-- FSM states. Explained below in detail
type STAGE_TYPE is (IDLE, LATCH_GUIDPREFIX, LATCH_ENTITYID, INITIATE_ENDPOINT_SEARCH, LATCH_ENDPOINT_DATA, METATRAFFIC_OPERATION, LATCH_SRC_ADDR,
LATCH_EXTRA_DATA, LATCH_HEARTBEAT, PROCESS_HEARTBEAT, LATCH_GAP, PROCESS_GAP, FIND_NEXT_VALID_IN_BITMAP, PROCESS_INLINE_QOS,
LATCH_KEY_HASH, LATCH_STATUS_INFO, INITIATE_ADD_CACHE_CHANGE_REQUEST, ADD_CACHE_CHANGE, PUSH_PAYLOAD, FINALIZE_ADD_CACHE_CHANGE_REQUEST,
type STAGE_TYPE is (IDLE, LATCH_GUIDPREFIX, LATCH_ENTITYID, INITIATE_ENDPOINT_SEARCH, LATCH_ENDPOINT_DATA, METATRAFFIC_OPERATION, LATCH_SRC_ADDR,
LATCH_EXTRA_DATA, LATCH_HEARTBEAT, PROCESS_HEARTBEAT, LATCH_GAP, PROCESS_GAP, FIND_NEXT_VALID_IN_BITMAP, PROCESS_INLINE_QOS,
LATCH_KEY_HASH, LATCH_STATUS_INFO, INITIATE_ADD_CACHE_CHANGE_REQUEST, ADD_CACHE_CHANGE, PUSH_PAYLOAD, FINALIZE_ADD_CACHE_CHANGE_REQUEST,
ENDPOINT_STALE_CHECK, SEND_HEADER, SEND_ACKNACK, SKIP_PARAMETER, SKIP_PACKET, SKIP_META_OPERATION, LATCH_PAYLOAD);
-- Memory FSM states. Explained below in detail
type MEM_STAGE_TYPE is (IDLE, SEARCH_ENDPOINT, GET_ENDPOINT_DATA, INSERT_ENDPOINT, UPDATE_ENDPOINT, REMOVE_ENDPOINT, GET_NEXT_ENDPOINT, RESET_MEMORY);
@ -229,7 +229,7 @@ architecture arch of rtps_reader is
type MEM_OPCODE_TYPE is (NOP, SEARCH_ENDPOINT, INSERT_ENDPOINT, UPDATE_ENDPOINT, REMOVE_ENDPOINT, GET_NEXT_ENDPOINT, GET_ENDPOINT);
-- Record of Endpoint Data
type ENDPOINT_DATA_TYPE is record
i : natural range 0 to NUM_READERS-1;
i : natural range 0 to NUM_READERS-1;
addr : unsigned(ENDPOINT_MEMORY_ADDR_WIDTH-1 downto 0);
guid : GUID_TYPE;
ip_addr : std_logic_vector(IPv4_ADDRESS_WIDTH-1 downto 0);
@ -629,7 +629,7 @@ begin
-- Last Word Latch Setter
-- NOTE: Assumes meta and user traffic are not consumed concurrently
if (last_word_in_user = '1' or last_word_in_meta = '1') then
if ((last_word_in_user = '1' and empty_user /= (empty_user'range => '1')) or (last_word_in_meta = '1' and empty_meta /= (empty_meta'range => '1'))) then
last_word_in_latch_next <= '1';
end if;
@ -774,7 +774,7 @@ begin
assert stable(clk, last_word_in_meta = '1') severity FAILURE;
stage_next <= INITIATE_ENDPOINT_SEARCH;
cnt_next <= 0;
when EMO_LIVELINESS_UPDATE =>
when EMO_LIVELINESS_UPDATE =>
assert stable(clk, last_word_in_meta = '1') severity FAILURE;
stage_next <= INITIATE_ENDPOINT_SEARCH;
cnt_next <= 0;
@ -907,7 +907,7 @@ begin
stage_next <= LATCH_PAYLOAD;
end if;
end if;
when others =>
when others =>
null;
end case;
end if;
@ -1043,7 +1043,7 @@ begin
-- EXIT
stage_next <= SKIP_PARAMETER;
when others =>
when others =>
null;
end case;
end if;
@ -1114,7 +1114,7 @@ begin
stage_next <= INITIATE_ENDPOINT_SEARCH;
cnt_next <= 0;
when others =>
when others =>
null;
end case;
end if;
@ -1571,7 +1571,7 @@ begin
-- Set Response Delay
mem_op_start <= '1';
mem_opcode <= UPDATE_ENDPOINT;
mem_r.i <= ind;
mem_r.i <= ind;
mem_r.addr <= mem_endpoint_data.addr;
mem_r.field_flags <= EMF_RES_TIME_FLAG;
@ -3349,7 +3349,7 @@ begin
-- DONE
mem_stage_next <= IDLE;
end if;
when others =>
when others =>
null;
end case;
when UPDATE_ENDPOINT =>
@ -3601,7 +3601,7 @@ begin
-- DONE
mem_stage_next <= IDLE;
end if;
when others =>
when others =>
null;
end case;
when GET_NEXT_ENDPOINT =>

50
src/rtps_writer.vhd
View File

@ -25,9 +25,9 @@ use work.rtps_config_package.all;
-- This entity has an internal sequence number that is incremented on each new cache change. Depending on the setting
-- of 'PUSH_MODE' a new cache change is sent immediately, or only after the remote reliable reader has requested it via
-- an ACKNACK Submessage.
-- A request bitmap (of a range of up to 32 SN), and the sequence number of the last acknowledged SN of each remote
-- A request bitmap (of a range of up to 32 SN), and the sequence number of the last acknowledged SN of each remote
-- endpoint are stored in the local memory. (Note that only reliable readers can send ACKNACKs).
-- A global signal contains the highest common ACKed SN of all remote reader endpoints (remote best effort readers are
-- A global signal contains the highest common ACKed SN of all remote reader endpoints (remote best effort readers are
-- ignored), and allows this entity to mark SNs in the HistoryCache for deletion.
-- This entity interacts with the HistoryCache via a start/done operation schema.
@ -35,12 +35,12 @@ use work.rtps_config_package.all;
-- and GET_MAX_SN.
-- every time new data is available ('data_available' signal of the HistoryCache is high), or data needs to be fetched to
-- satisfy a request the GET_CACHE_CHANGE operation is executed.
-- Once a SN has been acknowledged by all matched remote (reliable) readers, either the ACK_CACHE_CHANGE operation is
-- performed on the HistoryCache to convey this information, or the REMOVE_CACHE_CHANGE operation is executed to remove
-- Once a SN has been acknowledged by all matched remote (reliable) readers, either the ACK_CACHE_CHANGE operation is
-- performed on the HistoryCache to convey this information, or the REMOVE_CACHE_CHANGE operation is executed to remove
-- the CacheChange from the HistoryCache (if the local endpoint is configured with DURABILITY QoS VOLATILE).
-- Requested SN from remote endpoint readers, on the other hand, are NACKed (reversing the ACK) using the
-- Requested SN from remote endpoint readers, on the other hand, are NACKed (reversing the ACK) using the
-- NACK_CACHE_CHANGE operation.
-- In order to formulate a HEARTBEAT SUbmessage the entity has to know the highest and lowest SN still available in the
-- In order to formulate a HEARTBEAT SUbmessage the entity has to know the highest and lowest SN still available in the
-- HistoryCache, which it gets with the GET_MIN_SN and GET_MAX_SN operations.
-- MEMORY LAYOUT
@ -249,12 +249,12 @@ architecture arch of rtps_writer is
type ENDPOINT_ADDRESS_ARRAY_TYPE is array(0 to NUM_WRITERS-1) of unsigned(ENDPOINT_MEMORY_ADDR_WIDTH-1 downto 0);
type HEARTBEAT_COUNT_ARRAY is array (0 to NUM_WRITERS-1) of unsigned(COUNT_WIDTH-1 downto 0);
-- FSM states. Explained below in detail
type STAGE_TYPE is (IDLE, LATCH_GUIDPREFIX, LATCH_ENTITYID, INITIATE_ENDPOINT_SEARCH, LATCH_ENDPOINT_DATA, METATRAFFIC_OPERATION,
LATCH_SRC_ADDR, LATCH_ACKNACK, PROCESS_ACK, UPDATE_GLOBAL_ACK, PROCESS_NACK, PARSE_NACK_BITMAP, ENDPOINT_STALE_CHECK,
HANDLE_REQUESTS, HANDLE_HEARTBEATS, HANDLE_NEW, HANDLE_HISTORICAL, SEND_HEADER, SEND_INFO_TS,
type STAGE_TYPE is (IDLE, LATCH_GUIDPREFIX, LATCH_ENTITYID, INITIATE_ENDPOINT_SEARCH, LATCH_ENDPOINT_DATA, METATRAFFIC_OPERATION,
LATCH_SRC_ADDR, LATCH_ACKNACK, PROCESS_ACK, UPDATE_GLOBAL_ACK, PROCESS_NACK, PARSE_NACK_BITMAP, ENDPOINT_STALE_CHECK,
HANDLE_REQUESTS, HANDLE_HEARTBEATS, HANDLE_NEW, HANDLE_HISTORICAL, SEND_HEADER, SEND_INFO_TS,
SEND_DATA_A, SEND_INLINE_QOS, SEND_DATA_B, SEND_GAP_A, SEND_GAP_B, SEND_HEARTBEAT, SKIP_PACKET, SKIP_META_OPERATION);
-- Memory FSM states. Explained below in detail
type MEM_STAGE_TYPE is (IDLE, SEARCH_ENDPOINT, GET_ENDPOINT_DATA, INSERT_ENDPOINT, UPDATE_ENDPOINT, REMOVE_ENDPOINT,
type MEM_STAGE_TYPE is (IDLE, SEARCH_ENDPOINT, GET_ENDPOINT_DATA, INSERT_ENDPOINT, UPDATE_ENDPOINT, REMOVE_ENDPOINT,
GET_NEXT_ENDPOINT, RESET_MEMORY);
-- *Memory FSM Opcodes*
-- OPCODE DESCRIPTION
@ -590,7 +590,7 @@ begin
-- HANDLE_REQUESTS Send requested Cache Changes to remote Reader
-- HANDLE_HEARTBEATS Send Heartbeat to all remote Readers
-- HANDLE_NEW Send new Cache Change to all remote Readers
-- HANDLE_HISTORICAL Send all available Cache Changes to remote Endpoint
-- HANDLE_HISTORICAL Send all available Cache Changes to remote Endpoint
-- SEND_HEADER Send Output Data Header and RTPS Message Header
-- SEND_INFO_TS Send INFO_TS Submessage
-- SEND_DATA_A Send DATA Submessage Part 1
@ -639,7 +639,7 @@ begin
last_seq_nr_next <= last_seq_nr;
new_push_next <= new_push;
historical_push_next <= historical_push;
initial_heartbeat_next <= initial_heartbeat;
initial_heartbeat_next <= initial_heartbeat;
assert_liveliness_latch_next<= assert_liveliness_latch;
w_assert_liveliness_next <= w_assert_liveliness;
bitmap_cnt_next <= bitmap_cnt;
@ -671,7 +671,7 @@ begin
-- Last Word Latch Setter
-- NOTE: Assumes meta and user traffic are not consumed concurrently
if (last_word_in_user = '1' or last_word_in_meta = '1') then
if ((last_word_in_user = '1' and empty_user /= (empty_user'range => '1')) or (last_word_in_meta = '1' and empty_meta /= (empty_meta'range => '1'))) then
last_word_in_latch_next <= '1';
end if;
@ -943,7 +943,7 @@ begin
cnt_next <= 0;
end if;
end if;
when others =>
when others =>
null;
end case;
end if;
@ -1178,7 +1178,7 @@ begin
stage_next <= INITIATE_ENDPOINT_SEARCH;
cnt_next <= 1; -- GET NEXT WRITER
end if;
when others =>
when others =>
null;
end case;
when EMO_ENDPOINT_UNMATCH =>
@ -1360,7 +1360,7 @@ begin
mem_r.ack_seq_nr_base <= ack_base;
-- NOTE: The global_ack_seq_nr_base contains the lowest SN of all remote Endpoints.
-- It only needs to be updated, if the remote Endpoint with the lowest ACKed SN is updated.
-- This does not necessarily mean, that the Global ACK SN will change, as there can
-- This does not necessarily mean, that the Global ACK SN will change, as there can
-- be multiple remote Endpoints with the same lowest ACK SN.
-- Global ACK SN needs updating
if (mem_endpoint_data.ack_seq_nr_base = global_ack_seq_nr_base(ind)) then
@ -1693,7 +1693,7 @@ begin
when 4 =>
-- Wait until Operation Response
if (done_hc(ind) = '1') then
if (ret_hc(ind) = OK) then
if (ret_hc(ind) = OK) then
-- Only request Payload if necessary (Contains DATA or Serialized Key)
if (cc_kind(ind) = ALIVE or (CONFIG_ARRAY_T(ind).WITH_KEY and cc_kind(ind) /= ALIVE)) then
get_data_hc(ind) <= '1';
@ -1897,7 +1897,7 @@ begin
-- End of Endpoints
if ((not CONFIG_ARRAY_T(ind).PUSH_MODE) or mem_endpoint_data.addr = ENDPOINT_MEMORY_MAX_ADDRESS) then
-- NOTE: If PUSH_MODE false and remote reliable endpoints are available, this just does NOPs
-- NOTE: If PUSH_MODE false and remote reliable endpoints are available, this just does NOPs
-- (leaves the CCs NACKed in the HC) and updates the last_seq_nr.
-- ACK newly sent Cache Changes if Writer is BEST_EFFORT, or if all remote Readers are BEST_EFFORT
@ -2051,7 +2051,7 @@ begin
-- Wait until Operation Response
if (done_hc(ind) = '1') then
-- Wait for Operation Response
if (ret_hc(ind) = OK) then
if (ret_hc(ind) = OK) then
-- Only request Payload if necessary (Contains DATA or Serialized Key)
if (cc_kind(ind) = ALIVE or (CONFIG_ARRAY_T(ind).WITH_KEY and cc_kind(ind) /= ALIVE)) then
get_data_hc(ind) <= '1';
@ -2205,7 +2205,7 @@ begin
data_out_ro <= std_logic_vector(cc_source_timestamp(ind)(1));
stage_next <= SEND_DATA_A;
cnt_next <= 0;
cnt_next <= 0;
when others =>
null;
end case;
@ -2370,7 +2370,7 @@ begin
-- Payload Available (DATA or Serialized Key)
if (cc_kind(ind) = ALIVE or (CONFIG_ARRAY_T(ind).WITH_KEY and cc_kind(ind) /= ALIVE)) then
stage_next <= SEND_DATA_B;
stage_next <= SEND_DATA_B;
else
last_word_out_ro <= '1';
-- Continue
@ -2408,7 +2408,7 @@ begin
if (cnt3 = INLINE_QOS_T(ind).length-1) then
-- Payload Available (DATA or Serialized Key)
if (cc_kind(ind) = ALIVE or (CONFIG_ARRAY_T(ind).WITH_KEY and cc_kind(ind) /= ALIVE)) then
stage_next <= SEND_DATA_B;
stage_next <= SEND_DATA_B;
else
last_word_out_ro <= '1';
-- Continue
@ -3694,7 +3694,7 @@ begin
-- DONE
mem_stage_next <= IDLE;
end if;
when others =>
when others =>
null;
end case;
when UPDATE_ENDPOINT =>
@ -3877,7 +3877,7 @@ begin
when others =>
null;
end case;
when REMOVE_ENDPOINT =>
when REMOVE_ENDPOINT =>
case (mem_cnt) is
-- GET Next Addr
when 0 =>
@ -3971,7 +3971,7 @@ begin
-- DONE
mem_stage_next <= IDLE;
end if;
when others =>
when others =>
null;
end case;
when GET_NEXT_ENDPOINT =>