From d388e29c366308973609626303010a80bd543b93 Mon Sep 17 00:00:00 2001 From: Greek64 Date: Sun, 10 Apr 2022 11:04:59 +0200 Subject: [PATCH] Convert dds_reader to Vector Endpoint --- sim/L0_dds_reader_test1.do | 190 + sim/L0_dds_reader_test1_abzkriu.do | 196 - sim/L0_dds_reader_test1_arzkriu.do | 180 - sim/L0_dds_reader_test1_arzksiu.do | 196 - sim/L0_dds_reader_test1_arznriu.do | 175 - sim/L0_dds_reader_test1_lbzkriu.do | 196 - sim/L0_dds_reader_test1_lrzkriu.do | 196 - sim/L0_dds_reader_test2.do | 190 + sim/L0_dds_reader_test2_arpkriu.do | 195 - sim/L0_dds_reader_test3.do | 190 + sim/L0_dds_reader_test3_arzkrio.do | 199 - sim/L0_dds_reader_test3_arzkriu.do | 199 - sim/L0_dds_reader_test3_arzkrto.do | 199 - sim/L0_dds_reader_test3_arzkrtu.do | 199 - sim/L0_dds_reader_test3_arzksto.do | 201 - sim/L0_dds_reader_test3_arznriu.do | 178 - sim/L0_dds_reader_test4.do | 184 + sim/L0_dds_reader_test4_arzkriu.do | 199 - sim/L0_dds_reader_test4_arznriu.do | 199 - sim/L0_dds_reader_test5.do | 190 + sim/L0_dds_reader_test5_arzkriu.do | 198 - sim/L0_dds_reader_test6.do | 190 + sim/L0_dds_reader_test6_arzkriu.do | 199 - src/TODO.txt | 6 + src/Tests/Level_0/L0_dds_reader_test1.vhd | 6916 ++++++++++++++++ .../Level_0/L0_dds_reader_test1_abzkriu.vhd | 1690 ---- .../Level_0/L0_dds_reader_test1_arzkriu.vhd | 1696 ---- .../Level_0/L0_dds_reader_test1_arzksiu.vhd | 1694 ---- .../Level_0/L0_dds_reader_test1_arznriu.vhd | 1145 --- .../Level_0/L0_dds_reader_test1_lbzkriu.vhd | 1690 ---- .../Level_0/L0_dds_reader_test1_lrzkriu.vhd | 1690 ---- src/Tests/Level_0/L0_dds_reader_test2.vhd | 776 ++ src/Tests/Level_0/L0_dds_reader_test3.vhd | 4026 +++++++++ .../Level_0/L0_dds_reader_test3_arzkrio.vhd | 1482 ---- .../Level_0/L0_dds_reader_test3_arzkriu.vhd | 1481 ---- .../Level_0/L0_dds_reader_test3_arzkrto.vhd | 1481 ---- .../Level_0/L0_dds_reader_test3_arzkrtu.vhd | 1481 ---- .../Level_0/L0_dds_reader_test3_arzksto.vhd | 1500 ---- .../Level_0/L0_dds_reader_test3_arznriu.vhd | 841 -- src/Tests/Level_0/L0_dds_reader_test4.vhd | 957 +++ .../Level_0/L0_dds_reader_test4_arzkriu.vhd | 764 -- .../Level_0/L0_dds_reader_test4_arznriu.vhd | 633 -- ...t5_arzkriu.vhd => L0_dds_reader_test5.vhd} | 555 +- ...t6_arzkriu.vhd => L0_dds_reader_test6.vhd} | 434 +- ...t2_arpkriu.vhd => L0_dds_reader_test7.vhd} | 468 +- src/Tests/Level_2/L2_Testbench_Lib2.vhd | 75 +- src/Tests/Level_2/L2_Testbench_Lib3.vhd | 75 +- src/Tests/Level_2/L2_testbench_Lib4.vhd | 75 +- src/Tests/Level_2/L2_testbench_Lib5.vhd | 75 +- src/Tests/testbench.pro | 50 +- src/dds_reader.vhd | 7358 ++++++++--------- .../Tests/Level_2/L2_Testbench_ROS_Lib2.vhd | 75 +- .../Tests/Level_2/L2_Testbench_ROS_Lib3.vhd | 75 +- .../Tests/Level_2/L2_Testbench_ROS_Lib4.vhd | 75 +- .../Tests/Level_2/L2_Testbench_ROS_Lib5.vhd | 75 +- src/rtps_package.vhd | 10 +- syn/DE10-Nano/top.qsf | 2 +- syn/dds_reader_syn.vhd | 75 +- 58 files changed, 18523 insertions(+), 27416 deletions(-) create mode 100644 sim/L0_dds_reader_test1.do delete mode 100644 sim/L0_dds_reader_test1_abzkriu.do delete mode 100644 sim/L0_dds_reader_test1_arzkriu.do delete mode 100644 sim/L0_dds_reader_test1_arzksiu.do delete mode 100644 sim/L0_dds_reader_test1_arznriu.do delete mode 100644 sim/L0_dds_reader_test1_lbzkriu.do delete mode 100644 sim/L0_dds_reader_test1_lrzkriu.do create mode 100644 sim/L0_dds_reader_test2.do delete mode 100644 sim/L0_dds_reader_test2_arpkriu.do create mode 100644 sim/L0_dds_reader_test3.do delete mode 100644 sim/L0_dds_reader_test3_arzkrio.do delete mode 100644 sim/L0_dds_reader_test3_arzkriu.do delete mode 100644 sim/L0_dds_reader_test3_arzkrto.do delete mode 100644 sim/L0_dds_reader_test3_arzkrtu.do delete mode 100644 sim/L0_dds_reader_test3_arzksto.do delete mode 100644 sim/L0_dds_reader_test3_arznriu.do create mode 100644 sim/L0_dds_reader_test4.do delete mode 100644 sim/L0_dds_reader_test4_arzkriu.do delete mode 100644 sim/L0_dds_reader_test4_arznriu.do create mode 100644 sim/L0_dds_reader_test5.do delete mode 100644 sim/L0_dds_reader_test5_arzkriu.do create mode 100644 sim/L0_dds_reader_test6.do delete mode 100644 sim/L0_dds_reader_test6_arzkriu.do create mode 100644 src/Tests/Level_0/L0_dds_reader_test1.vhd delete mode 100644 src/Tests/Level_0/L0_dds_reader_test1_abzkriu.vhd delete mode 100644 src/Tests/Level_0/L0_dds_reader_test1_arzkriu.vhd delete mode 100644 src/Tests/Level_0/L0_dds_reader_test1_arzksiu.vhd delete mode 100644 src/Tests/Level_0/L0_dds_reader_test1_arznriu.vhd delete mode 100644 src/Tests/Level_0/L0_dds_reader_test1_lbzkriu.vhd delete mode 100644 src/Tests/Level_0/L0_dds_reader_test1_lrzkriu.vhd create mode 100644 src/Tests/Level_0/L0_dds_reader_test2.vhd create mode 100644 src/Tests/Level_0/L0_dds_reader_test3.vhd delete mode 100644 src/Tests/Level_0/L0_dds_reader_test3_arzkrio.vhd delete mode 100644 src/Tests/Level_0/L0_dds_reader_test3_arzkriu.vhd delete mode 100644 src/Tests/Level_0/L0_dds_reader_test3_arzkrto.vhd delete mode 100644 src/Tests/Level_0/L0_dds_reader_test3_arzkrtu.vhd delete mode 100644 src/Tests/Level_0/L0_dds_reader_test3_arzksto.vhd delete mode 100644 src/Tests/Level_0/L0_dds_reader_test3_arznriu.vhd create mode 100644 src/Tests/Level_0/L0_dds_reader_test4.vhd delete mode 100644 src/Tests/Level_0/L0_dds_reader_test4_arzkriu.vhd delete mode 100644 src/Tests/Level_0/L0_dds_reader_test4_arznriu.vhd rename src/Tests/Level_0/{L0_dds_reader_test5_arzkriu.vhd => L0_dds_reader_test5.vhd} (56%) rename src/Tests/Level_0/{L0_dds_reader_test6_arzkriu.vhd => L0_dds_reader_test6.vhd} (53%) rename src/Tests/Level_0/{L0_dds_reader_test2_arpkriu.vhd => L0_dds_reader_test7.vhd} (50%) diff --git a/sim/L0_dds_reader_test1.do b/sim/L0_dds_reader_test1.do new file mode 100644 index 0000000..c3d071f --- /dev/null +++ b/sim/L0_dds_reader_test1.do @@ -0,0 +1,190 @@ +onerror {resume} +radix define DDS_RETCODE { + "10#0#" "RETCODE_OK", + "10#1#" "RETCODE_ERROR", + "10#2#" "RETCODE_UNSUPPORTED", + "10#3#" "RETCODE_BAD_PARAMETER", + "10#4#" "RETCODE_PRECONDITION_NOT_MET", + "10#5#" "RETCODE_OUT_OF_RESOURCES", + "10#6#" "RETCODE_NOT_ENABLED", + "10#7#" "RETCODE_IMMUTABLE_POLICY", + "10#8#" "RETCODE_INCONSISTENT_POLICY", + "10#9#" "RETCODE_ALREADY_DELETED", + "10#10#" "RETCODE_TIMEOUT", + "10#11#" "RETCODE_NO_DATA", + "10#12#" "RETCODE_ILLEGAL_OPERATION", + -default unsigned +} +radix define SAMPLE_STATE { + "16#00000001#" "READ_SAMPLE_STATE", + "16#00000002#" "NOT_READ_SAMPLE_STATE", + "16#FFFFFFFF#" "ANY_SAMPLE_STATE", + -default binary +} +radix define VIEW_STATE { + "16#00000001#" "NEW_VIEW_STATE", + "16#00000002#" "NOT_NEW_VIEW_STATE", + "16#FFFFFFFF#" "ANY_VIEW_STATE", + -default binary +} +radix define INSTANCE_STATE { + "16#00000001#" "ALIVE_INSTANCE_STATE", + "16#00000002#" "NOT_ALIVE_DISPOSED_INSTANCE_STATE", + "16#00000004#" "NOT_ALIVE_NO_WRITERS_INSTANCE_STATE", + "16#FFFFFFFF#" "ANY_INSTANCE_STATE", + -default binary +} +radix define LAST_REASON { + "16#00000000#" "NOT_REJECTED", + "16#00000001#" "REJECTED_BY_INSTANCES_LIMIT", + "16#00000002#" "REJECTED_BY_SAMPLES_LIMIT", + "16#00000003#" "REJECTED_BY_SAMPLES_PER_INSTANCE_LIMIT", + "16#000000FF#" "REJECTED_BY_PAYOAD_MEMORY_LIMIT", + -default binary +} +quietly WaveActivateNextPane {} 0 +add wave -noupdate -divider SYSTEM +add wave -noupdate /l0_dds_reader_test1/uut/clk +add wave -noupdate /l0_dds_reader_test1/uut/reset +add wave -noupdate -radix unsigned /l0_dds_reader_test1/uut/time +add wave -noupdate -divider RTPS +add wave -noupdate -group RTPS /l0_dds_reader_test1/uut/start_rtps +add wave -noupdate -group RTPS /l0_dds_reader_test1/uut/opcode_rtps +add wave -noupdate -group RTPS /l0_dds_reader_test1/uut/ack_rtps +add wave -noupdate -group RTPS /l0_dds_reader_test1/uut/ret_rtps +add wave -noupdate -group RTPS /l0_dds_reader_test1/uut/done_rtps +add wave -noupdate -group RTPS /l0_dds_reader_test1/uut/ready_in_rtps +add wave -noupdate -group RTPS /l0_dds_reader_test1/uut/valid_in_rtps +add wave -noupdate -group RTPS -radix hexadecimal /l0_dds_reader_test1/uut/data_in_rtps +add wave -noupdate -group RTPS /l0_dds_reader_test1/uut/last_word_in_rtps +add wave -noupdate -divider DDS +add wave -noupdate -group DDS /l0_dds_reader_test1/uut/start_dds +add wave -noupdate -group DDS /l0_dds_reader_test1/uut/ack_dds +add wave -noupdate -group DDS /l0_dds_reader_test1/uut/opcode_dds +add wave -noupdate -group DDS -radix SAMPLE_STATE /l0_dds_reader_test1/uut/sample_state_dds +add wave -noupdate -group DDS -radix INSTANCE_STATE /l0_dds_reader_test1/uut/instance_state_dds +add wave -noupdate -group DDS -radix VIEW_STATE /l0_dds_reader_test1/uut/view_state_dds +add wave -noupdate -group DDS -radix hexadecimal /l0_dds_reader_test1/uut/instance_handle_dds +add wave -noupdate -group DDS -radix unsigned /l0_dds_reader_test1/uut/max_samples_dds +add wave -noupdate -group DDS -radix DDS_RETCODE -childformat {{/l0_dds_reader_test1/uut/return_code_dds(0) -radix DDS_RETCODE} {/l0_dds_reader_test1/uut/return_code_dds(1) -radix DDS_RETCODE} {/l0_dds_reader_test1/uut/return_code_dds(2) -radix DDS_RETCODE} {/l0_dds_reader_test1/uut/return_code_dds(3) -radix DDS_RETCODE} {/l0_dds_reader_test1/uut/return_code_dds(4) -radix DDS_RETCODE} {/l0_dds_reader_test1/uut/return_code_dds(5) -radix DDS_RETCODE}} -subitemconfig {/l0_dds_reader_test1/uut/return_code_dds(0) {-height 15 -radix DDS_RETCODE} /l0_dds_reader_test1/uut/return_code_dds(1) {-height 15 -radix DDS_RETCODE} /l0_dds_reader_test1/uut/return_code_dds(2) {-height 15 -radix DDS_RETCODE} /l0_dds_reader_test1/uut/return_code_dds(3) {-height 15 -radix DDS_RETCODE} /l0_dds_reader_test1/uut/return_code_dds(4) {-height 15 -radix DDS_RETCODE} /l0_dds_reader_test1/uut/return_code_dds(5) {-height 15 -radix DDS_RETCODE}} /l0_dds_reader_test1/uut/return_code_dds +add wave -noupdate -group DDS /l0_dds_reader_test1/uut/done_dds +add wave -noupdate -group DDS -divider SI +add wave -noupdate -group DDS -radix hexadecimal -childformat {{/l0_dds_reader_test1/uut/sample_info(0) -radix hexadecimal -childformat {{/l0_dds_reader_test1/uut/sample_info(0).sample_state -radix hexadecimal} {/l0_dds_reader_test1/uut/sample_info(0).view_state -radix hexadecimal} {/l0_dds_reader_test1/uut/sample_info(0).instance_state -radix hexadecimal} {/l0_dds_reader_test1/uut/sample_info(0).source_timestamp -radix hexadecimal} {/l0_dds_reader_test1/uut/sample_info(0).instance_handle -radix hexadecimal} {/l0_dds_reader_test1/uut/sample_info(0).publication_handle -radix hexadecimal} {/l0_dds_reader_test1/uut/sample_info(0).disposed_generation_count -radix hexadecimal} {/l0_dds_reader_test1/uut/sample_info(0).no_writers_generation_count -radix hexadecimal} {/l0_dds_reader_test1/uut/sample_info(0).sample_rank -radix hexadecimal} {/l0_dds_reader_test1/uut/sample_info(0).generation_rank -radix hexadecimal} {/l0_dds_reader_test1/uut/sample_info(0).absolute_generation_rank -radix hexadecimal} {/l0_dds_reader_test1/uut/sample_info(0).valid_data -radix hexadecimal}}} {/l0_dds_reader_test1/uut/sample_info(1) -radix hexadecimal} {/l0_dds_reader_test1/uut/sample_info(2) -radix hexadecimal} {/l0_dds_reader_test1/uut/sample_info(3) -radix hexadecimal} {/l0_dds_reader_test1/uut/sample_info(4) -radix hexadecimal} {/l0_dds_reader_test1/uut/sample_info(5) -radix hexadecimal}} -subitemconfig {/l0_dds_reader_test1/uut/sample_info(0) {-height 15 -radix hexadecimal -childformat {{/l0_dds_reader_test1/uut/sample_info(0).sample_state -radix hexadecimal} {/l0_dds_reader_test1/uut/sample_info(0).view_state -radix hexadecimal} {/l0_dds_reader_test1/uut/sample_info(0).instance_state -radix hexadecimal} {/l0_dds_reader_test1/uut/sample_info(0).source_timestamp -radix hexadecimal} {/l0_dds_reader_test1/uut/sample_info(0).instance_handle -radix hexadecimal} {/l0_dds_reader_test1/uut/sample_info(0).publication_handle -radix hexadecimal} {/l0_dds_reader_test1/uut/sample_info(0).disposed_generation_count -radix hexadecimal} {/l0_dds_reader_test1/uut/sample_info(0).no_writers_generation_count -radix hexadecimal} {/l0_dds_reader_test1/uut/sample_info(0).sample_rank -radix hexadecimal} {/l0_dds_reader_test1/uut/sample_info(0).generation_rank -radix hexadecimal} {/l0_dds_reader_test1/uut/sample_info(0).absolute_generation_rank -radix hexadecimal} {/l0_dds_reader_test1/uut/sample_info(0).valid_data -radix hexadecimal}}} /l0_dds_reader_test1/uut/sample_info(0).sample_state {-height 15 -radix hexadecimal} /l0_dds_reader_test1/uut/sample_info(0).view_state {-height 15 -radix hexadecimal} /l0_dds_reader_test1/uut/sample_info(0).instance_state {-height 15 -radix hexadecimal} /l0_dds_reader_test1/uut/sample_info(0).source_timestamp {-height 15 -radix hexadecimal} /l0_dds_reader_test1/uut/sample_info(0).instance_handle {-height 15 -radix hexadecimal} /l0_dds_reader_test1/uut/sample_info(0).publication_handle {-height 15 -radix hexadecimal} /l0_dds_reader_test1/uut/sample_info(0).disposed_generation_count {-height 15 -radix hexadecimal} /l0_dds_reader_test1/uut/sample_info(0).no_writers_generation_count {-height 15 -radix hexadecimal} /l0_dds_reader_test1/uut/sample_info(0).sample_rank {-height 15 -radix hexadecimal} /l0_dds_reader_test1/uut/sample_info(0).generation_rank {-height 15 -radix hexadecimal} /l0_dds_reader_test1/uut/sample_info(0).absolute_generation_rank {-height 15 -radix hexadecimal} /l0_dds_reader_test1/uut/sample_info(0).valid_data {-height 15 -radix hexadecimal} /l0_dds_reader_test1/uut/sample_info(1) {-height 15 -radix hexadecimal} /l0_dds_reader_test1/uut/sample_info(2) {-height 15 -radix hexadecimal} /l0_dds_reader_test1/uut/sample_info(3) {-height 15 -radix hexadecimal} /l0_dds_reader_test1/uut/sample_info(4) {-height 15 -radix hexadecimal} /l0_dds_reader_test1/uut/sample_info(5) {-height 15 -radix hexadecimal}} /l0_dds_reader_test1/uut/sample_info +add wave -noupdate -group DDS /l0_dds_reader_test1/uut/sample_info_valid +add wave -noupdate -group DDS /l0_dds_reader_test1/uut/sample_info_ack +add wave -noupdate -group DDS /l0_dds_reader_test1/uut/eoc +add wave -noupdate -group DDS /l0_dds_reader_test1/uut/get_data_dds +add wave -noupdate -group DDS -divider OUTPUT +add wave -noupdate -group DDS /l0_dds_reader_test1/uut/ready_out_dds +add wave -noupdate -group DDS /l0_dds_reader_test1/uut/valid_out_dds +add wave -noupdate -group DDS -radix hexadecimal /l0_dds_reader_test1/uut/data_out_dds +add wave -noupdate -group DDS /l0_dds_reader_test1/uut/last_word_out_dds +add wave -noupdate -divider {MAIN FSM} +add wave -noupdate /l0_dds_reader_test1/uut/stage +add wave -noupdate /l0_dds_reader_test1/uut/cnt +add wave -noupdate /l0_dds_reader_test1/uut/ind +add wave -noupdate -divider MEMORY +add wave -noupdate /l0_dds_reader_test1/uut/inst_op_start +add wave -noupdate /l0_dds_reader_test1/uut/inst_opcode +add wave -noupdate /l0_dds_reader_test1/uut/inst_op_done +add wave -noupdate /l0_dds_reader_test1/uut/inst_stage +add wave -noupdate /l0_dds_reader_test1/uut/inst_cnt +add wave -noupdate -radix unsigned /l0_dds_reader_test1/uut/inst_addr_base +add wave -noupdate -childformat {{/l0_dds_reader_test1/uut/inst_data.addr -radix unsigned} {/l0_dds_reader_test1/uut/inst_data.key_hash -radix hexadecimal} {/l0_dds_reader_test1/uut/inst_data.status_info -radix binary} {/l0_dds_reader_test1/uut/inst_data.sample_cnt -radix unsigned} {/l0_dds_reader_test1/uut/inst_data.disposed_gen_cnt -radix unsigned} {/l0_dds_reader_test1/uut/inst_data.no_writers_gen_cnt -radix unsigned} {/l0_dds_reader_test1/uut/inst_data.ignore_deadline -radix unsigned} {/l0_dds_reader_test1/uut/inst_data.writer_bitmap -radix binary -childformat {{/l0_dds_reader_test1/uut/inst_data.writer_bitmap(0) -radix binary -childformat {{/l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(0) -radix binary} {/l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(1) -radix binary} {/l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(2) -radix binary} {/l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(3) -radix binary} {/l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(4) -radix binary} {/l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(5) -radix binary} {/l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(6) -radix binary} {/l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(7) -radix binary} {/l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(8) -radix binary} {/l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(9) -radix binary} {/l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(10) -radix binary} {/l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(11) -radix binary} {/l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(12) -radix binary} {/l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(13) -radix binary} {/l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(14) -radix binary} {/l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(15) -radix binary} {/l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(16) -radix binary} {/l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(17) -radix binary} {/l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(18) -radix binary} {/l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(19) -radix binary} {/l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(20) -radix binary} {/l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(21) -radix binary} {/l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(22) -radix binary} {/l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(23) -radix binary} {/l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(24) -radix binary} {/l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(25) -radix binary} {/l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(26) -radix binary} {/l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(27) -radix binary} {/l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(28) -radix binary} {/l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(29) -radix binary} {/l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(30) -radix binary} {/l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(31) -radix binary}}}}}} -expand -subitemconfig {/l0_dds_reader_test1/uut/inst_data.addr {-radix unsigned} /l0_dds_reader_test1/uut/inst_data.key_hash {-height 15 -radix hexadecimal} /l0_dds_reader_test1/uut/inst_data.status_info {-height 15 -radix binary} /l0_dds_reader_test1/uut/inst_data.sample_cnt {-height 15 -radix unsigned} /l0_dds_reader_test1/uut/inst_data.disposed_gen_cnt {-height 15 -radix unsigned} /l0_dds_reader_test1/uut/inst_data.no_writers_gen_cnt {-height 15 -radix unsigned} /l0_dds_reader_test1/uut/inst_data.ignore_deadline {-height 15 -radix unsigned} /l0_dds_reader_test1/uut/inst_data.writer_bitmap {-height 15 -radix binary -childformat {{/l0_dds_reader_test1/uut/inst_data.writer_bitmap(0) -radix binary -childformat {{/l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(0) -radix binary} {/l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(1) -radix binary} {/l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(2) -radix binary} {/l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(3) -radix binary} {/l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(4) -radix binary} {/l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(5) -radix binary} {/l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(6) -radix binary} {/l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(7) -radix binary} {/l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(8) -radix binary} {/l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(9) -radix binary} {/l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(10) -radix binary} {/l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(11) -radix binary} {/l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(12) -radix binary} {/l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(13) -radix binary} {/l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(14) -radix binary} {/l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(15) -radix binary} {/l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(16) -radix binary} {/l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(17) -radix binary} {/l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(18) -radix binary} {/l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(19) -radix binary} {/l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(20) -radix binary} {/l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(21) -radix binary} {/l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(22) -radix binary} {/l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(23) -radix binary} {/l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(24) -radix binary} {/l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(25) -radix binary} {/l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(26) -radix binary} {/l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(27) -radix binary} {/l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(28) -radix binary} {/l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(29) -radix binary} {/l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(30) -radix binary} {/l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(31) -radix binary}}}}} /l0_dds_reader_test1/uut/inst_data.writer_bitmap(0) {-height 15 -radix binary -childformat {{/l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(0) -radix binary} {/l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(1) -radix binary} {/l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(2) -radix binary} {/l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(3) -radix binary} {/l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(4) -radix binary} {/l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(5) -radix binary} {/l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(6) -radix binary} {/l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(7) -radix binary} {/l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(8) -radix binary} {/l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(9) -radix binary} {/l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(10) -radix binary} {/l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(11) -radix binary} {/l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(12) -radix binary} {/l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(13) -radix binary} {/l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(14) -radix binary} {/l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(15) -radix binary} {/l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(16) -radix binary} {/l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(17) -radix binary} {/l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(18) -radix binary} {/l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(19) -radix binary} {/l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(20) -radix binary} {/l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(21) -radix binary} {/l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(22) -radix binary} {/l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(23) -radix binary} {/l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(24) -radix binary} {/l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(25) -radix binary} {/l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(26) -radix binary} {/l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(27) -radix binary} {/l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(28) -radix binary} {/l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(29) -radix binary} {/l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(30) -radix binary} {/l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(31) -radix binary}}} /l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(0) {-height 15 -radix binary} /l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(1) {-height 15 -radix binary} /l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(2) {-height 15 -radix binary} /l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(3) {-height 15 -radix binary} /l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(4) {-height 15 -radix binary} /l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(5) {-height 15 -radix binary} /l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(6) {-height 15 -radix binary} /l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(7) {-height 15 -radix binary} /l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(8) {-height 15 -radix binary} /l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(9) {-height 15 -radix binary} /l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(10) {-height 15 -radix binary} /l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(11) {-height 15 -radix binary} /l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(12) {-height 15 -radix binary} /l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(13) {-height 15 -radix binary} /l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(14) {-height 15 -radix binary} /l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(15) {-height 15 -radix binary} /l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(16) {-height 15 -radix binary} /l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(17) {-height 15 -radix binary} /l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(18) {-height 15 -radix binary} /l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(19) {-height 15 -radix binary} /l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(20) {-height 15 -radix binary} /l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(21) {-height 15 -radix binary} /l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(22) {-height 15 -radix binary} /l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(23) {-height 15 -radix binary} /l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(24) {-height 15 -radix binary} /l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(25) {-height 15 -radix binary} /l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(26) {-height 15 -radix binary} /l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(27) {-height 15 -radix binary} /l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(28) {-height 15 -radix binary} /l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(29) {-height 15 -radix binary} /l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(30) {-height 15 -radix binary} /l0_dds_reader_test1/uut/inst_data.writer_bitmap(0)(31) {-height 15 -radix binary}} /l0_dds_reader_test1/uut/inst_data +add wave -noupdate /l0_dds_reader_test1/uut/stale_inst_cnt +add wave -noupdate -group {SAMPLE MEM} -radix unsigned /l0_dds_reader_test1/uut/sample_addr +add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test1/uut/sample_read +add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test1/uut/sample_ready_in +add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test1/uut/sample_valid_in +add wave -noupdate -group {SAMPLE MEM} -radix hexadecimal /l0_dds_reader_test1/uut/sample_write_data +add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test1/uut/sample_ready_out +add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test1/uut/sample_valid_out +add wave -noupdate -group {SAMPLE MEM} -radix hexadecimal /l0_dds_reader_test1/uut/sample_read_data +add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test1/uut/sample_abort_read +add wave -noupdate -group {PAYLOAD MEM} -radix unsigned /l0_dds_reader_test1/uut/payload_addr +add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test1/uut/payload_read +add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test1/uut/payload_ready_in +add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test1/uut/payload_valid_in +add wave -noupdate -group {PAYLOAD MEM} -radix hexadecimal /l0_dds_reader_test1/uut/payload_write_data +add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test1/uut/payload_ready_out +add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test1/uut/payload_valid_out +add wave -noupdate -group {PAYLOAD MEM} -radix hexadecimal /l0_dds_reader_test1/uut/payload_read_data +add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test1/uut/payload_abort_read +add wave -noupdate -group {INSTANCE MEM} -radix unsigned /l0_dds_reader_test1/uut/inst_addr +add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test1/uut/inst_read +add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test1/uut/inst_ready_in +add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test1/uut/inst_valid_in +add wave -noupdate -group {INSTANCE MEM} -radix hexadecimal /l0_dds_reader_test1/uut/inst_write_data +add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test1/uut/inst_ready_out +add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test1/uut/inst_valid_out +add wave -noupdate -group {INSTANCE MEM} -radix hexadecimal /l0_dds_reader_test1/uut/inst_read_data +add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test1/uut/inst_abort_read +add wave -noupdate -divider POINTERS +add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test1/uut/empty_sample_list_head +add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test1/uut/empty_sample_list_tail +add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test1/uut/empty_payload_list_head +add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test1/uut/oldest_sample +add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test1/uut/newest_sample +add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test1/uut/inst_empty_head +add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test1/uut/inst_occupied_head +add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test1/uut/cur_sample +add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test1/uut/next_sample +add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test1/uut/prev_sample +add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test1/uut/cur_payload +add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test1/uut/next_payload +add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test1/uut/cur_inst +add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test1/uut/next_inst +add wave -noupdate -divider MISC +add wave -noupdate /l0_dds_reader_test1/uut/trigger_sample_gen +add wave -noupdate /l0_dds_reader_test1/uut/wait_for_sample_removal +add wave -noupdate -radix unsigned /l0_dds_reader_test1/uut/sample_p1 +add wave -noupdate -radix unsigned /l0_dds_reader_test1/uut/sample_p2 +add wave -noupdate -radix unsigned /l0_dds_reader_test1/uut/collection_cnt +add wave -noupdate -radix unsigned /l0_dds_reader_test1/uut/collection_cnt_max +add wave -noupdate -radix unsigned /l0_dds_reader_test1/uut/collection_generation_rank +add wave -noupdate -radix unsigned /l0_dds_reader_test1/uut/cur_generation_rank +add wave -noupdate -radix unsigned -childformat {{/l0_dds_reader_test1/uut/max_samples_latch(31) -radix unsigned} {/l0_dds_reader_test1/uut/max_samples_latch(30) -radix unsigned} {/l0_dds_reader_test1/uut/max_samples_latch(29) -radix unsigned} {/l0_dds_reader_test1/uut/max_samples_latch(28) -radix unsigned} {/l0_dds_reader_test1/uut/max_samples_latch(27) -radix unsigned} {/l0_dds_reader_test1/uut/max_samples_latch(26) -radix unsigned} {/l0_dds_reader_test1/uut/max_samples_latch(25) -radix unsigned} {/l0_dds_reader_test1/uut/max_samples_latch(24) -radix unsigned} {/l0_dds_reader_test1/uut/max_samples_latch(23) -radix unsigned} {/l0_dds_reader_test1/uut/max_samples_latch(22) -radix unsigned} {/l0_dds_reader_test1/uut/max_samples_latch(21) -radix unsigned} {/l0_dds_reader_test1/uut/max_samples_latch(20) -radix unsigned} {/l0_dds_reader_test1/uut/max_samples_latch(19) -radix unsigned} {/l0_dds_reader_test1/uut/max_samples_latch(18) -radix unsigned} {/l0_dds_reader_test1/uut/max_samples_latch(17) -radix unsigned} {/l0_dds_reader_test1/uut/max_samples_latch(16) -radix unsigned} {/l0_dds_reader_test1/uut/max_samples_latch(15) -radix unsigned} {/l0_dds_reader_test1/uut/max_samples_latch(14) -radix unsigned} {/l0_dds_reader_test1/uut/max_samples_latch(13) -radix unsigned} {/l0_dds_reader_test1/uut/max_samples_latch(12) -radix unsigned} {/l0_dds_reader_test1/uut/max_samples_latch(11) -radix unsigned} {/l0_dds_reader_test1/uut/max_samples_latch(10) -radix unsigned} {/l0_dds_reader_test1/uut/max_samples_latch(9) -radix unsigned} {/l0_dds_reader_test1/uut/max_samples_latch(8) -radix unsigned} {/l0_dds_reader_test1/uut/max_samples_latch(7) -radix unsigned} {/l0_dds_reader_test1/uut/max_samples_latch(6) -radix unsigned} {/l0_dds_reader_test1/uut/max_samples_latch(5) -radix unsigned} {/l0_dds_reader_test1/uut/max_samples_latch(4) -radix unsigned} {/l0_dds_reader_test1/uut/max_samples_latch(3) -radix unsigned} {/l0_dds_reader_test1/uut/max_samples_latch(2) -radix unsigned} {/l0_dds_reader_test1/uut/max_samples_latch(1) -radix unsigned} {/l0_dds_reader_test1/uut/max_samples_latch(0) -radix unsigned}} -subitemconfig {/l0_dds_reader_test1/uut/max_samples_latch(31) {-height 15 -radix unsigned} /l0_dds_reader_test1/uut/max_samples_latch(30) {-height 15 -radix unsigned} /l0_dds_reader_test1/uut/max_samples_latch(29) {-height 15 -radix unsigned} /l0_dds_reader_test1/uut/max_samples_latch(28) {-height 15 -radix unsigned} /l0_dds_reader_test1/uut/max_samples_latch(27) {-height 15 -radix unsigned} /l0_dds_reader_test1/uut/max_samples_latch(26) {-height 15 -radix unsigned} /l0_dds_reader_test1/uut/max_samples_latch(25) {-height 15 -radix unsigned} /l0_dds_reader_test1/uut/max_samples_latch(24) {-height 15 -radix unsigned} /l0_dds_reader_test1/uut/max_samples_latch(23) {-height 15 -radix unsigned} /l0_dds_reader_test1/uut/max_samples_latch(22) {-height 15 -radix unsigned} /l0_dds_reader_test1/uut/max_samples_latch(21) {-height 15 -radix unsigned} /l0_dds_reader_test1/uut/max_samples_latch(20) {-height 15 -radix unsigned} /l0_dds_reader_test1/uut/max_samples_latch(19) {-height 15 -radix unsigned} /l0_dds_reader_test1/uut/max_samples_latch(18) {-height 15 -radix unsigned} /l0_dds_reader_test1/uut/max_samples_latch(17) {-height 15 -radix unsigned} /l0_dds_reader_test1/uut/max_samples_latch(16) {-height 15 -radix unsigned} /l0_dds_reader_test1/uut/max_samples_latch(15) {-height 15 -radix unsigned} /l0_dds_reader_test1/uut/max_samples_latch(14) {-height 15 -radix unsigned} /l0_dds_reader_test1/uut/max_samples_latch(13) {-height 15 -radix unsigned} /l0_dds_reader_test1/uut/max_samples_latch(12) {-height 15 -radix unsigned} /l0_dds_reader_test1/uut/max_samples_latch(11) {-height 15 -radix unsigned} /l0_dds_reader_test1/uut/max_samples_latch(10) {-height 15 -radix unsigned} /l0_dds_reader_test1/uut/max_samples_latch(9) {-height 15 -radix unsigned} /l0_dds_reader_test1/uut/max_samples_latch(8) {-height 15 -radix unsigned} /l0_dds_reader_test1/uut/max_samples_latch(7) {-height 15 -radix unsigned} /l0_dds_reader_test1/uut/max_samples_latch(6) {-height 15 -radix unsigned} /l0_dds_reader_test1/uut/max_samples_latch(5) {-height 15 -radix unsigned} /l0_dds_reader_test1/uut/max_samples_latch(4) {-height 15 -radix unsigned} /l0_dds_reader_test1/uut/max_samples_latch(3) {-height 15 -radix unsigned} /l0_dds_reader_test1/uut/max_samples_latch(2) {-height 15 -radix unsigned} /l0_dds_reader_test1/uut/max_samples_latch(1) {-height 15 -radix unsigned} /l0_dds_reader_test1/uut/max_samples_latch(0) {-height 15 -radix unsigned}} /l0_dds_reader_test1/uut/max_samples_latch +add wave -noupdate /l0_dds_reader_test1/uut/single_instance +add wave -noupdate /l0_dds_reader_test1/uut/is_take +add wave -noupdate -radix unsigned -childformat {{/l0_dds_reader_test1/uut/sample_rej_last_reason(0) -radix LAST_REASON} {/l0_dds_reader_test1/uut/sample_rej_last_reason(1) -radix LAST_REASON} {/l0_dds_reader_test1/uut/sample_rej_last_reason(2) -radix LAST_REASON} {/l0_dds_reader_test1/uut/sample_rej_last_reason(3) -radix LAST_REASON} {/l0_dds_reader_test1/uut/sample_rej_last_reason(4) -radix LAST_REASON} {/l0_dds_reader_test1/uut/sample_rej_last_reason(5) -radix LAST_REASON}} -subitemconfig {/l0_dds_reader_test1/uut/sample_rej_last_reason(0) {-radix LAST_REASON} /l0_dds_reader_test1/uut/sample_rej_last_reason(1) {-radix LAST_REASON} /l0_dds_reader_test1/uut/sample_rej_last_reason(2) {-radix LAST_REASON} /l0_dds_reader_test1/uut/sample_rej_last_reason(3) {-radix LAST_REASON} /l0_dds_reader_test1/uut/sample_rej_last_reason(4) {-radix LAST_REASON} /l0_dds_reader_test1/uut/sample_rej_last_reason(5) {-radix LAST_REASON}} /l0_dds_reader_test1/uut/sample_rej_last_reason +add wave -noupdate -divider TESTBENCH +add wave -noupdate -group TESTBENCH /l0_dds_reader_test1/dds_start +add wave -noupdate -group TESTBENCH /l0_dds_reader_test1/dds_stage +add wave -noupdate -group TESTBENCH /l0_dds_reader_test1/dds_cnt +add wave -noupdate -group TESTBENCH /l0_dds_reader_test1/dds_cnt2 +add wave -noupdate -group TESTBENCH /l0_dds_reader_test1/dds_done +add wave -noupdate -group TESTBENCH /l0_dds_reader_test1/rtps_start +add wave -noupdate -group TESTBENCH /l0_dds_reader_test1/rtps_stage +add wave -noupdate -group TESTBENCH /l0_dds_reader_test1/rtps_cnt +add wave -noupdate -group TESTBENCH /l0_dds_reader_test1/rtps_done +add wave -noupdate -divider {KEY HOLDER} +add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test1/uut/start_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test1/uut/opcode_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test1/uut/ack_kh +add wave -noupdate -group {KEY HOLDER} -radix hexadecimal /l0_dds_reader_test1/uut/data_in_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test1/uut/valid_in_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test1/uut/ready_in_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test1/uut/last_word_in_kh +add wave -noupdate -group {KEY HOLDER} -radix hexadecimal /l0_dds_reader_test1/uut/data_out_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test1/uut/valid_out_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test1/uut/ready_out_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test1/uut/last_word_out_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test1/uut/abort_kh +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {50639746 ps} 0} +quietly wave cursor active 1 +configure wave -namecolwidth 187 +configure wave -valuecolwidth 206 +configure wave -justifyvalue left +configure wave -signalnamewidth 1 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ns +update +WaveRestoreZoom {50034942 ps} {50968663 ps} diff --git a/sim/L0_dds_reader_test1_abzkriu.do b/sim/L0_dds_reader_test1_abzkriu.do deleted file mode 100644 index 0649aaa..0000000 --- a/sim/L0_dds_reader_test1_abzkriu.do +++ /dev/null @@ -1,196 +0,0 @@ -onerror {resume} -radix define DDS_RETCODE { - "10#0#" "RETCODE_OK", - "10#1#" "RETCODE_ERROR", - "10#2#" "RETCODE_UNSUPPORTED", - "10#3#" "RETCODE_BAD_PARAMETER", - "10#4#" "RETCODE_PRECONDITION_NOT_MET", - "10#5#" "RETCODE_OUT_OF_RESOURCES", - "10#6#" "RETCODE_NOT_ENABLED", - "10#7#" "RETCODE_IMMUTABLE_POLICY", - "10#8#" "RETCODE_INCONSISTENT_POLICY", - "10#9#" "RETCODE_ALREADY_DELETED", - "10#10#" "RETCODE_TIMEOUT", - "10#11#" "RETCODE_NO_DATA", - "10#12#" "RETCODE_ILLEGAL_OPERATION", - -default unsigned -} -radix define SAMPLE_STATE { - "16#00000001#" "READ_SAMPLE_STATE", - "16#00000002#" "NOT_READ_SAMPLE_STATE", - "16#FFFFFFFF#" "ANY_SAMPLE_STATE", - -default binary -} -radix define VIEW_STATE { - "16#00000001#" "NEW_VIEW_STATE", - "16#00000002#" "NOT_NEW_VIEW_STATE", - "16#FFFFFFFF#" "ANY_VIEW_STATE", - -default binary -} -radix define INSTANCE_STATE { - "16#00000001#" "ALIVE_INSTANCE_STATE", - "16#00000002#" "NOT_ALIVE_DISPOSED_INSTANCE_STATE", - "16#00000004#" "NOT_ALIVE_NO_WRITERS_INSTANCE_STATE", - "16#FFFFFFFF#" "ANY_INSTANCE_STATE", - -default binary -} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -divider SYSTEM -add wave -noupdate /l0_dds_reader_test1_abzkriu/uut/clk -add wave -noupdate /l0_dds_reader_test1_abzkriu/uut/reset -add wave -noupdate /l0_dds_reader_test1_abzkriu/uut/time -add wave -noupdate -divider RTPS -add wave -noupdate -expand -group RTPS /l0_dds_reader_test1_abzkriu/uut/start_rtps -add wave -noupdate -expand -group RTPS /l0_dds_reader_test1_abzkriu/uut/opcode_rtps -add wave -noupdate -expand -group RTPS /l0_dds_reader_test1_abzkriu/uut/ack_rtps -add wave -noupdate -expand -group RTPS /l0_dds_reader_test1_abzkriu/uut/ret_rtps -add wave -noupdate -expand -group RTPS /l0_dds_reader_test1_abzkriu/uut/done_rtps -add wave -noupdate -expand -group RTPS /l0_dds_reader_test1_abzkriu/uut/ready_in_rtps -add wave -noupdate -expand -group RTPS /l0_dds_reader_test1_abzkriu/uut/valid_in_rtps -add wave -noupdate -expand -group RTPS -radix hexadecimal /l0_dds_reader_test1_abzkriu/uut/data_in_rtps -add wave -noupdate -expand -group RTPS /l0_dds_reader_test1_abzkriu/uut/last_word_in_rtps -add wave -noupdate -divider DDS -add wave -noupdate -group DDS /l0_dds_reader_test1_abzkriu/uut/start_dds -add wave -noupdate -group DDS /l0_dds_reader_test1_abzkriu/uut/ack_dds -add wave -noupdate -group DDS /l0_dds_reader_test1_abzkriu/uut/opcode_dds -add wave -noupdate -group DDS -radix SAMPLE_STATE /l0_dds_reader_test1_abzkriu/uut/sample_state_dds -add wave -noupdate -group DDS -radix INSTANCE_STATE /l0_dds_reader_test1_abzkriu/uut/instance_state_dds -add wave -noupdate -group DDS -radix VIEW_STATE /l0_dds_reader_test1_abzkriu/uut/view_state_dds -add wave -noupdate -group DDS -radix hexadecimal /l0_dds_reader_test1_abzkriu/uut/instance_handle_dds -add wave -noupdate -group DDS -radix unsigned /l0_dds_reader_test1_abzkriu/uut/max_samples_dds -add wave -noupdate -group DDS -radix DDS_RETCODE /l0_dds_reader_test1_abzkriu/uut/return_code_dds -add wave -noupdate -group DDS /l0_dds_reader_test1_abzkriu/uut/done_dds -add wave -noupdate -group DDS -divider SI -add wave -noupdate -group DDS -radix SAMPLE_STATE /l0_dds_reader_test1_abzkriu/uut/si_sample_state -add wave -noupdate -group DDS -radix VIEW_STATE /l0_dds_reader_test1_abzkriu/uut/si_view_state -add wave -noupdate -group DDS -radix INSTANCE_STATE /l0_dds_reader_test1_abzkriu/uut/si_instance_state -add wave -noupdate -group DDS -radix unsigned /l0_dds_reader_test1_abzkriu/uut/si_source_timestamp -add wave -noupdate -group DDS -radix hexadecimal /l0_dds_reader_test1_abzkriu/uut/si_instance_handle -add wave -noupdate -group DDS -radix hexadecimal /l0_dds_reader_test1_abzkriu/uut/si_publication_handle -add wave -noupdate -group DDS -radix unsigned /l0_dds_reader_test1_abzkriu/uut/si_disposed_generation_count -add wave -noupdate -group DDS -radix unsigned /l0_dds_reader_test1_abzkriu/uut/si_no_writers_generation_count -add wave -noupdate -group DDS -radix unsigned /l0_dds_reader_test1_abzkriu/uut/si_sample_rank -add wave -noupdate -group DDS -radix unsigned /l0_dds_reader_test1_abzkriu/uut/si_generation_rank -add wave -noupdate -group DDS -radix unsigned /l0_dds_reader_test1_abzkriu/uut/si_absolute_generation_rank -add wave -noupdate -group DDS /l0_dds_reader_test1_abzkriu/uut/si_valid_data -add wave -noupdate -group DDS /l0_dds_reader_test1_abzkriu/uut/si_valid -add wave -noupdate -group DDS /l0_dds_reader_test1_abzkriu/uut/eoc -add wave -noupdate -group DDS /l0_dds_reader_test1_abzkriu/uut/get_data_dds -add wave -noupdate -group DDS -divider OUTPUT -add wave -noupdate -group DDS /l0_dds_reader_test1_abzkriu/uut/ready_out_dds -add wave -noupdate -group DDS /l0_dds_reader_test1_abzkriu/uut/valid_out_dds -add wave -noupdate -group DDS -radix hexadecimal /l0_dds_reader_test1_abzkriu/uut/data_out_dds -add wave -noupdate -group DDS /l0_dds_reader_test1_abzkriu/uut/last_word_out_dds -add wave -noupdate -divider {MAIN FSM} -add wave -noupdate /l0_dds_reader_test1_abzkriu/uut/stage -add wave -noupdate /l0_dds_reader_test1_abzkriu/uut/stage_next -add wave -noupdate /l0_dds_reader_test1_abzkriu/uut/cnt -add wave -noupdate -divider MEMORY -add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test1_abzkriu/uut/sample_abort_read -add wave -noupdate -group {SAMPLE MEM} -radix unsigned /l0_dds_reader_test1_abzkriu/uut/sample_mem_ctrl_inst/addr -add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test1_abzkriu/uut/sample_mem_ctrl_inst/read -add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test1_abzkriu/uut/sample_mem_ctrl_inst/ready_in -add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test1_abzkriu/uut/sample_mem_ctrl_inst/valid_in -add wave -noupdate -group {SAMPLE MEM} -radix hexadecimal /l0_dds_reader_test1_abzkriu/uut/sample_mem_ctrl_inst/data_in -add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test1_abzkriu/uut/sample_mem_ctrl_inst/ready_out -add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test1_abzkriu/uut/sample_mem_ctrl_inst/valid_out -add wave -noupdate -group {SAMPLE MEM} -radix hexadecimal /l0_dds_reader_test1_abzkriu/uut/sample_mem_ctrl_inst/data_out -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test1_abzkriu/uut/payload_abort_read -add wave -noupdate -group {PAYLOAD MEM} -radix unsigned /l0_dds_reader_test1_abzkriu/uut/payload_mem_ctrl_inst/addr -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test1_abzkriu/uut/payload_mem_ctrl_inst/read -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test1_abzkriu/uut/payload_mem_ctrl_inst/ready_in -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test1_abzkriu/uut/payload_mem_ctrl_inst/valid_in -add wave -noupdate -group {PAYLOAD MEM} -radix hexadecimal /l0_dds_reader_test1_abzkriu/uut/payload_mem_ctrl_inst/data_in -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test1_abzkriu/uut/payload_mem_ctrl_inst/ready_out -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test1_abzkriu/uut/payload_mem_ctrl_inst/valid_out -add wave -noupdate -group {PAYLOAD MEM} -radix hexadecimal /l0_dds_reader_test1_abzkriu/uut/payload_mem_ctrl_inst/data_out -add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test1_abzkriu/uut/inst_abort_read -add wave -noupdate -group {INSTANCE MEM} -radix unsigned /l0_dds_reader_test1_abzkriu/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/addr -add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test1_abzkriu/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/read -add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test1_abzkriu/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/ready_in -add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test1_abzkriu/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/valid_in -add wave -noupdate -group {INSTANCE MEM} -radix hexadecimal /l0_dds_reader_test1_abzkriu/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/data_in -add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test1_abzkriu/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/ready_out -add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test1_abzkriu/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/valid_out -add wave -noupdate -group {INSTANCE MEM} -radix hexadecimal /l0_dds_reader_test1_abzkriu/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/data_out -add wave -noupdate /l0_dds_reader_test1_abzkriu/uut/inst_op_start -add wave -noupdate /l0_dds_reader_test1_abzkriu/uut/inst_opcode -add wave -noupdate /l0_dds_reader_test1_abzkriu/uut/inst_op_done -add wave -noupdate /l0_dds_reader_test1_abzkriu/uut/inst_stage -add wave -noupdate /l0_dds_reader_test1_abzkriu/uut/inst_stage_next -add wave -noupdate /l0_dds_reader_test1_abzkriu/uut/inst_cnt -add wave -noupdate -radix unsigned /l0_dds_reader_test1_abzkriu/uut/inst_addr_base -add wave -noupdate /l0_dds_reader_test1_abzkriu/uut/inst_mem_fields -add wave -noupdate -childformat {{/l0_dds_reader_test1_abzkriu/uut/inst_data.key_hash -radix hexadecimal} {/l0_dds_reader_test1_abzkriu/uut/inst_data.status_info -radix binary} {/l0_dds_reader_test1_abzkriu/uut/inst_data.sample_cnt -radix unsigned} {/l0_dds_reader_test1_abzkriu/uut/inst_data.disposed_gen_cnt -radix unsigned} {/l0_dds_reader_test1_abzkriu/uut/inst_data.no_writers_gen_cnt -radix unsigned} {/l0_dds_reader_test1_abzkriu/uut/inst_data.ignore_deadline -radix unsigned} {/l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap -radix binary -childformat {{/l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0) -radix binary -childformat {{/l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(0) -radix binary} {/l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(1) -radix binary} {/l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(2) -radix binary} {/l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(3) -radix binary} {/l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(4) -radix binary} {/l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(5) -radix binary} {/l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(6) -radix binary} {/l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(7) -radix binary} {/l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(8) -radix binary} {/l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(9) -radix binary} {/l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(10) -radix binary} {/l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(11) -radix binary} {/l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(12) -radix binary} {/l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(13) -radix binary} {/l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(14) -radix binary} {/l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(15) -radix binary} {/l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(16) -radix binary} {/l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(17) -radix binary} {/l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(18) -radix binary} {/l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(19) -radix binary} {/l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(20) -radix binary} {/l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(21) -radix binary} {/l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(22) -radix binary} {/l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(23) -radix binary} {/l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(24) -radix binary} {/l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(25) -radix binary} {/l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(26) -radix binary} {/l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(27) -radix binary} {/l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(28) -radix binary} {/l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(29) -radix binary} {/l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(30) -radix binary} {/l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(31) -radix binary}}}}}} -expand -subitemconfig {/l0_dds_reader_test1_abzkriu/uut/inst_data.key_hash {-height 15 -radix hexadecimal} /l0_dds_reader_test1_abzkriu/uut/inst_data.status_info {-height 15 -radix binary} /l0_dds_reader_test1_abzkriu/uut/inst_data.sample_cnt {-height 15 -radix unsigned} /l0_dds_reader_test1_abzkriu/uut/inst_data.disposed_gen_cnt {-height 15 -radix unsigned} /l0_dds_reader_test1_abzkriu/uut/inst_data.no_writers_gen_cnt {-height 15 -radix unsigned} /l0_dds_reader_test1_abzkriu/uut/inst_data.ignore_deadline {-height 15 -radix unsigned} /l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap {-height 15 -radix binary -childformat {{/l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0) -radix binary -childformat {{/l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(0) -radix binary} {/l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(1) -radix binary} {/l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(2) -radix binary} {/l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(3) -radix binary} {/l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(4) -radix binary} {/l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(5) -radix binary} {/l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(6) -radix binary} {/l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(7) -radix binary} {/l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(8) -radix binary} {/l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(9) -radix binary} {/l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(10) -radix binary} {/l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(11) -radix binary} {/l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(12) -radix binary} {/l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(13) -radix binary} {/l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(14) -radix binary} {/l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(15) -radix binary} {/l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(16) -radix binary} {/l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(17) -radix binary} {/l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(18) -radix binary} {/l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(19) -radix binary} {/l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(20) -radix binary} {/l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(21) -radix binary} {/l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(22) -radix binary} {/l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(23) -radix binary} {/l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(24) -radix binary} {/l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(25) -radix binary} {/l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(26) -radix binary} {/l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(27) -radix binary} {/l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(28) -radix binary} {/l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(29) -radix binary} {/l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(30) -radix binary} {/l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(31) -radix binary}}}}} /l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0) {-height 15 -radix binary -childformat {{/l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(0) -radix binary} {/l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(1) -radix binary} {/l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(2) -radix binary} {/l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(3) -radix binary} {/l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(4) -radix binary} {/l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(5) -radix binary} {/l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(6) -radix binary} {/l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(7) -radix binary} {/l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(8) -radix binary} {/l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(9) -radix binary} {/l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(10) -radix binary} {/l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(11) -radix binary} {/l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(12) -radix binary} {/l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(13) -radix binary} {/l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(14) -radix binary} {/l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(15) -radix binary} {/l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(16) -radix binary} {/l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(17) -radix binary} {/l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(18) -radix binary} {/l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(19) -radix binary} {/l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(20) -radix binary} {/l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(21) -radix binary} {/l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(22) -radix binary} {/l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(23) -radix binary} {/l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(24) -radix binary} {/l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(25) -radix binary} {/l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(26) -radix binary} {/l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(27) -radix binary} {/l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(28) -radix binary} {/l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(29) -radix binary} {/l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(30) -radix binary} {/l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(31) -radix binary}}} /l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(0) {-height 15 -radix binary} /l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(1) {-height 15 -radix binary} /l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(2) {-height 15 -radix binary} /l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(3) {-height 15 -radix binary} /l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(4) {-height 15 -radix binary} /l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(5) {-height 15 -radix binary} /l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(6) {-height 15 -radix binary} /l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(7) {-height 15 -radix binary} /l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(8) {-height 15 -radix binary} /l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(9) {-height 15 -radix binary} /l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(10) {-height 15 -radix binary} /l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(11) {-height 15 -radix binary} /l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(12) {-height 15 -radix binary} /l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(13) {-height 15 -radix binary} /l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(14) {-height 15 -radix binary} /l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(15) {-height 15 -radix binary} /l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(16) {-height 15 -radix binary} /l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(17) {-height 15 -radix binary} /l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(18) {-height 15 -radix binary} /l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(19) {-height 15 -radix binary} /l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(20) {-height 15 -radix binary} /l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(21) {-height 15 -radix binary} /l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(22) {-height 15 -radix binary} /l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(23) {-height 15 -radix binary} /l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(24) {-height 15 -radix binary} /l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(25) {-height 15 -radix binary} /l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(26) {-height 15 -radix binary} /l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(27) {-height 15 -radix binary} /l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(28) {-height 15 -radix binary} /l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(29) {-height 15 -radix binary} /l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(30) {-height 15 -radix binary} /l0_dds_reader_test1_abzkriu/uut/inst_data.writer_bitmap(0)(31) {-height 15 -radix binary}} /l0_dds_reader_test1_abzkriu/uut/inst_data -add wave -noupdate -radix unsigned /l0_dds_reader_test1_abzkriu/uut/inst_next_addr_base -add wave -noupdate -radix unsigned /l0_dds_reader_test1_abzkriu/uut/inst_prev_addr_base -add wave -noupdate /l0_dds_reader_test1_abzkriu/uut/current_imf -add wave -noupdate /l0_dds_reader_test1_abzkriu/uut/stale_inst_cnt -add wave -noupdate -divider POINTERS -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test1_abzkriu/uut/empty_sample_list_head -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test1_abzkriu/uut/empty_sample_list_tail -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test1_abzkriu/uut/empty_payload_list_head -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test1_abzkriu/uut/oldest_sample -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test1_abzkriu/uut/newest_sample -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test1_abzkriu/uut/inst_empty_head -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test1_abzkriu/uut/inst_occupied_head -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test1_abzkriu/uut/cur_sample -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test1_abzkriu/uut/next_sample -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test1_abzkriu/uut/prev_sample -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test1_abzkriu/uut/cur_payload -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test1_abzkriu/uut/next_payload -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test1_abzkriu/uut/cur_inst -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test1_abzkriu/uut/next_inst -add wave -noupdate -divider MISC -add wave -noupdate /l0_dds_reader_test1_abzkriu/uut/trigger_sample_gen -add wave -noupdate /l0_dds_reader_test1_abzkriu/uut/wait_for_sample_removal -add wave -noupdate /l0_dds_reader_test1_abzkriu/uut/sample_p1 -add wave -noupdate /l0_dds_reader_test1_abzkriu/uut/sample_p2 -add wave -noupdate -radix unsigned /l0_dds_reader_test1_abzkriu/uut/collection_cnt -add wave -noupdate -radix unsigned /l0_dds_reader_test1_abzkriu/uut/collection_cnt_max -add wave -noupdate -radix unsigned /l0_dds_reader_test1_abzkriu/uut/collection_generation_rank -add wave -noupdate -radix unsigned /l0_dds_reader_test1_abzkriu/uut/cur_generation_rank -add wave -noupdate -radix unsigned /l0_dds_reader_test1_abzkriu/uut/max_samples_latch -add wave -noupdate /l0_dds_reader_test1_abzkriu/uut/single_instance -add wave -noupdate /l0_dds_reader_test1_abzkriu/uut/is_take -add wave -noupdate -divider TESTBENCH -add wave -noupdate -group TESTBENCH /l0_dds_reader_test1_abzkriu/dds_start -add wave -noupdate -group TESTBENCH /l0_dds_reader_test1_abzkriu/dds_stage -add wave -noupdate -group TESTBENCH /l0_dds_reader_test1_abzkriu/dds_cnt -add wave -noupdate -group TESTBENCH /l0_dds_reader_test1_abzkriu/dds_cnt2 -add wave -noupdate -group TESTBENCH /l0_dds_reader_test1_abzkriu/dds_done -add wave -noupdate -group TESTBENCH /l0_dds_reader_test1_abzkriu/rtps_start -add wave -noupdate -group TESTBENCH /l0_dds_reader_test1_abzkriu/rtps_stage -add wave -noupdate -group TESTBENCH /l0_dds_reader_test1_abzkriu/rtps_cnt -add wave -noupdate -group TESTBENCH /l0_dds_reader_test1_abzkriu/rtps_done -add wave -noupdate -divider {KEY HOLDER} -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test1_abzkriu/uut/start_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test1_abzkriu/uut/opcode_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test1_abzkriu/uut/ack_kh -add wave -noupdate -group {KEY HOLDER} -radix hexadecimal /l0_dds_reader_test1_abzkriu/uut/data_in_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test1_abzkriu/uut/valid_in_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test1_abzkriu/uut/ready_in_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test1_abzkriu/uut/last_word_in_kh -add wave -noupdate -group {KEY HOLDER} -radix hexadecimal /l0_dds_reader_test1_abzkriu/uut/data_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test1_abzkriu/uut/valid_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test1_abzkriu/uut/ready_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test1_abzkriu/uut/last_word_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test1_abzkriu/uut/abort_kh -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {77695423 ps} 0} {{Cursor 2} {115175000 ps} 1} -quietly wave cursor active 1 -configure wave -namecolwidth 187 -configure wave -valuecolwidth 206 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -configure wave -timelineunits ns -update -WaveRestoreZoom {76925214 ps} {77858935 ps} diff --git a/sim/L0_dds_reader_test1_arzkriu.do b/sim/L0_dds_reader_test1_arzkriu.do deleted file mode 100644 index 05c04d0..0000000 --- a/sim/L0_dds_reader_test1_arzkriu.do +++ /dev/null @@ -1,180 +0,0 @@ -onerror {resume} -radix define DDS_RETCODE { - "10#0#" "RETCODE_OK", - "10#1#" "RETCODE_ERROR", - "10#2#" "RETCODE_UNSUPPORTED", - "10#3#" "RETCODE_BAD_PARAMETER", - "10#4#" "RETCODE_PRECONDITION_NOT_MET", - "10#5#" "RETCODE_OUT_OF_RESOURCES", - "10#6#" "RETCODE_NOT_ENABLED", - "10#7#" "RETCODE_IMMUTABLE_POLICY", - "10#8#" "RETCODE_INCONSISTENT_POLICY", - "10#9#" "RETCODE_ALREADY_DELETED", - "10#10#" "RETCODE_TIMEOUT", - "10#11#" "RETCODE_NO_DATA", - "10#12#" "RETCODE_ILLEGAL_OPERATION", - -default unsigned -} -radix define SAMPLE_STATE { - "16#00000001#" "READ_SAMPLE_STATE", - "16#00000002#" "NOT_READ_SAMPLE_STATE", - "16#FFFFFFFF#" "ANY_SAMPLE_STATE", - -default binary -} -radix define VIEW_STATE { - "16#00000001#" "NEW_VIEW_STATE", - "16#00000002#" "NOT_NEW_VIEW_STATE", - "16#FFFFFFFF#" "ANY_VIEW_STATE", - -default binary -} -radix define INSTANCE_STATE { - "16#00000001#" "ALIVE_INSTANCE_STATE", - "16#00000002#" "NOT_ALIVE_DISPOSED_INSTANCE_STATE", - "16#00000004#" "NOT_ALIVE_NO_WRITERS_INSTANCE_STATE", - "16#FFFFFFFF#" "ANY_INSTANCE_STATE", - -default binary -} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -divider SYSTEM -add wave -noupdate /l0_dds_reader_test1_arzkriu/uut/clk -add wave -noupdate /l0_dds_reader_test1_arzkriu/uut/reset -add wave -noupdate /l0_dds_reader_test1_arzkriu/uut/time -add wave -noupdate -divider RTPS -add wave -noupdate -group RTPS /l0_dds_reader_test1_arzkriu/uut/start_rtps -add wave -noupdate -group RTPS /l0_dds_reader_test1_arzkriu/uut/opcode_rtps -add wave -noupdate -group RTPS /l0_dds_reader_test1_arzkriu/uut/ack_rtps -add wave -noupdate -group RTPS /l0_dds_reader_test1_arzkriu/uut/ret_rtps -add wave -noupdate -group RTPS /l0_dds_reader_test1_arzkriu/uut/done_rtps -add wave -noupdate -group RTPS /l0_dds_reader_test1_arzkriu/uut/ready_in_rtps -add wave -noupdate -group RTPS /l0_dds_reader_test1_arzkriu/uut/valid_in_rtps -add wave -noupdate -group RTPS -radix hexadecimal /l0_dds_reader_test1_arzkriu/uut/data_in_rtps -add wave -noupdate -group RTPS /l0_dds_reader_test1_arzkriu/uut/last_word_in_rtps -add wave -noupdate -divider DDS -add wave -noupdate -group DDS /l0_dds_reader_test1_arzkriu/uut/start_dds -add wave -noupdate -group DDS /l0_dds_reader_test1_arzkriu/uut/ack_dds -add wave -noupdate -group DDS /l0_dds_reader_test1_arzkriu/uut/opcode_dds -add wave -noupdate -group DDS -radix SAMPLE_STATE /l0_dds_reader_test1_arzkriu/uut/sample_state_dds -add wave -noupdate -group DDS -radix INSTANCE_STATE /l0_dds_reader_test1_arzkriu/uut/instance_state_dds -add wave -noupdate -group DDS -radix VIEW_STATE /l0_dds_reader_test1_arzkriu/uut/view_state_dds -add wave -noupdate -group DDS -radix hexadecimal /l0_dds_reader_test1_arzkriu/uut/instance_handle_dds -add wave -noupdate -group DDS -radix unsigned /l0_dds_reader_test1_arzkriu/uut/max_samples_dds -add wave -noupdate -group DDS -radix DDS_RETCODE /l0_dds_reader_test1_arzkriu/uut/return_code_dds -add wave -noupdate -group DDS /l0_dds_reader_test1_arzkriu/uut/done_dds -add wave -noupdate -group DDS -divider SI -add wave -noupdate -group DDS -radix hexadecimal -childformat {{/l0_dds_reader_test1_arzkriu/uut/sample_info.sample_state -radix unsigned} {/l0_dds_reader_test1_arzkriu/uut/sample_info.view_state -radix unsigned} {/l0_dds_reader_test1_arzkriu/uut/sample_info.instance_state -radix unsigned} {/l0_dds_reader_test1_arzkriu/uut/sample_info.source_timestamp -radix unsigned} {/l0_dds_reader_test1_arzkriu/uut/sample_info.instance_handle -radix hexadecimal} {/l0_dds_reader_test1_arzkriu/uut/sample_info.publication_handle -radix hexadecimal} {/l0_dds_reader_test1_arzkriu/uut/sample_info.disposed_generation_count -radix unsigned} {/l0_dds_reader_test1_arzkriu/uut/sample_info.no_writers_generation_count -radix unsigned} {/l0_dds_reader_test1_arzkriu/uut/sample_info.sample_rank -radix unsigned} {/l0_dds_reader_test1_arzkriu/uut/sample_info.generation_rank -radix unsigned} {/l0_dds_reader_test1_arzkriu/uut/sample_info.absolute_generation_rank -radix unsigned} {/l0_dds_reader_test1_arzkriu/uut/sample_info.valid_data -radix hexadecimal}} -expand -subitemconfig {/l0_dds_reader_test1_arzkriu/uut/sample_info.sample_state {-height 15 -radix unsigned} /l0_dds_reader_test1_arzkriu/uut/sample_info.view_state {-height 15 -radix unsigned} /l0_dds_reader_test1_arzkriu/uut/sample_info.instance_state {-height 15 -radix unsigned} /l0_dds_reader_test1_arzkriu/uut/sample_info.source_timestamp {-height 15 -radix unsigned} /l0_dds_reader_test1_arzkriu/uut/sample_info.instance_handle {-height 15 -radix hexadecimal} /l0_dds_reader_test1_arzkriu/uut/sample_info.publication_handle {-height 15 -radix hexadecimal} /l0_dds_reader_test1_arzkriu/uut/sample_info.disposed_generation_count {-height 15 -radix unsigned} /l0_dds_reader_test1_arzkriu/uut/sample_info.no_writers_generation_count {-height 15 -radix unsigned} /l0_dds_reader_test1_arzkriu/uut/sample_info.sample_rank {-height 15 -radix unsigned} /l0_dds_reader_test1_arzkriu/uut/sample_info.generation_rank {-height 15 -radix unsigned} /l0_dds_reader_test1_arzkriu/uut/sample_info.absolute_generation_rank {-height 15 -radix unsigned} /l0_dds_reader_test1_arzkriu/uut/sample_info.valid_data {-radix hexadecimal}} /l0_dds_reader_test1_arzkriu/uut/sample_info -add wave -noupdate -group DDS /l0_dds_reader_test1_arzkriu/uut/sample_info_valid -add wave -noupdate -group DDS /l0_dds_reader_test1_arzkriu/uut/sample_info_ack -add wave -noupdate -group DDS /l0_dds_reader_test1_arzkriu/uut/eoc -add wave -noupdate -group DDS /l0_dds_reader_test1_arzkriu/uut/get_data_dds -add wave -noupdate -group DDS -divider OUTPUT -add wave -noupdate -group DDS /l0_dds_reader_test1_arzkriu/uut/ready_out_dds -add wave -noupdate -group DDS /l0_dds_reader_test1_arzkriu/uut/valid_out_dds -add wave -noupdate -group DDS -radix hexadecimal /l0_dds_reader_test1_arzkriu/uut/data_out_dds -add wave -noupdate -group DDS /l0_dds_reader_test1_arzkriu/uut/last_word_out_dds -add wave -noupdate -divider {MAIN FSM} -add wave -noupdate /l0_dds_reader_test1_arzkriu/uut/stage -add wave -noupdate /l0_dds_reader_test1_arzkriu/uut/cnt -add wave -noupdate -divider MEMORY -add wave -noupdate /l0_dds_reader_test1_arzkriu/uut/inst_op_start -add wave -noupdate /l0_dds_reader_test1_arzkriu/uut/inst_opcode -add wave -noupdate /l0_dds_reader_test1_arzkriu/uut/inst_op_done -add wave -noupdate /l0_dds_reader_test1_arzkriu/uut/inst_stage -add wave -noupdate /l0_dds_reader_test1_arzkriu/uut/inst_cnt -add wave -noupdate -radix unsigned /l0_dds_reader_test1_arzkriu/uut/inst_addr_base -add wave -noupdate -childformat {{/l0_dds_reader_test1_arzkriu/uut/inst_data.key_hash -radix hexadecimal} {/l0_dds_reader_test1_arzkriu/uut/inst_data.status_info -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.sample_cnt -radix unsigned} {/l0_dds_reader_test1_arzkriu/uut/inst_data.disposed_gen_cnt -radix unsigned} {/l0_dds_reader_test1_arzkriu/uut/inst_data.no_writers_gen_cnt -radix unsigned} {/l0_dds_reader_test1_arzkriu/uut/inst_data.ignore_deadline -radix unsigned} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap -radix binary -childformat {{/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0) -radix binary -childformat {{/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(0) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(1) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(2) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(3) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(4) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(5) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(6) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(7) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(8) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(9) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(10) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(11) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(12) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(13) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(14) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(15) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(16) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(17) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(18) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(19) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(20) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(21) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(22) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(23) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(24) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(25) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(26) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(27) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(28) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(29) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(30) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(31) -radix binary}}}}}} -subitemconfig {/l0_dds_reader_test1_arzkriu/uut/inst_data.key_hash {-height 15 -radix hexadecimal} /l0_dds_reader_test1_arzkriu/uut/inst_data.status_info {-height 15 -radix binary} /l0_dds_reader_test1_arzkriu/uut/inst_data.sample_cnt {-height 15 -radix unsigned} /l0_dds_reader_test1_arzkriu/uut/inst_data.disposed_gen_cnt {-height 15 -radix unsigned} /l0_dds_reader_test1_arzkriu/uut/inst_data.no_writers_gen_cnt {-height 15 -radix unsigned} /l0_dds_reader_test1_arzkriu/uut/inst_data.ignore_deadline {-height 15 -radix unsigned} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap {-height 15 -radix binary -childformat {{/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0) -radix binary -childformat {{/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(0) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(1) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(2) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(3) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(4) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(5) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(6) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(7) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(8) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(9) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(10) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(11) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(12) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(13) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(14) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(15) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(16) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(17) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(18) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(19) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(20) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(21) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(22) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(23) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(24) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(25) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(26) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(27) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(28) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(29) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(30) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(31) -radix binary}}}}} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0) {-height 15 -radix binary -childformat {{/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(0) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(1) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(2) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(3) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(4) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(5) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(6) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(7) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(8) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(9) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(10) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(11) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(12) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(13) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(14) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(15) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(16) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(17) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(18) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(19) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(20) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(21) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(22) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(23) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(24) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(25) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(26) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(27) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(28) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(29) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(30) -radix binary} {/l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(31) -radix binary}}} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(0) {-height 15 -radix binary} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(1) {-height 15 -radix binary} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(2) {-height 15 -radix binary} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(3) {-height 15 -radix binary} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(4) {-height 15 -radix binary} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(5) {-height 15 -radix binary} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(6) {-height 15 -radix binary} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(7) {-height 15 -radix binary} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(8) {-height 15 -radix binary} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(9) {-height 15 -radix binary} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(10) {-height 15 -radix binary} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(11) {-height 15 -radix binary} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(12) {-height 15 -radix binary} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(13) {-height 15 -radix binary} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(14) {-height 15 -radix binary} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(15) {-height 15 -radix binary} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(16) {-height 15 -radix binary} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(17) {-height 15 -radix binary} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(18) {-height 15 -radix binary} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(19) {-height 15 -radix binary} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(20) {-height 15 -radix binary} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(21) {-height 15 -radix binary} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(22) {-height 15 -radix binary} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(23) {-height 15 -radix binary} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(24) {-height 15 -radix binary} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(25) {-height 15 -radix binary} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(26) {-height 15 -radix binary} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(27) {-height 15 -radix binary} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(28) {-height 15 -radix binary} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(29) {-height 15 -radix binary} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(30) {-height 15 -radix binary} /l0_dds_reader_test1_arzkriu/uut/inst_data.writer_bitmap(0)(31) {-height 15 -radix binary}} /l0_dds_reader_test1_arzkriu/uut/inst_data -add wave -noupdate /l0_dds_reader_test1_arzkriu/uut/stale_inst_cnt -add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test1_arzkriu/uut/sample_abort_read -add wave -noupdate -group {SAMPLE MEM} -radix unsigned /l0_dds_reader_test1_arzkriu/uut/sample_mem_ctrl_inst/addr -add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test1_arzkriu/uut/sample_mem_ctrl_inst/read -add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test1_arzkriu/uut/sample_mem_ctrl_inst/ready_in -add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test1_arzkriu/uut/sample_mem_ctrl_inst/valid_in -add wave -noupdate -group {SAMPLE MEM} -radix hexadecimal /l0_dds_reader_test1_arzkriu/uut/sample_mem_ctrl_inst/data_in -add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test1_arzkriu/uut/sample_mem_ctrl_inst/ready_out -add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test1_arzkriu/uut/sample_mem_ctrl_inst/valid_out -add wave -noupdate -group {SAMPLE MEM} -radix hexadecimal /l0_dds_reader_test1_arzkriu/uut/sample_mem_ctrl_inst/data_out -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test1_arzkriu/uut/payload_abort_read -add wave -noupdate -group {PAYLOAD MEM} -radix unsigned /l0_dds_reader_test1_arzkriu/uut/payload_mem_ctrl_inst/addr -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test1_arzkriu/uut/payload_mem_ctrl_inst/read -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test1_arzkriu/uut/payload_mem_ctrl_inst/ready_in -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test1_arzkriu/uut/payload_mem_ctrl_inst/valid_in -add wave -noupdate -group {PAYLOAD MEM} -radix hexadecimal /l0_dds_reader_test1_arzkriu/uut/payload_mem_ctrl_inst/data_in -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test1_arzkriu/uut/payload_mem_ctrl_inst/ready_out -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test1_arzkriu/uut/payload_mem_ctrl_inst/valid_out -add wave -noupdate -group {PAYLOAD MEM} -radix hexadecimal /l0_dds_reader_test1_arzkriu/uut/payload_mem_ctrl_inst/data_out -add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test1_arzkriu/uut/inst_abort_read -add wave -noupdate -group {INSTANCE MEM} -radix unsigned /l0_dds_reader_test1_arzkriu/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/addr -add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test1_arzkriu/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/read -add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test1_arzkriu/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/ready_in -add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test1_arzkriu/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/valid_in -add wave -noupdate -group {INSTANCE MEM} -radix hexadecimal /l0_dds_reader_test1_arzkriu/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/data_in -add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test1_arzkriu/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/ready_out -add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test1_arzkriu/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/valid_out -add wave -noupdate -group {INSTANCE MEM} -radix hexadecimal /l0_dds_reader_test1_arzkriu/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/data_out -add wave -noupdate -divider POINTERS -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test1_arzkriu/uut/empty_sample_list_head -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test1_arzkriu/uut/empty_sample_list_tail -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test1_arzkriu/uut/empty_payload_list_head -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test1_arzkriu/uut/oldest_sample -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test1_arzkriu/uut/newest_sample -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test1_arzkriu/uut/inst_empty_head -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test1_arzkriu/uut/inst_occupied_head -add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test1_arzkriu/uut/cur_sample -add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test1_arzkriu/uut/next_sample -add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test1_arzkriu/uut/prev_sample -add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test1_arzkriu/uut/cur_payload -add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test1_arzkriu/uut/next_payload -add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test1_arzkriu/uut/cur_inst -add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test1_arzkriu/uut/next_inst -add wave -noupdate -divider MISC -add wave -noupdate /l0_dds_reader_test1_arzkriu/uut/trigger_sample_gen -add wave -noupdate /l0_dds_reader_test1_arzkriu/uut/wait_for_sample_removal -add wave -noupdate /l0_dds_reader_test1_arzkriu/uut/sample_p1 -add wave -noupdate /l0_dds_reader_test1_arzkriu/uut/sample_p2 -add wave -noupdate -radix unsigned /l0_dds_reader_test1_arzkriu/uut/collection_cnt -add wave -noupdate -radix unsigned /l0_dds_reader_test1_arzkriu/uut/collection_cnt_max -add wave -noupdate -radix unsigned /l0_dds_reader_test1_arzkriu/uut/collection_generation_rank -add wave -noupdate -radix unsigned /l0_dds_reader_test1_arzkriu/uut/cur_generation_rank -add wave -noupdate -radix unsigned /l0_dds_reader_test1_arzkriu/uut/max_samples_latch -add wave -noupdate /l0_dds_reader_test1_arzkriu/uut/single_instance -add wave -noupdate /l0_dds_reader_test1_arzkriu/uut/is_take -add wave -noupdate -divider TESTBENCH -add wave -noupdate -group TESTBENCH /l0_dds_reader_test1_arzkriu/dds_start -add wave -noupdate -group TESTBENCH /l0_dds_reader_test1_arzkriu/dds_stage -add wave -noupdate -group TESTBENCH /l0_dds_reader_test1_arzkriu/dds_cnt -add wave -noupdate -group TESTBENCH /l0_dds_reader_test1_arzkriu/dds_cnt2 -add wave -noupdate -group TESTBENCH /l0_dds_reader_test1_arzkriu/dds_done -add wave -noupdate -group TESTBENCH /l0_dds_reader_test1_arzkriu/rtps_start -add wave -noupdate -group TESTBENCH /l0_dds_reader_test1_arzkriu/rtps_stage -add wave -noupdate -group TESTBENCH /l0_dds_reader_test1_arzkriu/rtps_cnt -add wave -noupdate -group TESTBENCH /l0_dds_reader_test1_arzkriu/rtps_done -add wave -noupdate -divider {KEY HOLDER} -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test1_arzkriu/uut/start_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test1_arzkriu/uut/opcode_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test1_arzkriu/uut/ack_kh -add wave -noupdate -group {KEY HOLDER} -radix hexadecimal /l0_dds_reader_test1_arzkriu/uut/data_in_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test1_arzkriu/uut/valid_in_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test1_arzkriu/uut/ready_in_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test1_arzkriu/uut/last_word_in_kh -add wave -noupdate -group {KEY HOLDER} -radix hexadecimal /l0_dds_reader_test1_arzkriu/uut/data_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test1_arzkriu/uut/valid_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test1_arzkriu/uut/ready_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test1_arzkriu/uut/last_word_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test1_arzkriu/uut/abort_kh -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {9775000 ps} 0} -quietly wave cursor active 1 -configure wave -namecolwidth 187 -configure wave -valuecolwidth 206 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -configure wave -timelineunits ns -update -WaveRestoreZoom {6112965 ps} {7046686 ps} diff --git a/sim/L0_dds_reader_test1_arzksiu.do b/sim/L0_dds_reader_test1_arzksiu.do deleted file mode 100644 index b1a9e8e..0000000 --- a/sim/L0_dds_reader_test1_arzksiu.do +++ /dev/null @@ -1,196 +0,0 @@ -onerror {resume} -radix define DDS_RETCODE { - "10#0#" "RETCODE_OK", - "10#1#" "RETCODE_ERROR", - "10#2#" "RETCODE_UNSUPPORTED", - "10#3#" "RETCODE_BAD_PARAMETER", - "10#4#" "RETCODE_PRECONDITION_NOT_MET", - "10#5#" "RETCODE_OUT_OF_RESOURCES", - "10#6#" "RETCODE_NOT_ENABLED", - "10#7#" "RETCODE_IMMUTABLE_POLICY", - "10#8#" "RETCODE_INCONSISTENT_POLICY", - "10#9#" "RETCODE_ALREADY_DELETED", - "10#10#" "RETCODE_TIMEOUT", - "10#11#" "RETCODE_NO_DATA", - "10#12#" "RETCODE_ILLEGAL_OPERATION", - -default unsigned -} -radix define SAMPLE_STATE { - "16#00000001#" "READ_SAMPLE_STATE", - "16#00000002#" "NOT_READ_SAMPLE_STATE", - "16#FFFFFFFF#" "ANY_SAMPLE_STATE", - -default binary -} -radix define VIEW_STATE { - "16#00000001#" "NEW_VIEW_STATE", - "16#00000002#" "NOT_NEW_VIEW_STATE", - "16#FFFFFFFF#" "ANY_VIEW_STATE", - -default binary -} -radix define INSTANCE_STATE { - "16#00000001#" "ALIVE_INSTANCE_STATE", - "16#00000002#" "NOT_ALIVE_DISPOSED_INSTANCE_STATE", - "16#00000004#" "NOT_ALIVE_NO_WRITERS_INSTANCE_STATE", - "16#FFFFFFFF#" "ANY_INSTANCE_STATE", - -default binary -} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -divider SYSTEM -add wave -noupdate /l0_dds_reader_test1_arzksiu/uut/clk -add wave -noupdate /l0_dds_reader_test1_arzksiu/uut/reset -add wave -noupdate /l0_dds_reader_test1_arzksiu/uut/time -add wave -noupdate -divider RTPS -add wave -noupdate -expand -group RTPS /l0_dds_reader_test1_arzksiu/uut/start_rtps -add wave -noupdate -expand -group RTPS /l0_dds_reader_test1_arzksiu/uut/opcode_rtps -add wave -noupdate -expand -group RTPS /l0_dds_reader_test1_arzksiu/uut/ack_rtps -add wave -noupdate -expand -group RTPS /l0_dds_reader_test1_arzksiu/uut/ret_rtps -add wave -noupdate -expand -group RTPS /l0_dds_reader_test1_arzksiu/uut/done_rtps -add wave -noupdate -expand -group RTPS /l0_dds_reader_test1_arzksiu/uut/ready_in_rtps -add wave -noupdate -expand -group RTPS /l0_dds_reader_test1_arzksiu/uut/valid_in_rtps -add wave -noupdate -expand -group RTPS -radix hexadecimal /l0_dds_reader_test1_arzksiu/uut/data_in_rtps -add wave -noupdate -expand -group RTPS /l0_dds_reader_test1_arzksiu/uut/last_word_in_rtps -add wave -noupdate -divider DDS -add wave -noupdate -group DDS /l0_dds_reader_test1_arzksiu/uut/start_dds -add wave -noupdate -group DDS /l0_dds_reader_test1_arzksiu/uut/ack_dds -add wave -noupdate -group DDS /l0_dds_reader_test1_arzksiu/uut/opcode_dds -add wave -noupdate -group DDS -radix SAMPLE_STATE /l0_dds_reader_test1_arzksiu/uut/sample_state_dds -add wave -noupdate -group DDS -radix INSTANCE_STATE /l0_dds_reader_test1_arzksiu/uut/instance_state_dds -add wave -noupdate -group DDS -radix VIEW_STATE /l0_dds_reader_test1_arzksiu/uut/view_state_dds -add wave -noupdate -group DDS -radix hexadecimal /l0_dds_reader_test1_arzksiu/uut/instance_handle_dds -add wave -noupdate -group DDS -radix unsigned /l0_dds_reader_test1_arzksiu/uut/max_samples_dds -add wave -noupdate -group DDS -radix DDS_RETCODE /l0_dds_reader_test1_arzksiu/uut/return_code_dds -add wave -noupdate -group DDS /l0_dds_reader_test1_arzksiu/uut/done_dds -add wave -noupdate -group DDS -divider SI -add wave -noupdate -group DDS -radix SAMPLE_STATE /l0_dds_reader_test1_arzksiu/uut/si_sample_state -add wave -noupdate -group DDS -radix VIEW_STATE /l0_dds_reader_test1_arzksiu/uut/si_view_state -add wave -noupdate -group DDS -radix INSTANCE_STATE /l0_dds_reader_test1_arzksiu/uut/si_instance_state -add wave -noupdate -group DDS -radix unsigned /l0_dds_reader_test1_arzksiu/uut/si_source_timestamp -add wave -noupdate -group DDS -radix hexadecimal /l0_dds_reader_test1_arzksiu/uut/si_instance_handle -add wave -noupdate -group DDS -radix hexadecimal /l0_dds_reader_test1_arzksiu/uut/si_publication_handle -add wave -noupdate -group DDS -radix unsigned /l0_dds_reader_test1_arzksiu/uut/si_disposed_generation_count -add wave -noupdate -group DDS -radix unsigned /l0_dds_reader_test1_arzksiu/uut/si_no_writers_generation_count -add wave -noupdate -group DDS -radix unsigned /l0_dds_reader_test1_arzksiu/uut/si_sample_rank -add wave -noupdate -group DDS -radix unsigned /l0_dds_reader_test1_arzksiu/uut/si_generation_rank -add wave -noupdate -group DDS -radix unsigned /l0_dds_reader_test1_arzksiu/uut/si_absolute_generation_rank -add wave -noupdate -group DDS /l0_dds_reader_test1_arzksiu/uut/si_valid_data -add wave -noupdate -group DDS /l0_dds_reader_test1_arzksiu/uut/si_valid -add wave -noupdate -group DDS /l0_dds_reader_test1_arzksiu/uut/eoc -add wave -noupdate -group DDS /l0_dds_reader_test1_arzksiu/uut/get_data_dds -add wave -noupdate -group DDS -divider OUTPUT -add wave -noupdate -group DDS /l0_dds_reader_test1_arzksiu/uut/ready_out_dds -add wave -noupdate -group DDS /l0_dds_reader_test1_arzksiu/uut/valid_out_dds -add wave -noupdate -group DDS -radix hexadecimal /l0_dds_reader_test1_arzksiu/uut/data_out_dds -add wave -noupdate -group DDS /l0_dds_reader_test1_arzksiu/uut/last_word_out_dds -add wave -noupdate -divider {MAIN FSM} -add wave -noupdate /l0_dds_reader_test1_arzksiu/uut/stage -add wave -noupdate /l0_dds_reader_test1_arzksiu/uut/stage_next -add wave -noupdate /l0_dds_reader_test1_arzksiu/uut/cnt -add wave -noupdate -divider MEMORY -add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test1_arzksiu/uut/sample_abort_read -add wave -noupdate -group {SAMPLE MEM} -radix unsigned /l0_dds_reader_test1_arzksiu/uut/sample_mem_ctrl_inst/addr -add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test1_arzksiu/uut/sample_mem_ctrl_inst/read -add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test1_arzksiu/uut/sample_mem_ctrl_inst/ready_in -add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test1_arzksiu/uut/sample_mem_ctrl_inst/valid_in -add wave -noupdate -group {SAMPLE MEM} -radix hexadecimal /l0_dds_reader_test1_arzksiu/uut/sample_mem_ctrl_inst/data_in -add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test1_arzksiu/uut/sample_mem_ctrl_inst/ready_out -add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test1_arzksiu/uut/sample_mem_ctrl_inst/valid_out -add wave -noupdate -group {SAMPLE MEM} -radix hexadecimal /l0_dds_reader_test1_arzksiu/uut/sample_mem_ctrl_inst/data_out -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test1_arzksiu/uut/payload_abort_read -add wave -noupdate -group {PAYLOAD MEM} -radix unsigned /l0_dds_reader_test1_arzksiu/uut/payload_mem_ctrl_inst/addr -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test1_arzksiu/uut/payload_mem_ctrl_inst/read -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test1_arzksiu/uut/payload_mem_ctrl_inst/ready_in -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test1_arzksiu/uut/payload_mem_ctrl_inst/valid_in -add wave -noupdate -group {PAYLOAD MEM} -radix hexadecimal /l0_dds_reader_test1_arzksiu/uut/payload_mem_ctrl_inst/data_in -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test1_arzksiu/uut/payload_mem_ctrl_inst/ready_out -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test1_arzksiu/uut/payload_mem_ctrl_inst/valid_out -add wave -noupdate -group {PAYLOAD MEM} -radix hexadecimal /l0_dds_reader_test1_arzksiu/uut/payload_mem_ctrl_inst/data_out -add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test1_arzksiu/uut/inst_abort_read -add wave -noupdate -group {INSTANCE MEM} -radix unsigned /l0_dds_reader_test1_arzksiu/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/addr -add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test1_arzksiu/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/read -add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test1_arzksiu/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/ready_in -add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test1_arzksiu/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/valid_in -add wave -noupdate -group {INSTANCE MEM} -radix hexadecimal /l0_dds_reader_test1_arzksiu/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/data_in -add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test1_arzksiu/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/ready_out -add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test1_arzksiu/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/valid_out -add wave -noupdate -group {INSTANCE MEM} -radix hexadecimal /l0_dds_reader_test1_arzksiu/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/data_out -add wave -noupdate /l0_dds_reader_test1_arzksiu/uut/inst_op_start -add wave -noupdate /l0_dds_reader_test1_arzksiu/uut/inst_opcode -add wave -noupdate /l0_dds_reader_test1_arzksiu/uut/inst_op_done -add wave -noupdate /l0_dds_reader_test1_arzksiu/uut/inst_stage -add wave -noupdate /l0_dds_reader_test1_arzksiu/uut/inst_stage_next -add wave -noupdate /l0_dds_reader_test1_arzksiu/uut/inst_cnt -add wave -noupdate -radix unsigned /l0_dds_reader_test1_arzksiu/uut/inst_addr_base -add wave -noupdate /l0_dds_reader_test1_arzksiu/uut/inst_mem_fields -add wave -noupdate -childformat {{/l0_dds_reader_test1_arzksiu/uut/inst_data.key_hash -radix hexadecimal} {/l0_dds_reader_test1_arzksiu/uut/inst_data.status_info -radix binary} {/l0_dds_reader_test1_arzksiu/uut/inst_data.sample_cnt -radix unsigned} {/l0_dds_reader_test1_arzksiu/uut/inst_data.disposed_gen_cnt -radix unsigned} {/l0_dds_reader_test1_arzksiu/uut/inst_data.no_writers_gen_cnt -radix unsigned} {/l0_dds_reader_test1_arzksiu/uut/inst_data.ignore_deadline -radix unsigned} {/l0_dds_reader_test1_arzksiu/uut/inst_data.writer_bitmap -radix binary -childformat {{/l0_dds_reader_test1_arzksiu/uut/inst_data.writer_bitmap(0) -radix binary -childformat {{/l0_dds_reader_test1_arzksiu/uut/inst_data.writer_bitmap(0)(0) -radix binary} {/l0_dds_reader_test1_arzksiu/uut/inst_data.writer_bitmap(0)(1) -radix binary} {/l0_dds_reader_test1_arzksiu/uut/inst_data.writer_bitmap(0)(2) -radix binary} {/l0_dds_reader_test1_arzksiu/uut/inst_data.writer_bitmap(0)(3) -radix binary} {/l0_dds_reader_test1_arzksiu/uut/inst_data.writer_bitmap(0)(4) -radix binary} {/l0_dds_reader_test1_arzksiu/uut/inst_data.writer_bitmap(0)(5) -radix binary} {/l0_dds_reader_test1_arzksiu/uut/inst_data.writer_bitmap(0)(6) -radix binary} {/l0_dds_reader_test1_arzksiu/uut/inst_data.writer_bitmap(0)(7) -radix binary} {/l0_dds_reader_test1_arzksiu/uut/inst_data.writer_bitmap(0)(8) -radix binary} {/l0_dds_reader_test1_arzksiu/uut/inst_data.writer_bitmap(0)(9) -radix binary} {/l0_dds_reader_test1_arzksiu/uut/inst_data.writer_bitmap(0)(10) -radix binary} {/l0_dds_reader_test1_arzksiu/uut/inst_data.writer_bitmap(0)(11) -radix binary} {/l0_dds_reader_test1_arzksiu/uut/inst_data.writer_bitmap(0)(12) -radix binary} {/l0_dds_reader_test1_arzksiu/uut/inst_data.writer_bitmap(0)(13) -radix binary} {/l0_dds_reader_test1_arzksiu/uut/inst_data.writer_bitmap(0)(14) -radix binary} {/l0_dds_reader_test1_arzksiu/uut/inst_data.writer_bitmap(0)(15) -radix binary} {/l0_dds_reader_test1_arzksiu/uut/inst_data.writer_bitmap(0)(16) -radix binary} {/l0_dds_reader_test1_arzksiu/uut/inst_data.writer_bitmap(0)(17) -radix binary} {/l0_dds_reader_test1_arzksiu/uut/inst_data.writer_bitmap(0)(18) -radix binary} {/l0_dds_reader_test1_arzksiu/uut/inst_data.writer_bitmap(0)(19) -radix binary} {/l0_dds_reader_test1_arzksiu/uut/inst_data.writer_bitmap(0)(20) -radix binary} {/l0_dds_reader_test1_arzksiu/uut/inst_data.writer_bitmap(0)(21) -radix binary} {/l0_dds_reader_test1_arzksiu/uut/inst_data.writer_bitmap(0)(22) -radix binary} {/l0_dds_reader_test1_arzksiu/uut/inst_data.writer_bitmap(0)(23) -radix binary} {/l0_dds_reader_test1_arzksiu/uut/inst_data.writer_bitmap(0)(24) -radix binary} {/l0_dds_reader_test1_arzksiu/uut/inst_data.writer_bitmap(0)(25) -radix binary} {/l0_dds_reader_test1_arzksiu/uut/inst_data.writer_bitmap(0)(26) -radix binary} {/l0_dds_reader_test1_arzksiu/uut/inst_data.writer_bitmap(0)(27) -radix binary} {/l0_dds_reader_test1_arzksiu/uut/inst_data.writer_bitmap(0)(28) -radix binary} {/l0_dds_reader_test1_arzksiu/uut/inst_data.writer_bitmap(0)(29) -radix binary} {/l0_dds_reader_test1_arzksiu/uut/inst_data.writer_bitmap(0)(30) -radix binary} {/l0_dds_reader_test1_arzksiu/uut/inst_data.writer_bitmap(0)(31) -radix binary}}}}}} -expand -subitemconfig {/l0_dds_reader_test1_arzksiu/uut/inst_data.key_hash {-height 15 -radix hexadecimal} /l0_dds_reader_test1_arzksiu/uut/inst_data.status_info {-height 15 -radix binary} /l0_dds_reader_test1_arzksiu/uut/inst_data.sample_cnt {-height 15 -radix unsigned} /l0_dds_reader_test1_arzksiu/uut/inst_data.disposed_gen_cnt {-height 15 -radix unsigned} /l0_dds_reader_test1_arzksiu/uut/inst_data.no_writers_gen_cnt {-height 15 -radix unsigned} /l0_dds_reader_test1_arzksiu/uut/inst_data.ignore_deadline {-height 15 -radix unsigned} /l0_dds_reader_test1_arzksiu/uut/inst_data.writer_bitmap {-height 15 -radix binary -childformat {{/l0_dds_reader_test1_arzksiu/uut/inst_data.writer_bitmap(0) -radix binary -childformat {{/l0_dds_reader_test1_arzksiu/uut/inst_data.writer_bitmap(0)(0) -radix binary} {/l0_dds_reader_test1_arzksiu/uut/inst_data.writer_bitmap(0)(1) -radix binary} {/l0_dds_reader_test1_arzksiu/uut/inst_data.writer_bitmap(0)(2) -radix binary} {/l0_dds_reader_test1_arzksiu/uut/inst_data.writer_bitmap(0)(3) -radix binary} {/l0_dds_reader_test1_arzksiu/uut/inst_data.writer_bitmap(0)(4) -radix binary} {/l0_dds_reader_test1_arzksiu/uut/inst_data.writer_bitmap(0)(5) -radix binary} {/l0_dds_reader_test1_arzksiu/uut/inst_data.writer_bitmap(0)(6) -radix binary} {/l0_dds_reader_test1_arzksiu/uut/inst_data.writer_bitmap(0)(7) -radix binary} {/l0_dds_reader_test1_arzksiu/uut/inst_data.writer_bitmap(0)(8) -radix binary} {/l0_dds_reader_test1_arzksiu/uut/inst_data.writer_bitmap(0)(9) -radix binary} {/l0_dds_reader_test1_arzksiu/uut/inst_data.writer_bitmap(0)(10) -radix binary} {/l0_dds_reader_test1_arzksiu/uut/inst_data.writer_bitmap(0)(11) -radix binary} {/l0_dds_reader_test1_arzksiu/uut/inst_data.writer_bitmap(0)(12) -radix binary} {/l0_dds_reader_test1_arzksiu/uut/inst_data.writer_bitmap(0)(13) -radix binary} {/l0_dds_reader_test1_arzksiu/uut/inst_data.writer_bitmap(0)(14) -radix binary} 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/l0_dds_reader_test1_arzksiu/uut/inst_data.writer_bitmap(0)(9) {-height 15 -radix binary} /l0_dds_reader_test1_arzksiu/uut/inst_data.writer_bitmap(0)(10) {-height 15 -radix binary} /l0_dds_reader_test1_arzksiu/uut/inst_data.writer_bitmap(0)(11) {-height 15 -radix binary} /l0_dds_reader_test1_arzksiu/uut/inst_data.writer_bitmap(0)(12) {-height 15 -radix binary} /l0_dds_reader_test1_arzksiu/uut/inst_data.writer_bitmap(0)(13) {-height 15 -radix binary} /l0_dds_reader_test1_arzksiu/uut/inst_data.writer_bitmap(0)(14) {-height 15 -radix binary} /l0_dds_reader_test1_arzksiu/uut/inst_data.writer_bitmap(0)(15) {-height 15 -radix binary} /l0_dds_reader_test1_arzksiu/uut/inst_data.writer_bitmap(0)(16) {-height 15 -radix binary} /l0_dds_reader_test1_arzksiu/uut/inst_data.writer_bitmap(0)(17) {-height 15 -radix binary} /l0_dds_reader_test1_arzksiu/uut/inst_data.writer_bitmap(0)(18) {-height 15 -radix binary} /l0_dds_reader_test1_arzksiu/uut/inst_data.writer_bitmap(0)(19) {-height 15 -radix binary} /l0_dds_reader_test1_arzksiu/uut/inst_data.writer_bitmap(0)(20) {-height 15 -radix binary} /l0_dds_reader_test1_arzksiu/uut/inst_data.writer_bitmap(0)(21) {-height 15 -radix binary} /l0_dds_reader_test1_arzksiu/uut/inst_data.writer_bitmap(0)(22) {-height 15 -radix binary} /l0_dds_reader_test1_arzksiu/uut/inst_data.writer_bitmap(0)(23) {-height 15 -radix binary} /l0_dds_reader_test1_arzksiu/uut/inst_data.writer_bitmap(0)(24) {-height 15 -radix binary} /l0_dds_reader_test1_arzksiu/uut/inst_data.writer_bitmap(0)(25) {-height 15 -radix binary} /l0_dds_reader_test1_arzksiu/uut/inst_data.writer_bitmap(0)(26) {-height 15 -radix binary} /l0_dds_reader_test1_arzksiu/uut/inst_data.writer_bitmap(0)(27) {-height 15 -radix binary} /l0_dds_reader_test1_arzksiu/uut/inst_data.writer_bitmap(0)(28) {-height 15 -radix binary} /l0_dds_reader_test1_arzksiu/uut/inst_data.writer_bitmap(0)(29) {-height 15 -radix binary} /l0_dds_reader_test1_arzksiu/uut/inst_data.writer_bitmap(0)(30) {-height 15 -radix binary} /l0_dds_reader_test1_arzksiu/uut/inst_data.writer_bitmap(0)(31) {-height 15 -radix binary}} /l0_dds_reader_test1_arzksiu/uut/inst_data -add wave -noupdate -radix unsigned /l0_dds_reader_test1_arzksiu/uut/inst_next_addr_base -add wave -noupdate -radix unsigned /l0_dds_reader_test1_arzksiu/uut/inst_prev_addr_base -add wave -noupdate /l0_dds_reader_test1_arzksiu/uut/current_imf -add wave -noupdate /l0_dds_reader_test1_arzksiu/uut/stale_inst_cnt -add wave -noupdate -divider POINTERS -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test1_arzksiu/uut/empty_sample_list_head -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test1_arzksiu/uut/empty_sample_list_tail -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test1_arzksiu/uut/empty_payload_list_head -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test1_arzksiu/uut/oldest_sample -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test1_arzksiu/uut/newest_sample -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test1_arzksiu/uut/inst_empty_head -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test1_arzksiu/uut/inst_occupied_head -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test1_arzksiu/uut/cur_sample -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test1_arzksiu/uut/next_sample -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test1_arzksiu/uut/prev_sample -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test1_arzksiu/uut/cur_payload -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test1_arzksiu/uut/next_payload -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test1_arzksiu/uut/cur_inst -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test1_arzksiu/uut/next_inst -add wave -noupdate -divider MISC -add wave -noupdate /l0_dds_reader_test1_arzksiu/uut/trigger_sample_gen -add wave -noupdate /l0_dds_reader_test1_arzksiu/uut/wait_for_sample_removal -add wave -noupdate /l0_dds_reader_test1_arzksiu/uut/sample_p1 -add wave -noupdate /l0_dds_reader_test1_arzksiu/uut/sample_p2 -add wave -noupdate -radix unsigned /l0_dds_reader_test1_arzksiu/uut/collection_cnt -add wave -noupdate -radix unsigned /l0_dds_reader_test1_arzksiu/uut/collection_cnt_max -add wave -noupdate -radix unsigned /l0_dds_reader_test1_arzksiu/uut/collection_generation_rank -add wave -noupdate -radix unsigned /l0_dds_reader_test1_arzksiu/uut/cur_generation_rank -add wave -noupdate -radix unsigned /l0_dds_reader_test1_arzksiu/uut/max_samples_latch -add wave -noupdate /l0_dds_reader_test1_arzksiu/uut/single_instance -add wave -noupdate /l0_dds_reader_test1_arzksiu/uut/is_take -add wave -noupdate -divider TESTBENCH -add wave -noupdate -group TESTBENCH /l0_dds_reader_test1_arzksiu/dds_start -add wave -noupdate -group TESTBENCH /l0_dds_reader_test1_arzksiu/dds_stage -add wave -noupdate -group TESTBENCH /l0_dds_reader_test1_arzksiu/dds_cnt -add wave -noupdate -group TESTBENCH /l0_dds_reader_test1_arzksiu/dds_cnt2 -add wave -noupdate -group TESTBENCH /l0_dds_reader_test1_arzksiu/dds_done -add wave -noupdate -group TESTBENCH /l0_dds_reader_test1_arzksiu/rtps_start -add wave -noupdate -group TESTBENCH /l0_dds_reader_test1_arzksiu/rtps_stage -add wave -noupdate -group TESTBENCH /l0_dds_reader_test1_arzksiu/rtps_cnt -add wave -noupdate -group TESTBENCH /l0_dds_reader_test1_arzksiu/rtps_done -add wave -noupdate -divider {KEY HOLDER} -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test1_arzksiu/uut/start_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test1_arzksiu/uut/opcode_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test1_arzksiu/uut/ack_kh -add wave -noupdate -group {KEY HOLDER} -radix hexadecimal /l0_dds_reader_test1_arzksiu/uut/data_in_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test1_arzksiu/uut/valid_in_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test1_arzksiu/uut/ready_in_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test1_arzksiu/uut/last_word_in_kh -add wave -noupdate -group {KEY HOLDER} -radix hexadecimal /l0_dds_reader_test1_arzksiu/uut/data_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test1_arzksiu/uut/valid_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test1_arzksiu/uut/ready_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test1_arzksiu/uut/last_word_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test1_arzksiu/uut/abort_kh -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {77695423 ps} 0} {{Cursor 2} {115175000 ps} 1} -quietly wave cursor active 1 -configure wave -namecolwidth 187 -configure wave -valuecolwidth 206 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -configure wave -timelineunits ns -update -WaveRestoreZoom {76925214 ps} {77858935 ps} diff --git a/sim/L0_dds_reader_test1_arznriu.do b/sim/L0_dds_reader_test1_arznriu.do deleted file mode 100644 index d559b3c..0000000 --- a/sim/L0_dds_reader_test1_arznriu.do +++ /dev/null @@ -1,175 +0,0 @@ -onerror {resume} -radix define DDS_RETCODE { - "10#0#" "RETCODE_OK", - "10#1#" "RETCODE_ERROR", - "10#2#" "RETCODE_UNSUPPORTED", - "10#3#" "RETCODE_BAD_PARAMETER", - "10#4#" "RETCODE_PRECONDITION_NOT_MET", - "10#5#" "RETCODE_OUT_OF_RESOURCES", - "10#6#" "RETCODE_NOT_ENABLED", - "10#7#" "RETCODE_IMMUTABLE_POLICY", - "10#8#" "RETCODE_INCONSISTENT_POLICY", - "10#9#" "RETCODE_ALREADY_DELETED", - "10#10#" "RETCODE_TIMEOUT", - "10#11#" "RETCODE_NO_DATA", - "10#12#" "RETCODE_ILLEGAL_OPERATION", - -default unsigned -} -radix define SAMPLE_STATE { - "16#00000001#" "READ_SAMPLE_STATE", - "16#00000002#" "NOT_READ_SAMPLE_STATE", - "16#FFFFFFFF#" "ANY_SAMPLE_STATE", - -default binary -} -radix define VIEW_STATE { - "16#00000001#" "NEW_VIEW_STATE", - "16#00000002#" "NOT_NEW_VIEW_STATE", - "16#FFFFFFFF#" "ANY_VIEW_STATE", - -default binary -} -radix define INSTANCE_STATE { - "16#00000001#" "ALIVE_INSTANCE_STATE", - "16#00000002#" "NOT_ALIVE_DISPOSED_INSTANCE_STATE", - "16#00000004#" "NOT_ALIVE_NO_WRITERS_INSTANCE_STATE", - "16#FFFFFFFF#" "ANY_INSTANCE_STATE", - -default binary -} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -divider SYSTEM -add wave -noupdate /l0_dds_reader_test1_arznriu/uut/clk -add wave -noupdate /l0_dds_reader_test1_arznriu/uut/reset -add wave -noupdate /l0_dds_reader_test1_arznriu/uut/time -add wave -noupdate -divider RTPS -add wave -noupdate -expand -group RTPS /l0_dds_reader_test1_arznriu/uut/start_rtps -add wave -noupdate -expand -group RTPS /l0_dds_reader_test1_arznriu/uut/opcode_rtps -add wave -noupdate -expand -group RTPS /l0_dds_reader_test1_arznriu/uut/ack_rtps -add wave -noupdate -expand -group RTPS /l0_dds_reader_test1_arznriu/uut/ret_rtps -add wave -noupdate -expand -group RTPS /l0_dds_reader_test1_arznriu/uut/done_rtps -add wave -noupdate -expand -group RTPS /l0_dds_reader_test1_arznriu/uut/ready_in_rtps -add wave -noupdate -expand -group RTPS /l0_dds_reader_test1_arznriu/uut/valid_in_rtps -add wave -noupdate -expand -group RTPS -radix hexadecimal /l0_dds_reader_test1_arznriu/uut/data_in_rtps -add wave -noupdate -expand -group RTPS /l0_dds_reader_test1_arznriu/uut/last_word_in_rtps -add wave -noupdate -divider DDS -add wave -noupdate -group DDS /l0_dds_reader_test1_arznriu/uut/start_dds -add wave -noupdate -group DDS /l0_dds_reader_test1_arznriu/uut/ack_dds -add wave -noupdate -group DDS /l0_dds_reader_test1_arznriu/uut/opcode_dds -add wave -noupdate -group DDS -radix SAMPLE_STATE /l0_dds_reader_test1_arznriu/uut/sample_state_dds -add wave -noupdate -group DDS -radix INSTANCE_STATE /l0_dds_reader_test1_arznriu/uut/instance_state_dds -add wave -noupdate -group DDS -radix VIEW_STATE /l0_dds_reader_test1_arznriu/uut/view_state_dds -add wave -noupdate -group DDS -radix hexadecimal /l0_dds_reader_test1_arznriu/uut/instance_handle_dds -add wave -noupdate -group DDS -radix unsigned /l0_dds_reader_test1_arznriu/uut/max_samples_dds -add wave -noupdate -group DDS -radix DDS_RETCODE /l0_dds_reader_test1_arznriu/uut/return_code_dds -add wave -noupdate -group DDS /l0_dds_reader_test1_arznriu/uut/done_dds -add wave -noupdate -group DDS -divider SI -add wave -noupdate -group DDS -radix SAMPLE_STATE /l0_dds_reader_test1_arznriu/uut/si_sample_state -add wave -noupdate -group DDS -radix VIEW_STATE /l0_dds_reader_test1_arznriu/uut/si_view_state -add wave -noupdate -group DDS -radix INSTANCE_STATE /l0_dds_reader_test1_arznriu/uut/si_instance_state -add wave -noupdate -group DDS -radix unsigned /l0_dds_reader_test1_arznriu/uut/si_source_timestamp -add wave -noupdate -group DDS -radix hexadecimal /l0_dds_reader_test1_arznriu/uut/si_instance_handle -add wave -noupdate -group DDS -radix hexadecimal /l0_dds_reader_test1_arznriu/uut/si_publication_handle -add wave -noupdate -group DDS -radix unsigned /l0_dds_reader_test1_arznriu/uut/si_disposed_generation_count -add wave -noupdate -group DDS -radix unsigned /l0_dds_reader_test1_arznriu/uut/si_no_writers_generation_count -add wave -noupdate -group DDS -radix unsigned /l0_dds_reader_test1_arznriu/uut/si_sample_rank -add wave -noupdate -group DDS -radix unsigned /l0_dds_reader_test1_arznriu/uut/si_generation_rank -add wave -noupdate -group DDS -radix unsigned /l0_dds_reader_test1_arznriu/uut/si_absolute_generation_rank -add wave -noupdate -group DDS /l0_dds_reader_test1_arznriu/uut/si_valid_data -add wave -noupdate -group DDS /l0_dds_reader_test1_arznriu/uut/si_valid -add wave -noupdate -group DDS /l0_dds_reader_test1_arznriu/uut/eoc -add wave -noupdate -group DDS /l0_dds_reader_test1_arznriu/uut/get_data_dds -add wave -noupdate -group DDS -divider OUTPUT -add wave -noupdate -group DDS /l0_dds_reader_test1_arznriu/uut/ready_out_dds -add wave -noupdate -group DDS /l0_dds_reader_test1_arznriu/uut/valid_out_dds -add wave -noupdate -group DDS -radix hexadecimal /l0_dds_reader_test1_arznriu/uut/data_out_dds -add wave -noupdate -group DDS /l0_dds_reader_test1_arznriu/uut/last_word_out_dds -add wave -noupdate -divider {MAIN FSM} -add wave -noupdate /l0_dds_reader_test1_arznriu/uut/stage -add wave -noupdate /l0_dds_reader_test1_arznriu/uut/stage_next -add wave -noupdate /l0_dds_reader_test1_arznriu/uut/cnt -add wave -noupdate -divider MEMORY -add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test1_arznriu/uut/sample_abort_read -add wave -noupdate -group {SAMPLE MEM} -radix unsigned /l0_dds_reader_test1_arznriu/uut/sample_mem_ctrl_inst/addr -add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test1_arznriu/uut/sample_mem_ctrl_inst/read -add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test1_arznriu/uut/sample_mem_ctrl_inst/ready_in -add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test1_arznriu/uut/sample_mem_ctrl_inst/valid_in -add wave -noupdate -group {SAMPLE MEM} -radix hexadecimal /l0_dds_reader_test1_arznriu/uut/sample_mem_ctrl_inst/data_in -add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test1_arznriu/uut/sample_mem_ctrl_inst/ready_out -add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test1_arznriu/uut/sample_mem_ctrl_inst/valid_out -add wave -noupdate -group {SAMPLE MEM} -radix hexadecimal /l0_dds_reader_test1_arznriu/uut/sample_mem_ctrl_inst/data_out -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test1_arznriu/uut/payload_abort_read -add wave -noupdate -group {PAYLOAD MEM} -radix unsigned /l0_dds_reader_test1_arznriu/uut/payload_mem_ctrl_inst/addr -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test1_arznriu/uut/payload_mem_ctrl_inst/read -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test1_arznriu/uut/payload_mem_ctrl_inst/ready_in -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test1_arznriu/uut/payload_mem_ctrl_inst/valid_in -add wave -noupdate -group {PAYLOAD MEM} -radix hexadecimal /l0_dds_reader_test1_arznriu/uut/payload_mem_ctrl_inst/data_in -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test1_arznriu/uut/payload_mem_ctrl_inst/ready_out -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test1_arznriu/uut/payload_mem_ctrl_inst/valid_out -add wave -noupdate -group {PAYLOAD MEM} -radix hexadecimal /l0_dds_reader_test1_arznriu/uut/payload_mem_ctrl_inst/data_out -add wave -noupdate -childformat {{/l0_dds_reader_test1_arznriu/uut/inst_data.key_hash -radix hexadecimal} {/l0_dds_reader_test1_arznriu/uut/inst_data.status_info -radix binary} {/l0_dds_reader_test1_arznriu/uut/inst_data.sample_cnt -radix unsigned} {/l0_dds_reader_test1_arznriu/uut/inst_data.disposed_gen_cnt -radix unsigned} {/l0_dds_reader_test1_arznriu/uut/inst_data.no_writers_gen_cnt -radix unsigned} {/l0_dds_reader_test1_arznriu/uut/inst_data.ignore_deadline -radix unsigned} {/l0_dds_reader_test1_arznriu/uut/inst_data.writer_bitmap -radix binary -childformat {{/l0_dds_reader_test1_arznriu/uut/inst_data.writer_bitmap(0) -radix binary -childformat {{/l0_dds_reader_test1_arznriu/uut/inst_data.writer_bitmap(0)(0) -radix binary} {/l0_dds_reader_test1_arznriu/uut/inst_data.writer_bitmap(0)(1) -radix binary} {/l0_dds_reader_test1_arznriu/uut/inst_data.writer_bitmap(0)(2) -radix binary} {/l0_dds_reader_test1_arznriu/uut/inst_data.writer_bitmap(0)(3) -radix binary} {/l0_dds_reader_test1_arznriu/uut/inst_data.writer_bitmap(0)(4) -radix binary} {/l0_dds_reader_test1_arznriu/uut/inst_data.writer_bitmap(0)(5) -radix binary} {/l0_dds_reader_test1_arznriu/uut/inst_data.writer_bitmap(0)(6) -radix binary} {/l0_dds_reader_test1_arznriu/uut/inst_data.writer_bitmap(0)(7) -radix binary} {/l0_dds_reader_test1_arznriu/uut/inst_data.writer_bitmap(0)(8) -radix binary} {/l0_dds_reader_test1_arznriu/uut/inst_data.writer_bitmap(0)(9) -radix binary} {/l0_dds_reader_test1_arznriu/uut/inst_data.writer_bitmap(0)(10) -radix binary} {/l0_dds_reader_test1_arznriu/uut/inst_data.writer_bitmap(0)(11) -radix binary} {/l0_dds_reader_test1_arznriu/uut/inst_data.writer_bitmap(0)(12) -radix binary} {/l0_dds_reader_test1_arznriu/uut/inst_data.writer_bitmap(0)(13) -radix binary} {/l0_dds_reader_test1_arznriu/uut/inst_data.writer_bitmap(0)(14) -radix binary} {/l0_dds_reader_test1_arznriu/uut/inst_data.writer_bitmap(0)(15) -radix binary} {/l0_dds_reader_test1_arznriu/uut/inst_data.writer_bitmap(0)(16) -radix binary} {/l0_dds_reader_test1_arznriu/uut/inst_data.writer_bitmap(0)(17) -radix binary} {/l0_dds_reader_test1_arznriu/uut/inst_data.writer_bitmap(0)(18) -radix binary} {/l0_dds_reader_test1_arznriu/uut/inst_data.writer_bitmap(0)(19) -radix binary} {/l0_dds_reader_test1_arznriu/uut/inst_data.writer_bitmap(0)(20) -radix binary} {/l0_dds_reader_test1_arznriu/uut/inst_data.writer_bitmap(0)(21) -radix binary} {/l0_dds_reader_test1_arznriu/uut/inst_data.writer_bitmap(0)(22) -radix binary} {/l0_dds_reader_test1_arznriu/uut/inst_data.writer_bitmap(0)(23) -radix binary} {/l0_dds_reader_test1_arznriu/uut/inst_data.writer_bitmap(0)(24) -radix binary} {/l0_dds_reader_test1_arznriu/uut/inst_data.writer_bitmap(0)(25) -radix binary} {/l0_dds_reader_test1_arznriu/uut/inst_data.writer_bitmap(0)(26) -radix binary} {/l0_dds_reader_test1_arznriu/uut/inst_data.writer_bitmap(0)(27) -radix binary} {/l0_dds_reader_test1_arznriu/uut/inst_data.writer_bitmap(0)(28) -radix binary} {/l0_dds_reader_test1_arznriu/uut/inst_data.writer_bitmap(0)(29) -radix binary} {/l0_dds_reader_test1_arznriu/uut/inst_data.writer_bitmap(0)(30) -radix binary} {/l0_dds_reader_test1_arznriu/uut/inst_data.writer_bitmap(0)(31) -radix binary}}}}}} -expand -subitemconfig {/l0_dds_reader_test1_arznriu/uut/inst_data.key_hash {-height 15 -radix hexadecimal} /l0_dds_reader_test1_arznriu/uut/inst_data.status_info {-height 15 -radix binary} /l0_dds_reader_test1_arznriu/uut/inst_data.sample_cnt {-height 15 -radix unsigned} /l0_dds_reader_test1_arznriu/uut/inst_data.disposed_gen_cnt {-height 15 -radix unsigned} /l0_dds_reader_test1_arznriu/uut/inst_data.no_writers_gen_cnt {-height 15 -radix unsigned} /l0_dds_reader_test1_arznriu/uut/inst_data.ignore_deadline {-height 15 -radix unsigned} /l0_dds_reader_test1_arznriu/uut/inst_data.writer_bitmap {-height 15 -radix binary -childformat {{/l0_dds_reader_test1_arznriu/uut/inst_data.writer_bitmap(0) -radix binary -childformat {{/l0_dds_reader_test1_arznriu/uut/inst_data.writer_bitmap(0)(0) -radix binary} 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{/l0_dds_reader_test1_arznriu/uut/inst_data.writer_bitmap(0)(28) -radix binary} {/l0_dds_reader_test1_arznriu/uut/inst_data.writer_bitmap(0)(29) -radix binary} {/l0_dds_reader_test1_arznriu/uut/inst_data.writer_bitmap(0)(30) -radix binary} {/l0_dds_reader_test1_arznriu/uut/inst_data.writer_bitmap(0)(31) -radix binary}}} /l0_dds_reader_test1_arznriu/uut/inst_data.writer_bitmap(0)(0) {-height 15 -radix binary} /l0_dds_reader_test1_arznriu/uut/inst_data.writer_bitmap(0)(1) {-height 15 -radix binary} /l0_dds_reader_test1_arznriu/uut/inst_data.writer_bitmap(0)(2) {-height 15 -radix binary} /l0_dds_reader_test1_arznriu/uut/inst_data.writer_bitmap(0)(3) {-height 15 -radix binary} /l0_dds_reader_test1_arznriu/uut/inst_data.writer_bitmap(0)(4) {-height 15 -radix binary} /l0_dds_reader_test1_arznriu/uut/inst_data.writer_bitmap(0)(5) {-height 15 -radix binary} /l0_dds_reader_test1_arznriu/uut/inst_data.writer_bitmap(0)(6) {-height 15 -radix binary} /l0_dds_reader_test1_arznriu/uut/inst_data.writer_bitmap(0)(7) {-height 15 -radix binary} /l0_dds_reader_test1_arznriu/uut/inst_data.writer_bitmap(0)(8) {-height 15 -radix binary} /l0_dds_reader_test1_arznriu/uut/inst_data.writer_bitmap(0)(9) {-height 15 -radix binary} /l0_dds_reader_test1_arznriu/uut/inst_data.writer_bitmap(0)(10) {-height 15 -radix binary} /l0_dds_reader_test1_arznriu/uut/inst_data.writer_bitmap(0)(11) {-height 15 -radix binary} /l0_dds_reader_test1_arznriu/uut/inst_data.writer_bitmap(0)(12) {-height 15 -radix binary} /l0_dds_reader_test1_arznriu/uut/inst_data.writer_bitmap(0)(13) {-height 15 -radix binary} /l0_dds_reader_test1_arznriu/uut/inst_data.writer_bitmap(0)(14) {-height 15 -radix binary} /l0_dds_reader_test1_arznriu/uut/inst_data.writer_bitmap(0)(15) {-height 15 -radix binary} /l0_dds_reader_test1_arznriu/uut/inst_data.writer_bitmap(0)(16) {-height 15 -radix binary} /l0_dds_reader_test1_arznriu/uut/inst_data.writer_bitmap(0)(17) {-height 15 -radix binary} /l0_dds_reader_test1_arznriu/uut/inst_data.writer_bitmap(0)(18) {-height 15 -radix binary} /l0_dds_reader_test1_arznriu/uut/inst_data.writer_bitmap(0)(19) {-height 15 -radix binary} /l0_dds_reader_test1_arznriu/uut/inst_data.writer_bitmap(0)(20) {-height 15 -radix binary} /l0_dds_reader_test1_arznriu/uut/inst_data.writer_bitmap(0)(21) {-height 15 -radix binary} /l0_dds_reader_test1_arznriu/uut/inst_data.writer_bitmap(0)(22) {-height 15 -radix binary} /l0_dds_reader_test1_arznriu/uut/inst_data.writer_bitmap(0)(23) {-height 15 -radix binary} /l0_dds_reader_test1_arznriu/uut/inst_data.writer_bitmap(0)(24) {-height 15 -radix binary} /l0_dds_reader_test1_arznriu/uut/inst_data.writer_bitmap(0)(25) {-height 15 -radix binary} /l0_dds_reader_test1_arznriu/uut/inst_data.writer_bitmap(0)(26) {-height 15 -radix binary} /l0_dds_reader_test1_arznriu/uut/inst_data.writer_bitmap(0)(27) {-height 15 -radix binary} /l0_dds_reader_test1_arznriu/uut/inst_data.writer_bitmap(0)(28) {-height 15 -radix binary} /l0_dds_reader_test1_arznriu/uut/inst_data.writer_bitmap(0)(29) {-height 15 -radix binary} /l0_dds_reader_test1_arznriu/uut/inst_data.writer_bitmap(0)(30) {-height 15 -radix binary} /l0_dds_reader_test1_arznriu/uut/inst_data.writer_bitmap(0)(31) {-height 15 -radix binary}} /l0_dds_reader_test1_arznriu/uut/inst_data -add wave -noupdate -divider POINTERS -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test1_arznriu/uut/empty_sample_list_head -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test1_arznriu/uut/empty_sample_list_tail -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test1_arznriu/uut/empty_payload_list_head -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test1_arznriu/uut/oldest_sample -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test1_arznriu/uut/newest_sample -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test1_arznriu/uut/inst_empty_head -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test1_arznriu/uut/inst_occupied_head -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test1_arznriu/uut/cur_sample -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test1_arznriu/uut/next_sample -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test1_arznriu/uut/prev_sample -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test1_arznriu/uut/cur_payload -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test1_arznriu/uut/next_payload -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test1_arznriu/uut/cur_inst -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test1_arznriu/uut/next_inst -add wave -noupdate -divider MISC -add wave -noupdate /l0_dds_reader_test1_arznriu/uut/trigger_sample_gen -add wave -noupdate /l0_dds_reader_test1_arznriu/uut/wait_for_sample_removal -add wave -noupdate /l0_dds_reader_test1_arznriu/uut/sample_p1 -add wave -noupdate /l0_dds_reader_test1_arznriu/uut/sample_p2 -add wave -noupdate -radix unsigned /l0_dds_reader_test1_arznriu/uut/collection_cnt -add wave -noupdate -radix unsigned /l0_dds_reader_test1_arznriu/uut/collection_cnt_max -add wave -noupdate -radix unsigned /l0_dds_reader_test1_arznriu/uut/collection_generation_rank -add wave -noupdate -radix unsigned /l0_dds_reader_test1_arznriu/uut/cur_generation_rank -add wave -noupdate -radix unsigned /l0_dds_reader_test1_arznriu/uut/max_samples_latch -add wave -noupdate /l0_dds_reader_test1_arznriu/uut/single_instance -add wave -noupdate /l0_dds_reader_test1_arznriu/uut/is_take -add wave -noupdate -divider TESTBENCH -add wave -noupdate -group TESTBENCH /l0_dds_reader_test1_arznriu/dds_start -add wave -noupdate -group TESTBENCH /l0_dds_reader_test1_arznriu/dds_stage -add wave -noupdate -group TESTBENCH /l0_dds_reader_test1_arznriu/dds_cnt -add wave -noupdate -group TESTBENCH /l0_dds_reader_test1_arznriu/dds_cnt2 -add wave -noupdate -group TESTBENCH /l0_dds_reader_test1_arznriu/dds_done -add wave -noupdate -group TESTBENCH /l0_dds_reader_test1_arznriu/rtps_start -add wave -noupdate -group TESTBENCH /l0_dds_reader_test1_arznriu/rtps_stage -add wave -noupdate -group TESTBENCH /l0_dds_reader_test1_arznriu/rtps_cnt -add wave -noupdate -group TESTBENCH /l0_dds_reader_test1_arznriu/rtps_done -add wave -noupdate -divider {KEY HOLDER} -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test1_arznriu/uut/start_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test1_arznriu/uut/opcode_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test1_arznriu/uut/ack_kh -add wave -noupdate -group {KEY HOLDER} -radix hexadecimal /l0_dds_reader_test1_arznriu/uut/data_in_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test1_arznriu/uut/valid_in_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test1_arznriu/uut/ready_in_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test1_arznriu/uut/last_word_in_kh -add wave -noupdate -group {KEY HOLDER} -radix hexadecimal /l0_dds_reader_test1_arznriu/uut/data_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test1_arznriu/uut/valid_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test1_arznriu/uut/ready_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test1_arznriu/uut/last_word_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test1_arznriu/uut/abort_kh -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {77695423 ps} 0} {{Cursor 2} {115175000 ps} 1} -quietly wave cursor active 1 -configure wave -namecolwidth 187 -configure wave -valuecolwidth 206 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -configure wave -timelineunits ns -update -WaveRestoreZoom {76925214 ps} {77858935 ps} diff --git a/sim/L0_dds_reader_test1_lbzkriu.do b/sim/L0_dds_reader_test1_lbzkriu.do deleted file mode 100644 index 8dfaf97..0000000 --- a/sim/L0_dds_reader_test1_lbzkriu.do +++ /dev/null @@ -1,196 +0,0 @@ -onerror {resume} -radix define DDS_RETCODE { - "10#0#" "RETCODE_OK", - "10#1#" "RETCODE_ERROR", - "10#2#" "RETCODE_UNSUPPORTED", - "10#3#" "RETCODE_BAD_PARAMETER", - "10#4#" "RETCODE_PRECONDITION_NOT_MET", - "10#5#" "RETCODE_OUT_OF_RESOURCES", - "10#6#" "RETCODE_NOT_ENABLED", - "10#7#" "RETCODE_IMMUTABLE_POLICY", - "10#8#" "RETCODE_INCONSISTENT_POLICY", - "10#9#" "RETCODE_ALREADY_DELETED", - "10#10#" "RETCODE_TIMEOUT", - "10#11#" "RETCODE_NO_DATA", - "10#12#" "RETCODE_ILLEGAL_OPERATION", - -default unsigned -} -radix define SAMPLE_STATE { - "16#00000001#" "READ_SAMPLE_STATE", - "16#00000002#" "NOT_READ_SAMPLE_STATE", - "16#FFFFFFFF#" "ANY_SAMPLE_STATE", - -default binary -} -radix define VIEW_STATE { - "16#00000001#" "NEW_VIEW_STATE", - "16#00000002#" "NOT_NEW_VIEW_STATE", - "16#FFFFFFFF#" "ANY_VIEW_STATE", - -default binary -} -radix define INSTANCE_STATE { - "16#00000001#" "ALIVE_INSTANCE_STATE", - "16#00000002#" "NOT_ALIVE_DISPOSED_INSTANCE_STATE", - "16#00000004#" "NOT_ALIVE_NO_WRITERS_INSTANCE_STATE", - "16#FFFFFFFF#" "ANY_INSTANCE_STATE", - -default binary -} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -divider SYSTEM -add wave -noupdate /l0_dds_reader_test1_lbzkriu/uut/clk -add wave -noupdate /l0_dds_reader_test1_lbzkriu/uut/reset -add wave -noupdate /l0_dds_reader_test1_lbzkriu/uut/time -add wave -noupdate -divider RTPS -add wave -noupdate -expand -group RTPS /l0_dds_reader_test1_lbzkriu/uut/start_rtps -add wave -noupdate -expand -group RTPS /l0_dds_reader_test1_lbzkriu/uut/opcode_rtps -add wave -noupdate -expand -group RTPS /l0_dds_reader_test1_lbzkriu/uut/ack_rtps -add wave -noupdate -expand -group RTPS /l0_dds_reader_test1_lbzkriu/uut/ret_rtps -add wave -noupdate -expand -group RTPS /l0_dds_reader_test1_lbzkriu/uut/done_rtps -add wave -noupdate -expand -group RTPS /l0_dds_reader_test1_lbzkriu/uut/ready_in_rtps -add wave -noupdate -expand -group RTPS /l0_dds_reader_test1_lbzkriu/uut/valid_in_rtps -add wave -noupdate -expand -group RTPS -radix hexadecimal /l0_dds_reader_test1_lbzkriu/uut/data_in_rtps -add wave -noupdate -expand -group RTPS /l0_dds_reader_test1_lbzkriu/uut/last_word_in_rtps -add wave -noupdate -divider DDS -add wave -noupdate -group DDS /l0_dds_reader_test1_lbzkriu/uut/start_dds -add wave -noupdate -group DDS /l0_dds_reader_test1_lbzkriu/uut/ack_dds -add wave -noupdate -group DDS /l0_dds_reader_test1_lbzkriu/uut/opcode_dds -add wave -noupdate -group DDS -radix SAMPLE_STATE /l0_dds_reader_test1_lbzkriu/uut/sample_state_dds -add wave -noupdate -group DDS -radix INSTANCE_STATE /l0_dds_reader_test1_lbzkriu/uut/instance_state_dds -add wave -noupdate -group DDS -radix VIEW_STATE /l0_dds_reader_test1_lbzkriu/uut/view_state_dds -add wave -noupdate -group DDS -radix hexadecimal /l0_dds_reader_test1_lbzkriu/uut/instance_handle_dds -add wave -noupdate -group DDS -radix unsigned /l0_dds_reader_test1_lbzkriu/uut/max_samples_dds -add wave -noupdate -group DDS -radix DDS_RETCODE /l0_dds_reader_test1_lbzkriu/uut/return_code_dds -add wave -noupdate -group DDS /l0_dds_reader_test1_lbzkriu/uut/done_dds -add wave -noupdate -group DDS -divider SI -add wave -noupdate -group DDS -radix SAMPLE_STATE /l0_dds_reader_test1_lbzkriu/uut/si_sample_state -add wave -noupdate -group DDS -radix VIEW_STATE /l0_dds_reader_test1_lbzkriu/uut/si_view_state -add wave -noupdate -group DDS -radix INSTANCE_STATE /l0_dds_reader_test1_lbzkriu/uut/si_instance_state -add wave -noupdate -group DDS -radix unsigned /l0_dds_reader_test1_lbzkriu/uut/si_source_timestamp -add wave -noupdate -group DDS -radix hexadecimal /l0_dds_reader_test1_lbzkriu/uut/si_instance_handle -add wave -noupdate -group DDS -radix hexadecimal /l0_dds_reader_test1_lbzkriu/uut/si_publication_handle -add wave -noupdate -group DDS -radix unsigned /l0_dds_reader_test1_lbzkriu/uut/si_disposed_generation_count -add wave -noupdate -group DDS -radix unsigned /l0_dds_reader_test1_lbzkriu/uut/si_no_writers_generation_count -add wave -noupdate -group DDS -radix unsigned /l0_dds_reader_test1_lbzkriu/uut/si_sample_rank -add wave -noupdate -group DDS -radix unsigned /l0_dds_reader_test1_lbzkriu/uut/si_generation_rank -add wave -noupdate -group DDS -radix unsigned /l0_dds_reader_test1_lbzkriu/uut/si_absolute_generation_rank -add wave -noupdate -group DDS /l0_dds_reader_test1_lbzkriu/uut/si_valid_data -add wave -noupdate -group DDS /l0_dds_reader_test1_lbzkriu/uut/si_valid -add wave -noupdate -group DDS /l0_dds_reader_test1_lbzkriu/uut/eoc -add wave -noupdate -group DDS /l0_dds_reader_test1_lbzkriu/uut/get_data_dds -add wave -noupdate -group DDS -divider OUTPUT -add wave -noupdate -group DDS /l0_dds_reader_test1_lbzkriu/uut/ready_out_dds -add wave -noupdate -group DDS /l0_dds_reader_test1_lbzkriu/uut/valid_out_dds -add wave -noupdate -group DDS -radix hexadecimal /l0_dds_reader_test1_lbzkriu/uut/data_out_dds -add wave -noupdate -group DDS /l0_dds_reader_test1_lbzkriu/uut/last_word_out_dds -add wave -noupdate -divider {MAIN FSM} -add wave -noupdate /l0_dds_reader_test1_lbzkriu/uut/stage -add wave -noupdate /l0_dds_reader_test1_lbzkriu/uut/stage_next -add wave -noupdate /l0_dds_reader_test1_lbzkriu/uut/cnt -add wave -noupdate -divider MEMORY -add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test1_lbzkriu/uut/sample_abort_read -add wave -noupdate -group {SAMPLE MEM} -radix unsigned /l0_dds_reader_test1_lbzkriu/uut/sample_mem_ctrl_inst/addr -add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test1_lbzkriu/uut/sample_mem_ctrl_inst/read -add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test1_lbzkriu/uut/sample_mem_ctrl_inst/ready_in -add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test1_lbzkriu/uut/sample_mem_ctrl_inst/valid_in -add wave -noupdate -group {SAMPLE MEM} -radix hexadecimal /l0_dds_reader_test1_lbzkriu/uut/sample_mem_ctrl_inst/data_in -add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test1_lbzkriu/uut/sample_mem_ctrl_inst/ready_out -add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test1_lbzkriu/uut/sample_mem_ctrl_inst/valid_out -add wave -noupdate -group {SAMPLE MEM} -radix hexadecimal /l0_dds_reader_test1_lbzkriu/uut/sample_mem_ctrl_inst/data_out -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test1_lbzkriu/uut/payload_abort_read -add wave -noupdate -group {PAYLOAD MEM} -radix unsigned /l0_dds_reader_test1_lbzkriu/uut/payload_mem_ctrl_inst/addr -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test1_lbzkriu/uut/payload_mem_ctrl_inst/read -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test1_lbzkriu/uut/payload_mem_ctrl_inst/ready_in -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test1_lbzkriu/uut/payload_mem_ctrl_inst/valid_in -add wave -noupdate -group {PAYLOAD MEM} -radix hexadecimal /l0_dds_reader_test1_lbzkriu/uut/payload_mem_ctrl_inst/data_in -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test1_lbzkriu/uut/payload_mem_ctrl_inst/ready_out -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test1_lbzkriu/uut/payload_mem_ctrl_inst/valid_out -add wave -noupdate -group {PAYLOAD MEM} -radix hexadecimal /l0_dds_reader_test1_lbzkriu/uut/payload_mem_ctrl_inst/data_out -add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test1_lbzkriu/uut/inst_abort_read -add wave -noupdate -group {INSTANCE MEM} -radix unsigned /l0_dds_reader_test1_lbzkriu/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/addr -add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test1_lbzkriu/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/read -add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test1_lbzkriu/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/ready_in -add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test1_lbzkriu/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/valid_in -add wave -noupdate -group {INSTANCE MEM} -radix hexadecimal /l0_dds_reader_test1_lbzkriu/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/data_in -add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test1_lbzkriu/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/ready_out -add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test1_lbzkriu/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/valid_out -add wave -noupdate -group {INSTANCE MEM} -radix hexadecimal /l0_dds_reader_test1_lbzkriu/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/data_out -add wave -noupdate /l0_dds_reader_test1_lbzkriu/uut/inst_op_start -add wave -noupdate /l0_dds_reader_test1_lbzkriu/uut/inst_opcode -add wave -noupdate /l0_dds_reader_test1_lbzkriu/uut/inst_op_done -add wave -noupdate /l0_dds_reader_test1_lbzkriu/uut/inst_stage -add wave -noupdate /l0_dds_reader_test1_lbzkriu/uut/inst_stage_next -add wave -noupdate /l0_dds_reader_test1_lbzkriu/uut/inst_cnt -add wave -noupdate -radix unsigned /l0_dds_reader_test1_lbzkriu/uut/inst_addr_base -add wave -noupdate /l0_dds_reader_test1_lbzkriu/uut/inst_mem_fields -add wave -noupdate -childformat {{/l0_dds_reader_test1_lbzkriu/uut/inst_data.key_hash -radix hexadecimal} {/l0_dds_reader_test1_lbzkriu/uut/inst_data.status_info -radix binary} {/l0_dds_reader_test1_lbzkriu/uut/inst_data.sample_cnt -radix unsigned} {/l0_dds_reader_test1_lbzkriu/uut/inst_data.disposed_gen_cnt -radix unsigned} {/l0_dds_reader_test1_lbzkriu/uut/inst_data.no_writers_gen_cnt -radix unsigned} {/l0_dds_reader_test1_lbzkriu/uut/inst_data.ignore_deadline -radix unsigned} {/l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap -radix binary -childformat {{/l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0) -radix binary -childformat {{/l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(0) -radix binary} {/l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(1) -radix binary} {/l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(2) -radix binary} {/l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(3) -radix binary} {/l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(4) -radix binary} {/l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(5) -radix binary} {/l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(6) -radix binary} {/l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(7) -radix binary} {/l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(8) -radix binary} {/l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(9) -radix binary} {/l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(10) -radix binary} {/l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(11) -radix binary} {/l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(12) -radix binary} {/l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(13) -radix binary} {/l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(14) -radix binary} {/l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(15) -radix binary} {/l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(16) -radix binary} {/l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(17) -radix binary} {/l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(18) -radix binary} {/l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(19) -radix binary} {/l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(20) -radix binary} {/l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(21) -radix binary} {/l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(22) -radix binary} {/l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(23) -radix binary} {/l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(24) -radix binary} {/l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(25) -radix binary} {/l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(26) -radix binary} {/l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(27) -radix binary} {/l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(28) -radix binary} {/l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(29) -radix binary} {/l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(30) -radix binary} {/l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(31) -radix binary}}}}}} -expand -subitemconfig {/l0_dds_reader_test1_lbzkriu/uut/inst_data.key_hash {-height 15 -radix hexadecimal} /l0_dds_reader_test1_lbzkriu/uut/inst_data.status_info {-height 15 -radix binary} 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-radix binary} {/l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(6) -radix binary} {/l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(7) -radix binary} {/l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(8) -radix binary} {/l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(9) -radix binary} {/l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(10) -radix binary} {/l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(11) -radix binary} {/l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(12) -radix binary} {/l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(13) -radix binary} {/l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(14) -radix binary} {/l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(15) -radix binary} {/l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(16) -radix binary} {/l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(17) -radix binary} {/l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(18) -radix binary} {/l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(19) -radix binary} {/l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(20) -radix binary} {/l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(21) -radix binary} {/l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(22) -radix binary} {/l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(23) -radix binary} {/l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(24) -radix binary} {/l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(25) -radix binary} {/l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(26) -radix binary} {/l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(27) -radix binary} {/l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(28) -radix binary} {/l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(29) -radix binary} {/l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(30) -radix binary} {/l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(31) -radix binary}}}}} /l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0) {-height 15 -radix binary -childformat {{/l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(0) -radix binary} {/l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(1) -radix binary} {/l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(2) -radix binary} {/l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(3) -radix binary} {/l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(4) -radix binary} {/l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(5) -radix binary} {/l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(6) -radix binary} {/l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(7) -radix binary} {/l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(8) -radix binary} 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{/l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(21) -radix binary} {/l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(22) -radix binary} {/l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(23) -radix binary} {/l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(24) -radix binary} {/l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(25) -radix binary} {/l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(26) -radix binary} {/l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(27) -radix binary} {/l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(28) -radix binary} {/l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(29) -radix binary} {/l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(30) -radix binary} {/l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(31) -radix binary}}} /l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(0) {-height 15 -radix binary} /l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(1) {-height 15 -radix binary} /l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(2) {-height 15 -radix binary} /l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(3) {-height 15 -radix binary} /l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(4) {-height 15 -radix binary} /l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(5) {-height 15 -radix binary} /l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(6) {-height 15 -radix binary} /l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(7) {-height 15 -radix binary} /l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(8) {-height 15 -radix binary} /l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(9) {-height 15 -radix binary} /l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(10) {-height 15 -radix binary} /l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(11) {-height 15 -radix binary} /l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(12) {-height 15 -radix binary} /l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(13) {-height 15 -radix binary} /l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(14) {-height 15 -radix binary} /l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(15) {-height 15 -radix binary} /l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(16) {-height 15 -radix binary} /l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(17) {-height 15 -radix binary} /l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(18) {-height 15 -radix binary} /l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(19) {-height 15 -radix binary} /l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(20) {-height 15 -radix binary} /l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(21) {-height 15 -radix binary} /l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(22) {-height 15 -radix binary} /l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(23) {-height 15 -radix binary} /l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(24) {-height 15 -radix binary} /l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(25) {-height 15 -radix binary} /l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(26) {-height 15 -radix binary} /l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(27) {-height 15 -radix binary} /l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(28) {-height 15 -radix binary} /l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(29) {-height 15 -radix binary} /l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(30) {-height 15 -radix binary} /l0_dds_reader_test1_lbzkriu/uut/inst_data.writer_bitmap(0)(31) {-height 15 -radix binary}} /l0_dds_reader_test1_lbzkriu/uut/inst_data -add wave -noupdate -radix unsigned /l0_dds_reader_test1_lbzkriu/uut/inst_next_addr_base -add wave -noupdate -radix unsigned /l0_dds_reader_test1_lbzkriu/uut/inst_prev_addr_base -add wave -noupdate /l0_dds_reader_test1_lbzkriu/uut/current_imf -add wave -noupdate /l0_dds_reader_test1_lbzkriu/uut/stale_inst_cnt -add wave -noupdate -divider POINTERS -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test1_lbzkriu/uut/empty_sample_list_head -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test1_lbzkriu/uut/empty_sample_list_tail -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test1_lbzkriu/uut/empty_payload_list_head -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test1_lbzkriu/uut/oldest_sample -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test1_lbzkriu/uut/newest_sample -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test1_lbzkriu/uut/inst_empty_head -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test1_lbzkriu/uut/inst_occupied_head -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test1_lbzkriu/uut/cur_sample -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test1_lbzkriu/uut/next_sample -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test1_lbzkriu/uut/prev_sample -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test1_lbzkriu/uut/cur_payload -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test1_lbzkriu/uut/next_payload -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test1_lbzkriu/uut/cur_inst -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test1_lbzkriu/uut/next_inst -add wave -noupdate -divider MISC -add wave -noupdate /l0_dds_reader_test1_lbzkriu/uut/trigger_sample_gen -add wave -noupdate /l0_dds_reader_test1_lbzkriu/uut/wait_for_sample_removal -add wave -noupdate /l0_dds_reader_test1_lbzkriu/uut/sample_p1 -add wave -noupdate /l0_dds_reader_test1_lbzkriu/uut/sample_p2 -add wave -noupdate -radix unsigned /l0_dds_reader_test1_lbzkriu/uut/collection_cnt -add wave -noupdate -radix unsigned /l0_dds_reader_test1_lbzkriu/uut/collection_cnt_max -add wave -noupdate -radix unsigned /l0_dds_reader_test1_lbzkriu/uut/collection_generation_rank -add wave -noupdate -radix unsigned /l0_dds_reader_test1_lbzkriu/uut/cur_generation_rank -add wave -noupdate -radix unsigned /l0_dds_reader_test1_lbzkriu/uut/max_samples_latch -add wave -noupdate /l0_dds_reader_test1_lbzkriu/uut/single_instance -add wave -noupdate /l0_dds_reader_test1_lbzkriu/uut/is_take -add wave -noupdate -divider TESTBENCH -add wave -noupdate -group TESTBENCH /l0_dds_reader_test1_lbzkriu/dds_start -add wave -noupdate -group TESTBENCH /l0_dds_reader_test1_lbzkriu/dds_stage -add wave -noupdate -group TESTBENCH /l0_dds_reader_test1_lbzkriu/dds_cnt -add wave -noupdate -group TESTBENCH /l0_dds_reader_test1_lbzkriu/dds_cnt2 -add wave -noupdate -group TESTBENCH /l0_dds_reader_test1_lbzkriu/dds_done -add wave -noupdate -group TESTBENCH /l0_dds_reader_test1_lbzkriu/rtps_start -add wave -noupdate -group TESTBENCH /l0_dds_reader_test1_lbzkriu/rtps_stage -add wave -noupdate -group TESTBENCH /l0_dds_reader_test1_lbzkriu/rtps_cnt -add wave -noupdate -group TESTBENCH /l0_dds_reader_test1_lbzkriu/rtps_done -add wave -noupdate -divider {KEY HOLDER} -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test1_lbzkriu/uut/start_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test1_lbzkriu/uut/opcode_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test1_lbzkriu/uut/ack_kh -add wave -noupdate -group {KEY HOLDER} -radix hexadecimal /l0_dds_reader_test1_lbzkriu/uut/data_in_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test1_lbzkriu/uut/valid_in_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test1_lbzkriu/uut/ready_in_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test1_lbzkriu/uut/last_word_in_kh -add wave -noupdate -group {KEY HOLDER} -radix hexadecimal /l0_dds_reader_test1_lbzkriu/uut/data_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test1_lbzkriu/uut/valid_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test1_lbzkriu/uut/ready_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test1_lbzkriu/uut/last_word_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test1_lbzkriu/uut/abort_kh -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {77695423 ps} 0} {{Cursor 2} {115175000 ps} 1} -quietly wave cursor active 1 -configure wave -namecolwidth 187 -configure wave -valuecolwidth 206 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -configure wave -timelineunits ns -update -WaveRestoreZoom {76925214 ps} {77858935 ps} diff --git a/sim/L0_dds_reader_test1_lrzkriu.do b/sim/L0_dds_reader_test1_lrzkriu.do deleted file mode 100644 index b516407..0000000 --- a/sim/L0_dds_reader_test1_lrzkriu.do +++ /dev/null @@ -1,196 +0,0 @@ -onerror {resume} -radix define DDS_RETCODE { - "10#0#" "RETCODE_OK", - "10#1#" "RETCODE_ERROR", - "10#2#" "RETCODE_UNSUPPORTED", - "10#3#" "RETCODE_BAD_PARAMETER", - "10#4#" "RETCODE_PRECONDITION_NOT_MET", - "10#5#" "RETCODE_OUT_OF_RESOURCES", - "10#6#" "RETCODE_NOT_ENABLED", - "10#7#" "RETCODE_IMMUTABLE_POLICY", - "10#8#" "RETCODE_INCONSISTENT_POLICY", - "10#9#" "RETCODE_ALREADY_DELETED", - "10#10#" "RETCODE_TIMEOUT", - "10#11#" "RETCODE_NO_DATA", - "10#12#" "RETCODE_ILLEGAL_OPERATION", - -default unsigned -} -radix define SAMPLE_STATE { - "16#00000001#" "READ_SAMPLE_STATE", - "16#00000002#" "NOT_READ_SAMPLE_STATE", - "16#FFFFFFFF#" "ANY_SAMPLE_STATE", - -default binary -} -radix define VIEW_STATE { - "16#00000001#" "NEW_VIEW_STATE", - "16#00000002#" "NOT_NEW_VIEW_STATE", - "16#FFFFFFFF#" "ANY_VIEW_STATE", - -default binary -} -radix define INSTANCE_STATE { - "16#00000001#" "ALIVE_INSTANCE_STATE", - "16#00000002#" "NOT_ALIVE_DISPOSED_INSTANCE_STATE", - "16#00000004#" "NOT_ALIVE_NO_WRITERS_INSTANCE_STATE", - "16#FFFFFFFF#" "ANY_INSTANCE_STATE", - -default binary -} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -divider SYSTEM -add wave -noupdate /l0_dds_reader_test1_lrzkriu/uut/clk -add wave -noupdate /l0_dds_reader_test1_lrzkriu/uut/reset -add wave -noupdate /l0_dds_reader_test1_lrzkriu/uut/time -add wave -noupdate -divider RTPS -add wave -noupdate -expand -group RTPS /l0_dds_reader_test1_lrzkriu/uut/start_rtps -add wave -noupdate -expand -group RTPS /l0_dds_reader_test1_lrzkriu/uut/opcode_rtps -add wave -noupdate -expand -group RTPS /l0_dds_reader_test1_lrzkriu/uut/ack_rtps -add wave -noupdate -expand -group RTPS /l0_dds_reader_test1_lrzkriu/uut/ret_rtps -add wave -noupdate -expand -group RTPS /l0_dds_reader_test1_lrzkriu/uut/done_rtps -add wave -noupdate -expand -group RTPS /l0_dds_reader_test1_lrzkriu/uut/ready_in_rtps -add wave -noupdate -expand -group RTPS /l0_dds_reader_test1_lrzkriu/uut/valid_in_rtps -add wave -noupdate -expand -group RTPS -radix hexadecimal /l0_dds_reader_test1_lrzkriu/uut/data_in_rtps -add wave -noupdate -expand -group RTPS /l0_dds_reader_test1_lrzkriu/uut/last_word_in_rtps -add wave -noupdate -divider DDS -add wave -noupdate -group DDS /l0_dds_reader_test1_lrzkriu/uut/start_dds -add wave -noupdate -group DDS /l0_dds_reader_test1_lrzkriu/uut/ack_dds -add wave -noupdate -group DDS /l0_dds_reader_test1_lrzkriu/uut/opcode_dds -add wave -noupdate -group DDS -radix SAMPLE_STATE /l0_dds_reader_test1_lrzkriu/uut/sample_state_dds -add wave -noupdate -group DDS -radix INSTANCE_STATE /l0_dds_reader_test1_lrzkriu/uut/instance_state_dds -add wave -noupdate -group DDS -radix VIEW_STATE /l0_dds_reader_test1_lrzkriu/uut/view_state_dds -add wave -noupdate -group DDS -radix hexadecimal /l0_dds_reader_test1_lrzkriu/uut/instance_handle_dds -add wave -noupdate -group DDS -radix unsigned /l0_dds_reader_test1_lrzkriu/uut/max_samples_dds -add wave -noupdate -group DDS -radix DDS_RETCODE /l0_dds_reader_test1_lrzkriu/uut/return_code_dds -add wave -noupdate -group DDS /l0_dds_reader_test1_lrzkriu/uut/done_dds -add wave -noupdate -group DDS -divider SI -add wave -noupdate -group DDS -radix SAMPLE_STATE /l0_dds_reader_test1_lrzkriu/uut/si_sample_state -add wave -noupdate -group DDS -radix VIEW_STATE /l0_dds_reader_test1_lrzkriu/uut/si_view_state -add wave -noupdate -group DDS -radix INSTANCE_STATE /l0_dds_reader_test1_lrzkriu/uut/si_instance_state -add wave -noupdate -group DDS -radix unsigned /l0_dds_reader_test1_lrzkriu/uut/si_source_timestamp -add wave -noupdate -group DDS -radix hexadecimal /l0_dds_reader_test1_lrzkriu/uut/si_instance_handle -add wave -noupdate -group DDS -radix hexadecimal /l0_dds_reader_test1_lrzkriu/uut/si_publication_handle -add wave -noupdate -group DDS -radix unsigned /l0_dds_reader_test1_lrzkriu/uut/si_disposed_generation_count -add wave -noupdate -group DDS -radix unsigned /l0_dds_reader_test1_lrzkriu/uut/si_no_writers_generation_count -add wave -noupdate -group DDS -radix unsigned /l0_dds_reader_test1_lrzkriu/uut/si_sample_rank -add wave -noupdate -group DDS -radix unsigned /l0_dds_reader_test1_lrzkriu/uut/si_generation_rank -add wave -noupdate -group DDS -radix unsigned /l0_dds_reader_test1_lrzkriu/uut/si_absolute_generation_rank -add wave -noupdate -group DDS /l0_dds_reader_test1_lrzkriu/uut/si_valid_data -add wave -noupdate -group DDS /l0_dds_reader_test1_lrzkriu/uut/si_valid -add wave -noupdate -group DDS /l0_dds_reader_test1_lrzkriu/uut/eoc -add wave -noupdate -group DDS /l0_dds_reader_test1_lrzkriu/uut/get_data_dds -add wave -noupdate -group DDS -divider OUTPUT -add wave -noupdate -group DDS /l0_dds_reader_test1_lrzkriu/uut/ready_out_dds -add wave -noupdate -group DDS /l0_dds_reader_test1_lrzkriu/uut/valid_out_dds -add wave -noupdate -group DDS -radix hexadecimal /l0_dds_reader_test1_lrzkriu/uut/data_out_dds -add wave -noupdate -group DDS /l0_dds_reader_test1_lrzkriu/uut/last_word_out_dds -add wave -noupdate -divider {MAIN FSM} -add wave -noupdate /l0_dds_reader_test1_lrzkriu/uut/stage -add wave -noupdate /l0_dds_reader_test1_lrzkriu/uut/stage_next -add wave -noupdate /l0_dds_reader_test1_lrzkriu/uut/cnt -add wave -noupdate -divider MEMORY -add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test1_lrzkriu/uut/sample_abort_read -add wave -noupdate -group {SAMPLE MEM} -radix unsigned /l0_dds_reader_test1_lrzkriu/uut/sample_mem_ctrl_inst/addr -add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test1_lrzkriu/uut/sample_mem_ctrl_inst/read -add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test1_lrzkriu/uut/sample_mem_ctrl_inst/ready_in -add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test1_lrzkriu/uut/sample_mem_ctrl_inst/valid_in -add wave -noupdate -group {SAMPLE MEM} -radix hexadecimal /l0_dds_reader_test1_lrzkriu/uut/sample_mem_ctrl_inst/data_in -add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test1_lrzkriu/uut/sample_mem_ctrl_inst/ready_out -add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test1_lrzkriu/uut/sample_mem_ctrl_inst/valid_out -add wave -noupdate -group {SAMPLE MEM} -radix hexadecimal /l0_dds_reader_test1_lrzkriu/uut/sample_mem_ctrl_inst/data_out -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test1_lrzkriu/uut/payload_abort_read -add wave -noupdate -group {PAYLOAD MEM} -radix unsigned /l0_dds_reader_test1_lrzkriu/uut/payload_mem_ctrl_inst/addr -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test1_lrzkriu/uut/payload_mem_ctrl_inst/read -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test1_lrzkriu/uut/payload_mem_ctrl_inst/ready_in -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test1_lrzkriu/uut/payload_mem_ctrl_inst/valid_in -add wave -noupdate -group {PAYLOAD MEM} -radix hexadecimal /l0_dds_reader_test1_lrzkriu/uut/payload_mem_ctrl_inst/data_in -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test1_lrzkriu/uut/payload_mem_ctrl_inst/ready_out -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test1_lrzkriu/uut/payload_mem_ctrl_inst/valid_out -add wave -noupdate -group {PAYLOAD MEM} -radix hexadecimal /l0_dds_reader_test1_lrzkriu/uut/payload_mem_ctrl_inst/data_out -add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test1_lrzkriu/uut/inst_abort_read -add wave -noupdate -group {INSTANCE MEM} -radix unsigned /l0_dds_reader_test1_lrzkriu/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/addr -add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test1_lrzkriu/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/read -add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test1_lrzkriu/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/ready_in -add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test1_lrzkriu/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/valid_in -add wave -noupdate -group {INSTANCE MEM} -radix hexadecimal /l0_dds_reader_test1_lrzkriu/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/data_in -add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test1_lrzkriu/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/ready_out -add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test1_lrzkriu/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/valid_out -add wave -noupdate -group {INSTANCE MEM} -radix hexadecimal /l0_dds_reader_test1_lrzkriu/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/data_out -add wave -noupdate /l0_dds_reader_test1_lrzkriu/uut/inst_op_start -add wave -noupdate /l0_dds_reader_test1_lrzkriu/uut/inst_opcode -add wave -noupdate /l0_dds_reader_test1_lrzkriu/uut/inst_op_done -add wave -noupdate /l0_dds_reader_test1_lrzkriu/uut/inst_stage -add wave -noupdate /l0_dds_reader_test1_lrzkriu/uut/inst_stage_next -add wave -noupdate /l0_dds_reader_test1_lrzkriu/uut/inst_cnt -add wave -noupdate -radix unsigned /l0_dds_reader_test1_lrzkriu/uut/inst_addr_base -add wave -noupdate /l0_dds_reader_test1_lrzkriu/uut/inst_mem_fields -add wave -noupdate -childformat {{/l0_dds_reader_test1_lrzkriu/uut/inst_data.key_hash -radix hexadecimal} {/l0_dds_reader_test1_lrzkriu/uut/inst_data.status_info -radix binary} {/l0_dds_reader_test1_lrzkriu/uut/inst_data.sample_cnt -radix unsigned} {/l0_dds_reader_test1_lrzkriu/uut/inst_data.disposed_gen_cnt -radix unsigned} {/l0_dds_reader_test1_lrzkriu/uut/inst_data.no_writers_gen_cnt -radix unsigned} {/l0_dds_reader_test1_lrzkriu/uut/inst_data.ignore_deadline -radix unsigned} {/l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap -radix binary -childformat {{/l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0) -radix binary -childformat {{/l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(0) -radix binary} {/l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(1) -radix binary} {/l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(2) -radix binary} {/l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(3) -radix binary} {/l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(4) -radix binary} {/l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(5) -radix binary} {/l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(6) -radix binary} {/l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(7) -radix binary} {/l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(8) -radix binary} {/l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(9) -radix binary} {/l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(10) -radix binary} {/l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(11) -radix binary} {/l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(12) -radix binary} {/l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(13) -radix binary} {/l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(14) -radix binary} {/l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(15) -radix binary} {/l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(16) -radix binary} {/l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(17) -radix binary} {/l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(18) -radix binary} {/l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(19) -radix binary} {/l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(20) -radix binary} {/l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(21) -radix binary} {/l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(22) -radix binary} {/l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(23) -radix binary} {/l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(24) -radix binary} {/l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(25) -radix binary} {/l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(26) -radix binary} {/l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(27) -radix binary} {/l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(28) -radix binary} {/l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(29) -radix binary} {/l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(30) -radix binary} {/l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(31) -radix binary}}}}}} -expand -subitemconfig {/l0_dds_reader_test1_lrzkriu/uut/inst_data.key_hash {-height 15 -radix hexadecimal} /l0_dds_reader_test1_lrzkriu/uut/inst_data.status_info {-height 15 -radix binary} /l0_dds_reader_test1_lrzkriu/uut/inst_data.sample_cnt {-height 15 -radix unsigned} /l0_dds_reader_test1_lrzkriu/uut/inst_data.disposed_gen_cnt {-height 15 -radix unsigned} /l0_dds_reader_test1_lrzkriu/uut/inst_data.no_writers_gen_cnt {-height 15 -radix unsigned} /l0_dds_reader_test1_lrzkriu/uut/inst_data.ignore_deadline {-height 15 -radix unsigned} /l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap {-height 15 -radix binary -childformat {{/l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0) -radix binary -childformat {{/l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(0) -radix binary} {/l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(1) -radix binary} {/l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(2) -radix binary} {/l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(3) -radix binary} {/l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(4) -radix binary} {/l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(5) -radix binary} {/l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(6) -radix binary} {/l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(7) -radix binary} {/l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(8) -radix binary} {/l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(9) -radix binary} {/l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(10) -radix binary} {/l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(11) -radix binary} {/l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(12) -radix binary} {/l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(13) -radix binary} {/l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(14) -radix binary} {/l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(15) -radix binary} {/l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(16) -radix binary} {/l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(17) -radix binary} {/l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(18) -radix binary} {/l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(19) -radix binary} {/l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(20) -radix binary} {/l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(21) -radix binary} {/l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(22) -radix binary} {/l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(23) -radix binary} {/l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(24) -radix binary} {/l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(25) -radix binary} {/l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(26) -radix binary} {/l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(27) -radix binary} {/l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(28) -radix binary} {/l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(29) -radix binary} {/l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(30) -radix binary} {/l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(31) -radix binary}}}}} /l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0) {-height 15 -radix binary -childformat {{/l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(0) -radix binary} {/l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(1) -radix binary} {/l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(2) -radix binary} {/l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(3) -radix binary} {/l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(4) -radix binary} {/l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(5) -radix binary} {/l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(6) -radix binary} {/l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(7) -radix binary} {/l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(8) -radix binary} {/l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(9) -radix binary} {/l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(10) -radix binary} {/l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(11) -radix binary} {/l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(12) -radix binary} {/l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(13) -radix binary} {/l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(14) -radix binary} {/l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(15) -radix binary} {/l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(16) -radix binary} {/l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(17) -radix binary} {/l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(18) -radix binary} {/l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(19) -radix binary} {/l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(20) -radix binary} {/l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(21) -radix binary} {/l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(22) -radix binary} {/l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(23) -radix binary} {/l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(24) -radix binary} {/l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(25) -radix binary} {/l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(26) -radix binary} {/l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(27) -radix binary} {/l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(28) -radix binary} {/l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(29) -radix binary} {/l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(30) -radix binary} {/l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(31) -radix binary}}} /l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(0) {-height 15 -radix binary} /l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(1) {-height 15 -radix binary} /l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(2) {-height 15 -radix binary} /l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(3) {-height 15 -radix binary} /l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(4) {-height 15 -radix binary} /l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(5) {-height 15 -radix binary} /l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(6) {-height 15 -radix binary} /l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(7) {-height 15 -radix binary} /l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(8) {-height 15 -radix binary} /l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(9) {-height 15 -radix binary} /l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(10) {-height 15 -radix binary} /l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(11) {-height 15 -radix binary} /l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(12) {-height 15 -radix binary} /l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(13) {-height 15 -radix binary} /l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(14) {-height 15 -radix binary} /l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(15) {-height 15 -radix binary} /l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(16) {-height 15 -radix binary} /l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(17) {-height 15 -radix binary} /l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(18) {-height 15 -radix binary} /l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(19) {-height 15 -radix binary} /l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(20) {-height 15 -radix binary} /l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(21) {-height 15 -radix binary} /l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(22) {-height 15 -radix binary} /l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(23) {-height 15 -radix binary} /l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(24) {-height 15 -radix binary} /l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(25) {-height 15 -radix binary} /l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(26) {-height 15 -radix binary} /l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(27) {-height 15 -radix binary} /l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(28) {-height 15 -radix binary} /l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(29) {-height 15 -radix binary} /l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(30) {-height 15 -radix binary} /l0_dds_reader_test1_lrzkriu/uut/inst_data.writer_bitmap(0)(31) {-height 15 -radix binary}} /l0_dds_reader_test1_lrzkriu/uut/inst_data -add wave -noupdate -radix unsigned /l0_dds_reader_test1_lrzkriu/uut/inst_next_addr_base -add wave -noupdate -radix unsigned /l0_dds_reader_test1_lrzkriu/uut/inst_prev_addr_base -add wave -noupdate /l0_dds_reader_test1_lrzkriu/uut/current_imf -add wave -noupdate /l0_dds_reader_test1_lrzkriu/uut/stale_inst_cnt -add wave -noupdate -divider POINTERS -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test1_lrzkriu/uut/empty_sample_list_head -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test1_lrzkriu/uut/empty_sample_list_tail -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test1_lrzkriu/uut/empty_payload_list_head -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test1_lrzkriu/uut/oldest_sample -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test1_lrzkriu/uut/newest_sample -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test1_lrzkriu/uut/inst_empty_head -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test1_lrzkriu/uut/inst_occupied_head -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test1_lrzkriu/uut/cur_sample -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test1_lrzkriu/uut/next_sample -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test1_lrzkriu/uut/prev_sample -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test1_lrzkriu/uut/cur_payload -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test1_lrzkriu/uut/next_payload -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test1_lrzkriu/uut/cur_inst -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test1_lrzkriu/uut/next_inst -add wave -noupdate -divider MISC -add wave -noupdate /l0_dds_reader_test1_lrzkriu/uut/trigger_sample_gen -add wave -noupdate /l0_dds_reader_test1_lrzkriu/uut/wait_for_sample_removal -add wave -noupdate /l0_dds_reader_test1_lrzkriu/uut/sample_p1 -add wave -noupdate /l0_dds_reader_test1_lrzkriu/uut/sample_p2 -add wave -noupdate -radix unsigned /l0_dds_reader_test1_lrzkriu/uut/collection_cnt -add wave -noupdate -radix unsigned /l0_dds_reader_test1_lrzkriu/uut/collection_cnt_max -add wave -noupdate -radix unsigned /l0_dds_reader_test1_lrzkriu/uut/collection_generation_rank -add wave -noupdate -radix unsigned /l0_dds_reader_test1_lrzkriu/uut/cur_generation_rank -add wave -noupdate -radix unsigned /l0_dds_reader_test1_lrzkriu/uut/max_samples_latch -add wave -noupdate /l0_dds_reader_test1_lrzkriu/uut/single_instance -add wave -noupdate /l0_dds_reader_test1_lrzkriu/uut/is_take -add wave -noupdate -divider TESTBENCH -add wave -noupdate -group TESTBENCH /l0_dds_reader_test1_lrzkriu/dds_start -add wave -noupdate -group TESTBENCH /l0_dds_reader_test1_lrzkriu/dds_stage -add wave -noupdate -group TESTBENCH /l0_dds_reader_test1_lrzkriu/dds_cnt -add wave -noupdate -group TESTBENCH /l0_dds_reader_test1_lrzkriu/dds_cnt2 -add wave -noupdate -group TESTBENCH /l0_dds_reader_test1_lrzkriu/dds_done -add wave -noupdate -group TESTBENCH /l0_dds_reader_test1_lrzkriu/rtps_start -add wave -noupdate -group TESTBENCH /l0_dds_reader_test1_lrzkriu/rtps_stage -add wave -noupdate -group TESTBENCH /l0_dds_reader_test1_lrzkriu/rtps_cnt -add wave -noupdate -group TESTBENCH /l0_dds_reader_test1_lrzkriu/rtps_done -add wave -noupdate -divider {KEY HOLDER} -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test1_lrzkriu/uut/start_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test1_lrzkriu/uut/opcode_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test1_lrzkriu/uut/ack_kh -add wave -noupdate -group {KEY HOLDER} -radix hexadecimal /l0_dds_reader_test1_lrzkriu/uut/data_in_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test1_lrzkriu/uut/valid_in_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test1_lrzkriu/uut/ready_in_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test1_lrzkriu/uut/last_word_in_kh -add wave -noupdate -group {KEY HOLDER} -radix hexadecimal /l0_dds_reader_test1_lrzkriu/uut/data_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test1_lrzkriu/uut/valid_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test1_lrzkriu/uut/ready_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test1_lrzkriu/uut/last_word_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test1_lrzkriu/uut/abort_kh -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {77695423 ps} 0} {{Cursor 2} {115175000 ps} 1} -quietly wave cursor active 1 -configure wave -namecolwidth 187 -configure wave -valuecolwidth 206 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -configure wave -timelineunits ns -update -WaveRestoreZoom {76925214 ps} {77858935 ps} diff --git a/sim/L0_dds_reader_test2.do b/sim/L0_dds_reader_test2.do new file mode 100644 index 0000000..b82faac --- /dev/null +++ b/sim/L0_dds_reader_test2.do @@ -0,0 +1,190 @@ +onerror {resume} +radix define DDS_RETCODE { + "10#0#" "RETCODE_OK", + "10#1#" "RETCODE_ERROR", + "10#2#" "RETCODE_UNSUPPORTED", + "10#3#" "RETCODE_BAD_PARAMETER", + "10#4#" "RETCODE_PRECONDITION_NOT_MET", + "10#5#" "RETCODE_OUT_OF_RESOURCES", + "10#6#" "RETCODE_NOT_ENABLED", + "10#7#" "RETCODE_IMMUTABLE_POLICY", + "10#8#" "RETCODE_INCONSISTENT_POLICY", + "10#9#" "RETCODE_ALREADY_DELETED", + "10#10#" "RETCODE_TIMEOUT", + "10#11#" "RETCODE_NO_DATA", + "10#12#" "RETCODE_ILLEGAL_OPERATION", + -default unsigned +} +radix define SAMPLE_STATE { + "16#00000001#" "READ_SAMPLE_STATE", + "16#00000002#" "NOT_READ_SAMPLE_STATE", + "16#FFFFFFFF#" "ANY_SAMPLE_STATE", + -default binary +} +radix define VIEW_STATE { + "16#00000001#" "NEW_VIEW_STATE", + "16#00000002#" "NOT_NEW_VIEW_STATE", + "16#FFFFFFFF#" "ANY_VIEW_STATE", + -default binary +} +radix define INSTANCE_STATE { + "16#00000001#" "ALIVE_INSTANCE_STATE", + "16#00000002#" "NOT_ALIVE_DISPOSED_INSTANCE_STATE", + "16#00000004#" "NOT_ALIVE_NO_WRITERS_INSTANCE_STATE", + "16#FFFFFFFF#" "ANY_INSTANCE_STATE", + -default binary +} +radix define LAST_REASON { + "16#00000000#" "NOT_REJECTED", + "16#00000001#" "REJECTED_BY_INSTANCES_LIMIT", + "16#00000002#" "REJECTED_BY_SAMPLES_LIMIT", + "16#00000003#" "REJECTED_BY_SAMPLES_PER_INSTANCE_LIMIT", + "16#000000FF#" "REJECTED_BY_PAYOAD_MEMORY_LIMIT", + -default binary +} +quietly WaveActivateNextPane {} 0 +add wave -noupdate -divider SYSTEM +add wave -noupdate /l0_dds_reader_test2/uut/clk +add wave -noupdate /l0_dds_reader_test2/uut/reset +add wave -noupdate -radix unsigned /l0_dds_reader_test2/uut/time +add wave -noupdate -divider RTPS +add wave -noupdate -group RTPS /l0_dds_reader_test2/uut/start_rtps +add wave -noupdate -group RTPS /l0_dds_reader_test2/uut/opcode_rtps +add wave -noupdate -group RTPS /l0_dds_reader_test2/uut/ack_rtps +add wave -noupdate -group RTPS /l0_dds_reader_test2/uut/ret_rtps +add wave -noupdate -group RTPS /l0_dds_reader_test2/uut/done_rtps +add wave -noupdate -group RTPS /l0_dds_reader_test2/uut/ready_in_rtps +add wave -noupdate -group RTPS /l0_dds_reader_test2/uut/valid_in_rtps +add wave -noupdate -group RTPS -radix hexadecimal /l0_dds_reader_test2/uut/data_in_rtps +add wave -noupdate -group RTPS /l0_dds_reader_test2/uut/last_word_in_rtps +add wave -noupdate -divider DDS +add wave -noupdate -group DDS /l0_dds_reader_test2/uut/start_dds +add wave -noupdate -group DDS /l0_dds_reader_test2/uut/ack_dds +add wave -noupdate -group DDS /l0_dds_reader_test2/uut/opcode_dds +add wave -noupdate -group DDS -radix SAMPLE_STATE /l0_dds_reader_test2/uut/sample_state_dds +add wave -noupdate -group DDS -radix INSTANCE_STATE /l0_dds_reader_test2/uut/instance_state_dds +add wave -noupdate -group DDS -radix VIEW_STATE /l0_dds_reader_test2/uut/view_state_dds +add wave -noupdate -group DDS -radix hexadecimal /l0_dds_reader_test2/uut/instance_handle_dds +add wave -noupdate -group DDS -radix unsigned /l0_dds_reader_test2/uut/max_samples_dds +add wave -noupdate -group DDS -radix DDS_RETCODE -childformat {{/l0_dds_reader_test2/uut/return_code_dds(0) -radix DDS_RETCODE} {/l0_dds_reader_test2/uut/return_code_dds(1) -radix DDS_RETCODE} {/l0_dds_reader_test2/uut/return_code_dds(2) -radix DDS_RETCODE} {/l0_dds_reader_test2/uut/return_code_dds(3) -radix DDS_RETCODE} {/l0_dds_reader_test2/uut/return_code_dds(4) -radix DDS_RETCODE} {/l0_dds_reader_test2/uut/return_code_dds(5) -radix DDS_RETCODE}} -subitemconfig {/l0_dds_reader_test2/uut/return_code_dds(0) {-height 15 -radix DDS_RETCODE} /l0_dds_reader_test2/uut/return_code_dds(1) {-height 15 -radix DDS_RETCODE} /l0_dds_reader_test2/uut/return_code_dds(2) {-height 15 -radix DDS_RETCODE} /l0_dds_reader_test2/uut/return_code_dds(3) {-height 15 -radix DDS_RETCODE} /l0_dds_reader_test2/uut/return_code_dds(4) {-height 15 -radix DDS_RETCODE} /l0_dds_reader_test2/uut/return_code_dds(5) {-height 15 -radix DDS_RETCODE}} /l0_dds_reader_test2/uut/return_code_dds +add wave -noupdate -group DDS /l0_dds_reader_test2/uut/done_dds +add wave -noupdate -group DDS -divider SI +add wave -noupdate -group DDS -radix hexadecimal -childformat {{/l0_dds_reader_test2/uut/sample_info(0) -radix hexadecimal -childformat {{/l0_dds_reader_test2/uut/sample_info(0).sample_state -radix hexadecimal} {/l0_dds_reader_test2/uut/sample_info(0).view_state -radix hexadecimal} {/l0_dds_reader_test2/uut/sample_info(0).instance_state -radix hexadecimal} {/l0_dds_reader_test2/uut/sample_info(0).source_timestamp -radix hexadecimal} {/l0_dds_reader_test2/uut/sample_info(0).instance_handle -radix hexadecimal} {/l0_dds_reader_test2/uut/sample_info(0).publication_handle -radix hexadecimal} {/l0_dds_reader_test2/uut/sample_info(0).disposed_generation_count -radix hexadecimal} {/l0_dds_reader_test2/uut/sample_info(0).no_writers_generation_count -radix hexadecimal} {/l0_dds_reader_test2/uut/sample_info(0).sample_rank -radix hexadecimal} {/l0_dds_reader_test2/uut/sample_info(0).generation_rank -radix hexadecimal} {/l0_dds_reader_test2/uut/sample_info(0).absolute_generation_rank -radix hexadecimal} {/l0_dds_reader_test2/uut/sample_info(0).valid_data -radix hexadecimal}}} {/l0_dds_reader_test2/uut/sample_info(1) -radix hexadecimal} {/l0_dds_reader_test2/uut/sample_info(2) -radix hexadecimal} {/l0_dds_reader_test2/uut/sample_info(3) -radix hexadecimal} {/l0_dds_reader_test2/uut/sample_info(4) -radix hexadecimal} {/l0_dds_reader_test2/uut/sample_info(5) -radix hexadecimal}} -subitemconfig {/l0_dds_reader_test2/uut/sample_info(0) {-height 15 -radix hexadecimal -childformat {{/l0_dds_reader_test2/uut/sample_info(0).sample_state -radix hexadecimal} {/l0_dds_reader_test2/uut/sample_info(0).view_state -radix hexadecimal} {/l0_dds_reader_test2/uut/sample_info(0).instance_state -radix hexadecimal} {/l0_dds_reader_test2/uut/sample_info(0).source_timestamp -radix hexadecimal} {/l0_dds_reader_test2/uut/sample_info(0).instance_handle -radix hexadecimal} {/l0_dds_reader_test2/uut/sample_info(0).publication_handle -radix hexadecimal} {/l0_dds_reader_test2/uut/sample_info(0).disposed_generation_count -radix hexadecimal} {/l0_dds_reader_test2/uut/sample_info(0).no_writers_generation_count -radix hexadecimal} {/l0_dds_reader_test2/uut/sample_info(0).sample_rank -radix hexadecimal} {/l0_dds_reader_test2/uut/sample_info(0).generation_rank -radix hexadecimal} {/l0_dds_reader_test2/uut/sample_info(0).absolute_generation_rank -radix hexadecimal} {/l0_dds_reader_test2/uut/sample_info(0).valid_data -radix hexadecimal}}} /l0_dds_reader_test2/uut/sample_info(0).sample_state {-height 15 -radix hexadecimal} /l0_dds_reader_test2/uut/sample_info(0).view_state {-height 15 -radix hexadecimal} /l0_dds_reader_test2/uut/sample_info(0).instance_state {-height 15 -radix hexadecimal} /l0_dds_reader_test2/uut/sample_info(0).source_timestamp {-height 15 -radix hexadecimal} /l0_dds_reader_test2/uut/sample_info(0).instance_handle {-height 15 -radix hexadecimal} /l0_dds_reader_test2/uut/sample_info(0).publication_handle {-height 15 -radix hexadecimal} /l0_dds_reader_test2/uut/sample_info(0).disposed_generation_count {-height 15 -radix hexadecimal} /l0_dds_reader_test2/uut/sample_info(0).no_writers_generation_count {-height 15 -radix hexadecimal} /l0_dds_reader_test2/uut/sample_info(0).sample_rank {-height 15 -radix hexadecimal} /l0_dds_reader_test2/uut/sample_info(0).generation_rank {-height 15 -radix hexadecimal} /l0_dds_reader_test2/uut/sample_info(0).absolute_generation_rank {-height 15 -radix hexadecimal} /l0_dds_reader_test2/uut/sample_info(0).valid_data {-height 15 -radix hexadecimal} /l0_dds_reader_test2/uut/sample_info(1) {-height 15 -radix hexadecimal} /l0_dds_reader_test2/uut/sample_info(2) {-height 15 -radix hexadecimal} /l0_dds_reader_test2/uut/sample_info(3) {-height 15 -radix hexadecimal} /l0_dds_reader_test2/uut/sample_info(4) {-height 15 -radix hexadecimal} /l0_dds_reader_test2/uut/sample_info(5) {-height 15 -radix hexadecimal}} /l0_dds_reader_test2/uut/sample_info +add wave -noupdate -group DDS /l0_dds_reader_test2/uut/sample_info_valid +add wave -noupdate -group DDS /l0_dds_reader_test2/uut/sample_info_ack +add wave -noupdate -group DDS /l0_dds_reader_test2/uut/eoc +add wave -noupdate -group DDS /l0_dds_reader_test2/uut/get_data_dds +add wave -noupdate -group DDS -divider OUTPUT +add wave -noupdate -group DDS /l0_dds_reader_test2/uut/ready_out_dds +add wave -noupdate -group DDS /l0_dds_reader_test2/uut/valid_out_dds +add wave -noupdate -group DDS -radix hexadecimal /l0_dds_reader_test2/uut/data_out_dds +add wave -noupdate -group DDS /l0_dds_reader_test2/uut/last_word_out_dds +add wave -noupdate -divider {MAIN FSM} +add wave -noupdate /l0_dds_reader_test2/uut/stage +add wave -noupdate /l0_dds_reader_test2/uut/cnt +add wave -noupdate /l0_dds_reader_test2/uut/ind +add wave -noupdate -divider MEMORY +add wave -noupdate /l0_dds_reader_test2/uut/inst_op_start +add wave -noupdate /l0_dds_reader_test2/uut/inst_opcode +add wave -noupdate /l0_dds_reader_test2/uut/inst_op_done +add wave -noupdate /l0_dds_reader_test2/uut/inst_stage +add wave -noupdate /l0_dds_reader_test2/uut/inst_cnt +add wave -noupdate -radix unsigned /l0_dds_reader_test2/uut/inst_addr_base +add wave -noupdate -childformat {{/l0_dds_reader_test2/uut/inst_data.addr -radix unsigned} {/l0_dds_reader_test2/uut/inst_data.key_hash -radix hexadecimal} {/l0_dds_reader_test2/uut/inst_data.status_info -radix binary} {/l0_dds_reader_test2/uut/inst_data.sample_cnt -radix unsigned} {/l0_dds_reader_test2/uut/inst_data.disposed_gen_cnt -radix unsigned} {/l0_dds_reader_test2/uut/inst_data.no_writers_gen_cnt -radix unsigned} {/l0_dds_reader_test2/uut/inst_data.ignore_deadline -radix unsigned} {/l0_dds_reader_test2/uut/inst_data.writer_bitmap -radix binary -childformat {{/l0_dds_reader_test2/uut/inst_data.writer_bitmap(0) -radix binary -childformat {{/l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(0) -radix binary} {/l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(1) -radix binary} {/l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(2) -radix binary} {/l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(3) -radix binary} {/l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(4) -radix binary} {/l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(5) -radix binary} {/l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(6) -radix binary} {/l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(7) -radix binary} {/l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(8) -radix binary} {/l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(9) -radix binary} {/l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(10) -radix binary} {/l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(11) -radix binary} {/l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(12) -radix binary} {/l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(13) -radix binary} {/l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(14) -radix binary} {/l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(15) -radix binary} {/l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(16) -radix binary} {/l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(17) -radix binary} {/l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(18) -radix binary} {/l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(19) -radix binary} {/l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(20) -radix binary} {/l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(21) -radix binary} {/l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(22) -radix binary} {/l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(23) -radix binary} {/l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(24) -radix binary} {/l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(25) -radix binary} {/l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(26) -radix binary} {/l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(27) -radix binary} {/l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(28) -radix binary} {/l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(29) -radix binary} {/l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(30) -radix binary} {/l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(31) -radix binary}}}}}} -expand -subitemconfig {/l0_dds_reader_test2/uut/inst_data.addr {-radix unsigned} /l0_dds_reader_test2/uut/inst_data.key_hash {-height 15 -radix hexadecimal} /l0_dds_reader_test2/uut/inst_data.status_info {-height 15 -radix binary} /l0_dds_reader_test2/uut/inst_data.sample_cnt {-height 15 -radix unsigned} /l0_dds_reader_test2/uut/inst_data.disposed_gen_cnt {-height 15 -radix unsigned} /l0_dds_reader_test2/uut/inst_data.no_writers_gen_cnt {-height 15 -radix unsigned} /l0_dds_reader_test2/uut/inst_data.ignore_deadline {-height 15 -radix unsigned} /l0_dds_reader_test2/uut/inst_data.writer_bitmap {-height 15 -radix binary -childformat {{/l0_dds_reader_test2/uut/inst_data.writer_bitmap(0) -radix binary -childformat {{/l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(0) -radix binary} {/l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(1) -radix binary} {/l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(2) -radix binary} {/l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(3) -radix binary} {/l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(4) -radix binary} {/l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(5) -radix binary} {/l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(6) -radix binary} {/l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(7) -radix binary} {/l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(8) -radix binary} {/l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(9) -radix binary} {/l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(10) -radix binary} {/l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(11) -radix binary} {/l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(12) -radix binary} {/l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(13) -radix binary} {/l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(14) -radix binary} {/l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(15) -radix binary} {/l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(16) -radix binary} {/l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(17) -radix binary} {/l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(18) -radix binary} {/l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(19) -radix binary} {/l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(20) -radix binary} {/l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(21) -radix binary} {/l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(22) -radix binary} {/l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(23) -radix binary} {/l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(24) -radix binary} {/l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(25) -radix binary} {/l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(26) -radix binary} {/l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(27) -radix binary} {/l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(28) -radix binary} {/l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(29) -radix binary} {/l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(30) -radix binary} {/l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(31) -radix binary}}}}} /l0_dds_reader_test2/uut/inst_data.writer_bitmap(0) {-height 15 -radix binary -childformat {{/l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(0) -radix binary} {/l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(1) -radix binary} {/l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(2) -radix binary} {/l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(3) -radix binary} {/l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(4) -radix binary} {/l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(5) -radix binary} {/l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(6) -radix binary} {/l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(7) -radix binary} {/l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(8) -radix binary} {/l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(9) -radix binary} {/l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(10) -radix binary} {/l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(11) -radix binary} {/l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(12) -radix binary} {/l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(13) -radix binary} {/l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(14) -radix binary} {/l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(15) -radix binary} {/l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(16) -radix binary} {/l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(17) -radix binary} {/l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(18) -radix binary} {/l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(19) -radix binary} {/l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(20) -radix binary} {/l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(21) -radix binary} {/l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(22) -radix binary} {/l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(23) -radix binary} {/l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(24) -radix binary} {/l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(25) -radix binary} {/l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(26) -radix binary} {/l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(27) -radix binary} {/l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(28) -radix binary} {/l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(29) -radix binary} {/l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(30) -radix binary} {/l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(31) -radix binary}}} /l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(0) {-height 15 -radix binary} /l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(1) {-height 15 -radix binary} /l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(2) {-height 15 -radix binary} /l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(3) {-height 15 -radix binary} /l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(4) {-height 15 -radix binary} /l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(5) {-height 15 -radix binary} /l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(6) {-height 15 -radix binary} /l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(7) {-height 15 -radix binary} /l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(8) {-height 15 -radix binary} /l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(9) {-height 15 -radix binary} /l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(10) {-height 15 -radix binary} /l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(11) {-height 15 -radix binary} /l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(12) {-height 15 -radix binary} /l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(13) {-height 15 -radix binary} /l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(14) {-height 15 -radix binary} /l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(15) {-height 15 -radix binary} /l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(16) {-height 15 -radix binary} /l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(17) {-height 15 -radix binary} /l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(18) {-height 15 -radix binary} /l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(19) {-height 15 -radix binary} /l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(20) {-height 15 -radix binary} /l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(21) {-height 15 -radix binary} /l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(22) {-height 15 -radix binary} /l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(23) {-height 15 -radix binary} /l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(24) {-height 15 -radix binary} /l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(25) {-height 15 -radix binary} /l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(26) {-height 15 -radix binary} /l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(27) {-height 15 -radix binary} /l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(28) {-height 15 -radix binary} /l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(29) {-height 15 -radix binary} /l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(30) {-height 15 -radix binary} /l0_dds_reader_test2/uut/inst_data.writer_bitmap(0)(31) {-height 15 -radix binary}} /l0_dds_reader_test2/uut/inst_data +add wave -noupdate /l0_dds_reader_test2/uut/stale_inst_cnt +add wave -noupdate -group {SAMPLE MEM} -radix unsigned /l0_dds_reader_test2/uut/sample_addr +add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test2/uut/sample_read +add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test2/uut/sample_ready_in +add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test2/uut/sample_valid_in +add wave -noupdate -group {SAMPLE MEM} -radix hexadecimal /l0_dds_reader_test2/uut/sample_write_data +add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test2/uut/sample_ready_out +add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test2/uut/sample_valid_out +add wave -noupdate -group {SAMPLE MEM} -radix hexadecimal /l0_dds_reader_test2/uut/sample_read_data +add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test2/uut/sample_abort_read +add wave -noupdate -group {PAYLOAD MEM} -radix unsigned /l0_dds_reader_test2/uut/payload_addr +add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test2/uut/payload_read +add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test2/uut/payload_ready_in +add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test2/uut/payload_valid_in +add wave -noupdate -group {PAYLOAD MEM} -radix hexadecimal /l0_dds_reader_test2/uut/payload_write_data +add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test2/uut/payload_ready_out +add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test2/uut/payload_valid_out +add wave -noupdate -group {PAYLOAD MEM} -radix hexadecimal /l0_dds_reader_test2/uut/payload_read_data +add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test2/uut/payload_abort_read +add wave -noupdate -group {INSTANCE MEM} -radix unsigned /l0_dds_reader_test2/uut/inst_addr +add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test2/uut/inst_read +add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test2/uut/inst_ready_in +add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test2/uut/inst_valid_in +add wave -noupdate -group {INSTANCE MEM} -radix hexadecimal /l0_dds_reader_test2/uut/inst_write_data +add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test2/uut/inst_ready_out +add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test2/uut/inst_valid_out +add wave -noupdate -group {INSTANCE MEM} -radix hexadecimal /l0_dds_reader_test2/uut/inst_read_data +add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test2/uut/inst_abort_read +add wave -noupdate -divider POINTERS +add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test2/uut/empty_sample_list_head +add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test2/uut/empty_sample_list_tail +add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test2/uut/empty_payload_list_head +add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test2/uut/oldest_sample +add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test2/uut/newest_sample +add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test2/uut/inst_empty_head +add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test2/uut/inst_occupied_head +add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test2/uut/cur_sample +add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test2/uut/next_sample +add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test2/uut/prev_sample +add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test2/uut/cur_payload +add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test2/uut/next_payload +add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test2/uut/cur_inst +add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test2/uut/next_inst +add wave -noupdate -divider MISC +add wave -noupdate /l0_dds_reader_test2/uut/trigger_sample_gen +add wave -noupdate /l0_dds_reader_test2/uut/wait_for_sample_removal +add wave -noupdate -radix unsigned /l0_dds_reader_test2/uut/sample_p1 +add wave -noupdate -radix unsigned /l0_dds_reader_test2/uut/sample_p2 +add wave -noupdate -radix unsigned /l0_dds_reader_test2/uut/collection_cnt +add wave -noupdate -radix unsigned /l0_dds_reader_test2/uut/collection_cnt_max +add wave -noupdate -radix unsigned /l0_dds_reader_test2/uut/collection_generation_rank +add wave -noupdate -radix unsigned /l0_dds_reader_test2/uut/cur_generation_rank +add wave -noupdate -radix unsigned -childformat {{/l0_dds_reader_test2/uut/max_samples_latch(31) -radix unsigned} {/l0_dds_reader_test2/uut/max_samples_latch(30) -radix unsigned} {/l0_dds_reader_test2/uut/max_samples_latch(29) -radix unsigned} {/l0_dds_reader_test2/uut/max_samples_latch(28) -radix unsigned} {/l0_dds_reader_test2/uut/max_samples_latch(27) -radix unsigned} {/l0_dds_reader_test2/uut/max_samples_latch(26) -radix unsigned} {/l0_dds_reader_test2/uut/max_samples_latch(25) -radix unsigned} {/l0_dds_reader_test2/uut/max_samples_latch(24) -radix unsigned} {/l0_dds_reader_test2/uut/max_samples_latch(23) -radix unsigned} {/l0_dds_reader_test2/uut/max_samples_latch(22) -radix unsigned} {/l0_dds_reader_test2/uut/max_samples_latch(21) -radix unsigned} {/l0_dds_reader_test2/uut/max_samples_latch(20) -radix unsigned} {/l0_dds_reader_test2/uut/max_samples_latch(19) -radix unsigned} {/l0_dds_reader_test2/uut/max_samples_latch(18) -radix unsigned} {/l0_dds_reader_test2/uut/max_samples_latch(17) -radix unsigned} {/l0_dds_reader_test2/uut/max_samples_latch(16) -radix unsigned} {/l0_dds_reader_test2/uut/max_samples_latch(15) -radix unsigned} {/l0_dds_reader_test2/uut/max_samples_latch(14) -radix unsigned} {/l0_dds_reader_test2/uut/max_samples_latch(13) -radix unsigned} {/l0_dds_reader_test2/uut/max_samples_latch(12) -radix unsigned} {/l0_dds_reader_test2/uut/max_samples_latch(11) -radix unsigned} {/l0_dds_reader_test2/uut/max_samples_latch(10) -radix unsigned} {/l0_dds_reader_test2/uut/max_samples_latch(9) -radix unsigned} {/l0_dds_reader_test2/uut/max_samples_latch(8) -radix unsigned} {/l0_dds_reader_test2/uut/max_samples_latch(7) -radix unsigned} {/l0_dds_reader_test2/uut/max_samples_latch(6) -radix unsigned} {/l0_dds_reader_test2/uut/max_samples_latch(5) -radix unsigned} {/l0_dds_reader_test2/uut/max_samples_latch(4) -radix unsigned} {/l0_dds_reader_test2/uut/max_samples_latch(3) -radix unsigned} {/l0_dds_reader_test2/uut/max_samples_latch(2) -radix unsigned} {/l0_dds_reader_test2/uut/max_samples_latch(1) -radix unsigned} {/l0_dds_reader_test2/uut/max_samples_latch(0) -radix unsigned}} -subitemconfig {/l0_dds_reader_test2/uut/max_samples_latch(31) {-height 15 -radix unsigned} /l0_dds_reader_test2/uut/max_samples_latch(30) {-height 15 -radix unsigned} /l0_dds_reader_test2/uut/max_samples_latch(29) {-height 15 -radix unsigned} /l0_dds_reader_test2/uut/max_samples_latch(28) {-height 15 -radix unsigned} /l0_dds_reader_test2/uut/max_samples_latch(27) {-height 15 -radix unsigned} /l0_dds_reader_test2/uut/max_samples_latch(26) {-height 15 -radix unsigned} /l0_dds_reader_test2/uut/max_samples_latch(25) {-height 15 -radix unsigned} /l0_dds_reader_test2/uut/max_samples_latch(24) {-height 15 -radix unsigned} /l0_dds_reader_test2/uut/max_samples_latch(23) {-height 15 -radix unsigned} /l0_dds_reader_test2/uut/max_samples_latch(22) {-height 15 -radix unsigned} /l0_dds_reader_test2/uut/max_samples_latch(21) {-height 15 -radix unsigned} /l0_dds_reader_test2/uut/max_samples_latch(20) {-height 15 -radix unsigned} /l0_dds_reader_test2/uut/max_samples_latch(19) {-height 15 -radix unsigned} /l0_dds_reader_test2/uut/max_samples_latch(18) {-height 15 -radix unsigned} /l0_dds_reader_test2/uut/max_samples_latch(17) {-height 15 -radix unsigned} /l0_dds_reader_test2/uut/max_samples_latch(16) {-height 15 -radix unsigned} /l0_dds_reader_test2/uut/max_samples_latch(15) {-height 15 -radix unsigned} /l0_dds_reader_test2/uut/max_samples_latch(14) {-height 15 -radix unsigned} /l0_dds_reader_test2/uut/max_samples_latch(13) {-height 15 -radix unsigned} /l0_dds_reader_test2/uut/max_samples_latch(12) {-height 15 -radix unsigned} /l0_dds_reader_test2/uut/max_samples_latch(11) {-height 15 -radix unsigned} /l0_dds_reader_test2/uut/max_samples_latch(10) {-height 15 -radix unsigned} /l0_dds_reader_test2/uut/max_samples_latch(9) {-height 15 -radix unsigned} /l0_dds_reader_test2/uut/max_samples_latch(8) {-height 15 -radix unsigned} /l0_dds_reader_test2/uut/max_samples_latch(7) {-height 15 -radix unsigned} /l0_dds_reader_test2/uut/max_samples_latch(6) {-height 15 -radix unsigned} /l0_dds_reader_test2/uut/max_samples_latch(5) {-height 15 -radix unsigned} /l0_dds_reader_test2/uut/max_samples_latch(4) {-height 15 -radix unsigned} /l0_dds_reader_test2/uut/max_samples_latch(3) {-height 15 -radix unsigned} /l0_dds_reader_test2/uut/max_samples_latch(2) {-height 15 -radix unsigned} /l0_dds_reader_test2/uut/max_samples_latch(1) {-height 15 -radix unsigned} /l0_dds_reader_test2/uut/max_samples_latch(0) {-height 15 -radix unsigned}} /l0_dds_reader_test2/uut/max_samples_latch +add wave -noupdate /l0_dds_reader_test2/uut/single_instance +add wave -noupdate /l0_dds_reader_test2/uut/is_take +add wave -noupdate -radix unsigned -childformat {{/l0_dds_reader_test2/uut/sample_rej_last_reason(0) -radix LAST_REASON} {/l0_dds_reader_test2/uut/sample_rej_last_reason(1) -radix LAST_REASON} {/l0_dds_reader_test2/uut/sample_rej_last_reason(2) -radix LAST_REASON} {/l0_dds_reader_test2/uut/sample_rej_last_reason(3) -radix LAST_REASON} {/l0_dds_reader_test2/uut/sample_rej_last_reason(4) -radix LAST_REASON} {/l0_dds_reader_test2/uut/sample_rej_last_reason(5) -radix LAST_REASON}} -subitemconfig {/l0_dds_reader_test2/uut/sample_rej_last_reason(0) {-radix LAST_REASON} /l0_dds_reader_test2/uut/sample_rej_last_reason(1) {-radix LAST_REASON} /l0_dds_reader_test2/uut/sample_rej_last_reason(2) {-radix LAST_REASON} /l0_dds_reader_test2/uut/sample_rej_last_reason(3) {-radix LAST_REASON} /l0_dds_reader_test2/uut/sample_rej_last_reason(4) {-radix LAST_REASON} /l0_dds_reader_test2/uut/sample_rej_last_reason(5) {-radix LAST_REASON}} /l0_dds_reader_test2/uut/sample_rej_last_reason +add wave -noupdate -divider TESTBENCH +add wave -noupdate -group TESTBENCH /l0_dds_reader_test2/dds_start +add wave -noupdate -group TESTBENCH /l0_dds_reader_test2/dds_stage +add wave -noupdate -group TESTBENCH /l0_dds_reader_test2/dds_cnt +add wave -noupdate -group TESTBENCH /l0_dds_reader_test2/dds_cnt2 +add wave -noupdate -group TESTBENCH /l0_dds_reader_test2/dds_done +add wave -noupdate -group TESTBENCH /l0_dds_reader_test2/rtps_start +add wave -noupdate -group TESTBENCH /l0_dds_reader_test2/rtps_stage +add wave -noupdate -group TESTBENCH /l0_dds_reader_test2/rtps_cnt +add wave -noupdate -group TESTBENCH /l0_dds_reader_test2/rtps_done +add wave -noupdate -divider {KEY HOLDER} +add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test2/uut/start_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test2/uut/opcode_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test2/uut/ack_kh +add wave -noupdate -group {KEY HOLDER} -radix hexadecimal /l0_dds_reader_test2/uut/data_in_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test2/uut/valid_in_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test2/uut/ready_in_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test2/uut/last_word_in_kh +add wave -noupdate -group {KEY HOLDER} -radix hexadecimal /l0_dds_reader_test2/uut/data_out_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test2/uut/valid_out_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test2/uut/ready_out_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test2/uut/last_word_out_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test2/uut/abort_kh +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {50639746 ps} 0} +quietly wave cursor active 1 +configure wave -namecolwidth 187 +configure wave -valuecolwidth 206 +configure wave -justifyvalue left +configure wave -signalnamewidth 1 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ns +update +WaveRestoreZoom {50034942 ps} {50968663 ps} diff --git a/sim/L0_dds_reader_test2_arpkriu.do b/sim/L0_dds_reader_test2_arpkriu.do deleted file mode 100644 index a353931..0000000 --- a/sim/L0_dds_reader_test2_arpkriu.do +++ /dev/null @@ -1,195 +0,0 @@ -onerror {resume} -radix define DDS_RETCODE { - "10#0#" "RETCODE_OK", - "10#1#" "RETCODE_ERROR", - "10#2#" "RETCODE_UNSUPPORTED", - "10#3#" "RETCODE_BAD_PARAMETER", - "10#4#" "RETCODE_PRECONDITION_NOT_MET", - "10#5#" "RETCODE_OUT_OF_RESOURCES", - "10#6#" "RETCODE_NOT_ENABLED", - "10#7#" "RETCODE_IMMUTABLE_POLICY", - "10#8#" "RETCODE_INCONSISTENT_POLICY", - "10#9#" "RETCODE_ALREADY_DELETED", - "10#10#" "RETCODE_TIMEOUT", - "10#11#" "RETCODE_NO_DATA", - "10#12#" "RETCODE_ILLEGAL_OPERATION", - -default unsigned -} -radix define SAMPLE_STATE { - "16#00000001#" "READ_SAMPLE_STATE", - "16#00000002#" "NOT_READ_SAMPLE_STATE", - "16#FFFFFFFF#" "ANY_SAMPLE_STATE", - -default binary -} -radix define VIEW_STATE { - "16#00000001#" "NEW_VIEW_STATE", - "16#00000002#" "NOT_NEW_VIEW_STATE", - "16#FFFFFFFF#" "ANY_VIEW_STATE", - -default binary -} -radix define INSTANCE_STATE { - "16#00000001#" "ALIVE_INSTANCE_STATE", - "16#00000002#" "NOT_ALIVE_DISPOSED_INSTANCE_STATE", - "16#00000004#" "NOT_ALIVE_NO_WRITERS_INSTANCE_STATE", - "16#FFFFFFFF#" "ANY_INSTANCE_STATE", - -default binary -} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -divider SYSTEM -add wave -noupdate /l0_dds_reader_test2_arpkriu/uut/clk -add wave -noupdate /l0_dds_reader_test2_arpkriu/uut/reset -add wave -noupdate -radix unsigned /l0_dds_reader_test2_arpkriu/uut/time -add wave -noupdate -divider RTPS -add wave -noupdate -expand -group RTPS /l0_dds_reader_test2_arpkriu/uut/start_rtps -add wave -noupdate -expand -group RTPS /l0_dds_reader_test2_arpkriu/uut/opcode_rtps -add wave -noupdate -expand -group RTPS /l0_dds_reader_test2_arpkriu/uut/ack_rtps -add wave -noupdate -expand -group RTPS /l0_dds_reader_test2_arpkriu/uut/ret_rtps -add wave -noupdate -expand -group RTPS /l0_dds_reader_test2_arpkriu/uut/done_rtps -add wave -noupdate -expand -group RTPS /l0_dds_reader_test2_arpkriu/uut/ready_in_rtps -add wave -noupdate -expand -group RTPS /l0_dds_reader_test2_arpkriu/uut/valid_in_rtps -add wave -noupdate -expand -group RTPS -radix hexadecimal /l0_dds_reader_test2_arpkriu/uut/data_in_rtps -add wave -noupdate -expand -group RTPS /l0_dds_reader_test2_arpkriu/uut/last_word_in_rtps -add wave -noupdate -divider DDS -add wave -noupdate -group DDS /l0_dds_reader_test2_arpkriu/uut/start_dds -add wave -noupdate -group DDS /l0_dds_reader_test2_arpkriu/uut/ack_dds -add wave -noupdate -group DDS /l0_dds_reader_test2_arpkriu/uut/opcode_dds -add wave -noupdate -group DDS -radix SAMPLE_STATE /l0_dds_reader_test2_arpkriu/uut/sample_state_dds -add wave -noupdate -group DDS -radix INSTANCE_STATE /l0_dds_reader_test2_arpkriu/uut/instance_state_dds -add wave -noupdate -group DDS -radix VIEW_STATE /l0_dds_reader_test2_arpkriu/uut/view_state_dds -add wave -noupdate -group DDS -radix hexadecimal /l0_dds_reader_test2_arpkriu/uut/instance_handle_dds -add wave -noupdate -group DDS -radix unsigned /l0_dds_reader_test2_arpkriu/uut/max_samples_dds -add wave -noupdate -group DDS -radix DDS_RETCODE /l0_dds_reader_test2_arpkriu/uut/return_code_dds -add wave -noupdate -group DDS /l0_dds_reader_test2_arpkriu/uut/done_dds -add wave -noupdate -group DDS -divider SI -add wave -noupdate -group DDS -radix SAMPLE_STATE /l0_dds_reader_test2_arpkriu/uut/si_sample_state -add wave -noupdate -group DDS -radix VIEW_STATE /l0_dds_reader_test2_arpkriu/uut/si_view_state -add wave -noupdate -group DDS -radix INSTANCE_STATE /l0_dds_reader_test2_arpkriu/uut/si_instance_state -add wave -noupdate -group DDS -radix unsigned /l0_dds_reader_test2_arpkriu/uut/si_source_timestamp -add wave -noupdate -group DDS -radix hexadecimal /l0_dds_reader_test2_arpkriu/uut/si_instance_handle -add wave -noupdate -group DDS -radix hexadecimal /l0_dds_reader_test2_arpkriu/uut/si_publication_handle -add wave -noupdate -group DDS -radix unsigned /l0_dds_reader_test2_arpkriu/uut/si_disposed_generation_count -add wave -noupdate -group DDS -radix unsigned /l0_dds_reader_test2_arpkriu/uut/si_no_writers_generation_count -add wave -noupdate -group DDS -radix unsigned /l0_dds_reader_test2_arpkriu/uut/si_sample_rank -add wave -noupdate -group DDS -radix unsigned /l0_dds_reader_test2_arpkriu/uut/si_generation_rank -add wave -noupdate -group DDS -radix unsigned /l0_dds_reader_test2_arpkriu/uut/si_absolute_generation_rank -add wave -noupdate -group DDS /l0_dds_reader_test2_arpkriu/uut/si_valid_data -add wave -noupdate -group DDS /l0_dds_reader_test2_arpkriu/uut/si_valid -add wave -noupdate -group DDS /l0_dds_reader_test2_arpkriu/uut/si_last -add wave -noupdate -group DDS /l0_dds_reader_test2_arpkriu/uut/get_data_dds -add wave -noupdate -group DDS -divider OUTPUT -add wave -noupdate -group DDS /l0_dds_reader_test2_arpkriu/uut/ready_out_dds -add wave -noupdate -group DDS /l0_dds_reader_test2_arpkriu/uut/valid_out_dds -add wave -noupdate -group DDS -radix hexadecimal /l0_dds_reader_test2_arpkriu/uut/data_out_dds -add wave -noupdate -group DDS /l0_dds_reader_test2_arpkriu/uut/last_word_out_dds -add wave -noupdate -divider {MAIN FSM} -add wave -noupdate /l0_dds_reader_test2_arpkriu/uut/stage -add wave -noupdate /l0_dds_reader_test2_arpkriu/uut/stage_next -add wave -noupdate /l0_dds_reader_test2_arpkriu/uut/cnt -add wave -noupdate -divider MEMORY -add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test2_arpkriu/uut/sample_abort_read -add wave -noupdate -group {SAMPLE MEM} -radix unsigned /l0_dds_reader_test2_arpkriu/uut/sample_mem_ctrl_inst/addr -add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test2_arpkriu/uut/sample_mem_ctrl_inst/read -add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test2_arpkriu/uut/sample_mem_ctrl_inst/ready_in -add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test2_arpkriu/uut/sample_mem_ctrl_inst/valid_in -add wave -noupdate -group {SAMPLE MEM} -radix hexadecimal /l0_dds_reader_test2_arpkriu/uut/sample_mem_ctrl_inst/data_in -add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test2_arpkriu/uut/sample_mem_ctrl_inst/ready_out -add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test2_arpkriu/uut/sample_mem_ctrl_inst/valid_out -add wave -noupdate -group {SAMPLE MEM} -radix hexadecimal /l0_dds_reader_test2_arpkriu/uut/sample_mem_ctrl_inst/data_out -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test2_arpkriu/uut/payload_abort_read -add wave -noupdate -group {PAYLOAD MEM} -radix unsigned /l0_dds_reader_test2_arpkriu/uut/payload_mem_ctrl_inst/addr -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test2_arpkriu/uut/payload_mem_ctrl_inst/read -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test2_arpkriu/uut/payload_mem_ctrl_inst/ready_in -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test2_arpkriu/uut/payload_mem_ctrl_inst/valid_in -add wave -noupdate -group {PAYLOAD MEM} -radix hexadecimal /l0_dds_reader_test2_arpkriu/uut/payload_mem_ctrl_inst/data_in -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test2_arpkriu/uut/payload_mem_ctrl_inst/ready_out -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test2_arpkriu/uut/payload_mem_ctrl_inst/valid_out -add wave -noupdate -group {PAYLOAD MEM} -radix hexadecimal /l0_dds_reader_test2_arpkriu/uut/payload_mem_ctrl_inst/data_out -add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test2_arpkriu/uut/inst_abort_read -add wave -noupdate -group {INSTANCE MEM} -radix unsigned /l0_dds_reader_test2_arpkriu/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/addr -add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test2_arpkriu/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/read -add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test2_arpkriu/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/ready_in -add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test2_arpkriu/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/valid_in -add wave -noupdate -group {INSTANCE MEM} -radix hexadecimal /l0_dds_reader_test2_arpkriu/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/data_in -add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test2_arpkriu/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/ready_out -add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test2_arpkriu/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/valid_out -add wave -noupdate -group {INSTANCE MEM} -radix hexadecimal /l0_dds_reader_test2_arpkriu/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/data_out -add wave -noupdate /l0_dds_reader_test2_arpkriu/uut/inst_op_start -add wave -noupdate /l0_dds_reader_test2_arpkriu/uut/inst_opcode -add wave -noupdate /l0_dds_reader_test2_arpkriu/uut/inst_op_done -add wave -noupdate /l0_dds_reader_test2_arpkriu/uut/inst_stage -add wave -noupdate /l0_dds_reader_test2_arpkriu/uut/inst_stage_next -add wave -noupdate /l0_dds_reader_test2_arpkriu/uut/inst_cnt -add wave -noupdate -radix unsigned /l0_dds_reader_test2_arpkriu/uut/inst_addr_base -add wave -noupdate /l0_dds_reader_test2_arpkriu/uut/inst_mem_fields -add wave -noupdate -childformat {{/l0_dds_reader_test2_arpkriu/uut/inst_data.key_hash -radix hexadecimal} {/l0_dds_reader_test2_arpkriu/uut/inst_data.status_info -radix binary} {/l0_dds_reader_test2_arpkriu/uut/inst_data.sample_cnt -radix unsigned} {/l0_dds_reader_test2_arpkriu/uut/inst_data.disposed_gen_cnt -radix unsigned} {/l0_dds_reader_test2_arpkriu/uut/inst_data.no_writers_gen_cnt -radix unsigned} {/l0_dds_reader_test2_arpkriu/uut/inst_data.ignore_deadline -radix unsigned} {/l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap -radix binary -childformat {{/l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0) -radix binary -childformat {{/l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(0) -radix binary} {/l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(1) -radix binary} {/l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(2) -radix binary} {/l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(3) -radix binary} {/l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(4) -radix binary} {/l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(5) -radix binary} {/l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(6) -radix binary} {/l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(7) -radix binary} {/l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(8) -radix binary} {/l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(9) -radix binary} {/l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(10) -radix binary} {/l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(11) -radix binary} {/l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(12) -radix binary} {/l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(13) -radix binary} {/l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(14) -radix binary} {/l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(15) -radix binary} {/l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(16) -radix binary} {/l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(17) -radix binary} {/l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(18) -radix binary} {/l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(19) -radix binary} {/l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(20) -radix binary} {/l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(21) -radix binary} {/l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(22) -radix binary} {/l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(23) -radix binary} {/l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(24) -radix binary} {/l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(25) -radix binary} {/l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(26) -radix binary} {/l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(27) -radix binary} {/l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(28) -radix binary} {/l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(29) -radix binary} {/l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(30) -radix binary} {/l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(31) -radix binary}}}}}} -subitemconfig {/l0_dds_reader_test2_arpkriu/uut/inst_data.key_hash {-height 15 -radix hexadecimal} /l0_dds_reader_test2_arpkriu/uut/inst_data.status_info {-height 15 -radix binary} /l0_dds_reader_test2_arpkriu/uut/inst_data.sample_cnt {-height 15 -radix unsigned} /l0_dds_reader_test2_arpkriu/uut/inst_data.disposed_gen_cnt {-height 15 -radix unsigned} /l0_dds_reader_test2_arpkriu/uut/inst_data.no_writers_gen_cnt {-height 15 -radix unsigned} /l0_dds_reader_test2_arpkriu/uut/inst_data.ignore_deadline {-height 15 -radix unsigned} /l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap {-height 15 -radix binary -childformat {{/l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0) -radix binary -childformat {{/l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(0) -radix binary} {/l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(1) -radix binary} {/l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(2) -radix binary} {/l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(3) -radix binary} {/l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(4) -radix binary} {/l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(5) -radix binary} {/l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(6) -radix binary} {/l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(7) -radix binary} {/l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(8) -radix binary} {/l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(9) -radix binary} {/l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(10) -radix binary} {/l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(11) -radix binary} {/l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(12) -radix binary} {/l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(13) -radix binary} {/l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(14) -radix binary} {/l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(15) -radix binary} {/l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(16) -radix binary} {/l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(17) -radix binary} {/l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(18) -radix binary} {/l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(19) -radix binary} {/l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(20) -radix binary} {/l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(21) -radix binary} {/l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(22) -radix binary} {/l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(23) -radix binary} {/l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(24) -radix binary} {/l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(25) -radix binary} {/l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(26) -radix binary} {/l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(27) -radix binary} {/l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(28) -radix binary} {/l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(29) -radix binary} {/l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(30) -radix binary} {/l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(31) -radix binary}}}}} /l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0) {-height 15 -radix binary -childformat {{/l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(0) -radix binary} {/l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(1) -radix binary} {/l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(2) -radix binary} {/l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(3) -radix binary} {/l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(4) -radix binary} {/l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(5) -radix binary} {/l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(6) -radix binary} {/l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(7) -radix binary} {/l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(8) -radix binary} {/l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(9) -radix binary} {/l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(10) -radix binary} {/l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(11) -radix binary} {/l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(12) -radix binary} {/l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(13) -radix binary} {/l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(14) -radix binary} {/l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(15) -radix binary} {/l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(16) -radix binary} {/l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(17) -radix binary} {/l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(18) -radix binary} {/l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(19) -radix binary} {/l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(20) -radix binary} {/l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(21) -radix binary} {/l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(22) -radix binary} {/l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(23) -radix binary} {/l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(24) -radix binary} {/l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(25) -radix binary} {/l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(26) -radix binary} {/l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(27) -radix binary} {/l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(28) -radix binary} {/l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(29) -radix binary} {/l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(30) -radix binary} {/l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(31) -radix binary}}} /l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(0) {-height 15 -radix binary} /l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(1) {-height 15 -radix binary} /l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(2) {-height 15 -radix binary} /l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(3) {-height 15 -radix binary} /l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(4) {-height 15 -radix binary} /l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(5) {-height 15 -radix binary} /l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(6) {-height 15 -radix binary} /l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(7) {-height 15 -radix binary} /l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(8) {-height 15 -radix binary} /l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(9) {-height 15 -radix binary} /l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(10) {-height 15 -radix binary} /l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(11) {-height 15 -radix binary} /l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(12) {-height 15 -radix binary} /l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(13) {-height 15 -radix binary} /l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(14) {-height 15 -radix binary} /l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(15) {-height 15 -radix binary} /l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(16) {-height 15 -radix binary} /l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(17) {-height 15 -radix binary} /l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(18) {-height 15 -radix binary} /l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(19) {-height 15 -radix binary} /l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(20) {-height 15 -radix binary} /l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(21) {-height 15 -radix binary} /l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(22) {-height 15 -radix binary} /l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(23) {-height 15 -radix binary} /l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(24) {-height 15 -radix binary} /l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(25) {-height 15 -radix binary} /l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(26) {-height 15 -radix binary} /l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(27) {-height 15 -radix binary} /l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(28) {-height 15 -radix binary} /l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(29) {-height 15 -radix binary} /l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(30) {-height 15 -radix binary} /l0_dds_reader_test2_arpkriu/uut/inst_data.writer_bitmap(0)(31) {-height 15 -radix binary}} /l0_dds_reader_test2_arpkriu/uut/inst_data -add wave -noupdate -radix unsigned /l0_dds_reader_test2_arpkriu/uut/inst_next_addr_base -add wave -noupdate -radix unsigned /l0_dds_reader_test2_arpkriu/uut/inst_prev_addr_base -add wave -noupdate /l0_dds_reader_test2_arpkriu/uut/current_imf -add wave -noupdate /l0_dds_reader_test2_arpkriu/uut/stale_inst_cnt -add wave -noupdate -divider POINTERS -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test2_arpkriu/uut/empty_sample_list_head -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test2_arpkriu/uut/empty_sample_list_tail -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test2_arpkriu/uut/empty_payload_list_head -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test2_arpkriu/uut/oldest_sample -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test2_arpkriu/uut/newest_sample -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test2_arpkriu/uut/inst_empty_head -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test2_arpkriu/uut/inst_occupied_head -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test2_arpkriu/uut/cur_sample -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test2_arpkriu/uut/next_sample -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test2_arpkriu/uut/prev_sample -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test2_arpkriu/uut/cur_payload -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test2_arpkriu/uut/next_payload -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test2_arpkriu/uut/cur_inst -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test2_arpkriu/uut/next_inst -add wave -noupdate -divider TESTBENCH -add wave -noupdate -group TESTBENCH /l0_dds_reader_test2_arpkriu/dds_start -add wave -noupdate -group TESTBENCH /l0_dds_reader_test2_arpkriu/dds_stage -add wave -noupdate -group TESTBENCH /l0_dds_reader_test2_arpkriu/dds_cnt -add wave -noupdate -group TESTBENCH /l0_dds_reader_test2_arpkriu/dds_cnt2 -add wave -noupdate -group TESTBENCH /l0_dds_reader_test2_arpkriu/dds_done -add wave -noupdate -group TESTBENCH /l0_dds_reader_test2_arpkriu/rtps_start -add wave -noupdate -group TESTBENCH /l0_dds_reader_test2_arpkriu/rtps_stage -add wave -noupdate -group TESTBENCH /l0_dds_reader_test2_arpkriu/rtps_cnt -add wave -noupdate -group TESTBENCH /l0_dds_reader_test2_arpkriu/rtps_done -add wave -noupdate -divider {KEY HOLDER} -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test2_arpkriu/uut/start_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test2_arpkriu/uut/opcode_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test2_arpkriu/uut/ack_kh -add wave -noupdate -group {KEY HOLDER} -radix hexadecimal /l0_dds_reader_test2_arpkriu/uut/data_in_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test2_arpkriu/uut/valid_in_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test2_arpkriu/uut/ready_in_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test2_arpkriu/uut/last_word_in_kh -add wave -noupdate -group {KEY HOLDER} -radix hexadecimal /l0_dds_reader_test2_arpkriu/uut/data_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test2_arpkriu/uut/valid_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test2_arpkriu/uut/ready_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test2_arpkriu/uut/last_word_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test2_arpkriu/uut/abort_kh -add wave -noupdate -divider MISC -add wave -noupdate -radix unsigned /l0_dds_reader_test2_arpkriu/uut/collection_cnt -add wave -noupdate -radix unsigned /l0_dds_reader_test2_arpkriu/uut/collection_cnt_max -add wave -noupdate -radix unsigned /l0_dds_reader_test2_arpkriu/uut/collection_generation_rank -add wave -noupdate -radix unsigned /l0_dds_reader_test2_arpkriu/uut/cur_generation_rank -add wave -noupdate -radix unsigned /l0_dds_reader_test2_arpkriu/uut/max_samples_latch -add wave -noupdate /l0_dds_reader_test2_arpkriu/uut/single_instance -add wave -noupdate /l0_dds_reader_test2_arpkriu/uut/is_take -add wave -noupdate -radix unsigned /l0_dds_reader_test2_arpkriu/uut/sel_sample -add wave -noupdate -radix unsigned /l0_dds_reader_test2_arpkriu/uut/sample_p1 -add wave -noupdate -radix unsigned /l0_dds_reader_test2_arpkriu/uut/sample_p2 -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {13448960 ps} 0} {{Cursor 2} {115175000 ps} 1} -quietly wave cursor active 1 -configure wave -namecolwidth 187 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -configure wave -timelineunits ns -update -WaveRestoreZoom {13008299 ps} {14008940 ps} diff --git a/sim/L0_dds_reader_test3.do b/sim/L0_dds_reader_test3.do new file mode 100644 index 0000000..6ce4eee --- /dev/null +++ b/sim/L0_dds_reader_test3.do @@ -0,0 +1,190 @@ +onerror {resume} +radix define DDS_RETCODE { + "10#0#" "RETCODE_OK", + "10#1#" "RETCODE_ERROR", + "10#2#" "RETCODE_UNSUPPORTED", + "10#3#" "RETCODE_BAD_PARAMETER", + "10#4#" "RETCODE_PRECONDITION_NOT_MET", + "10#5#" "RETCODE_OUT_OF_RESOURCES", + "10#6#" "RETCODE_NOT_ENABLED", + "10#7#" "RETCODE_IMMUTABLE_POLICY", + "10#8#" "RETCODE_INCONSISTENT_POLICY", + "10#9#" "RETCODE_ALREADY_DELETED", + "10#10#" "RETCODE_TIMEOUT", + "10#11#" "RETCODE_NO_DATA", + "10#12#" "RETCODE_ILLEGAL_OPERATION", + -default unsigned +} +radix define SAMPLE_STATE { + "16#00000001#" "READ_SAMPLE_STATE", + "16#00000002#" "NOT_READ_SAMPLE_STATE", + "16#FFFFFFFF#" "ANY_SAMPLE_STATE", + -default binary +} +radix define VIEW_STATE { + "16#00000001#" "NEW_VIEW_STATE", + "16#00000002#" "NOT_NEW_VIEW_STATE", + "16#FFFFFFFF#" "ANY_VIEW_STATE", + -default binary +} +radix define INSTANCE_STATE { + "16#00000001#" "ALIVE_INSTANCE_STATE", + "16#00000002#" "NOT_ALIVE_DISPOSED_INSTANCE_STATE", + "16#00000004#" "NOT_ALIVE_NO_WRITERS_INSTANCE_STATE", + "16#FFFFFFFF#" "ANY_INSTANCE_STATE", + -default binary +} +radix define LAST_REASON { + "16#00000000#" "NOT_REJECTED", + "16#00000001#" "REJECTED_BY_INSTANCES_LIMIT", + "16#00000002#" "REJECTED_BY_SAMPLES_LIMIT", + "16#00000003#" "REJECTED_BY_SAMPLES_PER_INSTANCE_LIMIT", + "16#000000FF#" "REJECTED_BY_PAYOAD_MEMORY_LIMIT", + -default binary +} +quietly WaveActivateNextPane {} 0 +add wave -noupdate -divider SYSTEM +add wave -noupdate /l0_dds_reader_test3/uut/clk +add wave -noupdate /l0_dds_reader_test3/uut/reset +add wave -noupdate -radix unsigned /l0_dds_reader_test3/uut/time +add wave -noupdate -divider RTPS +add wave -noupdate -group RTPS /l0_dds_reader_test3/uut/start_rtps +add wave -noupdate -group RTPS /l0_dds_reader_test3/uut/opcode_rtps +add wave -noupdate -group RTPS /l0_dds_reader_test3/uut/ack_rtps +add wave -noupdate -group RTPS /l0_dds_reader_test3/uut/ret_rtps +add wave -noupdate -group RTPS /l0_dds_reader_test3/uut/done_rtps +add wave -noupdate -group RTPS /l0_dds_reader_test3/uut/ready_in_rtps +add wave -noupdate -group RTPS /l0_dds_reader_test3/uut/valid_in_rtps +add wave -noupdate -group RTPS -radix hexadecimal /l0_dds_reader_test3/uut/data_in_rtps +add wave -noupdate -group RTPS /l0_dds_reader_test3/uut/last_word_in_rtps +add wave -noupdate -divider DDS +add wave -noupdate -group DDS /l0_dds_reader_test3/uut/start_dds +add wave -noupdate -group DDS /l0_dds_reader_test3/uut/ack_dds +add wave -noupdate -group DDS /l0_dds_reader_test3/uut/opcode_dds +add wave -noupdate -group DDS -radix SAMPLE_STATE /l0_dds_reader_test3/uut/sample_state_dds +add wave -noupdate -group DDS -radix INSTANCE_STATE /l0_dds_reader_test3/uut/instance_state_dds +add wave -noupdate -group DDS -radix VIEW_STATE /l0_dds_reader_test3/uut/view_state_dds +add wave -noupdate -group DDS -radix hexadecimal /l0_dds_reader_test3/uut/instance_handle_dds +add wave -noupdate -group DDS -radix unsigned /l0_dds_reader_test3/uut/max_samples_dds +add wave -noupdate -group DDS -radix DDS_RETCODE -childformat {{/l0_dds_reader_test3/uut/return_code_dds(0) -radix DDS_RETCODE} {/l0_dds_reader_test3/uut/return_code_dds(1) -radix DDS_RETCODE} {/l0_dds_reader_test3/uut/return_code_dds(2) -radix DDS_RETCODE} {/l0_dds_reader_test3/uut/return_code_dds(3) -radix DDS_RETCODE} {/l0_dds_reader_test3/uut/return_code_dds(4) -radix DDS_RETCODE} {/l0_dds_reader_test3/uut/return_code_dds(5) -radix DDS_RETCODE}} -subitemconfig {/l0_dds_reader_test3/uut/return_code_dds(0) {-height 15 -radix DDS_RETCODE} /l0_dds_reader_test3/uut/return_code_dds(1) {-height 15 -radix DDS_RETCODE} /l0_dds_reader_test3/uut/return_code_dds(2) {-height 15 -radix DDS_RETCODE} /l0_dds_reader_test3/uut/return_code_dds(3) {-height 15 -radix DDS_RETCODE} /l0_dds_reader_test3/uut/return_code_dds(4) {-height 15 -radix DDS_RETCODE} /l0_dds_reader_test3/uut/return_code_dds(5) {-height 15 -radix DDS_RETCODE}} /l0_dds_reader_test3/uut/return_code_dds +add wave -noupdate -group DDS /l0_dds_reader_test3/uut/done_dds +add wave -noupdate -group DDS -divider SI +add wave -noupdate -group DDS -radix hexadecimal -childformat {{/l0_dds_reader_test3/uut/sample_info(0) -radix hexadecimal -childformat {{/l0_dds_reader_test3/uut/sample_info(0).sample_state -radix hexadecimal} {/l0_dds_reader_test3/uut/sample_info(0).view_state -radix hexadecimal} {/l0_dds_reader_test3/uut/sample_info(0).instance_state -radix hexadecimal} {/l0_dds_reader_test3/uut/sample_info(0).source_timestamp -radix hexadecimal} {/l0_dds_reader_test3/uut/sample_info(0).instance_handle -radix hexadecimal} {/l0_dds_reader_test3/uut/sample_info(0).publication_handle -radix hexadecimal} {/l0_dds_reader_test3/uut/sample_info(0).disposed_generation_count -radix hexadecimal} {/l0_dds_reader_test3/uut/sample_info(0).no_writers_generation_count -radix hexadecimal} {/l0_dds_reader_test3/uut/sample_info(0).sample_rank -radix hexadecimal} {/l0_dds_reader_test3/uut/sample_info(0).generation_rank -radix hexadecimal} {/l0_dds_reader_test3/uut/sample_info(0).absolute_generation_rank -radix hexadecimal} {/l0_dds_reader_test3/uut/sample_info(0).valid_data -radix hexadecimal}}} {/l0_dds_reader_test3/uut/sample_info(1) -radix hexadecimal} {/l0_dds_reader_test3/uut/sample_info(2) -radix hexadecimal} {/l0_dds_reader_test3/uut/sample_info(3) -radix hexadecimal} {/l0_dds_reader_test3/uut/sample_info(4) -radix hexadecimal} {/l0_dds_reader_test3/uut/sample_info(5) -radix hexadecimal}} -subitemconfig {/l0_dds_reader_test3/uut/sample_info(0) {-height 15 -radix hexadecimal -childformat {{/l0_dds_reader_test3/uut/sample_info(0).sample_state -radix hexadecimal} {/l0_dds_reader_test3/uut/sample_info(0).view_state -radix hexadecimal} {/l0_dds_reader_test3/uut/sample_info(0).instance_state -radix hexadecimal} {/l0_dds_reader_test3/uut/sample_info(0).source_timestamp -radix hexadecimal} {/l0_dds_reader_test3/uut/sample_info(0).instance_handle -radix hexadecimal} {/l0_dds_reader_test3/uut/sample_info(0).publication_handle -radix hexadecimal} {/l0_dds_reader_test3/uut/sample_info(0).disposed_generation_count -radix hexadecimal} {/l0_dds_reader_test3/uut/sample_info(0).no_writers_generation_count -radix hexadecimal} {/l0_dds_reader_test3/uut/sample_info(0).sample_rank -radix hexadecimal} {/l0_dds_reader_test3/uut/sample_info(0).generation_rank -radix hexadecimal} {/l0_dds_reader_test3/uut/sample_info(0).absolute_generation_rank -radix hexadecimal} {/l0_dds_reader_test3/uut/sample_info(0).valid_data -radix hexadecimal}}} /l0_dds_reader_test3/uut/sample_info(0).sample_state {-height 15 -radix hexadecimal} /l0_dds_reader_test3/uut/sample_info(0).view_state {-height 15 -radix hexadecimal} /l0_dds_reader_test3/uut/sample_info(0).instance_state {-height 15 -radix hexadecimal} /l0_dds_reader_test3/uut/sample_info(0).source_timestamp {-height 15 -radix hexadecimal} /l0_dds_reader_test3/uut/sample_info(0).instance_handle {-height 15 -radix hexadecimal} /l0_dds_reader_test3/uut/sample_info(0).publication_handle {-height 15 -radix hexadecimal} /l0_dds_reader_test3/uut/sample_info(0).disposed_generation_count {-height 15 -radix hexadecimal} /l0_dds_reader_test3/uut/sample_info(0).no_writers_generation_count {-height 15 -radix hexadecimal} /l0_dds_reader_test3/uut/sample_info(0).sample_rank {-height 15 -radix hexadecimal} /l0_dds_reader_test3/uut/sample_info(0).generation_rank {-height 15 -radix hexadecimal} /l0_dds_reader_test3/uut/sample_info(0).absolute_generation_rank {-height 15 -radix hexadecimal} /l0_dds_reader_test3/uut/sample_info(0).valid_data {-height 15 -radix hexadecimal} /l0_dds_reader_test3/uut/sample_info(1) {-height 15 -radix hexadecimal} /l0_dds_reader_test3/uut/sample_info(2) {-height 15 -radix hexadecimal} /l0_dds_reader_test3/uut/sample_info(3) {-height 15 -radix hexadecimal} /l0_dds_reader_test3/uut/sample_info(4) {-height 15 -radix hexadecimal} /l0_dds_reader_test3/uut/sample_info(5) {-height 15 -radix hexadecimal}} /l0_dds_reader_test3/uut/sample_info +add wave -noupdate -group DDS /l0_dds_reader_test3/uut/sample_info_valid +add wave -noupdate -group DDS /l0_dds_reader_test3/uut/sample_info_ack +add wave -noupdate -group DDS /l0_dds_reader_test3/uut/eoc +add wave -noupdate -group DDS /l0_dds_reader_test3/uut/get_data_dds +add wave -noupdate -group DDS -divider OUTPUT +add wave -noupdate -group DDS /l0_dds_reader_test3/uut/ready_out_dds +add wave -noupdate -group DDS /l0_dds_reader_test3/uut/valid_out_dds +add wave -noupdate -group DDS -radix hexadecimal /l0_dds_reader_test3/uut/data_out_dds +add wave -noupdate -group DDS /l0_dds_reader_test3/uut/last_word_out_dds +add wave -noupdate -divider {MAIN FSM} +add wave -noupdate /l0_dds_reader_test3/uut/stage +add wave -noupdate /l0_dds_reader_test3/uut/cnt +add wave -noupdate /l0_dds_reader_test3/uut/ind +add wave -noupdate -divider MEMORY +add wave -noupdate /l0_dds_reader_test3/uut/inst_op_start +add wave -noupdate /l0_dds_reader_test3/uut/inst_opcode +add wave -noupdate /l0_dds_reader_test3/uut/inst_op_done +add wave -noupdate /l0_dds_reader_test3/uut/inst_stage +add wave -noupdate /l0_dds_reader_test3/uut/inst_cnt +add wave -noupdate -radix unsigned /l0_dds_reader_test3/uut/inst_addr_base +add wave -noupdate -childformat {{/l0_dds_reader_test3/uut/inst_data.addr -radix unsigned} {/l0_dds_reader_test3/uut/inst_data.key_hash -radix hexadecimal} {/l0_dds_reader_test3/uut/inst_data.status_info -radix binary} {/l0_dds_reader_test3/uut/inst_data.sample_cnt -radix unsigned} {/l0_dds_reader_test3/uut/inst_data.disposed_gen_cnt -radix unsigned} {/l0_dds_reader_test3/uut/inst_data.no_writers_gen_cnt -radix unsigned} {/l0_dds_reader_test3/uut/inst_data.ignore_deadline -radix unsigned} {/l0_dds_reader_test3/uut/inst_data.writer_bitmap -radix binary -childformat {{/l0_dds_reader_test3/uut/inst_data.writer_bitmap(0) -radix binary -childformat {{/l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(0) -radix binary} {/l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(1) -radix binary} {/l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(2) -radix binary} {/l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(3) -radix binary} {/l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(4) -radix binary} {/l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(5) -radix binary} {/l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(6) -radix binary} {/l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(7) -radix binary} {/l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(8) -radix binary} {/l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(9) -radix binary} {/l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(10) -radix binary} {/l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(11) -radix binary} {/l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(12) -radix binary} {/l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(13) -radix binary} {/l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(14) -radix binary} {/l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(15) -radix binary} {/l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(16) -radix binary} {/l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(17) -radix binary} {/l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(18) -radix binary} {/l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(19) -radix binary} {/l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(20) -radix binary} {/l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(21) -radix binary} {/l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(22) -radix binary} {/l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(23) -radix binary} {/l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(24) -radix binary} {/l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(25) -radix binary} {/l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(26) -radix binary} {/l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(27) -radix binary} {/l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(28) -radix binary} {/l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(29) -radix binary} {/l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(30) -radix binary} {/l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(31) -radix binary}}}}}} -expand -subitemconfig {/l0_dds_reader_test3/uut/inst_data.addr {-radix unsigned} /l0_dds_reader_test3/uut/inst_data.key_hash {-height 15 -radix hexadecimal} /l0_dds_reader_test3/uut/inst_data.status_info {-height 15 -radix binary} /l0_dds_reader_test3/uut/inst_data.sample_cnt {-height 15 -radix unsigned} /l0_dds_reader_test3/uut/inst_data.disposed_gen_cnt {-height 15 -radix unsigned} /l0_dds_reader_test3/uut/inst_data.no_writers_gen_cnt {-height 15 -radix unsigned} /l0_dds_reader_test3/uut/inst_data.ignore_deadline {-height 15 -radix unsigned} /l0_dds_reader_test3/uut/inst_data.writer_bitmap {-height 15 -radix binary -childformat {{/l0_dds_reader_test3/uut/inst_data.writer_bitmap(0) -radix binary -childformat {{/l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(0) -radix binary} {/l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(1) -radix binary} {/l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(2) -radix binary} {/l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(3) -radix binary} {/l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(4) -radix binary} {/l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(5) -radix binary} {/l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(6) -radix binary} {/l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(7) -radix binary} {/l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(8) -radix binary} {/l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(9) -radix binary} {/l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(10) -radix binary} {/l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(11) -radix binary} {/l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(12) -radix binary} {/l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(13) -radix binary} {/l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(14) -radix binary} {/l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(15) -radix binary} {/l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(16) -radix binary} {/l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(17) -radix binary} {/l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(18) -radix binary} {/l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(19) -radix binary} {/l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(20) -radix binary} {/l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(21) -radix binary} {/l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(22) -radix binary} {/l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(23) -radix binary} {/l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(24) -radix binary} {/l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(25) -radix binary} {/l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(26) -radix binary} {/l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(27) -radix binary} {/l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(28) -radix binary} {/l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(29) -radix binary} {/l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(30) -radix binary} {/l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(31) -radix binary}}}}} /l0_dds_reader_test3/uut/inst_data.writer_bitmap(0) {-height 15 -radix binary -childformat {{/l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(0) -radix binary} {/l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(1) -radix binary} {/l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(2) -radix binary} {/l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(3) -radix binary} {/l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(4) -radix binary} {/l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(5) -radix binary} {/l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(6) -radix binary} {/l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(7) -radix binary} {/l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(8) -radix binary} {/l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(9) -radix binary} {/l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(10) -radix binary} {/l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(11) -radix binary} {/l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(12) -radix binary} {/l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(13) -radix binary} {/l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(14) -radix binary} {/l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(15) -radix binary} {/l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(16) -radix binary} {/l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(17) -radix binary} {/l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(18) -radix binary} {/l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(19) -radix binary} {/l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(20) -radix binary} {/l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(21) -radix binary} {/l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(22) -radix binary} {/l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(23) -radix binary} {/l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(24) -radix binary} {/l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(25) -radix binary} {/l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(26) -radix binary} {/l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(27) -radix binary} {/l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(28) -radix binary} {/l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(29) -radix binary} {/l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(30) -radix binary} {/l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(31) -radix binary}}} /l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(0) {-height 15 -radix binary} /l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(1) {-height 15 -radix binary} /l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(2) {-height 15 -radix binary} /l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(3) {-height 15 -radix binary} /l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(4) {-height 15 -radix binary} /l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(5) {-height 15 -radix binary} /l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(6) {-height 15 -radix binary} /l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(7) {-height 15 -radix binary} /l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(8) {-height 15 -radix binary} /l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(9) {-height 15 -radix binary} /l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(10) {-height 15 -radix binary} /l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(11) {-height 15 -radix binary} /l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(12) {-height 15 -radix binary} /l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(13) {-height 15 -radix binary} /l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(14) {-height 15 -radix binary} /l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(15) {-height 15 -radix binary} /l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(16) {-height 15 -radix binary} /l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(17) {-height 15 -radix binary} /l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(18) {-height 15 -radix binary} /l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(19) {-height 15 -radix binary} /l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(20) {-height 15 -radix binary} /l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(21) {-height 15 -radix binary} /l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(22) {-height 15 -radix binary} /l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(23) {-height 15 -radix binary} /l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(24) {-height 15 -radix binary} /l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(25) {-height 15 -radix binary} /l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(26) {-height 15 -radix binary} /l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(27) {-height 15 -radix binary} /l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(28) {-height 15 -radix binary} /l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(29) {-height 15 -radix binary} /l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(30) {-height 15 -radix binary} /l0_dds_reader_test3/uut/inst_data.writer_bitmap(0)(31) {-height 15 -radix binary}} /l0_dds_reader_test3/uut/inst_data +add wave -noupdate /l0_dds_reader_test3/uut/stale_inst_cnt +add wave -noupdate -group {SAMPLE MEM} -radix unsigned /l0_dds_reader_test3/uut/sample_addr +add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test3/uut/sample_read +add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test3/uut/sample_ready_in +add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test3/uut/sample_valid_in +add wave -noupdate -group {SAMPLE MEM} -radix hexadecimal /l0_dds_reader_test3/uut/sample_write_data +add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test3/uut/sample_ready_out +add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test3/uut/sample_valid_out +add wave -noupdate -group {SAMPLE MEM} -radix hexadecimal /l0_dds_reader_test3/uut/sample_read_data +add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test3/uut/sample_abort_read +add wave -noupdate -group {PAYLOAD MEM} -radix unsigned /l0_dds_reader_test3/uut/payload_addr +add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test3/uut/payload_read +add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test3/uut/payload_ready_in +add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test3/uut/payload_valid_in +add wave -noupdate -group {PAYLOAD MEM} -radix hexadecimal /l0_dds_reader_test3/uut/payload_write_data +add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test3/uut/payload_ready_out +add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test3/uut/payload_valid_out +add wave -noupdate -group {PAYLOAD MEM} -radix hexadecimal /l0_dds_reader_test3/uut/payload_read_data +add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test3/uut/payload_abort_read +add wave -noupdate -group {INSTANCE MEM} -radix unsigned /l0_dds_reader_test3/uut/inst_addr +add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test3/uut/inst_read +add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test3/uut/inst_ready_in +add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test3/uut/inst_valid_in +add wave -noupdate -group {INSTANCE MEM} -radix hexadecimal /l0_dds_reader_test3/uut/inst_write_data +add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test3/uut/inst_ready_out +add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test3/uut/inst_valid_out +add wave -noupdate -group {INSTANCE MEM} -radix hexadecimal /l0_dds_reader_test3/uut/inst_read_data +add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test3/uut/inst_abort_read +add wave -noupdate -divider POINTERS +add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test3/uut/empty_sample_list_head +add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test3/uut/empty_sample_list_tail +add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test3/uut/empty_payload_list_head +add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test3/uut/oldest_sample +add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test3/uut/newest_sample +add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test3/uut/inst_empty_head +add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test3/uut/inst_occupied_head +add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test3/uut/cur_sample +add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test3/uut/next_sample +add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test3/uut/prev_sample +add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test3/uut/cur_payload +add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test3/uut/next_payload +add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test3/uut/cur_inst +add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test3/uut/next_inst +add wave -noupdate -divider MISC +add wave -noupdate /l0_dds_reader_test3/uut/trigger_sample_gen +add wave -noupdate /l0_dds_reader_test3/uut/wait_for_sample_removal +add wave -noupdate -radix unsigned /l0_dds_reader_test3/uut/sample_p1 +add wave -noupdate -radix unsigned /l0_dds_reader_test3/uut/sample_p2 +add wave -noupdate -radix unsigned /l0_dds_reader_test3/uut/collection_cnt +add wave -noupdate -radix unsigned /l0_dds_reader_test3/uut/collection_cnt_max +add wave -noupdate -radix unsigned /l0_dds_reader_test3/uut/collection_generation_rank +add wave -noupdate -radix unsigned /l0_dds_reader_test3/uut/cur_generation_rank +add wave -noupdate -radix unsigned -childformat {{/l0_dds_reader_test3/uut/max_samples_latch(31) -radix unsigned} {/l0_dds_reader_test3/uut/max_samples_latch(30) -radix unsigned} {/l0_dds_reader_test3/uut/max_samples_latch(29) -radix unsigned} {/l0_dds_reader_test3/uut/max_samples_latch(28) -radix unsigned} {/l0_dds_reader_test3/uut/max_samples_latch(27) -radix unsigned} {/l0_dds_reader_test3/uut/max_samples_latch(26) -radix unsigned} {/l0_dds_reader_test3/uut/max_samples_latch(25) -radix unsigned} {/l0_dds_reader_test3/uut/max_samples_latch(24) -radix unsigned} {/l0_dds_reader_test3/uut/max_samples_latch(23) -radix unsigned} {/l0_dds_reader_test3/uut/max_samples_latch(22) -radix unsigned} {/l0_dds_reader_test3/uut/max_samples_latch(21) -radix unsigned} {/l0_dds_reader_test3/uut/max_samples_latch(20) -radix unsigned} {/l0_dds_reader_test3/uut/max_samples_latch(19) -radix unsigned} {/l0_dds_reader_test3/uut/max_samples_latch(18) -radix unsigned} {/l0_dds_reader_test3/uut/max_samples_latch(17) -radix unsigned} {/l0_dds_reader_test3/uut/max_samples_latch(16) -radix unsigned} {/l0_dds_reader_test3/uut/max_samples_latch(15) -radix unsigned} {/l0_dds_reader_test3/uut/max_samples_latch(14) -radix unsigned} {/l0_dds_reader_test3/uut/max_samples_latch(13) -radix unsigned} {/l0_dds_reader_test3/uut/max_samples_latch(12) -radix unsigned} {/l0_dds_reader_test3/uut/max_samples_latch(11) -radix unsigned} {/l0_dds_reader_test3/uut/max_samples_latch(10) -radix unsigned} {/l0_dds_reader_test3/uut/max_samples_latch(9) -radix unsigned} {/l0_dds_reader_test3/uut/max_samples_latch(8) -radix unsigned} {/l0_dds_reader_test3/uut/max_samples_latch(7) -radix unsigned} {/l0_dds_reader_test3/uut/max_samples_latch(6) -radix unsigned} {/l0_dds_reader_test3/uut/max_samples_latch(5) -radix unsigned} {/l0_dds_reader_test3/uut/max_samples_latch(4) -radix unsigned} {/l0_dds_reader_test3/uut/max_samples_latch(3) -radix unsigned} {/l0_dds_reader_test3/uut/max_samples_latch(2) -radix unsigned} {/l0_dds_reader_test3/uut/max_samples_latch(1) -radix unsigned} {/l0_dds_reader_test3/uut/max_samples_latch(0) -radix unsigned}} -subitemconfig {/l0_dds_reader_test3/uut/max_samples_latch(31) {-height 15 -radix unsigned} /l0_dds_reader_test3/uut/max_samples_latch(30) {-height 15 -radix unsigned} /l0_dds_reader_test3/uut/max_samples_latch(29) {-height 15 -radix unsigned} /l0_dds_reader_test3/uut/max_samples_latch(28) {-height 15 -radix unsigned} /l0_dds_reader_test3/uut/max_samples_latch(27) {-height 15 -radix unsigned} /l0_dds_reader_test3/uut/max_samples_latch(26) {-height 15 -radix unsigned} /l0_dds_reader_test3/uut/max_samples_latch(25) {-height 15 -radix unsigned} /l0_dds_reader_test3/uut/max_samples_latch(24) {-height 15 -radix unsigned} /l0_dds_reader_test3/uut/max_samples_latch(23) {-height 15 -radix unsigned} /l0_dds_reader_test3/uut/max_samples_latch(22) {-height 15 -radix unsigned} /l0_dds_reader_test3/uut/max_samples_latch(21) {-height 15 -radix unsigned} /l0_dds_reader_test3/uut/max_samples_latch(20) {-height 15 -radix unsigned} /l0_dds_reader_test3/uut/max_samples_latch(19) {-height 15 -radix unsigned} /l0_dds_reader_test3/uut/max_samples_latch(18) {-height 15 -radix unsigned} /l0_dds_reader_test3/uut/max_samples_latch(17) {-height 15 -radix unsigned} /l0_dds_reader_test3/uut/max_samples_latch(16) {-height 15 -radix unsigned} /l0_dds_reader_test3/uut/max_samples_latch(15) {-height 15 -radix unsigned} /l0_dds_reader_test3/uut/max_samples_latch(14) {-height 15 -radix unsigned} /l0_dds_reader_test3/uut/max_samples_latch(13) {-height 15 -radix unsigned} /l0_dds_reader_test3/uut/max_samples_latch(12) {-height 15 -radix unsigned} /l0_dds_reader_test3/uut/max_samples_latch(11) {-height 15 -radix unsigned} /l0_dds_reader_test3/uut/max_samples_latch(10) {-height 15 -radix unsigned} /l0_dds_reader_test3/uut/max_samples_latch(9) {-height 15 -radix unsigned} /l0_dds_reader_test3/uut/max_samples_latch(8) {-height 15 -radix unsigned} /l0_dds_reader_test3/uut/max_samples_latch(7) {-height 15 -radix unsigned} /l0_dds_reader_test3/uut/max_samples_latch(6) {-height 15 -radix unsigned} /l0_dds_reader_test3/uut/max_samples_latch(5) {-height 15 -radix unsigned} /l0_dds_reader_test3/uut/max_samples_latch(4) {-height 15 -radix unsigned} /l0_dds_reader_test3/uut/max_samples_latch(3) {-height 15 -radix unsigned} /l0_dds_reader_test3/uut/max_samples_latch(2) {-height 15 -radix unsigned} /l0_dds_reader_test3/uut/max_samples_latch(1) {-height 15 -radix unsigned} /l0_dds_reader_test3/uut/max_samples_latch(0) {-height 15 -radix unsigned}} /l0_dds_reader_test3/uut/max_samples_latch +add wave -noupdate /l0_dds_reader_test3/uut/single_instance +add wave -noupdate /l0_dds_reader_test3/uut/is_take +add wave -noupdate -radix unsigned -childformat {{/l0_dds_reader_test3/uut/sample_rej_last_reason(0) -radix LAST_REASON} {/l0_dds_reader_test3/uut/sample_rej_last_reason(1) -radix LAST_REASON} {/l0_dds_reader_test3/uut/sample_rej_last_reason(2) -radix LAST_REASON} {/l0_dds_reader_test3/uut/sample_rej_last_reason(3) -radix LAST_REASON} {/l0_dds_reader_test3/uut/sample_rej_last_reason(4) -radix LAST_REASON} {/l0_dds_reader_test3/uut/sample_rej_last_reason(5) -radix LAST_REASON}} -subitemconfig {/l0_dds_reader_test3/uut/sample_rej_last_reason(0) {-radix LAST_REASON} /l0_dds_reader_test3/uut/sample_rej_last_reason(1) {-radix LAST_REASON} /l0_dds_reader_test3/uut/sample_rej_last_reason(2) {-radix LAST_REASON} /l0_dds_reader_test3/uut/sample_rej_last_reason(3) {-radix LAST_REASON} /l0_dds_reader_test3/uut/sample_rej_last_reason(4) {-radix LAST_REASON} /l0_dds_reader_test3/uut/sample_rej_last_reason(5) {-radix LAST_REASON}} /l0_dds_reader_test3/uut/sample_rej_last_reason +add wave -noupdate -divider TESTBENCH +add wave -noupdate -group TESTBENCH /l0_dds_reader_test3/dds_start +add wave -noupdate -group TESTBENCH /l0_dds_reader_test3/dds_stage +add wave -noupdate -group TESTBENCH /l0_dds_reader_test3/dds_cnt +add wave -noupdate -group TESTBENCH /l0_dds_reader_test3/dds_cnt2 +add wave -noupdate -group TESTBENCH /l0_dds_reader_test3/dds_done +add wave -noupdate -group TESTBENCH /l0_dds_reader_test3/rtps_start +add wave -noupdate -group TESTBENCH /l0_dds_reader_test3/rtps_stage +add wave -noupdate -group TESTBENCH /l0_dds_reader_test3/rtps_cnt +add wave -noupdate -group TESTBENCH /l0_dds_reader_test3/rtps_done +add wave -noupdate -divider {KEY HOLDER} +add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test3/uut/start_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test3/uut/opcode_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test3/uut/ack_kh +add wave -noupdate -group {KEY HOLDER} -radix hexadecimal /l0_dds_reader_test3/uut/data_in_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test3/uut/valid_in_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test3/uut/ready_in_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test3/uut/last_word_in_kh +add wave -noupdate -group {KEY HOLDER} -radix hexadecimal /l0_dds_reader_test3/uut/data_out_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test3/uut/valid_out_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test3/uut/ready_out_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test3/uut/last_word_out_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test3/uut/abort_kh +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {50639746 ps} 0} +quietly wave cursor active 1 +configure wave -namecolwidth 187 +configure wave -valuecolwidth 206 +configure wave -justifyvalue left +configure wave -signalnamewidth 1 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ns +update +WaveRestoreZoom {50034942 ps} {50968663 ps} diff --git a/sim/L0_dds_reader_test3_arzkrio.do b/sim/L0_dds_reader_test3_arzkrio.do deleted file mode 100644 index e37c700..0000000 --- a/sim/L0_dds_reader_test3_arzkrio.do +++ /dev/null @@ -1,199 +0,0 @@ -onerror {resume} -radix define DDS_RETCODE { - "10#0#" "RETCODE_OK", - "10#1#" "RETCODE_ERROR", - "10#2#" "RETCODE_UNSUPPORTED", - "10#3#" "RETCODE_BAD_PARAMETER", - "10#4#" "RETCODE_PRECONDITION_NOT_MET", - "10#5#" "RETCODE_OUT_OF_RESOURCES", - "10#6#" "RETCODE_NOT_ENABLED", - "10#7#" "RETCODE_IMMUTABLE_POLICY", - "10#8#" "RETCODE_INCONSISTENT_POLICY", - "10#9#" "RETCODE_ALREADY_DELETED", - "10#10#" "RETCODE_TIMEOUT", - "10#11#" "RETCODE_NO_DATA", - "10#12#" "RETCODE_ILLEGAL_OPERATION", - -default unsigned -} -radix define SAMPLE_STATE { - "16#00000001#" "READ_SAMPLE_STATE", - "16#00000002#" "NOT_READ_SAMPLE_STATE", - "16#FFFFFFFF#" "ANY_SAMPLE_STATE", - -default binary -} -radix define VIEW_STATE { - "16#00000001#" "NEW_VIEW_STATE", - "16#00000002#" "NOT_NEW_VIEW_STATE", - "16#FFFFFFFF#" "ANY_VIEW_STATE", - -default binary -} -radix define INSTANCE_STATE { - "16#00000001#" "ALIVE_INSTANCE_STATE", - "16#00000002#" "NOT_ALIVE_DISPOSED_INSTANCE_STATE", - "16#00000004#" "NOT_ALIVE_NO_WRITERS_INSTANCE_STATE", - "16#FFFFFFFF#" "ANY_INSTANCE_STATE", - -default binary -} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -divider SYSTEM -add wave -noupdate /l0_dds_reader_test3_arzkrio/uut/clk -add wave -noupdate /l0_dds_reader_test3_arzkrio/uut/reset -add wave -noupdate -radix unsigned /l0_dds_reader_test3_arzkrio/uut/time -add wave -noupdate -divider RTPS -add wave -noupdate -group RTPS /l0_dds_reader_test3_arzkrio/uut/start_rtps -add wave -noupdate -group RTPS /l0_dds_reader_test3_arzkrio/uut/opcode_rtps -add wave -noupdate -group RTPS /l0_dds_reader_test3_arzkrio/uut/ack_rtps -add wave -noupdate -group RTPS /l0_dds_reader_test3_arzkrio/uut/ret_rtps -add wave -noupdate -group RTPS /l0_dds_reader_test3_arzkrio/uut/done_rtps -add wave -noupdate -group RTPS /l0_dds_reader_test3_arzkrio/uut/ready_in_rtps -add wave -noupdate -group RTPS /l0_dds_reader_test3_arzkrio/uut/valid_in_rtps -add wave -noupdate -group RTPS -radix hexadecimal /l0_dds_reader_test3_arzkrio/uut/data_in_rtps -add wave -noupdate -group RTPS /l0_dds_reader_test3_arzkrio/uut/last_word_in_rtps -add wave -noupdate -divider DDS -add wave -noupdate -expand -group DDS /l0_dds_reader_test3_arzkrio/uut/start_dds -add wave -noupdate -expand -group DDS /l0_dds_reader_test3_arzkrio/uut/ack_dds -add wave -noupdate -expand -group DDS /l0_dds_reader_test3_arzkrio/uut/opcode_dds -add wave -noupdate -expand -group DDS -radix SAMPLE_STATE /l0_dds_reader_test3_arzkrio/uut/sample_state_dds -add wave -noupdate -expand -group DDS -radix INSTANCE_STATE /l0_dds_reader_test3_arzkrio/uut/instance_state_dds -add wave -noupdate -expand -group DDS -radix VIEW_STATE /l0_dds_reader_test3_arzkrio/uut/view_state_dds -add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_reader_test3_arzkrio/uut/instance_handle_dds -add wave -noupdate -expand -group DDS -radix unsigned /l0_dds_reader_test3_arzkrio/uut/max_samples_dds -add wave -noupdate -expand -group DDS -radix DDS_RETCODE /l0_dds_reader_test3_arzkrio/uut/return_code_dds -add wave -noupdate -expand -group DDS /l0_dds_reader_test3_arzkrio/uut/done_dds -add wave -noupdate -expand -group DDS -divider SI -add wave -noupdate -expand -group DDS -radix SAMPLE_STATE /l0_dds_reader_test3_arzkrio/uut/si_sample_state -add wave -noupdate -expand -group DDS -radix VIEW_STATE /l0_dds_reader_test3_arzkrio/uut/si_view_state -add wave -noupdate -expand -group DDS -radix INSTANCE_STATE /l0_dds_reader_test3_arzkrio/uut/si_instance_state -add wave -noupdate -expand -group DDS -radix unsigned /l0_dds_reader_test3_arzkrio/uut/si_source_timestamp -add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_reader_test3_arzkrio/uut/si_instance_handle -add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_reader_test3_arzkrio/uut/si_publication_handle -add wave -noupdate -expand -group DDS -radix unsigned /l0_dds_reader_test3_arzkrio/uut/si_disposed_generation_count -add wave -noupdate -expand -group DDS -radix unsigned /l0_dds_reader_test3_arzkrio/uut/si_no_writers_generation_count -add wave -noupdate -expand -group DDS -radix unsigned /l0_dds_reader_test3_arzkrio/uut/si_sample_rank -add wave -noupdate -expand -group DDS -radix unsigned /l0_dds_reader_test3_arzkrio/uut/si_generation_rank -add wave -noupdate -expand -group DDS -radix unsigned /l0_dds_reader_test3_arzkrio/uut/si_absolute_generation_rank -add wave -noupdate -expand -group DDS /l0_dds_reader_test3_arzkrio/uut/si_valid_data -add wave -noupdate -expand -group DDS /l0_dds_reader_test3_arzkrio/uut/si_valid -add wave -noupdate -expand -group DDS /l0_dds_reader_test3_arzkrio/uut/get_data_dds -add wave -noupdate -expand -group DDS /l0_dds_reader_test3_arzkrio/uut/eoc -add wave -noupdate -expand -group DDS -divider OUTPUT -add wave -noupdate -expand -group DDS /l0_dds_reader_test3_arzkrio/uut/ready_out_dds -add wave -noupdate -expand -group DDS /l0_dds_reader_test3_arzkrio/uut/valid_out_dds -add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_reader_test3_arzkrio/uut/data_out_dds -add wave -noupdate -expand -group DDS /l0_dds_reader_test3_arzkrio/uut/last_word_out_dds -add wave -noupdate -divider {MAIN FSM} -add wave -noupdate /l0_dds_reader_test3_arzkrio/uut/stage -add wave -noupdate /l0_dds_reader_test3_arzkrio/uut/stage_next -add wave -noupdate /l0_dds_reader_test3_arzkrio/uut/cnt -add wave -noupdate -divider MEMORY -add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test3_arzkrio/uut/sample_abort_read -add wave -noupdate -group {SAMPLE MEM} -radix unsigned /l0_dds_reader_test3_arzkrio/uut/sample_mem_ctrl_inst/addr -add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test3_arzkrio/uut/sample_mem_ctrl_inst/read -add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test3_arzkrio/uut/sample_mem_ctrl_inst/ready_in -add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test3_arzkrio/uut/sample_mem_ctrl_inst/valid_in -add wave -noupdate -group {SAMPLE MEM} -radix hexadecimal /l0_dds_reader_test3_arzkrio/uut/sample_mem_ctrl_inst/data_in -add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test3_arzkrio/uut/sample_mem_ctrl_inst/ready_out -add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test3_arzkrio/uut/sample_mem_ctrl_inst/valid_out -add wave -noupdate -group {SAMPLE MEM} -radix hexadecimal /l0_dds_reader_test3_arzkrio/uut/sample_mem_ctrl_inst/data_out -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test3_arzkrio/uut/payload_abort_read -add wave -noupdate -group {PAYLOAD MEM} -radix unsigned /l0_dds_reader_test3_arzkrio/uut/payload_mem_ctrl_inst/addr -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test3_arzkrio/uut/payload_mem_ctrl_inst/read -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test3_arzkrio/uut/payload_mem_ctrl_inst/ready_in -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test3_arzkrio/uut/payload_mem_ctrl_inst/valid_in -add wave -noupdate -group {PAYLOAD MEM} -radix hexadecimal /l0_dds_reader_test3_arzkrio/uut/payload_mem_ctrl_inst/data_in -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test3_arzkrio/uut/payload_mem_ctrl_inst/ready_out -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test3_arzkrio/uut/payload_mem_ctrl_inst/valid_out -add wave -noupdate -group {PAYLOAD MEM} -radix hexadecimal /l0_dds_reader_test3_arzkrio/uut/payload_mem_ctrl_inst/data_out -add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test3_arzkrio/uut/inst_abort_read -add wave -noupdate -group {INSTANCE MEM} -radix unsigned /l0_dds_reader_test3_arzkrio/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/addr -add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test3_arzkrio/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/read -add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test3_arzkrio/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/ready_in -add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test3_arzkrio/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/valid_in -add wave -noupdate -group {INSTANCE MEM} -radix hexadecimal /l0_dds_reader_test3_arzkrio/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/data_in -add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test3_arzkrio/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/ready_out -add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test3_arzkrio/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/valid_out -add wave -noupdate -group {INSTANCE MEM} -radix hexadecimal /l0_dds_reader_test3_arzkrio/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/data_out -add wave -noupdate /l0_dds_reader_test3_arzkrio/uut/inst_op_start -add wave -noupdate /l0_dds_reader_test3_arzkrio/uut/inst_opcode -add wave -noupdate /l0_dds_reader_test3_arzkrio/uut/inst_op_done -add wave -noupdate /l0_dds_reader_test3_arzkrio/uut/inst_stage -add wave -noupdate /l0_dds_reader_test3_arzkrio/uut/inst_stage_next -add wave -noupdate /l0_dds_reader_test3_arzkrio/uut/inst_cnt -add wave -noupdate -radix unsigned /l0_dds_reader_test3_arzkrio/uut/inst_addr_base -add wave -noupdate /l0_dds_reader_test3_arzkrio/uut/inst_mem_fields -add wave -noupdate -childformat {{/l0_dds_reader_test3_arzkrio/uut/inst_data.key_hash -radix hexadecimal} {/l0_dds_reader_test3_arzkrio/uut/inst_data.status_info -radix binary} {/l0_dds_reader_test3_arzkrio/uut/inst_data.sample_cnt -radix unsigned} {/l0_dds_reader_test3_arzkrio/uut/inst_data.disposed_gen_cnt -radix unsigned} {/l0_dds_reader_test3_arzkrio/uut/inst_data.no_writers_gen_cnt -radix unsigned} {/l0_dds_reader_test3_arzkrio/uut/inst_data.ignore_deadline -radix unsigned} {/l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap -radix binary -childformat {{/l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0) -radix binary -childformat {{/l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(0) -radix binary} {/l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(1) -radix binary} {/l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(2) -radix binary} {/l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(3) -radix binary} {/l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(4) -radix binary} {/l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(5) -radix binary} {/l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(6) -radix binary} {/l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(7) -radix binary} {/l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(8) -radix binary} {/l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(9) -radix binary} {/l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(10) -radix binary} {/l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(11) -radix binary} {/l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(12) -radix binary} {/l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(13) -radix binary} {/l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(14) -radix binary} {/l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(15) -radix binary} {/l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(16) -radix binary} {/l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(17) -radix binary} {/l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(18) -radix binary} {/l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(19) -radix binary} {/l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(20) -radix binary} {/l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(21) -radix binary} {/l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(22) -radix binary} {/l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(23) -radix binary} {/l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(24) -radix binary} {/l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(25) -radix binary} {/l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(26) -radix binary} {/l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(27) -radix binary} {/l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(28) -radix binary} {/l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(29) -radix binary} {/l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(30) -radix binary} {/l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(31) -radix binary}}}}}} -expand -subitemconfig {/l0_dds_reader_test3_arzkrio/uut/inst_data.key_hash {-height 15 -radix hexadecimal} /l0_dds_reader_test3_arzkrio/uut/inst_data.status_info {-height 15 -radix binary} /l0_dds_reader_test3_arzkrio/uut/inst_data.sample_cnt {-height 15 -radix unsigned} /l0_dds_reader_test3_arzkrio/uut/inst_data.disposed_gen_cnt {-height 15 -radix unsigned} /l0_dds_reader_test3_arzkrio/uut/inst_data.no_writers_gen_cnt {-height 15 -radix unsigned} /l0_dds_reader_test3_arzkrio/uut/inst_data.ignore_deadline {-height 15 -radix unsigned} /l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap {-height 15 -radix binary -childformat {{/l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0) -radix binary -childformat {{/l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(0) -radix binary} {/l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(1) -radix binary} {/l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(2) -radix binary} {/l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(3) -radix binary} {/l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(4) -radix binary} {/l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(5) -radix binary} {/l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(6) -radix binary} {/l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(7) -radix binary} {/l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(8) -radix binary} {/l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(9) -radix binary} {/l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(10) -radix binary} {/l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(11) -radix binary} {/l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(12) -radix binary} {/l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(13) -radix binary} {/l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(14) -radix binary} {/l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(15) -radix binary} {/l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(16) -radix binary} {/l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(17) -radix binary} {/l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(18) -radix binary} {/l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(19) -radix binary} {/l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(20) -radix binary} {/l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(21) -radix binary} {/l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(22) -radix binary} {/l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(23) -radix binary} {/l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(24) -radix binary} {/l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(25) -radix binary} {/l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(26) -radix binary} {/l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(27) -radix binary} {/l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(28) -radix binary} {/l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(29) -radix binary} {/l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(30) -radix binary} {/l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(31) -radix binary}}}}} /l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0) {-height 15 -radix binary -childformat {{/l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(0) -radix binary} {/l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(1) -radix binary} {/l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(2) -radix binary} {/l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(3) -radix binary} {/l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(4) -radix binary} {/l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(5) -radix binary} {/l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(6) -radix binary} {/l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(7) -radix binary} {/l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(8) -radix binary} {/l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(9) -radix binary} {/l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(10) -radix binary} {/l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(11) -radix binary} {/l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(12) -radix binary} {/l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(13) -radix binary} {/l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(14) -radix binary} {/l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(15) -radix binary} {/l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(16) -radix binary} {/l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(17) -radix binary} {/l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(18) -radix binary} {/l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(19) -radix binary} {/l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(20) -radix binary} {/l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(21) -radix binary} {/l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(22) -radix binary} {/l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(23) -radix binary} {/l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(24) -radix binary} {/l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(25) -radix binary} {/l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(26) -radix binary} {/l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(27) -radix binary} {/l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(28) -radix binary} {/l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(29) -radix binary} {/l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(30) -radix binary} {/l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(31) -radix binary}}} /l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(0) {-height 15 -radix binary} /l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(1) {-height 15 -radix binary} /l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(2) {-height 15 -radix binary} /l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(3) {-height 15 -radix binary} /l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(4) {-height 15 -radix binary} /l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(5) {-height 15 -radix binary} /l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(6) {-height 15 -radix binary} /l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(7) {-height 15 -radix binary} /l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(8) {-height 15 -radix binary} /l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(9) {-height 15 -radix binary} /l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(10) {-height 15 -radix binary} /l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(11) {-height 15 -radix binary} /l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(12) {-height 15 -radix binary} /l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(13) {-height 15 -radix binary} /l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(14) {-height 15 -radix binary} /l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(15) {-height 15 -radix binary} /l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(16) {-height 15 -radix binary} /l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(17) {-height 15 -radix binary} /l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(18) {-height 15 -radix binary} /l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(19) {-height 15 -radix binary} /l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(20) {-height 15 -radix binary} /l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(21) {-height 15 -radix binary} /l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(22) {-height 15 -radix binary} /l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(23) {-height 15 -radix binary} /l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(24) {-height 15 -radix binary} /l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(25) {-height 15 -radix binary} /l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(26) {-height 15 -radix binary} /l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(27) {-height 15 -radix binary} /l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(28) {-height 15 -radix binary} /l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(29) {-height 15 -radix binary} /l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(30) {-height 15 -radix binary} /l0_dds_reader_test3_arzkrio/uut/inst_data.writer_bitmap(0)(31) {-height 15 -radix binary}} /l0_dds_reader_test3_arzkrio/uut/inst_data -add wave -noupdate -radix unsigned /l0_dds_reader_test3_arzkrio/uut/inst_next_addr_base -add wave -noupdate -radix unsigned /l0_dds_reader_test3_arzkrio/uut/inst_prev_addr_base -add wave -noupdate /l0_dds_reader_test3_arzkrio/uut/current_imf -add wave -noupdate /l0_dds_reader_test3_arzkrio/uut/stale_inst_cnt -add wave -noupdate -divider POINTERS -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test3_arzkrio/uut/empty_sample_list_head -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test3_arzkrio/uut/empty_sample_list_tail -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test3_arzkrio/uut/empty_payload_list_head -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test3_arzkrio/uut/oldest_sample -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test3_arzkrio/uut/newest_sample -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test3_arzkrio/uut/inst_empty_head -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test3_arzkrio/uut/inst_occupied_head -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test3_arzkrio/uut/cur_sample -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test3_arzkrio/uut/next_sample -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test3_arzkrio/uut/prev_sample -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test3_arzkrio/uut/cur_payload -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test3_arzkrio/uut/next_payload -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test3_arzkrio/uut/cur_inst -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test3_arzkrio/uut/next_inst -add wave -noupdate -divider TESTBENCH -add wave -noupdate -group TESTBENCH /l0_dds_reader_test3_arzkrio/dds_start -add wave -noupdate -group TESTBENCH /l0_dds_reader_test3_arzkrio/dds_stage -add wave -noupdate -group TESTBENCH /l0_dds_reader_test3_arzkrio/dds_cnt -add wave -noupdate -group TESTBENCH /l0_dds_reader_test3_arzkrio/dds_cnt2 -add wave -noupdate -group TESTBENCH /l0_dds_reader_test3_arzkrio/dds_done -add wave -noupdate -group TESTBENCH /l0_dds_reader_test3_arzkrio/rtps_start -add wave -noupdate -group TESTBENCH /l0_dds_reader_test3_arzkrio/rtps_stage -add wave -noupdate -group TESTBENCH /l0_dds_reader_test3_arzkrio/rtps_cnt -add wave -noupdate -group TESTBENCH /l0_dds_reader_test3_arzkrio/rtps_done -add wave -noupdate -divider {KEY HOLDER} -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test3_arzkrio/uut/start_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test3_arzkrio/uut/opcode_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test3_arzkrio/uut/ack_kh -add wave -noupdate -group {KEY HOLDER} -radix hexadecimal /l0_dds_reader_test3_arzkrio/uut/data_in_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test3_arzkrio/uut/valid_in_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test3_arzkrio/uut/ready_in_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test3_arzkrio/uut/last_word_in_kh -add wave -noupdate -group {KEY HOLDER} -radix hexadecimal /l0_dds_reader_test3_arzkrio/uut/data_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test3_arzkrio/uut/valid_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test3_arzkrio/uut/ready_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test3_arzkrio/uut/last_word_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test3_arzkrio/uut/abort_kh -add wave -noupdate -divider MISC -add wave -noupdate -radix unsigned /l0_dds_reader_test3_arzkrio/uut/collection_cnt -add wave -noupdate -radix unsigned /l0_dds_reader_test3_arzkrio/uut/collection_cnt_max -add wave -noupdate -radix unsigned /l0_dds_reader_test3_arzkrio/uut/collection_generation_rank -add wave -noupdate -radix unsigned /l0_dds_reader_test3_arzkrio/uut/cur_generation_rank -add wave -noupdate -radix unsigned /l0_dds_reader_test3_arzkrio/uut/max_samples_latch -add wave -noupdate /l0_dds_reader_test3_arzkrio/uut/dynamic_next_instance -add wave -noupdate /l0_dds_reader_test3_arzkrio/uut/single_instance -add wave -noupdate /l0_dds_reader_test3_arzkrio/uut/is_take -add wave -noupdate -radix unsigned /l0_dds_reader_test3_arzkrio/uut/sel_sample -add wave -noupdate -radix unsigned /l0_dds_reader_test3_arzkrio/uut/sample_p1 -add wave -noupdate -radix unsigned /l0_dds_reader_test3_arzkrio/uut/sample_p2 -add wave -noupdate -radix SAMPLE_STATE /l0_dds_reader_test3_arzkrio/uut/sample_state -add wave -noupdate -radix VIEW_STATE /l0_dds_reader_test3_arzkrio/uut/view_state -add wave -noupdate -radix INSTANCE_STATE /l0_dds_reader_test3_arzkrio/uut/instance_state -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {262408405 ps} 0} {{Cursor 2} {115175000 ps} 1} -quietly wave cursor active 1 -configure wave -namecolwidth 187 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -configure wave -timelineunits ns -update -WaveRestoreZoom {261834536 ps} {262835177 ps} diff --git a/sim/L0_dds_reader_test3_arzkriu.do b/sim/L0_dds_reader_test3_arzkriu.do deleted file mode 100644 index 4376142..0000000 --- a/sim/L0_dds_reader_test3_arzkriu.do +++ /dev/null @@ -1,199 +0,0 @@ -onerror {resume} -radix define DDS_RETCODE { - "10#0#" "RETCODE_OK", - "10#1#" "RETCODE_ERROR", - "10#2#" "RETCODE_UNSUPPORTED", - "10#3#" "RETCODE_BAD_PARAMETER", - "10#4#" "RETCODE_PRECONDITION_NOT_MET", - "10#5#" "RETCODE_OUT_OF_RESOURCES", - "10#6#" "RETCODE_NOT_ENABLED", - "10#7#" "RETCODE_IMMUTABLE_POLICY", - "10#8#" "RETCODE_INCONSISTENT_POLICY", - "10#9#" "RETCODE_ALREADY_DELETED", - "10#10#" "RETCODE_TIMEOUT", - "10#11#" "RETCODE_NO_DATA", - "10#12#" "RETCODE_ILLEGAL_OPERATION", - -default unsigned -} -radix define SAMPLE_STATE { - "16#00000001#" "READ_SAMPLE_STATE", - "16#00000002#" "NOT_READ_SAMPLE_STATE", - "16#FFFFFFFF#" "ANY_SAMPLE_STATE", - -default binary -} -radix define VIEW_STATE { - "16#00000001#" "NEW_VIEW_STATE", - "16#00000002#" "NOT_NEW_VIEW_STATE", - "16#FFFFFFFF#" "ANY_VIEW_STATE", - -default binary -} -radix define INSTANCE_STATE { - "16#00000001#" "ALIVE_INSTANCE_STATE", - "16#00000002#" "NOT_ALIVE_DISPOSED_INSTANCE_STATE", - "16#00000004#" "NOT_ALIVE_NO_WRITERS_INSTANCE_STATE", - "16#FFFFFFFF#" "ANY_INSTANCE_STATE", - -default binary -} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -divider SYSTEM -add wave -noupdate /l0_dds_reader_test3_arzkriu/uut/clk -add wave -noupdate /l0_dds_reader_test3_arzkriu/uut/reset -add wave -noupdate -radix unsigned /l0_dds_reader_test3_arzkriu/uut/time -add wave -noupdate -divider RTPS -add wave -noupdate -group RTPS /l0_dds_reader_test3_arzkriu/uut/start_rtps -add wave -noupdate -group RTPS /l0_dds_reader_test3_arzkriu/uut/opcode_rtps -add wave -noupdate -group RTPS /l0_dds_reader_test3_arzkriu/uut/ack_rtps -add wave -noupdate -group RTPS /l0_dds_reader_test3_arzkriu/uut/ret_rtps -add wave -noupdate -group RTPS /l0_dds_reader_test3_arzkriu/uut/done_rtps -add wave -noupdate -group RTPS /l0_dds_reader_test3_arzkriu/uut/ready_in_rtps -add wave -noupdate -group RTPS /l0_dds_reader_test3_arzkriu/uut/valid_in_rtps -add wave -noupdate -group RTPS -radix hexadecimal /l0_dds_reader_test3_arzkriu/uut/data_in_rtps -add wave -noupdate -group RTPS /l0_dds_reader_test3_arzkriu/uut/last_word_in_rtps -add wave -noupdate -divider DDS -add wave -noupdate -expand -group DDS /l0_dds_reader_test3_arzkriu/uut/start_dds -add wave -noupdate -expand -group DDS /l0_dds_reader_test3_arzkriu/uut/ack_dds -add wave -noupdate -expand -group DDS /l0_dds_reader_test3_arzkriu/uut/opcode_dds -add wave -noupdate -expand -group DDS -radix SAMPLE_STATE /l0_dds_reader_test3_arzkriu/uut/sample_state_dds -add wave -noupdate -expand -group DDS -radix INSTANCE_STATE /l0_dds_reader_test3_arzkriu/uut/instance_state_dds -add wave -noupdate -expand -group DDS -radix VIEW_STATE /l0_dds_reader_test3_arzkriu/uut/view_state_dds -add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_reader_test3_arzkriu/uut/instance_handle_dds -add wave -noupdate -expand -group DDS -radix unsigned /l0_dds_reader_test3_arzkriu/uut/max_samples_dds -add wave -noupdate -expand -group DDS -radix DDS_RETCODE /l0_dds_reader_test3_arzkriu/uut/return_code_dds -add wave -noupdate -expand -group DDS /l0_dds_reader_test3_arzkriu/uut/done_dds -add wave -noupdate -expand -group DDS -divider SI -add wave -noupdate -expand -group DDS -radix SAMPLE_STATE /l0_dds_reader_test3_arzkriu/uut/si_sample_state -add wave -noupdate -expand -group DDS -radix VIEW_STATE /l0_dds_reader_test3_arzkriu/uut/si_view_state -add wave -noupdate -expand -group DDS -radix INSTANCE_STATE /l0_dds_reader_test3_arzkriu/uut/si_instance_state -add wave -noupdate -expand -group DDS -radix unsigned /l0_dds_reader_test3_arzkriu/uut/si_source_timestamp -add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_reader_test3_arzkriu/uut/si_instance_handle -add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_reader_test3_arzkriu/uut/si_publication_handle -add wave -noupdate -expand -group DDS -radix unsigned /l0_dds_reader_test3_arzkriu/uut/si_disposed_generation_count -add wave -noupdate -expand -group DDS -radix unsigned /l0_dds_reader_test3_arzkriu/uut/si_no_writers_generation_count -add wave -noupdate -expand -group DDS -radix unsigned /l0_dds_reader_test3_arzkriu/uut/si_sample_rank -add wave -noupdate -expand -group DDS -radix unsigned /l0_dds_reader_test3_arzkriu/uut/si_generation_rank -add wave -noupdate -expand -group DDS -radix unsigned /l0_dds_reader_test3_arzkriu/uut/si_absolute_generation_rank -add wave -noupdate -expand -group DDS /l0_dds_reader_test3_arzkriu/uut/si_valid_data -add wave -noupdate -expand -group DDS /l0_dds_reader_test3_arzkriu/uut/si_valid -add wave -noupdate -expand -group DDS /l0_dds_reader_test3_arzkriu/uut/get_data_dds -add wave -noupdate -expand -group DDS /l0_dds_reader_test3_arzkriu/uut/eoc -add wave -noupdate -expand -group DDS -divider OUTPUT -add wave -noupdate -expand -group DDS /l0_dds_reader_test3_arzkriu/uut/ready_out_dds -add wave -noupdate -expand -group DDS /l0_dds_reader_test3_arzkriu/uut/valid_out_dds -add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_reader_test3_arzkriu/uut/data_out_dds -add wave -noupdate -expand -group DDS /l0_dds_reader_test3_arzkriu/uut/last_word_out_dds -add wave -noupdate -divider {MAIN FSM} -add wave -noupdate /l0_dds_reader_test3_arzkriu/uut/stage -add wave -noupdate /l0_dds_reader_test3_arzkriu/uut/stage_next -add wave -noupdate /l0_dds_reader_test3_arzkriu/uut/cnt -add wave -noupdate -divider MEMORY -add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test3_arzkriu/uut/sample_abort_read -add wave -noupdate -group {SAMPLE MEM} -radix unsigned /l0_dds_reader_test3_arzkriu/uut/sample_mem_ctrl_inst/addr -add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test3_arzkriu/uut/sample_mem_ctrl_inst/read -add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test3_arzkriu/uut/sample_mem_ctrl_inst/ready_in -add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test3_arzkriu/uut/sample_mem_ctrl_inst/valid_in -add wave -noupdate -group {SAMPLE MEM} -radix hexadecimal /l0_dds_reader_test3_arzkriu/uut/sample_mem_ctrl_inst/data_in -add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test3_arzkriu/uut/sample_mem_ctrl_inst/ready_out -add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test3_arzkriu/uut/sample_mem_ctrl_inst/valid_out -add wave -noupdate -group {SAMPLE MEM} -radix hexadecimal /l0_dds_reader_test3_arzkriu/uut/sample_mem_ctrl_inst/data_out -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test3_arzkriu/uut/payload_abort_read -add wave -noupdate -group {PAYLOAD MEM} -radix unsigned /l0_dds_reader_test3_arzkriu/uut/payload_mem_ctrl_inst/addr -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test3_arzkriu/uut/payload_mem_ctrl_inst/read -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test3_arzkriu/uut/payload_mem_ctrl_inst/ready_in -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test3_arzkriu/uut/payload_mem_ctrl_inst/valid_in -add wave -noupdate -group {PAYLOAD MEM} -radix hexadecimal /l0_dds_reader_test3_arzkriu/uut/payload_mem_ctrl_inst/data_in -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test3_arzkriu/uut/payload_mem_ctrl_inst/ready_out -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test3_arzkriu/uut/payload_mem_ctrl_inst/valid_out -add wave -noupdate -group {PAYLOAD MEM} -radix hexadecimal /l0_dds_reader_test3_arzkriu/uut/payload_mem_ctrl_inst/data_out -add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test3_arzkriu/uut/inst_abort_read -add wave -noupdate -group {INSTANCE MEM} -radix unsigned /l0_dds_reader_test3_arzkriu/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/addr -add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test3_arzkriu/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/read -add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test3_arzkriu/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/ready_in -add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test3_arzkriu/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/valid_in -add wave -noupdate -group {INSTANCE MEM} -radix hexadecimal /l0_dds_reader_test3_arzkriu/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/data_in -add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test3_arzkriu/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/ready_out -add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test3_arzkriu/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/valid_out -add wave -noupdate -group {INSTANCE MEM} -radix hexadecimal /l0_dds_reader_test3_arzkriu/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/data_out -add wave -noupdate /l0_dds_reader_test3_arzkriu/uut/inst_op_start -add wave -noupdate /l0_dds_reader_test3_arzkriu/uut/inst_opcode -add wave -noupdate /l0_dds_reader_test3_arzkriu/uut/inst_op_done -add wave -noupdate /l0_dds_reader_test3_arzkriu/uut/inst_stage -add wave -noupdate /l0_dds_reader_test3_arzkriu/uut/inst_stage_next -add wave -noupdate /l0_dds_reader_test3_arzkriu/uut/inst_cnt -add wave -noupdate -radix unsigned /l0_dds_reader_test3_arzkriu/uut/inst_addr_base -add wave -noupdate /l0_dds_reader_test3_arzkriu/uut/inst_mem_fields -add wave -noupdate -childformat {{/l0_dds_reader_test3_arzkriu/uut/inst_data.key_hash -radix hexadecimal} {/l0_dds_reader_test3_arzkriu/uut/inst_data.status_info -radix binary} {/l0_dds_reader_test3_arzkriu/uut/inst_data.sample_cnt -radix unsigned} {/l0_dds_reader_test3_arzkriu/uut/inst_data.disposed_gen_cnt -radix unsigned} {/l0_dds_reader_test3_arzkriu/uut/inst_data.no_writers_gen_cnt -radix unsigned} {/l0_dds_reader_test3_arzkriu/uut/inst_data.ignore_deadline -radix unsigned} {/l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap -radix binary -childformat {{/l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0) -radix binary -childformat {{/l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(0) -radix binary} {/l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(1) -radix binary} {/l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(2) -radix binary} {/l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(3) -radix binary} {/l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(4) -radix binary} {/l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(5) -radix binary} {/l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(6) -radix binary} {/l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(7) -radix binary} {/l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(8) -radix binary} {/l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(9) -radix binary} {/l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(10) -radix binary} {/l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(11) -radix binary} {/l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(12) -radix binary} {/l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(13) -radix binary} {/l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(14) -radix binary} {/l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(15) -radix binary} {/l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(16) -radix binary} {/l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(17) -radix binary} {/l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(18) -radix binary} {/l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(19) -radix binary} {/l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(20) -radix binary} {/l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(21) -radix binary} {/l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(22) -radix binary} {/l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(23) -radix binary} {/l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(24) -radix binary} {/l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(25) -radix binary} {/l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(26) -radix binary} {/l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(27) -radix binary} {/l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(28) -radix binary} {/l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(29) -radix binary} {/l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(30) -radix binary} {/l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(31) -radix binary}}}}}} -expand -subitemconfig {/l0_dds_reader_test3_arzkriu/uut/inst_data.key_hash {-height 15 -radix hexadecimal} /l0_dds_reader_test3_arzkriu/uut/inst_data.status_info {-height 15 -radix binary} /l0_dds_reader_test3_arzkriu/uut/inst_data.sample_cnt {-height 15 -radix unsigned} /l0_dds_reader_test3_arzkriu/uut/inst_data.disposed_gen_cnt {-height 15 -radix unsigned} /l0_dds_reader_test3_arzkriu/uut/inst_data.no_writers_gen_cnt {-height 15 -radix unsigned} /l0_dds_reader_test3_arzkriu/uut/inst_data.ignore_deadline {-height 15 -radix unsigned} /l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap {-height 15 -radix binary -childformat {{/l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0) -radix binary -childformat {{/l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(0) -radix binary} {/l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(1) -radix binary} {/l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(2) -radix binary} {/l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(3) -radix binary} {/l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(4) -radix binary} {/l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(5) -radix binary} {/l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(6) -radix binary} {/l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(7) -radix binary} {/l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(8) -radix binary} {/l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(9) -radix binary} {/l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(10) -radix binary} {/l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(11) -radix binary} {/l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(12) -radix binary} {/l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(13) -radix binary} {/l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(14) -radix binary} {/l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(15) -radix binary} {/l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(16) -radix binary} {/l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(17) -radix binary} {/l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(18) -radix binary} {/l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(19) -radix binary} {/l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(20) -radix binary} {/l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(21) -radix binary} {/l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(22) -radix binary} {/l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(23) -radix binary} {/l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(24) -radix binary} {/l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(25) -radix binary} {/l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(26) -radix binary} {/l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(27) -radix binary} {/l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(28) -radix binary} {/l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(29) -radix binary} {/l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(30) -radix binary} {/l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(31) -radix binary}}}}} /l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0) {-height 15 -radix binary -childformat {{/l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(0) -radix binary} {/l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(1) -radix binary} {/l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(2) -radix binary} {/l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(3) -radix binary} {/l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(4) -radix binary} {/l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(5) -radix binary} {/l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(6) -radix binary} {/l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(7) -radix binary} {/l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(8) -radix binary} {/l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(9) -radix binary} {/l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(10) -radix binary} {/l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(11) -radix binary} {/l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(12) -radix binary} {/l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(13) -radix binary} {/l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(14) -radix binary} {/l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(15) -radix binary} {/l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(16) -radix binary} {/l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(17) -radix binary} {/l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(18) -radix binary} {/l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(19) -radix binary} {/l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(20) -radix binary} {/l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(21) -radix binary} {/l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(22) -radix binary} {/l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(23) -radix binary} {/l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(24) -radix binary} {/l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(25) -radix binary} {/l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(26) -radix binary} {/l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(27) -radix binary} {/l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(28) -radix binary} {/l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(29) -radix binary} {/l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(30) -radix binary} {/l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(31) -radix binary}}} /l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(0) {-height 15 -radix binary} /l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(1) {-height 15 -radix binary} /l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(2) {-height 15 -radix binary} /l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(3) {-height 15 -radix binary} /l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(4) {-height 15 -radix binary} /l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(5) {-height 15 -radix binary} /l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(6) {-height 15 -radix binary} /l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(7) {-height 15 -radix binary} /l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(8) {-height 15 -radix binary} /l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(9) {-height 15 -radix binary} /l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(10) {-height 15 -radix binary} /l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(11) {-height 15 -radix binary} /l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(12) {-height 15 -radix binary} /l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(13) {-height 15 -radix binary} /l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(14) {-height 15 -radix binary} /l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(15) {-height 15 -radix binary} /l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(16) {-height 15 -radix binary} /l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(17) {-height 15 -radix binary} /l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(18) {-height 15 -radix binary} /l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(19) {-height 15 -radix binary} /l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(20) {-height 15 -radix binary} /l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(21) {-height 15 -radix binary} /l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(22) {-height 15 -radix binary} /l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(23) {-height 15 -radix binary} /l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(24) {-height 15 -radix binary} /l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(25) {-height 15 -radix binary} /l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(26) {-height 15 -radix binary} /l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(27) {-height 15 -radix binary} /l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(28) {-height 15 -radix binary} /l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(29) {-height 15 -radix binary} /l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(30) {-height 15 -radix binary} /l0_dds_reader_test3_arzkriu/uut/inst_data.writer_bitmap(0)(31) {-height 15 -radix binary}} /l0_dds_reader_test3_arzkriu/uut/inst_data -add wave -noupdate -radix unsigned /l0_dds_reader_test3_arzkriu/uut/inst_next_addr_base -add wave -noupdate -radix unsigned /l0_dds_reader_test3_arzkriu/uut/inst_prev_addr_base -add wave -noupdate /l0_dds_reader_test3_arzkriu/uut/current_imf -add wave -noupdate /l0_dds_reader_test3_arzkriu/uut/stale_inst_cnt -add wave -noupdate -divider POINTERS -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test3_arzkriu/uut/empty_sample_list_head -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test3_arzkriu/uut/empty_sample_list_tail -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test3_arzkriu/uut/empty_payload_list_head -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test3_arzkriu/uut/oldest_sample -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test3_arzkriu/uut/newest_sample -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test3_arzkriu/uut/inst_empty_head -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test3_arzkriu/uut/inst_occupied_head -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test3_arzkriu/uut/cur_sample -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test3_arzkriu/uut/next_sample -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test3_arzkriu/uut/prev_sample -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test3_arzkriu/uut/cur_payload -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test3_arzkriu/uut/next_payload -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test3_arzkriu/uut/cur_inst -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test3_arzkriu/uut/next_inst -add wave -noupdate -divider TESTBENCH -add wave -noupdate -group TESTBENCH /l0_dds_reader_test3_arzkriu/dds_start -add wave -noupdate -group TESTBENCH /l0_dds_reader_test3_arzkriu/dds_stage -add wave -noupdate -group TESTBENCH /l0_dds_reader_test3_arzkriu/dds_cnt -add wave -noupdate -group TESTBENCH /l0_dds_reader_test3_arzkriu/dds_cnt2 -add wave -noupdate -group TESTBENCH /l0_dds_reader_test3_arzkriu/dds_done -add wave -noupdate -group TESTBENCH /l0_dds_reader_test3_arzkriu/rtps_start -add wave -noupdate -group TESTBENCH /l0_dds_reader_test3_arzkriu/rtps_stage -add wave -noupdate -group TESTBENCH /l0_dds_reader_test3_arzkriu/rtps_cnt -add wave -noupdate -group TESTBENCH /l0_dds_reader_test3_arzkriu/rtps_done -add wave -noupdate -divider {KEY HOLDER} -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test3_arzkriu/uut/start_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test3_arzkriu/uut/opcode_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test3_arzkriu/uut/ack_kh -add wave -noupdate -group {KEY HOLDER} -radix hexadecimal /l0_dds_reader_test3_arzkriu/uut/data_in_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test3_arzkriu/uut/valid_in_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test3_arzkriu/uut/ready_in_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test3_arzkriu/uut/last_word_in_kh -add wave -noupdate -group {KEY HOLDER} -radix hexadecimal /l0_dds_reader_test3_arzkriu/uut/data_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test3_arzkriu/uut/valid_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test3_arzkriu/uut/ready_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test3_arzkriu/uut/last_word_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test3_arzkriu/uut/abort_kh -add wave -noupdate -divider MISC -add wave -noupdate -radix unsigned /l0_dds_reader_test3_arzkriu/uut/collection_cnt -add wave -noupdate -radix unsigned /l0_dds_reader_test3_arzkriu/uut/collection_cnt_max -add wave -noupdate -radix unsigned /l0_dds_reader_test3_arzkriu/uut/collection_generation_rank -add wave -noupdate -radix unsigned /l0_dds_reader_test3_arzkriu/uut/cur_generation_rank -add wave -noupdate -radix unsigned /l0_dds_reader_test3_arzkriu/uut/max_samples_latch -add wave -noupdate /l0_dds_reader_test3_arzkriu/uut/dynamic_next_instance -add wave -noupdate /l0_dds_reader_test3_arzkriu/uut/single_instance -add wave -noupdate /l0_dds_reader_test3_arzkriu/uut/is_take -add wave -noupdate -radix unsigned /l0_dds_reader_test3_arzkriu/uut/sel_sample -add wave -noupdate -radix unsigned /l0_dds_reader_test3_arzkriu/uut/sample_p1 -add wave -noupdate -radix unsigned /l0_dds_reader_test3_arzkriu/uut/sample_p2 -add wave -noupdate -radix SAMPLE_STATE /l0_dds_reader_test3_arzkriu/uut/sample_state -add wave -noupdate -radix VIEW_STATE /l0_dds_reader_test3_arzkriu/uut/view_state -add wave -noupdate -radix INSTANCE_STATE /l0_dds_reader_test3_arzkriu/uut/instance_state -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {262408405 ps} 0} {{Cursor 2} {115175000 ps} 1} -quietly wave cursor active 1 -configure wave -namecolwidth 187 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -configure wave -timelineunits ns -update -WaveRestoreZoom {261834536 ps} {262835177 ps} diff --git a/sim/L0_dds_reader_test3_arzkrto.do b/sim/L0_dds_reader_test3_arzkrto.do deleted file mode 100644 index 0310a3b..0000000 --- a/sim/L0_dds_reader_test3_arzkrto.do +++ /dev/null @@ -1,199 +0,0 @@ -onerror {resume} -radix define DDS_RETCODE { - "10#0#" "RETCODE_OK", - "10#1#" "RETCODE_ERROR", - "10#2#" "RETCODE_UNSUPPORTED", - "10#3#" "RETCODE_BAD_PARAMETER", - "10#4#" "RETCODE_PRECONDITION_NOT_MET", - "10#5#" "RETCODE_OUT_OF_RESOURCES", - "10#6#" "RETCODE_NOT_ENABLED", - "10#7#" "RETCODE_IMMUTABLE_POLICY", - "10#8#" "RETCODE_INCONSISTENT_POLICY", - "10#9#" "RETCODE_ALREADY_DELETED", - "10#10#" "RETCODE_TIMEOUT", - "10#11#" "RETCODE_NO_DATA", - "10#12#" "RETCODE_ILLEGAL_OPERATION", - -default unsigned -} -radix define SAMPLE_STATE { - "16#00000001#" "READ_SAMPLE_STATE", - "16#00000002#" "NOT_READ_SAMPLE_STATE", - "16#FFFFFFFF#" "ANY_SAMPLE_STATE", - -default binary -} -radix define VIEW_STATE { - "16#00000001#" "NEW_VIEW_STATE", - "16#00000002#" "NOT_NEW_VIEW_STATE", - "16#FFFFFFFF#" "ANY_VIEW_STATE", - -default binary -} -radix define INSTANCE_STATE { - "16#00000001#" "ALIVE_INSTANCE_STATE", - "16#00000002#" "NOT_ALIVE_DISPOSED_INSTANCE_STATE", - "16#00000004#" "NOT_ALIVE_NO_WRITERS_INSTANCE_STATE", - "16#FFFFFFFF#" "ANY_INSTANCE_STATE", - -default binary -} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -divider SYSTEM -add wave -noupdate /l0_dds_reader_test3_arzkrto/uut/clk -add wave -noupdate /l0_dds_reader_test3_arzkrto/uut/reset -add wave -noupdate -radix unsigned /l0_dds_reader_test3_arzkrto/uut/time -add wave -noupdate -divider RTPS -add wave -noupdate -group RTPS /l0_dds_reader_test3_arzkrto/uut/start_rtps -add wave -noupdate -group RTPS /l0_dds_reader_test3_arzkrto/uut/opcode_rtps -add wave -noupdate -group RTPS /l0_dds_reader_test3_arzkrto/uut/ack_rtps -add wave -noupdate -group RTPS /l0_dds_reader_test3_arzkrto/uut/ret_rtps -add wave -noupdate -group RTPS /l0_dds_reader_test3_arzkrto/uut/done_rtps -add wave -noupdate -group RTPS /l0_dds_reader_test3_arzkrto/uut/ready_in_rtps -add wave -noupdate -group RTPS /l0_dds_reader_test3_arzkrto/uut/valid_in_rtps -add wave -noupdate -group RTPS -radix hexadecimal /l0_dds_reader_test3_arzkrto/uut/data_in_rtps -add wave -noupdate -group RTPS /l0_dds_reader_test3_arzkrto/uut/last_word_in_rtps -add wave -noupdate -divider DDS -add wave -noupdate -expand -group DDS /l0_dds_reader_test3_arzkrto/uut/start_dds -add wave -noupdate -expand -group DDS /l0_dds_reader_test3_arzkrto/uut/ack_dds -add wave -noupdate -expand -group DDS /l0_dds_reader_test3_arzkrto/uut/opcode_dds -add wave -noupdate -expand -group DDS -radix SAMPLE_STATE /l0_dds_reader_test3_arzkrto/uut/sample_state_dds -add wave -noupdate -expand -group DDS -radix INSTANCE_STATE /l0_dds_reader_test3_arzkrto/uut/instance_state_dds -add wave -noupdate -expand -group DDS -radix VIEW_STATE /l0_dds_reader_test3_arzkrto/uut/view_state_dds -add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_reader_test3_arzkrto/uut/instance_handle_dds -add wave -noupdate -expand -group DDS -radix unsigned /l0_dds_reader_test3_arzkrto/uut/max_samples_dds -add wave -noupdate -expand -group DDS -radix DDS_RETCODE /l0_dds_reader_test3_arzkrto/uut/return_code_dds -add wave -noupdate -expand -group DDS /l0_dds_reader_test3_arzkrto/uut/done_dds -add wave -noupdate -expand -group DDS -divider SI -add wave -noupdate -expand -group DDS -radix SAMPLE_STATE /l0_dds_reader_test3_arzkrto/uut/si_sample_state -add wave -noupdate -expand -group DDS -radix VIEW_STATE /l0_dds_reader_test3_arzkrto/uut/si_view_state -add wave -noupdate -expand -group DDS -radix INSTANCE_STATE /l0_dds_reader_test3_arzkrto/uut/si_instance_state -add wave -noupdate -expand -group DDS -radix unsigned /l0_dds_reader_test3_arzkrto/uut/si_source_timestamp -add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_reader_test3_arzkrto/uut/si_instance_handle -add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_reader_test3_arzkrto/uut/si_publication_handle -add wave -noupdate -expand -group DDS -radix unsigned /l0_dds_reader_test3_arzkrto/uut/si_disposed_generation_count -add wave -noupdate -expand -group DDS -radix unsigned /l0_dds_reader_test3_arzkrto/uut/si_no_writers_generation_count -add wave -noupdate -expand -group DDS -radix unsigned /l0_dds_reader_test3_arzkrto/uut/si_sample_rank -add wave -noupdate -expand -group DDS -radix unsigned /l0_dds_reader_test3_arzkrto/uut/si_generation_rank -add wave -noupdate -expand -group DDS -radix unsigned /l0_dds_reader_test3_arzkrto/uut/si_absolute_generation_rank -add wave -noupdate -expand -group DDS /l0_dds_reader_test3_arzkrto/uut/si_valid_data -add wave -noupdate -expand -group DDS /l0_dds_reader_test3_arzkrto/uut/si_valid -add wave -noupdate -expand -group DDS /l0_dds_reader_test3_arzkrto/uut/get_data_dds -add wave -noupdate -expand -group DDS /l0_dds_reader_test3_arzkrto/uut/eoc -add wave -noupdate -expand -group DDS -divider OUTPUT -add wave -noupdate -expand -group DDS /l0_dds_reader_test3_arzkrto/uut/ready_out_dds -add wave -noupdate -expand -group DDS /l0_dds_reader_test3_arzkrto/uut/valid_out_dds -add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_reader_test3_arzkrto/uut/data_out_dds -add wave -noupdate -expand -group DDS /l0_dds_reader_test3_arzkrto/uut/last_word_out_dds -add wave -noupdate -divider {MAIN FSM} -add wave -noupdate /l0_dds_reader_test3_arzkrto/uut/stage -add wave -noupdate /l0_dds_reader_test3_arzkrto/uut/stage_next -add wave -noupdate /l0_dds_reader_test3_arzkrto/uut/cnt -add wave -noupdate -divider MEMORY -add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test3_arzkrto/uut/sample_abort_read -add wave -noupdate -group {SAMPLE MEM} -radix unsigned /l0_dds_reader_test3_arzkrto/uut/sample_mem_ctrl_inst/addr -add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test3_arzkrto/uut/sample_mem_ctrl_inst/read -add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test3_arzkrto/uut/sample_mem_ctrl_inst/ready_in -add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test3_arzkrto/uut/sample_mem_ctrl_inst/valid_in -add wave -noupdate -group {SAMPLE MEM} -radix hexadecimal /l0_dds_reader_test3_arzkrto/uut/sample_mem_ctrl_inst/data_in -add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test3_arzkrto/uut/sample_mem_ctrl_inst/ready_out -add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test3_arzkrto/uut/sample_mem_ctrl_inst/valid_out -add wave -noupdate -group {SAMPLE MEM} -radix hexadecimal /l0_dds_reader_test3_arzkrto/uut/sample_mem_ctrl_inst/data_out -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test3_arzkrto/uut/payload_abort_read -add wave -noupdate -group {PAYLOAD MEM} -radix unsigned /l0_dds_reader_test3_arzkrto/uut/payload_mem_ctrl_inst/addr -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test3_arzkrto/uut/payload_mem_ctrl_inst/read -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test3_arzkrto/uut/payload_mem_ctrl_inst/ready_in -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test3_arzkrto/uut/payload_mem_ctrl_inst/valid_in -add wave -noupdate -group {PAYLOAD MEM} -radix hexadecimal /l0_dds_reader_test3_arzkrto/uut/payload_mem_ctrl_inst/data_in -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test3_arzkrto/uut/payload_mem_ctrl_inst/ready_out -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test3_arzkrto/uut/payload_mem_ctrl_inst/valid_out -add wave -noupdate -group {PAYLOAD MEM} -radix hexadecimal /l0_dds_reader_test3_arzkrto/uut/payload_mem_ctrl_inst/data_out -add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test3_arzkrto/uut/inst_abort_read -add wave -noupdate -group {INSTANCE MEM} -radix unsigned /l0_dds_reader_test3_arzkrto/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/addr -add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test3_arzkrto/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/read -add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test3_arzkrto/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/ready_in -add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test3_arzkrto/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/valid_in -add wave -noupdate -group {INSTANCE MEM} -radix hexadecimal /l0_dds_reader_test3_arzkrto/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/data_in -add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test3_arzkrto/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/ready_out -add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test3_arzkrto/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/valid_out -add wave -noupdate -group {INSTANCE MEM} -radix hexadecimal /l0_dds_reader_test3_arzkrto/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/data_out -add wave -noupdate /l0_dds_reader_test3_arzkrto/uut/inst_op_start -add wave -noupdate /l0_dds_reader_test3_arzkrto/uut/inst_opcode -add wave -noupdate /l0_dds_reader_test3_arzkrto/uut/inst_op_done -add wave -noupdate /l0_dds_reader_test3_arzkrto/uut/inst_stage -add wave -noupdate /l0_dds_reader_test3_arzkrto/uut/inst_stage_next -add wave -noupdate /l0_dds_reader_test3_arzkrto/uut/inst_cnt -add wave -noupdate -radix unsigned /l0_dds_reader_test3_arzkrto/uut/inst_addr_base -add wave -noupdate /l0_dds_reader_test3_arzkrto/uut/inst_mem_fields -add wave -noupdate -childformat {{/l0_dds_reader_test3_arzkrto/uut/inst_data.key_hash -radix hexadecimal} {/l0_dds_reader_test3_arzkrto/uut/inst_data.status_info -radix binary} {/l0_dds_reader_test3_arzkrto/uut/inst_data.sample_cnt -radix unsigned} {/l0_dds_reader_test3_arzkrto/uut/inst_data.disposed_gen_cnt -radix unsigned} {/l0_dds_reader_test3_arzkrto/uut/inst_data.no_writers_gen_cnt -radix unsigned} {/l0_dds_reader_test3_arzkrto/uut/inst_data.ignore_deadline -radix unsigned} {/l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap -radix binary -childformat {{/l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0) -radix binary -childformat {{/l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(0) -radix binary} {/l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(1) -radix binary} {/l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(2) -radix binary} {/l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(3) -radix binary} {/l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(4) -radix binary} {/l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(5) -radix binary} {/l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(6) -radix binary} {/l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(7) -radix binary} {/l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(8) -radix binary} {/l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(9) -radix binary} {/l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(10) -radix binary} {/l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(11) -radix binary} {/l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(12) -radix binary} {/l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(13) -radix binary} {/l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(14) -radix binary} {/l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(15) -radix binary} {/l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(16) -radix binary} {/l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(17) -radix binary} {/l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(18) -radix binary} {/l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(19) -radix binary} {/l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(20) -radix binary} {/l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(21) -radix binary} {/l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(22) -radix binary} {/l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(23) -radix binary} {/l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(24) -radix binary} {/l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(25) -radix binary} {/l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(26) -radix binary} {/l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(27) -radix binary} {/l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(28) -radix binary} {/l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(29) -radix binary} {/l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(30) -radix binary} {/l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(31) -radix binary}}}}}} -expand -subitemconfig {/l0_dds_reader_test3_arzkrto/uut/inst_data.key_hash {-height 15 -radix hexadecimal} /l0_dds_reader_test3_arzkrto/uut/inst_data.status_info {-height 15 -radix binary} /l0_dds_reader_test3_arzkrto/uut/inst_data.sample_cnt {-height 15 -radix unsigned} /l0_dds_reader_test3_arzkrto/uut/inst_data.disposed_gen_cnt {-height 15 -radix unsigned} /l0_dds_reader_test3_arzkrto/uut/inst_data.no_writers_gen_cnt {-height 15 -radix unsigned} /l0_dds_reader_test3_arzkrto/uut/inst_data.ignore_deadline {-height 15 -radix unsigned} /l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap {-height 15 -radix binary -childformat {{/l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0) -radix binary -childformat {{/l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(0) -radix binary} {/l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(1) -radix binary} {/l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(2) -radix binary} {/l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(3) -radix binary} {/l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(4) -radix binary} {/l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(5) -radix binary} {/l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(6) -radix binary} {/l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(7) -radix binary} {/l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(8) -radix binary} {/l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(9) -radix binary} {/l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(10) -radix binary} {/l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(11) -radix binary} {/l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(12) -radix binary} {/l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(13) -radix binary} {/l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(14) -radix binary} {/l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(15) -radix binary} {/l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(16) -radix binary} {/l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(17) -radix binary} {/l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(18) -radix binary} {/l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(19) -radix binary} {/l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(20) -radix binary} {/l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(21) -radix binary} {/l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(22) -radix binary} {/l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(23) -radix binary} {/l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(24) -radix binary} {/l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(25) -radix binary} {/l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(26) -radix binary} {/l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(27) -radix binary} {/l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(28) -radix binary} {/l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(29) -radix binary} {/l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(30) -radix binary} {/l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(31) -radix binary}}}}} /l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0) {-height 15 -radix binary -childformat {{/l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(0) -radix binary} {/l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(1) -radix binary} {/l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(2) -radix binary} {/l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(3) -radix binary} {/l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(4) -radix binary} {/l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(5) -radix binary} {/l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(6) -radix binary} {/l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(7) -radix binary} {/l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(8) -radix binary} {/l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(9) -radix binary} {/l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(10) -radix binary} {/l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(11) -radix binary} {/l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(12) -radix binary} {/l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(13) -radix binary} {/l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(14) -radix binary} {/l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(15) -radix binary} {/l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(16) -radix binary} {/l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(17) -radix binary} {/l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(18) -radix binary} {/l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(19) -radix binary} {/l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(20) -radix binary} {/l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(21) -radix binary} {/l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(22) -radix binary} {/l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(23) -radix binary} {/l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(24) -radix binary} {/l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(25) -radix binary} {/l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(26) -radix binary} {/l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(27) -radix binary} {/l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(28) -radix binary} {/l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(29) -radix binary} {/l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(30) -radix binary} {/l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(31) -radix binary}}} /l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(0) {-height 15 -radix binary} /l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(1) {-height 15 -radix binary} /l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(2) {-height 15 -radix binary} /l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(3) {-height 15 -radix binary} /l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(4) {-height 15 -radix binary} /l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(5) {-height 15 -radix binary} /l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(6) {-height 15 -radix binary} /l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(7) {-height 15 -radix binary} /l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(8) {-height 15 -radix binary} /l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(9) {-height 15 -radix binary} /l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(10) {-height 15 -radix binary} /l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(11) {-height 15 -radix binary} /l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(12) {-height 15 -radix binary} /l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(13) {-height 15 -radix binary} /l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(14) {-height 15 -radix binary} /l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(15) {-height 15 -radix binary} /l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(16) {-height 15 -radix binary} /l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(17) {-height 15 -radix binary} /l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(18) {-height 15 -radix binary} /l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(19) {-height 15 -radix binary} /l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(20) {-height 15 -radix binary} /l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(21) {-height 15 -radix binary} /l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(22) {-height 15 -radix binary} /l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(23) {-height 15 -radix binary} /l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(24) {-height 15 -radix binary} /l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(25) {-height 15 -radix binary} /l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(26) {-height 15 -radix binary} /l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(27) {-height 15 -radix binary} /l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(28) {-height 15 -radix binary} /l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(29) {-height 15 -radix binary} /l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(30) {-height 15 -radix binary} /l0_dds_reader_test3_arzkrto/uut/inst_data.writer_bitmap(0)(31) {-height 15 -radix binary}} /l0_dds_reader_test3_arzkrto/uut/inst_data -add wave -noupdate -radix unsigned /l0_dds_reader_test3_arzkrto/uut/inst_next_addr_base -add wave -noupdate -radix unsigned /l0_dds_reader_test3_arzkrto/uut/inst_prev_addr_base -add wave -noupdate /l0_dds_reader_test3_arzkrto/uut/current_imf -add wave -noupdate /l0_dds_reader_test3_arzkrto/uut/stale_inst_cnt -add wave -noupdate -divider POINTERS -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test3_arzkrto/uut/empty_sample_list_head -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test3_arzkrto/uut/empty_sample_list_tail -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test3_arzkrto/uut/empty_payload_list_head -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test3_arzkrto/uut/oldest_sample -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test3_arzkrto/uut/newest_sample -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test3_arzkrto/uut/inst_empty_head -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test3_arzkrto/uut/inst_occupied_head -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test3_arzkrto/uut/cur_sample -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test3_arzkrto/uut/next_sample -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test3_arzkrto/uut/prev_sample -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test3_arzkrto/uut/cur_payload -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test3_arzkrto/uut/next_payload -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test3_arzkrto/uut/cur_inst -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test3_arzkrto/uut/next_inst -add wave -noupdate -divider TESTBENCH -add wave -noupdate -group TESTBENCH /l0_dds_reader_test3_arzkrto/dds_start -add wave -noupdate -group TESTBENCH /l0_dds_reader_test3_arzkrto/dds_stage -add wave -noupdate -group TESTBENCH /l0_dds_reader_test3_arzkrto/dds_cnt -add wave -noupdate -group TESTBENCH /l0_dds_reader_test3_arzkrto/dds_cnt2 -add wave -noupdate -group TESTBENCH /l0_dds_reader_test3_arzkrto/dds_done -add wave -noupdate -group TESTBENCH /l0_dds_reader_test3_arzkrto/rtps_start -add wave -noupdate -group TESTBENCH /l0_dds_reader_test3_arzkrto/rtps_stage -add wave -noupdate -group TESTBENCH /l0_dds_reader_test3_arzkrto/rtps_cnt -add wave -noupdate -group TESTBENCH /l0_dds_reader_test3_arzkrto/rtps_done -add wave -noupdate -divider {KEY HOLDER} -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test3_arzkrto/uut/start_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test3_arzkrto/uut/opcode_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test3_arzkrto/uut/ack_kh -add wave -noupdate -group {KEY HOLDER} -radix hexadecimal /l0_dds_reader_test3_arzkrto/uut/data_in_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test3_arzkrto/uut/valid_in_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test3_arzkrto/uut/ready_in_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test3_arzkrto/uut/last_word_in_kh -add wave -noupdate -group {KEY HOLDER} -radix hexadecimal /l0_dds_reader_test3_arzkrto/uut/data_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test3_arzkrto/uut/valid_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test3_arzkrto/uut/ready_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test3_arzkrto/uut/last_word_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test3_arzkrto/uut/abort_kh -add wave -noupdate -divider MISC -add wave -noupdate -radix unsigned /l0_dds_reader_test3_arzkrto/uut/collection_cnt -add wave -noupdate -radix unsigned /l0_dds_reader_test3_arzkrto/uut/collection_cnt_max -add wave -noupdate -radix unsigned /l0_dds_reader_test3_arzkrto/uut/collection_generation_rank -add wave -noupdate -radix unsigned /l0_dds_reader_test3_arzkrto/uut/cur_generation_rank -add wave -noupdate -radix unsigned /l0_dds_reader_test3_arzkrto/uut/max_samples_latch -add wave -noupdate /l0_dds_reader_test3_arzkrto/uut/dynamic_next_instance -add wave -noupdate /l0_dds_reader_test3_arzkrto/uut/single_instance -add wave -noupdate /l0_dds_reader_test3_arzkrto/uut/is_take -add wave -noupdate -radix unsigned /l0_dds_reader_test3_arzkrto/uut/sel_sample -add wave -noupdate -radix unsigned /l0_dds_reader_test3_arzkrto/uut/sample_p1 -add wave -noupdate -radix unsigned /l0_dds_reader_test3_arzkrto/uut/sample_p2 -add wave -noupdate -radix SAMPLE_STATE /l0_dds_reader_test3_arzkrto/uut/sample_state -add wave -noupdate -radix VIEW_STATE /l0_dds_reader_test3_arzkrto/uut/view_state -add wave -noupdate -radix INSTANCE_STATE /l0_dds_reader_test3_arzkrto/uut/instance_state -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {262408405 ps} 0} {{Cursor 2} {115175000 ps} 1} -quietly wave cursor active 1 -configure wave -namecolwidth 187 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -configure wave -timelineunits ns -update -WaveRestoreZoom {261834536 ps} {262835177 ps} diff --git a/sim/L0_dds_reader_test3_arzkrtu.do b/sim/L0_dds_reader_test3_arzkrtu.do deleted file mode 100644 index 54c813c..0000000 --- a/sim/L0_dds_reader_test3_arzkrtu.do +++ /dev/null @@ -1,199 +0,0 @@ -onerror {resume} -radix define DDS_RETCODE { - "10#0#" "RETCODE_OK", - "10#1#" "RETCODE_ERROR", - "10#2#" "RETCODE_UNSUPPORTED", - "10#3#" "RETCODE_BAD_PARAMETER", - "10#4#" "RETCODE_PRECONDITION_NOT_MET", - "10#5#" "RETCODE_OUT_OF_RESOURCES", - "10#6#" "RETCODE_NOT_ENABLED", - "10#7#" "RETCODE_IMMUTABLE_POLICY", - "10#8#" "RETCODE_INCONSISTENT_POLICY", - "10#9#" "RETCODE_ALREADY_DELETED", - "10#10#" "RETCODE_TIMEOUT", - "10#11#" "RETCODE_NO_DATA", - "10#12#" "RETCODE_ILLEGAL_OPERATION", - -default unsigned -} -radix define SAMPLE_STATE { - "16#00000001#" "READ_SAMPLE_STATE", - "16#00000002#" "NOT_READ_SAMPLE_STATE", - "16#FFFFFFFF#" "ANY_SAMPLE_STATE", - -default binary -} -radix define VIEW_STATE { - "16#00000001#" "NEW_VIEW_STATE", - "16#00000002#" "NOT_NEW_VIEW_STATE", - "16#FFFFFFFF#" "ANY_VIEW_STATE", - -default binary -} -radix define INSTANCE_STATE { - "16#00000001#" "ALIVE_INSTANCE_STATE", - "16#00000002#" "NOT_ALIVE_DISPOSED_INSTANCE_STATE", - "16#00000004#" "NOT_ALIVE_NO_WRITERS_INSTANCE_STATE", - "16#FFFFFFFF#" "ANY_INSTANCE_STATE", - -default binary -} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -divider SYSTEM -add wave -noupdate /l0_dds_reader_test3_arzkrtu/uut/clk -add wave -noupdate /l0_dds_reader_test3_arzkrtu/uut/reset -add wave -noupdate -radix unsigned /l0_dds_reader_test3_arzkrtu/uut/time -add wave -noupdate -divider RTPS -add wave -noupdate -group RTPS /l0_dds_reader_test3_arzkrtu/uut/start_rtps -add wave -noupdate -group RTPS /l0_dds_reader_test3_arzkrtu/uut/opcode_rtps -add wave -noupdate -group RTPS /l0_dds_reader_test3_arzkrtu/uut/ack_rtps -add wave -noupdate -group RTPS /l0_dds_reader_test3_arzkrtu/uut/ret_rtps -add wave -noupdate -group RTPS /l0_dds_reader_test3_arzkrtu/uut/done_rtps -add wave -noupdate -group RTPS /l0_dds_reader_test3_arzkrtu/uut/ready_in_rtps -add wave -noupdate -group RTPS /l0_dds_reader_test3_arzkrtu/uut/valid_in_rtps -add wave -noupdate -group RTPS -radix hexadecimal /l0_dds_reader_test3_arzkrtu/uut/data_in_rtps -add wave -noupdate -group RTPS /l0_dds_reader_test3_arzkrtu/uut/last_word_in_rtps -add wave -noupdate -divider DDS -add wave -noupdate -expand -group DDS /l0_dds_reader_test3_arzkrtu/uut/start_dds -add wave -noupdate -expand -group DDS /l0_dds_reader_test3_arzkrtu/uut/ack_dds -add wave -noupdate -expand -group DDS /l0_dds_reader_test3_arzkrtu/uut/opcode_dds -add wave -noupdate -expand -group DDS -radix SAMPLE_STATE /l0_dds_reader_test3_arzkrtu/uut/sample_state_dds -add wave -noupdate -expand -group DDS -radix INSTANCE_STATE /l0_dds_reader_test3_arzkrtu/uut/instance_state_dds -add wave -noupdate -expand -group DDS -radix VIEW_STATE /l0_dds_reader_test3_arzkrtu/uut/view_state_dds -add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_reader_test3_arzkrtu/uut/instance_handle_dds -add wave -noupdate -expand -group DDS -radix unsigned /l0_dds_reader_test3_arzkrtu/uut/max_samples_dds -add wave -noupdate -expand -group DDS -radix DDS_RETCODE /l0_dds_reader_test3_arzkrtu/uut/return_code_dds -add wave -noupdate -expand -group DDS /l0_dds_reader_test3_arzkrtu/uut/done_dds -add wave -noupdate -expand -group DDS -divider SI -add wave -noupdate -expand -group DDS -radix SAMPLE_STATE /l0_dds_reader_test3_arzkrtu/uut/si_sample_state -add wave -noupdate -expand -group DDS -radix VIEW_STATE /l0_dds_reader_test3_arzkrtu/uut/si_view_state -add wave -noupdate -expand -group DDS -radix INSTANCE_STATE /l0_dds_reader_test3_arzkrtu/uut/si_instance_state -add wave -noupdate -expand -group DDS -radix unsigned /l0_dds_reader_test3_arzkrtu/uut/si_source_timestamp -add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_reader_test3_arzkrtu/uut/si_instance_handle -add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_reader_test3_arzkrtu/uut/si_publication_handle -add wave -noupdate -expand -group DDS -radix unsigned /l0_dds_reader_test3_arzkrtu/uut/si_disposed_generation_count -add wave -noupdate -expand -group DDS -radix unsigned /l0_dds_reader_test3_arzkrtu/uut/si_no_writers_generation_count -add wave -noupdate -expand -group DDS -radix unsigned /l0_dds_reader_test3_arzkrtu/uut/si_sample_rank -add wave -noupdate -expand -group DDS -radix unsigned /l0_dds_reader_test3_arzkrtu/uut/si_generation_rank -add wave -noupdate -expand -group DDS -radix unsigned /l0_dds_reader_test3_arzkrtu/uut/si_absolute_generation_rank -add wave -noupdate -expand -group DDS /l0_dds_reader_test3_arzkrtu/uut/si_valid_data -add wave -noupdate -expand -group DDS /l0_dds_reader_test3_arzkrtu/uut/si_valid -add wave -noupdate -expand -group DDS /l0_dds_reader_test3_arzkrtu/uut/get_data_dds -add wave -noupdate -expand -group DDS /l0_dds_reader_test3_arzkrtu/uut/eoc -add wave -noupdate -expand -group DDS -divider OUTPUT -add wave -noupdate -expand -group DDS /l0_dds_reader_test3_arzkrtu/uut/ready_out_dds -add wave -noupdate -expand -group DDS /l0_dds_reader_test3_arzkrtu/uut/valid_out_dds -add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_reader_test3_arzkrtu/uut/data_out_dds -add wave -noupdate -expand -group DDS /l0_dds_reader_test3_arzkrtu/uut/last_word_out_dds -add wave -noupdate -divider {MAIN FSM} -add wave -noupdate /l0_dds_reader_test3_arzkrtu/uut/stage -add wave -noupdate /l0_dds_reader_test3_arzkrtu/uut/stage_next -add wave -noupdate /l0_dds_reader_test3_arzkrtu/uut/cnt -add wave -noupdate -divider MEMORY -add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test3_arzkrtu/uut/sample_abort_read -add wave -noupdate -group {SAMPLE MEM} -radix unsigned /l0_dds_reader_test3_arzkrtu/uut/sample_mem_ctrl_inst/addr -add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test3_arzkrtu/uut/sample_mem_ctrl_inst/read -add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test3_arzkrtu/uut/sample_mem_ctrl_inst/ready_in -add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test3_arzkrtu/uut/sample_mem_ctrl_inst/valid_in -add wave -noupdate -group {SAMPLE MEM} -radix hexadecimal /l0_dds_reader_test3_arzkrtu/uut/sample_mem_ctrl_inst/data_in -add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test3_arzkrtu/uut/sample_mem_ctrl_inst/ready_out -add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test3_arzkrtu/uut/sample_mem_ctrl_inst/valid_out -add wave -noupdate -group {SAMPLE MEM} -radix hexadecimal /l0_dds_reader_test3_arzkrtu/uut/sample_mem_ctrl_inst/data_out -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test3_arzkrtu/uut/payload_abort_read -add wave -noupdate -group {PAYLOAD MEM} -radix unsigned /l0_dds_reader_test3_arzkrtu/uut/payload_mem_ctrl_inst/addr -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test3_arzkrtu/uut/payload_mem_ctrl_inst/read -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test3_arzkrtu/uut/payload_mem_ctrl_inst/ready_in -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test3_arzkrtu/uut/payload_mem_ctrl_inst/valid_in -add wave -noupdate -group {PAYLOAD MEM} -radix hexadecimal /l0_dds_reader_test3_arzkrtu/uut/payload_mem_ctrl_inst/data_in -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test3_arzkrtu/uut/payload_mem_ctrl_inst/ready_out -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test3_arzkrtu/uut/payload_mem_ctrl_inst/valid_out -add wave -noupdate -group {PAYLOAD MEM} -radix hexadecimal /l0_dds_reader_test3_arzkrtu/uut/payload_mem_ctrl_inst/data_out -add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test3_arzkrtu/uut/inst_abort_read -add wave -noupdate -group {INSTANCE MEM} -radix unsigned /l0_dds_reader_test3_arzkrtu/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/addr -add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test3_arzkrtu/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/read -add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test3_arzkrtu/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/ready_in -add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test3_arzkrtu/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/valid_in -add wave -noupdate -group {INSTANCE MEM} -radix hexadecimal /l0_dds_reader_test3_arzkrtu/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/data_in -add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test3_arzkrtu/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/ready_out -add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test3_arzkrtu/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/valid_out -add wave -noupdate -group {INSTANCE MEM} -radix hexadecimal /l0_dds_reader_test3_arzkrtu/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/data_out -add wave -noupdate /l0_dds_reader_test3_arzkrtu/uut/inst_op_start -add wave -noupdate /l0_dds_reader_test3_arzkrtu/uut/inst_opcode -add wave -noupdate /l0_dds_reader_test3_arzkrtu/uut/inst_op_done -add wave -noupdate /l0_dds_reader_test3_arzkrtu/uut/inst_stage -add wave -noupdate /l0_dds_reader_test3_arzkrtu/uut/inst_stage_next -add wave -noupdate /l0_dds_reader_test3_arzkrtu/uut/inst_cnt -add wave -noupdate -radix unsigned /l0_dds_reader_test3_arzkrtu/uut/inst_addr_base -add wave -noupdate /l0_dds_reader_test3_arzkrtu/uut/inst_mem_fields -add wave -noupdate -childformat {{/l0_dds_reader_test3_arzkrtu/uut/inst_data.key_hash -radix hexadecimal} {/l0_dds_reader_test3_arzkrtu/uut/inst_data.status_info -radix binary} {/l0_dds_reader_test3_arzkrtu/uut/inst_data.sample_cnt -radix unsigned} {/l0_dds_reader_test3_arzkrtu/uut/inst_data.disposed_gen_cnt -radix unsigned} {/l0_dds_reader_test3_arzkrtu/uut/inst_data.no_writers_gen_cnt -radix unsigned} {/l0_dds_reader_test3_arzkrtu/uut/inst_data.ignore_deadline -radix unsigned} {/l0_dds_reader_test3_arzkrtu/uut/inst_data.writer_bitmap -radix binary -childformat {{/l0_dds_reader_test3_arzkrtu/uut/inst_data.writer_bitmap(0) -radix binary -childformat {{/l0_dds_reader_test3_arzkrtu/uut/inst_data.writer_bitmap(0)(0) -radix binary} {/l0_dds_reader_test3_arzkrtu/uut/inst_data.writer_bitmap(0)(1) -radix binary} {/l0_dds_reader_test3_arzkrtu/uut/inst_data.writer_bitmap(0)(2) -radix binary} {/l0_dds_reader_test3_arzkrtu/uut/inst_data.writer_bitmap(0)(3) -radix binary} {/l0_dds_reader_test3_arzkrtu/uut/inst_data.writer_bitmap(0)(4) -radix binary} {/l0_dds_reader_test3_arzkrtu/uut/inst_data.writer_bitmap(0)(5) -radix binary} {/l0_dds_reader_test3_arzkrtu/uut/inst_data.writer_bitmap(0)(6) -radix binary} {/l0_dds_reader_test3_arzkrtu/uut/inst_data.writer_bitmap(0)(7) -radix binary} {/l0_dds_reader_test3_arzkrtu/uut/inst_data.writer_bitmap(0)(8) -radix binary} {/l0_dds_reader_test3_arzkrtu/uut/inst_data.writer_bitmap(0)(9) -radix binary} {/l0_dds_reader_test3_arzkrtu/uut/inst_data.writer_bitmap(0)(10) -radix binary} {/l0_dds_reader_test3_arzkrtu/uut/inst_data.writer_bitmap(0)(11) -radix binary} {/l0_dds_reader_test3_arzkrtu/uut/inst_data.writer_bitmap(0)(12) -radix binary} {/l0_dds_reader_test3_arzkrtu/uut/inst_data.writer_bitmap(0)(13) -radix binary} {/l0_dds_reader_test3_arzkrtu/uut/inst_data.writer_bitmap(0)(14) -radix binary} {/l0_dds_reader_test3_arzkrtu/uut/inst_data.writer_bitmap(0)(15) -radix binary} {/l0_dds_reader_test3_arzkrtu/uut/inst_data.writer_bitmap(0)(16) -radix binary} {/l0_dds_reader_test3_arzkrtu/uut/inst_data.writer_bitmap(0)(17) -radix binary} {/l0_dds_reader_test3_arzkrtu/uut/inst_data.writer_bitmap(0)(18) -radix binary} {/l0_dds_reader_test3_arzkrtu/uut/inst_data.writer_bitmap(0)(19) -radix binary} {/l0_dds_reader_test3_arzkrtu/uut/inst_data.writer_bitmap(0)(20) -radix binary} {/l0_dds_reader_test3_arzkrtu/uut/inst_data.writer_bitmap(0)(21) -radix binary} {/l0_dds_reader_test3_arzkrtu/uut/inst_data.writer_bitmap(0)(22) -radix binary} {/l0_dds_reader_test3_arzkrtu/uut/inst_data.writer_bitmap(0)(23) -radix binary} {/l0_dds_reader_test3_arzkrtu/uut/inst_data.writer_bitmap(0)(24) -radix binary} {/l0_dds_reader_test3_arzkrtu/uut/inst_data.writer_bitmap(0)(25) -radix binary} {/l0_dds_reader_test3_arzkrtu/uut/inst_data.writer_bitmap(0)(26) -radix binary} {/l0_dds_reader_test3_arzkrtu/uut/inst_data.writer_bitmap(0)(27) -radix binary} {/l0_dds_reader_test3_arzkrtu/uut/inst_data.writer_bitmap(0)(28) -radix binary} {/l0_dds_reader_test3_arzkrtu/uut/inst_data.writer_bitmap(0)(29) -radix binary} {/l0_dds_reader_test3_arzkrtu/uut/inst_data.writer_bitmap(0)(30) -radix binary} {/l0_dds_reader_test3_arzkrtu/uut/inst_data.writer_bitmap(0)(31) -radix binary}}}}}} -expand -subitemconfig {/l0_dds_reader_test3_arzkrtu/uut/inst_data.key_hash {-height 15 -radix hexadecimal} /l0_dds_reader_test3_arzkrtu/uut/inst_data.status_info {-height 15 -radix binary} /l0_dds_reader_test3_arzkrtu/uut/inst_data.sample_cnt {-height 15 -radix unsigned} /l0_dds_reader_test3_arzkrtu/uut/inst_data.disposed_gen_cnt {-height 15 -radix unsigned} /l0_dds_reader_test3_arzkrtu/uut/inst_data.no_writers_gen_cnt {-height 15 -radix unsigned} /l0_dds_reader_test3_arzkrtu/uut/inst_data.ignore_deadline {-height 15 -radix unsigned} /l0_dds_reader_test3_arzkrtu/uut/inst_data.writer_bitmap {-height 15 -radix binary -childformat {{/l0_dds_reader_test3_arzkrtu/uut/inst_data.writer_bitmap(0) -radix binary -childformat {{/l0_dds_reader_test3_arzkrtu/uut/inst_data.writer_bitmap(0)(0) -radix binary} {/l0_dds_reader_test3_arzkrtu/uut/inst_data.writer_bitmap(0)(1) -radix binary} {/l0_dds_reader_test3_arzkrtu/uut/inst_data.writer_bitmap(0)(2) -radix binary} {/l0_dds_reader_test3_arzkrtu/uut/inst_data.writer_bitmap(0)(3) -radix binary} {/l0_dds_reader_test3_arzkrtu/uut/inst_data.writer_bitmap(0)(4) -radix binary} {/l0_dds_reader_test3_arzkrtu/uut/inst_data.writer_bitmap(0)(5) -radix binary} {/l0_dds_reader_test3_arzkrtu/uut/inst_data.writer_bitmap(0)(6) -radix binary} {/l0_dds_reader_test3_arzkrtu/uut/inst_data.writer_bitmap(0)(7) -radix binary} {/l0_dds_reader_test3_arzkrtu/uut/inst_data.writer_bitmap(0)(8) -radix binary} {/l0_dds_reader_test3_arzkrtu/uut/inst_data.writer_bitmap(0)(9) -radix binary} {/l0_dds_reader_test3_arzkrtu/uut/inst_data.writer_bitmap(0)(10) -radix binary} {/l0_dds_reader_test3_arzkrtu/uut/inst_data.writer_bitmap(0)(11) -radix binary} {/l0_dds_reader_test3_arzkrtu/uut/inst_data.writer_bitmap(0)(12) -radix binary} {/l0_dds_reader_test3_arzkrtu/uut/inst_data.writer_bitmap(0)(13) -radix binary} {/l0_dds_reader_test3_arzkrtu/uut/inst_data.writer_bitmap(0)(14) -radix binary} {/l0_dds_reader_test3_arzkrtu/uut/inst_data.writer_bitmap(0)(15) -radix binary} {/l0_dds_reader_test3_arzkrtu/uut/inst_data.writer_bitmap(0)(16) -radix binary} {/l0_dds_reader_test3_arzkrtu/uut/inst_data.writer_bitmap(0)(17) -radix binary} {/l0_dds_reader_test3_arzkrtu/uut/inst_data.writer_bitmap(0)(18) -radix binary} {/l0_dds_reader_test3_arzkrtu/uut/inst_data.writer_bitmap(0)(19) -radix binary} {/l0_dds_reader_test3_arzkrtu/uut/inst_data.writer_bitmap(0)(20) -radix binary} {/l0_dds_reader_test3_arzkrtu/uut/inst_data.writer_bitmap(0)(21) -radix binary} {/l0_dds_reader_test3_arzkrtu/uut/inst_data.writer_bitmap(0)(22) -radix binary} {/l0_dds_reader_test3_arzkrtu/uut/inst_data.writer_bitmap(0)(23) -radix binary} {/l0_dds_reader_test3_arzkrtu/uut/inst_data.writer_bitmap(0)(24) -radix binary} {/l0_dds_reader_test3_arzkrtu/uut/inst_data.writer_bitmap(0)(25) -radix binary} {/l0_dds_reader_test3_arzkrtu/uut/inst_data.writer_bitmap(0)(26) -radix binary} {/l0_dds_reader_test3_arzkrtu/uut/inst_data.writer_bitmap(0)(27) -radix binary} {/l0_dds_reader_test3_arzkrtu/uut/inst_data.writer_bitmap(0)(28) -radix binary} {/l0_dds_reader_test3_arzkrtu/uut/inst_data.writer_bitmap(0)(29) -radix binary} {/l0_dds_reader_test3_arzkrtu/uut/inst_data.writer_bitmap(0)(30) -radix binary} {/l0_dds_reader_test3_arzkrtu/uut/inst_data.writer_bitmap(0)(31) -radix binary}}}}} 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/l0_dds_reader_test3_arzkrtu/uut/inst_data.writer_bitmap(0)(14) {-height 15 -radix binary} /l0_dds_reader_test3_arzkrtu/uut/inst_data.writer_bitmap(0)(15) {-height 15 -radix binary} /l0_dds_reader_test3_arzkrtu/uut/inst_data.writer_bitmap(0)(16) {-height 15 -radix binary} /l0_dds_reader_test3_arzkrtu/uut/inst_data.writer_bitmap(0)(17) {-height 15 -radix binary} /l0_dds_reader_test3_arzkrtu/uut/inst_data.writer_bitmap(0)(18) {-height 15 -radix binary} /l0_dds_reader_test3_arzkrtu/uut/inst_data.writer_bitmap(0)(19) {-height 15 -radix binary} /l0_dds_reader_test3_arzkrtu/uut/inst_data.writer_bitmap(0)(20) {-height 15 -radix binary} /l0_dds_reader_test3_arzkrtu/uut/inst_data.writer_bitmap(0)(21) {-height 15 -radix binary} /l0_dds_reader_test3_arzkrtu/uut/inst_data.writer_bitmap(0)(22) {-height 15 -radix binary} /l0_dds_reader_test3_arzkrtu/uut/inst_data.writer_bitmap(0)(23) {-height 15 -radix binary} /l0_dds_reader_test3_arzkrtu/uut/inst_data.writer_bitmap(0)(24) {-height 15 -radix binary} /l0_dds_reader_test3_arzkrtu/uut/inst_data.writer_bitmap(0)(25) {-height 15 -radix binary} /l0_dds_reader_test3_arzkrtu/uut/inst_data.writer_bitmap(0)(26) {-height 15 -radix binary} /l0_dds_reader_test3_arzkrtu/uut/inst_data.writer_bitmap(0)(27) {-height 15 -radix binary} /l0_dds_reader_test3_arzkrtu/uut/inst_data.writer_bitmap(0)(28) {-height 15 -radix binary} /l0_dds_reader_test3_arzkrtu/uut/inst_data.writer_bitmap(0)(29) {-height 15 -radix binary} /l0_dds_reader_test3_arzkrtu/uut/inst_data.writer_bitmap(0)(30) {-height 15 -radix binary} /l0_dds_reader_test3_arzkrtu/uut/inst_data.writer_bitmap(0)(31) {-height 15 -radix binary}} /l0_dds_reader_test3_arzkrtu/uut/inst_data -add wave -noupdate -radix unsigned /l0_dds_reader_test3_arzkrtu/uut/inst_next_addr_base -add wave -noupdate -radix unsigned /l0_dds_reader_test3_arzkrtu/uut/inst_prev_addr_base -add wave -noupdate /l0_dds_reader_test3_arzkrtu/uut/current_imf -add wave -noupdate /l0_dds_reader_test3_arzkrtu/uut/stale_inst_cnt -add wave -noupdate -divider POINTERS -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test3_arzkrtu/uut/empty_sample_list_head -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test3_arzkrtu/uut/empty_sample_list_tail -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test3_arzkrtu/uut/empty_payload_list_head -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test3_arzkrtu/uut/oldest_sample -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test3_arzkrtu/uut/newest_sample -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test3_arzkrtu/uut/inst_empty_head -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test3_arzkrtu/uut/inst_occupied_head -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test3_arzkrtu/uut/cur_sample -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test3_arzkrtu/uut/next_sample -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test3_arzkrtu/uut/prev_sample -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test3_arzkrtu/uut/cur_payload -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test3_arzkrtu/uut/next_payload -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test3_arzkrtu/uut/cur_inst -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test3_arzkrtu/uut/next_inst -add wave -noupdate -divider TESTBENCH -add wave -noupdate -group TESTBENCH /l0_dds_reader_test3_arzkrtu/dds_start -add wave -noupdate -group TESTBENCH /l0_dds_reader_test3_arzkrtu/dds_stage -add wave -noupdate -group TESTBENCH /l0_dds_reader_test3_arzkrtu/dds_cnt -add wave -noupdate -group TESTBENCH /l0_dds_reader_test3_arzkrtu/dds_cnt2 -add wave -noupdate -group TESTBENCH /l0_dds_reader_test3_arzkrtu/dds_done -add wave -noupdate -group TESTBENCH /l0_dds_reader_test3_arzkrtu/rtps_start -add wave -noupdate -group TESTBENCH /l0_dds_reader_test3_arzkrtu/rtps_stage -add wave -noupdate -group TESTBENCH /l0_dds_reader_test3_arzkrtu/rtps_cnt -add wave -noupdate -group TESTBENCH /l0_dds_reader_test3_arzkrtu/rtps_done -add wave -noupdate -divider {KEY HOLDER} -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test3_arzkrtu/uut/start_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test3_arzkrtu/uut/opcode_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test3_arzkrtu/uut/ack_kh -add wave -noupdate -group {KEY HOLDER} -radix hexadecimal /l0_dds_reader_test3_arzkrtu/uut/data_in_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test3_arzkrtu/uut/valid_in_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test3_arzkrtu/uut/ready_in_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test3_arzkrtu/uut/last_word_in_kh -add wave -noupdate -group {KEY HOLDER} -radix hexadecimal /l0_dds_reader_test3_arzkrtu/uut/data_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test3_arzkrtu/uut/valid_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test3_arzkrtu/uut/ready_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test3_arzkrtu/uut/last_word_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test3_arzkrtu/uut/abort_kh -add wave -noupdate -divider MISC -add wave -noupdate -radix unsigned /l0_dds_reader_test3_arzkrtu/uut/collection_cnt -add wave -noupdate -radix unsigned /l0_dds_reader_test3_arzkrtu/uut/collection_cnt_max -add wave -noupdate -radix unsigned /l0_dds_reader_test3_arzkrtu/uut/collection_generation_rank -add wave -noupdate -radix unsigned /l0_dds_reader_test3_arzkrtu/uut/cur_generation_rank -add wave -noupdate -radix unsigned /l0_dds_reader_test3_arzkrtu/uut/max_samples_latch -add wave -noupdate /l0_dds_reader_test3_arzkrtu/uut/dynamic_next_instance -add wave -noupdate /l0_dds_reader_test3_arzkrtu/uut/single_instance -add wave -noupdate /l0_dds_reader_test3_arzkrtu/uut/is_take -add wave -noupdate -radix unsigned /l0_dds_reader_test3_arzkrtu/uut/sel_sample -add wave -noupdate -radix unsigned /l0_dds_reader_test3_arzkrtu/uut/sample_p1 -add wave -noupdate -radix unsigned /l0_dds_reader_test3_arzkrtu/uut/sample_p2 -add wave -noupdate -radix SAMPLE_STATE /l0_dds_reader_test3_arzkrtu/uut/sample_state -add wave -noupdate -radix VIEW_STATE /l0_dds_reader_test3_arzkrtu/uut/view_state -add wave -noupdate -radix INSTANCE_STATE /l0_dds_reader_test3_arzkrtu/uut/instance_state -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {262408405 ps} 0} {{Cursor 2} {115175000 ps} 1} -quietly wave cursor active 1 -configure wave -namecolwidth 187 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -configure wave -timelineunits ns -update -WaveRestoreZoom {261834536 ps} {262835177 ps} diff --git a/sim/L0_dds_reader_test3_arzksto.do b/sim/L0_dds_reader_test3_arzksto.do deleted file mode 100644 index e42090b..0000000 --- a/sim/L0_dds_reader_test3_arzksto.do +++ /dev/null @@ -1,201 +0,0 @@ -onerror {resume} -radix define DDS_RETCODE { - "10#0#" "RETCODE_OK", - "10#1#" "RETCODE_ERROR", - "10#2#" "RETCODE_UNSUPPORTED", - "10#3#" "RETCODE_BAD_PARAMETER", - "10#4#" "RETCODE_PRECONDITION_NOT_MET", - "10#5#" "RETCODE_OUT_OF_RESOURCES", - "10#6#" "RETCODE_NOT_ENABLED", - "10#7#" "RETCODE_IMMUTABLE_POLICY", - "10#8#" "RETCODE_INCONSISTENT_POLICY", - "10#9#" "RETCODE_ALREADY_DELETED", - "10#10#" "RETCODE_TIMEOUT", - "10#11#" "RETCODE_NO_DATA", - "10#12#" "RETCODE_ILLEGAL_OPERATION", - -default unsigned -} -radix define SAMPLE_STATE { - "16#00000001#" "READ_SAMPLE_STATE", - "16#00000002#" "NOT_READ_SAMPLE_STATE", - "16#FFFFFFFF#" "ANY_SAMPLE_STATE", - -default binary -} -radix define VIEW_STATE { - "16#00000001#" "NEW_VIEW_STATE", - "16#00000002#" "NOT_NEW_VIEW_STATE", - "16#FFFFFFFF#" "ANY_VIEW_STATE", - -default binary -} -radix define INSTANCE_STATE { - "16#00000001#" "ALIVE_INSTANCE_STATE", - "16#00000002#" "NOT_ALIVE_DISPOSED_INSTANCE_STATE", - "16#00000004#" "NOT_ALIVE_NO_WRITERS_INSTANCE_STATE", - "16#FFFFFFFF#" "ANY_INSTANCE_STATE", - -default binary -} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -divider SYSTEM -add wave -noupdate /l0_dds_reader_test3_arzksto/uut/clk -add wave -noupdate /l0_dds_reader_test3_arzksto/uut/reset -add wave -noupdate -radix unsigned /l0_dds_reader_test3_arzksto/uut/time -add wave -noupdate -divider RTPS -add wave -noupdate -expand -group RTPS /l0_dds_reader_test3_arzksto/uut/start_rtps -add wave -noupdate -expand -group RTPS /l0_dds_reader_test3_arzksto/uut/opcode_rtps -add wave -noupdate -expand -group RTPS /l0_dds_reader_test3_arzksto/uut/ack_rtps -add wave -noupdate -expand -group RTPS /l0_dds_reader_test3_arzksto/uut/ret_rtps -add wave -noupdate -expand -group RTPS /l0_dds_reader_test3_arzksto/uut/done_rtps -add wave -noupdate -expand -group RTPS /l0_dds_reader_test3_arzksto/uut/ready_in_rtps -add wave -noupdate -expand -group RTPS /l0_dds_reader_test3_arzksto/uut/valid_in_rtps -add wave -noupdate -expand -group RTPS -radix hexadecimal /l0_dds_reader_test3_arzksto/uut/data_in_rtps -add wave -noupdate -expand -group RTPS /l0_dds_reader_test3_arzksto/uut/last_word_in_rtps -add wave -noupdate -divider DDS -add wave -noupdate -group DDS /l0_dds_reader_test3_arzksto/uut/start_dds -add wave -noupdate -group DDS /l0_dds_reader_test3_arzksto/uut/ack_dds -add wave -noupdate -group DDS /l0_dds_reader_test3_arzksto/uut/opcode_dds -add wave -noupdate -group DDS -radix SAMPLE_STATE /l0_dds_reader_test3_arzksto/uut/sample_state_dds -add wave -noupdate -group DDS -radix INSTANCE_STATE /l0_dds_reader_test3_arzksto/uut/instance_state_dds -add wave -noupdate -group DDS -radix VIEW_STATE /l0_dds_reader_test3_arzksto/uut/view_state_dds -add wave -noupdate -group DDS -radix hexadecimal /l0_dds_reader_test3_arzksto/uut/instance_handle_dds -add wave -noupdate -group DDS -radix unsigned /l0_dds_reader_test3_arzksto/uut/max_samples_dds -add wave -noupdate -group DDS -radix DDS_RETCODE /l0_dds_reader_test3_arzksto/uut/return_code_dds -add wave -noupdate -group DDS /l0_dds_reader_test3_arzksto/uut/done_dds -add wave -noupdate -group DDS -divider SI -add wave -noupdate -group DDS -radix SAMPLE_STATE /l0_dds_reader_test3_arzksto/uut/si_sample_state -add wave -noupdate -group DDS -radix VIEW_STATE /l0_dds_reader_test3_arzksto/uut/si_view_state -add wave -noupdate -group DDS -radix INSTANCE_STATE /l0_dds_reader_test3_arzksto/uut/si_instance_state -add wave -noupdate -group DDS -radix unsigned /l0_dds_reader_test3_arzksto/uut/si_source_timestamp -add wave -noupdate -group DDS -radix hexadecimal /l0_dds_reader_test3_arzksto/uut/si_instance_handle -add wave -noupdate -group DDS -radix hexadecimal /l0_dds_reader_test3_arzksto/uut/si_publication_handle -add wave -noupdate -group DDS -radix unsigned /l0_dds_reader_test3_arzksto/uut/si_disposed_generation_count -add wave -noupdate -group DDS -radix unsigned /l0_dds_reader_test3_arzksto/uut/si_no_writers_generation_count -add wave -noupdate -group DDS -radix unsigned /l0_dds_reader_test3_arzksto/uut/si_sample_rank -add wave -noupdate -group DDS -radix unsigned /l0_dds_reader_test3_arzksto/uut/si_generation_rank -add wave -noupdate -group DDS -radix unsigned /l0_dds_reader_test3_arzksto/uut/si_absolute_generation_rank -add wave -noupdate -group DDS /l0_dds_reader_test3_arzksto/uut/si_valid_data -add wave -noupdate -group DDS /l0_dds_reader_test3_arzksto/uut/si_valid -add wave -noupdate -group DDS /l0_dds_reader_test3_arzksto/uut/get_data_dds -add wave -noupdate -group DDS /l0_dds_reader_test3_arzksto/uut/eoc -add wave -noupdate -group DDS -divider OUTPUT -add wave -noupdate -group DDS /l0_dds_reader_test3_arzksto/uut/ready_out_dds -add wave -noupdate -group DDS /l0_dds_reader_test3_arzksto/uut/valid_out_dds -add wave -noupdate -group DDS -radix hexadecimal /l0_dds_reader_test3_arzksto/uut/data_out_dds -add wave -noupdate -group DDS /l0_dds_reader_test3_arzksto/uut/last_word_out_dds -add wave -noupdate -divider {MAIN FSM} -add wave -noupdate /l0_dds_reader_test3_arzksto/uut/stage -add wave -noupdate /l0_dds_reader_test3_arzksto/uut/stage_next -add wave -noupdate /l0_dds_reader_test3_arzksto/uut/cnt -add wave -noupdate -divider MEMORY -add wave -noupdate -expand -group {SAMPLE MEM} /l0_dds_reader_test3_arzksto/uut/sample_abort_read -add wave -noupdate -expand -group {SAMPLE MEM} -radix unsigned /l0_dds_reader_test3_arzksto/uut/sample_mem_ctrl_inst/addr -add wave -noupdate -expand -group {SAMPLE MEM} /l0_dds_reader_test3_arzksto/uut/sample_mem_ctrl_inst/read -add wave -noupdate -expand -group {SAMPLE MEM} /l0_dds_reader_test3_arzksto/uut/sample_mem_ctrl_inst/ready_in -add wave -noupdate -expand -group {SAMPLE MEM} /l0_dds_reader_test3_arzksto/uut/sample_mem_ctrl_inst/valid_in -add wave -noupdate -expand -group {SAMPLE MEM} -radix hexadecimal /l0_dds_reader_test3_arzksto/uut/sample_mem_ctrl_inst/data_in -add wave -noupdate -expand -group {SAMPLE MEM} /l0_dds_reader_test3_arzksto/uut/sample_mem_ctrl_inst/ready_out -add wave -noupdate -expand -group {SAMPLE MEM} /l0_dds_reader_test3_arzksto/uut/sample_mem_ctrl_inst/valid_out -add wave -noupdate -expand -group {SAMPLE MEM} -radix hexadecimal /l0_dds_reader_test3_arzksto/uut/sample_mem_ctrl_inst/data_out -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test3_arzksto/uut/payload_abort_read -add wave -noupdate -group {PAYLOAD MEM} -radix unsigned /l0_dds_reader_test3_arzksto/uut/payload_mem_ctrl_inst/addr -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test3_arzksto/uut/payload_mem_ctrl_inst/read -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test3_arzksto/uut/payload_mem_ctrl_inst/ready_in -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test3_arzksto/uut/payload_mem_ctrl_inst/valid_in -add wave -noupdate -group {PAYLOAD MEM} -radix hexadecimal /l0_dds_reader_test3_arzksto/uut/payload_mem_ctrl_inst/data_in -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test3_arzksto/uut/payload_mem_ctrl_inst/ready_out -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test3_arzksto/uut/payload_mem_ctrl_inst/valid_out -add wave -noupdate -group {PAYLOAD MEM} -radix hexadecimal /l0_dds_reader_test3_arzksto/uut/payload_mem_ctrl_inst/data_out -add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test3_arzksto/uut/inst_abort_read -add wave -noupdate -group {INSTANCE MEM} -radix unsigned /l0_dds_reader_test3_arzksto/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/addr -add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test3_arzksto/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/read -add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test3_arzksto/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/ready_in -add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test3_arzksto/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/valid_in -add wave -noupdate -group {INSTANCE MEM} -radix hexadecimal /l0_dds_reader_test3_arzksto/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/data_in -add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test3_arzksto/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/ready_out -add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test3_arzksto/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/valid_out -add wave -noupdate -group {INSTANCE MEM} -radix hexadecimal /l0_dds_reader_test3_arzksto/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/data_out -add wave -noupdate /l0_dds_reader_test3_arzksto/uut/inst_op_start -add wave -noupdate /l0_dds_reader_test3_arzksto/uut/inst_opcode -add wave -noupdate /l0_dds_reader_test3_arzksto/uut/inst_op_done -add wave -noupdate /l0_dds_reader_test3_arzksto/uut/inst_stage -add wave -noupdate /l0_dds_reader_test3_arzksto/uut/inst_stage_next -add wave -noupdate /l0_dds_reader_test3_arzksto/uut/inst_cnt -add wave -noupdate -radix unsigned /l0_dds_reader_test3_arzksto/uut/inst_addr_base -add wave -noupdate /l0_dds_reader_test3_arzksto/uut/inst_mem_fields -add wave -noupdate -childformat {{/l0_dds_reader_test3_arzksto/uut/inst_data.key_hash -radix hexadecimal} {/l0_dds_reader_test3_arzksto/uut/inst_data.status_info -radix binary} {/l0_dds_reader_test3_arzksto/uut/inst_data.sample_cnt -radix unsigned} {/l0_dds_reader_test3_arzksto/uut/inst_data.disposed_gen_cnt -radix unsigned} {/l0_dds_reader_test3_arzksto/uut/inst_data.no_writers_gen_cnt -radix unsigned} {/l0_dds_reader_test3_arzksto/uut/inst_data.ignore_deadline -radix unsigned} {/l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap -radix binary -childformat {{/l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0) -radix binary -childformat {{/l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(0) -radix binary} {/l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(1) -radix binary} {/l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(2) -radix binary} {/l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(3) -radix binary} {/l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(4) -radix binary} {/l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(5) -radix binary} {/l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(6) -radix binary} {/l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(7) -radix binary} {/l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(8) -radix binary} {/l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(9) -radix binary} {/l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(10) -radix binary} {/l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(11) -radix binary} {/l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(12) -radix binary} {/l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(13) -radix binary} {/l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(14) -radix binary} {/l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(15) -radix binary} {/l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(16) -radix binary} {/l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(17) -radix binary} {/l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(18) -radix binary} {/l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(19) -radix binary} {/l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(20) -radix binary} {/l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(21) -radix binary} {/l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(22) -radix binary} {/l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(23) -radix binary} {/l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(24) -radix binary} {/l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(25) -radix binary} {/l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(26) -radix binary} {/l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(27) -radix binary} {/l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(28) -radix binary} {/l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(29) -radix binary} {/l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(30) -radix binary} {/l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(31) -radix binary}}}}}} -expand -subitemconfig {/l0_dds_reader_test3_arzksto/uut/inst_data.key_hash {-height 15 -radix hexadecimal} /l0_dds_reader_test3_arzksto/uut/inst_data.status_info {-height 15 -radix binary} /l0_dds_reader_test3_arzksto/uut/inst_data.sample_cnt {-height 15 -radix unsigned} /l0_dds_reader_test3_arzksto/uut/inst_data.disposed_gen_cnt {-height 15 -radix unsigned} /l0_dds_reader_test3_arzksto/uut/inst_data.no_writers_gen_cnt {-height 15 -radix unsigned} /l0_dds_reader_test3_arzksto/uut/inst_data.ignore_deadline {-height 15 -radix unsigned} /l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap {-height 15 -radix binary -childformat {{/l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0) -radix binary -childformat {{/l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(0) -radix binary} {/l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(1) -radix binary} {/l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(2) -radix binary} {/l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(3) -radix binary} {/l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(4) -radix binary} {/l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(5) -radix binary} {/l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(6) -radix binary} {/l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(7) -radix binary} {/l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(8) -radix binary} {/l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(9) -radix binary} {/l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(10) -radix binary} {/l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(11) -radix binary} {/l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(12) -radix binary} {/l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(13) -radix binary} {/l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(14) -radix binary} {/l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(15) -radix binary} {/l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(16) -radix binary} {/l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(17) -radix binary} {/l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(18) -radix binary} {/l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(19) -radix binary} {/l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(20) -radix binary} {/l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(21) -radix binary} {/l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(22) -radix binary} {/l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(23) -radix binary} {/l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(24) -radix binary} {/l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(25) -radix binary} {/l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(26) -radix binary} {/l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(27) -radix binary} {/l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(28) -radix binary} {/l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(29) -radix binary} {/l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(30) -radix binary} {/l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(31) -radix binary}}}}} /l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0) {-height 15 -radix binary -childformat {{/l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(0) -radix binary} {/l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(1) -radix binary} {/l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(2) -radix binary} {/l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(3) -radix binary} {/l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(4) -radix binary} {/l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(5) -radix binary} {/l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(6) -radix binary} {/l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(7) -radix binary} {/l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(8) -radix binary} {/l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(9) -radix binary} {/l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(10) -radix binary} {/l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(11) -radix binary} {/l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(12) -radix binary} {/l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(13) -radix binary} {/l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(14) -radix binary} {/l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(15) -radix binary} {/l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(16) -radix binary} {/l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(17) -radix binary} {/l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(18) -radix binary} {/l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(19) -radix binary} {/l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(20) -radix binary} {/l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(21) -radix binary} {/l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(22) -radix binary} {/l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(23) -radix binary} {/l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(24) -radix binary} {/l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(25) -radix binary} {/l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(26) -radix binary} {/l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(27) -radix binary} {/l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(28) -radix binary} {/l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(29) -radix binary} {/l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(30) -radix binary} {/l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(31) -radix binary}}} /l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(0) {-height 15 -radix binary} /l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(1) {-height 15 -radix binary} /l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(2) {-height 15 -radix binary} /l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(3) {-height 15 -radix binary} /l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(4) {-height 15 -radix binary} /l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(5) {-height 15 -radix binary} /l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(6) {-height 15 -radix binary} /l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(7) {-height 15 -radix binary} /l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(8) {-height 15 -radix binary} /l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(9) {-height 15 -radix binary} /l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(10) {-height 15 -radix binary} /l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(11) {-height 15 -radix binary} /l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(12) {-height 15 -radix binary} /l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(13) {-height 15 -radix binary} /l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(14) {-height 15 -radix binary} /l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(15) {-height 15 -radix binary} /l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(16) {-height 15 -radix binary} /l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(17) {-height 15 -radix binary} /l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(18) {-height 15 -radix binary} /l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(19) {-height 15 -radix binary} /l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(20) {-height 15 -radix binary} /l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(21) {-height 15 -radix binary} /l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(22) {-height 15 -radix binary} /l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(23) {-height 15 -radix binary} /l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(24) {-height 15 -radix binary} /l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(25) {-height 15 -radix binary} /l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(26) {-height 15 -radix binary} /l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(27) {-height 15 -radix binary} /l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(28) {-height 15 -radix binary} /l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(29) {-height 15 -radix binary} /l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(30) {-height 15 -radix binary} /l0_dds_reader_test3_arzksto/uut/inst_data.writer_bitmap(0)(31) {-height 15 -radix binary}} /l0_dds_reader_test3_arzksto/uut/inst_data -add wave -noupdate -radix unsigned /l0_dds_reader_test3_arzksto/uut/inst_next_addr_base -add wave -noupdate -radix unsigned /l0_dds_reader_test3_arzksto/uut/inst_prev_addr_base -add wave -noupdate /l0_dds_reader_test3_arzksto/uut/current_imf -add wave -noupdate /l0_dds_reader_test3_arzksto/uut/stale_inst_cnt -add wave -noupdate -divider MISC -add wave -noupdate /l0_dds_reader_test3_arzksto/uut/newer_inst_sample -add wave -noupdate -radix unsigned /l0_dds_reader_test3_arzksto/uut/ts_latch -add wave -noupdate -radix unsigned /l0_dds_reader_test3_arzksto/uut/collection_cnt -add wave -noupdate -radix unsigned /l0_dds_reader_test3_arzksto/uut/collection_cnt_max -add wave -noupdate -radix unsigned /l0_dds_reader_test3_arzksto/uut/collection_generation_rank -add wave -noupdate -radix unsigned /l0_dds_reader_test3_arzksto/uut/cur_generation_rank -add wave -noupdate -radix unsigned /l0_dds_reader_test3_arzksto/uut/max_samples_latch -add wave -noupdate /l0_dds_reader_test3_arzksto/uut/dynamic_next_instance -add wave -noupdate /l0_dds_reader_test3_arzksto/uut/single_instance -add wave -noupdate /l0_dds_reader_test3_arzksto/uut/is_take -add wave -noupdate -radix unsigned /l0_dds_reader_test3_arzksto/uut/sel_sample -add wave -noupdate -radix unsigned /l0_dds_reader_test3_arzksto/uut/sample_p1 -add wave -noupdate -radix unsigned /l0_dds_reader_test3_arzksto/uut/sample_p2 -add wave -noupdate -radix SAMPLE_STATE /l0_dds_reader_test3_arzksto/uut/sample_state -add wave -noupdate -radix VIEW_STATE /l0_dds_reader_test3_arzksto/uut/view_state -add wave -noupdate -radix INSTANCE_STATE /l0_dds_reader_test3_arzksto/uut/instance_state -add wave -noupdate -divider POINTERS -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test3_arzksto/uut/empty_sample_list_head -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test3_arzksto/uut/empty_sample_list_tail -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test3_arzksto/uut/empty_payload_list_head -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test3_arzksto/uut/oldest_sample -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test3_arzksto/uut/newest_sample -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test3_arzksto/uut/inst_empty_head -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test3_arzksto/uut/inst_occupied_head -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test3_arzksto/uut/cur_sample -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test3_arzksto/uut/next_sample -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test3_arzksto/uut/prev_sample -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test3_arzksto/uut/cur_payload -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test3_arzksto/uut/next_payload -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test3_arzksto/uut/cur_inst -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test3_arzksto/uut/next_inst -add wave -noupdate -divider TESTBENCH -add wave -noupdate -group TESTBENCH /l0_dds_reader_test3_arzksto/dds_start -add wave -noupdate -group TESTBENCH /l0_dds_reader_test3_arzksto/dds_stage -add wave -noupdate -group TESTBENCH /l0_dds_reader_test3_arzksto/dds_cnt -add wave -noupdate -group TESTBENCH /l0_dds_reader_test3_arzksto/dds_cnt2 -add wave -noupdate -group TESTBENCH /l0_dds_reader_test3_arzksto/dds_done -add wave -noupdate -group TESTBENCH /l0_dds_reader_test3_arzksto/rtps_start -add wave -noupdate -group TESTBENCH /l0_dds_reader_test3_arzksto/rtps_stage -add wave -noupdate -group TESTBENCH /l0_dds_reader_test3_arzksto/rtps_cnt -add wave -noupdate -group TESTBENCH /l0_dds_reader_test3_arzksto/rtps_done -add wave -noupdate -divider {KEY HOLDER} -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test3_arzksto/uut/start_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test3_arzksto/uut/opcode_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test3_arzksto/uut/ack_kh -add wave -noupdate -group {KEY HOLDER} -radix hexadecimal /l0_dds_reader_test3_arzksto/uut/data_in_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test3_arzksto/uut/valid_in_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test3_arzksto/uut/ready_in_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test3_arzksto/uut/last_word_in_kh -add wave -noupdate -group {KEY HOLDER} -radix hexadecimal /l0_dds_reader_test3_arzksto/uut/data_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test3_arzksto/uut/valid_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test3_arzksto/uut/ready_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test3_arzksto/uut/last_word_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test3_arzksto/uut/abort_kh -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {6799706 ps} 0} {{Cursor 2} {115175000 ps} 1} -quietly wave cursor active 1 -configure wave -namecolwidth 187 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -configure wave -timelineunits ns -update -WaveRestoreZoom {6126088 ps} {7126729 ps} diff --git a/sim/L0_dds_reader_test3_arznriu.do b/sim/L0_dds_reader_test3_arznriu.do deleted file mode 100644 index 9daf1cc..0000000 --- a/sim/L0_dds_reader_test3_arznriu.do +++ /dev/null @@ -1,178 +0,0 @@ -onerror {resume} -radix define DDS_RETCODE { - "10#0#" "RETCODE_OK", - "10#1#" "RETCODE_ERROR", - "10#2#" "RETCODE_UNSUPPORTED", - "10#3#" "RETCODE_BAD_PARAMETER", - "10#4#" "RETCODE_PRECONDITION_NOT_MET", - "10#5#" "RETCODE_OUT_OF_RESOURCES", - "10#6#" "RETCODE_NOT_ENABLED", - "10#7#" "RETCODE_IMMUTABLE_POLICY", - "10#8#" "RETCODE_INCONSISTENT_POLICY", - "10#9#" "RETCODE_ALREADY_DELETED", - "10#10#" "RETCODE_TIMEOUT", - "10#11#" "RETCODE_NO_DATA", - "10#12#" "RETCODE_ILLEGAL_OPERATION", - -default unsigned -} -radix define SAMPLE_STATE { - "16#00000001#" "READ_SAMPLE_STATE", - "16#00000002#" "NOT_READ_SAMPLE_STATE", - "16#FFFFFFFF#" "ANY_SAMPLE_STATE", - -default binary -} -radix define VIEW_STATE { - "16#00000001#" "NEW_VIEW_STATE", - "16#00000002#" "NOT_NEW_VIEW_STATE", - "16#FFFFFFFF#" "ANY_VIEW_STATE", - -default binary -} -radix define INSTANCE_STATE { - "16#00000001#" "ALIVE_INSTANCE_STATE", - "16#00000002#" "NOT_ALIVE_DISPOSED_INSTANCE_STATE", - "16#00000004#" "NOT_ALIVE_NO_WRITERS_INSTANCE_STATE", - "16#FFFFFFFF#" "ANY_INSTANCE_STATE", - -default binary -} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -divider SYSTEM -add wave -noupdate /l0_dds_reader_test3_arznriu/uut/clk -add wave -noupdate /l0_dds_reader_test3_arznriu/uut/reset -add wave -noupdate -radix unsigned /l0_dds_reader_test3_arznriu/uut/time -add wave -noupdate -divider RTPS -add wave -noupdate -group RTPS /l0_dds_reader_test3_arznriu/uut/start_rtps -add wave -noupdate -group RTPS /l0_dds_reader_test3_arznriu/uut/opcode_rtps -add wave -noupdate -group RTPS /l0_dds_reader_test3_arznriu/uut/ack_rtps -add wave -noupdate -group RTPS /l0_dds_reader_test3_arznriu/uut/ret_rtps -add wave -noupdate -group RTPS /l0_dds_reader_test3_arznriu/uut/done_rtps -add wave -noupdate -group RTPS /l0_dds_reader_test3_arznriu/uut/ready_in_rtps -add wave -noupdate -group RTPS /l0_dds_reader_test3_arznriu/uut/valid_in_rtps -add wave -noupdate -group RTPS -radix hexadecimal /l0_dds_reader_test3_arznriu/uut/data_in_rtps -add wave -noupdate -group RTPS /l0_dds_reader_test3_arznriu/uut/last_word_in_rtps -add wave -noupdate -divider DDS -add wave -noupdate -expand -group DDS /l0_dds_reader_test3_arznriu/uut/start_dds -add wave -noupdate -expand -group DDS /l0_dds_reader_test3_arznriu/uut/ack_dds -add wave -noupdate -expand -group DDS /l0_dds_reader_test3_arznriu/uut/opcode_dds -add wave -noupdate -expand -group DDS -radix SAMPLE_STATE /l0_dds_reader_test3_arznriu/uut/sample_state_dds -add wave -noupdate -expand -group DDS -radix INSTANCE_STATE /l0_dds_reader_test3_arznriu/uut/instance_state_dds -add wave -noupdate -expand -group DDS -radix VIEW_STATE /l0_dds_reader_test3_arznriu/uut/view_state_dds -add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_reader_test3_arznriu/uut/instance_handle_dds -add wave -noupdate -expand -group DDS -radix unsigned /l0_dds_reader_test3_arznriu/uut/max_samples_dds -add wave -noupdate -expand -group DDS -radix DDS_RETCODE /l0_dds_reader_test3_arznriu/uut/return_code_dds -add wave -noupdate -expand -group DDS /l0_dds_reader_test3_arznriu/uut/done_dds -add wave -noupdate -expand -group DDS -divider SI -add wave -noupdate -expand -group DDS -radix SAMPLE_STATE /l0_dds_reader_test3_arznriu/uut/si_sample_state -add wave -noupdate -expand -group DDS -radix VIEW_STATE /l0_dds_reader_test3_arznriu/uut/si_view_state -add wave -noupdate -expand -group DDS -radix INSTANCE_STATE /l0_dds_reader_test3_arznriu/uut/si_instance_state -add wave -noupdate -expand -group DDS -radix unsigned /l0_dds_reader_test3_arznriu/uut/si_source_timestamp -add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_reader_test3_arznriu/uut/si_instance_handle -add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_reader_test3_arznriu/uut/si_publication_handle -add wave -noupdate -expand -group DDS -radix unsigned /l0_dds_reader_test3_arznriu/uut/si_disposed_generation_count -add wave -noupdate -expand -group DDS -radix unsigned /l0_dds_reader_test3_arznriu/uut/si_no_writers_generation_count -add wave -noupdate -expand -group DDS -radix unsigned /l0_dds_reader_test3_arznriu/uut/si_sample_rank -add wave -noupdate -expand -group DDS -radix unsigned /l0_dds_reader_test3_arznriu/uut/si_generation_rank -add wave -noupdate -expand -group DDS -radix unsigned /l0_dds_reader_test3_arznriu/uut/si_absolute_generation_rank -add wave -noupdate -expand -group DDS /l0_dds_reader_test3_arznriu/uut/si_valid_data -add wave -noupdate -expand -group DDS /l0_dds_reader_test3_arznriu/uut/si_valid -add wave -noupdate -expand -group DDS /l0_dds_reader_test3_arznriu/uut/get_data_dds -add wave -noupdate -expand -group DDS /l0_dds_reader_test3_arznriu/uut/eoc -add wave -noupdate -expand -group DDS -divider OUTPUT -add wave -noupdate -expand -group DDS /l0_dds_reader_test3_arznriu/uut/ready_out_dds -add wave -noupdate -expand -group DDS /l0_dds_reader_test3_arznriu/uut/valid_out_dds -add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_reader_test3_arznriu/uut/data_out_dds -add wave -noupdate -expand -group DDS /l0_dds_reader_test3_arznriu/uut/last_word_out_dds -add wave -noupdate -divider {MAIN FSM} -add wave -noupdate /l0_dds_reader_test3_arznriu/uut/stage -add wave -noupdate /l0_dds_reader_test3_arznriu/uut/stage_next -add wave -noupdate /l0_dds_reader_test3_arznriu/uut/cnt -add wave -noupdate -divider MEMORY -add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test3_arznriu/uut/sample_abort_read -add wave -noupdate -group {SAMPLE MEM} -radix unsigned /l0_dds_reader_test3_arznriu/uut/sample_mem_ctrl_inst/addr -add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test3_arznriu/uut/sample_mem_ctrl_inst/read -add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test3_arznriu/uut/sample_mem_ctrl_inst/ready_in -add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test3_arznriu/uut/sample_mem_ctrl_inst/valid_in -add wave -noupdate -group {SAMPLE MEM} -radix hexadecimal /l0_dds_reader_test3_arznriu/uut/sample_mem_ctrl_inst/data_in -add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test3_arznriu/uut/sample_mem_ctrl_inst/ready_out -add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test3_arznriu/uut/sample_mem_ctrl_inst/valid_out -add wave -noupdate -group {SAMPLE MEM} -radix hexadecimal /l0_dds_reader_test3_arznriu/uut/sample_mem_ctrl_inst/data_out -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test3_arznriu/uut/payload_abort_read -add wave -noupdate -group {PAYLOAD MEM} -radix unsigned /l0_dds_reader_test3_arznriu/uut/payload_mem_ctrl_inst/addr -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test3_arznriu/uut/payload_mem_ctrl_inst/read -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test3_arznriu/uut/payload_mem_ctrl_inst/ready_in -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test3_arznriu/uut/payload_mem_ctrl_inst/valid_in -add wave -noupdate -group {PAYLOAD MEM} -radix hexadecimal /l0_dds_reader_test3_arznriu/uut/payload_mem_ctrl_inst/data_in -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test3_arznriu/uut/payload_mem_ctrl_inst/ready_out -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test3_arznriu/uut/payload_mem_ctrl_inst/valid_out -add wave -noupdate -group {PAYLOAD MEM} -radix hexadecimal /l0_dds_reader_test3_arznriu/uut/payload_mem_ctrl_inst/data_out -add wave -noupdate -childformat {{/l0_dds_reader_test3_arznriu/uut/inst_data.key_hash -radix hexadecimal} {/l0_dds_reader_test3_arznriu/uut/inst_data.status_info -radix binary} {/l0_dds_reader_test3_arznriu/uut/inst_data.sample_cnt -radix unsigned} {/l0_dds_reader_test3_arznriu/uut/inst_data.disposed_gen_cnt -radix unsigned} {/l0_dds_reader_test3_arznriu/uut/inst_data.no_writers_gen_cnt -radix unsigned} {/l0_dds_reader_test3_arznriu/uut/inst_data.ignore_deadline -radix unsigned} {/l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap -radix binary -childformat {{/l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0) -radix binary -childformat {{/l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(0) -radix binary} {/l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(1) -radix binary} {/l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(2) -radix binary} {/l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(3) -radix binary} {/l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(4) -radix binary} {/l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(5) -radix binary} {/l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(6) -radix binary} {/l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(7) -radix binary} {/l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(8) -radix binary} {/l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(9) -radix binary} {/l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(10) -radix binary} {/l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(11) -radix binary} {/l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(12) -radix binary} {/l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(13) -radix binary} {/l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(14) -radix binary} {/l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(15) -radix binary} {/l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(16) -radix binary} {/l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(17) -radix binary} {/l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(18) -radix binary} {/l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(19) -radix binary} {/l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(20) -radix binary} {/l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(21) -radix binary} {/l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(22) -radix binary} {/l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(23) -radix binary} {/l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(24) -radix binary} {/l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(25) -radix binary} {/l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(26) -radix binary} {/l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(27) -radix binary} {/l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(28) -radix binary} {/l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(29) -radix binary} {/l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(30) -radix binary} {/l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(31) -radix binary}}}}}} -expand -subitemconfig {/l0_dds_reader_test3_arznriu/uut/inst_data.key_hash {-height 15 -radix hexadecimal} /l0_dds_reader_test3_arznriu/uut/inst_data.status_info {-height 15 -radix binary} /l0_dds_reader_test3_arznriu/uut/inst_data.sample_cnt {-height 15 -radix unsigned} /l0_dds_reader_test3_arznriu/uut/inst_data.disposed_gen_cnt {-height 15 -radix unsigned} /l0_dds_reader_test3_arznriu/uut/inst_data.no_writers_gen_cnt {-height 15 -radix unsigned} /l0_dds_reader_test3_arznriu/uut/inst_data.ignore_deadline {-height 15 -radix unsigned} /l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap {-height 15 -radix binary -childformat {{/l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0) -radix binary -childformat {{/l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(0) -radix binary} {/l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(1) -radix binary} {/l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(2) -radix binary} {/l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(3) -radix binary} {/l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(4) -radix binary} {/l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(5) -radix binary} {/l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(6) -radix binary} {/l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(7) -radix binary} {/l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(8) -radix binary} {/l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(9) -radix binary} {/l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(10) -radix binary} {/l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(11) -radix binary} {/l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(12) -radix binary} {/l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(13) -radix binary} {/l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(14) -radix binary} {/l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(15) -radix binary} {/l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(16) -radix binary} {/l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(17) -radix binary} {/l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(18) -radix binary} {/l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(19) -radix binary} {/l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(20) -radix binary} {/l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(21) -radix binary} {/l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(22) -radix binary} {/l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(23) -radix binary} {/l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(24) -radix binary} {/l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(25) -radix binary} {/l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(26) -radix binary} {/l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(27) -radix binary} {/l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(28) -radix binary} {/l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(29) -radix binary} {/l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(30) -radix binary} {/l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(31) -radix binary}}}}} /l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0) {-height 15 -radix binary -childformat {{/l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(0) -radix binary} {/l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(1) -radix binary} {/l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(2) -radix binary} {/l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(3) -radix binary} {/l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(4) -radix binary} {/l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(5) -radix binary} {/l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(6) -radix binary} {/l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(7) -radix binary} {/l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(8) -radix binary} {/l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(9) -radix binary} {/l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(10) -radix binary} {/l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(11) -radix binary} {/l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(12) -radix binary} {/l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(13) -radix binary} {/l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(14) -radix binary} {/l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(15) -radix binary} {/l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(16) -radix binary} {/l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(17) -radix binary} {/l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(18) -radix binary} {/l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(19) -radix binary} {/l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(20) -radix binary} {/l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(21) -radix binary} {/l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(22) -radix binary} {/l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(23) -radix binary} {/l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(24) -radix binary} {/l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(25) -radix binary} {/l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(26) -radix binary} {/l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(27) -radix binary} {/l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(28) -radix binary} {/l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(29) -radix binary} {/l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(30) -radix binary} {/l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(31) -radix binary}}} /l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(0) {-height 15 -radix binary} /l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(1) {-height 15 -radix binary} /l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(2) {-height 15 -radix binary} /l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(3) {-height 15 -radix binary} /l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(4) {-height 15 -radix binary} /l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(5) {-height 15 -radix binary} /l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(6) {-height 15 -radix binary} /l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(7) {-height 15 -radix binary} /l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(8) {-height 15 -radix binary} /l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(9) {-height 15 -radix binary} /l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(10) {-height 15 -radix binary} /l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(11) {-height 15 -radix binary} /l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(12) {-height 15 -radix binary} /l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(13) {-height 15 -radix binary} /l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(14) {-height 15 -radix binary} /l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(15) {-height 15 -radix binary} /l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(16) {-height 15 -radix binary} /l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(17) {-height 15 -radix binary} /l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(18) {-height 15 -radix binary} /l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(19) {-height 15 -radix binary} /l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(20) {-height 15 -radix binary} /l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(21) {-height 15 -radix binary} /l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(22) {-height 15 -radix binary} /l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(23) {-height 15 -radix binary} /l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(24) {-height 15 -radix binary} /l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(25) {-height 15 -radix binary} /l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(26) {-height 15 -radix binary} /l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(27) {-height 15 -radix binary} /l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(28) {-height 15 -radix binary} /l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(29) {-height 15 -radix binary} /l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(30) {-height 15 -radix binary} /l0_dds_reader_test3_arznriu/uut/inst_data.writer_bitmap(0)(31) {-height 15 -radix binary}} /l0_dds_reader_test3_arznriu/uut/inst_data -add wave -noupdate -divider POINTERS -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test3_arznriu/uut/empty_sample_list_head -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test3_arznriu/uut/empty_sample_list_tail -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test3_arznriu/uut/empty_payload_list_head -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test3_arznriu/uut/oldest_sample -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test3_arznriu/uut/newest_sample -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test3_arznriu/uut/inst_empty_head -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test3_arznriu/uut/inst_occupied_head -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test3_arznriu/uut/cur_sample -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test3_arznriu/uut/next_sample -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test3_arznriu/uut/prev_sample -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test3_arznriu/uut/cur_payload -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test3_arznriu/uut/next_payload -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test3_arznriu/uut/cur_inst -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test3_arznriu/uut/next_inst -add wave -noupdate -divider TESTBENCH -add wave -noupdate -group TESTBENCH /l0_dds_reader_test3_arznriu/dds_start -add wave -noupdate -group TESTBENCH /l0_dds_reader_test3_arznriu/dds_stage -add wave -noupdate -group TESTBENCH /l0_dds_reader_test3_arznriu/dds_cnt -add wave -noupdate -group TESTBENCH /l0_dds_reader_test3_arznriu/dds_cnt2 -add wave -noupdate -group TESTBENCH /l0_dds_reader_test3_arznriu/dds_done -add wave -noupdate -group TESTBENCH /l0_dds_reader_test3_arznriu/rtps_start -add wave -noupdate -group TESTBENCH /l0_dds_reader_test3_arznriu/rtps_stage -add wave -noupdate -group TESTBENCH /l0_dds_reader_test3_arznriu/rtps_cnt -add wave -noupdate -group TESTBENCH /l0_dds_reader_test3_arznriu/rtps_done -add wave -noupdate -divider {KEY HOLDER} -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test3_arznriu/uut/start_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test3_arznriu/uut/opcode_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test3_arznriu/uut/ack_kh -add wave -noupdate -group {KEY HOLDER} -radix hexadecimal /l0_dds_reader_test3_arznriu/uut/data_in_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test3_arznriu/uut/valid_in_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test3_arznriu/uut/ready_in_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test3_arznriu/uut/last_word_in_kh -add wave -noupdate -group {KEY HOLDER} -radix hexadecimal /l0_dds_reader_test3_arznriu/uut/data_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test3_arznriu/uut/valid_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test3_arznriu/uut/ready_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test3_arznriu/uut/last_word_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test3_arznriu/uut/abort_kh -add wave -noupdate -divider MISC -add wave -noupdate -radix unsigned /l0_dds_reader_test3_arznriu/uut/collection_cnt -add wave -noupdate -radix unsigned /l0_dds_reader_test3_arznriu/uut/collection_cnt_max -add wave -noupdate -radix unsigned /l0_dds_reader_test3_arznriu/uut/collection_generation_rank -add wave -noupdate -radix unsigned /l0_dds_reader_test3_arznriu/uut/cur_generation_rank -add wave -noupdate -radix unsigned /l0_dds_reader_test3_arznriu/uut/max_samples_latch -add wave -noupdate /l0_dds_reader_test3_arznriu/uut/dynamic_next_instance -add wave -noupdate /l0_dds_reader_test3_arznriu/uut/single_instance -add wave -noupdate /l0_dds_reader_test3_arznriu/uut/is_take -add wave -noupdate -radix unsigned /l0_dds_reader_test3_arznriu/uut/sel_sample -add wave -noupdate -radix unsigned /l0_dds_reader_test3_arznriu/uut/sample_p1 -add wave -noupdate -radix unsigned /l0_dds_reader_test3_arznriu/uut/sample_p2 -add wave -noupdate -radix SAMPLE_STATE /l0_dds_reader_test3_arznriu/uut/sample_state -add wave -noupdate -radix VIEW_STATE /l0_dds_reader_test3_arznriu/uut/view_state -add wave -noupdate -radix INSTANCE_STATE /l0_dds_reader_test3_arznriu/uut/instance_state -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {262408405 ps} 0} {{Cursor 2} {115175000 ps} 1} -quietly wave cursor active 1 -configure wave -namecolwidth 187 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -configure wave -timelineunits ns -update -WaveRestoreZoom {261834536 ps} {262835177 ps} diff --git a/sim/L0_dds_reader_test4.do b/sim/L0_dds_reader_test4.do new file mode 100644 index 0000000..fb26e58 --- /dev/null +++ b/sim/L0_dds_reader_test4.do @@ -0,0 +1,184 @@ +onerror {resume} +radix define DDS_RETCODE { + "10#0#" "RETCODE_OK", + "10#1#" "RETCODE_ERROR", + "10#2#" "RETCODE_UNSUPPORTED", + "10#3#" "RETCODE_BAD_PARAMETER", + "10#4#" "RETCODE_PRECONDITION_NOT_MET", + "10#5#" "RETCODE_OUT_OF_RESOURCES", + "10#6#" "RETCODE_NOT_ENABLED", + "10#7#" "RETCODE_IMMUTABLE_POLICY", + "10#8#" "RETCODE_INCONSISTENT_POLICY", + "10#9#" "RETCODE_ALREADY_DELETED", + "10#10#" "RETCODE_TIMEOUT", + "10#11#" "RETCODE_NO_DATA", + "10#12#" "RETCODE_ILLEGAL_OPERATION", + -default unsigned +} +radix define SAMPLE_STATE { + "16#00000001#" "READ_SAMPLE_STATE", + "16#00000002#" "NOT_READ_SAMPLE_STATE", + "16#FFFFFFFF#" "ANY_SAMPLE_STATE", + -default binary +} +radix define VIEW_STATE { + "16#00000001#" "NEW_VIEW_STATE", + "16#00000002#" "NOT_NEW_VIEW_STATE", + "16#FFFFFFFF#" "ANY_VIEW_STATE", + -default binary +} +radix define INSTANCE_STATE { + "16#00000001#" "ALIVE_INSTANCE_STATE", + "16#00000002#" "NOT_ALIVE_DISPOSED_INSTANCE_STATE", + "16#00000004#" "NOT_ALIVE_NO_WRITERS_INSTANCE_STATE", + "16#FFFFFFFF#" "ANY_INSTANCE_STATE", + -default binary +} +radix define LAST_REASON { + "16#00000000#" "NOT_REJECTED", + "16#00000001#" "REJECTED_BY_INSTANCES_LIMIT", + "16#00000002#" "REJECTED_BY_SAMPLES_LIMIT", + "16#00000003#" "REJECTED_BY_SAMPLES_PER_INSTANCE_LIMIT", + "16#000000FF#" "REJECTED_BY_PAYOAD_MEMORY_LIMIT", + -default binary +} +quietly WaveActivateNextPane {} 0 +add wave -noupdate -divider SYSTEM +add wave -noupdate /l0_dds_reader_test4/uut/clk +add wave -noupdate /l0_dds_reader_test4/uut/reset +add wave -noupdate -radix unsigned /l0_dds_reader_test4/uut/time +add wave -noupdate -radix unsigned /l0_dds_reader_test4/uut/deadline_check_time +add wave -noupdate -divider RTPS +add wave -noupdate -group RTPS /l0_dds_reader_test4/uut/start_rtps +add wave -noupdate -group RTPS /l0_dds_reader_test4/uut/opcode_rtps +add wave -noupdate -group RTPS /l0_dds_reader_test4/uut/ack_rtps +add wave -noupdate -group RTPS /l0_dds_reader_test4/uut/ret_rtps +add wave -noupdate -group RTPS /l0_dds_reader_test4/uut/done_rtps +add wave -noupdate -group RTPS /l0_dds_reader_test4/uut/ready_in_rtps +add wave -noupdate -group RTPS /l0_dds_reader_test4/uut/valid_in_rtps +add wave -noupdate -group RTPS -radix hexadecimal /l0_dds_reader_test4/uut/data_in_rtps +add wave -noupdate -group RTPS /l0_dds_reader_test4/uut/last_word_in_rtps +add wave -noupdate -divider DDS +add wave -noupdate -group DDS /l0_dds_reader_test4/uut/start_dds +add wave -noupdate -group DDS /l0_dds_reader_test4/uut/ack_dds +add wave -noupdate -group DDS /l0_dds_reader_test4/uut/opcode_dds +add wave -noupdate -group DDS -radix SAMPLE_STATE /l0_dds_reader_test4/uut/sample_state_dds +add wave -noupdate -group DDS -radix INSTANCE_STATE /l0_dds_reader_test4/uut/instance_state_dds +add wave -noupdate -group DDS -radix VIEW_STATE /l0_dds_reader_test4/uut/view_state_dds +add wave -noupdate -group DDS -radix hexadecimal /l0_dds_reader_test4/uut/instance_handle_dds +add wave -noupdate -group DDS -radix unsigned /l0_dds_reader_test4/uut/max_samples_dds +add wave -noupdate -group DDS -radix DDS_RETCODE -childformat {{/l0_dds_reader_test4/uut/return_code_dds(0) -radix DDS_RETCODE} {/l0_dds_reader_test4/uut/return_code_dds(1) -radix DDS_RETCODE}} -subitemconfig {/l0_dds_reader_test4/uut/return_code_dds(0) {-height 15 -radix DDS_RETCODE} /l0_dds_reader_test4/uut/return_code_dds(1) {-height 15 -radix DDS_RETCODE}} /l0_dds_reader_test4/uut/return_code_dds +add wave -noupdate -group DDS /l0_dds_reader_test4/uut/done_dds +add wave -noupdate -group DDS -divider SI +add wave -noupdate -group DDS -radix hexadecimal -childformat {{/l0_dds_reader_test4/uut/sample_info(0) -radix hexadecimal -childformat {{/l0_dds_reader_test4/uut/sample_info(0).sample_state -radix hexadecimal} {/l0_dds_reader_test4/uut/sample_info(0).view_state -radix hexadecimal} {/l0_dds_reader_test4/uut/sample_info(0).instance_state -radix hexadecimal} {/l0_dds_reader_test4/uut/sample_info(0).source_timestamp -radix hexadecimal} {/l0_dds_reader_test4/uut/sample_info(0).instance_handle -radix hexadecimal} {/l0_dds_reader_test4/uut/sample_info(0).publication_handle -radix hexadecimal} {/l0_dds_reader_test4/uut/sample_info(0).disposed_generation_count -radix hexadecimal} {/l0_dds_reader_test4/uut/sample_info(0).no_writers_generation_count -radix hexadecimal} {/l0_dds_reader_test4/uut/sample_info(0).sample_rank -radix hexadecimal} {/l0_dds_reader_test4/uut/sample_info(0).generation_rank -radix hexadecimal} {/l0_dds_reader_test4/uut/sample_info(0).absolute_generation_rank -radix hexadecimal} {/l0_dds_reader_test4/uut/sample_info(0).valid_data -radix hexadecimal}}} {/l0_dds_reader_test4/uut/sample_info(1) -radix hexadecimal}} -subitemconfig {/l0_dds_reader_test4/uut/sample_info(0) {-height 15 -radix hexadecimal -childformat {{/l0_dds_reader_test4/uut/sample_info(0).sample_state -radix hexadecimal} {/l0_dds_reader_test4/uut/sample_info(0).view_state -radix hexadecimal} {/l0_dds_reader_test4/uut/sample_info(0).instance_state -radix hexadecimal} {/l0_dds_reader_test4/uut/sample_info(0).source_timestamp -radix hexadecimal} {/l0_dds_reader_test4/uut/sample_info(0).instance_handle -radix hexadecimal} {/l0_dds_reader_test4/uut/sample_info(0).publication_handle -radix hexadecimal} {/l0_dds_reader_test4/uut/sample_info(0).disposed_generation_count -radix hexadecimal} {/l0_dds_reader_test4/uut/sample_info(0).no_writers_generation_count -radix hexadecimal} {/l0_dds_reader_test4/uut/sample_info(0).sample_rank -radix hexadecimal} {/l0_dds_reader_test4/uut/sample_info(0).generation_rank -radix hexadecimal} {/l0_dds_reader_test4/uut/sample_info(0).absolute_generation_rank -radix hexadecimal} {/l0_dds_reader_test4/uut/sample_info(0).valid_data -radix hexadecimal}}} /l0_dds_reader_test4/uut/sample_info(0).sample_state {-height 15 -radix hexadecimal} /l0_dds_reader_test4/uut/sample_info(0).view_state {-height 15 -radix hexadecimal} /l0_dds_reader_test4/uut/sample_info(0).instance_state {-height 15 -radix hexadecimal} /l0_dds_reader_test4/uut/sample_info(0).source_timestamp {-height 15 -radix hexadecimal} /l0_dds_reader_test4/uut/sample_info(0).instance_handle {-height 15 -radix hexadecimal} /l0_dds_reader_test4/uut/sample_info(0).publication_handle {-height 15 -radix hexadecimal} /l0_dds_reader_test4/uut/sample_info(0).disposed_generation_count {-height 15 -radix hexadecimal} /l0_dds_reader_test4/uut/sample_info(0).no_writers_generation_count {-height 15 -radix hexadecimal} /l0_dds_reader_test4/uut/sample_info(0).sample_rank {-height 15 -radix hexadecimal} /l0_dds_reader_test4/uut/sample_info(0).generation_rank {-height 15 -radix hexadecimal} /l0_dds_reader_test4/uut/sample_info(0).absolute_generation_rank {-height 15 -radix hexadecimal} /l0_dds_reader_test4/uut/sample_info(0).valid_data {-height 15 -radix hexadecimal} /l0_dds_reader_test4/uut/sample_info(1) {-height 15 -radix hexadecimal}} /l0_dds_reader_test4/uut/sample_info +add wave -noupdate -group DDS /l0_dds_reader_test4/uut/sample_info_valid +add wave -noupdate -group DDS /l0_dds_reader_test4/uut/sample_info_ack +add wave -noupdate -group DDS /l0_dds_reader_test4/uut/eoc +add wave -noupdate -group DDS /l0_dds_reader_test4/uut/get_data_dds +add wave -noupdate -group DDS -divider OUTPUT +add wave -noupdate -group DDS /l0_dds_reader_test4/uut/ready_out_dds +add wave -noupdate -group DDS /l0_dds_reader_test4/uut/valid_out_dds +add wave -noupdate -group DDS -radix hexadecimal /l0_dds_reader_test4/uut/data_out_dds +add wave -noupdate -group DDS /l0_dds_reader_test4/uut/last_word_out_dds +add wave -noupdate -divider {MAIN FSM} +add wave -noupdate /l0_dds_reader_test4/uut/stage +add wave -noupdate /l0_dds_reader_test4/uut/cnt +add wave -noupdate /l0_dds_reader_test4/uut/ind +add wave -noupdate -radix unsigned /l0_dds_reader_test4/uut/deadline_time +add wave -noupdate -divider MEMORY +add wave -noupdate /l0_dds_reader_test4/uut/inst_op_start +add wave -noupdate /l0_dds_reader_test4/uut/inst_opcode +add wave -noupdate /l0_dds_reader_test4/uut/inst_op_done +add wave -noupdate /l0_dds_reader_test4/uut/inst_stage +add wave -noupdate /l0_dds_reader_test4/uut/inst_cnt +add wave -noupdate -radix unsigned /l0_dds_reader_test4/uut/inst_addr_base +add wave -noupdate -childformat {{/l0_dds_reader_test4/uut/inst_data.addr -radix unsigned} {/l0_dds_reader_test4/uut/inst_data.key_hash -radix hexadecimal} {/l0_dds_reader_test4/uut/inst_data.status_info -radix binary} {/l0_dds_reader_test4/uut/inst_data.sample_cnt -radix unsigned} {/l0_dds_reader_test4/uut/inst_data.disposed_gen_cnt -radix unsigned} {/l0_dds_reader_test4/uut/inst_data.no_writers_gen_cnt -radix unsigned} {/l0_dds_reader_test4/uut/inst_data.ignore_deadline -radix unsigned} {/l0_dds_reader_test4/uut/inst_data.writer_bitmap -radix binary -childformat {{/l0_dds_reader_test4/uut/inst_data.writer_bitmap(0) -radix binary -childformat {{/l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(0) -radix binary} {/l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(1) -radix binary} {/l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(2) -radix binary} {/l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(3) -radix binary} {/l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(4) -radix binary} {/l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(5) -radix binary} {/l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(6) -radix binary} {/l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(7) -radix binary} {/l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(8) -radix binary} {/l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(9) -radix binary} {/l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(10) -radix binary} {/l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(11) -radix binary} {/l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(12) -radix binary} {/l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(13) -radix binary} {/l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(14) -radix binary} {/l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(15) -radix binary} {/l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(16) -radix binary} {/l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(17) -radix binary} {/l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(18) -radix binary} {/l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(19) -radix binary} {/l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(20) -radix binary} {/l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(21) -radix binary} {/l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(22) -radix binary} {/l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(23) -radix binary} {/l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(24) -radix binary} {/l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(25) -radix binary} {/l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(26) -radix binary} {/l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(27) -radix binary} {/l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(28) -radix binary} {/l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(29) -radix binary} {/l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(30) -radix binary} {/l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(31) -radix binary}}}}}} -expand -subitemconfig {/l0_dds_reader_test4/uut/inst_data.addr {-height 15 -radix unsigned} /l0_dds_reader_test4/uut/inst_data.key_hash {-height 15 -radix hexadecimal} /l0_dds_reader_test4/uut/inst_data.status_info {-height 15 -radix binary} /l0_dds_reader_test4/uut/inst_data.sample_cnt {-height 15 -radix unsigned} /l0_dds_reader_test4/uut/inst_data.disposed_gen_cnt {-height 15 -radix unsigned} /l0_dds_reader_test4/uut/inst_data.no_writers_gen_cnt {-height 15 -radix unsigned} /l0_dds_reader_test4/uut/inst_data.ignore_deadline {-height 15 -radix unsigned} /l0_dds_reader_test4/uut/inst_data.writer_bitmap {-height 15 -radix binary -childformat {{/l0_dds_reader_test4/uut/inst_data.writer_bitmap(0) -radix binary -childformat {{/l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(0) -radix binary} {/l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(1) -radix binary} {/l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(2) -radix binary} {/l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(3) -radix binary} {/l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(4) -radix binary} {/l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(5) -radix binary} {/l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(6) -radix binary} {/l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(7) -radix binary} {/l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(8) -radix binary} {/l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(9) -radix binary} {/l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(10) -radix binary} {/l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(11) -radix binary} {/l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(12) -radix binary} {/l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(13) -radix binary} {/l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(14) -radix binary} {/l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(15) -radix binary} {/l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(16) -radix binary} {/l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(17) -radix binary} {/l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(18) -radix binary} {/l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(19) -radix binary} {/l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(20) -radix binary} {/l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(21) -radix binary} {/l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(22) -radix binary} {/l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(23) -radix binary} {/l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(24) -radix binary} {/l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(25) -radix binary} {/l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(26) -radix binary} {/l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(27) -radix binary} {/l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(28) -radix binary} {/l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(29) -radix binary} {/l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(30) -radix binary} {/l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(31) -radix binary}}}}} /l0_dds_reader_test4/uut/inst_data.writer_bitmap(0) {-height 15 -radix binary -childformat {{/l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(0) -radix binary} {/l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(1) -radix binary} {/l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(2) -radix binary} {/l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(3) -radix binary} {/l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(4) -radix binary} {/l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(5) -radix binary} {/l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(6) -radix binary} {/l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(7) -radix binary} {/l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(8) -radix binary} {/l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(9) -radix binary} {/l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(10) -radix binary} {/l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(11) -radix binary} {/l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(12) -radix binary} {/l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(13) -radix binary} {/l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(14) -radix binary} {/l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(15) -radix binary} {/l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(16) -radix binary} {/l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(17) -radix binary} {/l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(18) -radix binary} {/l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(19) -radix binary} {/l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(20) -radix binary} {/l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(21) -radix binary} {/l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(22) -radix binary} {/l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(23) -radix binary} {/l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(24) -radix binary} {/l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(25) -radix binary} {/l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(26) -radix binary} {/l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(27) -radix binary} {/l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(28) -radix binary} {/l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(29) -radix binary} {/l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(30) -radix binary} {/l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(31) -radix binary}}} /l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(0) {-height 15 -radix binary} /l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(1) {-height 15 -radix binary} /l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(2) {-height 15 -radix binary} /l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(3) {-height 15 -radix binary} /l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(4) {-height 15 -radix binary} /l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(5) {-height 15 -radix binary} /l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(6) {-height 15 -radix binary} /l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(7) {-height 15 -radix binary} /l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(8) {-height 15 -radix binary} /l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(9) {-height 15 -radix binary} /l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(10) {-height 15 -radix binary} /l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(11) {-height 15 -radix binary} /l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(12) {-height 15 -radix binary} /l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(13) {-height 15 -radix binary} /l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(14) {-height 15 -radix binary} /l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(15) {-height 15 -radix binary} /l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(16) {-height 15 -radix binary} /l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(17) {-height 15 -radix binary} /l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(18) {-height 15 -radix binary} /l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(19) {-height 15 -radix binary} /l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(20) {-height 15 -radix binary} /l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(21) {-height 15 -radix binary} /l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(22) {-height 15 -radix binary} /l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(23) {-height 15 -radix binary} /l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(24) {-height 15 -radix binary} /l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(25) {-height 15 -radix binary} /l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(26) {-height 15 -radix binary} /l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(27) {-height 15 -radix binary} /l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(28) {-height 15 -radix binary} /l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(29) {-height 15 -radix binary} /l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(30) {-height 15 -radix binary} /l0_dds_reader_test4/uut/inst_data.writer_bitmap(0)(31) {-height 15 -radix binary}} /l0_dds_reader_test4/uut/inst_data +add wave -noupdate /l0_dds_reader_test4/uut/stale_inst_cnt +add wave -noupdate -group {SAMPLE MEM} -radix unsigned /l0_dds_reader_test4/uut/sample_addr +add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test4/uut/sample_read +add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test4/uut/sample_ready_in +add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test4/uut/sample_valid_in +add wave -noupdate -group {SAMPLE MEM} -radix hexadecimal /l0_dds_reader_test4/uut/sample_write_data +add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test4/uut/sample_ready_out +add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test4/uut/sample_valid_out +add wave -noupdate -group {SAMPLE MEM} -radix hexadecimal /l0_dds_reader_test4/uut/sample_read_data +add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test4/uut/sample_abort_read +add wave -noupdate -group {PAYLOAD MEM} -radix unsigned /l0_dds_reader_test4/uut/payload_addr +add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test4/uut/payload_read +add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test4/uut/payload_ready_in +add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test4/uut/payload_valid_in +add wave -noupdate -group {PAYLOAD MEM} -radix hexadecimal /l0_dds_reader_test4/uut/payload_write_data +add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test4/uut/payload_ready_out +add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test4/uut/payload_valid_out +add wave -noupdate -group {PAYLOAD MEM} -radix hexadecimal /l0_dds_reader_test4/uut/payload_read_data +add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test4/uut/payload_abort_read +add wave -noupdate -group {INSTANCE MEM} -radix unsigned /l0_dds_reader_test4/uut/inst_addr +add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test4/uut/inst_read +add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test4/uut/inst_ready_in +add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test4/uut/inst_valid_in +add wave -noupdate -group {INSTANCE MEM} -radix hexadecimal /l0_dds_reader_test4/uut/inst_write_data +add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test4/uut/inst_ready_out +add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test4/uut/inst_valid_out +add wave -noupdate -group {INSTANCE MEM} -radix hexadecimal /l0_dds_reader_test4/uut/inst_read_data +add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test4/uut/inst_abort_read +add wave -noupdate -divider POINTERS +add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test4/uut/empty_sample_list_head +add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test4/uut/empty_sample_list_tail +add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test4/uut/empty_payload_list_head +add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test4/uut/oldest_sample +add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test4/uut/newest_sample +add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test4/uut/inst_empty_head +add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test4/uut/inst_occupied_head +add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test4/uut/cur_sample +add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test4/uut/next_sample +add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test4/uut/prev_sample +add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test4/uut/cur_payload +add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test4/uut/next_payload +add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test4/uut/cur_inst +add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test4/uut/next_inst +add wave -noupdate -divider MISC +add wave -noupdate -radix unsigned /l0_dds_reader_test4/uut/deadline_miss_cnt +add wave -noupdate -radix unsigned /l0_dds_reader_test4/uut/deadline_miss_cnt_change +add wave -noupdate -radix hexadecimal /l0_dds_reader_test4/uut/deadline_miss_last_inst +add wave -noupdate /l0_dds_reader_test4/uut/status +add wave -noupdate -divider TESTBENCH +add wave -noupdate -group TESTBENCH /l0_dds_reader_test4/dds_start +add wave -noupdate -group TESTBENCH /l0_dds_reader_test4/dds_stage +add wave -noupdate -group TESTBENCH /l0_dds_reader_test4/dds_cnt +add wave -noupdate -group TESTBENCH /l0_dds_reader_test4/dds_cnt2 +add wave -noupdate -group TESTBENCH /l0_dds_reader_test4/dds_done +add wave -noupdate -group TESTBENCH /l0_dds_reader_test4/rtps_start +add wave -noupdate -group TESTBENCH /l0_dds_reader_test4/rtps_stage +add wave -noupdate -group TESTBENCH /l0_dds_reader_test4/rtps_cnt +add wave -noupdate -group TESTBENCH /l0_dds_reader_test4/rtps_done +add wave -noupdate -divider {KEY HOLDER} +add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test4/uut/start_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test4/uut/opcode_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test4/uut/ack_kh +add wave -noupdate -group {KEY HOLDER} -radix hexadecimal /l0_dds_reader_test4/uut/data_in_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test4/uut/valid_in_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test4/uut/ready_in_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test4/uut/last_word_in_kh +add wave -noupdate -group {KEY HOLDER} -radix hexadecimal /l0_dds_reader_test4/uut/data_out_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test4/uut/valid_out_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test4/uut/ready_out_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test4/uut/last_word_out_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test4/uut/abort_kh +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {24924731 ps} 0} +quietly wave cursor active 1 +configure wave -namecolwidth 187 +configure wave -valuecolwidth 206 +configure wave -justifyvalue left +configure wave -signalnamewidth 1 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ns +update +WaveRestoreZoom {25050079 ps} {25983800 ps} diff --git a/sim/L0_dds_reader_test4_arzkriu.do b/sim/L0_dds_reader_test4_arzkriu.do deleted file mode 100644 index aa9d985..0000000 --- a/sim/L0_dds_reader_test4_arzkriu.do +++ /dev/null @@ -1,199 +0,0 @@ -onerror {resume} -radix define DDS_RETCODE { - "10#0#" "RETCODE_OK", - "10#1#" "RETCODE_ERROR", - "10#2#" "RETCODE_UNSUPPORTED", - "10#3#" "RETCODE_BAD_PARAMETER", - "10#4#" "RETCODE_PRECONDITION_NOT_MET", - "10#5#" "RETCODE_OUT_OF_RESOURCES", - "10#6#" "RETCODE_NOT_ENABLED", - "10#7#" "RETCODE_IMMUTABLE_POLICY", - "10#8#" "RETCODE_INCONSISTENT_POLICY", - "10#9#" "RETCODE_ALREADY_DELETED", - "10#10#" "RETCODE_TIMEOUT", - "10#11#" "RETCODE_NO_DATA", - "10#12#" "RETCODE_ILLEGAL_OPERATION", - -default unsigned -} -radix define SAMPLE_STATE { - "16#00000001#" "READ_SAMPLE_STATE", - "16#00000002#" "NOT_READ_SAMPLE_STATE", - "16#FFFFFFFF#" "ANY_SAMPLE_STATE", - -default binary -} -radix define VIEW_STATE { - "16#00000001#" "NEW_VIEW_STATE", - "16#00000002#" "NOT_NEW_VIEW_STATE", - "16#FFFFFFFF#" "ANY_VIEW_STATE", - -default binary -} -radix define INSTANCE_STATE { - "16#00000001#" "ALIVE_INSTANCE_STATE", - "16#00000002#" "NOT_ALIVE_DISPOSED_INSTANCE_STATE", - "16#00000004#" "NOT_ALIVE_NO_WRITERS_INSTANCE_STATE", - "16#FFFFFFFF#" "ANY_INSTANCE_STATE", - -default binary -} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -divider SYSTEM -add wave -noupdate /l0_dds_reader_test4_arzkriu/uut/clk -add wave -noupdate /l0_dds_reader_test4_arzkriu/uut/reset -add wave -noupdate -radix unsigned /l0_dds_reader_test4_arzkriu/uut/time -add wave -noupdate -divider RTPS -add wave -noupdate -group RTPS /l0_dds_reader_test4_arzkriu/uut/start_rtps -add wave -noupdate -group RTPS /l0_dds_reader_test4_arzkriu/uut/opcode_rtps -add wave -noupdate -group RTPS /l0_dds_reader_test4_arzkriu/uut/ack_rtps -add wave -noupdate -group RTPS /l0_dds_reader_test4_arzkriu/uut/ret_rtps -add wave -noupdate -group RTPS /l0_dds_reader_test4_arzkriu/uut/done_rtps -add wave -noupdate -group RTPS /l0_dds_reader_test4_arzkriu/uut/ready_in_rtps -add wave -noupdate -group RTPS /l0_dds_reader_test4_arzkriu/uut/valid_in_rtps -add wave -noupdate -group RTPS -radix hexadecimal /l0_dds_reader_test4_arzkriu/uut/data_in_rtps -add wave -noupdate -group RTPS /l0_dds_reader_test4_arzkriu/uut/last_word_in_rtps -add wave -noupdate -divider DDS -add wave -noupdate -expand -group DDS /l0_dds_reader_test4_arzkriu/uut/start_dds -add wave -noupdate -expand -group DDS /l0_dds_reader_test4_arzkriu/uut/ack_dds -add wave -noupdate -expand -group DDS /l0_dds_reader_test4_arzkriu/uut/opcode_dds -add wave -noupdate -expand -group DDS -radix SAMPLE_STATE /l0_dds_reader_test4_arzkriu/uut/sample_state_dds -add wave -noupdate -expand -group DDS -radix INSTANCE_STATE /l0_dds_reader_test4_arzkriu/uut/instance_state_dds -add wave -noupdate -expand -group DDS -radix VIEW_STATE /l0_dds_reader_test4_arzkriu/uut/view_state_dds -add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_reader_test4_arzkriu/uut/instance_handle_dds -add wave -noupdate -expand -group DDS -radix unsigned /l0_dds_reader_test4_arzkriu/uut/max_samples_dds -add wave -noupdate -expand -group DDS -radix DDS_RETCODE /l0_dds_reader_test4_arzkriu/uut/return_code_dds -add wave -noupdate -expand -group DDS /l0_dds_reader_test4_arzkriu/uut/done_dds -add wave -noupdate -expand -group DDS -divider SI -add wave -noupdate -expand -group DDS -radix SAMPLE_STATE /l0_dds_reader_test4_arzkriu/uut/si_sample_state -add wave -noupdate -expand -group DDS -radix VIEW_STATE /l0_dds_reader_test4_arzkriu/uut/si_view_state -add wave -noupdate -expand -group DDS -radix INSTANCE_STATE /l0_dds_reader_test4_arzkriu/uut/si_instance_state -add wave -noupdate -expand -group DDS -radix unsigned /l0_dds_reader_test4_arzkriu/uut/si_source_timestamp -add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_reader_test4_arzkriu/uut/si_instance_handle -add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_reader_test4_arzkriu/uut/si_publication_handle -add wave -noupdate -expand -group DDS -radix unsigned /l0_dds_reader_test4_arzkriu/uut/si_disposed_generation_count -add wave -noupdate -expand -group DDS -radix unsigned /l0_dds_reader_test4_arzkriu/uut/si_no_writers_generation_count -add wave -noupdate -expand -group DDS -radix unsigned /l0_dds_reader_test4_arzkriu/uut/si_sample_rank -add wave -noupdate -expand -group DDS -radix unsigned /l0_dds_reader_test4_arzkriu/uut/si_generation_rank -add wave -noupdate -expand -group DDS -radix unsigned /l0_dds_reader_test4_arzkriu/uut/si_absolute_generation_rank -add wave -noupdate -expand -group DDS /l0_dds_reader_test4_arzkriu/uut/si_valid_data -add wave -noupdate -expand -group DDS /l0_dds_reader_test4_arzkriu/uut/si_valid -add wave -noupdate -expand -group DDS /l0_dds_reader_test4_arzkriu/uut/get_data_dds -add wave -noupdate -expand -group DDS /l0_dds_reader_test4_arzkriu/uut/eoc -add wave -noupdate -expand -group DDS -divider OUTPUT -add wave -noupdate -expand -group DDS /l0_dds_reader_test4_arzkriu/uut/ready_out_dds -add wave -noupdate -expand -group DDS /l0_dds_reader_test4_arzkriu/uut/valid_out_dds -add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_reader_test4_arzkriu/uut/data_out_dds -add wave -noupdate -expand -group DDS /l0_dds_reader_test4_arzkriu/uut/last_word_out_dds -add wave -noupdate -divider {MAIN FSM} -add wave -noupdate /l0_dds_reader_test4_arzkriu/uut/stage -add wave -noupdate /l0_dds_reader_test4_arzkriu/uut/stage_next -add wave -noupdate /l0_dds_reader_test4_arzkriu/uut/cnt -add wave -noupdate -divider MEMORY -add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test4_arzkriu/uut/sample_abort_read -add wave -noupdate -group {SAMPLE MEM} -radix unsigned /l0_dds_reader_test4_arzkriu/uut/sample_mem_ctrl_inst/addr -add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test4_arzkriu/uut/sample_mem_ctrl_inst/read -add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test4_arzkriu/uut/sample_mem_ctrl_inst/ready_in -add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test4_arzkriu/uut/sample_mem_ctrl_inst/valid_in -add wave -noupdate -group {SAMPLE MEM} -radix hexadecimal /l0_dds_reader_test4_arzkriu/uut/sample_mem_ctrl_inst/data_in -add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test4_arzkriu/uut/sample_mem_ctrl_inst/ready_out -add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test4_arzkriu/uut/sample_mem_ctrl_inst/valid_out -add wave -noupdate -group {SAMPLE MEM} -radix hexadecimal /l0_dds_reader_test4_arzkriu/uut/sample_mem_ctrl_inst/data_out -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test4_arzkriu/uut/payload_abort_read -add wave -noupdate -group {PAYLOAD MEM} -radix unsigned /l0_dds_reader_test4_arzkriu/uut/payload_mem_ctrl_inst/addr -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test4_arzkriu/uut/payload_mem_ctrl_inst/read -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test4_arzkriu/uut/payload_mem_ctrl_inst/ready_in -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test4_arzkriu/uut/payload_mem_ctrl_inst/valid_in -add wave -noupdate -group {PAYLOAD MEM} -radix hexadecimal /l0_dds_reader_test4_arzkriu/uut/payload_mem_ctrl_inst/data_in -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test4_arzkriu/uut/payload_mem_ctrl_inst/ready_out -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test4_arzkriu/uut/payload_mem_ctrl_inst/valid_out -add wave -noupdate -group {PAYLOAD MEM} -radix hexadecimal /l0_dds_reader_test4_arzkriu/uut/payload_mem_ctrl_inst/data_out -add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test4_arzkriu/uut/inst_abort_read -add wave -noupdate -group {INSTANCE MEM} -radix unsigned /l0_dds_reader_test4_arzkriu/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/addr -add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test4_arzkriu/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/read -add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test4_arzkriu/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/ready_in -add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test4_arzkriu/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/valid_in -add wave -noupdate -group {INSTANCE MEM} -radix hexadecimal /l0_dds_reader_test4_arzkriu/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/data_in -add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test4_arzkriu/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/ready_out -add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test4_arzkriu/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/valid_out -add wave -noupdate -group {INSTANCE MEM} -radix hexadecimal /l0_dds_reader_test4_arzkriu/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/data_out -add wave -noupdate /l0_dds_reader_test4_arzkriu/uut/inst_op_start -add wave -noupdate /l0_dds_reader_test4_arzkriu/uut/inst_opcode -add wave -noupdate /l0_dds_reader_test4_arzkriu/uut/inst_op_done -add wave -noupdate /l0_dds_reader_test4_arzkriu/uut/inst_stage -add wave -noupdate /l0_dds_reader_test4_arzkriu/uut/inst_stage_next -add wave -noupdate /l0_dds_reader_test4_arzkriu/uut/inst_cnt -add wave -noupdate -radix unsigned /l0_dds_reader_test4_arzkriu/uut/inst_addr_base -add wave -noupdate /l0_dds_reader_test4_arzkriu/uut/inst_mem_fields -add wave -noupdate -childformat {{/l0_dds_reader_test4_arzkriu/uut/inst_data.key_hash -radix hexadecimal} {/l0_dds_reader_test4_arzkriu/uut/inst_data.status_info -radix binary} {/l0_dds_reader_test4_arzkriu/uut/inst_data.sample_cnt -radix unsigned} {/l0_dds_reader_test4_arzkriu/uut/inst_data.disposed_gen_cnt -radix unsigned} {/l0_dds_reader_test4_arzkriu/uut/inst_data.no_writers_gen_cnt -radix unsigned} {/l0_dds_reader_test4_arzkriu/uut/inst_data.ignore_deadline -radix unsigned} {/l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap -radix binary -childformat {{/l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0) -radix binary -childformat {{/l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(0) -radix binary} {/l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(1) -radix binary} {/l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(2) -radix binary} {/l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(3) -radix binary} {/l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(4) -radix binary} {/l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(5) -radix binary} {/l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(6) -radix binary} {/l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(7) -radix binary} {/l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(8) -radix binary} {/l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(9) -radix binary} {/l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(10) -radix binary} {/l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(11) -radix binary} {/l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(12) -radix binary} {/l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(13) -radix binary} {/l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(14) -radix binary} {/l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(15) -radix binary} {/l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(16) -radix binary} {/l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(17) -radix binary} {/l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(18) -radix binary} {/l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(19) -radix binary} {/l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(20) -radix binary} {/l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(21) -radix binary} {/l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(22) -radix binary} {/l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(23) -radix binary} {/l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(24) -radix binary} {/l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(25) -radix binary} {/l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(26) -radix binary} {/l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(27) -radix binary} {/l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(28) -radix binary} {/l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(29) -radix binary} {/l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(30) -radix binary} {/l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(31) -radix binary}}}}}} -expand -subitemconfig {/l0_dds_reader_test4_arzkriu/uut/inst_data.key_hash {-height 15 -radix hexadecimal} /l0_dds_reader_test4_arzkriu/uut/inst_data.status_info {-height 15 -radix binary} /l0_dds_reader_test4_arzkriu/uut/inst_data.sample_cnt {-height 15 -radix unsigned} /l0_dds_reader_test4_arzkriu/uut/inst_data.disposed_gen_cnt {-height 15 -radix unsigned} /l0_dds_reader_test4_arzkriu/uut/inst_data.no_writers_gen_cnt {-height 15 -radix unsigned} /l0_dds_reader_test4_arzkriu/uut/inst_data.ignore_deadline {-height 15 -radix unsigned} /l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap {-height 15 -radix binary -childformat {{/l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0) -radix binary -childformat {{/l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(0) -radix binary} {/l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(1) -radix binary} {/l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(2) -radix binary} {/l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(3) -radix binary} {/l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(4) -radix binary} {/l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(5) -radix binary} {/l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(6) -radix binary} {/l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(7) -radix binary} {/l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(8) -radix binary} {/l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(9) -radix binary} {/l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(10) -radix binary} {/l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(11) -radix binary} {/l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(12) -radix binary} {/l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(13) -radix binary} {/l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(14) -radix binary} {/l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(15) -radix binary} {/l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(16) -radix binary} {/l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(17) -radix binary} {/l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(18) -radix binary} {/l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(19) -radix binary} {/l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(20) -radix binary} {/l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(21) -radix binary} {/l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(22) -radix binary} {/l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(23) -radix binary} {/l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(24) -radix binary} {/l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(25) -radix binary} {/l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(26) -radix binary} {/l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(27) -radix binary} {/l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(28) -radix binary} {/l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(29) -radix binary} {/l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(30) -radix binary} {/l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(31) -radix binary}}}}} /l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0) {-height 15 -radix binary -childformat {{/l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(0) -radix binary} {/l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(1) -radix binary} {/l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(2) -radix binary} {/l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(3) -radix binary} {/l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(4) -radix binary} {/l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(5) -radix binary} {/l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(6) -radix binary} {/l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(7) -radix binary} {/l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(8) -radix binary} {/l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(9) -radix binary} {/l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(10) -radix binary} {/l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(11) -radix binary} {/l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(12) -radix binary} {/l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(13) -radix binary} {/l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(14) -radix binary} {/l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(15) -radix binary} {/l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(16) -radix binary} {/l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(17) -radix binary} {/l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(18) -radix binary} {/l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(19) -radix binary} {/l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(20) -radix binary} {/l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(21) -radix binary} {/l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(22) -radix binary} {/l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(23) -radix binary} {/l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(24) -radix binary} {/l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(25) -radix binary} {/l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(26) -radix binary} {/l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(27) -radix binary} {/l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(28) -radix binary} {/l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(29) -radix binary} {/l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(30) -radix binary} {/l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(31) -radix binary}}} /l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(0) {-height 15 -radix binary} /l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(1) {-height 15 -radix binary} /l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(2) {-height 15 -radix binary} /l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(3) {-height 15 -radix binary} /l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(4) {-height 15 -radix binary} /l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(5) {-height 15 -radix binary} /l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(6) {-height 15 -radix binary} /l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(7) {-height 15 -radix binary} /l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(8) {-height 15 -radix binary} /l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(9) {-height 15 -radix binary} /l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(10) {-height 15 -radix binary} /l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(11) {-height 15 -radix binary} /l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(12) {-height 15 -radix binary} /l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(13) {-height 15 -radix binary} /l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(14) {-height 15 -radix binary} /l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(15) {-height 15 -radix binary} /l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(16) {-height 15 -radix binary} /l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(17) {-height 15 -radix binary} /l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(18) {-height 15 -radix binary} /l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(19) {-height 15 -radix binary} /l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(20) {-height 15 -radix binary} /l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(21) {-height 15 -radix binary} /l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(22) {-height 15 -radix binary} /l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(23) {-height 15 -radix binary} /l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(24) {-height 15 -radix binary} /l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(25) {-height 15 -radix binary} /l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(26) {-height 15 -radix binary} /l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(27) {-height 15 -radix binary} /l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(28) {-height 15 -radix binary} /l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(29) {-height 15 -radix binary} /l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(30) {-height 15 -radix binary} /l0_dds_reader_test4_arzkriu/uut/inst_data.writer_bitmap(0)(31) {-height 15 -radix binary}} /l0_dds_reader_test4_arzkriu/uut/inst_data -add wave -noupdate -radix unsigned /l0_dds_reader_test4_arzkriu/uut/inst_next_addr_base -add wave -noupdate -radix unsigned /l0_dds_reader_test4_arzkriu/uut/inst_prev_addr_base -add wave -noupdate /l0_dds_reader_test4_arzkriu/uut/current_imf -add wave -noupdate /l0_dds_reader_test4_arzkriu/uut/stale_inst_cnt -add wave -noupdate -divider POINTERS -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test4_arzkriu/uut/empty_sample_list_head -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test4_arzkriu/uut/empty_sample_list_tail -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test4_arzkriu/uut/empty_payload_list_head -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test4_arzkriu/uut/oldest_sample -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test4_arzkriu/uut/newest_sample -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test4_arzkriu/uut/inst_empty_head -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test4_arzkriu/uut/inst_occupied_head -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test4_arzkriu/uut/cur_sample -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test4_arzkriu/uut/next_sample -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test4_arzkriu/uut/prev_sample -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test4_arzkriu/uut/cur_payload -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test4_arzkriu/uut/next_payload -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test4_arzkriu/uut/cur_inst -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test4_arzkriu/uut/next_inst -add wave -noupdate -divider TESTBENCH -add wave -noupdate -group TESTBENCH /l0_dds_reader_test4_arzkriu/dds_start -add wave -noupdate -group TESTBENCH /l0_dds_reader_test4_arzkriu/dds_stage -add wave -noupdate -group TESTBENCH /l0_dds_reader_test4_arzkriu/dds_cnt -add wave -noupdate -group TESTBENCH /l0_dds_reader_test4_arzkriu/dds_cnt2 -add wave -noupdate -group TESTBENCH /l0_dds_reader_test4_arzkriu/dds_done -add wave -noupdate -group TESTBENCH /l0_dds_reader_test4_arzkriu/rtps_start -add wave -noupdate -group TESTBENCH /l0_dds_reader_test4_arzkriu/rtps_stage -add wave -noupdate -group TESTBENCH /l0_dds_reader_test4_arzkriu/rtps_cnt -add wave -noupdate -group TESTBENCH /l0_dds_reader_test4_arzkriu/rtps_done -add wave -noupdate -divider {KEY HOLDER} -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test4_arzkriu/uut/start_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test4_arzkriu/uut/opcode_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test4_arzkriu/uut/ack_kh -add wave -noupdate -group {KEY HOLDER} -radix hexadecimal /l0_dds_reader_test4_arzkriu/uut/data_in_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test4_arzkriu/uut/valid_in_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test4_arzkriu/uut/ready_in_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test4_arzkriu/uut/last_word_in_kh -add wave -noupdate -group {KEY HOLDER} -radix hexadecimal /l0_dds_reader_test4_arzkriu/uut/data_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test4_arzkriu/uut/valid_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test4_arzkriu/uut/ready_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test4_arzkriu/uut/last_word_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test4_arzkriu/uut/abort_kh -add wave -noupdate -divider MISC -add wave -noupdate -radix unsigned /l0_dds_reader_test4_arzkriu/uut/collection_cnt -add wave -noupdate -radix unsigned /l0_dds_reader_test4_arzkriu/uut/collection_cnt_max -add wave -noupdate -radix unsigned /l0_dds_reader_test4_arzkriu/uut/collection_generation_rank -add wave -noupdate -radix unsigned /l0_dds_reader_test4_arzkriu/uut/cur_generation_rank -add wave -noupdate -radix unsigned /l0_dds_reader_test4_arzkriu/uut/max_samples_latch -add wave -noupdate /l0_dds_reader_test4_arzkriu/uut/dynamic_next_instance -add wave -noupdate /l0_dds_reader_test4_arzkriu/uut/single_instance -add wave -noupdate /l0_dds_reader_test4_arzkriu/uut/is_take -add wave -noupdate -radix unsigned /l0_dds_reader_test4_arzkriu/uut/sel_sample -add wave -noupdate -radix unsigned /l0_dds_reader_test4_arzkriu/uut/sample_p1 -add wave -noupdate -radix unsigned /l0_dds_reader_test4_arzkriu/uut/sample_p2 -add wave -noupdate -radix SAMPLE_STATE /l0_dds_reader_test4_arzkriu/uut/sample_state -add wave -noupdate -radix VIEW_STATE /l0_dds_reader_test4_arzkriu/uut/view_state -add wave -noupdate -radix INSTANCE_STATE /l0_dds_reader_test4_arzkriu/uut/instance_state -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {262408405 ps} 0} {{Cursor 2} {115175000 ps} 1} -quietly wave cursor active 1 -configure wave -namecolwidth 187 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -configure wave -timelineunits ns -update -WaveRestoreZoom {261834536 ps} {262835177 ps} diff --git a/sim/L0_dds_reader_test4_arznriu.do b/sim/L0_dds_reader_test4_arznriu.do deleted file mode 100644 index 38842b2..0000000 --- a/sim/L0_dds_reader_test4_arznriu.do +++ /dev/null @@ -1,199 +0,0 @@ -onerror {resume} -radix define DDS_RETCODE { - "10#0#" "RETCODE_OK", - "10#1#" "RETCODE_ERROR", - "10#2#" "RETCODE_UNSUPPORTED", - "10#3#" "RETCODE_BAD_PARAMETER", - "10#4#" "RETCODE_PRECONDITION_NOT_MET", - "10#5#" "RETCODE_OUT_OF_RESOURCES", - "10#6#" "RETCODE_NOT_ENABLED", - "10#7#" "RETCODE_IMMUTABLE_POLICY", - "10#8#" "RETCODE_INCONSISTENT_POLICY", - "10#9#" "RETCODE_ALREADY_DELETED", - "10#10#" "RETCODE_TIMEOUT", - "10#11#" "RETCODE_NO_DATA", - "10#12#" "RETCODE_ILLEGAL_OPERATION", - -default unsigned -} -radix define SAMPLE_STATE { - "16#00000001#" "READ_SAMPLE_STATE", - "16#00000002#" "NOT_READ_SAMPLE_STATE", - "16#FFFFFFFF#" "ANY_SAMPLE_STATE", - -default binary -} -radix define VIEW_STATE { - "16#00000001#" "NEW_VIEW_STATE", - "16#00000002#" "NOT_NEW_VIEW_STATE", - "16#FFFFFFFF#" "ANY_VIEW_STATE", - -default binary -} -radix define INSTANCE_STATE { - "16#00000001#" "ALIVE_INSTANCE_STATE", - "16#00000002#" "NOT_ALIVE_DISPOSED_INSTANCE_STATE", - "16#00000004#" "NOT_ALIVE_NO_WRITERS_INSTANCE_STATE", - "16#FFFFFFFF#" "ANY_INSTANCE_STATE", - -default binary -} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -divider SYSTEM -add wave -noupdate /l0_dds_reader_test4_arznriu/uut/clk -add wave -noupdate /l0_dds_reader_test4_arznriu/uut/reset -add wave -noupdate -radix unsigned /l0_dds_reader_test4_arznriu/uut/time -add wave -noupdate -divider RTPS -add wave -noupdate -group RTPS /l0_dds_reader_test4_arznriu/uut/start_rtps -add wave -noupdate -group RTPS /l0_dds_reader_test4_arznriu/uut/opcode_rtps -add wave -noupdate -group RTPS /l0_dds_reader_test4_arznriu/uut/ack_rtps -add wave -noupdate -group RTPS /l0_dds_reader_test4_arznriu/uut/ret_rtps -add wave -noupdate -group RTPS /l0_dds_reader_test4_arznriu/uut/done_rtps -add wave -noupdate -group RTPS /l0_dds_reader_test4_arznriu/uut/ready_in_rtps -add wave -noupdate -group RTPS /l0_dds_reader_test4_arznriu/uut/valid_in_rtps -add wave -noupdate -group RTPS -radix hexadecimal /l0_dds_reader_test4_arznriu/uut/data_in_rtps -add wave -noupdate -group RTPS /l0_dds_reader_test4_arznriu/uut/last_word_in_rtps -add wave -noupdate -divider DDS -add wave -noupdate -expand -group DDS /l0_dds_reader_test4_arznriu/uut/start_dds -add wave -noupdate -expand -group DDS /l0_dds_reader_test4_arznriu/uut/ack_dds -add wave -noupdate -expand -group DDS /l0_dds_reader_test4_arznriu/uut/opcode_dds -add wave -noupdate -expand -group DDS -radix SAMPLE_STATE /l0_dds_reader_test4_arznriu/uut/sample_state_dds -add wave -noupdate -expand -group DDS -radix INSTANCE_STATE /l0_dds_reader_test4_arznriu/uut/instance_state_dds -add wave -noupdate -expand -group DDS -radix VIEW_STATE /l0_dds_reader_test4_arznriu/uut/view_state_dds -add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_reader_test4_arznriu/uut/instance_handle_dds -add wave -noupdate -expand -group DDS -radix unsigned /l0_dds_reader_test4_arznriu/uut/max_samples_dds -add wave -noupdate -expand -group DDS -radix DDS_RETCODE /l0_dds_reader_test4_arznriu/uut/return_code_dds -add wave -noupdate -expand -group DDS /l0_dds_reader_test4_arznriu/uut/done_dds -add wave -noupdate -expand -group DDS -divider SI -add wave -noupdate -expand -group DDS -radix SAMPLE_STATE /l0_dds_reader_test4_arznriu/uut/si_sample_state -add wave -noupdate -expand -group DDS -radix VIEW_STATE /l0_dds_reader_test4_arznriu/uut/si_view_state -add wave -noupdate -expand -group DDS -radix INSTANCE_STATE /l0_dds_reader_test4_arznriu/uut/si_instance_state -add wave -noupdate -expand -group DDS -radix unsigned /l0_dds_reader_test4_arznriu/uut/si_source_timestamp -add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_reader_test4_arznriu/uut/si_instance_handle -add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_reader_test4_arznriu/uut/si_publication_handle -add wave -noupdate -expand -group DDS -radix unsigned /l0_dds_reader_test4_arznriu/uut/si_disposed_generation_count -add wave -noupdate -expand -group DDS -radix unsigned /l0_dds_reader_test4_arznriu/uut/si_no_writers_generation_count -add wave -noupdate -expand -group DDS -radix unsigned /l0_dds_reader_test4_arznriu/uut/si_sample_rank -add wave -noupdate -expand -group DDS -radix unsigned /l0_dds_reader_test4_arznriu/uut/si_generation_rank -add wave -noupdate -expand -group DDS -radix unsigned /l0_dds_reader_test4_arznriu/uut/si_absolute_generation_rank -add wave -noupdate -expand -group DDS /l0_dds_reader_test4_arznriu/uut/si_valid_data -add wave -noupdate -expand -group DDS /l0_dds_reader_test4_arznriu/uut/si_valid -add wave -noupdate -expand -group DDS /l0_dds_reader_test4_arznriu/uut/get_data_dds -add wave -noupdate -expand -group DDS /l0_dds_reader_test4_arznriu/uut/eoc -add wave -noupdate -expand -group DDS -divider OUTPUT -add wave -noupdate -expand -group DDS /l0_dds_reader_test4_arznriu/uut/ready_out_dds -add wave -noupdate -expand -group DDS /l0_dds_reader_test4_arznriu/uut/valid_out_dds -add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_reader_test4_arznriu/uut/data_out_dds -add wave -noupdate -expand -group DDS /l0_dds_reader_test4_arznriu/uut/last_word_out_dds -add wave -noupdate -divider {MAIN FSM} -add wave -noupdate /l0_dds_reader_test4_arznriu/uut/stage -add wave -noupdate /l0_dds_reader_test4_arznriu/uut/stage_next -add wave -noupdate /l0_dds_reader_test4_arznriu/uut/cnt -add wave -noupdate -divider MEMORY -add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test4_arznriu/uut/sample_abort_read -add wave -noupdate -group {SAMPLE MEM} -radix unsigned /l0_dds_reader_test4_arznriu/uut/sample_mem_ctrl_inst/addr -add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test4_arznriu/uut/sample_mem_ctrl_inst/read -add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test4_arznriu/uut/sample_mem_ctrl_inst/ready_in -add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test4_arznriu/uut/sample_mem_ctrl_inst/valid_in -add wave -noupdate -group {SAMPLE MEM} -radix hexadecimal /l0_dds_reader_test4_arznriu/uut/sample_mem_ctrl_inst/data_in -add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test4_arznriu/uut/sample_mem_ctrl_inst/ready_out -add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test4_arznriu/uut/sample_mem_ctrl_inst/valid_out -add wave -noupdate -group {SAMPLE MEM} -radix hexadecimal /l0_dds_reader_test4_arznriu/uut/sample_mem_ctrl_inst/data_out -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test4_arznriu/uut/payload_abort_read -add wave -noupdate -group {PAYLOAD MEM} -radix unsigned /l0_dds_reader_test4_arznriu/uut/payload_mem_ctrl_inst/addr -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test4_arznriu/uut/payload_mem_ctrl_inst/read -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test4_arznriu/uut/payload_mem_ctrl_inst/ready_in -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test4_arznriu/uut/payload_mem_ctrl_inst/valid_in -add wave -noupdate -group {PAYLOAD MEM} -radix hexadecimal /l0_dds_reader_test4_arznriu/uut/payload_mem_ctrl_inst/data_in -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test4_arznriu/uut/payload_mem_ctrl_inst/ready_out -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test4_arznriu/uut/payload_mem_ctrl_inst/valid_out -add wave -noupdate -group {PAYLOAD MEM} -radix hexadecimal /l0_dds_reader_test4_arznriu/uut/payload_mem_ctrl_inst/data_out -add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test4_arznriu/uut/inst_abort_read -add wave -noupdate -group {INSTANCE MEM} -radix unsigned /l0_dds_reader_test4_arznriu/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/addr -add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test4_arznriu/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/read -add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test4_arznriu/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/ready_in -add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test4_arznriu/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/valid_in -add wave -noupdate -group {INSTANCE MEM} -radix hexadecimal /l0_dds_reader_test4_arznriu/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/data_in -add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test4_arznriu/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/ready_out -add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test4_arznriu/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/valid_out -add wave -noupdate -group {INSTANCE MEM} -radix hexadecimal /l0_dds_reader_test4_arznriu/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/data_out -add wave -noupdate /l0_dds_reader_test4_arznriu/uut/inst_op_start -add wave -noupdate /l0_dds_reader_test4_arznriu/uut/inst_opcode -add wave -noupdate /l0_dds_reader_test4_arznriu/uut/inst_op_done -add wave -noupdate /l0_dds_reader_test4_arznriu/uut/inst_stage -add wave -noupdate /l0_dds_reader_test4_arznriu/uut/inst_stage_next -add wave -noupdate /l0_dds_reader_test4_arznriu/uut/inst_cnt -add wave -noupdate -radix unsigned /l0_dds_reader_test4_arznriu/uut/inst_addr_base -add wave -noupdate /l0_dds_reader_test4_arznriu/uut/inst_mem_fields -add wave -noupdate -childformat {{/l0_dds_reader_test4_arznriu/uut/inst_data.key_hash -radix hexadecimal} {/l0_dds_reader_test4_arznriu/uut/inst_data.status_info -radix binary} {/l0_dds_reader_test4_arznriu/uut/inst_data.sample_cnt -radix unsigned} {/l0_dds_reader_test4_arznriu/uut/inst_data.disposed_gen_cnt -radix unsigned} {/l0_dds_reader_test4_arznriu/uut/inst_data.no_writers_gen_cnt -radix unsigned} {/l0_dds_reader_test4_arznriu/uut/inst_data.ignore_deadline -radix unsigned} {/l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap -radix binary -childformat {{/l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0) -radix binary -childformat {{/l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(0) -radix binary} {/l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(1) -radix binary} {/l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(2) -radix binary} {/l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(3) -radix binary} {/l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(4) -radix binary} {/l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(5) -radix binary} {/l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(6) -radix binary} {/l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(7) -radix binary} {/l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(8) -radix binary} {/l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(9) -radix binary} {/l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(10) -radix binary} {/l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(11) -radix binary} {/l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(12) -radix binary} {/l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(13) -radix binary} {/l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(14) -radix binary} {/l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(15) -radix binary} {/l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(16) -radix binary} {/l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(17) -radix binary} {/l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(18) -radix binary} {/l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(19) -radix binary} {/l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(20) -radix binary} {/l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(21) -radix binary} {/l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(22) -radix binary} {/l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(23) -radix binary} {/l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(24) -radix binary} {/l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(25) -radix binary} {/l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(26) -radix binary} {/l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(27) -radix binary} {/l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(28) -radix binary} {/l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(29) -radix binary} {/l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(30) -radix binary} {/l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(31) -radix binary}}}}}} -expand -subitemconfig {/l0_dds_reader_test4_arznriu/uut/inst_data.key_hash {-height 15 -radix hexadecimal} /l0_dds_reader_test4_arznriu/uut/inst_data.status_info {-height 15 -radix binary} /l0_dds_reader_test4_arznriu/uut/inst_data.sample_cnt {-height 15 -radix unsigned} /l0_dds_reader_test4_arznriu/uut/inst_data.disposed_gen_cnt {-height 15 -radix unsigned} /l0_dds_reader_test4_arznriu/uut/inst_data.no_writers_gen_cnt {-height 15 -radix unsigned} /l0_dds_reader_test4_arznriu/uut/inst_data.ignore_deadline {-height 15 -radix unsigned} /l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap {-height 15 -radix binary -childformat {{/l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0) -radix binary -childformat {{/l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(0) -radix binary} {/l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(1) -radix binary} {/l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(2) -radix binary} {/l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(3) -radix binary} {/l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(4) -radix binary} {/l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(5) -radix binary} {/l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(6) -radix binary} {/l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(7) -radix binary} {/l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(8) -radix binary} {/l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(9) -radix binary} {/l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(10) -radix binary} {/l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(11) -radix binary} {/l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(12) -radix binary} {/l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(13) -radix binary} {/l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(14) -radix binary} {/l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(15) -radix binary} {/l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(16) -radix binary} {/l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(17) -radix binary} {/l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(18) -radix binary} {/l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(19) -radix binary} {/l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(20) -radix binary} {/l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(21) -radix binary} {/l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(22) -radix binary} {/l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(23) -radix binary} {/l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(24) -radix binary} {/l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(25) -radix binary} {/l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(26) -radix binary} {/l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(27) -radix binary} {/l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(28) -radix binary} {/l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(29) -radix binary} {/l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(30) -radix binary} {/l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(31) -radix binary}}}}} /l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0) {-height 15 -radix binary -childformat {{/l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(0) -radix binary} {/l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(1) -radix binary} {/l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(2) -radix binary} {/l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(3) -radix binary} {/l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(4) -radix binary} {/l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(5) -radix binary} {/l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(6) -radix binary} {/l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(7) -radix binary} {/l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(8) -radix binary} {/l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(9) -radix binary} {/l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(10) -radix binary} {/l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(11) -radix binary} {/l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(12) -radix binary} {/l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(13) -radix binary} {/l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(14) -radix binary} {/l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(15) -radix binary} {/l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(16) -radix binary} {/l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(17) -radix binary} {/l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(18) -radix binary} {/l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(19) -radix binary} {/l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(20) -radix binary} {/l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(21) -radix binary} {/l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(22) -radix binary} {/l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(23) -radix binary} {/l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(24) -radix binary} {/l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(25) -radix binary} {/l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(26) -radix binary} {/l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(27) -radix binary} {/l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(28) -radix binary} {/l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(29) -radix binary} {/l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(30) -radix binary} {/l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(31) -radix binary}}} /l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(0) {-height 15 -radix binary} /l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(1) {-height 15 -radix binary} /l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(2) {-height 15 -radix binary} /l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(3) {-height 15 -radix binary} /l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(4) {-height 15 -radix binary} /l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(5) {-height 15 -radix binary} /l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(6) {-height 15 -radix binary} /l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(7) {-height 15 -radix binary} /l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(8) {-height 15 -radix binary} /l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(9) {-height 15 -radix binary} /l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(10) {-height 15 -radix binary} /l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(11) {-height 15 -radix binary} /l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(12) {-height 15 -radix binary} /l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(13) {-height 15 -radix binary} /l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(14) {-height 15 -radix binary} /l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(15) {-height 15 -radix binary} /l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(16) {-height 15 -radix binary} /l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(17) {-height 15 -radix binary} /l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(18) {-height 15 -radix binary} /l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(19) {-height 15 -radix binary} /l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(20) {-height 15 -radix binary} /l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(21) {-height 15 -radix binary} /l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(22) {-height 15 -radix binary} /l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(23) {-height 15 -radix binary} /l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(24) {-height 15 -radix binary} /l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(25) {-height 15 -radix binary} /l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(26) {-height 15 -radix binary} /l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(27) {-height 15 -radix binary} /l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(28) {-height 15 -radix binary} /l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(29) {-height 15 -radix binary} /l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(30) {-height 15 -radix binary} /l0_dds_reader_test4_arznriu/uut/inst_data.writer_bitmap(0)(31) {-height 15 -radix binary}} /l0_dds_reader_test4_arznriu/uut/inst_data -add wave -noupdate -radix unsigned /l0_dds_reader_test4_arznriu/uut/inst_next_addr_base -add wave -noupdate -radix unsigned /l0_dds_reader_test4_arznriu/uut/inst_prev_addr_base -add wave -noupdate /l0_dds_reader_test4_arznriu/uut/current_imf -add wave -noupdate /l0_dds_reader_test4_arznriu/uut/stale_inst_cnt -add wave -noupdate -divider POINTERS -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test4_arznriu/uut/empty_sample_list_head -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test4_arznriu/uut/empty_sample_list_tail -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test4_arznriu/uut/empty_payload_list_head -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test4_arznriu/uut/oldest_sample -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test4_arznriu/uut/newest_sample -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test4_arznriu/uut/inst_empty_head -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test4_arznriu/uut/inst_occupied_head -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test4_arznriu/uut/cur_sample -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test4_arznriu/uut/next_sample -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test4_arznriu/uut/prev_sample -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test4_arznriu/uut/cur_payload -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test4_arznriu/uut/next_payload -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test4_arznriu/uut/cur_inst -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test4_arznriu/uut/next_inst -add wave -noupdate -divider TESTBENCH -add wave -noupdate -group TESTBENCH /l0_dds_reader_test4_arznriu/dds_start -add wave -noupdate -group TESTBENCH /l0_dds_reader_test4_arznriu/dds_stage -add wave -noupdate -group TESTBENCH /l0_dds_reader_test4_arznriu/dds_cnt -add wave -noupdate -group TESTBENCH /l0_dds_reader_test4_arznriu/dds_cnt2 -add wave -noupdate -group TESTBENCH /l0_dds_reader_test4_arznriu/dds_done -add wave -noupdate -group TESTBENCH /l0_dds_reader_test4_arznriu/rtps_start -add wave -noupdate -group TESTBENCH /l0_dds_reader_test4_arznriu/rtps_stage -add wave -noupdate -group TESTBENCH /l0_dds_reader_test4_arznriu/rtps_cnt -add wave -noupdate -group TESTBENCH /l0_dds_reader_test4_arznriu/rtps_done -add wave -noupdate -divider {KEY HOLDER} -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test4_arznriu/uut/start_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test4_arznriu/uut/opcode_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test4_arznriu/uut/ack_kh -add wave -noupdate -group {KEY HOLDER} -radix hexadecimal /l0_dds_reader_test4_arznriu/uut/data_in_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test4_arznriu/uut/valid_in_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test4_arznriu/uut/ready_in_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test4_arznriu/uut/last_word_in_kh -add wave -noupdate -group {KEY HOLDER} -radix hexadecimal /l0_dds_reader_test4_arznriu/uut/data_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test4_arznriu/uut/valid_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test4_arznriu/uut/ready_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test4_arznriu/uut/last_word_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test4_arznriu/uut/abort_kh -add wave -noupdate -divider MISC -add wave -noupdate -radix unsigned /l0_dds_reader_test4_arznriu/uut/collection_cnt -add wave -noupdate -radix unsigned /l0_dds_reader_test4_arznriu/uut/collection_cnt_max -add wave -noupdate -radix unsigned /l0_dds_reader_test4_arznriu/uut/collection_generation_rank -add wave -noupdate -radix unsigned /l0_dds_reader_test4_arznriu/uut/cur_generation_rank -add wave -noupdate -radix unsigned /l0_dds_reader_test4_arznriu/uut/max_samples_latch -add wave -noupdate /l0_dds_reader_test4_arznriu/uut/dynamic_next_instance -add wave -noupdate /l0_dds_reader_test4_arznriu/uut/single_instance -add wave -noupdate /l0_dds_reader_test4_arznriu/uut/is_take -add wave -noupdate -radix unsigned /l0_dds_reader_test4_arznriu/uut/sel_sample -add wave -noupdate -radix unsigned /l0_dds_reader_test4_arznriu/uut/sample_p1 -add wave -noupdate -radix unsigned /l0_dds_reader_test4_arznriu/uut/sample_p2 -add wave -noupdate -radix SAMPLE_STATE /l0_dds_reader_test4_arznriu/uut/sample_state -add wave -noupdate -radix VIEW_STATE /l0_dds_reader_test4_arznriu/uut/view_state -add wave -noupdate -radix INSTANCE_STATE /l0_dds_reader_test4_arznriu/uut/instance_state -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {262408405 ps} 0} {{Cursor 2} {115175000 ps} 1} -quietly wave cursor active 1 -configure wave -namecolwidth 187 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -configure wave -timelineunits ns -update -WaveRestoreZoom {261834536 ps} {262835177 ps} diff --git a/sim/L0_dds_reader_test5.do b/sim/L0_dds_reader_test5.do new file mode 100644 index 0000000..31a2cb5 --- /dev/null +++ b/sim/L0_dds_reader_test5.do @@ -0,0 +1,190 @@ +onerror {resume} +radix define DDS_RETCODE { + "10#0#" "RETCODE_OK", + "10#1#" "RETCODE_ERROR", + "10#2#" "RETCODE_UNSUPPORTED", + "10#3#" "RETCODE_BAD_PARAMETER", + "10#4#" "RETCODE_PRECONDITION_NOT_MET", + "10#5#" "RETCODE_OUT_OF_RESOURCES", + "10#6#" "RETCODE_NOT_ENABLED", + "10#7#" "RETCODE_IMMUTABLE_POLICY", + "10#8#" "RETCODE_INCONSISTENT_POLICY", + "10#9#" "RETCODE_ALREADY_DELETED", + "10#10#" "RETCODE_TIMEOUT", + "10#11#" "RETCODE_NO_DATA", + "10#12#" "RETCODE_ILLEGAL_OPERATION", + -default unsigned +} +radix define SAMPLE_STATE { + "16#00000001#" "READ_SAMPLE_STATE", + "16#00000002#" "NOT_READ_SAMPLE_STATE", + "16#FFFFFFFF#" "ANY_SAMPLE_STATE", + -default binary +} +radix define VIEW_STATE { + "16#00000001#" "NEW_VIEW_STATE", + "16#00000002#" "NOT_NEW_VIEW_STATE", + "16#FFFFFFFF#" "ANY_VIEW_STATE", + -default binary +} +radix define INSTANCE_STATE { + "16#00000001#" "ALIVE_INSTANCE_STATE", + "16#00000002#" "NOT_ALIVE_DISPOSED_INSTANCE_STATE", + "16#00000004#" "NOT_ALIVE_NO_WRITERS_INSTANCE_STATE", + "16#FFFFFFFF#" "ANY_INSTANCE_STATE", + -default binary +} +radix define LAST_REASON { + "16#00000000#" "NOT_REJECTED", + "16#00000001#" "REJECTED_BY_INSTANCES_LIMIT", + "16#00000002#" "REJECTED_BY_SAMPLES_LIMIT", + "16#00000003#" "REJECTED_BY_SAMPLES_PER_INSTANCE_LIMIT", + "16#000000FF#" "REJECTED_BY_PAYOAD_MEMORY_LIMIT", + -default binary +} +quietly WaveActivateNextPane {} 0 +add wave -noupdate -divider SYSTEM +add wave -noupdate /l0_dds_reader_test5/uut/clk +add wave -noupdate /l0_dds_reader_test5/uut/reset +add wave -noupdate -radix unsigned /l0_dds_reader_test5/uut/time +add wave -noupdate -divider RTPS +add wave -noupdate -group RTPS /l0_dds_reader_test5/uut/start_rtps +add wave -noupdate -group RTPS /l0_dds_reader_test5/uut/opcode_rtps +add wave -noupdate -group RTPS /l0_dds_reader_test5/uut/ack_rtps +add wave -noupdate -group RTPS /l0_dds_reader_test5/uut/ret_rtps +add wave -noupdate -group RTPS /l0_dds_reader_test5/uut/done_rtps +add wave -noupdate -group RTPS /l0_dds_reader_test5/uut/ready_in_rtps +add wave -noupdate -group RTPS /l0_dds_reader_test5/uut/valid_in_rtps +add wave -noupdate -group RTPS -radix hexadecimal /l0_dds_reader_test5/uut/data_in_rtps +add wave -noupdate -group RTPS /l0_dds_reader_test5/uut/last_word_in_rtps +add wave -noupdate -divider DDS +add wave -noupdate -group DDS /l0_dds_reader_test5/uut/start_dds +add wave -noupdate -group DDS /l0_dds_reader_test5/uut/ack_dds +add wave -noupdate -group DDS /l0_dds_reader_test5/uut/opcode_dds +add wave -noupdate -group DDS -radix SAMPLE_STATE /l0_dds_reader_test5/uut/sample_state_dds +add wave -noupdate -group DDS -radix INSTANCE_STATE /l0_dds_reader_test5/uut/instance_state_dds +add wave -noupdate -group DDS -radix VIEW_STATE /l0_dds_reader_test5/uut/view_state_dds +add wave -noupdate -group DDS -radix hexadecimal /l0_dds_reader_test5/uut/instance_handle_dds +add wave -noupdate -group DDS -radix unsigned /l0_dds_reader_test5/uut/max_samples_dds +add wave -noupdate -group DDS -radix DDS_RETCODE -childformat {{/l0_dds_reader_test5/uut/return_code_dds(0) -radix DDS_RETCODE} {/l0_dds_reader_test5/uut/return_code_dds(1) -radix DDS_RETCODE} {/l0_dds_reader_test5/uut/return_code_dds(2) -radix DDS_RETCODE} {/l0_dds_reader_test5/uut/return_code_dds(3) -radix DDS_RETCODE} {/l0_dds_reader_test5/uut/return_code_dds(4) -radix DDS_RETCODE} {/l0_dds_reader_test5/uut/return_code_dds(5) -radix DDS_RETCODE}} -subitemconfig {/l0_dds_reader_test5/uut/return_code_dds(0) {-height 15 -radix DDS_RETCODE} /l0_dds_reader_test5/uut/return_code_dds(1) {-height 15 -radix DDS_RETCODE} /l0_dds_reader_test5/uut/return_code_dds(2) {-height 15 -radix DDS_RETCODE} /l0_dds_reader_test5/uut/return_code_dds(3) {-height 15 -radix DDS_RETCODE} /l0_dds_reader_test5/uut/return_code_dds(4) {-height 15 -radix DDS_RETCODE} /l0_dds_reader_test5/uut/return_code_dds(5) {-height 15 -radix DDS_RETCODE}} /l0_dds_reader_test5/uut/return_code_dds +add wave -noupdate -group DDS /l0_dds_reader_test5/uut/done_dds +add wave -noupdate -group DDS -divider SI +add wave -noupdate -group DDS -radix hexadecimal -childformat {{/l0_dds_reader_test5/uut/sample_info(0) -radix hexadecimal -childformat {{/l0_dds_reader_test5/uut/sample_info(0).sample_state -radix hexadecimal} {/l0_dds_reader_test5/uut/sample_info(0).view_state -radix hexadecimal} {/l0_dds_reader_test5/uut/sample_info(0).instance_state -radix hexadecimal} {/l0_dds_reader_test5/uut/sample_info(0).source_timestamp -radix hexadecimal} {/l0_dds_reader_test5/uut/sample_info(0).instance_handle -radix hexadecimal} {/l0_dds_reader_test5/uut/sample_info(0).publication_handle -radix hexadecimal} {/l0_dds_reader_test5/uut/sample_info(0).disposed_generation_count -radix hexadecimal} {/l0_dds_reader_test5/uut/sample_info(0).no_writers_generation_count -radix hexadecimal} {/l0_dds_reader_test5/uut/sample_info(0).sample_rank -radix hexadecimal} {/l0_dds_reader_test5/uut/sample_info(0).generation_rank -radix hexadecimal} {/l0_dds_reader_test5/uut/sample_info(0).absolute_generation_rank -radix hexadecimal} {/l0_dds_reader_test5/uut/sample_info(0).valid_data -radix hexadecimal}}} {/l0_dds_reader_test5/uut/sample_info(1) -radix hexadecimal} {/l0_dds_reader_test5/uut/sample_info(2) -radix hexadecimal} {/l0_dds_reader_test5/uut/sample_info(3) -radix hexadecimal} {/l0_dds_reader_test5/uut/sample_info(4) -radix hexadecimal} {/l0_dds_reader_test5/uut/sample_info(5) -radix hexadecimal}} -subitemconfig {/l0_dds_reader_test5/uut/sample_info(0) {-height 15 -radix hexadecimal -childformat {{/l0_dds_reader_test5/uut/sample_info(0).sample_state -radix hexadecimal} {/l0_dds_reader_test5/uut/sample_info(0).view_state -radix hexadecimal} {/l0_dds_reader_test5/uut/sample_info(0).instance_state -radix hexadecimal} {/l0_dds_reader_test5/uut/sample_info(0).source_timestamp -radix hexadecimal} {/l0_dds_reader_test5/uut/sample_info(0).instance_handle -radix hexadecimal} {/l0_dds_reader_test5/uut/sample_info(0).publication_handle -radix hexadecimal} {/l0_dds_reader_test5/uut/sample_info(0).disposed_generation_count -radix hexadecimal} {/l0_dds_reader_test5/uut/sample_info(0).no_writers_generation_count -radix hexadecimal} {/l0_dds_reader_test5/uut/sample_info(0).sample_rank -radix hexadecimal} {/l0_dds_reader_test5/uut/sample_info(0).generation_rank -radix hexadecimal} {/l0_dds_reader_test5/uut/sample_info(0).absolute_generation_rank -radix hexadecimal} {/l0_dds_reader_test5/uut/sample_info(0).valid_data -radix hexadecimal}}} /l0_dds_reader_test5/uut/sample_info(0).sample_state {-height 15 -radix hexadecimal} /l0_dds_reader_test5/uut/sample_info(0).view_state {-height 15 -radix hexadecimal} /l0_dds_reader_test5/uut/sample_info(0).instance_state {-height 15 -radix hexadecimal} /l0_dds_reader_test5/uut/sample_info(0).source_timestamp {-height 15 -radix hexadecimal} /l0_dds_reader_test5/uut/sample_info(0).instance_handle {-height 15 -radix hexadecimal} /l0_dds_reader_test5/uut/sample_info(0).publication_handle {-height 15 -radix hexadecimal} /l0_dds_reader_test5/uut/sample_info(0).disposed_generation_count {-height 15 -radix hexadecimal} /l0_dds_reader_test5/uut/sample_info(0).no_writers_generation_count {-height 15 -radix hexadecimal} /l0_dds_reader_test5/uut/sample_info(0).sample_rank {-height 15 -radix hexadecimal} /l0_dds_reader_test5/uut/sample_info(0).generation_rank {-height 15 -radix hexadecimal} /l0_dds_reader_test5/uut/sample_info(0).absolute_generation_rank {-height 15 -radix hexadecimal} /l0_dds_reader_test5/uut/sample_info(0).valid_data {-height 15 -radix hexadecimal} /l0_dds_reader_test5/uut/sample_info(1) {-height 15 -radix hexadecimal} /l0_dds_reader_test5/uut/sample_info(2) {-height 15 -radix hexadecimal} /l0_dds_reader_test5/uut/sample_info(3) {-height 15 -radix hexadecimal} /l0_dds_reader_test5/uut/sample_info(4) {-height 15 -radix hexadecimal} /l0_dds_reader_test5/uut/sample_info(5) {-height 15 -radix hexadecimal}} /l0_dds_reader_test5/uut/sample_info +add wave -noupdate -group DDS /l0_dds_reader_test5/uut/sample_info_valid +add wave -noupdate -group DDS /l0_dds_reader_test5/uut/sample_info_ack +add wave -noupdate -group DDS /l0_dds_reader_test5/uut/eoc +add wave -noupdate -group DDS /l0_dds_reader_test5/uut/get_data_dds +add wave -noupdate -group DDS -divider OUTPUT +add wave -noupdate -group DDS /l0_dds_reader_test5/uut/ready_out_dds +add wave -noupdate -group DDS /l0_dds_reader_test5/uut/valid_out_dds +add wave -noupdate -group DDS -radix hexadecimal /l0_dds_reader_test5/uut/data_out_dds +add wave -noupdate -group DDS /l0_dds_reader_test5/uut/last_word_out_dds +add wave -noupdate -divider {MAIN FSM} +add wave -noupdate /l0_dds_reader_test5/uut/stage +add wave -noupdate /l0_dds_reader_test5/uut/cnt +add wave -noupdate /l0_dds_reader_test5/uut/ind +add wave -noupdate -divider MEMORY +add wave -noupdate /l0_dds_reader_test5/uut/inst_op_start +add wave -noupdate /l0_dds_reader_test5/uut/inst_opcode +add wave -noupdate /l0_dds_reader_test5/uut/inst_op_done +add wave -noupdate /l0_dds_reader_test5/uut/inst_stage +add wave -noupdate /l0_dds_reader_test5/uut/inst_cnt +add wave -noupdate -radix unsigned /l0_dds_reader_test5/uut/inst_addr_base +add wave -noupdate -childformat {{/l0_dds_reader_test5/uut/inst_data.addr -radix unsigned} {/l0_dds_reader_test5/uut/inst_data.key_hash -radix hexadecimal} {/l0_dds_reader_test5/uut/inst_data.status_info -radix binary} {/l0_dds_reader_test5/uut/inst_data.sample_cnt -radix unsigned} {/l0_dds_reader_test5/uut/inst_data.disposed_gen_cnt -radix unsigned} {/l0_dds_reader_test5/uut/inst_data.no_writers_gen_cnt -radix unsigned} {/l0_dds_reader_test5/uut/inst_data.ignore_deadline -radix unsigned} {/l0_dds_reader_test5/uut/inst_data.writer_bitmap -radix binary -childformat {{/l0_dds_reader_test5/uut/inst_data.writer_bitmap(0) -radix binary -childformat {{/l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(0) -radix binary} {/l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(1) -radix binary} {/l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(2) -radix binary} {/l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(3) -radix binary} {/l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(4) -radix binary} {/l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(5) -radix binary} {/l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(6) -radix binary} {/l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(7) -radix binary} {/l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(8) -radix binary} {/l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(9) -radix binary} {/l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(10) -radix binary} {/l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(11) -radix binary} {/l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(12) -radix binary} {/l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(13) -radix binary} {/l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(14) -radix binary} {/l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(15) -radix binary} {/l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(16) -radix binary} {/l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(17) -radix binary} {/l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(18) -radix binary} {/l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(19) -radix binary} {/l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(20) -radix binary} {/l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(21) -radix binary} {/l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(22) -radix binary} {/l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(23) -radix binary} {/l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(24) -radix binary} {/l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(25) -radix binary} {/l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(26) -radix binary} {/l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(27) -radix binary} {/l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(28) -radix binary} {/l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(29) -radix binary} {/l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(30) -radix binary} {/l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(31) -radix binary}}}}}} -expand -subitemconfig {/l0_dds_reader_test5/uut/inst_data.addr {-radix unsigned} /l0_dds_reader_test5/uut/inst_data.key_hash {-height 15 -radix hexadecimal} /l0_dds_reader_test5/uut/inst_data.status_info {-height 15 -radix binary} /l0_dds_reader_test5/uut/inst_data.sample_cnt {-height 15 -radix unsigned} /l0_dds_reader_test5/uut/inst_data.disposed_gen_cnt {-height 15 -radix unsigned} /l0_dds_reader_test5/uut/inst_data.no_writers_gen_cnt {-height 15 -radix unsigned} /l0_dds_reader_test5/uut/inst_data.ignore_deadline {-height 15 -radix unsigned} /l0_dds_reader_test5/uut/inst_data.writer_bitmap {-height 15 -radix binary -childformat {{/l0_dds_reader_test5/uut/inst_data.writer_bitmap(0) -radix binary -childformat {{/l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(0) -radix binary} {/l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(1) -radix binary} {/l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(2) -radix binary} {/l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(3) -radix binary} {/l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(4) -radix binary} {/l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(5) -radix binary} {/l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(6) -radix binary} {/l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(7) -radix binary} {/l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(8) -radix binary} {/l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(9) -radix binary} {/l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(10) -radix binary} {/l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(11) -radix binary} {/l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(12) -radix binary} {/l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(13) -radix binary} {/l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(14) -radix binary} {/l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(15) -radix binary} {/l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(16) -radix binary} {/l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(17) -radix binary} {/l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(18) -radix binary} {/l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(19) -radix binary} {/l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(20) -radix binary} {/l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(21) -radix binary} {/l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(22) -radix binary} {/l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(23) -radix binary} {/l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(24) -radix binary} {/l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(25) -radix binary} {/l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(26) -radix binary} {/l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(27) -radix binary} {/l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(28) -radix binary} {/l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(29) -radix binary} {/l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(30) -radix binary} {/l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(31) -radix binary}}}}} /l0_dds_reader_test5/uut/inst_data.writer_bitmap(0) {-height 15 -radix binary -childformat {{/l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(0) -radix binary} {/l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(1) -radix binary} {/l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(2) -radix binary} {/l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(3) -radix binary} {/l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(4) -radix binary} {/l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(5) -radix binary} {/l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(6) -radix binary} {/l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(7) -radix binary} {/l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(8) -radix binary} {/l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(9) -radix binary} {/l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(10) -radix binary} {/l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(11) -radix binary} {/l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(12) -radix binary} {/l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(13) -radix binary} {/l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(14) -radix binary} {/l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(15) -radix binary} {/l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(16) -radix binary} {/l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(17) -radix binary} {/l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(18) -radix binary} {/l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(19) -radix binary} {/l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(20) -radix binary} {/l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(21) -radix binary} {/l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(22) -radix binary} {/l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(23) -radix binary} {/l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(24) -radix binary} {/l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(25) -radix binary} {/l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(26) -radix binary} {/l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(27) -radix binary} {/l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(28) -radix binary} {/l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(29) -radix binary} {/l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(30) -radix binary} {/l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(31) -radix binary}}} /l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(0) {-height 15 -radix binary} /l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(1) {-height 15 -radix binary} /l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(2) {-height 15 -radix binary} /l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(3) {-height 15 -radix binary} /l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(4) {-height 15 -radix binary} /l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(5) {-height 15 -radix binary} /l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(6) {-height 15 -radix binary} /l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(7) {-height 15 -radix binary} /l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(8) {-height 15 -radix binary} /l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(9) {-height 15 -radix binary} /l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(10) {-height 15 -radix binary} /l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(11) {-height 15 -radix binary} /l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(12) {-height 15 -radix binary} /l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(13) {-height 15 -radix binary} /l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(14) {-height 15 -radix binary} /l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(15) {-height 15 -radix binary} /l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(16) {-height 15 -radix binary} /l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(17) {-height 15 -radix binary} /l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(18) {-height 15 -radix binary} /l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(19) {-height 15 -radix binary} /l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(20) {-height 15 -radix binary} /l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(21) {-height 15 -radix binary} /l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(22) {-height 15 -radix binary} /l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(23) {-height 15 -radix binary} /l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(24) {-height 15 -radix binary} /l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(25) {-height 15 -radix binary} /l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(26) {-height 15 -radix binary} /l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(27) {-height 15 -radix binary} /l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(28) {-height 15 -radix binary} /l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(29) {-height 15 -radix binary} /l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(30) {-height 15 -radix binary} /l0_dds_reader_test5/uut/inst_data.writer_bitmap(0)(31) {-height 15 -radix binary}} /l0_dds_reader_test5/uut/inst_data +add wave -noupdate /l0_dds_reader_test5/uut/stale_inst_cnt +add wave -noupdate -group {SAMPLE MEM} -radix unsigned /l0_dds_reader_test5/uut/sample_addr +add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test5/uut/sample_read +add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test5/uut/sample_ready_in +add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test5/uut/sample_valid_in +add wave -noupdate -group {SAMPLE MEM} -radix hexadecimal /l0_dds_reader_test5/uut/sample_write_data +add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test5/uut/sample_ready_out +add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test5/uut/sample_valid_out +add wave -noupdate -group {SAMPLE MEM} -radix hexadecimal /l0_dds_reader_test5/uut/sample_read_data +add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test5/uut/sample_abort_read +add wave -noupdate -group {PAYLOAD MEM} -radix unsigned /l0_dds_reader_test5/uut/payload_addr +add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test5/uut/payload_read +add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test5/uut/payload_ready_in +add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test5/uut/payload_valid_in +add wave -noupdate -group {PAYLOAD MEM} -radix hexadecimal /l0_dds_reader_test5/uut/payload_write_data +add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test5/uut/payload_ready_out +add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test5/uut/payload_valid_out +add wave -noupdate -group {PAYLOAD MEM} -radix hexadecimal /l0_dds_reader_test5/uut/payload_read_data +add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test5/uut/payload_abort_read +add wave -noupdate -group {INSTANCE MEM} -radix unsigned /l0_dds_reader_test5/uut/inst_addr +add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test5/uut/inst_read +add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test5/uut/inst_ready_in +add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test5/uut/inst_valid_in +add wave -noupdate -group {INSTANCE MEM} -radix hexadecimal /l0_dds_reader_test5/uut/inst_write_data +add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test5/uut/inst_ready_out +add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test5/uut/inst_valid_out +add wave -noupdate -group {INSTANCE MEM} -radix hexadecimal /l0_dds_reader_test5/uut/inst_read_data +add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test5/uut/inst_abort_read +add wave -noupdate -divider POINTERS +add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test5/uut/empty_sample_list_head +add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test5/uut/empty_sample_list_tail +add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test5/uut/empty_payload_list_head +add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test5/uut/oldest_sample +add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test5/uut/newest_sample +add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test5/uut/inst_empty_head +add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test5/uut/inst_occupied_head +add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test5/uut/cur_sample +add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test5/uut/next_sample +add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test5/uut/prev_sample +add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test5/uut/cur_payload +add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test5/uut/next_payload +add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test5/uut/cur_inst +add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test5/uut/next_inst +add wave -noupdate -divider MISC +add wave -noupdate /l0_dds_reader_test5/uut/trigger_sample_gen +add wave -noupdate /l0_dds_reader_test5/uut/wait_for_sample_removal +add wave -noupdate -radix unsigned /l0_dds_reader_test5/uut/sample_p1 +add wave -noupdate -radix unsigned /l0_dds_reader_test5/uut/sample_p2 +add wave -noupdate -radix unsigned /l0_dds_reader_test5/uut/collection_cnt +add wave -noupdate -radix unsigned /l0_dds_reader_test5/uut/collection_cnt_max +add wave -noupdate -radix unsigned /l0_dds_reader_test5/uut/collection_generation_rank +add wave -noupdate -radix unsigned /l0_dds_reader_test5/uut/cur_generation_rank +add wave -noupdate -radix unsigned -childformat {{/l0_dds_reader_test5/uut/max_samples_latch(31) -radix unsigned} {/l0_dds_reader_test5/uut/max_samples_latch(30) -radix unsigned} {/l0_dds_reader_test5/uut/max_samples_latch(29) -radix unsigned} {/l0_dds_reader_test5/uut/max_samples_latch(28) -radix unsigned} {/l0_dds_reader_test5/uut/max_samples_latch(27) -radix unsigned} {/l0_dds_reader_test5/uut/max_samples_latch(26) -radix unsigned} {/l0_dds_reader_test5/uut/max_samples_latch(25) -radix unsigned} {/l0_dds_reader_test5/uut/max_samples_latch(24) -radix unsigned} {/l0_dds_reader_test5/uut/max_samples_latch(23) -radix unsigned} {/l0_dds_reader_test5/uut/max_samples_latch(22) -radix unsigned} {/l0_dds_reader_test5/uut/max_samples_latch(21) -radix unsigned} {/l0_dds_reader_test5/uut/max_samples_latch(20) -radix unsigned} {/l0_dds_reader_test5/uut/max_samples_latch(19) -radix unsigned} {/l0_dds_reader_test5/uut/max_samples_latch(18) -radix unsigned} {/l0_dds_reader_test5/uut/max_samples_latch(17) -radix unsigned} {/l0_dds_reader_test5/uut/max_samples_latch(16) -radix unsigned} {/l0_dds_reader_test5/uut/max_samples_latch(15) -radix unsigned} {/l0_dds_reader_test5/uut/max_samples_latch(14) -radix unsigned} {/l0_dds_reader_test5/uut/max_samples_latch(13) -radix unsigned} {/l0_dds_reader_test5/uut/max_samples_latch(12) -radix unsigned} {/l0_dds_reader_test5/uut/max_samples_latch(11) -radix unsigned} {/l0_dds_reader_test5/uut/max_samples_latch(10) -radix unsigned} {/l0_dds_reader_test5/uut/max_samples_latch(9) -radix unsigned} {/l0_dds_reader_test5/uut/max_samples_latch(8) -radix unsigned} {/l0_dds_reader_test5/uut/max_samples_latch(7) -radix unsigned} {/l0_dds_reader_test5/uut/max_samples_latch(6) -radix unsigned} {/l0_dds_reader_test5/uut/max_samples_latch(5) -radix unsigned} {/l0_dds_reader_test5/uut/max_samples_latch(4) -radix unsigned} {/l0_dds_reader_test5/uut/max_samples_latch(3) -radix unsigned} {/l0_dds_reader_test5/uut/max_samples_latch(2) -radix unsigned} {/l0_dds_reader_test5/uut/max_samples_latch(1) -radix unsigned} {/l0_dds_reader_test5/uut/max_samples_latch(0) -radix unsigned}} -subitemconfig {/l0_dds_reader_test5/uut/max_samples_latch(31) {-height 15 -radix unsigned} /l0_dds_reader_test5/uut/max_samples_latch(30) {-height 15 -radix unsigned} /l0_dds_reader_test5/uut/max_samples_latch(29) {-height 15 -radix unsigned} /l0_dds_reader_test5/uut/max_samples_latch(28) {-height 15 -radix unsigned} /l0_dds_reader_test5/uut/max_samples_latch(27) {-height 15 -radix unsigned} /l0_dds_reader_test5/uut/max_samples_latch(26) {-height 15 -radix unsigned} /l0_dds_reader_test5/uut/max_samples_latch(25) {-height 15 -radix unsigned} /l0_dds_reader_test5/uut/max_samples_latch(24) {-height 15 -radix unsigned} /l0_dds_reader_test5/uut/max_samples_latch(23) {-height 15 -radix unsigned} /l0_dds_reader_test5/uut/max_samples_latch(22) {-height 15 -radix unsigned} /l0_dds_reader_test5/uut/max_samples_latch(21) {-height 15 -radix unsigned} /l0_dds_reader_test5/uut/max_samples_latch(20) {-height 15 -radix unsigned} /l0_dds_reader_test5/uut/max_samples_latch(19) {-height 15 -radix unsigned} /l0_dds_reader_test5/uut/max_samples_latch(18) {-height 15 -radix unsigned} /l0_dds_reader_test5/uut/max_samples_latch(17) {-height 15 -radix unsigned} /l0_dds_reader_test5/uut/max_samples_latch(16) {-height 15 -radix unsigned} /l0_dds_reader_test5/uut/max_samples_latch(15) {-height 15 -radix unsigned} /l0_dds_reader_test5/uut/max_samples_latch(14) {-height 15 -radix unsigned} /l0_dds_reader_test5/uut/max_samples_latch(13) {-height 15 -radix unsigned} /l0_dds_reader_test5/uut/max_samples_latch(12) {-height 15 -radix unsigned} /l0_dds_reader_test5/uut/max_samples_latch(11) {-height 15 -radix unsigned} /l0_dds_reader_test5/uut/max_samples_latch(10) {-height 15 -radix unsigned} /l0_dds_reader_test5/uut/max_samples_latch(9) {-height 15 -radix unsigned} /l0_dds_reader_test5/uut/max_samples_latch(8) {-height 15 -radix unsigned} /l0_dds_reader_test5/uut/max_samples_latch(7) {-height 15 -radix unsigned} /l0_dds_reader_test5/uut/max_samples_latch(6) {-height 15 -radix unsigned} /l0_dds_reader_test5/uut/max_samples_latch(5) {-height 15 -radix unsigned} /l0_dds_reader_test5/uut/max_samples_latch(4) {-height 15 -radix unsigned} /l0_dds_reader_test5/uut/max_samples_latch(3) {-height 15 -radix unsigned} /l0_dds_reader_test5/uut/max_samples_latch(2) {-height 15 -radix unsigned} /l0_dds_reader_test5/uut/max_samples_latch(1) {-height 15 -radix unsigned} /l0_dds_reader_test5/uut/max_samples_latch(0) {-height 15 -radix unsigned}} /l0_dds_reader_test5/uut/max_samples_latch +add wave -noupdate /l0_dds_reader_test5/uut/single_instance +add wave -noupdate /l0_dds_reader_test5/uut/is_take +add wave -noupdate -radix unsigned -childformat {{/l0_dds_reader_test5/uut/sample_rej_last_reason(0) -radix LAST_REASON} {/l0_dds_reader_test5/uut/sample_rej_last_reason(1) -radix LAST_REASON} {/l0_dds_reader_test5/uut/sample_rej_last_reason(2) -radix LAST_REASON} {/l0_dds_reader_test5/uut/sample_rej_last_reason(3) -radix LAST_REASON} {/l0_dds_reader_test5/uut/sample_rej_last_reason(4) -radix LAST_REASON} {/l0_dds_reader_test5/uut/sample_rej_last_reason(5) -radix LAST_REASON}} -subitemconfig {/l0_dds_reader_test5/uut/sample_rej_last_reason(0) {-radix LAST_REASON} /l0_dds_reader_test5/uut/sample_rej_last_reason(1) {-radix LAST_REASON} /l0_dds_reader_test5/uut/sample_rej_last_reason(2) {-radix LAST_REASON} /l0_dds_reader_test5/uut/sample_rej_last_reason(3) {-radix LAST_REASON} /l0_dds_reader_test5/uut/sample_rej_last_reason(4) {-radix LAST_REASON} /l0_dds_reader_test5/uut/sample_rej_last_reason(5) {-radix LAST_REASON}} /l0_dds_reader_test5/uut/sample_rej_last_reason +add wave -noupdate -divider TESTBENCH +add wave -noupdate -group TESTBENCH /l0_dds_reader_test5/dds_start +add wave -noupdate -group TESTBENCH /l0_dds_reader_test5/dds_stage +add wave -noupdate -group TESTBENCH /l0_dds_reader_test5/dds_cnt +add wave -noupdate -group TESTBENCH /l0_dds_reader_test5/dds_cnt2 +add wave -noupdate -group TESTBENCH /l0_dds_reader_test5/dds_done +add wave -noupdate -group TESTBENCH /l0_dds_reader_test5/rtps_start +add wave -noupdate -group TESTBENCH /l0_dds_reader_test5/rtps_stage +add wave -noupdate -group TESTBENCH /l0_dds_reader_test5/rtps_cnt +add wave -noupdate -group TESTBENCH /l0_dds_reader_test5/rtps_done +add wave -noupdate -divider {KEY HOLDER} +add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test5/uut/start_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test5/uut/opcode_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test5/uut/ack_kh +add wave -noupdate -group {KEY HOLDER} -radix hexadecimal /l0_dds_reader_test5/uut/data_in_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test5/uut/valid_in_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test5/uut/ready_in_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test5/uut/last_word_in_kh +add wave -noupdate -group {KEY HOLDER} -radix hexadecimal /l0_dds_reader_test5/uut/data_out_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test5/uut/valid_out_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test5/uut/ready_out_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test5/uut/last_word_out_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test5/uut/abort_kh +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {50639746 ps} 0} +quietly wave cursor active 1 +configure wave -namecolwidth 187 +configure wave -valuecolwidth 206 +configure wave -justifyvalue left +configure wave -signalnamewidth 1 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ns +update +WaveRestoreZoom {50034942 ps} {50968663 ps} diff --git a/sim/L0_dds_reader_test5_arzkriu.do b/sim/L0_dds_reader_test5_arzkriu.do deleted file mode 100644 index 1924091..0000000 --- a/sim/L0_dds_reader_test5_arzkriu.do +++ /dev/null @@ -1,198 +0,0 @@ -onerror {resume} -radix define DDS_RETCODE { - "10#0#" "RETCODE_OK", - "10#1#" "RETCODE_ERROR", - "10#2#" "RETCODE_UNSUPPORTED", - "10#3#" "RETCODE_BAD_PARAMETER", - "10#4#" "RETCODE_PRECONDITION_NOT_MET", - "10#5#" "RETCODE_OUT_OF_RESOURCES", - "10#6#" "RETCODE_NOT_ENABLED", - "10#7#" "RETCODE_IMMUTABLE_POLICY", - "10#8#" "RETCODE_INCONSISTENT_POLICY", - "10#9#" "RETCODE_ALREADY_DELETED", - "10#10#" "RETCODE_TIMEOUT", - "10#11#" "RETCODE_NO_DATA", - "10#12#" "RETCODE_ILLEGAL_OPERATION", - -default unsigned -} -radix define SAMPLE_STATE { - "16#00000001#" "READ_SAMPLE_STATE", - "16#00000002#" "NOT_READ_SAMPLE_STATE", - "16#FFFFFFFF#" "ANY_SAMPLE_STATE", - -default binary -} -radix define VIEW_STATE { - "16#00000001#" "NEW_VIEW_STATE", - "16#00000002#" "NOT_NEW_VIEW_STATE", - "16#FFFFFFFF#" "ANY_VIEW_STATE", - -default binary -} -radix define INSTANCE_STATE { - "16#00000001#" "ALIVE_INSTANCE_STATE", - "16#00000002#" "NOT_ALIVE_DISPOSED_INSTANCE_STATE", - "16#00000004#" "NOT_ALIVE_NO_WRITERS_INSTANCE_STATE", - "16#FFFFFFFF#" "ANY_INSTANCE_STATE", - -default binary -} -radix define LAST_REASON { - "16#00000000#" "NOT_REJECTED", - "16#00000001#" "REJECTED_BY_INSTANCES_LIMIT", - "16#00000002#" "REJECTED_BY_SAMPLES_LIMIT", - "16#00000003#" "REJECTED_BY_SAMPLES_PER_INSTANCE_LIMIT", - "16#000000FF#" "REJECTED_BY_PAYOAD_MEMORY_LIMIT", - -default binary -} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -divider SYSTEM -add wave -noupdate /l0_dds_reader_test5_arzkriu/uut/clk -add wave -noupdate /l0_dds_reader_test5_arzkriu/uut/reset -add wave -noupdate -radix unsigned /l0_dds_reader_test5_arzkriu/uut/time -add wave -noupdate -divider RTPS -add wave -noupdate -expand -group RTPS /l0_dds_reader_test5_arzkriu/uut/start_rtps -add wave -noupdate -expand -group RTPS /l0_dds_reader_test5_arzkriu/uut/opcode_rtps -add wave -noupdate -expand -group RTPS /l0_dds_reader_test5_arzkriu/uut/ack_rtps -add wave -noupdate -expand -group RTPS /l0_dds_reader_test5_arzkriu/uut/ret_rtps -add wave -noupdate -expand -group RTPS /l0_dds_reader_test5_arzkriu/uut/done_rtps -add wave -noupdate -expand -group RTPS /l0_dds_reader_test5_arzkriu/uut/ready_in_rtps -add wave -noupdate -expand -group RTPS /l0_dds_reader_test5_arzkriu/uut/valid_in_rtps -add wave -noupdate -expand -group RTPS -radix hexadecimal /l0_dds_reader_test5_arzkriu/uut/data_in_rtps -add wave -noupdate -expand -group RTPS /l0_dds_reader_test5_arzkriu/uut/last_word_in_rtps -add wave -noupdate -divider DDS -add wave -noupdate -group DDS /l0_dds_reader_test5_arzkriu/uut/start_dds -add wave -noupdate -group DDS /l0_dds_reader_test5_arzkriu/uut/ack_dds -add wave -noupdate -group DDS /l0_dds_reader_test5_arzkriu/uut/opcode_dds -add wave -noupdate -group DDS -radix SAMPLE_STATE /l0_dds_reader_test5_arzkriu/uut/sample_state_dds -add wave -noupdate -group DDS -radix INSTANCE_STATE /l0_dds_reader_test5_arzkriu/uut/instance_state_dds -add wave -noupdate -group DDS -radix VIEW_STATE /l0_dds_reader_test5_arzkriu/uut/view_state_dds -add wave -noupdate -group DDS -radix hexadecimal /l0_dds_reader_test5_arzkriu/uut/instance_handle_dds -add wave -noupdate -group DDS -radix unsigned /l0_dds_reader_test5_arzkriu/uut/max_samples_dds -add wave -noupdate -group DDS -radix DDS_RETCODE /l0_dds_reader_test5_arzkriu/uut/return_code_dds -add wave -noupdate -group DDS /l0_dds_reader_test5_arzkriu/uut/done_dds -add wave -noupdate -group DDS -divider SI -add wave -noupdate -group DDS -radix SAMPLE_STATE /l0_dds_reader_test5_arzkriu/uut/si_sample_state -add wave -noupdate -group DDS -radix VIEW_STATE /l0_dds_reader_test5_arzkriu/uut/si_view_state -add wave -noupdate -group DDS -radix INSTANCE_STATE /l0_dds_reader_test5_arzkriu/uut/si_instance_state -add wave -noupdate -group DDS -radix unsigned /l0_dds_reader_test5_arzkriu/uut/si_source_timestamp -add wave -noupdate -group DDS -radix hexadecimal /l0_dds_reader_test5_arzkriu/uut/si_instance_handle -add wave -noupdate -group DDS -radix hexadecimal /l0_dds_reader_test5_arzkriu/uut/si_publication_handle -add wave -noupdate -group DDS -radix unsigned /l0_dds_reader_test5_arzkriu/uut/si_disposed_generation_count -add wave -noupdate -group DDS -radix unsigned /l0_dds_reader_test5_arzkriu/uut/si_no_writers_generation_count -add wave -noupdate -group DDS -radix unsigned /l0_dds_reader_test5_arzkriu/uut/si_sample_rank -add wave -noupdate -group DDS -radix unsigned /l0_dds_reader_test5_arzkriu/uut/si_generation_rank -add wave -noupdate -group DDS -radix unsigned /l0_dds_reader_test5_arzkriu/uut/si_absolute_generation_rank -add wave -noupdate -group DDS /l0_dds_reader_test5_arzkriu/uut/si_valid_data -add wave -noupdate -group DDS /l0_dds_reader_test5_arzkriu/uut/si_valid -add wave -noupdate -group DDS /l0_dds_reader_test5_arzkriu/uut/get_data_dds -add wave -noupdate -group DDS /l0_dds_reader_test5_arzkriu/uut/eoc -add wave -noupdate -group DDS -divider OUTPUT -add wave -noupdate -group DDS /l0_dds_reader_test5_arzkriu/uut/ready_out_dds -add wave -noupdate -group DDS /l0_dds_reader_test5_arzkriu/uut/valid_out_dds -add wave -noupdate -group DDS -radix hexadecimal /l0_dds_reader_test5_arzkriu/uut/data_out_dds -add wave -noupdate -group DDS /l0_dds_reader_test5_arzkriu/uut/last_word_out_dds -add wave -noupdate -divider {MAIN FSM} -add wave -noupdate /l0_dds_reader_test5_arzkriu/uut/stage -add wave -noupdate /l0_dds_reader_test5_arzkriu/uut/stage_next -add wave -noupdate /l0_dds_reader_test5_arzkriu/uut/cnt -add wave -noupdate -divider MEMORY -add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test5_arzkriu/uut/sample_abort_read -add wave -noupdate -group {SAMPLE MEM} -radix unsigned /l0_dds_reader_test5_arzkriu/uut/sample_mem_ctrl_inst/addr -add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test5_arzkriu/uut/sample_mem_ctrl_inst/read -add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test5_arzkriu/uut/sample_mem_ctrl_inst/ready_in -add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test5_arzkriu/uut/sample_mem_ctrl_inst/valid_in -add wave -noupdate -group {SAMPLE MEM} -radix hexadecimal /l0_dds_reader_test5_arzkriu/uut/sample_mem_ctrl_inst/data_in -add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test5_arzkriu/uut/sample_mem_ctrl_inst/ready_out -add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test5_arzkriu/uut/sample_mem_ctrl_inst/valid_out -add wave -noupdate -group {SAMPLE MEM} -radix hexadecimal /l0_dds_reader_test5_arzkriu/uut/sample_mem_ctrl_inst/data_out -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test5_arzkriu/uut/payload_abort_read -add wave -noupdate -group {PAYLOAD MEM} -radix unsigned /l0_dds_reader_test5_arzkriu/uut/payload_mem_ctrl_inst/addr -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test5_arzkriu/uut/payload_mem_ctrl_inst/read -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test5_arzkriu/uut/payload_mem_ctrl_inst/ready_in -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test5_arzkriu/uut/payload_mem_ctrl_inst/valid_in -add wave -noupdate -group {PAYLOAD MEM} -radix hexadecimal /l0_dds_reader_test5_arzkriu/uut/payload_mem_ctrl_inst/data_in -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test5_arzkriu/uut/payload_mem_ctrl_inst/ready_out -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test5_arzkriu/uut/payload_mem_ctrl_inst/valid_out -add wave -noupdate -group {PAYLOAD MEM} -radix hexadecimal /l0_dds_reader_test5_arzkriu/uut/payload_mem_ctrl_inst/data_out -add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test5_arzkriu/uut/inst_abort_read -add wave -noupdate -group {INSTANCE MEM} -radix unsigned /l0_dds_reader_test5_arzkriu/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/addr -add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test5_arzkriu/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/read -add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test5_arzkriu/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/ready_in -add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test5_arzkriu/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/valid_in -add wave -noupdate -group {INSTANCE MEM} -radix hexadecimal /l0_dds_reader_test5_arzkriu/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/data_in -add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test5_arzkriu/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/ready_out -add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test5_arzkriu/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/valid_out -add wave -noupdate -group {INSTANCE MEM} -radix hexadecimal /l0_dds_reader_test5_arzkriu/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/data_out -add wave -noupdate /l0_dds_reader_test5_arzkriu/uut/inst_op_start -add wave -noupdate /l0_dds_reader_test5_arzkriu/uut/inst_opcode -add wave -noupdate /l0_dds_reader_test5_arzkriu/uut/inst_op_done -add wave -noupdate /l0_dds_reader_test5_arzkriu/uut/inst_stage -add wave -noupdate /l0_dds_reader_test5_arzkriu/uut/inst_stage_next -add wave -noupdate /l0_dds_reader_test5_arzkriu/uut/inst_cnt -add wave -noupdate -radix unsigned /l0_dds_reader_test5_arzkriu/uut/inst_addr_base -add wave -noupdate /l0_dds_reader_test5_arzkriu/uut/inst_mem_fields -add wave -noupdate -childformat {{/l0_dds_reader_test5_arzkriu/uut/inst_data.key_hash -radix hexadecimal} {/l0_dds_reader_test5_arzkriu/uut/inst_data.status_info -radix binary} {/l0_dds_reader_test5_arzkriu/uut/inst_data.sample_cnt -radix unsigned} {/l0_dds_reader_test5_arzkriu/uut/inst_data.disposed_gen_cnt -radix unsigned} {/l0_dds_reader_test5_arzkriu/uut/inst_data.no_writers_gen_cnt -radix unsigned} {/l0_dds_reader_test5_arzkriu/uut/inst_data.ignore_deadline -radix unsigned} {/l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap -radix binary -childformat {{/l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0) -radix binary -childformat {{/l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(0) -radix binary} {/l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(1) -radix binary} {/l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(2) -radix binary} {/l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(3) -radix binary} {/l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(4) -radix binary} {/l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(5) -radix binary} {/l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(6) -radix binary} {/l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(7) -radix binary} {/l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(8) -radix binary} {/l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(9) -radix binary} {/l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(10) -radix binary} {/l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(11) -radix binary} {/l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(12) -radix binary} {/l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(13) -radix binary} {/l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(14) -radix binary} {/l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(15) -radix binary} {/l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(16) -radix binary} {/l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(17) -radix binary} {/l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(18) -radix binary} {/l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(19) -radix binary} {/l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(20) -radix binary} {/l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(21) -radix binary} {/l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(22) -radix binary} {/l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(23) -radix binary} {/l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(24) -radix binary} {/l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(25) -radix binary} {/l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(26) -radix binary} {/l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(27) -radix binary} {/l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(28) -radix binary} {/l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(29) -radix binary} {/l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(30) -radix binary} {/l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(31) -radix binary}}}}}} -expand -subitemconfig {/l0_dds_reader_test5_arzkriu/uut/inst_data.key_hash {-height 15 -radix hexadecimal} /l0_dds_reader_test5_arzkriu/uut/inst_data.status_info {-height 15 -radix binary} /l0_dds_reader_test5_arzkriu/uut/inst_data.sample_cnt {-height 15 -radix unsigned} /l0_dds_reader_test5_arzkriu/uut/inst_data.disposed_gen_cnt {-height 15 -radix unsigned} /l0_dds_reader_test5_arzkriu/uut/inst_data.no_writers_gen_cnt {-height 15 -radix unsigned} /l0_dds_reader_test5_arzkriu/uut/inst_data.ignore_deadline {-height 15 -radix unsigned} /l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap {-height 15 -radix binary -childformat {{/l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0) -radix binary -childformat {{/l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(0) -radix binary} {/l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(1) -radix binary} {/l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(2) -radix binary} {/l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(3) -radix binary} {/l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(4) -radix binary} {/l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(5) -radix binary} {/l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(6) -radix binary} {/l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(7) -radix binary} {/l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(8) -radix binary} {/l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(9) -radix binary} {/l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(10) -radix binary} {/l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(11) -radix binary} {/l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(12) -radix binary} {/l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(13) -radix binary} {/l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(14) -radix binary} {/l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(15) -radix binary} {/l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(16) -radix binary} {/l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(17) -radix binary} {/l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(18) -radix binary} {/l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(19) -radix binary} {/l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(20) -radix binary} {/l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(21) -radix binary} {/l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(22) -radix binary} {/l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(23) -radix binary} {/l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(24) -radix binary} {/l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(25) -radix binary} {/l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(26) -radix binary} {/l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(27) -radix binary} {/l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(28) -radix binary} {/l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(29) -radix binary} {/l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(30) -radix binary} {/l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(31) -radix binary}}}}} /l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0) {-height 15 -radix binary -childformat {{/l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(0) -radix binary} {/l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(1) -radix binary} {/l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(2) -radix binary} {/l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(3) -radix binary} {/l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(4) -radix binary} {/l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(5) -radix binary} {/l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(6) -radix binary} {/l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(7) -radix binary} {/l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(8) -radix binary} {/l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(9) -radix binary} {/l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(10) -radix binary} {/l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(11) -radix binary} {/l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(12) -radix binary} {/l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(13) -radix binary} {/l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(14) -radix binary} {/l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(15) -radix binary} {/l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(16) -radix binary} {/l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(17) -radix binary} {/l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(18) -radix binary} {/l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(19) -radix binary} {/l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(20) -radix binary} {/l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(21) -radix binary} {/l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(22) -radix binary} {/l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(23) -radix binary} {/l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(24) -radix binary} {/l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(25) -radix binary} {/l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(26) -radix binary} {/l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(27) -radix binary} {/l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(28) -radix binary} {/l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(29) -radix binary} {/l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(30) -radix binary} {/l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(31) -radix binary}}} /l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(0) {-height 15 -radix binary} /l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(1) {-height 15 -radix binary} /l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(2) {-height 15 -radix binary} /l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(3) {-height 15 -radix binary} /l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(4) {-height 15 -radix binary} /l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(5) {-height 15 -radix binary} /l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(6) {-height 15 -radix binary} /l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(7) {-height 15 -radix binary} /l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(8) {-height 15 -radix binary} /l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(9) {-height 15 -radix binary} /l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(10) {-height 15 -radix binary} /l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(11) {-height 15 -radix binary} /l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(12) {-height 15 -radix binary} /l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(13) {-height 15 -radix binary} /l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(14) {-height 15 -radix binary} /l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(15) {-height 15 -radix binary} /l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(16) {-height 15 -radix binary} /l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(17) {-height 15 -radix binary} /l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(18) {-height 15 -radix binary} /l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(19) {-height 15 -radix binary} /l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(20) {-height 15 -radix binary} /l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(21) {-height 15 -radix binary} /l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(22) {-height 15 -radix binary} /l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(23) {-height 15 -radix binary} /l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(24) {-height 15 -radix binary} /l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(25) {-height 15 -radix binary} /l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(26) {-height 15 -radix binary} /l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(27) {-height 15 -radix binary} /l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(28) {-height 15 -radix binary} /l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(29) {-height 15 -radix binary} /l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(30) {-height 15 -radix binary} /l0_dds_reader_test5_arzkriu/uut/inst_data.writer_bitmap(0)(31) {-height 15 -radix binary}} /l0_dds_reader_test5_arzkriu/uut/inst_data -add wave -noupdate -radix unsigned /l0_dds_reader_test5_arzkriu/uut/inst_next_addr_base -add wave -noupdate -radix unsigned /l0_dds_reader_test5_arzkriu/uut/inst_prev_addr_base -add wave -noupdate /l0_dds_reader_test5_arzkriu/uut/current_imf -add wave -noupdate /l0_dds_reader_test5_arzkriu/uut/stale_inst_cnt -add wave -noupdate -divider POINTERS -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test5_arzkriu/uut/empty_sample_list_head -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test5_arzkriu/uut/empty_sample_list_tail -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test5_arzkriu/uut/empty_payload_list_head -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test5_arzkriu/uut/oldest_sample -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test5_arzkriu/uut/newest_sample -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test5_arzkriu/uut/inst_empty_head -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test5_arzkriu/uut/inst_occupied_head -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test5_arzkriu/uut/cur_sample -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test5_arzkriu/uut/next_sample -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test5_arzkriu/uut/prev_sample -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test5_arzkriu/uut/cur_payload -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test5_arzkriu/uut/next_payload -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test5_arzkriu/uut/cur_inst -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test5_arzkriu/uut/next_inst -add wave -noupdate -divider TESTBENCH -add wave -noupdate -group TESTBENCH /l0_dds_reader_test5_arzkriu/dds_start -add wave -noupdate -group TESTBENCH /l0_dds_reader_test5_arzkriu/dds_stage -add wave -noupdate -group TESTBENCH /l0_dds_reader_test5_arzkriu/dds_cnt -add wave -noupdate -group TESTBENCH /l0_dds_reader_test5_arzkriu/dds_cnt2 -add wave -noupdate -group TESTBENCH /l0_dds_reader_test5_arzkriu/dds_done -add wave -noupdate -group TESTBENCH /l0_dds_reader_test5_arzkriu/rtps_start -add wave -noupdate -group TESTBENCH /l0_dds_reader_test5_arzkriu/rtps_stage -add wave -noupdate -group TESTBENCH /l0_dds_reader_test5_arzkriu/rtps_cnt -add wave -noupdate -group TESTBENCH /l0_dds_reader_test5_arzkriu/rtps_done -add wave -noupdate -divider {KEY HOLDER} -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test5_arzkriu/uut/start_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test5_arzkriu/uut/opcode_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test5_arzkriu/uut/ack_kh -add wave -noupdate -group {KEY HOLDER} -radix hexadecimal /l0_dds_reader_test5_arzkriu/uut/data_in_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test5_arzkriu/uut/valid_in_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test5_arzkriu/uut/ready_in_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test5_arzkriu/uut/last_word_in_kh -add wave -noupdate -group {KEY HOLDER} -radix hexadecimal /l0_dds_reader_test5_arzkriu/uut/data_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test5_arzkriu/uut/valid_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test5_arzkriu/uut/ready_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test5_arzkriu/uut/last_word_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test5_arzkriu/uut/abort_kh -add wave -noupdate -divider MISC -add wave -noupdate /l0_dds_reader_test5_arzkriu/uut/status -add wave -noupdate -radix unsigned /l0_dds_reader_test5_arzkriu/uut/sample_rej_cnt -add wave -noupdate -radix unsigned /l0_dds_reader_test5_arzkriu/uut/sample_rej_cnt_change -add wave -noupdate /l0_dds_reader_test5_arzkriu/uut/sample_rej_last_reason -add wave -noupdate -radix hexadecimal /l0_dds_reader_test5_arzkriu/uut/sample_rej_last_inst -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {32825000 ps} 0} {{Cursor 2} {115175000 ps} 1} -quietly wave cursor active 1 -configure wave -namecolwidth 187 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -configure wave -timelineunits ns -update -WaveRestoreZoom {32324680 ps} {33325321 ps} diff --git a/sim/L0_dds_reader_test6.do b/sim/L0_dds_reader_test6.do new file mode 100644 index 0000000..9e1b6e1 --- /dev/null +++ b/sim/L0_dds_reader_test6.do @@ -0,0 +1,190 @@ +onerror {resume} +radix define DDS_RETCODE { + "10#0#" "RETCODE_OK", + "10#1#" "RETCODE_ERROR", + "10#2#" "RETCODE_UNSUPPORTED", + "10#3#" "RETCODE_BAD_PARAMETER", + "10#4#" "RETCODE_PRECONDITION_NOT_MET", + "10#5#" "RETCODE_OUT_OF_RESOURCES", + "10#6#" "RETCODE_NOT_ENABLED", + "10#7#" "RETCODE_IMMUTABLE_POLICY", + "10#8#" "RETCODE_INCONSISTENT_POLICY", + "10#9#" "RETCODE_ALREADY_DELETED", + "10#10#" "RETCODE_TIMEOUT", + "10#11#" "RETCODE_NO_DATA", + "10#12#" "RETCODE_ILLEGAL_OPERATION", + -default unsigned +} +radix define SAMPLE_STATE { + "16#00000001#" "READ_SAMPLE_STATE", + "16#00000002#" "NOT_READ_SAMPLE_STATE", + "16#FFFFFFFF#" "ANY_SAMPLE_STATE", + -default binary +} +radix define VIEW_STATE { + "16#00000001#" "NEW_VIEW_STATE", + "16#00000002#" "NOT_NEW_VIEW_STATE", + "16#FFFFFFFF#" "ANY_VIEW_STATE", + -default binary +} +radix define INSTANCE_STATE { + "16#00000001#" "ALIVE_INSTANCE_STATE", + "16#00000002#" "NOT_ALIVE_DISPOSED_INSTANCE_STATE", + "16#00000004#" "NOT_ALIVE_NO_WRITERS_INSTANCE_STATE", + "16#FFFFFFFF#" "ANY_INSTANCE_STATE", + -default binary +} +radix define LAST_REASON { + "16#00000000#" "NOT_REJECTED", + "16#00000001#" "REJECTED_BY_INSTANCES_LIMIT", + "16#00000002#" "REJECTED_BY_SAMPLES_LIMIT", + "16#00000003#" "REJECTED_BY_SAMPLES_PER_INSTANCE_LIMIT", + "16#000000FF#" "REJECTED_BY_PAYOAD_MEMORY_LIMIT", + -default binary +} +quietly WaveActivateNextPane {} 0 +add wave -noupdate -divider SYSTEM +add wave -noupdate /l0_dds_reader_test6/uut/clk +add wave -noupdate /l0_dds_reader_test6/uut/reset +add wave -noupdate -radix unsigned /l0_dds_reader_test6/uut/time +add wave -noupdate -divider RTPS +add wave -noupdate -group RTPS /l0_dds_reader_test6/uut/start_rtps +add wave -noupdate -group RTPS /l0_dds_reader_test6/uut/opcode_rtps +add wave -noupdate -group RTPS /l0_dds_reader_test6/uut/ack_rtps +add wave -noupdate -group RTPS /l0_dds_reader_test6/uut/ret_rtps +add wave -noupdate -group RTPS /l0_dds_reader_test6/uut/done_rtps +add wave -noupdate -group RTPS /l0_dds_reader_test6/uut/ready_in_rtps +add wave -noupdate -group RTPS /l0_dds_reader_test6/uut/valid_in_rtps +add wave -noupdate -group RTPS -radix hexadecimal /l0_dds_reader_test6/uut/data_in_rtps +add wave -noupdate -group RTPS /l0_dds_reader_test6/uut/last_word_in_rtps +add wave -noupdate -divider DDS +add wave -noupdate -group DDS /l0_dds_reader_test6/uut/start_dds +add wave -noupdate -group DDS /l0_dds_reader_test6/uut/ack_dds +add wave -noupdate -group DDS /l0_dds_reader_test6/uut/opcode_dds +add wave -noupdate -group DDS -radix SAMPLE_STATE /l0_dds_reader_test6/uut/sample_state_dds +add wave -noupdate -group DDS -radix INSTANCE_STATE /l0_dds_reader_test6/uut/instance_state_dds +add wave -noupdate -group DDS -radix VIEW_STATE /l0_dds_reader_test6/uut/view_state_dds +add wave -noupdate -group DDS -radix hexadecimal /l0_dds_reader_test6/uut/instance_handle_dds +add wave -noupdate -group DDS -radix unsigned /l0_dds_reader_test6/uut/max_samples_dds +add wave -noupdate -group DDS -radix DDS_RETCODE -childformat {{/l0_dds_reader_test6/uut/return_code_dds(0) -radix DDS_RETCODE} {/l0_dds_reader_test6/uut/return_code_dds(1) -radix DDS_RETCODE} {/l0_dds_reader_test6/uut/return_code_dds(2) -radix DDS_RETCODE} {/l0_dds_reader_test6/uut/return_code_dds(3) -radix DDS_RETCODE} {/l0_dds_reader_test6/uut/return_code_dds(4) -radix DDS_RETCODE} {/l0_dds_reader_test6/uut/return_code_dds(5) -radix DDS_RETCODE}} -subitemconfig {/l0_dds_reader_test6/uut/return_code_dds(0) {-height 15 -radix DDS_RETCODE} /l0_dds_reader_test6/uut/return_code_dds(1) {-height 15 -radix DDS_RETCODE} /l0_dds_reader_test6/uut/return_code_dds(2) {-height 15 -radix DDS_RETCODE} /l0_dds_reader_test6/uut/return_code_dds(3) {-height 15 -radix DDS_RETCODE} /l0_dds_reader_test6/uut/return_code_dds(4) {-height 15 -radix DDS_RETCODE} /l0_dds_reader_test6/uut/return_code_dds(5) {-height 15 -radix DDS_RETCODE}} /l0_dds_reader_test6/uut/return_code_dds +add wave -noupdate -group DDS /l0_dds_reader_test6/uut/done_dds +add wave -noupdate -group DDS -divider SI +add wave -noupdate -group DDS -radix hexadecimal -childformat {{/l0_dds_reader_test6/uut/sample_info(0) -radix hexadecimal -childformat {{/l0_dds_reader_test6/uut/sample_info(0).sample_state -radix hexadecimal} {/l0_dds_reader_test6/uut/sample_info(0).view_state -radix hexadecimal} {/l0_dds_reader_test6/uut/sample_info(0).instance_state -radix hexadecimal} {/l0_dds_reader_test6/uut/sample_info(0).source_timestamp -radix hexadecimal} {/l0_dds_reader_test6/uut/sample_info(0).instance_handle -radix hexadecimal} {/l0_dds_reader_test6/uut/sample_info(0).publication_handle -radix hexadecimal} {/l0_dds_reader_test6/uut/sample_info(0).disposed_generation_count -radix hexadecimal} {/l0_dds_reader_test6/uut/sample_info(0).no_writers_generation_count -radix hexadecimal} {/l0_dds_reader_test6/uut/sample_info(0).sample_rank -radix hexadecimal} {/l0_dds_reader_test6/uut/sample_info(0).generation_rank -radix hexadecimal} {/l0_dds_reader_test6/uut/sample_info(0).absolute_generation_rank -radix hexadecimal} {/l0_dds_reader_test6/uut/sample_info(0).valid_data -radix hexadecimal}}} {/l0_dds_reader_test6/uut/sample_info(1) -radix hexadecimal} {/l0_dds_reader_test6/uut/sample_info(2) -radix hexadecimal} {/l0_dds_reader_test6/uut/sample_info(3) -radix hexadecimal} {/l0_dds_reader_test6/uut/sample_info(4) -radix hexadecimal} {/l0_dds_reader_test6/uut/sample_info(5) -radix hexadecimal}} -subitemconfig {/l0_dds_reader_test6/uut/sample_info(0) {-height 15 -radix hexadecimal -childformat {{/l0_dds_reader_test6/uut/sample_info(0).sample_state -radix hexadecimal} {/l0_dds_reader_test6/uut/sample_info(0).view_state -radix hexadecimal} {/l0_dds_reader_test6/uut/sample_info(0).instance_state -radix hexadecimal} {/l0_dds_reader_test6/uut/sample_info(0).source_timestamp -radix hexadecimal} {/l0_dds_reader_test6/uut/sample_info(0).instance_handle -radix hexadecimal} {/l0_dds_reader_test6/uut/sample_info(0).publication_handle -radix hexadecimal} {/l0_dds_reader_test6/uut/sample_info(0).disposed_generation_count -radix hexadecimal} {/l0_dds_reader_test6/uut/sample_info(0).no_writers_generation_count -radix hexadecimal} {/l0_dds_reader_test6/uut/sample_info(0).sample_rank -radix hexadecimal} {/l0_dds_reader_test6/uut/sample_info(0).generation_rank -radix hexadecimal} {/l0_dds_reader_test6/uut/sample_info(0).absolute_generation_rank -radix hexadecimal} {/l0_dds_reader_test6/uut/sample_info(0).valid_data -radix hexadecimal}}} /l0_dds_reader_test6/uut/sample_info(0).sample_state {-height 15 -radix hexadecimal} /l0_dds_reader_test6/uut/sample_info(0).view_state {-height 15 -radix hexadecimal} /l0_dds_reader_test6/uut/sample_info(0).instance_state {-height 15 -radix hexadecimal} /l0_dds_reader_test6/uut/sample_info(0).source_timestamp {-height 15 -radix hexadecimal} /l0_dds_reader_test6/uut/sample_info(0).instance_handle {-height 15 -radix hexadecimal} /l0_dds_reader_test6/uut/sample_info(0).publication_handle {-height 15 -radix hexadecimal} /l0_dds_reader_test6/uut/sample_info(0).disposed_generation_count {-height 15 -radix hexadecimal} /l0_dds_reader_test6/uut/sample_info(0).no_writers_generation_count {-height 15 -radix hexadecimal} /l0_dds_reader_test6/uut/sample_info(0).sample_rank {-height 15 -radix hexadecimal} /l0_dds_reader_test6/uut/sample_info(0).generation_rank {-height 15 -radix hexadecimal} /l0_dds_reader_test6/uut/sample_info(0).absolute_generation_rank {-height 15 -radix hexadecimal} /l0_dds_reader_test6/uut/sample_info(0).valid_data {-height 15 -radix hexadecimal} /l0_dds_reader_test6/uut/sample_info(1) {-height 15 -radix hexadecimal} /l0_dds_reader_test6/uut/sample_info(2) {-height 15 -radix hexadecimal} /l0_dds_reader_test6/uut/sample_info(3) {-height 15 -radix hexadecimal} /l0_dds_reader_test6/uut/sample_info(4) {-height 15 -radix hexadecimal} /l0_dds_reader_test6/uut/sample_info(5) {-height 15 -radix hexadecimal}} /l0_dds_reader_test6/uut/sample_info +add wave -noupdate -group DDS /l0_dds_reader_test6/uut/sample_info_valid +add wave -noupdate -group DDS /l0_dds_reader_test6/uut/sample_info_ack +add wave -noupdate -group DDS /l0_dds_reader_test6/uut/eoc +add wave -noupdate -group DDS /l0_dds_reader_test6/uut/get_data_dds +add wave -noupdate -group DDS -divider OUTPUT +add wave -noupdate -group DDS /l0_dds_reader_test6/uut/ready_out_dds +add wave -noupdate -group DDS /l0_dds_reader_test6/uut/valid_out_dds +add wave -noupdate -group DDS -radix hexadecimal /l0_dds_reader_test6/uut/data_out_dds +add wave -noupdate -group DDS /l0_dds_reader_test6/uut/last_word_out_dds +add wave -noupdate -divider {MAIN FSM} +add wave -noupdate /l0_dds_reader_test6/uut/stage +add wave -noupdate /l0_dds_reader_test6/uut/cnt +add wave -noupdate /l0_dds_reader_test6/uut/ind +add wave -noupdate -divider MEMORY +add wave -noupdate /l0_dds_reader_test6/uut/inst_op_start +add wave -noupdate /l0_dds_reader_test6/uut/inst_opcode +add wave -noupdate /l0_dds_reader_test6/uut/inst_op_done +add wave -noupdate /l0_dds_reader_test6/uut/inst_stage +add wave -noupdate /l0_dds_reader_test6/uut/inst_cnt +add wave -noupdate -radix unsigned /l0_dds_reader_test6/uut/inst_addr_base +add wave -noupdate -childformat {{/l0_dds_reader_test6/uut/inst_data.addr -radix unsigned} {/l0_dds_reader_test6/uut/inst_data.key_hash -radix hexadecimal} {/l0_dds_reader_test6/uut/inst_data.status_info -radix binary} {/l0_dds_reader_test6/uut/inst_data.sample_cnt -radix unsigned} {/l0_dds_reader_test6/uut/inst_data.disposed_gen_cnt -radix unsigned} {/l0_dds_reader_test6/uut/inst_data.no_writers_gen_cnt -radix unsigned} {/l0_dds_reader_test6/uut/inst_data.ignore_deadline -radix unsigned} {/l0_dds_reader_test6/uut/inst_data.writer_bitmap -radix binary -childformat {{/l0_dds_reader_test6/uut/inst_data.writer_bitmap(0) -radix binary -childformat {{/l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(0) -radix binary} {/l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(1) -radix binary} {/l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(2) -radix binary} {/l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(3) -radix binary} {/l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(4) -radix binary} {/l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(5) -radix binary} {/l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(6) -radix binary} {/l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(7) -radix binary} {/l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(8) -radix binary} {/l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(9) -radix binary} {/l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(10) -radix binary} {/l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(11) -radix binary} {/l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(12) -radix binary} {/l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(13) -radix binary} {/l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(14) -radix binary} {/l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(15) -radix binary} {/l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(16) -radix binary} {/l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(17) -radix binary} {/l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(18) -radix binary} {/l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(19) -radix binary} {/l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(20) -radix binary} {/l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(21) -radix binary} {/l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(22) -radix binary} {/l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(23) -radix binary} {/l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(24) -radix binary} {/l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(25) -radix binary} {/l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(26) -radix binary} {/l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(27) -radix binary} {/l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(28) -radix binary} {/l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(29) -radix binary} {/l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(30) -radix binary} {/l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(31) -radix binary}}}}}} -expand -subitemconfig {/l0_dds_reader_test6/uut/inst_data.addr {-radix unsigned} /l0_dds_reader_test6/uut/inst_data.key_hash {-height 15 -radix hexadecimal} /l0_dds_reader_test6/uut/inst_data.status_info {-height 15 -radix binary} /l0_dds_reader_test6/uut/inst_data.sample_cnt {-height 15 -radix unsigned} /l0_dds_reader_test6/uut/inst_data.disposed_gen_cnt {-height 15 -radix unsigned} /l0_dds_reader_test6/uut/inst_data.no_writers_gen_cnt {-height 15 -radix unsigned} /l0_dds_reader_test6/uut/inst_data.ignore_deadline {-height 15 -radix unsigned} /l0_dds_reader_test6/uut/inst_data.writer_bitmap {-height 15 -radix binary -childformat {{/l0_dds_reader_test6/uut/inst_data.writer_bitmap(0) -radix binary -childformat {{/l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(0) -radix binary} {/l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(1) -radix binary} {/l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(2) -radix binary} {/l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(3) -radix binary} {/l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(4) -radix binary} {/l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(5) -radix binary} {/l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(6) -radix binary} {/l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(7) -radix binary} {/l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(8) -radix binary} {/l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(9) -radix binary} {/l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(10) -radix binary} {/l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(11) -radix binary} {/l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(12) -radix binary} {/l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(13) -radix binary} {/l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(14) -radix binary} {/l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(15) -radix binary} {/l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(16) -radix binary} {/l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(17) -radix binary} {/l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(18) -radix binary} {/l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(19) -radix binary} {/l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(20) -radix binary} {/l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(21) -radix binary} {/l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(22) -radix binary} {/l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(23) -radix binary} {/l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(24) -radix binary} {/l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(25) -radix binary} {/l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(26) -radix binary} {/l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(27) -radix binary} {/l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(28) -radix binary} {/l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(29) -radix binary} {/l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(30) -radix binary} {/l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(31) -radix binary}}}}} /l0_dds_reader_test6/uut/inst_data.writer_bitmap(0) {-height 15 -radix binary -childformat {{/l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(0) -radix binary} {/l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(1) -radix binary} {/l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(2) -radix binary} {/l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(3) -radix binary} {/l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(4) -radix binary} {/l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(5) -radix binary} {/l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(6) -radix binary} {/l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(7) -radix binary} {/l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(8) -radix binary} {/l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(9) -radix binary} {/l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(10) -radix binary} {/l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(11) -radix binary} {/l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(12) -radix binary} {/l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(13) -radix binary} {/l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(14) -radix binary} {/l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(15) -radix binary} {/l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(16) -radix binary} {/l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(17) -radix binary} {/l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(18) -radix binary} {/l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(19) -radix binary} {/l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(20) -radix binary} {/l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(21) -radix binary} {/l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(22) -radix binary} {/l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(23) -radix binary} {/l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(24) -radix binary} {/l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(25) -radix binary} {/l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(26) -radix binary} {/l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(27) -radix binary} {/l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(28) -radix binary} {/l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(29) -radix binary} {/l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(30) -radix binary} {/l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(31) -radix binary}}} /l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(0) {-height 15 -radix binary} /l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(1) {-height 15 -radix binary} /l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(2) {-height 15 -radix binary} /l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(3) {-height 15 -radix binary} /l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(4) {-height 15 -radix binary} /l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(5) {-height 15 -radix binary} /l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(6) {-height 15 -radix binary} /l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(7) {-height 15 -radix binary} /l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(8) {-height 15 -radix binary} /l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(9) {-height 15 -radix binary} /l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(10) {-height 15 -radix binary} /l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(11) {-height 15 -radix binary} /l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(12) {-height 15 -radix binary} /l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(13) {-height 15 -radix binary} /l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(14) {-height 15 -radix binary} /l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(15) {-height 15 -radix binary} /l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(16) {-height 15 -radix binary} /l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(17) {-height 15 -radix binary} /l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(18) {-height 15 -radix binary} /l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(19) {-height 15 -radix binary} /l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(20) {-height 15 -radix binary} /l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(21) {-height 15 -radix binary} /l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(22) {-height 15 -radix binary} /l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(23) {-height 15 -radix binary} /l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(24) {-height 15 -radix binary} /l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(25) {-height 15 -radix binary} /l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(26) {-height 15 -radix binary} /l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(27) {-height 15 -radix binary} /l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(28) {-height 15 -radix binary} /l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(29) {-height 15 -radix binary} /l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(30) {-height 15 -radix binary} /l0_dds_reader_test6/uut/inst_data.writer_bitmap(0)(31) {-height 15 -radix binary}} /l0_dds_reader_test6/uut/inst_data +add wave -noupdate /l0_dds_reader_test6/uut/stale_inst_cnt +add wave -noupdate -group {SAMPLE MEM} -radix unsigned /l0_dds_reader_test6/uut/sample_addr +add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test6/uut/sample_read +add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test6/uut/sample_ready_in +add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test6/uut/sample_valid_in +add wave -noupdate -group {SAMPLE MEM} -radix hexadecimal /l0_dds_reader_test6/uut/sample_write_data +add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test6/uut/sample_ready_out +add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test6/uut/sample_valid_out +add wave -noupdate -group {SAMPLE MEM} -radix hexadecimal /l0_dds_reader_test6/uut/sample_read_data +add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test6/uut/sample_abort_read +add wave -noupdate -group {PAYLOAD MEM} -radix unsigned /l0_dds_reader_test6/uut/payload_addr +add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test6/uut/payload_read +add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test6/uut/payload_ready_in +add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test6/uut/payload_valid_in +add wave -noupdate -group {PAYLOAD MEM} -radix hexadecimal /l0_dds_reader_test6/uut/payload_write_data +add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test6/uut/payload_ready_out +add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test6/uut/payload_valid_out +add wave -noupdate -group {PAYLOAD MEM} -radix hexadecimal /l0_dds_reader_test6/uut/payload_read_data +add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test6/uut/payload_abort_read +add wave -noupdate -group {INSTANCE MEM} -radix unsigned /l0_dds_reader_test6/uut/inst_addr +add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test6/uut/inst_read +add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test6/uut/inst_ready_in +add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test6/uut/inst_valid_in +add wave -noupdate -group {INSTANCE MEM} -radix hexadecimal /l0_dds_reader_test6/uut/inst_write_data +add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test6/uut/inst_ready_out +add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test6/uut/inst_valid_out +add wave -noupdate -group {INSTANCE MEM} -radix hexadecimal /l0_dds_reader_test6/uut/inst_read_data +add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test6/uut/inst_abort_read +add wave -noupdate -divider POINTERS +add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test6/uut/empty_sample_list_head +add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test6/uut/empty_sample_list_tail +add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test6/uut/empty_payload_list_head +add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test6/uut/oldest_sample +add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test6/uut/newest_sample +add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test6/uut/inst_empty_head +add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test6/uut/inst_occupied_head +add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test6/uut/cur_sample +add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test6/uut/next_sample +add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test6/uut/prev_sample +add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test6/uut/cur_payload +add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test6/uut/next_payload +add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test6/uut/cur_inst +add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test6/uut/next_inst +add wave -noupdate -divider MISC +add wave -noupdate /l0_dds_reader_test6/uut/trigger_sample_gen +add wave -noupdate /l0_dds_reader_test6/uut/wait_for_sample_removal +add wave -noupdate -radix unsigned /l0_dds_reader_test6/uut/sample_p1 +add wave -noupdate -radix unsigned /l0_dds_reader_test6/uut/sample_p2 +add wave -noupdate -radix unsigned /l0_dds_reader_test6/uut/collection_cnt +add wave -noupdate -radix unsigned /l0_dds_reader_test6/uut/collection_cnt_max +add wave -noupdate -radix unsigned /l0_dds_reader_test6/uut/collection_generation_rank +add wave -noupdate -radix unsigned /l0_dds_reader_test6/uut/cur_generation_rank +add wave -noupdate -radix unsigned -childformat {{/l0_dds_reader_test6/uut/max_samples_latch(31) -radix unsigned} {/l0_dds_reader_test6/uut/max_samples_latch(30) -radix unsigned} {/l0_dds_reader_test6/uut/max_samples_latch(29) -radix unsigned} {/l0_dds_reader_test6/uut/max_samples_latch(28) -radix unsigned} {/l0_dds_reader_test6/uut/max_samples_latch(27) -radix unsigned} {/l0_dds_reader_test6/uut/max_samples_latch(26) -radix unsigned} {/l0_dds_reader_test6/uut/max_samples_latch(25) -radix unsigned} {/l0_dds_reader_test6/uut/max_samples_latch(24) -radix unsigned} {/l0_dds_reader_test6/uut/max_samples_latch(23) -radix unsigned} {/l0_dds_reader_test6/uut/max_samples_latch(22) -radix unsigned} {/l0_dds_reader_test6/uut/max_samples_latch(21) -radix unsigned} {/l0_dds_reader_test6/uut/max_samples_latch(20) -radix unsigned} {/l0_dds_reader_test6/uut/max_samples_latch(19) -radix unsigned} {/l0_dds_reader_test6/uut/max_samples_latch(18) -radix unsigned} {/l0_dds_reader_test6/uut/max_samples_latch(17) -radix unsigned} {/l0_dds_reader_test6/uut/max_samples_latch(16) -radix unsigned} {/l0_dds_reader_test6/uut/max_samples_latch(15) -radix unsigned} {/l0_dds_reader_test6/uut/max_samples_latch(14) -radix unsigned} {/l0_dds_reader_test6/uut/max_samples_latch(13) -radix unsigned} {/l0_dds_reader_test6/uut/max_samples_latch(12) -radix unsigned} {/l0_dds_reader_test6/uut/max_samples_latch(11) -radix unsigned} {/l0_dds_reader_test6/uut/max_samples_latch(10) -radix unsigned} {/l0_dds_reader_test6/uut/max_samples_latch(9) -radix unsigned} {/l0_dds_reader_test6/uut/max_samples_latch(8) -radix unsigned} {/l0_dds_reader_test6/uut/max_samples_latch(7) -radix unsigned} {/l0_dds_reader_test6/uut/max_samples_latch(6) -radix unsigned} {/l0_dds_reader_test6/uut/max_samples_latch(5) -radix unsigned} {/l0_dds_reader_test6/uut/max_samples_latch(4) -radix unsigned} {/l0_dds_reader_test6/uut/max_samples_latch(3) -radix unsigned} {/l0_dds_reader_test6/uut/max_samples_latch(2) -radix unsigned} {/l0_dds_reader_test6/uut/max_samples_latch(1) -radix unsigned} {/l0_dds_reader_test6/uut/max_samples_latch(0) -radix unsigned}} -subitemconfig {/l0_dds_reader_test6/uut/max_samples_latch(31) {-height 15 -radix unsigned} /l0_dds_reader_test6/uut/max_samples_latch(30) {-height 15 -radix unsigned} /l0_dds_reader_test6/uut/max_samples_latch(29) {-height 15 -radix unsigned} /l0_dds_reader_test6/uut/max_samples_latch(28) {-height 15 -radix unsigned} /l0_dds_reader_test6/uut/max_samples_latch(27) {-height 15 -radix unsigned} /l0_dds_reader_test6/uut/max_samples_latch(26) {-height 15 -radix unsigned} /l0_dds_reader_test6/uut/max_samples_latch(25) {-height 15 -radix unsigned} /l0_dds_reader_test6/uut/max_samples_latch(24) {-height 15 -radix unsigned} /l0_dds_reader_test6/uut/max_samples_latch(23) {-height 15 -radix unsigned} /l0_dds_reader_test6/uut/max_samples_latch(22) {-height 15 -radix unsigned} /l0_dds_reader_test6/uut/max_samples_latch(21) {-height 15 -radix unsigned} /l0_dds_reader_test6/uut/max_samples_latch(20) {-height 15 -radix unsigned} /l0_dds_reader_test6/uut/max_samples_latch(19) {-height 15 -radix unsigned} /l0_dds_reader_test6/uut/max_samples_latch(18) {-height 15 -radix unsigned} /l0_dds_reader_test6/uut/max_samples_latch(17) {-height 15 -radix unsigned} /l0_dds_reader_test6/uut/max_samples_latch(16) {-height 15 -radix unsigned} /l0_dds_reader_test6/uut/max_samples_latch(15) {-height 15 -radix unsigned} /l0_dds_reader_test6/uut/max_samples_latch(14) {-height 15 -radix unsigned} /l0_dds_reader_test6/uut/max_samples_latch(13) {-height 15 -radix unsigned} /l0_dds_reader_test6/uut/max_samples_latch(12) {-height 15 -radix unsigned} /l0_dds_reader_test6/uut/max_samples_latch(11) {-height 15 -radix unsigned} /l0_dds_reader_test6/uut/max_samples_latch(10) {-height 15 -radix unsigned} /l0_dds_reader_test6/uut/max_samples_latch(9) {-height 15 -radix unsigned} /l0_dds_reader_test6/uut/max_samples_latch(8) {-height 15 -radix unsigned} /l0_dds_reader_test6/uut/max_samples_latch(7) {-height 15 -radix unsigned} /l0_dds_reader_test6/uut/max_samples_latch(6) {-height 15 -radix unsigned} /l0_dds_reader_test6/uut/max_samples_latch(5) {-height 15 -radix unsigned} /l0_dds_reader_test6/uut/max_samples_latch(4) {-height 15 -radix unsigned} /l0_dds_reader_test6/uut/max_samples_latch(3) {-height 15 -radix unsigned} /l0_dds_reader_test6/uut/max_samples_latch(2) {-height 15 -radix unsigned} /l0_dds_reader_test6/uut/max_samples_latch(1) {-height 15 -radix unsigned} /l0_dds_reader_test6/uut/max_samples_latch(0) {-height 15 -radix unsigned}} /l0_dds_reader_test6/uut/max_samples_latch +add wave -noupdate /l0_dds_reader_test6/uut/single_instance +add wave -noupdate /l0_dds_reader_test6/uut/is_take +add wave -noupdate -radix unsigned -childformat {{/l0_dds_reader_test6/uut/sample_rej_last_reason(0) -radix LAST_REASON} {/l0_dds_reader_test6/uut/sample_rej_last_reason(1) -radix LAST_REASON} {/l0_dds_reader_test6/uut/sample_rej_last_reason(2) -radix LAST_REASON} {/l0_dds_reader_test6/uut/sample_rej_last_reason(3) -radix LAST_REASON} {/l0_dds_reader_test6/uut/sample_rej_last_reason(4) -radix LAST_REASON} {/l0_dds_reader_test6/uut/sample_rej_last_reason(5) -radix LAST_REASON}} -subitemconfig {/l0_dds_reader_test6/uut/sample_rej_last_reason(0) {-radix LAST_REASON} /l0_dds_reader_test6/uut/sample_rej_last_reason(1) {-radix LAST_REASON} /l0_dds_reader_test6/uut/sample_rej_last_reason(2) {-radix LAST_REASON} /l0_dds_reader_test6/uut/sample_rej_last_reason(3) {-radix LAST_REASON} /l0_dds_reader_test6/uut/sample_rej_last_reason(4) {-radix LAST_REASON} /l0_dds_reader_test6/uut/sample_rej_last_reason(5) {-radix LAST_REASON}} /l0_dds_reader_test6/uut/sample_rej_last_reason +add wave -noupdate -divider TESTBENCH +add wave -noupdate -group TESTBENCH /l0_dds_reader_test6/dds_start +add wave -noupdate -group TESTBENCH /l0_dds_reader_test6/dds_stage +add wave -noupdate -group TESTBENCH /l0_dds_reader_test6/dds_cnt +add wave -noupdate -group TESTBENCH /l0_dds_reader_test6/dds_cnt2 +add wave -noupdate -group TESTBENCH /l0_dds_reader_test6/dds_done +add wave -noupdate -group TESTBENCH /l0_dds_reader_test6/rtps_start +add wave -noupdate -group TESTBENCH /l0_dds_reader_test6/rtps_stage +add wave -noupdate -group TESTBENCH /l0_dds_reader_test6/rtps_cnt +add wave -noupdate -group TESTBENCH /l0_dds_reader_test6/rtps_done +add wave -noupdate -divider {KEY HOLDER} +add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test6/uut/start_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test6/uut/opcode_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test6/uut/ack_kh +add wave -noupdate -group {KEY HOLDER} -radix hexadecimal /l0_dds_reader_test6/uut/data_in_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test6/uut/valid_in_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test6/uut/ready_in_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test6/uut/last_word_in_kh +add wave -noupdate -group {KEY HOLDER} -radix hexadecimal /l0_dds_reader_test6/uut/data_out_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test6/uut/valid_out_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test6/uut/ready_out_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test6/uut/last_word_out_kh +add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test6/uut/abort_kh +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {50639746 ps} 0} +quietly wave cursor active 1 +configure wave -namecolwidth 187 +configure wave -valuecolwidth 206 +configure wave -justifyvalue left +configure wave -signalnamewidth 1 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ns +update +WaveRestoreZoom {50034942 ps} {50968663 ps} diff --git a/sim/L0_dds_reader_test6_arzkriu.do b/sim/L0_dds_reader_test6_arzkriu.do deleted file mode 100644 index 2ad2f4c..0000000 --- a/sim/L0_dds_reader_test6_arzkriu.do +++ /dev/null @@ -1,199 +0,0 @@ -onerror {resume} -radix define DDS_RETCODE { - "10#0#" "RETCODE_OK", - "10#1#" "RETCODE_ERROR", - "10#2#" "RETCODE_UNSUPPORTED", - "10#3#" "RETCODE_BAD_PARAMETER", - "10#4#" "RETCODE_PRECONDITION_NOT_MET", - "10#5#" "RETCODE_OUT_OF_RESOURCES", - "10#6#" "RETCODE_NOT_ENABLED", - "10#7#" "RETCODE_IMMUTABLE_POLICY", - "10#8#" "RETCODE_INCONSISTENT_POLICY", - "10#9#" "RETCODE_ALREADY_DELETED", - "10#10#" "RETCODE_TIMEOUT", - "10#11#" "RETCODE_NO_DATA", - "10#12#" "RETCODE_ILLEGAL_OPERATION", - -default unsigned -} -radix define SAMPLE_STATE { - "16#00000001#" "READ_SAMPLE_STATE", - "16#00000002#" "NOT_READ_SAMPLE_STATE", - "16#FFFFFFFF#" "ANY_SAMPLE_STATE", - -default binary -} -radix define VIEW_STATE { - "16#00000001#" "NEW_VIEW_STATE", - "16#00000002#" "NOT_NEW_VIEW_STATE", - "16#FFFFFFFF#" "ANY_VIEW_STATE", - -default binary -} -radix define INSTANCE_STATE { - "16#00000001#" "ALIVE_INSTANCE_STATE", - "16#00000002#" "NOT_ALIVE_DISPOSED_INSTANCE_STATE", - "16#00000004#" "NOT_ALIVE_NO_WRITERS_INSTANCE_STATE", - "16#FFFFFFFF#" "ANY_INSTANCE_STATE", - -default binary -} -radix define LAST_REASON { - "16#00000000#" "NOT_REJECTED", - "16#00000001#" "REJECTED_BY_INSTANCES_LIMIT", - "16#00000002#" "REJECTED_BY_SAMPLES_LIMIT", - "16#00000003#" "REJECTED_BY_SAMPLES_PER_INSTANCE_LIMIT", - "16#000000FF#" "REJECTED_BY_PAYOAD_MEMORY_LIMIT", - -default binary -} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -divider SYSTEM -add wave -noupdate /l0_dds_reader_test6_arzkriu/uut/clk -add wave -noupdate /l0_dds_reader_test6_arzkriu/uut/reset -add wave -noupdate -radix unsigned /l0_dds_reader_test6_arzkriu/uut/time -add wave -noupdate -radix unsigned /l0_dds_reader_test6_arzkriu/uut/lifespan_time -add wave -noupdate -divider RTPS -add wave -noupdate -expand -group RTPS /l0_dds_reader_test6_arzkriu/uut/start_rtps -add wave -noupdate -expand -group RTPS /l0_dds_reader_test6_arzkriu/uut/opcode_rtps -add wave -noupdate -expand -group RTPS /l0_dds_reader_test6_arzkriu/uut/ack_rtps -add wave -noupdate -expand -group RTPS /l0_dds_reader_test6_arzkriu/uut/ret_rtps -add wave -noupdate -expand -group RTPS /l0_dds_reader_test6_arzkriu/uut/done_rtps -add wave -noupdate -expand -group RTPS /l0_dds_reader_test6_arzkriu/uut/ready_in_rtps -add wave -noupdate -expand -group RTPS /l0_dds_reader_test6_arzkriu/uut/valid_in_rtps -add wave -noupdate -expand -group RTPS -radix hexadecimal /l0_dds_reader_test6_arzkriu/uut/data_in_rtps -add wave -noupdate -expand -group RTPS /l0_dds_reader_test6_arzkriu/uut/last_word_in_rtps -add wave -noupdate -divider DDS -add wave -noupdate -group DDS /l0_dds_reader_test6_arzkriu/uut/start_dds -add wave -noupdate -group DDS /l0_dds_reader_test6_arzkriu/uut/ack_dds -add wave -noupdate -group DDS /l0_dds_reader_test6_arzkriu/uut/opcode_dds -add wave -noupdate -group DDS -radix SAMPLE_STATE /l0_dds_reader_test6_arzkriu/uut/sample_state_dds -add wave -noupdate -group DDS -radix INSTANCE_STATE /l0_dds_reader_test6_arzkriu/uut/instance_state_dds -add wave -noupdate -group DDS -radix VIEW_STATE /l0_dds_reader_test6_arzkriu/uut/view_state_dds -add wave -noupdate -group DDS -radix hexadecimal /l0_dds_reader_test6_arzkriu/uut/instance_handle_dds -add wave -noupdate -group DDS -radix unsigned /l0_dds_reader_test6_arzkriu/uut/max_samples_dds -add wave -noupdate -group DDS -radix DDS_RETCODE /l0_dds_reader_test6_arzkriu/uut/return_code_dds -add wave -noupdate -group DDS /l0_dds_reader_test6_arzkriu/uut/done_dds -add wave -noupdate -group DDS -divider SI -add wave -noupdate -group DDS -radix SAMPLE_STATE /l0_dds_reader_test6_arzkriu/uut/si_sample_state -add wave -noupdate -group DDS -radix VIEW_STATE /l0_dds_reader_test6_arzkriu/uut/si_view_state -add wave -noupdate -group DDS -radix INSTANCE_STATE /l0_dds_reader_test6_arzkriu/uut/si_instance_state -add wave -noupdate -group DDS -radix unsigned /l0_dds_reader_test6_arzkriu/uut/si_source_timestamp -add wave -noupdate -group DDS -radix hexadecimal /l0_dds_reader_test6_arzkriu/uut/si_instance_handle -add wave -noupdate -group DDS -radix hexadecimal /l0_dds_reader_test6_arzkriu/uut/si_publication_handle -add wave -noupdate -group DDS -radix unsigned /l0_dds_reader_test6_arzkriu/uut/si_disposed_generation_count -add wave -noupdate -group DDS -radix unsigned /l0_dds_reader_test6_arzkriu/uut/si_no_writers_generation_count -add wave -noupdate -group DDS -radix unsigned /l0_dds_reader_test6_arzkriu/uut/si_sample_rank -add wave -noupdate -group DDS -radix unsigned /l0_dds_reader_test6_arzkriu/uut/si_generation_rank -add wave -noupdate -group DDS -radix unsigned /l0_dds_reader_test6_arzkriu/uut/si_absolute_generation_rank -add wave -noupdate -group DDS /l0_dds_reader_test6_arzkriu/uut/si_valid_data -add wave -noupdate -group DDS /l0_dds_reader_test6_arzkriu/uut/si_valid -add wave -noupdate -group DDS /l0_dds_reader_test6_arzkriu/uut/get_data_dds -add wave -noupdate -group DDS /l0_dds_reader_test6_arzkriu/uut/eoc -add wave -noupdate -group DDS -divider OUTPUT -add wave -noupdate -group DDS /l0_dds_reader_test6_arzkriu/uut/ready_out_dds -add wave -noupdate -group DDS /l0_dds_reader_test6_arzkriu/uut/valid_out_dds -add wave -noupdate -group DDS -radix hexadecimal /l0_dds_reader_test6_arzkriu/uut/data_out_dds -add wave -noupdate -group DDS /l0_dds_reader_test6_arzkriu/uut/last_word_out_dds -add wave -noupdate -divider {MAIN FSM} -add wave -noupdate /l0_dds_reader_test6_arzkriu/uut/stage -add wave -noupdate /l0_dds_reader_test6_arzkriu/uut/stage_next -add wave -noupdate /l0_dds_reader_test6_arzkriu/uut/cnt -add wave -noupdate -divider MEMORY -add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test6_arzkriu/uut/sample_abort_read -add wave -noupdate -group {SAMPLE MEM} -radix unsigned /l0_dds_reader_test6_arzkriu/uut/sample_mem_ctrl_inst/addr -add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test6_arzkriu/uut/sample_mem_ctrl_inst/read -add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test6_arzkriu/uut/sample_mem_ctrl_inst/ready_in -add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test6_arzkriu/uut/sample_mem_ctrl_inst/valid_in -add wave -noupdate -group {SAMPLE MEM} -radix hexadecimal /l0_dds_reader_test6_arzkriu/uut/sample_mem_ctrl_inst/data_in -add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test6_arzkriu/uut/sample_mem_ctrl_inst/ready_out -add wave -noupdate -group {SAMPLE MEM} /l0_dds_reader_test6_arzkriu/uut/sample_mem_ctrl_inst/valid_out -add wave -noupdate -group {SAMPLE MEM} -radix hexadecimal /l0_dds_reader_test6_arzkriu/uut/sample_mem_ctrl_inst/data_out -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test6_arzkriu/uut/payload_abort_read -add wave -noupdate -group {PAYLOAD MEM} -radix unsigned /l0_dds_reader_test6_arzkriu/uut/payload_mem_ctrl_inst/addr -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test6_arzkriu/uut/payload_mem_ctrl_inst/read -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test6_arzkriu/uut/payload_mem_ctrl_inst/ready_in -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test6_arzkriu/uut/payload_mem_ctrl_inst/valid_in -add wave -noupdate -group {PAYLOAD MEM} -radix hexadecimal /l0_dds_reader_test6_arzkriu/uut/payload_mem_ctrl_inst/data_in -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test6_arzkriu/uut/payload_mem_ctrl_inst/ready_out -add wave -noupdate -group {PAYLOAD MEM} /l0_dds_reader_test6_arzkriu/uut/payload_mem_ctrl_inst/valid_out -add wave -noupdate -group {PAYLOAD MEM} -radix hexadecimal /l0_dds_reader_test6_arzkriu/uut/payload_mem_ctrl_inst/data_out -add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test6_arzkriu/uut/inst_abort_read -add wave -noupdate -group {INSTANCE MEM} -radix unsigned /l0_dds_reader_test6_arzkriu/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/addr -add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test6_arzkriu/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/read -add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test6_arzkriu/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/ready_in -add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test6_arzkriu/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/valid_in -add wave -noupdate -group {INSTANCE MEM} -radix hexadecimal /l0_dds_reader_test6_arzkriu/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/data_in -add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test6_arzkriu/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/ready_out -add wave -noupdate -group {INSTANCE MEM} /l0_dds_reader_test6_arzkriu/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/valid_out -add wave -noupdate -group {INSTANCE MEM} -radix hexadecimal /l0_dds_reader_test6_arzkriu/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/data_out -add wave -noupdate /l0_dds_reader_test6_arzkriu/uut/inst_op_start -add wave -noupdate /l0_dds_reader_test6_arzkriu/uut/inst_opcode -add wave -noupdate /l0_dds_reader_test6_arzkriu/uut/inst_op_done -add wave -noupdate /l0_dds_reader_test6_arzkriu/uut/inst_stage -add wave -noupdate /l0_dds_reader_test6_arzkriu/uut/inst_stage_next -add wave -noupdate /l0_dds_reader_test6_arzkriu/uut/inst_cnt -add wave -noupdate -radix unsigned /l0_dds_reader_test6_arzkriu/uut/inst_addr_base -add wave -noupdate /l0_dds_reader_test6_arzkriu/uut/inst_mem_fields -add wave -noupdate -childformat {{/l0_dds_reader_test6_arzkriu/uut/inst_data.key_hash -radix hexadecimal} {/l0_dds_reader_test6_arzkriu/uut/inst_data.status_info -radix binary} {/l0_dds_reader_test6_arzkriu/uut/inst_data.sample_cnt -radix unsigned} {/l0_dds_reader_test6_arzkriu/uut/inst_data.disposed_gen_cnt -radix unsigned} {/l0_dds_reader_test6_arzkriu/uut/inst_data.no_writers_gen_cnt -radix unsigned} {/l0_dds_reader_test6_arzkriu/uut/inst_data.ignore_deadline -radix unsigned} {/l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap -radix binary -childformat {{/l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0) -radix binary -childformat {{/l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(0) -radix binary} {/l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(1) -radix binary} {/l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(2) -radix binary} {/l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(3) -radix binary} {/l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(4) -radix binary} {/l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(5) -radix binary} {/l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(6) -radix binary} {/l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(7) -radix binary} {/l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(8) -radix binary} {/l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(9) -radix binary} {/l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(10) -radix binary} {/l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(11) -radix binary} {/l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(12) -radix binary} {/l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(13) -radix binary} {/l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(14) -radix binary} {/l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(15) -radix binary} {/l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(16) -radix binary} {/l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(17) -radix binary} {/l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(18) -radix binary} {/l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(19) -radix binary} {/l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(20) -radix binary} {/l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(21) -radix binary} {/l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(22) -radix binary} {/l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(23) -radix binary} {/l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(24) -radix binary} {/l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(25) -radix binary} {/l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(26) -radix binary} {/l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(27) -radix binary} {/l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(28) -radix binary} {/l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(29) -radix binary} {/l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(30) -radix binary} {/l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(31) -radix binary}}}}}} -expand -subitemconfig {/l0_dds_reader_test6_arzkriu/uut/inst_data.key_hash {-height 15 -radix hexadecimal} /l0_dds_reader_test6_arzkriu/uut/inst_data.status_info {-height 15 -radix binary} /l0_dds_reader_test6_arzkriu/uut/inst_data.sample_cnt {-height 15 -radix unsigned} /l0_dds_reader_test6_arzkriu/uut/inst_data.disposed_gen_cnt {-height 15 -radix unsigned} /l0_dds_reader_test6_arzkriu/uut/inst_data.no_writers_gen_cnt {-height 15 -radix unsigned} /l0_dds_reader_test6_arzkriu/uut/inst_data.ignore_deadline {-height 15 -radix unsigned} /l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap {-height 15 -radix binary -childformat {{/l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0) -radix binary -childformat {{/l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(0) -radix binary} {/l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(1) -radix binary} {/l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(2) -radix binary} {/l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(3) -radix binary} {/l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(4) -radix binary} {/l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(5) -radix binary} {/l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(6) -radix binary} {/l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(7) -radix binary} {/l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(8) -radix binary} {/l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(9) -radix binary} {/l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(10) -radix binary} {/l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(11) -radix binary} {/l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(12) -radix binary} {/l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(13) -radix binary} {/l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(14) -radix binary} {/l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(15) -radix binary} {/l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(16) -radix binary} {/l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(17) -radix binary} {/l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(18) -radix binary} {/l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(19) -radix binary} {/l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(20) -radix binary} {/l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(21) -radix binary} {/l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(22) -radix binary} {/l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(23) -radix binary} {/l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(24) -radix binary} {/l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(25) -radix binary} {/l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(26) -radix binary} {/l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(27) -radix binary} {/l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(28) -radix binary} {/l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(29) -radix binary} {/l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(30) -radix binary} {/l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(31) -radix binary}}}}} /l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0) {-height 15 -radix binary -childformat {{/l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(0) -radix binary} {/l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(1) -radix binary} {/l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(2) -radix binary} {/l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(3) -radix binary} {/l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(4) -radix binary} {/l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(5) -radix binary} {/l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(6) -radix binary} {/l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(7) -radix binary} {/l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(8) -radix binary} {/l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(9) -radix binary} {/l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(10) -radix binary} {/l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(11) -radix binary} {/l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(12) -radix binary} {/l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(13) -radix binary} {/l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(14) -radix binary} {/l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(15) -radix binary} {/l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(16) -radix binary} {/l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(17) -radix binary} {/l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(18) -radix binary} {/l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(19) -radix binary} {/l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(20) -radix binary} {/l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(21) -radix binary} {/l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(22) -radix binary} {/l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(23) -radix binary} {/l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(24) -radix binary} {/l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(25) -radix binary} {/l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(26) -radix binary} {/l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(27) -radix binary} {/l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(28) -radix binary} {/l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(29) -radix binary} {/l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(30) -radix binary} {/l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(31) -radix binary}}} /l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(0) {-height 15 -radix binary} /l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(1) {-height 15 -radix binary} /l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(2) {-height 15 -radix binary} /l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(3) {-height 15 -radix binary} /l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(4) {-height 15 -radix binary} /l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(5) {-height 15 -radix binary} /l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(6) {-height 15 -radix binary} /l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(7) {-height 15 -radix binary} /l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(8) {-height 15 -radix binary} /l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(9) {-height 15 -radix binary} /l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(10) {-height 15 -radix binary} /l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(11) {-height 15 -radix binary} /l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(12) {-height 15 -radix binary} /l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(13) {-height 15 -radix binary} /l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(14) {-height 15 -radix binary} /l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(15) {-height 15 -radix binary} /l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(16) {-height 15 -radix binary} /l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(17) {-height 15 -radix binary} /l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(18) {-height 15 -radix binary} /l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(19) {-height 15 -radix binary} /l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(20) {-height 15 -radix binary} /l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(21) {-height 15 -radix binary} /l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(22) {-height 15 -radix binary} /l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(23) {-height 15 -radix binary} /l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(24) {-height 15 -radix binary} /l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(25) {-height 15 -radix binary} /l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(26) {-height 15 -radix binary} /l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(27) {-height 15 -radix binary} /l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(28) {-height 15 -radix binary} /l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(29) {-height 15 -radix binary} /l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(30) {-height 15 -radix binary} /l0_dds_reader_test6_arzkriu/uut/inst_data.writer_bitmap(0)(31) {-height 15 -radix binary}} /l0_dds_reader_test6_arzkriu/uut/inst_data -add wave -noupdate -radix unsigned /l0_dds_reader_test6_arzkriu/uut/inst_next_addr_base -add wave -noupdate -radix unsigned /l0_dds_reader_test6_arzkriu/uut/inst_prev_addr_base -add wave -noupdate /l0_dds_reader_test6_arzkriu/uut/current_imf -add wave -noupdate /l0_dds_reader_test6_arzkriu/uut/stale_inst_cnt -add wave -noupdate -divider POINTERS -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test6_arzkriu/uut/empty_sample_list_head -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test6_arzkriu/uut/empty_sample_list_tail -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test6_arzkriu/uut/empty_payload_list_head -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test6_arzkriu/uut/oldest_sample -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test6_arzkriu/uut/newest_sample -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test6_arzkriu/uut/inst_empty_head -add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_reader_test6_arzkriu/uut/inst_occupied_head -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test6_arzkriu/uut/cur_sample -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test6_arzkriu/uut/next_sample -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test6_arzkriu/uut/prev_sample -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test6_arzkriu/uut/cur_payload -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test6_arzkriu/uut/next_payload -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test6_arzkriu/uut/cur_inst -add wave -noupdate -expand -group {GENERAL POINTERS} -radix unsigned /l0_dds_reader_test6_arzkriu/uut/next_inst -add wave -noupdate -divider TESTBENCH -add wave -noupdate -group TESTBENCH /l0_dds_reader_test6_arzkriu/dds_start -add wave -noupdate -group TESTBENCH /l0_dds_reader_test6_arzkriu/dds_stage -add wave -noupdate -group TESTBENCH /l0_dds_reader_test6_arzkriu/dds_cnt -add wave -noupdate -group TESTBENCH /l0_dds_reader_test6_arzkriu/dds_cnt2 -add wave -noupdate -group TESTBENCH /l0_dds_reader_test6_arzkriu/dds_done -add wave -noupdate -group TESTBENCH /l0_dds_reader_test6_arzkriu/rtps_start -add wave -noupdate -group TESTBENCH /l0_dds_reader_test6_arzkriu/rtps_stage -add wave -noupdate -group TESTBENCH /l0_dds_reader_test6_arzkriu/rtps_cnt -add wave -noupdate -group TESTBENCH /l0_dds_reader_test6_arzkriu/rtps_done -add wave -noupdate -divider {KEY HOLDER} -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test6_arzkriu/uut/start_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test6_arzkriu/uut/opcode_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test6_arzkriu/uut/ack_kh -add wave -noupdate -group {KEY HOLDER} -radix hexadecimal /l0_dds_reader_test6_arzkriu/uut/data_in_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test6_arzkriu/uut/valid_in_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test6_arzkriu/uut/ready_in_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test6_arzkriu/uut/last_word_in_kh -add wave -noupdate -group {KEY HOLDER} -radix hexadecimal /l0_dds_reader_test6_arzkriu/uut/data_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test6_arzkriu/uut/valid_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test6_arzkriu/uut/ready_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test6_arzkriu/uut/last_word_out_kh -add wave -noupdate -group {KEY HOLDER} /l0_dds_reader_test6_arzkriu/uut/abort_kh -add wave -noupdate -divider MISC -add wave -noupdate /l0_dds_reader_test6_arzkriu/uut/status -add wave -noupdate -radix unsigned /l0_dds_reader_test6_arzkriu/uut/sample_rej_cnt -add wave -noupdate -radix unsigned /l0_dds_reader_test6_arzkriu/uut/sample_rej_cnt_change -add wave -noupdate /l0_dds_reader_test6_arzkriu/uut/sample_rej_last_reason -add wave -noupdate -radix hexadecimal /l0_dds_reader_test6_arzkriu/uut/sample_rej_last_inst -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {7016727 ps} 0} {{Cursor 2} {115175000 ps} 1} -quietly wave cursor active 1 -configure wave -namecolwidth 187 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -configure wave -timelineunits ns -update -WaveRestoreZoom {6874680 ps} {7875321 ps} diff --git a/src/TODO.txt b/src/TODO.txt index fd0ab22..47907e2 100644 --- a/src/TODO.txt +++ b/src/TODO.txt @@ -469,6 +469,12 @@ DESIGN DECISIONS writer (Writer ID, Lifespan Deadline), we cannot write to multiple DDS endpoints at the same time. This means that we have to temporarily store the payload and push it to each DDS Endpoint individually. +* Since the DDS Reader is waiting on USER via the 'sample_info_ack' signal before continuing, a singel + user can stall all other USERs/Readers (DoS) of a vector entity of the DDS Reader. + +* The DEADLINE check times of the DDS Entities are aligned to the release of the reset, and not on the + addition of a new instance. That means that all Instances are checked at the smae time, non depending + on when they were added. BRAINSTORMING ------------- diff --git a/src/Tests/Level_0/L0_dds_reader_test1.vhd b/src/Tests/Level_0/L0_dds_reader_test1.vhd new file mode 100644 index 0000000..9679fe2 --- /dev/null +++ b/src/Tests/Level_0/L0_dds_reader_test1.vhd @@ -0,0 +1,6916 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library osvvm; -- Utility Library +context osvvm.OsvvmContext; + +use work.rtps_package.all; +use work.user_config.all; +use work.rtps_config_package.all; +use work.rtps_test_package.all; + +-- This testbench tests the RTPS handling of the DDS Reader. It tests the correctness of the RTPS ADD_CACHE_CHANGE, and REMOVE_WRITER Operations. +-- Implicitly some DDS Operations are also tested, since they are used for state checking. +-- More specifically the testbench covers following tests: +-- TEST: NORMAL ADD_CACHE_CHANGE +-- TEST: ADD_CACHE_CHANGE ON PAYLOAD MEMORY FULL +-- TEST: REMOVE_WRITER [UNKNOWN WRITER] +-- TEST: REMOVE_WRITER [KNOWN WRITER (1 Instance)] +-- TEST: REMOVE_WRITER [KNOWN WRITER (>1 Instances)] +-- TEST: REMOVE_WRITER [NOT_ALIVE_NO_WRITERS Transition] +-- TEST: REMOVE_WRITER [Multiple Pending NOT_ALIVE_NO_WRITERS Transitions] +-- TEST: REMOVE_WRITER ON MAX_SAMPLES [NOT_ALIVE_NO_WRITERS Transition] +-- TEST: REMOVE_WRITER ON MAX_SAMPLES_PER_INSTANCE [NOT_ALIVE_NO_WRITERS Transition] +-- TEST: SAMPLE WITH ALIGNED PAYLOAD +-- TEST: SAMPLE WITH UNALIGNED PAYLOAD [>1 SLOT] +-- TEST: SAMPLE WITH UNALIGNED PAYLOAD [<1 SLOT] +-- TEST: NORMAL SAMPLE [KNOWN INSTANCE] +-- TEST: NORMAL SAMPLE [UNKNOWN INSTANCE] +-- TEST: UNREGISTER SAMPLE [KNOWN INSTANCE, KNOWN WRITER] +-- TEST: UNREGISTER SAMPLE [KNOWN INSTANCE, UNKNOWN WRITER] +-- TEST: UNREGISTER SAMPLE [UNKNOWN INSTANCE] +-- TEST: UNREGISTER SAMPLE [NOT_ALIVE_NO_WRITERS INSTANCE] +-- TEST: UNREGISTER SAMPLE [NOT_ALIVE_DISPOSED INSTANCE] +-- TEST: UNREGISTER SAMPLE [NOT_ALIVE_DISPOSED INSTANCE, STALE INSTANCE TRANSITION] +-- TEST: DISPOSE SAMPLE [KNOWN INSTANCE] +-- TEST: DISPOSE SAMPLE [UNKNOWN INSTANCE] +-- TEST: DISPOSE SAMPLE [NOT_ALIVE_NO_WRITERS INSTANCE] +-- TEST: DISPOSE SAMPLE [NOT_ALIVE_DISPOSED INSTANCE] +-- TEST: FILTER SAMPLE [KNOWN INSTANCE] +-- TEST: FILTER SAMPLE [UNKNOWN INSTANCE] +-- TEST: FILTER SAMPLE [NOT_ALIVE_DISPOSED INSTANCE] +-- TEST: FILTER SAMPLE [NOT_ALIVE_NO_WRITERS INSTANCE] +-- TEST: SAMPLE WITH KEY_HASH +-- TEST: SAMPLE WITHOUT KEY_HASH +-- TEST: SAMPLE WITH SERIALIZED KEY [WITH KEY_HASH] +-- TEST: SAMPLE WITH SERIALIZED KEY [WITHOUT KEY_HASH] +-- TEST: SAMPLE WITH EARLY TIMESTAMP [TIMESTAMP EARLIER THAN LAST READ] +-- TEST: TEST SAMPLE WITH SERIALIZED KEY EFFECT ON PAYLOAD MEMORY FULLNESS +-- TEST: ADD SAMPLE ON MAX_SAMPLES_PER_INSTANCE +-- TEST: ADD SAMPLE ON MAX_SAMPLES [KNOWN INSTANCE] +-- TEST: ADD SAMPLE ON MAX_SAMPLES [UNKNOWN INSTANCE] +-- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKOWN INSTANCE, WITH STALE INSTANCE] +-- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKOWN INSTANCE, WITHOUT STALE INSTANCE] +-- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKOWN INSTANCE, WITHOUT STALE INSTANCE, WITH EMPTY INSTANCE] +-- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKOWN INSTANCE, NOT_ALIVE_DISPOSED & STALE INSTANCE] +-- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE, WITH STALE INSTANCE] +-- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE, WITHOUT STALE INSTANCE] +-- TEST: ADD SAMPLE BIGGER THAN AVAILABLE MEMORY SPACE + +entity L0_dds_reader_test1 is +end entity; + + +architecture testbench of L0_dds_reader_test1 is + + -- *CONSTANT DECLARATION* + constant MAX_REMOTE_ENDPOINTS : natural := 3; + constant NUM_READERS : natural := 6; + + impure function gen_test_config return CONFIG_ARRAY_TYPE is + variable ret : CONFIG_ARRAY_TYPE(0 to NUM_READERS-1) := (others => DEFAULT_WRITER_CONFIG); + begin + -- arzkriu + ret(0).TIME_BASED_FILTER_QOS := DURATION_ZERO; + ret(0).DEADLINE_QOS := DURATION_INFINITE; + ret(0).MAX_SAMPLES := std_logic_vector(to_unsigned(4,CDR_LONG_WIDTH)); + ret(0).MAX_INSTANCES := std_logic_vector(to_unsigned(3,CDR_LONG_WIDTH)); + ret(0).MAX_SAMPLES_PER_INSTANCE := std_logic_vector(to_unsigned(2,CDR_LONG_WIDTH)); + ret(0).HISTORY_QOS := KEEP_ALL_HISTORY_QOS; + ret(0).RELIABILITY_QOS := RELIABLE_RELIABILITY_QOS; + ret(0).PRESENTATION_QOS := INSTANCE_PRESENTATION_QOS; + ret(0).DESTINATION_ORDER_QOS := BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS; + ret(0).COHERENT_ACCESS := FALSE; + ret(0).ORDERED_ACCESS := FALSE; + ret(0).WITH_KEY := TRUE; + ret(0).MAX_PAYLOAD_SIZE := 40; + -- lrzkriu + ret(1).TIME_BASED_FILTER_QOS := DURATION_ZERO; + ret(1).DEADLINE_QOS := DURATION_INFINITE; + ret(1).MAX_SAMPLES := std_logic_vector(to_unsigned(4,CDR_LONG_WIDTH)); + ret(1).MAX_INSTANCES := std_logic_vector(to_unsigned(3,CDR_LONG_WIDTH)); + ret(1).MAX_SAMPLES_PER_INSTANCE := std_logic_vector(to_unsigned(2,CDR_LONG_WIDTH)); + ret(1).HISTORY_QOS := KEEP_LAST_HISTORY_QOS; + ret(1).RELIABILITY_QOS := RELIABLE_RELIABILITY_QOS; + ret(1).PRESENTATION_QOS := INSTANCE_PRESENTATION_QOS; + ret(1).DESTINATION_ORDER_QOS := BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS; + ret(1).COHERENT_ACCESS := FALSE; + ret(1).ORDERED_ACCESS := FALSE; + ret(1).WITH_KEY := TRUE; + ret(1).MAX_PAYLOAD_SIZE := 40; + -- lbzkriu + ret(2).TIME_BASED_FILTER_QOS := DURATION_ZERO; + ret(2).DEADLINE_QOS := DURATION_INFINITE; + ret(2).MAX_SAMPLES := std_logic_vector(to_unsigned(4,CDR_LONG_WIDTH)); + ret(2).MAX_INSTANCES := std_logic_vector(to_unsigned(3,CDR_LONG_WIDTH)); + ret(2).MAX_SAMPLES_PER_INSTANCE := std_logic_vector(to_unsigned(2,CDR_LONG_WIDTH)); + ret(2).HISTORY_QOS := KEEP_LAST_HISTORY_QOS; + ret(2).RELIABILITY_QOS := BEST_EFFORT_RELIABILITY_QOS; + ret(2).PRESENTATION_QOS := INSTANCE_PRESENTATION_QOS; + ret(2).DESTINATION_ORDER_QOS := BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS; + ret(2).COHERENT_ACCESS := FALSE; + ret(2).ORDERED_ACCESS := FALSE; + ret(2).WITH_KEY := TRUE; + ret(2).MAX_PAYLOAD_SIZE := 40; + -- abzkriu + ret(3).TIME_BASED_FILTER_QOS := DURATION_ZERO; + ret(3).DEADLINE_QOS := DURATION_INFINITE; + ret(3).MAX_SAMPLES := std_logic_vector(to_unsigned(4,CDR_LONG_WIDTH)); + ret(3).MAX_INSTANCES := std_logic_vector(to_unsigned(3,CDR_LONG_WIDTH)); + ret(3).MAX_SAMPLES_PER_INSTANCE := std_logic_vector(to_unsigned(2,CDR_LONG_WIDTH)); + ret(3).HISTORY_QOS := KEEP_ALL_HISTORY_QOS; + ret(3).RELIABILITY_QOS := BEST_EFFORT_RELIABILITY_QOS; + ret(3).PRESENTATION_QOS := INSTANCE_PRESENTATION_QOS; + ret(3).DESTINATION_ORDER_QOS := BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS; + ret(3).COHERENT_ACCESS := FALSE; + ret(3).ORDERED_ACCESS := FALSE; + ret(3).WITH_KEY := TRUE; + ret(3).MAX_PAYLOAD_SIZE := 40; + -- arznriu + ret(4).TIME_BASED_FILTER_QOS := DURATION_ZERO; + ret(4).DEADLINE_QOS := DURATION_INFINITE; + ret(4).MAX_SAMPLES := std_logic_vector(to_unsigned(2,CDR_LONG_WIDTH)); + ret(4).MAX_INSTANCES := std_logic_vector(to_unsigned(3,CDR_LONG_WIDTH)); + ret(4).MAX_SAMPLES_PER_INSTANCE := std_logic_vector(to_unsigned(2,CDR_LONG_WIDTH)); + ret(4).HISTORY_QOS := KEEP_ALL_HISTORY_QOS; + ret(4).RELIABILITY_QOS := RELIABLE_RELIABILITY_QOS; + ret(4).PRESENTATION_QOS := INSTANCE_PRESENTATION_QOS; + ret(4).DESTINATION_ORDER_QOS := BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS; + ret(4).COHERENT_ACCESS := FALSE; + ret(4).ORDERED_ACCESS := FALSE; + ret(4).WITH_KEY := FALSE; + ret(4).MAX_PAYLOAD_SIZE := 35; + -- arzksiu + ret(5).TIME_BASED_FILTER_QOS := DURATION_ZERO; + ret(5).DEADLINE_QOS := DURATION_INFINITE; + ret(5).MAX_SAMPLES := std_logic_vector(to_unsigned(4,CDR_LONG_WIDTH)); + ret(5).MAX_INSTANCES := std_logic_vector(to_unsigned(3,CDR_LONG_WIDTH)); + ret(5).MAX_SAMPLES_PER_INSTANCE := std_logic_vector(to_unsigned(2,CDR_LONG_WIDTH)); + ret(5).HISTORY_QOS := KEEP_ALL_HISTORY_QOS; + ret(5).RELIABILITY_QOS := RELIABLE_RELIABILITY_QOS; + ret(5).PRESENTATION_QOS := INSTANCE_PRESENTATION_QOS; + ret(5).DESTINATION_ORDER_QOS := BY_SOURCE_TIMESTAMP_DESTINATION_ORDER_QOS; + ret(5).COHERENT_ACCESS := FALSE; + ret(5).ORDERED_ACCESS := FALSE; + ret(5).WITH_KEY := TRUE; + ret(5).MAX_PAYLOAD_SIZE := 40; + return ret; + end function; + constant TEST_CONFIG : CONFIG_ARRAY_TYPE := gen_test_config; + + -- *TYPE DECLARATION* + type DDS_STAGE_TYPE is (IDLE, START, DONE, CHECK_SI, CHECK_DATA, WAIT_EOC); + type RTPS_STAGE_TYPE is (IDLE, START, PUSH, DONE); + type EMPTY_HEAD_SIG_ARRAY_TYPE is array (0 to NUM_READERS-1) of natural; + type DDS_READER_MEM_ARRAY_TYPE is array (0 to NUM_READERS-1) of DDS_READER_MEM_TYPE; + + -- *SIGNAL DECLARATION* + signal clk : std_logic := '0'; + signal reset : std_logic := '1'; + signal check_time : TIME_TYPE := TIME_ZERO; + signal start_rtps, start_dds, ack_rtps, ack_dds, done_rtps, done_dds : std_logic_vector(0 to NUM_READERS-1) := (others => '0'); + signal opcode_rtps : HISTORY_CACHE_OPCODE_ARRAY_TYPE(0 to NUM_READERS-1) := (others => NOP); + signal opcode_dds : DDS_READER_OPCODE_ARRAY_TYPE(0 to NUM_READERS-1) := (others => NOP); + signal ret_rtps : HISTORY_CACHE_RESPONSE_ARRAY_TYPE(0 to NUM_READERS-1) := (others => ERROR); + signal ready_in_rtps, valid_in_rtps, last_word_in_rtps : std_logic_vector(0 to NUM_READERS-1) := (others => '0'); + signal ready_out_dds, valid_out_dds, last_word_out_dds : std_logic_vector(0 to NUM_READERS-1) := (others => '0'); + signal data_in_rtps, data_out_dds : WORD_ARRAY_TYPE(0 to NUM_READERS-1) := (others => (others => '0')); + signal get_data_dds, si_valid, eoc : std_logic_vector(0 to NUM_READERS-1) := (others => '0'); + signal return_code_dds : RETURN_CODE_ARRAY_TYPE(0 to NUM_READERS-1) := (others => (others => '0')); + signal status : STATUS_KIND_ARRAY_TYPE(0 to NUM_READERS-1) := (others => (others => '0')); + signal instance_state_dds : INSTANCE_STATE_ARRAY_TYPE(0 to NUM_READERS-1) := (others => ANY_INSTANCE_STATE); + signal view_state_dds : VIEW_STATE_ARRAY_TYPE(0 to NUM_READERS-1) := (others => ANY_VIEW_STATE); + signal sample_state_dds : SAMPLE_STATE_ARRAY_TYPE(0 to NUM_READERS-1) := (others => ANY_SAMPLE_STATE); + signal instance_handle_dds : INSTANCE_HANDLE_ARRAY_TYPE(0 to NUM_READERS-1) := (others => HANDLE_NIL); + signal max_samples_dds : MAX_SAMPLES_ARRAY_TYPE(0 to NUM_READERS-1) := (others => (others => '0')); + signal sample_info : SAMPLE_INFO_ARRAY_TYPE(0 to NUM_READERS-1); + + signal ind : natural := 0; + signal dds_start , dds_done , rtps_start, rtps_done : std_logic := '0'; + signal dds_cnt, dds_cnt2, rtps_cnt : natural := 0; + signal dds_stage : DDS_STAGE_TYPE := IDLE; + signal rtps_stage : RTPS_STAGE_TYPE := IDLE; + shared variable dds : DDS_READER_TEST_TYPE := DEFAULT_DDS_READER_TEST; + shared variable rtps : RTPS_READER_TEST_TYPE := DEFAULT_RTPS_READER_TEST; + shared variable mem : DDS_READER_MEM_ARRAY_TYPE := (others => DEFAULT_DDS_READER_MEM); + signal data_id, ret_id, sstate_id, vstate_id, istate_id, inst_id, ts_id, pub_id, dis_gen_cnt_id, no_w_gen_cnt_id, srank_id, grank_id, agrank_id, eoc_id, valid_id, status_id : AlertLogIDType; + + -- *FUNCTION DECLARATION* + function extract_key_hash (payload : TEST_PACKET_TYPE) return INSTANCE_HANDLE_TYPE is + variable ret : INSTANCE_HANDLE_TYPE := HANDLE_NIL; + begin + for i in 0 to 3 loop + ret(i) := not payload.data(i); + end loop; + + return ret; + end function; + + function gen_sn(input : natural) return SEQUENCENUMBER_TYPE is + variable ret : SEQUENCENUMBER_TYPE; + begin + ret(0) := (others => '0'); + ret(1) := unsigned(int(input, WORD_WIDTH)); + return ret; + end function; + + procedure wait_on_sig(signal sig : std_logic) is + begin + if (sig /= '1') then + wait on sig until sig = '1'; + end if; + end procedure; + +begin + + -- Unit Under Test + uut : entity work.dds_reader(arch) + generic map ( + NUM_READERS => NUM_READERS, + CONFIG_ARRAY => to_QUARTUS_CONFIG_ARRAY_TYPE(TEST_CONFIG), + MAX_REMOTE_ENDPOINTS => MAX_REMOTE_ENDPOINTS + ) + port map ( + clk => clk, + reset => reset, + time => check_time, + start_rtps => start_rtps, + opcode_rtps => opcode_rtps, + ack_rtps => ack_rtps, + done_rtps => done_rtps, + ret_rtps => ret_rtps, + data_in_rtps => data_in_rtps, + valid_in_rtps => valid_in_rtps, + ready_in_rtps => ready_in_rtps, + last_word_in_rtps => last_word_in_rtps, + start_dds => start_dds, + ack_dds => ack_dds, + opcode_dds => opcode_dds, + instance_state_dds => instance_state_dds, + view_state_dds => view_state_dds, + sample_state_dds => sample_state_dds, + instance_handle_dds => instance_handle_dds, + max_samples_dds => max_samples_dds, + get_data_dds => get_data_dds, + done_dds => done_dds, + return_code_dds => return_code_dds, + ready_out_dds => ready_out_dds, + valid_out_dds => valid_out_dds, + data_out_dds => data_out_dds, + last_word_out_dds => last_word_out_dds, + sample_info => sample_info, + sample_info_valid => si_valid, + sample_info_ack => (others => '1'), + eoc => eoc, + status => status + ); + + stimulus_prc : process + variable RV : RandomPType; + variable cc : CACHE_CHANGE_TYPE := DEFAULT_CACHE_CHANGE; + variable s : SAMPLE_TYPE := DEFAULT_SAMPLE; + variable kh1, kh2, kh3, kh4 : INSTANCE_HANDLE_TYPE := HANDLE_NIL; + + alias idle_sig is <>; + alias inst_op_done is <>; + alias empty_inst_head is <>; + alias empty_sample_head is <>; + alias empty_payload_head is <>; + + impure function gen_payload(key_hash : INSTANCE_HANDLE_TYPE; len : natural) return TEST_PACKET_TYPE is + variable ret : TEST_PACKET_TYPE := EMPTY_TEST_PACKET; + begin + assert (len >= 4) report "Payload length has to be at least 16 Bytes long" severity FAILURE; + + for i in 0 to len-1 loop + if (i < 4) then + -- NOTE: Beginning of payload is negated key to allow deterministic Key Hash generation from the kh_prc + ret.data(ret.length) := not key_hash(i); + else + ret.data(ret.length) := RV.RandSlv(WORD_WIDTH); + end if; + ret.length := ret.length + 1; + end loop; + ret.last(ret.length-1) := '1'; + + return ret; + end function; + + impure function gen_key_hash return KEY_HASH_TYPE is + variable ret : KEY_HASH_TYPE := KEY_HASH_NIL; + begin + for i in 0 to KEY_HASH_TYPE'length-1 loop + ret(i) := RV.RandSlv(WORD_WIDTH); + end loop; + return ret; + end function; + + procedure start_dds is + begin + dds_start <= '1'; + wait until rising_edge(clk); + dds_start <= '0'; + wait until rising_edge(clk); + end procedure; + + procedure start_rtps is + begin + rtps_start <= '1'; + wait until rising_edge(clk); + rtps_start <= '0'; + wait until rising_edge(clk); + end procedure; + + procedure wait_on_completion is + begin + if (rtps_done /= '1' or dds_done /= '1') then + wait until rtps_done = '1' and dds_done = '1'; + end if; + end procedure; + + -- NOTE: This procedure waits until the idle_sig is high for at least + -- two consecutive clock cycles. + procedure wait_on_idle is + variable first : boolean := TRUE; + begin + loop + if (idle_sig /= '1') then + wait until idle_sig = '1'; + elsif (not first) then + exit; + end if; + wait until rising_edge(clk); + wait until rising_edge(clk); + first := FALSE; + end loop; + wait_on_sig(inst_op_done); + end procedure; + + begin + + SetAlertLogName("L0_dds_reader_test1 - RTPS Handling"); + SetAlertEnable(FAILURE, TRUE); + SetAlertEnable(ERROR, TRUE); + SetAlertEnable(WARNING, TRUE); + SetLogEnable(DEBUG, FALSE); + SetLogEnable(PASSED, FALSE); + SetLogEnable(INFO, TRUE); + RV.InitSeed(RV'instance_name); + sstate_id <= GetAlertLogID("Sample State", ALERTLOG_BASE_ID); + vstate_id <= GetAlertLogID("View State", ALERTLOG_BASE_ID); + istate_id <= GetAlertLogID("Instance State", ALERTLOG_BASE_ID); + ts_id <= GetAlertLogID("Source Timestamp", ALERTLOG_BASE_ID); + inst_id <= GetAlertLogID("Instance Handle", ALERTLOG_BASE_ID); + pub_id <= GetAlertLogID("Publication Hanlde", ALERTLOG_BASE_ID); + dis_gen_cnt_id <= GetAlertLogID("Disposed Generation Count", ALERTLOG_BASE_ID); + no_w_gen_cnt_id <= GetAlertLogID("No Writers Generation Count", ALERTLOG_BASE_ID); + srank_id <= GetAlertLogID("Sample Rank", ALERTLOG_BASE_ID); + grank_id <= GetAlertLogID("Generation Rank", ALERTLOG_BASE_ID); + agrank_id <= GetAlertLogID("Absolute Generation Rank", ALERTLOG_BASE_ID); + eoc_id <= GetAlertLogID("End of Collection", ALERTLOG_BASE_ID); + valid_id <= GetAlertLogID("Valid Data", ALERTLOG_BASE_ID); + data_id <= GetAlertLogID("Data Out", ALERTLOG_BASE_ID); + ret_id <= GetAlertLogID("Return Code", ALERTLOG_BASE_ID); + status_id <= GetAlertLogID("Communication Status", ALERTLOG_BASE_ID); + + -- Key Hashes + kh3 := (x"0CEAB0C6", x"FA04B9AD", x"A96EB495", x"4E0EB999"); + kh4 := (x"A7EB605C", x"FF4BEF3A", x"3C5E8724", x"CCA0CA67"); + kh2 := (x"BC070AC4", x"0BAB5811", x"14EA8D61", x"F669189B"); + kh1 := (x"F12C31DA", x"E3FE0F3F", x"01F36685", x"446518CA"); + + + + Log("Initiating Test", INFO); + reset <= '1'; + wait until rising_edge(clk); + wait until rising_edge(clk); + reset <= '0'; + wait_on_idle; + + Log("*READER 0 / READER 5*", INFO); + -- READER 0 + AlertIf(empty_sample_head(0) /= 0, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 0, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 0, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: -/0,11,22,33,44 + -- PAYLOAD MEMORY: -/0,11,22,33,44 + -- INSTANCE MEMORY: -/0,13,26 + -- ISTATE: - + -- WRITER: - + -- READER 5 + AlertIf(empty_sample_head(5) /= 0, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(5) /= 0, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(5) /= 0, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: -/0,11,22,33,44 + -- PAYLOAD MEMORY: -/0,11,22,33,44 + -- INSTANCE MEMORY: -/0,13,26 + -- ISTATE: - + -- WRITER: - + + + AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh1; + cc.payload := gen_payload(kh1,10); + cc.src_timestamp := gen_duration(1 sec); + + -- TEST: NORMAL ADD_CACHE_CHANGE + -- TEST: SAMPLE WITH ALIGNED PAYLOAD + -- TEST: NORMAL SAMPLE [UNKNOWN INSTANCE] + -- TEST: SAMPLE WITH KEY_HASH + + Log("R0,R5: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Aligned Payload]", INFO); + Log("R0,R5: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 0; + rtps.ret_code := OK; + s := to_sample(cc,ALIVE_INSTANCE_STATE); + add_sample(s,mem(0), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(5), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + -- READER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- READER 5 + ind <= 5; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 0 + AlertIf(empty_sample_head(0) /= 11, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 11, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 13, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I1S1)/11,22,33,44 + -- PAYLOAD MEMORY: 0(I1S1)/11,22,33,44 + -- INSTANCE MEMORY: 0(I1)/13,26 + -- ISTATE: I1:ALIVE + -- WRITER: W0:I1 + -- READER 5 + AlertIf(empty_sample_head(5) /= 11, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(5) /= 11, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(5) /= 13, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I1S1)/11,22,33,44 + -- PAYLOAD MEMORY: 0(I1S1)/11,22,33,44 + -- INSTANCE MEMORY: 0(I1)/13,26 + -- ISTATE: I1:ALIVE + -- WRITER: W0:I1 + + AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := HANDLE_NIL; + cc.payload := gen_payload(kh1,18); + cc.src_timestamp := gen_duration(2 sec); + + -- TEST: SAMPLE WITHOUT KEY_HASH + -- TEST: SAMPLE WITH UNALIGNED PAYLOAD [>1 SLOT] + -- TEST: NORMAL SAMPLE [KNOWN INSTANCE] + + Log("R0,R5: RTPS Operation ADD_CACHE_CHANGE [NO KEY_HASH, Instance 1, Writer 0, Unaligned Payload (2 Slots)]", INFO); + Log("R0,R5: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 0; + rtps.ret_code := OK; + s := to_sample(cc,ALIVE_INSTANCE_STATE); + s.inst := kh1; + add_sample(s,mem(0), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(5), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + -- READER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- READER 5 + ind <= 5; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 0 + AlertIf(empty_sample_head(0) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 33, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 13, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I1S1),11(I1S2)/22,33,44 + -- PAYLOAD MEMORY: 0(I1S1),11(I1S2),22(I1S2)/33,44 + -- INSTANCE MEMORY: 0(I1)/13,26 + -- ISTATE: I1:ALIVE + -- WRITER: W0:I1 + -- READER 5 + AlertIf(empty_sample_head(5) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(5) /= 33, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(5) /= 13, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I1S1),11(I1S2)/22,33,44 + -- PAYLOAD MEMORY: 0(I1S1),11(I1S2),22(I1S2)/33,44 + -- INSTANCE MEMORY: 0(I1)/13,26 + -- ISTATE: I1:ALIVE + -- WRITER: W0:I1 + + AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + + -- VAILDATE STATE + + Log("R0,R5: DDS Operation READ [MAX_SAMPLES 4, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := READ; + dds.max_samples := 4; + dds.sstate := ANY_SAMPLE_STATE; + dds.istate := ANY_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + -- READER 0 + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- READER 5 + ind <= 5; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- READER 0 + AlertIf(empty_sample_head(0) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 33, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 13, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I1S1),11(I1S2)/22,33,44 + -- PAYLOAD MEMORY: 0(I1S1),11(I1S2),22(I1S2)/33,44 + -- INSTANCE MEMORY: 0(I1)/13,26 + -- ISTATE: I1:ALIVE + -- WRITER: W0:I1 + -- READER 5 + AlertIf(empty_sample_head(5) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(5) /= 33, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(5) /= 13, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I1S1),11(I1S2)/22,33,44 + -- PAYLOAD MEMORY: 0(I1S1),11(I1S2),22(I1S2)/33,44 + -- INSTANCE MEMORY: 0(I1)/13,26 + -- ISTATE: I1:ALIVE + -- WRITER: W0:I1 + + AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := TRUE; + cc.kind := NOT_ALIVE_DISPOSED; + cc.instance := kh1; + cc.payload := gen_payload(kh1,5); + cc.src_timestamp := gen_duration(3 sec); + + -- TEST: ADD SAMPLE ON MAX_SAMPLES_PER_INSTANCE + + Log("R0,R5: RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Instance 1, Writer 0]", INFO); + Log("R0,R5: REJECTED [MAX_SAMPLES_PER_INSTANCE exceeded]", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 0; + rtps.ret_code := REJECTED; + -- READER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- READER 5 + ind <= 5; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 0 + AlertIf(empty_sample_head(0) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 33, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 13, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I1S1),11(I1S2)/22,33,44 + -- PAYLOAD MEMORY: 0(I1S1),11(I1S2),22(I1S2)/33,44 + -- INSTANCE MEMORY: 0(I1)/13,26 + -- ISTATE: I1:ALIVE + -- WRITER: W0:I1 + -- READER 5 + AlertIf(empty_sample_head(5) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(5) /= 33, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(5) /= 13, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I1S1),11(I1S2)/22,33,44 + -- PAYLOAD MEMORY: 0(I1S1),11(I1S2),22(I1S2)/33,44 + -- INSTANCE MEMORY: 0(I1)/13,26 + -- ISTATE: I1:ALIVE + -- WRITER: W0:I1 + + AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + + Log("R0,R5: DDS Operation TAKE [MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := TAKE; + dds.max_samples := 1; + dds.sstate := ANY_SAMPLE_STATE; + dds.istate := ANY_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + -- READER 0 + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- READER 5 + ind <= 5; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- READER 0 + AlertIf(empty_sample_head(0) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 0, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 13, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 11(I1S2)/22,33,44,0 + -- PAYLOAD MEMORY: 11(I1S2),22(I1S2)/0,33,44 + -- INSTANCE MEMORY: 0(I1)/13,26 + -- ISTATE: I1:ALIVE + -- WRITER: W0:I1 + -- READER 5 + AlertIf(empty_sample_head(5) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(5) /= 0, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(5) /= 13, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 11(I1S2)/22,33,44,0 + -- PAYLOAD MEMORY: 11(I1S2),22(I1S2)/0,33,44 + -- INSTANCE MEMORY: 0(I1)/13,26 + -- ISTATE: I1:ALIVE + -- WRITER: W0:I1 + + AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + + -- TEST: DISPOSE SAMPLE [KNOWN INSTANCE] + -- TEST: SAMPLE WITH SERIALIZED KEY [WITH KEY_HASH] + -- TEST: SAMPLE WITH UNALIGNED PAYLOAD [<1 SLOT] + + Log("R0,R5: RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Instance 1, Writer 0]", INFO); + Log("R0,R5: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 0; + rtps.ret_code := OK; + s := to_sample(cc,NOT_ALIVE_DISPOSED_INSTANCE_STATE); + s.inst := kh1; + add_sample(s,mem(0), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(5), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + -- READER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- READER 5 + ind <= 5; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 0 + AlertIf(empty_sample_head(0) /= 33, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 0, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 13, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 11(I1S2),22(I1S3)/33,44,0 + -- PAYLOAD MEMORY: 11(I1S2),22(I1S2)/0,33,44 + -- INSTANCE MEMORY: 0(I1)/13,26 + -- ISTATE: I1:DISPOSED + -- WRITER: W0:I1 + -- READER 5 + AlertIf(empty_sample_head(5) /= 33, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(5) /= 0, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(5) /= 13, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 11(I1S2),22(I1S3)/33,44,0 + -- PAYLOAD MEMORY: 11(I1S2),22(I1S2)/0,33,44 + -- INSTANCE MEMORY: 0(I1)/13,26 + -- ISTATE: I1:DISPOSED + -- WRITER: W0:I1 + + AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh2; + cc.payload := gen_payload(kh2,20); + cc.src_timestamp := gen_duration(4 sec); + + Log("R0,R5: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 2, Writer 1, Aligned Payload (2 Slots)]", INFO); + Log("R0,R5: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 1; + rtps.ret_code := OK; + s := to_sample(cc,ALIVE_INSTANCE_STATE); + add_sample(s,mem(0), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(5), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + -- READER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- READER 5 + ind <= 5; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 0 + AlertIf(empty_sample_head(0) /= 44, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 11(I1S2),22(I1S3),33(I2S1)/44,0 + -- PAYLOAD MEMORY: 11(I1S2),22(I1S2),0(I2S1),33(I2S1)/44 + -- INSTANCE MEMORY: 13(I2),0(I1)/26 + -- ISTATE: I1:DISPOSED, I2:ALIVE + -- WRITER: W0:I1, W1:I2 + -- READER 5 + AlertIf(empty_sample_head(5) /= 44, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(5) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(5) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 11(I1S2),22(I1S3),33(I2S1)/44,0 + -- PAYLOAD MEMORY: 11(I1S2),22(I1S2),0(I2S1),33(I2S1)/44 + -- INSTANCE MEMORY: 13(I2),0(I1)/26 + -- ISTATE: I1:DISPOSED, I2:ALIVE + -- WRITER: W0:I1, W1:I2 + + AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh3; + cc.payload := gen_payload(kh3,10); + cc.src_timestamp := gen_duration(5 sec); + + -- TEST: TEST SAMPLE WITH SERIALIZED KEY EFFECT ON PAYLOAD MEMORY FULLNESS + + Log("R0,R5: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 3, Writer 1, Aligned Payload]", INFO); + Log("R0,R5: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 1; + s := to_sample(cc,ALIVE_INSTANCE_STATE); + add_sample(s,mem(0), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(5), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + rtps.ret_code := OK; + -- READER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- READER 5 + ind <= 5; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 0 + AlertIf(empty_sample_head(0) /= 0, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 54, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 11(I1S2),22(I1S3),33(I2S1),44(I3S1)/0 + -- PAYLOAD MEMORY: 11(I1S2),22(I1S2),0(I2S1),33(I2S1),44(I3S1)/- + -- INSTANCE MEMORY: 26(I3),13(I2),0(I1)/- + -- ISTATE: I1:DISPOSED, I2:ALIVE, I3: ALIVE + -- WRITER: W0:I1, W1:I2,I3 + -- READER 5 + AlertIf(empty_sample_head(5) /= 0, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(5) /= 54, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(5) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 11(I1S2),22(I1S3),33(I2S1),44(I3S1)/0 + -- PAYLOAD MEMORY: 11(I1S2),22(I1S2),0(I2S1),33(I2S1),44(I3S1)/- + -- INSTANCE MEMORY: 26(I3),13(I2),0(I1)/- + -- ISTATE: I1:DISPOSED, I2:ALIVE, I3: ALIVE + -- WRITER: W0:I1, W1:I2,I3 + + AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + + -- TEST: REMOVE_WRITER [UNKNOWN WRITER] + + Log("R0,R5: RTPS Operation REMOVE_WRITER [Writer 2]", INFO); + Log("R0,R5: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := REMOVE_WRITER; + rtps.writer_pos := 2; + rtps.ret_code := OK; + -- READER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- READER 5 + ind <= 5; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 0 + AlertIf(empty_sample_head(0) /= 0, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 54, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 11(I1S2),22(I1S3),33(I2S1),44(I3S1)/0 + -- PAYLOAD MEMORY: 11(I1S2),22(I1S2),0(I2S1),33(I2S1),44(I3S1)/- + -- INSTANCE MEMORY: 26(I3),13(I2),0(I1)/- + -- ISTATE: I1:DISPOSED, I2:ALIVE, I3: ALIVE + -- WRITER: W0:I1, W1:I2,I3 + -- READER 5 + AlertIf(empty_sample_head(5) /= 0, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(5) /= 54, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(5) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 11(I1S2),22(I1S3),33(I2S1),44(I3S1)/0 + -- PAYLOAD MEMORY: 11(I1S2),22(I1S2),0(I2S1),33(I2S1),44(I3S1)/- + -- INSTANCE MEMORY: 26(I3),13(I2),0(I1)/- + -- ISTATE: I1:DISPOSED, I2:ALIVE, I3: ALIVE + -- WRITER: W0:I1, W1:I2,I3 + + AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + + Log("R0,R5: DDS Operation TAKE [MAX_SAMPLES 1, NOT_READ_SAMPLE_STATE, NOT_ALIVE_DISPOSED_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := TAKE; + dds.max_samples := 1; + dds.sstate := NOT_READ_SAMPLE_STATE; + dds.istate := NOT_ALIVE_DISPOSED_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + -- READER 0 + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- READER 5 + ind <= 5; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- READER 0 + AlertIf(empty_sample_head(0) /= 0, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 54, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 11(I1S2),33(I2S1),44(I3S1)/0,22 + -- PAYLOAD MEMORY: 11(I1S2),22(I1S2),0(I2S1),33(I2S1),44(I3S1)/- + -- INSTANCE MEMORY: 26(I3),13(I2),0(I1)/- + -- ISTATE: I1:DISPOSED, I2:ALIVE, I3: ALIVE + -- WRITER: W0:I1, W1:I2,I3 + -- READER 5 + AlertIf(empty_sample_head(5) /= 0, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(5) /= 54, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(5) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 11(I1S2),33(I2S1),44(I3S1)/0,22 + -- PAYLOAD MEMORY: 11(I1S2),22(I1S2),0(I2S1),33(I2S1),44(I3S1)/- + -- INSTANCE MEMORY: 26(I3),13(I2),0(I1)/- + -- ISTATE: I1:DISPOSED, I2:ALIVE, I3: ALIVE + -- WRITER: W0:I1, W1:I2,I3 + + AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh3; + cc.payload := gen_payload(kh3,10); + cc.src_timestamp := gen_duration(6 sec); + + -- TEST: ADD_CACHE_CHANGE ON PAYLOAD MEMORY FULL + + Log("R0,R5: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 3, Writer 2, Aligned Payload]", INFO); + Log("R0,R5: REJECTED [Payload Memory Full]", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 2; + rtps.ret_code := REJECTED; + -- READER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- READER 5 + ind <= 5; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 0 + AlertIf(empty_sample_head(0) /= 0, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 54, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 11(I1S2),33(I2S1),44(I3S1)/0,22 + -- PAYLOAD MEMORY: 11(I1S2),22(I1S2),0(I2S1),33(I2S1),44(I3S1)/- + -- INSTANCE MEMORY: 26(I3),13(I2),0(I1)/- + -- ISTATE: I1:DISPOSED, I2:ALIVE, I3: ALIVE + -- WRITER: W0:I1, W1:I2,I3 + -- READER 5 + AlertIf(empty_sample_head(5) /= 0, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(5) /= 54, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(5) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 11(I1S2),33(I2S1),44(I3S1)/0,22 + -- PAYLOAD MEMORY: 11(I1S2),22(I1S2),0(I2S1),33(I2S1),44(I3S1)/- + -- INSTANCE MEMORY: 26(I3),13(I2),0(I1)/- + -- ISTATE: I1:DISPOSED, I2:ALIVE, I3: ALIVE + -- WRITER: W0:I1, W1:I2,I3 + + AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + + Log("R0: DDS Operation TAKE [MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := TAKE; + dds.max_samples := 1; + dds.sstate := ANY_SAMPLE_STATE; + dds.istate := ANY_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + -- READER 0 + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- READER 5 + ind <= 5; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- READER 0 + AlertIf(empty_sample_head(0) /= 0, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 11, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 33(I2S1),44(I3S1)/0,22,11 + -- PAYLOAD MEMORY: 0(I2S1),33(I2S1),44(I3S1)/11,22 + -- INSTANCE MEMORY: 26(I3),13(I2),0(I1)/- + -- ISTATE: I1:DISPOSED, I2:ALIVE, I3: ALIVE + -- WRITER: W0:I1, W1:I2,I3 + -- READER 5 + AlertIf(empty_sample_head(5) /= 0, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(5) /= 11, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(5) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 33(I2S1),44(I3S1)/0,22,11 + -- PAYLOAD MEMORY: 0(I2S1),33(I2S1),44(I3S1)/11,22 + -- INSTANCE MEMORY: 26(I3),13(I2),0(I1)/- + -- ISTATE: I1:DISPOSED, I2:ALIVE, I3: ALIVE + -- WRITER: W0:I1, W1:I2,I3 + + AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + + Log("R0,R5: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 3, Writer 2, Aligned Payload]", INFO); + Log("R0,R5: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 2; + s := to_sample(cc,ALIVE_INSTANCE_STATE); + add_sample(s,mem(0), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(5), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + rtps.ret_code := OK; + -- READER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- READER 5 + ind <= 5; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 0 + AlertIf(empty_sample_head(0) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 22, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 33(I2S1),44(I3S1),0(I3S2)/22,11 + -- PAYLOAD MEMORY: 0(I2S1),33(I2S1),44(I3S1),11(I3S2)/22 + -- INSTANCE MEMORY: 26(I3),13(I2),0(I1)/- + -- ISTATE: I1:DISPOSED, I2:ALIVE, I3: ALIVE + -- WRITER: W0:I1, W1:I2,I3, W2:I3 + -- READER 5 + AlertIf(empty_sample_head(5) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(5) /= 22, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(5) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 33(I2S1),44(I3S1),0(I3S2)/22,11 + -- PAYLOAD MEMORY: 0(I2S1),33(I2S1),44(I3S1),11(I3S2)/22 + -- INSTANCE MEMORY: 26(I3),13(I2),0(I1)/- + -- ISTATE: I1:DISPOSED, I2:ALIVE, I3: ALIVE + -- WRITER: W0:I1, W1:I2,I3, W2:I3 + + AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh4; + cc.payload := gen_payload(kh4,10); + cc.src_timestamp := gen_duration(7 sec); + + -- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKOWN INSTANCE, WITHOUT STALE INSTANCE, WITH EMPTY INSTANCE] + + Log("R0,R5: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 4, Writer 1, Aligned Payload]", INFO); + Log("R0,R5: REJECTED [MAX_INSTANCES exceeded]", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 1; + rtps.ret_code := REJECTED; + -- READER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- READER 5 + ind <= 5; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 0 + AlertIf(empty_sample_head(0) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 22, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 33(I2S1),44(I3S1),0(I3S2)/22,11 + -- PAYLOAD MEMORY: 0(I2S1),33(I2S1),44(I3S1),11(I3S2)/22 + -- INSTANCE MEMORY: 26(I3),13(I2),0(I1)/- + -- ISTATE: I1:DISPOSED, I2:ALIVE, I3: ALIVE + -- WRITER: W0:I1, W1:I2,I3, W2:I3 + -- READER 5 + AlertIf(empty_sample_head(5) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(5) /= 22, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(5) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 33(I2S1),44(I3S1),0(I3S2)/22,11 + -- PAYLOAD MEMORY: 0(I2S1),33(I2S1),44(I3S1),11(I3S2)/22 + -- INSTANCE MEMORY: 26(I3),13(I2),0(I1)/- + -- ISTATE: I1:DISPOSED, I2:ALIVE, I3: ALIVE + -- WRITER: W0:I1, W1:I2,I3, W2:I3 + + AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + + -- TEST: REMOVE_WRITER [KNOWN WRITER (1 Instance)] + + Log("R0,R5: RTPS Operation REMOVE_WRITER [Writer 0]", INFO); + Log("R0,R5: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := REMOVE_WRITER; + rtps.writer_pos := 0; + change_istate(kh1, NOT_ALIVE_NO_WRITERS_INSTANCE_STATE, mem(0)); + change_istate(kh1, NOT_ALIVE_NO_WRITERS_INSTANCE_STATE, mem(5)); + rtps.ret_code := OK; + -- READER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- READER 5 + ind <= 5; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 0 + AlertIf(empty_sample_head(0) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 22, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 33(I2S1),44(I3S1),0(I3S2)/22,11 + -- PAYLOAD MEMORY: 0(I2S1),33(I2S1),44(I3S1),11(I3S2)/22 + -- INSTANCE MEMORY: 26(I3),13(I2),0(I1)/- + -- ISTATE: I1:DISPOSED, I2:ALIVE, I3: ALIVE + -- WRITER: W1:I2,I3, W2:I3 + -- READER 5 + AlertIf(empty_sample_head(5) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(5) /= 22, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(5) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 33(I2S1),44(I3S1),0(I3S2)/22,11 + -- PAYLOAD MEMORY: 0(I2S1),33(I2S1),44(I3S1),11(I3S2)/22 + -- INSTANCE MEMORY: 26(I3),13(I2),0(I1)/- + -- ISTATE: I1:DISPOSED, I2:ALIVE, I3: ALIVE + -- WRITER: W1:I2,I3, W2:I3 + + AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + + -- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKOWN INSTANCE, WITH STALE INSTANCE] + + Log("R0,R5: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 4, Writer 1, Aligned Payload]", INFO); + Log("R0,R5: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 1; + remove_inst(kh1, mem(0)); + remove_inst(kh1, mem(5)); + s := to_sample(cc,ALIVE_INSTANCE_STATE); + add_sample(s,mem(0), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(5), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + rtps.ret_code := OK; + -- READER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- READER 5 + ind <= 5; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 0 + AlertIf(empty_sample_head(0) /= 11, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 54, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 33(I2S1),44(I3S1),0(I3S2),22(I4S1)/11 + -- PAYLOAD MEMORY: 0(I2S1),33(I2S1),44(I3S1),11(I3S2),22(I4S1)/- + -- INSTANCE MEMORY: 26(I3),0(I4),13(I2)/- + -- ISTATE: I2:ALIVE, I3: ALIVE, I4:ALIVE + -- WRITER: W1:I2,I3,I4, W2:I3 + -- READER 5 + AlertIf(empty_sample_head(5) /= 11, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(5) /= 54, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(5) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 33(I2S1),44(I3S1),0(I3S2),22(I4S1)/11 + -- PAYLOAD MEMORY: 0(I2S1),33(I2S1),44(I3S1),11(I3S2),22(I4S1)/- + -- INSTANCE MEMORY: 26(I3),0(I4),13(I2)/- + -- ISTATE: I2:ALIVE, I3: ALIVE, I4:ALIVE + -- WRITER: W1:I2,I3,I4, W2:I3 + + AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + + -- VALIDATE STATE + + Log("R0,R5: DDS Operation READ [MAX_SAMPLES 4, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := READ; + dds.max_samples := 4; + dds.sstate := ANY_SAMPLE_STATE; + dds.istate := ANY_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + -- READER 0 + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- READER 5 + ind <= 5; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- READER 0 + AlertIf(empty_sample_head(0) /= 11, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 54, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 33(I2S1),44(I3S1),0(I3S2),22(I4S1)/11 + -- PAYLOAD MEMORY: 0(I2S1),33(I2S1),44(I3S1),11(I3S2),22(I4S1)/- + -- INSTANCE MEMORY: 26(I3),0(I4),13(I2)/- + -- ISTATE: I2:ALIVE, I3: ALIVE, I4:ALIVE + -- WRITER: W1:I2,I3,I4, W2:I3 + -- READER 5 + AlertIf(empty_sample_head(5) /= 11, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(5) /= 54, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(5) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 33(I2S1),44(I3S1),0(I3S2),22(I4S1)/11 + -- PAYLOAD MEMORY: 0(I2S1),33(I2S1),44(I3S1),11(I3S2),22(I4S1)/- + -- INSTANCE MEMORY: 26(I3),0(I4),13(I2)/- + -- ISTATE: I2:ALIVE, I3: ALIVE, I4:ALIVE + -- WRITER: W1:I2,I3,I4, W2:I3 + + AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + + Log("R0,R5: DDS Operation TAKE [MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := TAKE; + dds.max_samples := 1; + dds.sstate := ANY_SAMPLE_STATE; + dds.istate := ANY_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + -- READER 0 + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- READER 5 + ind <= 5; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- READER 0 + AlertIf(empty_sample_head(0) /= 11, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 0, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 44(I3S1),0(I3S2),22(I4S1)/11,33 + -- PAYLOAD MEMORY: 44(I3S1),11(I3S2),22(I4S1)/0,33 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I2)/- + -- ISTATE: I2:ALIVE, I3: ALIVE, I4:ALIVE + -- WRITER: W1:I2,I3,I4, W2:I3 + -- READER 5 + AlertIf(empty_sample_head(5) /= 11, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(5) /= 0, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(5) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 44(I3S1),0(I3S2),22(I4S1)/11,33 + -- PAYLOAD MEMORY: 44(I3S1),11(I3S2),22(I4S1)/0,33 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I2)/- + -- ISTATE: I2:ALIVE, I3: ALIVE, I4:ALIVE + -- WRITER: W1:I2,I3,I4, W2:I3 + + AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh1; + cc.payload := gen_payload(kh1,10); + cc.src_timestamp := gen_duration(8 sec); + + -- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKOWN INSTANCE, WITHOUT STALE INSTANCE] + + Log("R0,R5: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Aligned Payload]", INFO); + Log("R0,R5: REJECTED [MAX_INSTANCES exceeded]", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 0; + rtps.ret_code := REJECTED; + -- READER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- READER 5 + ind <= 5; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 0 + AlertIf(empty_sample_head(0) /= 11, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 0, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 44(I3S1),0(I3S2),22(I4S1)/11,33 + -- PAYLOAD MEMORY: 44(I3S1),11(I3S2),22(I4S1)/0,33 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I2)/- + -- ISTATE: I2:ALIVE, I3: ALIVE, I4:ALIVE + -- WRITER: W1:I2,I3,I4, W2:I3 + -- READER 5 + AlertIf(empty_sample_head(5) /= 11, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(5) /= 0, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(5) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 44(I3S1),0(I3S2),22(I4S1)/11,33 + -- PAYLOAD MEMORY: 44(I3S1),11(I3S2),22(I4S1)/0,33 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I2)/- + -- ISTATE: I2:ALIVE, I3: ALIVE, I4:ALIVE + -- WRITER: W1:I2,I3,I4, W2:I3 + + AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh4; + cc.payload := gen_payload(kh4,10); + cc.src_timestamp := gen_duration(9 sec); + + Log("R0,R5: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 4, Writer 1, Aligned Payload]", INFO); + Log("R0,R5: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 1; + s := to_sample(cc,ALIVE_INSTANCE_STATE); + add_sample(s,mem(0), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(5), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + rtps.ret_code := OK; + -- READER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- READER 5 + ind <= 5; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 0 + AlertIf(empty_sample_head(0) /= 33, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 33, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 44(I3S1),0(I3S2),22(I4S1),11(I4S2)/33 + -- PAYLOAD MEMORY: 44(I3S1),11(I3S2),22(I4S1),0(I4S2)/33 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I2)/- + -- ISTATE: I2:ALIVE, I3: ALIVE, I4:ALIVE + -- WRITER: W1:I2,I3,I4, W2:I3 + -- READER 5 + AlertIf(empty_sample_head(5) /= 33, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(5) /= 33, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(5) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 44(I3S1),0(I3S2),22(I4S1),11(I4S2)/33 + -- PAYLOAD MEMORY: 44(I3S1),11(I3S2),22(I4S1),0(I4S2)/33 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I2)/- + -- ISTATE: I2:ALIVE, I3: ALIVE, I4:ALIVE + -- WRITER: W1:I2,I3,I4, W2:I3 + + AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh2; + cc.payload := gen_payload(kh2,10); + cc.src_timestamp := gen_duration(10 sec); + + -- TEST: ADD SAMPLE ON MAX_SAMPLES [KNOWN INSTANCE] + + Log("R0,R5: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 2, Writer 1, Aligned Payload]", INFO); + Log("R0,R5: REJECTED [MAX_SAMPLES exceeded]", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 1; + rtps.ret_code := REJECTED; + -- READER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- READER 5 + ind <= 5; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 0 + AlertIf(empty_sample_head(0) /= 33, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 33, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 44(I3S1),0(I3S2),22(I4S1),11(I4S2)/33 + -- PAYLOAD MEMORY: 44(I3S1),11(I3S2),22(I4S1),0(I4S2)/33 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I2)/- + -- ISTATE: I2:ALIVE, I3: ALIVE, I4:ALIVE + -- WRITER: W1:I2,I3,I4, W2:I3 + -- READER 5 + AlertIf(empty_sample_head(5) /= 33, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(5) /= 33, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(5) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 44(I3S1),0(I3S2),22(I4S1),11(I4S2)/33 + -- PAYLOAD MEMORY: 44(I3S1),11(I3S2),22(I4S1),0(I4S2)/33 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I2)/- + -- ISTATE: I2:ALIVE, I3: ALIVE, I4:ALIVE + -- WRITER: W1:I2,I3,I4, W2:I3 + + AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh1; + cc.payload := gen_payload(kh1,10); + cc.src_timestamp := gen_duration(11 sec); + + -- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE, WITHOUT STALE INSTANCE] + + Log("R0,R5: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Aligned Payload]", INFO); + Log("R0,R5: REJECTED [MAX_SAMPLES exceeded]", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 0; + rtps.ret_code := REJECTED; + -- READER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- READER 5 + ind <= 5; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 0 + AlertIf(empty_sample_head(0) /= 33, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 33, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 44(I3S1),0(I3S2),22(I4S1),11(I4S2)/33 + -- PAYLOAD MEMORY: 44(I3S1),11(I3S2),22(I4S1),0(I4S2)/33 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I2)/- + -- ISTATE: I2:ALIVE, I3: ALIVE, I4:ALIVE + -- WRITER: W1:I2,I3,I4, W2:I3 + -- READER 5 + AlertIf(empty_sample_head(5) /= 33, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(5) /= 33, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(5) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 44(I3S1),0(I3S2),22(I4S1),11(I4S2)/33 + -- PAYLOAD MEMORY: 44(I3S1),11(I3S2),22(I4S1),0(I4S2)/33 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I2)/- + -- ISTATE: I2:ALIVE, I3: ALIVE, I4:ALIVE + -- WRITER: W1:I2,I3,I4, W2:I3 + + AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + + -- TEST: REMOVE_WRITER [KNOWN WRITER (>1 Instances)] + -- TEST: REMOVE_WRITER [NOT_ALIVE_NO_WRITERS Transition] + -- TEST: REMOVE_WRITER [Multiple Pending NOT_ALIVE_NO_WRITERS Transitions] + -- TEST: REMOVE_WRITER ON MAX_SAMPLES [NOT_ALIVE_NO_WRITERS Transition] + -- TEST: REMOVE_WRITER ON MAX_SAMPLES_PER_INSTANCE [NOT_ALIVE_NO_WRITERS Transition] + + Log("R0,R5: RTPS Operation REMOVE_WRITER [Writer 1]", INFO); + Log("R0,R5: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := REMOVE_WRITER; + rtps.writer_pos := 1; + change_istate(kh2, NOT_ALIVE_NO_WRITERS_INSTANCE_STATE, mem(0)); + change_istate(kh2, NOT_ALIVE_NO_WRITERS_INSTANCE_STATE, mem(5)); + change_istate(kh4, NOT_ALIVE_NO_WRITERS_INSTANCE_STATE, mem(0)); + change_istate(kh4, NOT_ALIVE_NO_WRITERS_INSTANCE_STATE, mem(5)); + rtps.ret_code := OK; + -- READER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- READER 5 + ind <= 5; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 0 + AlertIf(empty_sample_head(0) /= 33, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 33, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 44(I3S1),0(I3S2),22(I4S1),11(I4S2)/33 + -- PAYLOAD MEMORY: 44(I3S1),11(I3S2),22(I4S1),0(I4S2)/33 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I2)/- + -- ISTATE: I2:NO_WRITER, I3: ALIVE, I4:NO_WRITER + -- WRITER: W2:I3 + -- READER 5 + AlertIf(empty_sample_head(5) /= 33, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(5) /= 33, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(5) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 44(I3S1),0(I3S2),22(I4S1),11(I4S2)/33 + -- PAYLOAD MEMORY: 44(I3S1),11(I3S2),22(I4S1),0(I4S2)/33 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I2)/- + -- ISTATE: I2:NO_WRITER, I3: ALIVE, I4:NO_WRITER + -- WRITER: W2:I3 + + -- NOTE: Because of the NOT_ALIVE_NO_WRITERS transition 2 Samples are pending generation, + -- but are waiting for space. + + AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := TRUE; + cc.kind := NOT_ALIVE_UNREGISTERED; + cc.instance := kh2; + cc.src_timestamp := check_time; + + Log("R0,R5: DDS Operation TAKE [MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := TAKE; + dds.max_samples := 1; + dds.sstate := ANY_SAMPLE_STATE; + dds.istate := ANY_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + s := to_sample(cc,NOT_ALIVE_NO_WRITERS_INSTANCE_STATE); + add_sample(s,mem(0), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(5), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + -- READER 0 + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- READER 5 + ind <= 5; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- READER 0 + AlertIf(empty_sample_head(0) /= 44, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I3S2),22(I4S1),11(I4S2),33(I2S2)/44 + -- PAYLOAD MEMORY: 11(I3S2),22(I4S1),0(I4S2)/44,33 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I2)/- + -- ISTATE: I2:NO_WRITER, I3: ALIVE, I4:NO_WRITER + -- WRITER: W2:I3 + -- READER 5 + AlertIf(empty_sample_head(5) /= 44, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(5) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(5) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I3S2),22(I4S1),11(I4S2),33(I2S2)/44 + -- PAYLOAD MEMORY: 11(I3S2),22(I4S1),0(I4S2)/44,33 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I2)/- + -- ISTATE: I2:NO_WRITER, I3: ALIVE, I4:NO_WRITER + -- WRITER: W2:I3 + + -- NOTE: Even though the sample of I4 should be generated first, because it hits the MAX_SAMPLES_PER_INSTANCE + -- Limit, it is skipped and the I2 sample is generated instead. + + AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + + -- NOTE: We read the current KH4 Samples, so that we can easily remove the new KH4 Sample + Log("R0,R5: DDS Operation READ_INSTANCE [Instance 4, MAX_SAMPLES 2, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := READ_INSTANCE; + dds.max_samples := 2; + dds.sstate := ANY_SAMPLE_STATE; + dds.istate := ANY_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + dds.inst := kh4; + -- READER 0 + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- READER 5 + ind <= 5; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- READER 0 + AlertIf(empty_sample_head(0) /= 44, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I3S2),22(I4S1),11(I4S2),33(I2S2)/44 + -- PAYLOAD MEMORY: 11(I3S2),22(I4S1),0(I4S2)/44,33 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I2)/- + -- ISTATE: I2:NO_WRITER, I3: ALIVE, I4:NO_WRITER + -- WRITER: W2:I3 + -- READER 5 + AlertIf(empty_sample_head(5) /= 44, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(5) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(5) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I3S2),22(I4S1),11(I4S2),33(I2S2)/44 + -- PAYLOAD MEMORY: 11(I3S2),22(I4S1),0(I4S2)/44,33 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I2)/- + -- ISTATE: I2:NO_WRITER, I3: ALIVE, I4:NO_WRITER + -- WRITER: W2:I3 + + AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := TRUE; + cc.kind := NOT_ALIVE_UNREGISTERED; + cc.instance := kh4; + cc.src_timestamp := check_time; + + Log("R0,R5: DDS Operation TAKE_INSTANCE [Instance 4, MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := TAKE_INSTANCE; + dds.max_samples := 1; + dds.sstate := ANY_SAMPLE_STATE; + dds.istate := ANY_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + dds.inst := kh4; + s := to_sample(cc,NOT_ALIVE_NO_WRITERS_INSTANCE_STATE); + add_sample(s,mem(0), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(5), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + -- READER 0 + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- READER 5 + ind <= 5; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- READER 0 + AlertIf(empty_sample_head(0) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 22, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I3S2),11(I4S2),33(I2S2),44(I4S3)/22 + -- PAYLOAD MEMORY: 11(I3S2),0(I4S2)/22,44,33 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I2)/- + -- ISTATE: I2:NO_WRITER, I3: ALIVE, I4:NO_WRITER + -- WRITER: W2:I3 + -- READER 5 + AlertIf(empty_sample_head(5) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(5) /= 22, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(5) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I3S2),11(I4S2),33(I2S2),44(I4S3)/22 + -- PAYLOAD MEMORY: 11(I3S2),0(I4S2)/22,44,33 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I2)/- + -- ISTATE: I2:NO_WRITER, I3: ALIVE, I4:NO_WRITER + -- WRITER: W2:I3 + + AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + + Log("R0: DDS Operation TAKE_INSTANCE [Instance 4, MAX_SAMPLES 1, NOT_READ_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := TAKE_INSTANCE; + dds.max_samples := 1; + dds.sstate := NOT_READ_SAMPLE_STATE; + dds.istate := ANY_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + dds.inst := kh4; + -- READER 0 + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- READER 5 + ind <= 5; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- READER 0 + AlertIf(empty_sample_head(0) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 22, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I3S2),11(I4S2),33(I2S2)/22,44 + -- PAYLOAD MEMORY: 11(I3S2),0(I4S2)/22,44,33 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I2)/- + -- ISTATE: I2:NO_WRITER, I3: ALIVE, I4:NO_WRITER + -- WRITER: W2:I3 + -- READER 5 + AlertIf(empty_sample_head(5) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(5) /= 22, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(5) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I3S2),11(I4S2),33(I2S2)/22,44 + -- PAYLOAD MEMORY: 11(I3S2),0(I4S2)/22,44,33 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I2)/- + -- ISTATE: I2:NO_WRITER, I3: ALIVE, I4:NO_WRITER + -- WRITER: W2:I3 + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := TRUE; + cc.kind := NOT_ALIVE_DISPOSED; + cc.instance := HANDLE_NIL; + cc.payload := gen_payload(kh4,5); + cc.src_timestamp := gen_duration(12 sec); + + -- TEST: DISPOSE SAMPLE [NOT_ALIVE_NO_WRITERS INSTANCE] + -- TEST: SAMPLE WITH SERIALIZED KEY [WITHOUT KEY_HASH] + + Log("R0,R5: RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Instance 4, Writer 1]", INFO); + Log("R0,R5: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 1; + s := to_sample(cc,NOT_ALIVE_DISPOSED_INSTANCE_STATE); + s.inst := kh4; + add_sample(s,mem(0), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(5), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + rtps.ret_code := OK; + -- READER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- READER 5 + ind <= 5; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 0 + AlertIf(empty_sample_head(0) /= 44, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 22, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I3S2),11(I4S2),33(I2S2),22(I4S4)/44 + -- PAYLOAD MEMORY: 11(I3S2),0(I4S2)/22,44,33 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I2)/- + -- ISTATE: I2:NO_WRITER, I3: ALIVE, I4:DISPOSED + -- WRITER: W1:I4, W2:I3 + -- READER 5 + AlertIf(empty_sample_head(5) /= 44, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(5) /= 22, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(5) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I3S2),11(I4S2),33(I2S2),22(I4S4)/44 + -- PAYLOAD MEMORY: 11(I3S2),0(I4S2)/22,44,33 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I2)/- + -- ISTATE: I2:NO_WRITER, I3: ALIVE, I4:DISPOSED + -- WRITER: W1:I4, W2:I3 + + AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh1; + cc.payload := gen_payload(kh1,10); + cc.src_timestamp := gen_duration(13 sec); + + -- TEST: ADD SAMPLE ON MAX_SAMPLES [UNKNOWN INSTANCE] + -- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE, WITH STALE INSTANCE] + + Log("R0,R5: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Aligned Payload]", INFO); + Log("R0,R5: REJECTED [MAX_SAMPLES exceeded]", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 0; + rtps.ret_code := REJECTED; + -- READER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- READER 5 + ind <= 5; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 0 + AlertIf(empty_sample_head(0) /= 44, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 22, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I3S2),11(I4S2),33(I2S2),22(I4S4)/44 + -- PAYLOAD MEMORY: 11(I3S2),0(I4S2)/22,44,33 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I2)/- + -- ISTATE: I2:NO_WRITER, I3: ALIVE, I4:DISPOSED + -- WRITER: W1:I4, W2:I3 + -- READER 5 + AlertIf(empty_sample_head(5) /= 44, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(5) /= 22, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(5) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I3S2),11(I4S2),33(I2S2),22(I4S4)/44 + -- PAYLOAD MEMORY: 11(I3S2),0(I4S2)/22,44,33 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I2)/- + -- ISTATE: I2:NO_WRITER, I3: ALIVE, I4:DISPOSED + -- WRITER: W1:I4, W2:I3 + + AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + + Log("R0,R5: DDS Operation TAKE [MAX_SAMPLES 2, NOT_READ_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := TAKE; + dds.max_samples := 2; + dds.sstate := NOT_READ_SAMPLE_STATE; + dds.istate := ANY_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + -- READER 0 + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- READER 5 + ind <= 5; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- READER 0 + AlertIf(empty_sample_head(0) /= 44, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 22, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I3S2),11(I4S2)/44,33,22 + -- PAYLOAD MEMORY: 11(I3S2),0(I4S2)/22,44,33 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I2)/- + -- ISTATE: I2:NO_WRITER, I3: ALIVE, I4:DISPOSED + -- WRITER: W1:I4, W2:I3 + -- READER 5 + AlertIf(empty_sample_head(5) /= 44, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(5) /= 22, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(5) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I3S2),11(I4S2)/44,33,22 + -- PAYLOAD MEMORY: 11(I3S2),0(I4S2)/22,44,33 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I2)/- + -- ISTATE: I2:NO_WRITER, I3: ALIVE, I4:DISPOSED + -- WRITER: W1:I4, W2:I3 + + AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh3; + cc.payload := gen_payload(kh3,10); + cc.src_timestamp := gen_duration(14 sec); + + Log("R0,R5: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 3, Writer 2, Aligned Payload]", INFO); + Log("R0,R5: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 2; + rtps.ret_code := OK; + s := to_sample(cc,ALIVE_INSTANCE_STATE); + add_sample(s,mem(0), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(5), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + -- READER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- READER 5 + ind <= 5; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 0 + AlertIf(empty_sample_head(0) /= 33, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I3S2),11(I4S2),44(I3S3)/33,22 + -- PAYLOAD MEMORY: 11(I3S2),0(I4S2),22(I3S3)/44,33 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I2)/- + -- ISTATE: I2:NO_WRITER, I3: ALIVE, I4:DISPOSED + -- WRITER: W1:I4, W2:I3 + -- READER 5 + AlertIf(empty_sample_head(5) /= 33, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(5) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(5) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I3S2),11(I4S2),44(I3S3)/33,22 + -- PAYLOAD MEMORY: 11(I3S2),0(I4S2),22(I3S3)/44,33 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I2)/- + -- ISTATE: I2:NO_WRITER, I3: ALIVE, I4:DISPOSED + -- WRITER: W1:I4, W2:I3 + + AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh1; + cc.payload := gen_payload(kh1,30); + cc.src_timestamp := gen_duration(15,0); + + -- TEST: ADD SAMPLE BIGGER THAN AVAILABLE MEMORY SPACE + + Log("R0,R5: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Aligned Payload (3 Slots)]", INFO); + Log("R0,R5: REJECTED [Payload Memory Full]", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 0; + rtps.ret_code := REJECTED; + -- READER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- READER 5 + ind <= 5; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 0 + AlertIf(empty_sample_head(0) /= 33, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I3S2),11(I4S2),44(I3S3)/33,22 + -- PAYLOAD MEMORY: 11(I3S2),0(I4S2),22(I3S3)/44,33 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I2)/- + -- ISTATE: I2:NO_WRITER, I3: ALIVE, I4:DISPOSED + -- WRITER: W1:I4, W2:I3 + -- READER 5 + AlertIf(empty_sample_head(5) /= 33, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(5) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(5) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I3S2),11(I4S2),44(I3S3)/33,22 + -- PAYLOAD MEMORY: 11(I3S2),0(I4S2),22(I3S3)/44,33 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I2)/- + -- ISTATE: I2:NO_WRITER, I3: ALIVE, I4:DISPOSED + -- WRITER: W1:I4, W2:I3 + + AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh1; + cc.payload := gen_payload(kh1,20); + cc.src_timestamp := gen_duration(16 sec); + + Log("R0,R5: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Aligned Payload (2 Slots)]", INFO); + Log("R0,R5: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 0; + remove_inst(kh2, mem(0)); + remove_inst(kh2, mem(5)); + s := to_sample(cc,ALIVE_INSTANCE_STATE); + add_sample(s,mem(0), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(5), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + rtps.ret_code := OK; + -- READER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- READER 5 + ind <= 5; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 0 + AlertIf(empty_sample_head(0) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 54, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I3S2),11(I4S2),44(I3S3),33(I1S1)/22 + -- PAYLOAD MEMORY: 11(I3S2),0(I4S2),22(I3S3),44(I1S1),33(I1S1)/- + -- INSTANCE MEMORY: 26(I3),0(I4),13(I1)/- + -- ISTATE: I1:ALIVE, I3: ALIVE, I4:DISPOSED + -- WRITER: W0:I1, W1:I4, W2:I3 + -- READER 5 + AlertIf(empty_sample_head(5) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(5) /= 54, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(5) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I3S2),11(I4S2),44(I3S3),33(I1S1)/22 + -- PAYLOAD MEMORY: 11(I3S2),0(I4S2),22(I3S3),44(I1S1),33(I1S1)/- + -- INSTANCE MEMORY: 26(I3),0(I4),13(I1)/- + -- ISTATE: I1:ALIVE, I3: ALIVE, I4:DISPOSED + -- WRITER: W0:I1, W1:I4, W2:I3 + + AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + + -- VALIDATE STATE + + Log("R0,R5: DDS Operation TAKE [MAX_SAMPLES 4, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := TAKE; + dds.max_samples := 4; + dds.sstate := ANY_SAMPLE_STATE; + dds.istate := ANY_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + -- READER 0 + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- READER 5 + ind <= 5; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- READER 0 + AlertIf(empty_sample_head(0) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: -/22,0,44,11,33 + -- PAYLOAD MEMORY: -/44,33,0,22,11 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I1)/- + -- ISTATE: I1:ALIVE, I3: ALIVE, I4:DISPOSED + -- WRITER: W0:I1, W1:I4, W2:I3 + -- READER 5 + AlertIf(empty_sample_head(5) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(5) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(5) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: -/22,0,44,11,33 + -- PAYLOAD MEMORY: -/44,33,0,22,11 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I1)/- + -- ISTATE: I1:ALIVE, I3: ALIVE, I4:DISPOSED + -- WRITER: W0:I1, W1:I4, W2:I3 + + -- NOTE: Samples are removed in INSTANCE presentation order + + AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := TRUE; + cc.kind := NOT_ALIVE_DISPOSED; + cc.instance := kh4; + cc.payload := gen_payload(kh4,5); + cc.src_timestamp := gen_duration(17 sec); + + -- TEST: DISPOSE SAMPLE [NOT_ALIVE_DISPOSED INSTANCE] + + Log("R0,R5: RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Instance 4, Writer 0]", INFO); + Log("R0,R5: DROPPED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 0; + rtps.ret_code := OK; + -- READER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- READER 5 + ind <= 5; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 0 + AlertIf(empty_sample_head(0) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: -/22,0,44,11,33 + -- PAYLOAD MEMORY: -/44,33,0,22,11 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I1)/- + -- ISTATE: I1:ALIVE, I3: ALIVE, I4:DISPOSED + -- WRITER: W0:I1,I4 W1:I4, W2:I3 + -- READER 5 + AlertIf(empty_sample_head(5) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(5) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(5) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: -/22,0,44,11,33 + -- PAYLOAD MEMORY: -/44,33,0,22,11 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I1)/- + -- ISTATE: I1:ALIVE, I3: ALIVE, I4:DISPOSED + -- WRITER: W0:I1,I4 W1:I4, W2:I3 + + AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := TRUE; + cc.kind := NOT_ALIVE_UNREGISTERED; + cc.instance := kh4; + cc.payload := gen_payload(kh4,5); + cc.src_timestamp := gen_duration(18 sec); + + -- TEST: UNREGISTER SAMPLE [KNOWN INSTANCE, KNOWN WRITER] + -- TEST: UNREGISTER SAMPLE [NOT_ALIVE_DISPOSED INSTANCE] + + Log("R0,R5: RTPS Operation ADD_CACHE_CHANGE [UNREGISTER, Instance 4, Writer 0]", INFO); + Log("R0,R5: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 0; + rtps.ret_code := OK; + -- READER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- READER 5 + ind <= 5; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 0 + AlertIf(empty_sample_head(0) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: -/22,0,44,11,33 + -- PAYLOAD MEMORY: -/44,33,0,22,11 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I1)/- + -- ISTATE: I1:ALIVE, I3: ALIVE, I4:DISPOSED + -- WRITER: W0:I1 W1:I4, W2:I3 + -- READER 5 + AlertIf(empty_sample_head(5) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(5) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(5) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: -/22,0,44,11,33 + -- PAYLOAD MEMORY: -/44,33,0,22,11 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I1)/- + -- ISTATE: I1:ALIVE, I3: ALIVE, I4:DISPOSED + -- WRITER: W0:I1 W1:I4, W2:I3 + + AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := TRUE; + cc.kind := NOT_ALIVE_UNREGISTERED; + cc.instance := kh1; + cc.payload := gen_payload(kh1,5); + cc.src_timestamp := gen_duration(19 sec); + + -- TEST: UNREGISTER SAMPLE [KNOWN INSTANCE, UNKNOWN WRITER] + + Log("R0,R5: RTPS Operation ADD_CACHE_CHANGE [UNREGISTER, Instance 1, Writer 1]", INFO); + Log("R0,R5: DROPPED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 1; + rtps.ret_code := OK; + -- READER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- READER 5 + ind <= 5; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 0 + AlertIf(empty_sample_head(0) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: -/22,0,44,11,33 + -- PAYLOAD MEMORY: -/44,33,0,22,11 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I1)/- + -- ISTATE: I1:ALIVE, I3: ALIVE, I4:DISPOSED + -- WRITER: W0:I1 W1:I4, W2:I3 + -- READER 5 + AlertIf(empty_sample_head(5) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(5) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(5) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: -/22,0,44,11,33 + -- PAYLOAD MEMORY: -/44,33,0,22,11 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I1)/- + -- ISTATE: I1:ALIVE, I3: ALIVE, I4:DISPOSED + -- WRITER: W0:I1 W1:I4, W2:I3 + + AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := TRUE; + cc.kind := NOT_ALIVE_UNREGISTERED; + cc.instance := kh2; + cc.payload := gen_payload(kh2,5); + cc.src_timestamp := gen_duration(20 sec); + + -- TEST: UNREGISTER SAMPLE [UNKNOWN INSTANCE] + + Log("R0,R5: RTPS Operation ADD_CACHE_CHANGE [UNREGISTER, Instance 2, Writer 1]", INFO); + Log("R0,R5: DROPPED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 1; + rtps.ret_code := OK; + -- READER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- READER 5 + ind <= 5; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 0 + AlertIf(empty_sample_head(0) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: -/22,0,44,11,33 + -- PAYLOAD MEMORY: -/44,33,0,22,11 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I1)/- + -- ISTATE: I1:ALIVE, I3: ALIVE, I4:DISPOSED + -- WRITER: W0:I1 W1:I4, W2:I3 + -- READER 5 + AlertIf(empty_sample_head(5) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(5) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(5) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: -/22,0,44,11,33 + -- PAYLOAD MEMORY: -/44,33,0,22,11 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I1)/- + -- ISTATE: I1:ALIVE, I3: ALIVE, I4:DISPOSED + -- WRITER: W0:I1 W1:I4, W2:I3 + + AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := TRUE; + cc.kind := NOT_ALIVE_UNREGISTERED; + cc.instance := kh1; + cc.payload := gen_payload(kh1,5); + cc.src_timestamp := gen_duration(21 sec); + + Log("R0,R5: RTPS Operation ADD_CACHE_CHANGE [UNREGISTER, Instance 1, Writer 0]", INFO); + Log("R0,R5: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 0; + s := to_sample(cc,NOT_ALIVE_NO_WRITERS_INSTANCE_STATE); + add_sample(s,mem(0), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(5), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + rtps.ret_code := OK; + -- READER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- READER 5 + ind <= 5; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 0 + AlertIf(empty_sample_head(0) /= 0, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 22(I1S2)/0,44,11,33 + -- PAYLOAD MEMORY: -/44,33,0,22,11 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I1)/- + -- ISTATE: I1:NO_WRITERS, I3: ALIVE, I4:DISPOSED + -- WRITER: W1:I4, W2:I3 + -- READER 5 + AlertIf(empty_sample_head(5) /= 0, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(5) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(5) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 22(I1S2)/0,44,11,33 + -- PAYLOAD MEMORY: -/44,33,0,22,11 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I1)/- + -- ISTATE: I1:NO_WRITERS, I3: ALIVE, I4:DISPOSED + -- WRITER: W1:I4, W2:I3 + + AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := TRUE; + cc.kind := NOT_ALIVE_UNREGISTERED; + cc.instance := kh1; + cc.payload := gen_payload(kh1,5); + cc.src_timestamp := gen_duration(22 sec); + + -- TEST: UNREGISTER SAMPLE [NOT_ALIVE_NO_WRITERS INSTANCE] + + Log("R0,R5: RTPS Operation ADD_CACHE_CHANGE [UNREGISTER, Instance 1, Writer 2]", INFO); + Log("R0,R5: DROPPED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 2; + rtps.ret_code := OK; + -- READER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- READER 5 + ind <= 5; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 0 + AlertIf(empty_sample_head(0) /= 0, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 22(I1S2)/0,44,11,33 + -- PAYLOAD MEMORY: -/44,33,0,22,11 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I1)/- + -- ISTATE: I1:NO_WRITERS, I3: ALIVE, I4:DISPOSED + -- WRITER: W1:I4, W2:I3 + -- READER 5 + AlertIf(empty_sample_head(5) /= 0, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(5) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(5) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 22(I1S2)/0,44,11,33 + -- PAYLOAD MEMORY: -/44,33,0,22,11 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I1)/- + -- ISTATE: I1:NO_WRITERS, I3: ALIVE, I4:DISPOSED + -- WRITER: W1:I4, W2:I3 + + AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := TRUE; + cc.kind := ALIVE_FILTERED; + cc.instance := kh1; + cc.payload := gen_payload(kh1,5); + cc.src_timestamp := gen_duration(23 sec); + + -- TEST: FILTER SAMPLE [KNOWN INSTANCE] + -- TEST: FILTER SAMPLE [NOT_ALIVE_NO_WRITERS INSTANCE] + + Log("R0,R5: RTPS Operation ADD_CACHE_CHANGE [FILTERED, Instance 1, Writer 2]", INFO); + Log("R0,R5: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + s := to_sample(cc,ALIVE_INSTANCE_STATE); + add_sample(s,mem(0), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(5), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + rtps.writer_pos := 2; + rtps.ret_code := OK; + -- READER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- READER 5 + ind <= 5; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 0 + AlertIf(empty_sample_head(0) /= 44, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 22(I1S2),0(I1S3)/44,11,33 + -- PAYLOAD MEMORY: -/44,33,0,22,11 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I1)/- + -- ISTATE: I1:ALIVE, I3: ALIVE, I4:DISPOSED + -- WRITER: W1:I4, W2:I1,I3 + -- READER 5 + AlertIf(empty_sample_head(5) /= 44, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(5) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(5) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 22(I1S2),0(I1S3)/44,11,33 + -- PAYLOAD MEMORY: -/44,33,0,22,11 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I1)/- + -- ISTATE: I1:ALIVE, I3: ALIVE, I4:DISPOSED + -- WRITER: W1:I4, W2:I1,I3 + + AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := TRUE; + cc.kind := NOT_ALIVE_UNREGISTERED; + cc.instance := kh4; + cc.payload := gen_payload(kh1,5); + cc.src_timestamp := gen_duration(24 sec); + + -- TEST: UNREGISTER SAMPLE [NOT_ALIVE_DISPOSED INSTANCE, STALE INSTANCE TRANSITION] + + Log("R0,R5: RTPS Operation ADD_CACHE_CHANGE [UNREGISTER, Instance 4, Writer 1]", INFO); + Log("R0,R5: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 1; + rtps.ret_code := OK; + -- READER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- READER 5 + ind <= 5; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 0 + AlertIf(empty_sample_head(0) /= 44, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 22(I1S2),0(I1S3)/44,11,33 + -- PAYLOAD MEMORY: -/44,33,0,22,11 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I1)/- + -- ISTATE: I1:ALIVE, I3: ALIVE, I4:DISPOSED + -- WRITER: W2:I1,I3 + -- READER 5 + AlertIf(empty_sample_head(5) /= 44, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(5) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(5) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 22(I1S2),0(I1S3)/44,11,33 + -- PAYLOAD MEMORY: -/44,33,0,22,11 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I1)/- + -- ISTATE: I1:ALIVE, I3: ALIVE, I4:DISPOSED + -- WRITER: W2:I1,I3 + + AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh2; + cc.payload := gen_payload(kh2,10); + cc.src_timestamp := gen_duration(25 sec); + + -- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKOWN INSTANCE, NOT_ALIVE_DISPOSED & STALE INSTANCE] + + Log("R0,R5: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 2, Writer 0, Aligned Payload]", INFO); + Log("R0,R5: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 0; + remove_inst(kh4, mem(0)); + remove_inst(kh4, mem(5)); + s := to_sample(cc,ALIVE_INSTANCE_STATE); + add_sample(s,mem(0), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(5), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + rtps.ret_code := OK; + -- READER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- READER 5 + ind <= 5; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 0 + AlertIf(empty_sample_head(0) /= 11, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 33, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 22(I1S2),0(I1S3),44(I2S1)/11,33 + -- PAYLOAD MEMORY: 44(I2S1)/33,0,22,11 + -- INSTANCE MEMORY: 26(I3),0(I2),13(I1)/- + -- ISTATE: I1:ALIVE, I2:ALIVE, I3: ALIVE + -- WRITER: W0:I2, W2:I1,I3 + -- READER 5 + AlertIf(empty_sample_head(5) /= 11, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(5) /= 33, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(5) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 22(I1S2),0(I1S3),44(I2S1)/11,33 + -- PAYLOAD MEMORY: 44(I2S1)/33,0,22,11 + -- INSTANCE MEMORY: 26(I3),0(I2),13(I1)/- + -- ISTATE: I1:ALIVE, I2:ALIVE, I3: ALIVE + -- WRITER: W0:I2, W2:I1,I3 + + AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + + -- VALIDATE STATE + + Log("R0,R5: DDS Operation TAKE [MAX_SAMPLES 4, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := TAKE; + dds.max_samples := 4; + dds.sstate := ANY_SAMPLE_STATE; + dds.istate := ANY_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + -- READER 0 + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- READER 5 + ind <= 5; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- READER 0 + AlertIf(empty_sample_head(0) /= 11, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: -/11,33,22,0,44 + -- PAYLOAD MEMORY: -/44,33,0,22,11, + -- INSTANCE MEMORY: 26(I3),0(I2),13(I1)/- + -- ISTATE: I1:ALIVE, I2:ALIVE, I3: ALIVE + -- WRITER: W0:I2, W2:I1,I3 + -- READER 5 + AlertIf(empty_sample_head(5) /= 11, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(5) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(5) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: -/11,33,22,0,44 + -- PAYLOAD MEMORY: -/44,33,0,22,11, + -- INSTANCE MEMORY: 26(I3),0(I2),13(I1)/- + -- ISTATE: I1:ALIVE, I2:ALIVE, I3: ALIVE + -- WRITER: W0:I2, W2:I1,I3 + + AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := TRUE; + cc.kind := NOT_ALIVE_DISPOSED; + cc.instance := kh1; + cc.payload := gen_payload(kh1,5); + cc.src_timestamp := gen_duration(26 sec); + + Log("R0,R5: RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Instance 1, Writer 2] (ACCEPTED)", INFO); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 2; + s := to_sample(cc,NOT_ALIVE_DISPOSED_INSTANCE_STATE); + add_sample(s,mem(0), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(5), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + rtps.ret_code := OK; + -- READER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- READER 5 + ind <= 5; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 0 + AlertIf(empty_sample_head(0) /= 33, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 11(I1S4)/33,22,0,44 + -- PAYLOAD MEMORY: -/44,33,0,22,11, + -- INSTANCE MEMORY: 26(I3),0(I2),13(I1)/- + -- ISTATE: I1:DISPOSED, I2:ALIVE, I3: ALIVE + -- WRITER: W0:I2, W2:I1,I3 + -- READER 5 + AlertIf(empty_sample_head(5) /= 33, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(5) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(5) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 11(I1S4)/33,22,0,44 + -- PAYLOAD MEMORY: -/44,33,0,22,11, + -- INSTANCE MEMORY: 26(I3),0(I2),13(I1)/- + -- ISTATE: I1:DISPOSED, I2:ALIVE, I3: ALIVE + -- WRITER: W0:I2, W2:I1,I3 + + AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := TRUE; + cc.kind := ALIVE_FILTERED; + cc.instance := kh1; + cc.payload := gen_payload(kh1,5); + cc.src_timestamp := gen_duration(27 sec); + + -- TEST: FILTER SAMPLE [NOT_ALIVE_DISPOSED INSTANCE] + + Log("R0,R5: RTPS Operation ADD_CACHE_CHANGE [FILTERED, Instance 1, Writer 2]", INFO); + Log("R0,R5: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + s := to_sample(cc,ALIVE_INSTANCE_STATE); + add_sample(s,mem(0), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(5), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + rtps.writer_pos := 2; + rtps.ret_code := OK; + -- READER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- READER 5 + ind <= 5; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 0 + AlertIf(empty_sample_head(0) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 11(I1S4),33(I1S5)/22,0,44 + -- PAYLOAD MEMORY: -/44,33,0,22,11 + -- INSTANCE MEMORY: 26(I3),0(I2),13(I1)/- + -- ISTATE: I1:ALIVE, I2:ALIVE, I3: ALIVE + -- WRITER: W0:I2, W2:I1,I3 + -- READER 5 + AlertIf(empty_sample_head(5) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(5) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(5) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 11(I1S4),33(I1S5)/22,0,44 + -- PAYLOAD MEMORY: -/44,33,0,22,11 + -- INSTANCE MEMORY: 26(I3),0(I2),13(I1)/- + -- ISTATE: I1:ALIVE, I2:ALIVE, I3: ALIVE + -- WRITER: W0:I2, W2:I1,I3 + + AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := TRUE; + cc.kind := ALIVE_FILTERED; + cc.instance := kh4; + cc.payload := gen_payload(kh4,5); + cc.src_timestamp := gen_duration(28 sec); + + -- TEST: FILTER SAMPLE [UNKNOWN INSTANCE] + + Log("R0,R5: RTPS Operation ADD_CACHE_CHANGE [FILTERED, Instance 4, Writer 1]", INFO); + Log("R0,R5: DROPPED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 1; + rtps.ret_code := OK; + -- READER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- READER 5 + ind <= 5; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 0 + AlertIf(empty_sample_head(0) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 11(I1S4),33(I1S5)/22,0,44 + -- PAYLOAD MEMORY: -/44,33,0,22,11 + -- INSTANCE MEMORY: 26(I3),0(I2),13(I1)/- + -- ISTATE: I1:ALIVE, I2:ALIVE, I3: ALIVE + -- WRITER: W0:I2, W2:I1,I3 + -- READER 5 + AlertIf(empty_sample_head(5) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(5) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(5) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 11(I1S4),33(I1S5)/22,0,44 + -- PAYLOAD MEMORY: -/44,33,0,22,11 + -- INSTANCE MEMORY: 26(I3),0(I2),13(I1)/- + -- ISTATE: I1:ALIVE, I2:ALIVE, I3: ALIVE + -- WRITER: W0:I2, W2:I1,I3 + + AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + + -- TEST: SAMPLE WITH EARLY TIMESTAMP [TIMESTAMP EARLIER THAN LAST READ] + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh3; + cc.payload := gen_payload(kh3,10); + cc.src_timestamp := gen_duration(10 sec); + + Log("R0,R5: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 3, Writer 2, Aligned Payload]", INFO); + Log("R0: ACCEPTED", DEBUG); + Log("R5: DROPPED [Timestamp earlier than last read]", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 2; + s := to_sample(cc,ALIVE_INSTANCE_STATE); + add_sample(s,mem(0), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + rtps.ret_code := OK; + -- READER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- READER 5 + ind <= 5; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 0 + AlertIf(empty_sample_head(0) /= 0, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 33, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 11(I1S4),33(I1S5),22(I3S4)/0,44 + -- PAYLOAD MEMORY: 44(I3S4)/33,0,22,11 + -- INSTANCE MEMORY: 26(I3),0(I2),13(I1)/- + -- ISTATE: I1:ALIVE, I2:ALIVE, I3: ALIVE + -- WRITER: W0:I2, W2:I1,I3 + -- READER 5 + AlertIf(empty_sample_head(5) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(5) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(5) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 11(I1S4),33(I1S5)/22,0,44 + -- PAYLOAD MEMORY: -/44,33,0,22,11 + -- INSTANCE MEMORY: 26(I3),0(I2),13(I1)/- + -- ISTATE: I1:ALIVE, I2:ALIVE, I3: ALIVE + -- WRITER: W0:I2, W2:I1,I3 + + AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := TRUE; + cc.kind := NOT_ALIVE_UNREGISTERED; + cc.instance := kh2; + cc.payload := gen_payload(kh2,5); + cc.src_timestamp := gen_duration(29 sec); + + Log("R0,R5: RTPS Operation ADD_CACHE_CHANGE [UNREGISTER, Instance 2, Writer 0]", INFO); + Log("R0,R5: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 0; + s := to_sample(cc,NOT_ALIVE_NO_WRITERS_INSTANCE_STATE); + add_sample(s,mem(0), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(5), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + rtps.ret_code := OK; + -- READER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- READER 5 + ind <= 5; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 0 + AlertIf(empty_sample_head(0) /= 44, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 33, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 11(I1S4),33(I1S5),22(I3S4),0(I2S2)/44 + -- PAYLOAD MEMORY: 44(I3S4)/33,0,22,11 + -- INSTANCE MEMORY: 26(I3),0(I2),13(I1)/- + -- ISTATE: I1:ALIVE, I2:NO_WRITERS, I3: ALIVE + -- WRITER: W2:I1,I3 + -- READER 5 + AlertIf(empty_sample_head(5) /= 0, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(5) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(5) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 11(I1S4),33(I1S5),22(I2S2)/0,44 + -- PAYLOAD MEMORY: -/44,33,0,22,11 + -- INSTANCE MEMORY: 26(I3),0(I2),13(I1)/- + -- ISTATE: I1:ALIVE, I2:NO_WRITERS, I3: ALIVE + -- WRITER: W2:I1,I3 + + AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + + -- VALIDATE STATE + + Log("R0,R5: DDS Operation TAKE [MAX_SAMPLES 4, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := TAKE; + dds.max_samples := 4; + dds.sstate := ANY_SAMPLE_STATE; + dds.istate := ANY_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + -- READER 0 + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- READER 5 + ind <= 5; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- READER 0 + AlertIf(empty_sample_head(0) /= 44, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: -/44,11,33,22,0 + -- PAYLOAD MEMORY: -/44,33,0,22,11 + -- INSTANCE MEMORY: 26(I3),0(I2),13(I1)/- + -- ISTATE: I1:ALIVE, I2:NO_WRITERS, I3: ALIVE + -- WRITER: W2:I1,I3 + -- READER 5 + AlertIf(empty_sample_head(5) /= 0, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(5) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(5) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: -/0,44,11,33,22 + -- PAYLOAD MEMORY: -/44,33,0,22,11 + -- INSTANCE MEMORY: 26(I3),0(I2),13(I1)/- + -- ISTATE: I1:ALIVE, I2:NO_WRITERS, I3: ALIVE + -- WRITER: W2:I1,I3 + + AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := TRUE; + cc.kind := NOT_ALIVE_DISPOSED; + cc.instance := kh4; + cc.payload := gen_payload(kh4,5); + cc.src_timestamp := gen_duration(30 sec); + + -- TEST: DISPOSE SAMPLE [UNKNOWN INSTANCE] + + Log("R0,R5: RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Instance 4, Writer 1]", INFO); + Log("R0,R5: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 1; + s := to_sample(cc,NOT_ALIVE_DISPOSED_INSTANCE_STATE); + add_sample(s,mem(0), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(5), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + rtps.ret_code := OK; + -- READER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- READER 5 + ind <= 5; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 0 + AlertIf(empty_sample_head(0) /= 11, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 44(I4S1)/11,33,22,0 + -- PAYLOAD MEMORY: -/44,33,0,22,11 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I1)/- + -- ISTATE: I1:ALIVE, I3: ALIVE, I4:DISPOSED + -- WRITER: W1:I4, W2:I1,I3 + -- READER 5 + AlertIf(empty_sample_head(5) /= 44, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(5) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(5) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I4S1)/44,11,33,22 + -- PAYLOAD MEMORY: -/44,33,0,22,11 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I1)/- + -- ISTATE: I1:ALIVE, I3: ALIVE, I4:DISPOSED + -- WRITER: W1:I4, W2:I1,I3 + + AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + + -- VALIDATE STATE + + Log("R0: DDS Operation READ [MAX_SAMPLES 4, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := TAKE; + dds.max_samples := 4; + dds.sstate := ANY_SAMPLE_STATE; + dds.istate := NOT_ALIVE_DISPOSED_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + -- READER 0 + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- READER 5 + ind <= 5; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- READER 0 + AlertIf(empty_sample_head(0) /= 11, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 44(I4S1)/11,33,22,0 + -- PAYLOAD MEMORY: -/44,33,0,22,11 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I1)/- + -- ISTATE: I1:ALIVE, I3: ALIVE, I4:DISPOSED + -- WRITER: W1:I4, W2:I1,I3 + -- READER 5 + AlertIf(empty_sample_head(5) /= 44, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(5) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(5) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I4S1)/44,11,33,22 + -- PAYLOAD MEMORY: -/44,33,0,22,11 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I1)/- + -- ISTATE: I1:ALIVE, I3: ALIVE, I4:DISPOSED + -- WRITER: W1:I4, W2:I1,I3 + + AffirmIf(status_id,(status(0) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(5) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + + Log("*READER 1 / READER 2 / READER 3*", INFO); + -- READER 1 + AlertIf(empty_sample_head(1) /= 0, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(1) /= 0, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(1) /= 0, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: -/0,11,22,33,44 + -- PAYLOAD MEMORY: -/0,11,22,33,44 + -- INSTANCE MEMORY: -/0,13,26 + -- ISTATE: - + -- WRITER: - + -- READER 2 + AlertIf(empty_sample_head(2) /= 0, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(2) /= 0, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(2) /= 0, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: -/0,11,22,33,44 + -- PAYLOAD MEMORY: -/0,11,22,33,44 + -- INSTANCE MEMORY: -/0,13,26 + -- ISTATE: - + -- WRITER: - + -- READER 3 + AlertIf(empty_sample_head(3) /= 0, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(3) /= 0, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(3) /= 0, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: -/0,11,22,33,44 + -- PAYLOAD MEMORY: -/0,11,22,33,44 + -- INSTANCE MEMORY: -/0,13,26 + -- ISTATE: - + -- WRITER: - + + AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh1; + cc.payload := gen_payload(kh1,10); + cc.src_timestamp := gen_duration(1 sec); + + -- TEST: NORMAL ADD_CACHE_CHANGE + -- TEST: SAMPLE WITH ALIGNED PAYLOAD + -- TEST: NORMAL SAMPLE [UNKNOWN INSTANCE] + -- TEST: SAMPLE WITH KEY_HASH + + Log("R1,R2,R3: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Aligned Payload] (ACCEPTED)", INFO); + Log("R1,R2,R3: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 0; + rtps.ret_code := OK; + s := to_sample(cc,ALIVE_INSTANCE_STATE); + add_sample(s,mem(1), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(2), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(3), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + -- READER 1 + ind <= 1; + start_rtps; + wait_on_sig(rtps_done); + -- READER 2 + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + -- READER 3 + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 1 + AlertIf(empty_sample_head(1) /= 11, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(1) /= 11, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(1) /= 13, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I1S1)/11,22,33,44 + -- PAYLOAD MEMORY: 0(I1S1)/11,22,33,44 + -- INSTANCE MEMORY: 0(I1)/13,26 + -- ISTATE: I1:ALIVE + -- WRITER: W0:I1 + -- READER 2 + AlertIf(empty_sample_head(2) /= 11, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(2) /= 11, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(2) /= 13, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I1S1)/11,22,33,44 + -- PAYLOAD MEMORY: 0(I1S1)/11,22,33,44 + -- INSTANCE MEMORY: 0(I1)/13,26 + -- ISTATE: I1:ALIVE + -- WRITER: W0:I1 + -- READER 3 + AlertIf(empty_sample_head(3) /= 11, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(3) /= 11, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(3) /= 13, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I1S1)/11,22,33,44 + -- PAYLOAD MEMORY: 0(I1S1)/11,22,33,44 + -- INSTANCE MEMORY: 0(I1)/13,26 + -- ISTATE: I1:ALIVE + -- WRITER: W0:I1 + + AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := HANDLE_NIL; + cc.payload := gen_payload(kh1,10); + cc.src_timestamp := gen_duration(2 sec); + + -- TEST: SAMPLE WITHOUT KEY_HASH + -- TEST: NORMAL SAMPLE [KNOWN INSTANCE] + + Log("R1,R2,R3: RTPS Operation ADD_CACHE_CHANGE [NO KEY_HASH, Instance 1, Writer 0, Aligned Payload]", INFO); + Log("R1,R2,R3: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 0; + rtps.ret_code := OK; + s := to_sample(cc,ALIVE_INSTANCE_STATE); + s.inst := kh1; + add_sample(s,mem(1), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(2), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(3), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + -- READER 1 + ind <= 1; + start_rtps; + wait_on_sig(rtps_done); + -- READER 2 + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + -- READER 3 + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 1 + AlertIf(empty_sample_head(1) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(1) /= 22, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(1) /= 13, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I1S1),11(I1S2)/22,33,44 + -- PAYLOAD MEMORY: 0(I1S1),11(I1S2)/22,33,44 + -- INSTANCE MEMORY: 0(I1)/13,26 + -- ISTATE: I1:ALIVE + -- WRITER: W0:I1 + -- READER 2 + AlertIf(empty_sample_head(2) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(2) /= 22, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(2) /= 13, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I1S1),11(I1S2)/22,33,44 + -- PAYLOAD MEMORY: 0(I1S1),11(I1S2)/22,33,44 + -- INSTANCE MEMORY: 0(I1)/13,26 + -- ISTATE: I1:ALIVE + -- WRITER: W0:I1 + -- READER 3 + AlertIf(empty_sample_head(3) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(3) /= 22, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(3) /= 13, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I1S1),11(I1S2)/22,33,44 + -- PAYLOAD MEMORY: 0(I1S1),11(I1S2)/22,33,44 + -- INSTANCE MEMORY: 0(I1)/13,26 + -- ISTATE: I1:ALIVE + -- WRITER: W0:I1 + + AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh1; + cc.payload := gen_payload(kh1,18); + cc.src_timestamp := gen_duration(3 sec); + + -- TEST: SAMPLE WITH UNALIGNED PAYLOAD [>1 SLOT] + -- TEST: ADD SAMPLE ON MAX_SAMPLES_PER_INSTANCE + + Log("R1,R2,R3: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Unaligned Payload (2 Slots)]", INFO); + Log("R1,R2,R3: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 0; + rtps.ret_code := OK; + remove_sample(0,mem(1)); + remove_sample(0,mem(2)); + remove_sample(0,mem(3)); + s := to_sample(cc,ALIVE_INSTANCE_STATE); + add_sample(s,mem(1), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(2), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(3), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + -- READER 1 + ind <= 1; + start_rtps; + wait_on_sig(rtps_done); + -- READER 2 + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + -- READER 3 + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 1 + AlertIf(empty_sample_head(1) /= 33, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(1) /= 0, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(1) /= 13, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 11(I1S2),22(I1S3)/33,44,0 + -- PAYLOAD MEMORY: 11(I1S2),22(I1S3),33(I1S3)/0,44 + -- INSTANCE MEMORY: 0(I1)/13,26 + -- ISTATE: I1:ALIVE + -- WRITER: W0:I1 + -- READER 2 + AlertIf(empty_sample_head(2) /= 33, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(2) /= 0, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(2) /= 13, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 11(I1S2),22(I1S3)/33,44,0 + -- PAYLOAD MEMORY: 11(I1S2),22(I1S3),33(I1S3)/0,44 + -- INSTANCE MEMORY: 0(I1)/13,26 + -- ISTATE: I1:ALIVE + -- WRITER: W0:I1 + -- READER 3 + AlertIf(empty_sample_head(3) /= 33, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(3) /= 0, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(3) /= 13, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 11(I1S2),22(I1S3)/33,44,0 + -- PAYLOAD MEMORY: 11(I1S2),22(I1S3),33(I1S3)/0,44 + -- INSTANCE MEMORY: 0(I1)/13,26 + -- ISTATE: I1:ALIVE + -- WRITER: W0:I1 + + AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + + -- VALIDATE STATE + + Log("R1,R2,R3: DDS Operation READ [MAX_SAMPLES 4, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := READ; + dds.max_samples := 4; + dds.sstate := ANY_SAMPLE_STATE; + dds.istate := ANY_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + -- READER 1 + ind <= 1; + start_dds; + wait_on_sig(dds_done); + -- READER 2 + ind <= 2; + start_dds; + wait_on_sig(dds_done); + -- READER 3 + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- READER 1 + AlertIf(empty_sample_head(1) /= 33, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(1) /= 0, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(1) /= 13, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 11(I1S2),22(I1S3)/33,44,0 + -- PAYLOAD MEMORY: 11(I1S2),22(I1S3),33(I1S3)/0,44 + -- INSTANCE MEMORY: 0(I1)/13,26 + -- ISTATE: I1:ALIVE + -- WRITER: W0:I1 + -- READER 2 + AlertIf(empty_sample_head(2) /= 33, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(2) /= 0, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(2) /= 13, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 11(I1S2),22(I1S3)/33,44,0 + -- PAYLOAD MEMORY: 11(I1S2),22(I1S3),33(I1S3)/0,44 + -- INSTANCE MEMORY: 0(I1)/13,26 + -- ISTATE: I1:ALIVE + -- WRITER: W0:I1 + -- READER 3 + AlertIf(empty_sample_head(3) /= 33, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(3) /= 0, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(3) /= 13, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 11(I1S2),22(I1S3)/33,44,0 + -- PAYLOAD MEMORY: 11(I1S2),22(I1S3),33(I1S3)/0,44 + -- INSTANCE MEMORY: 0(I1)/13,26 + -- ISTATE: I1:ALIVE + -- WRITER: W0:I1 + + AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + + Log("R1,R2,R3: DDS Operation TAKE [MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := TAKE; + dds.max_samples := 1; + dds.sstate := ANY_SAMPLE_STATE; + dds.istate := ANY_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + -- READER 1 + ind <= 1; + start_dds; + wait_on_sig(dds_done); + -- READER 2 + ind <= 2; + start_dds; + wait_on_sig(dds_done); + -- READER 3 + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- READER 1 + AlertIf(empty_sample_head(1) /= 33, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(1) /= 11, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(1) /= 13, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 22(I1S3)/33,44,0,11 + -- PAYLOAD MEMORY: 22(I1S3),33(I1S3)/11,0,44 + -- INSTANCE MEMORY: 0(I1)/13,26 + -- ISTATE: I1:ALIVE + -- WRITER: W0:I1 + -- READER 2 + AlertIf(empty_sample_head(2) /= 33, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(2) /= 11, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(2) /= 13, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 22(I1S3)/33,44,0,11 + -- PAYLOAD MEMORY: 22(I1S3),33(I1S3)/11,0,44 + -- INSTANCE MEMORY: 0(I1)/13,26 + -- ISTATE: I1:ALIVE + -- WRITER: W0:I1 + -- READER 3 + AlertIf(empty_sample_head(3) /= 33, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(3) /= 11, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(3) /= 13, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 22(I1S3)/33,44,0,11 + -- PAYLOAD MEMORY: 22(I1S3),33(I1S3)/11,0,44 + -- INSTANCE MEMORY: 0(I1)/13,26 + -- ISTATE: I1:ALIVE + -- WRITER: W0:I1 + + AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := TRUE; + cc.kind := NOT_ALIVE_DISPOSED; + cc.instance := kh1; + cc.payload := gen_payload(kh1,5); + cc.src_timestamp := gen_duration(4 sec); + + -- TEST: DISPOSE SAMPLE [KNOWN INSTANCE] + -- TEST: SAMPLE WITH SERIALIZED KEY [WITH KEY_HASH] + -- TEST: SAMPLE WITH UNALIGNED PAYLOAD [<1 SLOT] + + Log("R1,R2,R3: RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Instance 1, Writer 0]", INFO); + Log("R1,R2,R3: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 0; + rtps.ret_code := OK; + s := to_sample(cc,NOT_ALIVE_DISPOSED_INSTANCE_STATE); + s.inst := kh1; + add_sample(s,mem(1), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(2), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(3), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + -- READER 1 + ind <= 1; + start_rtps; + wait_on_sig(rtps_done); + -- READER 2 + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + -- READER 3 + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 1 + AlertIf(empty_sample_head(1) /= 44, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(1) /= 11, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(1) /= 13, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 22(I1S3),33(I1S4)/44,0,11 + -- PAYLOAD MEMORY: 22(I1S3),33(I1S3)/11,0,44 + -- INSTANCE MEMORY: 0(I1)/13,26 + -- ISTATE: I1:DISPOSED + -- WRITER: W0:I1 + -- READER 2 + AlertIf(empty_sample_head(2) /= 44, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(2) /= 11, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(2) /= 13, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 22(I1S3),33(I1S4)/44,0,11 + -- PAYLOAD MEMORY: 22(I1S3),33(I1S3)/11,0,44 + -- INSTANCE MEMORY: 0(I1)/13,26 + -- ISTATE: I1:DISPOSED + -- WRITER: W0:I1 + -- READER 3 + AlertIf(empty_sample_head(3) /= 44, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(3) /= 11, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(3) /= 13, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 22(I1S3),33(I1S4)/44,0,11 + -- PAYLOAD MEMORY: 22(I1S3),33(I1S3)/11,0,44 + -- INSTANCE MEMORY: 0(I1)/13,26 + -- ISTATE: I1:DISPOSED + -- WRITER: W0:I1 + + AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh2; + cc.payload := gen_payload(kh2,20); + cc.src_timestamp := gen_duration(5 sec); + + Log("R1,R2,R3: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 2, Writer 1, Aligned Payload (2 Slots)]", INFO); + Log("R1,R2,R3: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 1; + rtps.ret_code := OK; + s := to_sample(cc,ALIVE_INSTANCE_STATE); + add_sample(s,mem(1), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(2), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(3), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + -- READER 1 + ind <= 1; + start_rtps; + wait_on_sig(rtps_done); + -- READER 2 + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + -- READER 3 + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 1 + AlertIf(empty_sample_head(1) /= 0, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(1) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(1) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 22(I1S3),33(I1S4),44(I2S1)/0,11 + -- PAYLOAD MEMORY: 22(I1S3),33(I1S3),11(I2S1),0(I2S1)/44 + -- INSTANCE MEMORY: 13(I2),0(I1)/26 + -- ISTATE: I1:DISPOSED, I2:ALIVE + -- WRITER: W0:I1, W1:I2 + -- READER 2 + AlertIf(empty_sample_head(2) /= 0, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(2) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(2) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 22(I1S3),33(I1S4),44(I2S1)/0,11 + -- PAYLOAD MEMORY: 22(I1S3),33(I1S3),11(I2S1),0(I2S1)/44 + -- INSTANCE MEMORY: 13(I2),0(I1)/26 + -- ISTATE: I1:DISPOSED, I2:ALIVE + -- WRITER: W0:I1, W1:I2 + -- READER 3 + AlertIf(empty_sample_head(3) /= 0, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(3) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(3) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 22(I1S3),33(I1S4),44(I2S1)/0,11 + -- PAYLOAD MEMORY: 22(I1S3),33(I1S3),11(I2S1),0(I2S1)/44 + -- INSTANCE MEMORY: 13(I2),0(I1)/26 + -- ISTATE: I1:DISPOSED, I2:ALIVE + -- WRITER: W0:I1, W1:I2 + + AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh3; + cc.payload := gen_payload(kh3,10); + cc.src_timestamp := gen_duration(6 sec); + + -- TEST: TEST SAMPLE WITH SERIALIZED KEY EFFECT ON PAYLOAD MEMORY FULLNESS + + Log("R1,R2,R3: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 3, Writer 1, Aligned Payload]", INFO); + Log("R1,R2,R3: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 1; + s := to_sample(cc,ALIVE_INSTANCE_STATE); + add_sample(s,mem(1), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(2), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(3), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + rtps.ret_code := OK; + -- READER 1 + ind <= 1; + start_rtps; + wait_on_sig(rtps_done); + -- READER 2 + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + -- READER 3 + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 1 + AlertIf(empty_sample_head(1) /= 11, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(1) /= 54, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(1) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 22(I1S3),33(I1S4),44(I2S1),0(I3S1)/11 + -- PAYLOAD MEMORY: 22(I1S3),33(I1S3),11(I2S1),0(I2S1),44(I3S1)/- + -- INSTANCE MEMORY: 26(I3),13(I2),0(I1)/- + -- ISTATE: I1:DISPOSED, I2:ALIVE, I3:ALIVE + -- WRITER: W0:I1, W1:I2,I3 + -- READER 2 + AlertIf(empty_sample_head(2) /= 11, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(2) /= 54, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(2) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 22(I1S3),33(I1S4),44(I2S1),0(I3S1)/11 + -- PAYLOAD MEMORY: 22(I1S3),33(I1S3),11(I2S1),0(I2S1),44(I3S1)/- + -- INSTANCE MEMORY: 26(I3),13(I2),0(I1)/- + -- ISTATE: I1:DISPOSED, I2:ALIVE, I3:ALIVE + -- WRITER: W0:I1, W1:I2,I3 + -- READER 3 + AlertIf(empty_sample_head(3) /= 11, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(3) /= 54, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(3) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 22(I1S3),33(I1S4),44(I2S1),0(I3S1)/11 + -- PAYLOAD MEMORY: 22(I1S3),33(I1S3),11(I2S1),0(I2S1),44(I3S1)/- + -- INSTANCE MEMORY: 26(I3),13(I2),0(I1)/- + -- ISTATE: I1:DISPOSED, I2:ALIVE, I3:ALIVE + -- WRITER: W0:I1, W1:I2,I3 + + AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + + -- TEST: REMOVE_WRITER [UNKNOWN WRITER] + + Log("R1,R2,R3: RTPS Operation REMOVE_WRITER [Writer 2]", INFO); + Log("R1,R2,R3: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := REMOVE_WRITER; + rtps.writer_pos := 2; + rtps.ret_code := OK; + -- READER 1 + ind <= 1; + start_rtps; + wait_on_sig(rtps_done); + -- READER 2 + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + -- READER 3 + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 1 + AlertIf(empty_sample_head(1) /= 11, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(1) /= 54, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(1) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 22(I1S3),33(I1S4),44(I2S1),0(I3S1)/11 + -- PAYLOAD MEMORY: 22(I1S3),33(I1S3),11(I2S1),0(I2S1),44(I3S1)/- + -- INSTANCE MEMORY: 26(I3),13(I2),0(I1)/- + -- ISTATE: I1:DISPOSED, I2:ALIVE, I3:ALIVE + -- WRITER: W0:I1, W1:I2,I3 + -- READER 2 + AlertIf(empty_sample_head(2) /= 11, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(2) /= 54, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(2) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 22(I1S3),33(I1S4),44(I2S1),0(I3S1)/11 + -- PAYLOAD MEMORY: 22(I1S3),33(I1S3),11(I2S1),0(I2S1),44(I3S1)/- + -- INSTANCE MEMORY: 26(I3),13(I2),0(I1)/- + -- ISTATE: I1:DISPOSED, I2:ALIVE, I3:ALIVE + -- WRITER: W0:I1, W1:I2,I3 + -- READER 3 + AlertIf(empty_sample_head(3) /= 11, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(3) /= 54, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(3) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 22(I1S3),33(I1S4),44(I2S1),0(I3S1)/11 + -- PAYLOAD MEMORY: 22(I1S3),33(I1S3),11(I2S1),0(I2S1),44(I3S1)/- + -- INSTANCE MEMORY: 26(I3),13(I2),0(I1)/- + -- ISTATE: I1:DISPOSED, I2:ALIVE, I3:ALIVE + -- WRITER: W0:I1, W1:I2,I3 + + AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + + Log("R1,R2,R3: DDS Operation TAKE [MAX_SAMPLES 1, NOT_READ_SAMPLE_STATE, NOT_ALIVE_DISPOSED_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := TAKE; + dds.max_samples := 1; + dds.sstate := NOT_READ_SAMPLE_STATE; + dds.istate := NOT_ALIVE_DISPOSED_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + -- READER 1 + ind <= 1; + start_dds; + wait_on_sig(dds_done); + -- READER 2 + ind <= 2; + start_dds; + wait_on_sig(dds_done); + -- READER 3 + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- READER 1 + AlertIf(empty_sample_head(1) /= 11, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(1) /= 54, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(1) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 22(I1S3),44(I2S1),0(I3S1)/11,33 + -- PAYLOAD MEMORY: 22(I1S3),33(I1S3),11(I2S1),0(I2S1),44(I3S1)/- + -- INSTANCE MEMORY: 26(I3),13(I2),0(I1)/- + -- ISTATE: I1:DISPOSED, I2:ALIVE, I3:ALIVE + -- WRITER: W0:I1, W1:I2,I3 + -- READER 2 + AlertIf(empty_sample_head(2) /= 11, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(2) /= 54, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(2) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 22(I1S3),44(I2S1),0(I3S1)/11,33 + -- PAYLOAD MEMORY: 22(I1S3),33(I1S3),11(I2S1),0(I2S1),44(I3S1)/- + -- INSTANCE MEMORY: 26(I3),13(I2),0(I1)/- + -- ISTATE: I1:DISPOSED, I2:ALIVE, I3:ALIVE + -- WRITER: W0:I1, W1:I2,I3 + -- READER 3 + AlertIf(empty_sample_head(3) /= 11, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(3) /= 54, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(3) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 22(I1S3),44(I2S1),0(I3S1)/11,33 + -- PAYLOAD MEMORY: 22(I1S3),33(I1S3),11(I2S1),0(I2S1),44(I3S1)/- + -- INSTANCE MEMORY: 26(I3),13(I2),0(I1)/- + -- ISTATE: I1:DISPOSED, I2:ALIVE, I3:ALIVE + -- WRITER: W0:I1, W1:I2,I3 + + AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh3; + cc.payload := gen_payload(kh3,10); + cc.src_timestamp := gen_duration(7 sec); + + -- TEST: ADD_CACHE_CHANGE ON PAYLOAD MEMORY FULL + + Log("R1,R2,R3: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 3, Writer 2, Aligned Payload]", INFO); + Log("R1,R2,R3: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 2; + remove_sample(0,mem(1)); + remove_sample(0,mem(2)); + remove_sample(0,mem(3)); + s := to_sample(cc,ALIVE_INSTANCE_STATE); + add_sample(s,mem(1), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(2), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(3), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + rtps.ret_code := OK; + -- READER 1 + ind <= 1; + start_rtps; + wait_on_sig(rtps_done); + -- READER 2 + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + -- READER 3 + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 1 + AlertIf(empty_sample_head(1) /= 33, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(1) /= 33, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(1) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 44(I2S1),0(I3S1),11(I3S2)/33,22 + -- PAYLOAD MEMORY: 11(I2S1),0(I2S1),44(I3S1),22(I3S2)/33 + -- INSTANCE MEMORY: 26(I3),13(I2),0(I1)/- + -- ISTATE: I1:DISPOSED, I2:ALIVE, I3:ALIVE + -- WRITER: W0:I1, W1:I2,I3, W2:I3 + -- READER 2 + AlertIf(empty_sample_head(2) /= 33, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(2) /= 33, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(2) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 44(I2S1),0(I3S1),11(I3S2)/33,22 + -- PAYLOAD MEMORY: 11(I2S1),0(I2S1),44(I3S1),22(I3S2)/33 + -- INSTANCE MEMORY: 26(I3),13(I2),0(I1)/- + -- ISTATE: I1:DISPOSED, I2:ALIVE, I3:ALIVE + -- WRITER: W0:I1, W1:I2,I3, W2:I3 + -- READER 3 + AlertIf(empty_sample_head(3) /= 33, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(3) /= 33, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(3) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 44(I2S1),0(I3S1),11(I3S2)/33,22 + -- PAYLOAD MEMORY: 11(I2S1),0(I2S1),44(I3S1),22(I3S2)/33 + -- INSTANCE MEMORY: 26(I3),13(I2),0(I1)/- + -- ISTATE: I1:DISPOSED, I2:ALIVE, I3:ALIVE + -- WRITER: W0:I1, W1:I2,I3, W2:I3 + + AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh4; + cc.payload := gen_payload(kh4,10); + cc.src_timestamp := gen_duration(8 sec); + + -- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKOWN INSTANCE, WITHOUT STALE INSTANCE, WITH EMPTY INSTANCE] + + Log("R1,R2,R3: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 4, Writer 1, Aligned Payload]", INFO); + Log("R1,R2,R3: REJECTED [MAX_INSTANCES exceeded]", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 1; + rtps.ret_code := REJECTED; + -- READER 1 + ind <= 1; + start_rtps; + wait_on_sig(rtps_done); + -- READER 2 + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + -- READER 3 + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 1 + AlertIf(empty_sample_head(1) /= 33, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(1) /= 33, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(1) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 44(I2S1),0(I3S1),11(I3S2)/33,22 + -- PAYLOAD MEMORY: 11(I2S1),0(I2S1),44(I3S1),22(I3S2)/33 + -- INSTANCE MEMORY: 26(I3),13(I2),0(I1)/- + -- ISTATE: I1:DISPOSED, I2:ALIVE, I3:ALIVE + -- WRITER: W0:I1, W1:I2,I3, W2:I3 + -- READER 2 + AlertIf(empty_sample_head(2) /= 33, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(2) /= 33, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(2) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 44(I2S1),0(I3S1),11(I3S2)/33,22 + -- PAYLOAD MEMORY: 11(I2S1),0(I2S1),44(I3S1),22(I3S2)/33 + -- INSTANCE MEMORY: 26(I3),13(I2),0(I1)/- + -- ISTATE: I1:DISPOSED, I2:ALIVE, I3:ALIVE + -- WRITER: W0:I1, W1:I2,I3, W2:I3 + -- READER 3 + AlertIf(empty_sample_head(3) /= 33, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(3) /= 33, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(3) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 44(I2S1),0(I3S1),11(I3S2)/33,22 + -- PAYLOAD MEMORY: 11(I2S1),0(I2S1),44(I3S1),22(I3S2)/33 + -- INSTANCE MEMORY: 26(I3),13(I2),0(I1)/- + -- ISTATE: I1:DISPOSED, I2:ALIVE, I3:ALIVE + -- WRITER: W0:I1, W1:I2,I3, W2:I3 + + AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + + -- TEST: REMOVE_WRITER [KNOWN WRITER (1 Instance)] + + Log("R1,R2,R3: RTPS Operation REMOVE_WRITER [Writer 0]", INFO); + Log("R1,R2,R3: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := REMOVE_WRITER; + rtps.writer_pos := 0; + change_istate(kh1, NOT_ALIVE_NO_WRITERS_INSTANCE_STATE, mem(1)); + change_istate(kh1, NOT_ALIVE_NO_WRITERS_INSTANCE_STATE, mem(2)); + change_istate(kh1, NOT_ALIVE_NO_WRITERS_INSTANCE_STATE, mem(3)); + rtps.ret_code := OK; + -- READER 1 + ind <= 1; + start_rtps; + wait_on_sig(rtps_done); + -- READER 2 + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + -- READER 3 + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 1 + AlertIf(empty_sample_head(1) /= 33, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(1) /= 33, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(1) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 44(I2S1),0(I3S1),11(I3S2)/33,22 + -- PAYLOAD MEMORY: 11(I2S1),0(I2S1),44(I3S1),22(I3S2)/33 + -- INSTANCE MEMORY: 26(I3),13(I2),0(I1)/- + -- ISTATE: I1:DISPOSED, I2:ALIVE, I3:ALIVE + -- WRITER: W1:I2,I3, W2:I3 + -- READER 2 + AlertIf(empty_sample_head(2) /= 33, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(2) /= 33, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(2) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 44(I2S1),0(I3S1),11(I3S2)/33,22 + -- PAYLOAD MEMORY: 11(I2S1),0(I2S1),44(I3S1),22(I3S2)/33 + -- INSTANCE MEMORY: 26(I3),13(I2),0(I1)/- + -- ISTATE: I1:DISPOSED, I2:ALIVE, I3:ALIVE + -- WRITER: W1:I2,I3, W2:I3 + -- READER 3 + AlertIf(empty_sample_head(3) /= 33, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(3) /= 33, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(3) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 44(I2S1),0(I3S1),11(I3S2)/33,22 + -- PAYLOAD MEMORY: 11(I2S1),0(I2S1),44(I3S1),22(I3S2)/33 + -- INSTANCE MEMORY: 26(I3),13(I2),0(I1)/- + -- ISTATE: I1:DISPOSED, I2:ALIVE, I3:ALIVE + -- WRITER: W1:I2,I3, W2:I3 + + AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + + -- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKOWN INSTANCE, WITH STALE INSTANCE] + + Log("R1,R2,R3: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 4, Writer 1, Aligned Payload]", INFO); + Log("R1,R2,R3: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 1; + remove_inst(kh1, mem(1)); + remove_inst(kh1, mem(2)); + remove_inst(kh1, mem(3)); + s := to_sample(cc,ALIVE_INSTANCE_STATE); + add_sample(s,mem(1), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(2), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(3), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + rtps.ret_code := OK; + -- READER 1 + ind <= 1; + start_rtps; + wait_on_sig(rtps_done); + -- READER 2 + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + -- READER 3 + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 1 + AlertIf(empty_sample_head(1) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(1) /= 54, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(1) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 44(I2S1),0(I3S1),11(I3S2),33(I4S1)/22 + -- PAYLOAD MEMORY: 11(I2S1),0(I2S1),44(I3S1),22(I3S2),33(I4S1)/- + -- INSTANCE MEMORY: 26(I3),0(I4),13(I2)/- + -- ISTATE: I2:ALIVE, I3:ALIVE, I4:ALIVE + -- WRITER: W1:I2,I3,I4, W2:I3 + -- READER 2 + AlertIf(empty_sample_head(2) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(2) /= 54, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(2) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 44(I2S1),0(I3S1),11(I3S2),33(I4S1)/22 + -- PAYLOAD MEMORY: 11(I2S1),0(I2S1),44(I3S1),22(I3S2),33(I4S1)/- + -- INSTANCE MEMORY: 26(I3),0(I4),13(I2)/- + -- ISTATE: I2:ALIVE, I3:ALIVE, I4:ALIVE + -- WRITER: W1:I2,I3,I4, W2:I3 + -- READER 3 + AlertIf(empty_sample_head(3) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(3) /= 54, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(3) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 44(I2S1),0(I3S1),11(I3S2),33(I4S1)/22 + -- PAYLOAD MEMORY: 11(I2S1),0(I2S1),44(I3S1),22(I3S2),33(I4S1)/- + -- INSTANCE MEMORY: 26(I3),0(I4),13(I2)/- + -- ISTATE: I2:ALIVE, I3:ALIVE, I4:ALIVE + -- WRITER: W1:I2,I3,I4, W2:I3 + + AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + + -- VALIDATE STATE + + Log("R1,R2,R3: DDS Operation READ [MAX_SAMPLES 4, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := READ; + dds.max_samples := 4; + dds.sstate := ANY_SAMPLE_STATE; + dds.istate := ANY_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + -- READER 1 + ind <= 1; + start_dds; + wait_on_sig(dds_done); + -- READER 2 + ind <= 2; + start_dds; + wait_on_sig(dds_done); + -- READER 3 + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- READER 1 + AlertIf(empty_sample_head(1) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(1) /= 54, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(1) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 44(I2S1),0(I3S1),11(I3S2),33(I4S1)/22 + -- PAYLOAD MEMORY: 11(I2S1),0(I2S1),44(I3S1),22(I3S2),33(I4S1)/- + -- INSTANCE MEMORY: 26(I3),0(I4),13(I2)/- + -- ISTATE: I2:ALIVE, I3:ALIVE, I4:ALIVE + -- WRITER: W1:I2,I3,I4, W2:I3 + -- READER 2 + AlertIf(empty_sample_head(2) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(2) /= 54, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(2) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 44(I2S1),0(I3S1),11(I3S2),33(I4S1)/22 + -- PAYLOAD MEMORY: 11(I2S1),0(I2S1),44(I3S1),22(I3S2),33(I4S1)/- + -- INSTANCE MEMORY: 26(I3),0(I4),13(I2)/- + -- ISTATE: I2:ALIVE, I3:ALIVE, I4:ALIVE + -- WRITER: W1:I2,I3,I4, W2:I3 + -- READER 3 + AlertIf(empty_sample_head(3) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(3) /= 54, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(3) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 44(I2S1),0(I3S1),11(I3S2),33(I4S1)/22 + -- PAYLOAD MEMORY: 11(I2S1),0(I2S1),44(I3S1),22(I3S2),33(I4S1)/- + -- INSTANCE MEMORY: 26(I3),0(I4),13(I2)/- + -- ISTATE: I2:ALIVE, I3:ALIVE, I4:ALIVE + -- WRITER: W1:I2,I3,I4, W2:I3 + + AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + + Log("R1,R2,R3: DDS Operation TAKE [MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := TAKE; + dds.max_samples := 1; + dds.sstate := ANY_SAMPLE_STATE; + dds.istate := ANY_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + -- READER 1 + ind <= 1; + start_dds; + wait_on_sig(dds_done); + -- READER 2 + ind <= 2; + start_dds; + wait_on_sig(dds_done); + -- READER 3 + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- READER 1 + AlertIf(empty_sample_head(1) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(1) /= 11, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(1) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I3S1),11(I3S2),33(I4S1)/22,44 + -- PAYLOAD MEMORY: 44(I3S1),22(I3S2),33(I4S1)/11,0 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I2)/- + -- ISTATE: I2:ALIVE, I3:ALIVE, I4:ALIVE + -- WRITER: W1:I2,I3,I4, W2:I3 + -- READER 2 + AlertIf(empty_sample_head(2) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(2) /= 11, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(2) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I3S1),11(I3S2),33(I4S1)/22,44 + -- PAYLOAD MEMORY: 44(I3S1),22(I3S2),33(I4S1)/11,0 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I2)/- + -- ISTATE: I2:ALIVE, I3:ALIVE, I4:ALIVE + -- WRITER: W1:I2,I3,I4, W2:I3 + -- READER 3 + AlertIf(empty_sample_head(3) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(3) /= 11, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(3) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I3S1),11(I3S2),33(I4S1)/22,44 + -- PAYLOAD MEMORY: 44(I3S1),22(I3S2),33(I4S1)/11,0 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I2)/- + -- ISTATE: I2:ALIVE, I3:ALIVE, I4:ALIVE + -- WRITER: W1:I2,I3,I4, W2:I3 + + AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh1; + cc.payload := gen_payload(kh1,10); + cc.src_timestamp := gen_duration(9 sec); + + -- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKOWN INSTANCE, WITHOUT STALE INSTANCE] + + Log("R1,R2,R3: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Aligned Payload]", INFO); + Log("R1,R2,R3: REJECTED [MAX_INSTANCES exceeded]", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 0; + rtps.ret_code := REJECTED; + -- READER 1 + ind <= 1; + start_rtps; + wait_on_sig(rtps_done); + -- READER 2 + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + -- READER 3 + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 1 + AlertIf(empty_sample_head(1) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(1) /= 11, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(1) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I3S1),11(I3S2),33(I4S1)/22,44 + -- PAYLOAD MEMORY: 44(I3S1),22(I3S2),33(I4S1)/11,0 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I2)/- + -- ISTATE: I2:ALIVE, I3:ALIVE, I4:ALIVE + -- WRITER: W1:I2,I3,I4, W2:I3 + -- READER 2 + AlertIf(empty_sample_head(2) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(2) /= 11, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(2) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I3S1),11(I3S2),33(I4S1)/22,44 + -- PAYLOAD MEMORY: 44(I3S1),22(I3S2),33(I4S1)/11,0 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I2)/- + -- ISTATE: I2:ALIVE, I3:ALIVE, I4:ALIVE + -- WRITER: W1:I2,I3,I4, W2:I3 + -- READER 3 + AlertIf(empty_sample_head(3) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(3) /= 11, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(3) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I3S1),11(I3S2),33(I4S1)/22,44 + -- PAYLOAD MEMORY: 44(I3S1),22(I3S2),33(I4S1)/11,0 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I2)/- + -- ISTATE: I2:ALIVE, I3:ALIVE, I4:ALIVE + -- WRITER: W1:I2,I3,I4, W2:I3 + + AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh4; + cc.payload := gen_payload(kh4,10); + cc.src_timestamp := gen_duration(10 sec); + + Log("R1,R2,R3: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 4, Writer 1, Aligned Payload]", INFO); + Log("R1,R2,R3: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 1; + s := to_sample(cc,ALIVE_INSTANCE_STATE); + add_sample(s,mem(1), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(2), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(3), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + rtps.ret_code := OK; + -- READER 1 + ind <= 1; + start_rtps; + wait_on_sig(rtps_done); + -- READER 2 + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + -- READER 3 + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 1 + AlertIf(empty_sample_head(1) /= 44, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(1) /= 0, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(1) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I3S1),11(I3S2),33(I4S1),22(I4S2)/44 + -- PAYLOAD MEMORY: 44(I3S1),22(I3S2),33(I4S1),11(I4S2)/0 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I2)/- + -- ISTATE: I2:ALIVE, I3:ALIVE, I4:ALIVE + -- WRITER: W1:I2,I3,I4, W2:I3 + -- READER 2 + AlertIf(empty_sample_head(2) /= 44, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(2) /= 0, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(2) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I3S1),11(I3S2),33(I4S1),22(I4S2)/44 + -- PAYLOAD MEMORY: 44(I3S1),22(I3S2),33(I4S1),11(I4S2)/0 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I2)/- + -- ISTATE: I2:ALIVE, I3:ALIVE, I4:ALIVE + -- WRITER: W1:I2,I3,I4, W2:I3 + -- READER 3 + AlertIf(empty_sample_head(3) /= 44, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(3) /= 0, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(3) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I3S1),11(I3S2),33(I4S1),22(I4S2)/44 + -- PAYLOAD MEMORY: 44(I3S1),22(I3S2),33(I4S1),11(I4S2)/0 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I2)/- + -- ISTATE: I2:ALIVE, I3:ALIVE, I4:ALIVE + -- WRITER: W1:I2,I3,I4, W2:I3 + + AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh1; + cc.payload := gen_payload(kh1,10); + cc.src_timestamp := gen_duration(11 sec); + + -- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE, WITHOUT STALE INSTANCE] + + Log("R1,R2,R3: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Aligned Payload]", INFO); + Log("R1,R2,R3: REJECTED [MAX_INSTANCES exceeded]", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 0; + rtps.ret_code := REJECTED; + -- READER 1 + ind <= 1; + start_rtps; + wait_on_sig(rtps_done); + -- READER 2 + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + -- READER 3 + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 1 + AlertIf(empty_sample_head(1) /= 44, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(1) /= 0, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(1) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I3S1),11(I3S2),33(I4S1),22(I4S2)/44 + -- PAYLOAD MEMORY: 44(I3S1),22(I3S2),33(I4S1),11(I4S2)/0 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I2)/- + -- ISTATE: I2:ALIVE, I3:ALIVE, I4:ALIVE + -- WRITER: W1:I2,I3,I4, W2:I3 + -- READER 2 + AlertIf(empty_sample_head(2) /= 44, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(2) /= 0, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(2) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I3S1),11(I3S2),33(I4S1),22(I4S2)/44 + -- PAYLOAD MEMORY: 44(I3S1),22(I3S2),33(I4S1),11(I4S2)/0 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I2)/- + -- ISTATE: I2:ALIVE, I3:ALIVE, I4:ALIVE + -- WRITER: W1:I2,I3,I4, W2:I3 + -- READER 3 + AlertIf(empty_sample_head(3) /= 44, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(3) /= 0, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(3) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I3S1),11(I3S2),33(I4S1),22(I4S2)/44 + -- PAYLOAD MEMORY: 44(I3S1),22(I3S2),33(I4S1),11(I4S2)/0 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I2)/- + -- ISTATE: I2:ALIVE, I3:ALIVE, I4:ALIVE + -- WRITER: W1:I2,I3,I4, W2:I3 + + AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + + Log("R1,R2,R3: DDS Operation READ [MAX_SAMPLES 4, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := READ; + dds.max_samples := 4; + dds.sstate := ANY_SAMPLE_STATE; + dds.istate := ANY_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + -- READER 1 + ind <= 1; + start_dds; + wait_on_sig(dds_done); + -- READER 2 + ind <= 2; + start_dds; + wait_on_sig(dds_done); + -- READER 3 + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- READER 1 + AlertIf(empty_sample_head(1) /= 44, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(1) /= 0, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(1) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I3S1),11(I3S2),33(I4S1),22(I4S2)/44 + -- PAYLOAD MEMORY: 44(I3S1),22(I3S2),33(I4S1),11(I4S2)/0 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I2)/- + -- ISTATE: I2:ALIVE, I3:ALIVE, I4:ALIVE + -- WRITER: W1:I2,I3,I4, W2:I3 + -- READER 2 + AlertIf(empty_sample_head(2) /= 44, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(2) /= 0, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(2) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I3S1),11(I3S2),33(I4S1),22(I4S2)/44 + -- PAYLOAD MEMORY: 44(I3S1),22(I3S2),33(I4S1),11(I4S2)/0 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I2)/- + -- ISTATE: I2:ALIVE, I3:ALIVE, I4:ALIVE + -- WRITER: W1:I2,I3,I4, W2:I3 + -- READER 3 + AlertIf(empty_sample_head(3) /= 44, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(3) /= 0, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(3) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I3S1),11(I3S2),33(I4S1),22(I4S2)/44 + -- PAYLOAD MEMORY: 44(I3S1),22(I3S2),33(I4S1),11(I4S2)/0 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I2)/- + -- ISTATE: I2:ALIVE, I3:ALIVE, I4:ALIVE + -- WRITER: W1:I2,I3,I4, W2:I3 + + AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + + -- TEST: REMOVE_WRITER [KNOWN WRITER (>1 Instances)] + -- TEST: REMOVE_WRITER [NOT_ALIVE_NO_WRITERS Transition] + -- TEST: REMOVE_WRITER ON MAX_SAMPLES [NOT_ALIVE_NO_WRITERS Transition] + -- TEST: REMOVE_WRITER ON MAX_SAMPLES_PER_INSTANCE [NOT_ALIVE_NO_WRITERS Transition] + -- TEST: REMOVE_WRITER [Multiple Pending NOT_ALIVE_NO_WRITERS Transitions] + + Log("R1,R2,R3: RTPS Operation REMOVE_WRITER [Writer 1]", INFO); + Log("R1,R2,R3: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := REMOVE_WRITER; + rtps.writer_pos := 1; + remove_sample(0,mem(1)); + remove_sample(0,mem(2)); + remove_sample(0,mem(3)); + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := TRUE; + cc.kind := NOT_ALIVE_UNREGISTERED; + cc.instance := kh2; + cc.src_timestamp := check_time; + s := to_sample(cc,NOT_ALIVE_NO_WRITERS_INSTANCE_STATE); + add_sample(s,mem(1), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(2), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(3), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + remove_sample(1,mem(1)); + remove_sample(1,mem(2)); + remove_sample(1,mem(3)); + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := TRUE; + cc.kind := NOT_ALIVE_UNREGISTERED; + cc.instance := kh4; + cc.src_timestamp := check_time; + s := to_sample(cc,NOT_ALIVE_NO_WRITERS_INSTANCE_STATE); + add_sample(s,mem(1), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(2), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(3), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + rtps.ret_code := OK; + -- READER 1 + ind <= 1; + start_rtps; + wait_on_sig(rtps_done); + -- READER 2 + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + -- READER 3 + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 1 + AlertIf(empty_sample_head(1) /= 0, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(1) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(1) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 11(I3S2),22(I4S2),44(I4S3),33(I2S2)/0 + -- PAYLOAD MEMORY: 22(I3S2),11(I4S2)/44,33,0 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I2)/- + -- ISTATE: I2:NO_WRITERS, I3:ALIVE, I4:NO_WRITERS + -- WRITER: W2:I3 + -- READER 2 + AlertIf(empty_sample_head(2) /= 0, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(2) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(2) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 11(I3S2),22(I4S2),44(I4S3),33(I2S2)/0 + -- PAYLOAD MEMORY: 22(I3S2),11(I4S2)/44,33,0 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I2)/- + -- ISTATE: I2:NO_WRITERS, I3:ALIVE, I4:NO_WRITERS + -- WRITER: W2:I3 + -- READER 3 + AlertIf(empty_sample_head(3) /= 0, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(3) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(3) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 11(I3S2),22(I4S2),44(I4S3),33(I2S2)/0 + -- PAYLOAD MEMORY: 22(I3S2),11(I4S2)/44,33,0 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I2)/- + -- ISTATE: I2:NO_WRITERS, I3:ALIVE, I4:NO_WRITERS + -- WRITER: W2:I3 + + AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + + Log("R1,R2,R3: DDS Operation TAKE_INSTANCE [Instance 2, MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := TAKE_INSTANCE; + dds.max_samples := 1; + dds.sstate := ANY_SAMPLE_STATE; + dds.istate := ANY_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + dds.inst := kh2; + -- READER 1 + ind <= 1; + start_dds; + wait_on_sig(dds_done); + -- READER 2 + ind <= 2; + start_dds; + wait_on_sig(dds_done); + -- READER 3 + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- READER 1 + AlertIf(empty_sample_head(1) /= 0, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(1) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(1) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 11(I3S2),22(I4S2),44(I4S3)/0,33 + -- PAYLOAD MEMORY: 22(I3S2),11(I4S2)/44,33,0 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I2)/- + -- ISTATE: I2:NO_WRITERS, I3:ALIVE, I4:NO_WRITERS + -- WRITER: W2:I3 + -- READER 2 + AlertIf(empty_sample_head(2) /= 0, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(2) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(2) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 11(I3S2),22(I4S2),44(I4S3)/0,33 + -- PAYLOAD MEMORY: 22(I3S2),11(I4S2)/44,33,0 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I2)/- + -- ISTATE: I2:NO_WRITERS, I3:ALIVE, I4:NO_WRITERS + -- WRITER: W2:I3 + -- READER 3 + AlertIf(empty_sample_head(3) /= 0, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(3) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(3) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 11(I3S2),22(I4S2),44(I4S3)/0,33 + -- PAYLOAD MEMORY: 22(I3S2),11(I4S2)/44,33,0 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I2)/- + -- ISTATE: I2:NO_WRITERS, I3:ALIVE, I4:NO_WRITERS + -- WRITER: W2:I3 + + AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh3; + cc.payload := gen_payload(kh3,10); + cc.src_timestamp := gen_duration(12 sec); + + Log("R1,R2,R3: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 3, Writer 2, Aligned Payload]", INFO); + Log("R1,R2,R3: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 2; + s := to_sample(cc,ALIVE_INSTANCE_STATE); + add_sample(s,mem(1), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(2), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(3), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + rtps.ret_code := OK; + -- READER 1 + ind <= 1; + start_rtps; + wait_on_sig(rtps_done); + -- READER 2 + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + -- READER 3 + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 1 + AlertIf(empty_sample_head(1) /= 33, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(1) /= 33, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(1) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 11(I3S2),22(I4S2),44(I4S3),0(I3S3)/33 + -- PAYLOAD MEMORY: 22(I3S2),11(I4S2),44(I3S3)/33,0 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I2)/- + -- ISTATE: I2:NO_WRITERS, I3:ALIVE, I4:NO_WRITERS + -- WRITER: W2:I3 + -- READER 2 + AlertIf(empty_sample_head(2) /= 33, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(2) /= 33, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(2) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 11(I3S2),22(I4S2),44(I4S3),0(I3S3)/33 + -- PAYLOAD MEMORY: 22(I3S2),11(I4S2),44(I3S3)/33,0 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I2)/- + -- ISTATE: I2:NO_WRITERS, I3:ALIVE, I4:NO_WRITERS + -- WRITER: W2:I3 + -- READER 3 + AlertIf(empty_sample_head(3) /= 33, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(3) /= 33, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(3) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 11(I3S2),22(I4S2),44(I4S3),0(I3S3)/33 + -- PAYLOAD MEMORY: 22(I3S2),11(I4S2),44(I3S3)/33,0 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I2)/- + -- ISTATE: I2:NO_WRITERS, I3:ALIVE, I4:NO_WRITERS + -- WRITER: W2:I3 + + AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + + Log("R1,R2,R3: DDS Operation READ [MAX_SAMPLES 4, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := READ; + dds.max_samples := 4; + dds.sstate := ANY_SAMPLE_STATE; + dds.istate := ANY_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + -- READER 1 + ind <= 1; + start_dds; + wait_on_sig(dds_done); + -- READER 2 + ind <= 2; + start_dds; + wait_on_sig(dds_done); + -- READER 3 + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- READER 1 + AlertIf(empty_sample_head(1) /= 33, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(1) /= 33, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(1) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 11(I3S2),22(I4S2),44(I4S3),0(I3S3)/33 + -- PAYLOAD MEMORY: 22(I3S2),11(I4S2),44(I3S3)/33,0 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I2)/- + -- ISTATE: I2:NO_WRITERS, I3:ALIVE, I4:NO_WRITERS + -- WRITER: W2:I3 + -- READER 2 + AlertIf(empty_sample_head(2) /= 33, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(2) /= 33, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(2) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 11(I3S2),22(I4S2),44(I4S3),0(I3S3)/33 + -- PAYLOAD MEMORY: 22(I3S2),11(I4S2),44(I3S3)/33,0 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I2)/- + -- ISTATE: I2:NO_WRITERS, I3:ALIVE, I4:NO_WRITERS + -- WRITER: W2:I3 + -- READER 3 + AlertIf(empty_sample_head(3) /= 33, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(3) /= 33, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(3) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 11(I3S2),22(I4S2),44(I4S3),0(I3S3)/33 + -- PAYLOAD MEMORY: 22(I3S2),11(I4S2),44(I3S3)/33,0 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I2)/- + -- ISTATE: I2:NO_WRITERS, I3:ALIVE, I4:NO_WRITERS + -- WRITER: W2:I3 + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh1; + cc.payload := gen_payload(kh1,10); + cc.src_timestamp := gen_duration(13 sec); + + -- TEST: ADD SAMPLE ON MAX_SAMPLES [UNKNOWN INSTANCE] + -- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE, WITH STALE INSTANCE] + + Log("R1,R2,R3: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Aligned Payload]", INFO); + Log("R1,R2,R3: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 0; + remove_inst(kh2,mem(1)); + remove_inst(kh2,mem(2)); + remove_inst(kh2,mem(3)); + remove_sample(0,mem(1)); + remove_sample(0,mem(2)); + remove_sample(0,mem(3)); + s := to_sample(cc,ALIVE_INSTANCE_STATE); + add_sample(s,mem(1), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(2), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(3), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + rtps.ret_code := OK; + -- READER 1 + ind <= 1; + start_rtps; + wait_on_sig(rtps_done); + -- READER 2 + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + -- READER 3 + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 1 + AlertIf(empty_sample_head(1) /= 11, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(1) /= 22, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(1) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 22(I4S2),44(I4S3),0(I3S3),33(I1S1)/11 + -- PAYLOAD MEMORY: 11(I4S2),44(I3S3),33(I1S1)/22,0 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I1)/- + -- ISTATE: I1:ALIVE, I3:ALIVE, I4:NO_WRITERS + -- WRITER: W0:I1, W2:I3 + -- READER 2 + AlertIf(empty_sample_head(2) /= 11, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(2) /= 22, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(2) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 22(I4S2),44(I4S3),0(I3S3),33(I1S1)/11 + -- PAYLOAD MEMORY: 11(I4S2),44(I3S3),33(I1S1)/22,0 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I1)/- + -- ISTATE: I1:ALIVE, I3:ALIVE, I4:NO_WRITERS + -- WRITER: W0:I1, W2:I3 + -- READER 3 + AlertIf(empty_sample_head(3) /= 11, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(3) /= 22, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(3) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 22(I4S2),44(I4S3),0(I3S3),33(I1S1)/11 + -- PAYLOAD MEMORY: 11(I4S2),44(I3S3),33(I1S1)/22,0 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I1)/- + -- ISTATE: I1:ALIVE, I3:ALIVE, I4:NO_WRITERS + -- WRITER: W0:I1, W2:I3 + + AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh3; + cc.payload := gen_payload(kh3,10); + cc.src_timestamp := gen_duration(14 sec); + + -- TEST: ADD SAMPLE ON MAX_SAMPLES [KNOWN INSTANCE] + + Log("R1,R2,R3: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 3, Writer 2, Aligned Payload]", INFO); + Log("R1,R2,R3: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 2; + remove_sample(0,mem(1)); + remove_sample(0,mem(2)); + remove_sample(0,mem(3)); + s := to_sample(cc,ALIVE_INSTANCE_STATE); + add_sample(s,mem(1), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(2), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(3), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + rtps.ret_code := OK; + -- READER 1 + ind <= 1; + start_rtps; + wait_on_sig(rtps_done); + -- READER 2 + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + -- READER 3 + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 1 + AlertIf(empty_sample_head(1) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(1) /= 11, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(1) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 44(I4S3),0(I3S3),33(I1S1),11(I3S4)/22 + -- PAYLOAD MEMORY: 44(I3S3),33(I1S1),22(I3S4)/11,0 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I1)/- + -- ISTATE: I1:ALIVE, I3:ALIVE, I4:NO_WRITERS + -- WRITER: W0:I1, W2:I3 + -- READER 2 + AlertIf(empty_sample_head(2) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(2) /= 11, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(2) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 44(I4S3),0(I3S3),33(I1S1),11(I3S4)/22 + -- PAYLOAD MEMORY: 44(I3S3),33(I1S1),22(I3S4)/11,0 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I1)/- + -- ISTATE: I1:ALIVE, I3:ALIVE, I4:NO_WRITERS + -- WRITER: W0:I1, W2:I3 + -- READER 3 + AlertIf(empty_sample_head(3) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(3) /= 11, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(3) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 44(I4S3),0(I3S3),33(I1S1),11(I3S4)/22 + -- PAYLOAD MEMORY: 44(I3S3),33(I1S1),22(I3S4)/11,0 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I1)/- + -- ISTATE: I1:ALIVE, I3:ALIVE, I4:NO_WRITERS + -- WRITER: W0:I1, W2:I3 + + AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + + -- VALIDATE STATE + + Log("R1,R2,R3: DDS Operation READ [MAX_SAMPLES 4, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := READ; + dds.max_samples := 4; + dds.sstate := ANY_SAMPLE_STATE; + dds.istate := ANY_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + -- READER 1 + ind <= 1; + start_dds; + wait_on_sig(dds_done); + -- READER 2 + ind <= 2; + start_dds; + wait_on_sig(dds_done); + -- READER 3 + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- READER 1 + AlertIf(empty_sample_head(1) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(1) /= 11, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(1) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 44(I4S3),0(I3S3),33(I1S1),11(I3S4)/22 + -- PAYLOAD MEMORY: 44(I3S3),33(I1S1),22(I3S4)/11,0 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I1)/- + -- ISTATE: I1:ALIVE, I3:ALIVE, I4:NO_WRITERS + -- WRITER: W0:I1, W2:I3 + -- READER 2 + AlertIf(empty_sample_head(2) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(2) /= 11, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(2) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 44(I4S3),0(I3S3),33(I1S1),11(I3S4)/22 + -- PAYLOAD MEMORY: 44(I3S3),33(I1S1),22(I3S4)/11,0 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I1)/- + -- ISTATE: I1:ALIVE, I3:ALIVE, I4:NO_WRITERS + -- WRITER: W0:I1, W2:I3 + -- READER 3 + AlertIf(empty_sample_head(3) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(3) /= 11, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(3) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 44(I4S3),0(I3S3),33(I1S1),11(I3S4)/22 + -- PAYLOAD MEMORY: 44(I3S3),33(I1S1),22(I3S4)/11,0 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I1)/- + -- ISTATE: I1:ALIVE, I3:ALIVE, I4:NO_WRITERS + -- WRITER: W0:I1, W2:I3 + + AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh1; + cc.payload := gen_payload(kh1,15); + cc.src_timestamp := gen_duration(15 sec); + + Log("R1,R2,R3: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Aligned Payload (2 Slots)]", INFO); + Log("R1,R2,R3: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 0; + remove_sample(0,mem(1)); + remove_sample(0,mem(2)); + remove_sample(0,mem(3)); + s := to_sample(cc,ALIVE_INSTANCE_STATE); + add_sample(s,mem(1), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(2), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(3), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + rtps.ret_code := OK; + -- READER 1 + ind <= 1; + start_rtps; + wait_on_sig(rtps_done); + -- READER 2 + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + -- READER 3 + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 1 + AlertIf(empty_sample_head(1) /= 44, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(1) /= 54, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(1) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I3S3),33(I1S1),11(I3S4),22(I1S2)/44 + -- PAYLOAD MEMORY: 44(I3S3),33(I1S1),22(I3S4),11(I1S2),0(I1S2)/- + -- INSTANCE MEMORY: 26(I3),0(I4),13(I1)/- + -- ISTATE: I1:ALIVE, I3:ALIVE, I4:NO_WRITERS + -- WRITER: W0:I1, W2:I3 + -- READER 2 + AlertIf(empty_sample_head(2) /= 44, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(2) /= 54, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(2) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I3S3),33(I1S1),11(I3S4),22(I1S2)/44 + -- PAYLOAD MEMORY: 44(I3S3),33(I1S1),22(I3S4),11(I1S2),0(I1S2)/- + -- INSTANCE MEMORY: 26(I3),0(I4),13(I1)/- + -- ISTATE: I1:ALIVE, I3:ALIVE, I4:NO_WRITERS + -- WRITER: W0:I1, W2:I3 + -- READER 3 + AlertIf(empty_sample_head(3) /= 44, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(3) /= 54, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(3) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I3S3),33(I1S1),11(I3S4),22(I1S2)/44 + -- PAYLOAD MEMORY: 44(I3S3),33(I1S1),22(I3S4),11(I1S2),0(I1S2)/- + -- INSTANCE MEMORY: 26(I3),0(I4),13(I1)/- + -- ISTATE: I1:ALIVE, I3:ALIVE, I4:NO_WRITERS + -- WRITER: W0:I1, W2:I3 + + AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh1; + cc.payload := gen_payload(kh1,10); + cc.src_timestamp := gen_duration(16 sec); + + -- TEST: ADD SAMPLE ON PAYLOAD MEMORY FULL & MAX_SAMPLES_PER_INSTANCE (Induce Double Remove) + + Log("R1,R2,R3: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Aligned Payload]", INFO); + Log("R1,R2,R3: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 0; + remove_sample(1,mem(1)); + remove_sample(1,mem(2)); + remove_sample(1,mem(3)); + remove_sample(0,mem(1)); + remove_sample(0,mem(2)); + remove_sample(0,mem(3)); + s := to_sample(cc,ALIVE_INSTANCE_STATE); + add_sample(s,mem(1), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(2), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(3), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + rtps.ret_code := OK; + -- READER 1 + ind <= 1; + start_rtps; + wait_on_sig(rtps_done); + -- READER 2 + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + -- READER 3 + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 1 + AlertIf(empty_sample_head(1) /= 0, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(1) /= 33, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(1) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 11(I3S4),22(I1S2),44(I1S3)/0,33 + -- PAYLOAD MEMORY: 22(I3S4),11(I1S2),0(I1S2),44(I1S3)/33 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I1)/- + -- ISTATE: I1:ALIVE, I3:ALIVE, I4:NO_WRITERS + -- WRITER: W0:I1, W2:I3 + -- READER 2 + AlertIf(empty_sample_head(2) /= 0, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(2) /= 33, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(2) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 11(I3S4),22(I1S2),44(I1S3)/0,33 + -- PAYLOAD MEMORY: 22(I3S4),11(I1S2),0(I1S2),44(I1S3)/33 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I1)/- + -- ISTATE: I1:ALIVE, I3:ALIVE, I4:NO_WRITERS + -- WRITER: W0:I1, W2:I3 + -- READER 3 + AlertIf(empty_sample_head(3) /= 0, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(3) /= 33, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(3) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 11(I3S4),22(I1S2),44(I1S3)/0,33 + -- PAYLOAD MEMORY: 22(I3S4),11(I1S2),0(I1S2),44(I1S3)/33 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I1)/- + -- ISTATE: I1:ALIVE, I3:ALIVE, I4:NO_WRITERS + -- WRITER: W0:I1, W2:I3 + + AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh3; + cc.payload := gen_payload(kh3,30); + cc.src_timestamp := gen_duration(17 sec); + + -- TEST: ADD SAMPLE BIGGER THAN AVAILABLE MEMORY SPACE + + Log("R1,R2,R3: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 3, Writer 0, Aligned Payload (3 Slots)]", INFO); + Log("R1,R2,R3: REJECTED [Payload memory Full]", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 0; + rtps.ret_code := REJECTED; + -- READER 1 + ind <= 1; + start_rtps; + wait_on_sig(rtps_done); + -- READER 2 + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + -- READER 3 + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 1 + AlertIf(empty_sample_head(1) /= 0, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(1) /= 33, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(1) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 11(I3S4),22(I1S2),44(I1S3)/0,33 + -- PAYLOAD MEMORY: 22(I3S4),11(I1S2),0(I1S2),44(I1S3)/33 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I1)/- + -- ISTATE: I1:ALIVE, I3:ALIVE, I4:NO_WRITERS + -- WRITER: W0:I1, W2:I3 + -- READER 2 + AlertIf(empty_sample_head(2) /= 0, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(2) /= 33, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(2) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 11(I3S4),22(I1S2),44(I1S3)/0,33 + -- PAYLOAD MEMORY: 22(I3S4),11(I1S2),0(I1S2),44(I1S3)/33 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I1)/- + -- ISTATE: I1:ALIVE, I3:ALIVE, I4:NO_WRITERS + -- WRITER: W0:I1, W2:I3 + -- READER 3 + AlertIf(empty_sample_head(3) /= 0, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(3) /= 33, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(3) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 11(I3S4),22(I1S2),44(I1S3)/0,33 + -- PAYLOAD MEMORY: 22(I3S4),11(I1S2),0(I1S2),44(I1S3)/33 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I1)/- + -- ISTATE: I1:ALIVE, I3:ALIVE, I4:NO_WRITERS + -- WRITER: W0:I1, W2:I3 + + AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := TRUE; + cc.kind := NOT_ALIVE_DISPOSED; + cc.instance := HANDLE_NIL; + cc.payload := gen_payload(kh4,5); + cc.src_timestamp := gen_duration(18 sec); + + -- TEST: DISPOSE SAMPLE [NOT_ALIVE_NO_WRITERS INSTANCE] + -- TEST: SAMPLE WITH SERIALIZED KEY [WITHOUT KEY_HASH] + + Log("R1,R2,R3: RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Instance 4, Writer 1]", INFO); + Log("R1,R2,R3: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 1; + s := to_sample(cc,NOT_ALIVE_DISPOSED_INSTANCE_STATE); + s.inst := kh4; + add_sample(s,mem(1), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(2), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(3), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + rtps.ret_code := OK; + -- READER 1 + ind <= 1; + start_rtps; + wait_on_sig(rtps_done); + -- READER 2 + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + -- READER 3 + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 1 + AlertIf(empty_sample_head(1) /= 33, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(1) /= 33, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(1) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 11(I3S4),22(I1S2),44(I1S3),0(I4S4)/33 + -- PAYLOAD MEMORY: 22(I3S4),11(I1S2),0(I1S2),44(I1S3)/33 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I1)/- + -- ISTATE: I1:ALIVE, I3:ALIVE, I4:DISPOSED + -- WRITER: W0:I1, W1:I4, W2:I3 + -- READER 2 + AlertIf(empty_sample_head(2) /= 33, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(2) /= 33, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(2) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 11(I3S4),22(I1S2),44(I1S3),0(I4S4)/33 + -- PAYLOAD MEMORY: 22(I3S4),11(I1S2),0(I1S2),44(I1S3)/33 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I1)/- + -- ISTATE: I1:ALIVE, I3:ALIVE, I4:DISPOSED + -- WRITER: W0:I1, W1:I4, W2:I3 + -- READER 3 + AlertIf(empty_sample_head(3) /= 33, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(3) /= 33, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(3) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 11(I3S4),22(I1S2),44(I1S3),0(I4S4)/33 + -- PAYLOAD MEMORY: 22(I3S4),11(I1S2),0(I1S2),44(I1S3)/33 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I1)/- + -- ISTATE: I1:ALIVE, I3:ALIVE, I4:DISPOSED + -- WRITER: W0:I1, W1:I4, W2:I3 + + AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + + -- VALIDATE STATE + + Log("R1,R2,R3: DDS Operation TAKE [MAX_SAMPLES 4, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := TAKE; + dds.max_samples := 4; + dds.sstate := ANY_SAMPLE_STATE; + dds.istate := ANY_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + -- READER 1 + ind <= 1; + start_dds; + wait_on_sig(dds_done); + -- READER 2 + ind <= 2; + start_dds; + wait_on_sig(dds_done); + -- READER 3 + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- READER 1 + AlertIf(empty_sample_head(1) /= 33, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(1) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(1) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: -/33,11,22,44,0 + -- PAYLOAD MEMORY: -/44,11,0,22,33 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I1)/- + -- ISTATE: I1:ALIVE, I3:ALIVE, I4:DISPOSED + -- WRITER: W0:I1, W1:I4, W2:I3 + -- READER 2 + AlertIf(empty_sample_head(2) /= 33, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(2) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(2) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: -/33,11,22,44,0 + -- PAYLOAD MEMORY: -/44,11,0,22,33 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I1)/- + -- ISTATE: I1:ALIVE, I3:ALIVE, I4:DISPOSED + -- WRITER: W0:I1, W1:I4, W2:I3 + -- READER 3 + AlertIf(empty_sample_head(3) /= 33, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(3) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(3) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: -/33,11,22,44,0 + -- PAYLOAD MEMORY: -/44,11,0,22,33 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I1)/- + -- ISTATE: I1:ALIVE, I3:ALIVE, I4:DISPOSED + -- WRITER: W0:I1, W1:I4, W2:I3 + + AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := TRUE; + cc.kind := NOT_ALIVE_DISPOSED; + cc.instance := kh4; + cc.payload := gen_payload(kh4,5); + cc.src_timestamp := gen_duration(19 sec); + + -- TEST: DISPOSE SAMPLE [NOT_ALIVE_DISPOSED INSTANCE] + + Log("R1,R2,R3: RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Instance 4, Writer 0]", INFO); + Log("R1,R2,R3: DROPPED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 0; + rtps.ret_code := OK; + -- READER 1 + ind <= 1; + start_rtps; + wait_on_sig(rtps_done); + -- READER 2 + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + -- READER 3 + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 1 + AlertIf(empty_sample_head(1) /= 33, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(1) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(1) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: -/33,11,22,44,0 + -- PAYLOAD MEMORY: -/44,11,0,22,33 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I1)/- + -- ISTATE: I1:ALIVE, I3:ALIVE, I4:DISPOSED + -- WRITER: W0:I1,I4 W1:I4, W2:I3 + -- READER 2 + AlertIf(empty_sample_head(2) /= 33, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(2) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(2) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: -/33,11,22,44,0 + -- PAYLOAD MEMORY: -/44,11,0,22,33 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I1)/- + -- ISTATE: I1:ALIVE, I3:ALIVE, I4:DISPOSED + -- WRITER: W0:I1,I4 W1:I4, W2:I3 + -- READER 3 + AlertIf(empty_sample_head(3) /= 33, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(3) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(3) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: -/33,11,22,44,0 + -- PAYLOAD MEMORY: -/44,11,0,22,33 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I1)/- + -- ISTATE: I1:ALIVE, I3:ALIVE, I4:DISPOSED + -- WRITER: W0:I1,I4 W1:I4, W2:I3 + + AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := TRUE; + cc.kind := NOT_ALIVE_UNREGISTERED; + cc.instance := kh4; + cc.payload := gen_payload(kh4,5); + cc.src_timestamp := gen_duration(20 sec); + + -- TEST: UNREGISTER SAMPLE [KNOWN INSTANCE, KNOWN WRITER] + -- TEST: UNREGISTER SAMPLE [NOT_ALIVE_DISPOSED INSTANCE] + + Log("R1,R2,R3: RTPS Operation ADD_CACHE_CHANGE [UNREGISTER, Instance 4, Writer 0]", INFO); + Log("R1,R2,R3: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 0; + rtps.ret_code := OK; + -- READER 1 + ind <= 1; + start_rtps; + wait_on_sig(rtps_done); + -- READER 2 + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + -- READER 3 + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 1 + AlertIf(empty_sample_head(1) /= 33, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(1) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(1) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: -/33,11,22,44,0 + -- PAYLOAD MEMORY: -/44,11,0,22,33 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I1)/- + -- ISTATE: I1:ALIVE, I3:ALIVE, I4:DISPOSED + -- WRITER: W0:I1, W1:I4, W2:I3 + -- READER 2 + AlertIf(empty_sample_head(2) /= 33, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(2) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(2) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: -/33,11,22,44,0 + -- PAYLOAD MEMORY: -/44,11,0,22,33 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I1)/- + -- ISTATE: I1:ALIVE, I3:ALIVE, I4:DISPOSED + -- WRITER: W0:I1, W1:I4, W2:I3 + -- READER 3 + AlertIf(empty_sample_head(3) /= 33, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(3) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(3) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: -/33,11,22,44,0 + -- PAYLOAD MEMORY: -/44,11,0,22,33 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I1)/- + -- ISTATE: I1:ALIVE, I3:ALIVE, I4:DISPOSED + -- WRITER: W0:I1, W1:I4, W2:I3 + + AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := TRUE; + cc.kind := NOT_ALIVE_UNREGISTERED; + cc.instance := kh1; + cc.payload := gen_payload(kh1,5); + cc.src_timestamp := gen_duration(21 sec); + + -- TEST: UNREGISTER SAMPLE [KNOWN INSTANCE, UNKNOWN WRITER] + + Log("R1,R2,R3: RTPS Operation ADD_CACHE_CHANGE [UNREGISTER, Instance 1, Writer 1]", INFO); + Log("R1,R2,R3: DROPPED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 1; + rtps.ret_code := OK; + -- READER 1 + ind <= 1; + start_rtps; + wait_on_sig(rtps_done); + -- READER 2 + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + -- READER 3 + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 1 + AlertIf(empty_sample_head(1) /= 33, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(1) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(1) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: -/33,11,22,44,0 + -- PAYLOAD MEMORY: -/44,11,0,22,33 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I1)/- + -- ISTATE: I1:ALIVE, I3:ALIVE, I4:DISPOSED + -- WRITER: W0:I1, W1:I4, W2:I3 + -- READER 2 + AlertIf(empty_sample_head(2) /= 33, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(2) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(2) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: -/33,11,22,44,0 + -- PAYLOAD MEMORY: -/44,11,0,22,33 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I1)/- + -- ISTATE: I1:ALIVE, I3:ALIVE, I4:DISPOSED + -- WRITER: W0:I1, W1:I4, W2:I3 + -- READER 3 + AlertIf(empty_sample_head(3) /= 33, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(3) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(3) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: -/33,11,22,44,0 + -- PAYLOAD MEMORY: -/44,11,0,22,33 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I1)/- + -- ISTATE: I1:ALIVE, I3:ALIVE, I4:DISPOSED + -- WRITER: W0:I1, W1:I4, W2:I3 + + AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := TRUE; + cc.kind := NOT_ALIVE_UNREGISTERED; + cc.instance := kh2; + cc.payload := gen_payload(kh2,5); + cc.src_timestamp := gen_duration(22 sec); + + -- TEST: UNREGISTER SAMPLE [UNKNOWN INSTANCE] + + Log("R1,R2,R3: RTPS Operation ADD_CACHE_CHANGE [UNREGISTER, Instance 2, Writer 1]", INFO); + Log("R1,R2,R3: DROPPED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 1; + rtps.ret_code := OK; + -- READER 1 + ind <= 1; + start_rtps; + wait_on_sig(rtps_done); + -- READER 2 + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + -- READER 3 + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 1 + AlertIf(empty_sample_head(1) /= 33, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(1) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(1) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: -/33,11,22,44,0 + -- PAYLOAD MEMORY: -/44,11,0,22,33 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I1)/- + -- ISTATE: I1:ALIVE, I3:ALIVE, I4:DISPOSED + -- WRITER: W0:I1, W1:I4, W2:I3 + -- READER 2 + AlertIf(empty_sample_head(2) /= 33, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(2) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(2) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: -/33,11,22,44,0 + -- PAYLOAD MEMORY: -/44,11,0,22,33 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I1)/- + -- ISTATE: I1:ALIVE, I3:ALIVE, I4:DISPOSED + -- WRITER: W0:I1, W1:I4, W2:I3 + -- READER 3 + AlertIf(empty_sample_head(3) /= 33, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(3) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(3) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: -/33,11,22,44,0 + -- PAYLOAD MEMORY: -/44,11,0,22,33 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I1)/- + -- ISTATE: I1:ALIVE, I3:ALIVE, I4:DISPOSED + -- WRITER: W0:I1, W1:I4, W2:I3 + + AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := TRUE; + cc.kind := NOT_ALIVE_UNREGISTERED; + cc.instance := kh1; + cc.payload := gen_payload(kh1,5); + cc.src_timestamp := gen_duration(23 sec); + + Log("R1,R2,R3: RTPS Operation ADD_CACHE_CHANGE [UNREGISTER, Instance 1, Writer 0]", INFO); + Log("R1,R2,R3: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 0; + s := to_sample(cc,NOT_ALIVE_NO_WRITERS_INSTANCE_STATE); + add_sample(s,mem(1), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(2), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(3), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + rtps.ret_code := OK; + -- READER 1 + ind <= 1; + start_rtps; + wait_on_sig(rtps_done); + -- READER 2 + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + -- READER 3 + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 1 + AlertIf(empty_sample_head(1) /= 11, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(1) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(1) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 33(I1S4)/11,22,44,0 + -- PAYLOAD MEMORY: -/44,11,0,22,33 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I1)/- + -- ISTATE: I1:NO_WRITERS, I3:ALIVE, I4:DISPOSED + -- WRITER: W1:I4, W2:I3 + -- READER 2 + AlertIf(empty_sample_head(2) /= 11, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(2) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(2) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 33(I1S4)/11,22,44,0 + -- PAYLOAD MEMORY: -/44,11,0,22,33 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I1)/- + -- ISTATE: I1:NO_WRITERS, I3:ALIVE, I4:DISPOSED + -- WRITER: W1:I4, W2:I3 + -- READER 3 + AlertIf(empty_sample_head(3) /= 11, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(3) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(3) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 33(I1S4)/11,22,44,0 + -- PAYLOAD MEMORY: -/44,11,0,22,33 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I1)/- + -- ISTATE: I1:NO_WRITERS, I3:ALIVE, I4:DISPOSED + -- WRITER: W1:I4, W2:I3 + + AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := TRUE; + cc.kind := NOT_ALIVE_UNREGISTERED; + cc.instance := kh1; + cc.payload := gen_payload(kh1,5); + cc.src_timestamp := gen_duration(24 sec); + + -- TEST: UNREGISTER SAMPLE [NOT_ALIVE_NO_WRITERS INSTANCE] + + Log("R1,R2,R3: RTPS Operation ADD_CACHE_CHANGE [UNREGISTER, Instance 1, Writer 2]", INFO); + Log("R1,R2,R3: DROPPED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 2; + rtps.ret_code := OK; + -- READER 1 + ind <= 1; + start_rtps; + wait_on_sig(rtps_done); + -- READER 2 + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + -- READER 3 + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 1 + AlertIf(empty_sample_head(1) /= 11, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(1) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(1) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 33(I1S4)/11,22,44,0 + -- PAYLOAD MEMORY: -/44,11,0,22,33 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I1)/- + -- ISTATE: I1:NO_WRITERS, I3:ALIVE, I4:DISPOSED + -- WRITER: W1:I4, W2:I3 + -- READER 2 + AlertIf(empty_sample_head(2) /= 11, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(2) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(2) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 33(I1S4)/11,22,44,0 + -- PAYLOAD MEMORY: -/44,11,0,22,33 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I1)/- + -- ISTATE: I1:NO_WRITERS, I3:ALIVE, I4:DISPOSED + -- WRITER: W1:I4, W2:I3 + -- READER 3 + AlertIf(empty_sample_head(3) /= 11, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(3) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(3) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 33(I1S4)/11,22,44,0 + -- PAYLOAD MEMORY: -/44,11,0,22,33 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I1)/- + -- ISTATE: I1:NO_WRITERS, I3:ALIVE, I4:DISPOSED + -- WRITER: W1:I4, W2:I3 + + AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := TRUE; + cc.kind := ALIVE_FILTERED; + cc.instance := kh1; + cc.payload := gen_payload(kh1,5); + cc.src_timestamp := gen_duration(25 sec); + + -- TEST: FILTER SAMPLE [KNOWN INSTANCE] + -- TEST: FILTER SAMPLE [NOT_ALIVE_NO_WRITERS INSTANCE] + + Log("R1,R2,R3: RTPS Operation ADD_CACHE_CHANGE [FILTERED, Instance 1, Writer 2]", INFO); + Log("R1,R2,R3: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + s := to_sample(cc,ALIVE_INSTANCE_STATE); + add_sample(s,mem(1), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(2), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(3), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + rtps.writer_pos := 2; + rtps.ret_code := OK; + -- READER 1 + ind <= 1; + start_rtps; + wait_on_sig(rtps_done); + -- READER 2 + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + -- READER 3 + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 1 + AlertIf(empty_sample_head(1) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(1) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(1) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 33(I1S4),11(I1S5)/22,44,0 + -- PAYLOAD MEMORY: -/44,11,0,22,33 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I1)/- + -- ISTATE: I1:ALIVE, I3:ALIVE, I4:DISPOSED + -- WRITER: W1:I4, W2:I1,I3 + -- READER 2 + AlertIf(empty_sample_head(2) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(2) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(2) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 33(I1S4),11(I1S5)/22,44,0 + -- PAYLOAD MEMORY: -/44,11,0,22,33 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I1)/- + -- ISTATE: I1:ALIVE, I3:ALIVE, I4:DISPOSED + -- WRITER: W1:I4, W2:I1,I3 + -- READER 3 + AlertIf(empty_sample_head(3) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(3) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(3) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 33(I1S4),11(I1S5)/22,44,0 + -- PAYLOAD MEMORY: -/44,11,0,22,33 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I1)/- + -- ISTATE: I1:ALIVE, I3:ALIVE, I4:DISPOSED + -- WRITER: W1:I4, W2:I1,I3 + + AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := TRUE; + cc.kind := NOT_ALIVE_UNREGISTERED; + cc.instance := kh4; + cc.payload := gen_payload(kh1,5); + cc.src_timestamp := gen_duration(26 sec); + + -- TEST: UNREGISTER SAMPLE [NOT_ALIVE_DISPOSED INSTANCE, STALE INSTANCE TRANSITION] + + Log("R1,R2,R3: RTPS Operation ADD_CACHE_CHANGE [UNREGISTER, Instance 4, Writer 1]", INFO); + Log("R1,R2,R3: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 1; + rtps.ret_code := OK; + -- READER 1 + ind <= 1; + start_rtps; + wait_on_sig(rtps_done); + -- READER 2 + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + -- READER 3 + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 1 + AlertIf(empty_sample_head(1) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(1) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(1) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 33(I1S4),11(I1S5)/22,44,0 + -- PAYLOAD MEMORY: -/44,11,0,22,33 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I1)/- + -- ISTATE: I1:ALIVE, I3:ALIVE, I4:DISPOSED + -- WRITER: W2:I1,I3 + -- READER 2 + AlertIf(empty_sample_head(2) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(2) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(2) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 33(I1S4),11(I1S5)/22,44,0 + -- PAYLOAD MEMORY: -/44,11,0,22,33 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I1)/- + -- ISTATE: I1:ALIVE, I3:ALIVE, I4:DISPOSED + -- WRITER: W2:I1,I3 + -- READER 3 + AlertIf(empty_sample_head(3) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(3) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(3) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 33(I1S4),11(I1S5)/22,44,0 + -- PAYLOAD MEMORY: -/44,11,0,22,33 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I1)/- + -- ISTATE: I1:ALIVE, I3:ALIVE, I4:DISPOSED + -- WRITER: W2:I1,I3 + + AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh2; + cc.payload := gen_payload(kh2,10); + cc.src_timestamp := gen_duration(27 sec); + + -- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKOWN INSTANCE, NOT_ALIVE_DISPOSED & STALE INSTANCE] + + Log("R1,R2,R3: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 2, Writer 0, Aligned Payload]", INFO); + Log("R1,R2,R3: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 0; + remove_inst(kh4, mem(1)); + remove_inst(kh4, mem(2)); + remove_inst(kh4, mem(3)); + s := to_sample(cc,ALIVE_INSTANCE_STATE); + add_sample(s,mem(1), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(2), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(3), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + rtps.ret_code := OK; + -- READER 1 + ind <= 1; + start_rtps; + wait_on_sig(rtps_done); + -- READER 2 + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + -- READER 3 + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 1 + AlertIf(empty_sample_head(1) /= 44, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(1) /= 11, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(1) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 33(I1S4),11(I1S5),22(I2S1)/44,0 + -- PAYLOAD MEMORY: 44(I2S1)/11,0,22,33 + -- INSTANCE MEMORY: 26(I3),0(I2),13(I1)/- + -- ISTATE: I1:ALIVE, I2:ALIVE, I3:ALIVE + -- WRITER: W0:I2, W2:I1,I3 + -- READER 2 + AlertIf(empty_sample_head(2) /= 44, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(2) /= 11, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(2) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 33(I1S4),11(I1S5),22(I2S1)/44,0 + -- PAYLOAD MEMORY: 44(I2S1)/11,0,22,33 + -- INSTANCE MEMORY: 26(I3),0(I2),13(I1)/- + -- ISTATE: I1:ALIVE, I2:ALIVE, I3:ALIVE + -- WRITER: W0:I2, W2:I1,I3 + -- READER 3 + AlertIf(empty_sample_head(3) /= 44, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(3) /= 11, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(3) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 33(I1S4),11(I1S5),22(I2S1)/44,0 + -- PAYLOAD MEMORY: 44(I2S1)/11,0,22,33 + -- INSTANCE MEMORY: 26(I3),0(I2),13(I1)/- + -- ISTATE: I1:ALIVE, I2:ALIVE, I3:ALIVE + -- WRITER: W0:I2, W2:I1,I3 + + AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + + -- VALIDATE STATE + + Log("R1,R2,R3: DDS Operation TAKE [MAX_SAMPLES 4, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := TAKE; + dds.max_samples := 4; + dds.sstate := ANY_SAMPLE_STATE; + dds.istate := ANY_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + -- READER 1 + ind <= 1; + start_dds; + wait_on_sig(dds_done); + -- READER 2 + ind <= 2; + start_dds; + wait_on_sig(dds_done); + -- READER 3 + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- READER 1 + AlertIf(empty_sample_head(1) /= 44, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(1) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(1) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: -/44,0,33,11,22 + -- PAYLOAD MEMORY: -/44,11,0,22,33 + -- INSTANCE MEMORY: 26(I3),0(I2),13(I1)/- + -- ISTATE: I1:ALIVE, I2:ALIVE, I3:ALIVE + -- WRITER: W0:I2, W2:I1,I3 + -- READER 2 + AlertIf(empty_sample_head(2) /= 44, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(2) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(2) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: -/44,0,33,11,22 + -- PAYLOAD MEMORY: -/44,11,0,22,33 + -- INSTANCE MEMORY: 26(I3),0(I2),13(I1)/- + -- ISTATE: I1:ALIVE, I2:ALIVE, I3:ALIVE + -- WRITER: W0:I2, W2:I1,I3 + -- READER 3 + AlertIf(empty_sample_head(3) /= 44, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(3) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(3) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: -/44,0,33,11,22 + -- PAYLOAD MEMORY: -/44,11,0,22,33 + -- INSTANCE MEMORY: 26(I3),0(I2),13(I1)/- + -- ISTATE: I1:ALIVE, I2:ALIVE, I3:ALIVE + -- WRITER: W0:I2, W2:I1,I3 + + AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := TRUE; + cc.kind := NOT_ALIVE_DISPOSED; + cc.instance := kh1; + cc.payload := gen_payload(kh1,5); + cc.src_timestamp := gen_duration(28 sec); + + Log("R1,R2,R3: RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Instance 1, Writer 2]", INFO); + Log("R1,R2,R3: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 2; + s := to_sample(cc,NOT_ALIVE_DISPOSED_INSTANCE_STATE); + add_sample(s,mem(1), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(2), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(3), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + rtps.ret_code := OK; + -- READER 1 + ind <= 1; + start_rtps; + wait_on_sig(rtps_done); + -- READER 2 + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + -- READER 3 + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 1 + AlertIf(empty_sample_head(1) /= 0, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(1) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(1) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 44(I1S6)/0,33,11,22 + -- PAYLOAD MEMORY: -/44,11,0,22,33 + -- INSTANCE MEMORY: 26(I3),0(I2),13(I1)/- + -- ISTATE: I1:DISPOSED, I2:ALIVE, I3:ALIVE + -- WRITER: W0:I2, W2:I1,I3 + -- READER 2 + AlertIf(empty_sample_head(2) /= 0, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(2) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(2) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 44(I1S6)/0,33,11,22 + -- PAYLOAD MEMORY: -/44,11,0,22,33 + -- INSTANCE MEMORY: 26(I3),0(I2),13(I1)/- + -- ISTATE: I1:DISPOSED, I2:ALIVE, I3:ALIVE + -- WRITER: W0:I2, W2:I1,I3 + -- READER 3 + AlertIf(empty_sample_head(3) /= 0, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(3) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(3) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 44(I1S6)/0,33,11,22 + -- PAYLOAD MEMORY: -/44,11,0,22,33 + -- INSTANCE MEMORY: 26(I3),0(I2),13(I1)/- + -- ISTATE: I1:DISPOSED, I2:ALIVE, I3:ALIVE + -- WRITER: W0:I2, W2:I1,I3 + + AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := TRUE; + cc.kind := ALIVE_FILTERED; + cc.instance := kh1; + cc.payload := gen_payload(kh1,5); + cc.src_timestamp := gen_duration(29 sec); + + -- TEST: FILTER SAMPLE [NOT_ALIVE_DISPOSED INSTANCE] + + Log("R1,R2,R3: RTPS Operation ADD_CACHE_CHANGE [FILTERED, Instance 1, Writer 2]", INFO); + Log("R1,R2,R3: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + s := to_sample(cc,ALIVE_INSTANCE_STATE); + add_sample(s,mem(1), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(2), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(3), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + rtps.writer_pos := 2; + rtps.ret_code := OK; + -- READER 1 + ind <= 1; + start_rtps; + wait_on_sig(rtps_done); + -- READER 2 + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + -- READER 3 + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 1 + AlertIf(empty_sample_head(1) /= 33, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(1) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(1) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 44(I1S6),0(I1S7)/33,11,22 + -- PAYLOAD MEMORY: -/44,11,0,22,33 + -- INSTANCE MEMORY: 26(I3),0(I2),13(I1)/- + -- ISTATE: I1:ALIVE, I2:ALIVE, I3:ALIVE + -- WRITER: W0:I2, W2:I1,I3 + -- READER 2 + AlertIf(empty_sample_head(2) /= 33, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(2) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(2) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 44(I1S6),0(I1S7)/33,11,22 + -- PAYLOAD MEMORY: -/44,11,0,22,33 + -- INSTANCE MEMORY: 26(I3),0(I2),13(I1)/- + -- ISTATE: I1:ALIVE, I2:ALIVE, I3:ALIVE + -- WRITER: W0:I2, W2:I1,I3 + -- READER 3 + AlertIf(empty_sample_head(3) /= 33, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(3) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(3) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 44(I1S6),0(I1S7)/33,11,22 + -- PAYLOAD MEMORY: -/44,11,0,22,33 + -- INSTANCE MEMORY: 26(I3),0(I2),13(I1)/- + -- ISTATE: I1:ALIVE, I2:ALIVE, I3:ALIVE + -- WRITER: W0:I2, W2:I1,I3 + + AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := TRUE; + cc.kind := ALIVE_FILTERED; + cc.instance := kh4; + cc.payload := gen_payload(kh4,5); + cc.src_timestamp := gen_duration(30 sec); + + -- TEST: FILTER SAMPLE [UNKNOWN INSTANCE] + + Log("R1,R2,R3: RTPS Operation ADD_CACHE_CHANGE [FILTERED, Instance 4, Writer 1]", INFO); + Log("R1,R2,R3: DROPPED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 1; + rtps.ret_code := OK; + -- READER 1 + ind <= 1; + start_rtps; + wait_on_sig(rtps_done); + -- READER 2 + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + -- READER 3 + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 1 + AlertIf(empty_sample_head(1) /= 33, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(1) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(1) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 44(I1S6),0(I1S7)/33,11,22 + -- PAYLOAD MEMORY: -/44,11,0,22,33 + -- INSTANCE MEMORY: 26(I3),0(I2),13(I1)/- + -- ISTATE: I1:ALIVE, I2:ALIVE, I3:ALIVE + -- WRITER: W0:I2, W2:I1,I3 + -- READER 2 + AlertIf(empty_sample_head(2) /= 33, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(2) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(2) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 44(I1S6),0(I1S7)/33,11,22 + -- PAYLOAD MEMORY: -/44,11,0,22,33 + -- INSTANCE MEMORY: 26(I3),0(I2),13(I1)/- + -- ISTATE: I1:ALIVE, I2:ALIVE, I3:ALIVE + -- WRITER: W0:I2, W2:I1,I3 + -- READER 3 + AlertIf(empty_sample_head(3) /= 33, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(3) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(3) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 44(I1S6),0(I1S7)/33,11,22 + -- PAYLOAD MEMORY: -/44,11,0,22,33 + -- INSTANCE MEMORY: 26(I3),0(I2),13(I1)/- + -- ISTATE: I1:ALIVE, I2:ALIVE, I3:ALIVE + -- WRITER: W0:I2, W2:I1,I3 + + AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh3; + cc.payload := gen_payload(kh3,10); + cc.src_timestamp := gen_duration(10 sec); + + -- TEST: SAMPLE WITH EARLY TIMESTAMP [TIMESTAMP EARLIER THAN LAST READ] + + Log("R1,R2,R3: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 3, Writer 2, Aligned Payload]", INFO); + Log("R1,R2,R3: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 2; + s := to_sample(cc,ALIVE_INSTANCE_STATE); + add_sample(s,mem(1), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(2), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(3), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + rtps.ret_code := OK; + -- READER 1 + ind <= 1; + start_rtps; + wait_on_sig(rtps_done); + -- READER 2 + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + -- READER 3 + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 1 + AlertIf(empty_sample_head(1) /= 11, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(1) /= 11, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(1) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 44(I1S6),0(I1S7),33(I3S5)/11,22 + -- PAYLOAD MEMORY: 44(I3S5)/11,0,22,33 + -- INSTANCE MEMORY: 26(I3),0(I2),13(I1)/- + -- ISTATE: I1:ALIVE, I2:ALIVE, I3:ALIVE + -- WRITER: W0:I2, W2:I1,I3 + -- READER 2 + AlertIf(empty_sample_head(2) /= 11, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(2) /= 11, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(2) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 44(I1S6),0(I1S7),33(I3S5)/11,22 + -- PAYLOAD MEMORY: 44(I3S5)/11,0,22,33 + -- INSTANCE MEMORY: 26(I3),0(I2),13(I1)/- + -- ISTATE: I1:ALIVE, I2:ALIVE, I3:ALIVE + -- WRITER: W0:I2, W2:I1,I3 + -- READER 3 + AlertIf(empty_sample_head(3) /= 11, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(3) /= 11, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(3) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 44(I1S6),0(I1S7),33(I3S5)/11,22 + -- PAYLOAD MEMORY: 44(I3S5)/11,0,22,33 + -- INSTANCE MEMORY: 26(I3),0(I2),13(I1)/- + -- ISTATE: I1:ALIVE, I2:ALIVE, I3:ALIVE + -- WRITER: W0:I2, W2:I1,I3 + + AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := TRUE; + cc.kind := NOT_ALIVE_UNREGISTERED; + cc.instance := kh2; + cc.payload := gen_payload(kh2,5); + cc.src_timestamp := gen_duration(31 sec); + + Log("R1,R2,R3: RTPS Operation ADD_CACHE_CHANGE [UNREGISTER, Instance 2, Writer 0]", INFO); + Log("R1,R2,R3: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 0; + s := to_sample(cc,NOT_ALIVE_NO_WRITERS_INSTANCE_STATE); + add_sample(s,mem(1), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(2), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(3), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + rtps.ret_code := OK; + -- READER 1 + ind <= 1; + start_rtps; + wait_on_sig(rtps_done); + -- READER 2 + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + -- READER 3 + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 1 + AlertIf(empty_sample_head(1) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(1) /= 11, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(1) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 44(I1S6),0(I1S7),33(I3S5),11(I2S2)/22 + -- PAYLOAD MEMORY: 44(I3S5)/11,0,22,33 + -- INSTANCE MEMORY: 26(I3),0(I2),13(I1)/- + -- ISTATE: I1:ALIVE, I2:NO_WRITERS, I3: ALIVE + -- WRITER: W2:I1,I3 + -- READER 2 + AlertIf(empty_sample_head(2) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(2) /= 11, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(2) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 44(I1S6),0(I1S7),33(I3S5),11(I2S2)/22 + -- PAYLOAD MEMORY: 44(I3S5)/11,0,22,33 + -- INSTANCE MEMORY: 26(I3),0(I2),13(I1)/- + -- ISTATE: I1:ALIVE, I2:NO_WRITERS, I3: ALIVE + -- WRITER: W2:I1,I3 + -- READER 3 + AlertIf(empty_sample_head(3) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(3) /= 11, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(3) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 44(I1S6),0(I1S7),33(I3S5),11(I2S2)/22 + -- PAYLOAD MEMORY: 44(I3S5)/11,0,22,33 + -- INSTANCE MEMORY: 26(I3),0(I2),13(I1)/- + -- ISTATE: I1:ALIVE, I2:NO_WRITERS, I3: ALIVE + -- WRITER: W2:I1,I3 + + AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + + -- VALIDATE STATE + + Log("R1,R2,R3: DDS Operation TAKE [MAX_SAMPLES 4, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := TAKE; + dds.max_samples := 4; + dds.sstate := ANY_SAMPLE_STATE; + dds.istate := ANY_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + -- READER 1 + ind <= 1; + start_dds; + wait_on_sig(dds_done); + -- READER 2 + ind <= 2; + start_dds; + wait_on_sig(dds_done); + -- READER 3 + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- READER 1 + AlertIf(empty_sample_head(1) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(1) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(1) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: -/22,44,0,33,11 + -- PAYLOAD MEMORY: -/44,11,0,22,33 + -- INSTANCE MEMORY: 26(I3),0(I2),13(I1)/- + -- ISTATE: I1:ALIVE, I2:NO_WRITERS, I3: ALIVE + -- WRITER: W2:I1,I3 + -- READER 2 + AlertIf(empty_sample_head(2) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(2) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(2) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: -/22,44,0,33,11 + -- PAYLOAD MEMORY: -/44,11,0,22,33 + -- INSTANCE MEMORY: 26(I3),0(I2),13(I1)/- + -- ISTATE: I1:ALIVE, I2:NO_WRITERS, I3: ALIVE + -- WRITER: W2:I1,I3 + -- READER 3 + AlertIf(empty_sample_head(3) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(3) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(3) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: -/22,44,0,33,11 + -- PAYLOAD MEMORY: -/44,11,0,22,33 + -- INSTANCE MEMORY: 26(I3),0(I2),13(I1)/- + -- ISTATE: I1:ALIVE, I2:NO_WRITERS, I3: ALIVE + -- WRITER: W2:I1,I3 + + AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := TRUE; + cc.kind := NOT_ALIVE_DISPOSED; + cc.instance := kh4; + cc.payload := gen_payload(kh4,5); + cc.src_timestamp := gen_duration(32 sec); + + -- TEST: DISPOSE SAMPLE [UNKNOWN INSTANCE] + + Log("R1,R2,R3: RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Instance 4, Writer 1]", INFO); + Log("R1,R2,R3: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 1; + s := to_sample(cc,NOT_ALIVE_DISPOSED_INSTANCE_STATE); + add_sample(s,mem(1), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(2), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(3), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + rtps.ret_code := OK; + -- READER 1 + ind <= 1; + start_rtps; + wait_on_sig(rtps_done); + -- READER 2 + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + -- READER 3 + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 1 + AlertIf(empty_sample_head(1) /= 44, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(1) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(1) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 22(I4S1)/44,0,33,11 + -- PAYLOAD MEMORY: -/44,11,0,22,33 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I1)/- + -- ISTATE: I1:ALIVE, I3: ALIVE, I4:DISPOSED + -- WRITER: W1:I4, W2:I1,I3 + -- READER 2 + AlertIf(empty_sample_head(2) /= 44, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(2) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(2) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 22(I4S1)/44,0,33,11 + -- PAYLOAD MEMORY: -/44,11,0,22,33 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I1)/- + -- ISTATE: I1:ALIVE, I3: ALIVE, I4:DISPOSED + -- WRITER: W1:I4, W2:I1,I3 + -- READER 3 + AlertIf(empty_sample_head(3) /= 44, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(3) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(3) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 22(I4S1)/44,0,33,11 + -- PAYLOAD MEMORY: -/44,11,0,22,33 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I1)/- + -- ISTATE: I1:ALIVE, I3: ALIVE, I4:DISPOSED + -- WRITER: W1:I4, W2:I1,I3 + + AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + + -- VALIDATE STATE + + Log("R1,R2,R3: DDS Operation READ [MAX_SAMPLES 4, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := TAKE; + dds.max_samples := 4; + dds.sstate := ANY_SAMPLE_STATE; + dds.istate := NOT_ALIVE_DISPOSED_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + -- READER 1 + ind <= 1; + start_dds; + wait_on_sig(dds_done); + -- READER 2 + ind <= 2; + start_dds; + wait_on_sig(dds_done); + -- READER 3 + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- READER 1 + AlertIf(empty_sample_head(1) /= 44, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(1) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(1) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 22(I4S1)/44,0,33,11 + -- PAYLOAD MEMORY: -/44,11,0,22,33 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I1)/- + -- ISTATE: I1:ALIVE, I3: ALIVE, I4:DISPOSED + -- WRITER: W1:I4, W2:I1,I3 + -- READER 2 + AlertIf(empty_sample_head(2) /= 44, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(2) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(2) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 22(I4S1)/44,0,33,11 + -- PAYLOAD MEMORY: -/44,11,0,22,33 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I1)/- + -- ISTATE: I1:ALIVE, I3: ALIVE, I4:DISPOSED + -- WRITER: W1:I4, W2:I1,I3 + -- READER 3 + AlertIf(empty_sample_head(3) /= 44, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(3) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(3) /= 38, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 22(I4S1)/44,0,33,11 + -- PAYLOAD MEMORY: -/44,11,0,22,33 + -- INSTANCE MEMORY: 26(I3),0(I4),13(I1)/- + -- ISTATE: I1:ALIVE, I3: ALIVE, I4:DISPOSED + -- WRITER: W1:I4, W2:I1,I3 + + AffirmIf(status_id,(status(1) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(2) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(3) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + + Log("*READER 4*", INFO); + -- READER 4 + AlertIf(empty_sample_head(4) /= 0, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(4) /= 0, "Payload Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: -/0,11,22 + -- PAYLOAD MEMORY: -/0,10,20 + -- ISTATE: - + -- WRITER: - + + AffirmIf(status_id,(status(4) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.payload := gen_payload(KEY_HASH_NIL,9); + cc.src_timestamp := gen_duration(1 sec); + + -- TEST: NORMAL ADD_CACHE_CHANGE + -- TEST: NORMAL SAMPLE + -- TEST: SAMPLE WITH ALIGNED PAYLOAD + + Log("R4: RTPS Operation ADD_CACHE_CHANGE [Writer 0, Aligned Payload]", INFO); + Log("R4: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 0; + rtps.ret_code := OK; + s := to_sample(cc,ALIVE_INSTANCE_STATE); + add_sample(s,mem(4), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + -- READER 4 + ind <= 4; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 4 + AlertIf(empty_sample_head(4) /= 11, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(4) /= 10, "Payload Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(S1)/11,22 + -- PAYLOAD MEMORY: 0(S1)/10,20 + -- ISTATE: ALIVE + -- WRITER: W0 + + AffirmIf(status_id,(status(4) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.payload := gen_payload(KEY_HASH_NIL,27); + cc.src_timestamp := gen_duration(2 sec); + + -- TEST: ADD SAMPLE BIGGER THAN AVAILABLE MEMORY SPACE + + Log("R4: RTPS Operation ADD_CACHE_CHANGE [Writer 0, Aligned Payload (3 Slots)]", INFO); + Log("R4: REJECTED [Payload Memory exceeded]", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 0; + rtps.ret_code := REJECTED; + -- READER 4 + ind <= 4; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 4 + AlertIf(empty_sample_head(4) /= 11, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(4) /= 10, "Payload Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(S1)/11,22 + -- PAYLOAD MEMORY: 0(S1)/10,20 + -- ISTATE: ALIVE + -- WRITER: W0 + + AffirmIf(status_id,(status(4) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.payload := gen_payload(KEY_HASH_NIL,9); + cc.src_timestamp := gen_duration(3 sec); + + Log("R4: RTPS Operation ADD_CACHE_CHANGE [Writer 0, Aligned Payload]", INFO); + Log("R4: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 0; + rtps.ret_code := OK; + s := to_sample(cc,ALIVE_INSTANCE_STATE); + add_sample(s,mem(4), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + -- READER 4 + ind <= 4; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 4 + AlertIf(empty_sample_head(4) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(4) /= 20, "Payload Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(S1),11(S2)/22 + -- PAYLOAD MEMORY: 0(S1),10(S2)/20 + -- ISTATE: ALIVE + -- WRITER: W0 + + AffirmIf(status_id,(status(4) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.payload := gen_payload(KEY_HASH_NIL,9); + cc.src_timestamp := gen_duration(4 sec); + + -- TEST: ADD SAMPLE ON MAX_SAMPLES + + Log("R4: RTPS Operation ADD_CACHE_CHANGE [Writer 0, Aligned Payload]", INFO); + Log("R4: REJECTED [MAX_SAMPLES exceeded]", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 0; + rtps.ret_code := REJECTED; + -- READER 4 + ind <= 4; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 4 + AlertIf(empty_sample_head(4) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(4) /= 20, "Payload Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(S1),11(S2)/22 + -- PAYLOAD MEMORY: 0(S1),10(S2)/20 + -- ISTATE: ALIVE + -- WRITER: W0 + + AffirmIf(status_id,(status(4) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + + -- VALIDATE STATE + + Log("R4: DDS Operation TAKE [MAX_SAMPLES 2, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := TAKE; + dds.max_samples := 2; + dds.sstate := ANY_SAMPLE_STATE; + dds.istate := ANY_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + -- READER 4 + ind <= 4; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- READER 4 + AlertIf(empty_sample_head(4) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(4) /= 10, "Payload Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: -/22,0,11 + -- PAYLOAD MEMORY: -/10,0,20 + -- ISTATE: ALIVE + -- WRITER: W0 + + AffirmIf(status_id,(status(4) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := NOT_ALIVE_DISPOSED; + cc.src_timestamp := gen_duration(5 sec); + + -- TEST: DISPOSE SAMPLE + + Log("R4: RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Writer 0]", INFO); + Log("R4: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 0; + rtps.ret_code := OK; + s := to_sample(cc,NOT_ALIVE_DISPOSED_INSTANCE_STATE); + add_sample(s,mem(4), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + -- READER 4 + ind <= 4; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 4 + AlertIf(empty_sample_head(4) /= 0, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(4) /= 10, "Payload Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 22(S3)/0,11 + -- PAYLOAD MEMORY: -/10,0,20 + -- ISTATE: DISPOSED + -- WRITER: W0 + + AffirmIf(status_id,(status(4) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := NOT_ALIVE_DISPOSED; + cc.src_timestamp := gen_duration(6 sec); + + -- TEST: DISPOSE SAMPLE [NOT_ALIVE_DISPOSED INSTANCE] + + Log("R4: RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Writer 0]", INFO); + Log("R4: DROPPED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 0; + rtps.ret_code := OK; + -- READER 4 + ind <= 4; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 4 + AlertIf(empty_sample_head(4) /= 0, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(4) /= 10, "Payload Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 22(S3)/0,11 + -- PAYLOAD MEMORY: -/10,0,20 + -- ISTATE: DISPOSED + -- WRITER: W0 + + AffirmIf(status_id,(status(4) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE_FILTERED; + cc.src_timestamp := gen_duration(7 sec); + + -- TEST: FILTER SAMPLE + -- TEST: FILTER SAMPLE [NOT_ALIVE_DISPOSED INSTANCE] + + Log("R4: RTPS Operation ADD_CACHE_CHANGE [FILTERED, Writer 0]", INFO); + Log("R4: DROPPED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 0; + rtps.ret_code := OK; + s := to_sample(cc,ALIVE_INSTANCE_STATE); + add_sample(s,mem(4), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + -- READER 4 + ind <= 4; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 4 + AlertIf(empty_sample_head(4) /= 11, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(4) /= 10, "Payload Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 22(S3),0(S4)/11 + -- PAYLOAD MEMORY: -/10,0,20 + -- ISTATE: ALIVE + -- WRITER: W0 + + AffirmIf(status_id,(status(4) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + + -- VALIDATE STATE + + Log("R4: DDS Operation TAKE [MAX_SAMPLES 2, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := TAKE; + dds.max_samples := 2; + dds.sstate := ANY_SAMPLE_STATE; + dds.istate := ANY_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + -- READER 4 + ind <= 4; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- READER 4 + AlertIf(empty_sample_head(4) /= 11, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(4) /= 10, "Payload Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: -/11,22,0 + -- PAYLOAD MEMORY: -/10,0,20 + -- ISTATE: ALIVE + -- WRITER: W0 + + AffirmIf(status_id,(status(4) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + + -- TEST: SAMPLE WITH UNALIGNED PAYLOAD [>1 SLOT] + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.payload := gen_payload(KEY_HASH_NIL,27); + cc.src_timestamp := gen_duration(8 sec); + + Log("R4: RTPS Operation ADD_CACHE_CHANGE [Writer 0, Aligned Payload (3 Slots)]", INFO); + Log("R4: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 0; + rtps.ret_code := OK; + s := to_sample(cc,ALIVE_INSTANCE_STATE); + add_sample(s,mem(4), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 4 + AlertIf(empty_sample_head(4) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(4) /= 54, "Payload Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 11(S5)/22,0 + -- PAYLOAD MEMORY: 10(S5),0(S5),20(S5)/- + -- ISTATE: ALIVE + -- WRITER: W0 + + AffirmIf(status_id,(status(4) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.payload := gen_payload(KEY_HASH_NIL,9); + cc.src_timestamp := gen_duration(9 sec); + + -- TEST: ADD_CACHE_CHANGE ON PAYLOAD MEMORY FULL + + Log("R4: RTPS Operation ADD_CACHE_CHANGE [Writer 0, Aligned Payload]", INFO); + Log("R4: REJECTED [Payload Memory Full]", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 0; + rtps.ret_code := REJECTED; + -- READER 4 + ind <= 4; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 4 + AlertIf(empty_sample_head(4) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(4) /= 54, "Payload Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 11(S5)/22,0 + -- PAYLOAD MEMORY: 10(S5),0(S5),20(S5)/- + -- ISTATE: ALIVE + -- WRITER: W0 + + AffirmIf(status_id,(status(4) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + + -- TEST: REMOVE_WRITER [UNKNOWN WRITER] + + Log("R4: RTPS Operation REMOVE_WRITER [Writer 1]", INFO); + Log("R4: DROPPED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := REMOVE_WRITER; + rtps.writer_pos := 1; + rtps.ret_code := OK; + -- READER 4 + ind <= 4; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 4 + AlertIf(empty_sample_head(4) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(4) /= 54, "Payload Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 11(S5)/22,0 + -- PAYLOAD MEMORY: 10(S5),0(S5),20(S5)/- + -- ISTATE: ALIVE + -- WRITER: W0 + + AffirmIf(status_id,(status(4) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + + -- VALIDATE STATE + + Log("R4: DDS Operation TAKE [MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := TAKE; + dds.max_samples := 1; + dds.sstate := ANY_SAMPLE_STATE; + dds.istate := ANY_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + -- READER 4 + ind <= 4; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- READER 4 + AlertIf(empty_sample_head(4) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(4) /= 10, "Payload Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: -/22,0,11 + -- PAYLOAD MEMORY: -/10,0,20 + -- ISTATE: ALIVE + -- WRITER: W0 + + AffirmIf(status_id,(status(4) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.payload := gen_payload(KEY_HASH_NIL,9); + cc.src_timestamp := gen_duration(10 sec); + + Log("R4: RTPS Operation ADD_CACHE_CHANGE [Writer 0, Aligned Payload]", INFO); + Log("R4: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 0; + rtps.ret_code := OK; + s := to_sample(cc,ALIVE_INSTANCE_STATE); + add_sample(s,mem(4), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + -- READER 4 + ind <= 4; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 4 + AlertIf(empty_sample_head(4) /= 0, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(4) /= 0, "Payload Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 22(S6)/0,11 + -- PAYLOAD MEMORY: 10(S6)/0,20 + -- ISTATE: ALIVE + -- WRITER: W0 + + AffirmIf(status_id,(status(4) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.payload := gen_payload(KEY_HASH_NIL,9); + cc.src_timestamp := gen_duration(11 sec); + + Log("R4: RTPS Operation ADD_CACHE_CHANGE [Writer 0, Aligned Payload]", INFO); + Log("R4: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 0; + rtps.ret_code := OK; + s := to_sample(cc,ALIVE_INSTANCE_STATE); + add_sample(s,mem(4), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 4 + AlertIf(empty_sample_head(4) /= 11, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(4) /= 20, "Payload Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 22(S6),0(S7)/11 + -- PAYLOAD MEMORY: 10(S6),0(S7)/20 + -- ISTATE: ALIVE + -- WRITER: W0 + + AffirmIf(status_id,(status(4) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + + -- TEST: REMOVE_WRITER [KNOWN WRITER] + -- TEST: REMOVE_WRITER [NOT_ALIVE_NO_WRITERS Transition] + -- TEST: REMOVE_WRITER ON MAX_SAMPLES [NOT_ALIVE_NO_WRITERS Transition] + + Log("R4: RTPS Operation REMOVE_WRITER [Writer 0]", INFO); + Log("R4: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := REMOVE_WRITER; + rtps.writer_pos := 0; + change_istate(HANDLE_NIL, NOT_ALIVE_NO_WRITERS_INSTANCE_STATE, mem(4)); + rtps.ret_code := OK; + -- READER 4 + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 4 + AlertIf(empty_sample_head(4) /= 11, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(4) /= 20, "Payload Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 22(S6),0(S7)/11 + -- PAYLOAD MEMORY: 10(S6),0(S7)/20 + -- ISTATE: NO_WRITERS + -- WRITER: - + + AffirmIf(status_id,(status(4) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := TRUE; + cc.kind := NOT_ALIVE_UNREGISTERED; + cc.src_timestamp := check_time; + + Log("R4: DDS Operation TAKE [MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := TAKE; + dds.max_samples := 1; + dds.sstate := ANY_SAMPLE_STATE; + dds.istate := ANY_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + s := to_sample(cc,NOT_ALIVE_NO_WRITERS_INSTANCE_STATE); + add_sample(s,mem(4), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + -- READER 4 + ind <= 4; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- READER 4 + AlertIf(empty_sample_head(4) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(4) /= 10, "Payload Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(S7),11(S8)/22 + -- PAYLOAD MEMORY: 0(S7)/10,20 + -- ISTATE: NO_WRITERS + -- WRITER: - + + AffirmIf(status_id,(status(4) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + + Log("R4: DDS Operation TAKE [MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := TAKE; + dds.max_samples := 1; + dds.sstate := ANY_SAMPLE_STATE; + dds.istate := ANY_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + -- READER 4 + ind <= 4; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- READER 4 + AlertIf(empty_sample_head(4) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(4) /= 0, "Payload Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 11(S8)/22,0 + -- PAYLOAD MEMORY: -/0,10,20 + -- ISTATE: NO_WRITERS + -- WRITER: - + + AffirmIf(status_id,(status(4) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + + -- TEST: FILTER SAMPLE [NOT_ALIVE_NO_WRITERS INSTANCE] + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE_FILTERED; + cc.src_timestamp := gen_duration(12 sec); + + Log("R4: RTPS Operation ADD_CACHE_CHANGE [FILTERED, Writer 1]", INFO); + Log("R4: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 1; + rtps.ret_code := OK; + s := to_sample(cc,ALIVE_INSTANCE_STATE); + add_sample(s,mem(4), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + -- READER 4 + ind <= 4; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 4 + AlertIf(empty_sample_head(4) /= 0, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(4) /= 0, "Payload Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 11(S8),22(S9)/0 + -- PAYLOAD MEMORY: -/0,10,20 + -- ISTATE: ALIVE + -- WRITER: W1 + + AffirmIf(status_id,(status(4) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + + -- VALIDATE STATE + + Log("R4: DDS Operation TAKE [MAX_SAMPLES 2, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := TAKE; + dds.max_samples := 2; + dds.sstate := ANY_SAMPLE_STATE; + dds.istate := ANY_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + -- READER 4 + ind <= 4; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- READER 4 + AlertIf(empty_sample_head(4) /= 0, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(4) /= 0, "Payload Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: -/0,11,22 + -- PAYLOAD MEMORY: -/0,10,20 + -- ISTATE: ALIVE + -- WRITER: W1 + + AffirmIf(status_id,(status(4) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := NOT_ALIVE_UNREGISTERED; + cc.src_timestamp := gen_duration(13 sec); + + -- TEST: UNREGISTER SAMPLE [UNKNOWN WRITER] + + Log("R4: RTPS Operation ADD_CACHE_CHANGE [UNREGISTER, Writer 0]", INFO); + Log("R4: DROPPED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 0; + rtps.ret_code := OK; + -- READER 4 + ind <= 4; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 4 + AlertIf(empty_sample_head(4) /= 0, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(4) /= 0, "Payload Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: -/0,11,22 + -- PAYLOAD MEMORY: -/0,10,20 + -- ISTATE: ALIVE + -- WRITER: W1 + + AffirmIf(status_id,(status(4) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := NOT_ALIVE_UNREGISTERED; + cc.src_timestamp := gen_duration(14 sec); + + -- TEST: UNREGISTER SAMPLE [KNOWN WRITER] + + Log("R4: RTPS Operation ADD_CACHE_CHANGE [UNREGISTER, Writer 1]", INFO); + Log("R4: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 1; + rtps.ret_code := OK; + s := to_sample(cc,NOT_ALIVE_NO_WRITERS_INSTANCE_STATE); + add_sample(s,mem(4), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 4 + AlertIf(empty_sample_head(4) /= 11, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(4) /= 0, "Payload Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(S10)/11,22 + -- PAYLOAD MEMORY: -/0,10,20 + -- ISTATE: NO_WRITERS + -- WRITER: - + + AffirmIf(status_id,(status(4) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := NOT_ALIVE_UNREGISTERED; + cc.src_timestamp := gen_duration(15 sec); + + -- TEST: UNREGISTER SAMPLE [NOT_ALIVE_NO_WRITERS INSTANCE] + + Log("R4: RTPS Operation ADD_CACHE_CHANGE [UNREGISTER, Writer 0]", INFO); + Log("R4: DROPPED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 0; + rtps.ret_code := OK; + -- READER 4 + ind <= 4; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 4 + AlertIf(empty_sample_head(4) /= 11, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(4) /= 0, "Payload Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(S10)/11,22 + -- PAYLOAD MEMORY: -/0,10,20 + -- ISTATE: NO_WRITERS + -- WRITER: - + + AffirmIf(status_id,(status(4) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := NOT_ALIVE_DISPOSED; + cc.src_timestamp := gen_duration(16 sec); + + -- TEST: DISPOSE SAMPLE [NOT_ALIVE_NO_WRITERS INSTANCE] + + Log("R4: RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Writer 0]", INFO); + Log("R4: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 0; + rtps.ret_code := OK; + s := to_sample(cc,NOT_ALIVE_DISPOSED_INSTANCE_STATE); + add_sample(s,mem(4), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + -- READER 4 + ind <= 4; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 4 + AlertIf(empty_sample_head(4) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(4) /= 0, "Payload Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(S10),11(S11)/22 + -- PAYLOAD MEMORY: -/0,10,20 + -- ISTATE: DISPOSED + -- WRITER: W0 + + AffirmIf(status_id,(status(4) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + + -- VALIDATE STATE + + Log("R4: DDS Operation TAKE [MAX_SAMPLES 2, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := TAKE; + dds.max_samples := 2; + dds.sstate := ANY_SAMPLE_STATE; + dds.istate := ANY_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + -- READER 4 + ind <= 4; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- READER 4 + AlertIf(empty_sample_head(4) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(4) /= 0, "Payload Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: -/22,0,11 + -- PAYLOAD MEMORY: -/0,10,20 + -- ISTATE: DISPOSED + -- WRITER: W0 + + AffirmIf(status_id,(status(4) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := NOT_ALIVE_UNREGISTERED; + cc.src_timestamp := gen_duration(17 sec); + + -- TEST: UNREGISTER SAMPLE [NOT_ALIVE_DISPOSED INSTANCE] + + Log("R4: RTPS Operation ADD_CACHE_CHANGE [UNREGISTER, Writer 0]", INFO); + Log("R4: DROPPED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 0; + rtps.ret_code := OK; + -- READER 4 + ind <= 4; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 4 + AlertIf(empty_sample_head(4) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(4) /= 0, "Payload Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: -/22,0,11 + -- PAYLOAD MEMORY: -/0,10,20 + -- ISTATE: DISPOSED + -- WRITER: - + + AffirmIf(status_id,(status(4) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.payload := gen_payload(KEY_HASH_NIL,6); + cc.src_timestamp := gen_duration(18 sec); + + -- TEST: SAMPLE WITH UNALIGNED PAYLOAD [<1 SLOT] + + Log("R4: RTPS Operation ADD_CACHE_CHANGE [Writer 2, Unaligned Payload (1 Slot)]", INFO); + Log("R4: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 2; + rtps.ret_code := OK; + s := to_sample(cc,ALIVE_INSTANCE_STATE); + add_sample(s,mem(4), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + -- READER 4 + ind <= 4; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 4 + AlertIf(empty_sample_head(4) /= 0, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(4) /= 10, "Payload Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 22(S12)/0,11 + -- PAYLOAD MEMORY: 0(S12)/10,20 + -- ISTATE: ALIVE + -- WRITER: W2 + + AffirmIf(status_id,(status(4) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.payload := gen_payload(KEY_HASH_NIL,9); + cc.src_timestamp := gen_duration(19 sec); + + -- TEST: SAMPLE WITH EARLY TIMESTAMP [TIMESTAMP EARLIER THAN LAST READ] + + Log("R4: RTPS Operation ADD_CACHE_CHANGE [Writer 1, Aligned Payload]", INFO); + Log("R4: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 1; + rtps.ret_code := OK; + s := to_sample(cc,ALIVE_INSTANCE_STATE); + add_sample(s,mem(4), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + -- READER 4 + ind <= 4; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 4 + AlertIf(empty_sample_head(4) /= 11, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(4) /= 20, "Payload Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 22(S12),0(S13)/11 + -- PAYLOAD MEMORY: 0(S12),10(S13)/20 + -- ISTATE: ALIVE + -- WRITER: W1, W2 + + AffirmIf(status_id,(status(4) and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); + + -- VALIDATE STATE + + Log("R4: DDS Operation READ [MAX_SAMPLES 2, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := READ; + dds.max_samples := 2; + dds.sstate := ANY_SAMPLE_STATE; + dds.istate := ANY_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + -- READER 4 + ind <= 4; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- READER 4 + AlertIf(empty_sample_head(4) /= 11, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(4) /= 20, "Payload Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 22(S12),0(S13)/11 + -- PAYLOAD MEMORY: 0(S12),10(S13)/20 + -- ISTATE: ALIVE + -- WRITER: W1, W2 + + AffirmIf(status_id,(status(4) and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); + + wait_on_completion; + TranscriptOpen(RESULTS_FILE, APPEND_MODE); + SetTranscriptMirror; + ReportAlerts; + TranscriptClose; + std.env.stop; + wait; + end process; + + clock_prc : process + begin + clk <= '0'; + wait for 25 ns; + clk <= '1'; + wait for 25 ns; + end process; + + dds_prc : process(all) + variable col : COLLECTION_TYPE := DEFAULT_COLLECTION; + begin + if rising_edge(clk) then + dds_done <= '0'; + case (dds_stage ) is + when IDLE => + if (dds_start = '1') then + dds_stage <= START; + else + dds_done <= '1'; + end if; + when START => + if (ack_dds(ind) = '1') then + dds_stage <= DONE; + dds_cnt <= 0; + end if; + when DONE => + if (done_dds(ind) = '1') then + AffirmIfEqual(ret_id, return_code_dds(ind), dds.ret_code); + case (dds.ret_code) is + when RETCODE_OK => + gen_collection(mem(ind), col, dds, TEST_CONFIG(ind).PRESENTATION_QOS, TEST_CONFIG(ind).ORDERED_ACCESS); + dds_stage <= CHECK_SI; + dds_cnt <= 0; + when others => + dds_stage <= IDLE; + end case; + end if; + when CHECK_SI => + if (si_valid(ind) = '1') then + AffirmIfEqual(sstate_id, sample_info(ind).sample_state, col.s(dds_cnt).sstate); + AffirmIfEqual(vstate_id, sample_info(ind).view_state, col.s(dds_cnt).vstate); + AffirmIfEqual(istate_id, sample_info(ind).instance_state, col.s(dds_cnt).istate); + AffirmIfEqual(ts_id, to_unsigned(sample_info(ind).source_timestamp), to_unsigned(col.s(dds_cnt).ts)); + AffirmIfEqual(inst_id, to_unsigned(sample_info(ind).instance_handle), to_unsigned(col.s(dds_cnt).inst)); + AffirmIfEqual(pub_id, to_unsigned(sample_info(ind).publication_handle), to_unsigned(HANDLE_NIL)); + AffirmIfEqual(dis_gen_cnt_id, sample_info(ind).disposed_generation_count, std_logic_vector(to_unsigned(col.s(dds_cnt).dis_gen_cnt,WORD_WIDTH))); + AffirmIfEqual(no_w_gen_cnt_id, sample_info(ind).no_writers_generation_count, std_logic_vector(to_unsigned(col.s(dds_cnt).no_w_gen_cnt,WORD_WIDTH))); + AffirmIfEqual(srank_id, sample_info(ind).sample_rank, std_logic_vector(to_unsigned(col.s(dds_cnt).srank,WORD_WIDTH))); + AffirmIfEqual(grank_id, sample_info(ind).generation_rank, std_logic_vector(to_unsigned(col.s(dds_cnt).grank,WORD_WIDTH))); + AffirmIfEqual(agrank_id, sample_info(ind).absolute_generation_rank, std_logic_vector(to_unsigned(col.s(dds_cnt).agrank,WORD_WIDTH))); + if (sample_info(ind).valid_data = '1') then + AffirmIf(valid_id, col.s(dds_cnt).data /= EMPTY_TEST_PACKET, "Sample with Data not expected"); + dds_stage <= CHECK_DATA; + dds_cnt2 <= 0; + else + AffirmIf(valid_id, col.s(dds_cnt).data = EMPTY_TEST_PACKET, "Sample with Data expected"); + if (dds_cnt = col.len-1) then + -- DONE + dds_stage <= WAIT_EOC; + else + dds_cnt <= dds_cnt + 1; + end if; + end if; + end if; + AffirmIf(eoc_id, eoc(ind) = '0', "EOC pulled high"); + when CHECK_DATA => + if (valid_out_dds(ind) = '1') then + AffirmIfEqual(data_id, data_out_dds(ind), col.s(dds_cnt).data.data(dds_cnt2)); + dds_cnt2 <= dds_cnt2 + 1; + if (dds_cnt2 = col.s(dds_cnt).data.length-1) then + AlertIf(data_id, last_word_out_dds(ind) /= '1', "Last Word Signal not pulled High", ERROR); + if (dds_cnt = col.len-1) then + -- DONE + dds_stage <= WAIT_EOC; + else + dds_stage <= CHECK_SI; + dds_cnt <= dds_cnt + 1; + end if; + end if; + end if; + when WAIT_EOC => + if (eoc(ind) = '1') then + dds_stage <= IDLE; + end if; + end case; + end if; + + -- DEFAULT + start_dds <= (others => '0'); + opcode_dds <= (others => NOP); + instance_state_dds <= (others => ANY_INSTANCE_STATE); + view_state_dds <= (others => ANY_VIEW_STATE); + sample_state_dds <= (others => ANY_SAMPLE_STATE); + instance_handle_dds <= (others => HANDLE_NIL); + max_samples_dds <= (others => (others => '0')); + get_data_dds <= (others => '0'); + ready_out_dds <= (others => '0'); + + + case (dds_stage ) is + when START => + start_dds(ind) <= '1'; + opcode_dds(ind) <= dds.opcode; + instance_state_dds(ind) <= dds.istate; + view_state_dds(ind) <= dds.vstate; + sample_state_dds(ind) <= dds.sstate; + instance_handle_dds(ind) <= dds.inst; + max_samples_dds(ind) <= std_logic_vector(to_unsigned(dds.max_samples, WORD_WIDTH)); + when CHECK_SI => + if (si_valid(ind) = '1' and sample_info(ind).valid_data = '1') then + get_data_dds(ind) <= '1'; + end if; + when CHECK_DATA => + ready_out_dds(ind) <= '1'; + when others => + null; + end case; + end process; + + rtps_prc : process(all) + variable stimulus : TEST_PACKET_TYPE := EMPTY_TEST_PACKET; + begin + if rising_edge(clk) then + rtps_done <= '0'; + case (rtps_stage) is + when IDLE => + if (rtps_start = '1') then + rtps_stage <= START; + else + rtps_done <= '1'; + end if; + when START => + if (ack_rtps(ind) = '1') then + case (rtps.opcode) is + when ADD_CACHE_CHANGE => + gen_add_cache_change_dds(rtps.cc, rtps.lifespan, rtps.writer_pos, stimulus); + rtps_stage <= PUSH; + when others => + rtps_stage <= DONE; + end case; + end if; + when PUSH => + if (ready_in_rtps(ind) = '1') then + rtps_cnt <= rtps_cnt + 1; + if (rtps_cnt = stimulus.length-1) then + rtps_stage <= DONE; + end if; + end if; + when DONE => + if (done_rtps(ind) = '1') then + AffirmIfEqual(ret_id, HISTORY_CACHE_RESPONSE_TYPE'pos(ret_rtps(ind)), HISTORY_CACHE_RESPONSE_TYPE'pos(rtps.ret_code)); + rtps_stage <= IDLE; + end if; + end case; + end if; + + -- DEFAULT + start_rtps <= (others => '0'); + opcode_rtps <= (others => NOP); + valid_in_rtps <= (others => '0'); + last_word_in_rtps <= (others => '0'); + data_in_rtps <= (others => (others => '0')); + + case (rtps_stage) is + when START => + start_rtps(ind) <= '1'; + opcode_rtps(ind) <= rtps.opcode; + case (rtps.opcode) is + when REMOVE_WRITER => + data_in_rtps(ind) <= std_logic_vector(to_unsigned(rtps.writer_pos,WORD_WIDTH)); + when others => + null; + end case; + when PUSH => + valid_in_rtps(ind) <= '1'; + data_in_rtps(ind) <= stimulus.data(rtps_cnt); + last_word_in_rtps(ind) <= stimulus.last(rtps_cnt); + when others => + null; + end case; + end process; + + watchdog : process + begin + wait for 2 ms; + Alert("Test timeout", FAILURE); + std.env.stop; + end process; + +end architecture; \ No newline at end of file diff --git a/src/Tests/Level_0/L0_dds_reader_test1_abzkriu.vhd b/src/Tests/Level_0/L0_dds_reader_test1_abzkriu.vhd deleted file mode 100644 index 36fea19..0000000 --- a/src/Tests/Level_0/L0_dds_reader_test1_abzkriu.vhd +++ /dev/null @@ -1,1690 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library osvvm; -- Utility Library -context osvvm.OsvvmContext; - -use work.rtps_package.all; -use work.user_config.all; -use work.rtps_config_package.all; -use work.rtps_test_package.all; - --- This testbench tests the RTPS handling of the DDS Reader. It tests the correctness of the RTPS ADD_CACHE_CHANGE, and REMOVE_WRITER Operations. --- Implicitly some DDS Operations are also tested, since they are used for state checking. --- More specifically the testbench covers following tests: --- TEST: NORMAL ADD_CACHE_CHANGE --- TEST: ADD_CACHE_CHANGE ON PAYLOAD MEMORY FULL --- TEST: REMOVE_WRITER [UNKNOWN WRITER] --- TEST: REMOVE_WRITER [KNOWN WRITER (1 Instance)] --- TEST: REMOVE_WRITER [KNOWN WRITER (>1 Instances)] --- TEST: REMOVE_WRITER [NOT_ALIVE_NO_WRITERS Transition] --- TEST: REMOVE_WRITER ON MAX_SAMPLES [NOT_ALIVE_NO_WRITERS Transition] --- TEST: REMOVE_WRITER ON MAX_SAMPLES_PER_INSTANCE [NOT_ALIVE_NO_WRITERS Transition] --- TEST: REMOVE_WRITER [Multiple Pending NOT_ALIVE_NO_WRITERS Transitions] --- TEST: SAMPLE WITH ALIGNED PAYLOAD --- TEST: SAMPLE WITH UNALIGNED PAYLOAD [>1 SLOT] --- TEST: SAMPLE WITH UNALIGNED PAYLOAD [<1 SLOT] --- TEST: NORMAL SAMPLE [KNOWN INSTANCE] --- TEST: NORMAL SAMPLE [UNKNOWN INSTANCE] --- TEST: UNREGISTER SAMPLE [KNOWN INSTANCE, KNOWN WRITER] --- TEST: UNREGISTER SAMPLE [KNOWN INSTANCE, UNKNOWN WRITER] --- TEST: UNREGISTER SAMPLE [UNKNOWN INSTANCE] --- TEST: UNREGISTER SAMPLE [NOT_ALIVE_NO_WRITERS INSTANCE] --- TEST: UNREGISTER SAMPLE [NOT_ALIVE_DISPOSED INSTANCE] --- TEST: UNREGISTER SAMPLE [NOT_ALIVE_DISPOSED INSTANCE, STALE INSTANCE TRANSITION] --- TEST: DISPOSE SAMPLE [KNOWN INSTANCE] --- TEST: DISPOSE SAMPLE [UNKNOWN INSTANCE] --- TEST: DISPOSE SAMPLE [NOT_ALIVE_NO_WRITERS INSTANCE] --- TEST: DISPOSE SAMPLE [NOT_ALIVE_DISPOSED INSTANCE] --- TEST: FILTER SAMPLE [KNOWN INSTANCE] --- TEST: FILTER SAMPLE [UNKNOWN INSTANCE] --- TEST: FILTER SAMPLE [NOT_ALIVE_DISPOSED INSTANCE] --- TEST: FILTER SAMPLE [NOT_ALIVE_NO_WRITERS INSTANCE] --- TEST: SAMPLE WITH KEY_HASH --- TEST: SAMPLE WITHOUT KEY_HASH --- TEST: SAMPLE WITH SERIALIZED KEY [WITH KEY_HASH] --- TEST: SAMPLE WITH SERIALIZED KEY [WITHOUT KEY_HASH] --- TEST: SAMPLE WITH EARLY TIMESTAMP [TIMESTAMP EARLIER THAN LAST READ] --- TEST: TEST SAMPLE WITH SERIALIZED KEY EFFECT ON PAYLOAD MEMORY FULLNESS --- TEST: ADD SAMPLE ON MAX_SAMPLES_PER_INSTANCE --- TEST: ADD SAMPLE ON MAX_SAMPLES [KNOWN INSTANCE] --- TEST: ADD SAMPLE ON MAX_SAMPLES [UNKNOWN INSTANCE] --- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKOWN INSTANCE, WITH STALE INSTANCE] --- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKOWN INSTANCE, WITHOUT STALE INSTANCE] --- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKOWN INSTANCE, WITHOUT STALE INSTANCE, WITH EMPTY INSTANCE] --- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKOWN INSTANCE, NOT_ALIVE_DISPOSED & STALE INSTANCE] --- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE, WITH STALE INSTANCE] --- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE, WITHOUT STALE INSTANCE] --- TEST: ADD SAMPLE BIGGER THAN AVAILABLE MEMORY SPACE --- TEST: ADD SAMPLE ON PAYLOAD MEMORY FULL & MAX_SAMPLES_PER_INSTANCE (Induce Double Remove) - -entity L0_dds_reader_test1_abzkriu is -end entity; - - -architecture testbench of L0_dds_reader_test1_abzkriu is - - -- *CONSTANT DECLARATION* - constant MAX_REMOTE_ENDPOINTS : natural := 3; - - -- *TYPE DECLARATION* - type DDS_STAGE_TYPE is (IDLE, START, DONE, CHECK_SI, CHECK_DATA, WAIT_EOC); - type RTPS_STAGE_TYPE is (IDLE, START, PUSH, DONE); - - -- *SIGNAL DECLARATION* - signal clk : std_logic := '0'; - signal reset : std_logic := '1'; - signal check_time : TIME_TYPE := TIME_ZERO; - signal start_rtps, start_dds, ack_rtps, ack_dds, done_rtps, done_dds : std_logic := '0'; - signal opcode_rtps : HISTORY_CACHE_OPCODE_TYPE := NOP; - signal opcode_dds : DDS_READER_OPCODE_TYPE := NOP; - signal ret_rtps : HISTORY_CACHE_RESPONSE_TYPE := ERROR; - signal ready_in_rtps, valid_in_rtps, last_word_in_rtps : std_logic := '0'; - signal ready_out_dds, valid_out_dds, last_word_out_dds : std_logic := '0'; - signal data_in_rtps, data_out_dds : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); - signal get_data_dds, si_valid_data, si_valid, eoc : std_logic := '0'; - signal return_code_dds : std_logic_vector(RETURN_CODE_WIDTH-1 downto 0) := (others => '0'); - signal status : std_logic_vector(STATUS_KIND_WIDTH-1 downto 0) := (others => '0'); - signal instance_state_dds, si_instance_state : std_logic_vector(INSTANCE_STATE_KIND_WIDTH-1 downto 0) := ANY_INSTANCE_STATE; - signal view_state_dds, si_view_state : std_logic_vector(VIEW_STATE_KIND_WIDTH-1 downto 0) := ANY_VIEW_STATE; - signal sample_state_dds, si_sample_state : std_logic_vector(SAMPLE_STATE_KIND_WIDTH-1 downto 0) := ANY_SAMPLE_STATE; - signal instance_handle_dds, si_instance_handle : INSTANCE_HANDLE_TYPE := HANDLE_NIL; - signal max_samples_dds : std_logic_vector(MAX_SAMPLES_WIDTH-1 downto 0) := (others => '0'); - signal si_source_timestamp : TIME_TYPE := TIME_INVALID; - signal si_publication_handle : INSTANCE_HANDLE_TYPE := HANDLE_NIL; - signal si_disposed_generation_count : std_logic_vector(DISPOSED_GENERATION_COUNT_WIDTH-1 downto 0) := (others => '0'); - signal si_no_writers_generation_count : std_logic_vector(NO_WRITERS_GENERATION_COUNT_WIDTH-1 downto 0) := (others => '0'); - signal si_sample_rank : std_logic_vector(SAMPLE_RANK_WIDTH-1 downto 0) := (others => '0'); - signal si_generation_rank : std_logic_vector(GENERATION_RANK_WIDTH-1 downto 0) := (others => '0'); - signal si_absolute_generation_rank: std_logic_vector(ABSOLUTE_GENERATION_COUNT_WIDTH-1 downto 0) := (others => '0'); - - signal dds_start , dds_done , rtps_start, rtps_done : std_logic := '0'; - signal dds_cnt, dds_cnt2, rtps_cnt : natural := 0; - signal dds_stage : DDS_STAGE_TYPE := IDLE; - signal rtps_stage : RTPS_STAGE_TYPE := IDLE; - shared variable dds : DDS_READER_TEST_TYPE := DEFAULT_DDS_READER_TEST; - shared variable rtps : RTPS_READER_TEST_TYPE := DEFAULT_RTPS_READER_TEST; - shared variable mem : DDS_READER_MEM_TYPE := DEFAULT_DDS_READER_MEM; - signal data_id, ret_id, sstate_id, vstate_id, istate_id, inst_id, ts_id, pub_id, dis_gen_cnt_id, no_w_gen_cnt_id, srank_id, grank_id, agrank_id, eoc_id, valid_id, status_id : AlertLogIDType; - - -- *FUNCTION DECLARATION* - function extract_key_hash (payload : TEST_PACKET_TYPE) return INSTANCE_HANDLE_TYPE is - variable ret : INSTANCE_HANDLE_TYPE := HANDLE_NIL; - begin - for i in 0 to 3 loop - ret(i) := not payload.data(i); - end loop; - - return ret; - end function; - - function gen_sn(input : natural) return SEQUENCENUMBER_TYPE is - variable ret : SEQUENCENUMBER_TYPE; - begin - ret(0) := (others => '0'); - ret(1) := unsigned(int(input, WORD_WIDTH)); - return ret; - end function; - -begin - - -- Unit Under Test - uut : entity work.dds_reader(arch) - generic map ( - TIME_BASED_FILTER_QOS => DURATION_ZERO, - DEADLINE_QOS => DURATION_INFINITE, - MAX_SAMPLES => std_logic_vector(to_unsigned(4,CDR_LONG_WIDTH)), - MAX_INSTANCES => std_logic_vector(to_unsigned(3,CDR_LONG_WIDTH)), - MAX_SAMPLES_PER_INSTANCE => std_logic_vector(to_unsigned(2,CDR_LONG_WIDTH)), - HISTORY_QOS => KEEP_ALL_HISTORY_QOS, - RELIABILITY_QOS => BEST_EFFORT_RELIABILITY_QOS, - PRESENTATION_QOS => INSTANCE_PRESENTATION_QOS, - DESTINATION_ORDER_QOS => BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS, - COHERENT_ACCESS => FALSE, - ORDERED_ACCESS => FALSE, - WITH_KEY => TRUE, - PAYLOAD_FRAME_SIZE => 11, - MAX_REMOTE_ENDPOINTS => MAX_REMOTE_ENDPOINTS - ) - port map ( - clk => clk, - reset => reset, - time => check_time, - start_rtps => start_rtps, - opcode_rtps => opcode_rtps, - ack_rtps => ack_rtps, - done_rtps => done_rtps, - ret_rtps => ret_rtps, - data_in_rtps => data_in_rtps, - valid_in_rtps => valid_in_rtps, - ready_in_rtps => ready_in_rtps, - last_word_in_rtps => last_word_in_rtps, - start_dds => start_dds, - ack_dds => ack_dds, - opcode_dds => opcode_dds, - instance_state_dds => instance_state_dds, - view_state_dds => view_state_dds, - sample_state_dds => sample_state_dds, - instance_handle_dds => instance_handle_dds, - max_samples_dds => max_samples_dds, - get_data_dds => get_data_dds, - done_dds => done_dds, - return_code_dds => return_code_dds, - ready_out_dds => ready_out_dds, - valid_out_dds => valid_out_dds, - data_out_dds => data_out_dds, - last_word_out_dds => last_word_out_dds, - sample_info.sample_state => si_sample_state, - sample_info.view_state => si_view_state, - sample_info.instance_state => si_instance_state, - sample_info.source_timestamp => si_source_timestamp, - sample_info.instance_handle => si_instance_handle, - sample_info.publication_handle => si_publication_handle, - sample_info.disposed_generation_count => si_disposed_generation_count, - sample_info.no_writers_generation_count => si_no_writers_generation_count, - sample_info.sample_rank => si_sample_rank, - sample_info.generation_rank => si_generation_rank, - sample_info.absolute_generation_rank => si_absolute_generation_rank, - sample_info.valid_data => si_valid_data, - sample_info_valid => si_valid, - sample_info_ack => '1', - eoc => eoc, - status => status - ); - - stimulus_prc : process - variable RV : RandomPType; - variable cc : CACHE_CHANGE_TYPE := DEFAULT_CACHE_CHANGE; - variable s : SAMPLE_TYPE := DEFAULT_SAMPLE; - variable kh1, kh2, kh3, kh4, kh5 : INSTANCE_HANDLE_TYPE := HANDLE_NIL; - - alias idle_sig is <>; - - impure function gen_payload(key_hash : INSTANCE_HANDLE_TYPE; len : natural) return TEST_PACKET_TYPE is - variable ret : TEST_PACKET_TYPE := EMPTY_TEST_PACKET; - begin - assert (len >= 4) report "Payload length has to be at least 16 Bytes long" severity FAILURE; - - for i in 0 to len-1 loop - if (i < 4) then - -- NOTE: Beginning of payload is negated key to allow deterministic Key Hash generation from the kh_prc - ret.data(ret.length) := not key_hash(i); - else - ret.data(ret.length) := RV.RandSlv(WORD_WIDTH); - end if; - ret.length := ret.length + 1; - end loop; - ret.last(ret.length-1) := '1'; - - return ret; - end function; - - impure function gen_key_hash return KEY_HASH_TYPE is - variable ret : KEY_HASH_TYPE := KEY_HASH_NIL; - begin - for i in 0 to KEY_HASH_TYPE'length-1 loop - ret(i) := RV.RandSlv(WORD_WIDTH); - end loop; - return ret; - end function; - - procedure start_dds is - begin - dds_start <= '1'; - wait until rising_edge(clk); - dds_start <= '0'; - wait until rising_edge(clk); - end procedure; - - procedure start_rtps is - begin - rtps_start <= '1'; - wait until rising_edge(clk); - rtps_start <= '0'; - wait until rising_edge(clk); - end procedure; - - procedure wait_on_dds is - begin - if (dds_done /= '1') then - wait until dds_done = '1'; - end if; - end procedure; - - procedure wait_on_rtps is - begin - if (rtps_done /= '1') then - wait until rtps_done = '1'; - end if; - end procedure; - - procedure wait_on_completion is - begin - if (rtps_done /= '1' or dds_done /= '1') then - wait until rtps_done = '1' and dds_done = '1'; - end if; - end procedure; - - -- NOTE: This procedure waits until the idle_sig is high for at least - -- two consecutive clock cycles. - procedure wait_on_idle is - variable first : boolean := TRUE; - begin - loop - if (idle_sig /= '1') then - wait until idle_sig = '1'; - elsif (not first) then - exit; - end if; - wait until rising_edge(clk); - wait until rising_edge(clk); - first := FALSE; - end loop; - end procedure; - - begin - - SetAlertLogName("L0_dds_reader_test1_abzkriu - (KEEP ALL, Best Effort, Zero TIME_BASED_FILTER, Keyed, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER, ACCESS SCOPE Instance, Unordered) - RTPS Handling"); - SetAlertEnable(FAILURE, TRUE); - SetAlertEnable(ERROR, TRUE); - SetAlertEnable(WARNING, TRUE); - SetLogEnable(DEBUG, FALSE); - SetLogEnable(PASSED, FALSE); - SetLogEnable(INFO, TRUE); - RV.InitSeed(RV'instance_name); - sstate_id <= GetAlertLogID("Sample State", ALERTLOG_BASE_ID); - vstate_id <= GetAlertLogID("View State", ALERTLOG_BASE_ID); - istate_id <= GetAlertLogID("Instance State", ALERTLOG_BASE_ID); - ts_id <= GetAlertLogID("Source Timestamp", ALERTLOG_BASE_ID); - inst_id <= GetAlertLogID("Instance Handle", ALERTLOG_BASE_ID); - pub_id <= GetAlertLogID("Publication Hanlde", ALERTLOG_BASE_ID); - dis_gen_cnt_id <= GetAlertLogID("Disposed Generation Count", ALERTLOG_BASE_ID); - no_w_gen_cnt_id <= GetAlertLogID("No Writers Generation Count", ALERTLOG_BASE_ID); - srank_id <= GetAlertLogID("Sample Rank", ALERTLOG_BASE_ID); - grank_id <= GetAlertLogID("Generation Rank", ALERTLOG_BASE_ID); - agrank_id <= GetAlertLogID("Absolute Generation Rank", ALERTLOG_BASE_ID); - eoc_id <= GetAlertLogID("End of Collection", ALERTLOG_BASE_ID); - valid_id <= GetAlertLogID("Valid Data", ALERTLOG_BASE_ID); - data_id <= GetAlertLogID("Data Out", ALERTLOG_BASE_ID); - ret_id <= GetAlertLogID("Return Code", ALERTLOG_BASE_ID); - status_id <= GetAlertLogID("Communication Status", ALERTLOG_BASE_ID); - - -- Key Hashes - kh3 := (x"0CEAB0C6", x"FA04B9AD", x"A96EB495", x"4E0EB999"); - kh4 := (x"A7EB605C", x"FF4BEF3A", x"3C5E8724", x"CCA0CA67"); - kh2 := (x"BC070AC4", x"0BAB5811", x"14EA8D61", x"F669189B"); - kh1 := (x"F12C31DA", x"E3FE0F3F", x"01F36685", x"446518CA"); - kh5 := gen_key_hash; - - - - Log("Initiating Test", INFO); - reset <= '1'; - wait until rising_edge(clk); - wait until rising_edge(clk); - reset <= '0'; - -- MEM: 0, 0, 0, 0 - -- ISTATE: - - -- WRITER: - - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh1; - cc.payload := gen_payload(kh1,10); - cc.src_timestamp := gen_duration(1,0); - - -- TEST: NORMAL ADD_CACHE_CHANGE - -- TEST: SAMPLE WITH ALIGNED PAYLOAD - -- TEST: NORMAL SAMPLE [UNKNOWN INSTANCE] - -- TEST: SAMPLE WITH KEY_HASH - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Aligned Payload] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - rtps.ret_code := OK; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S1, 0, 0, 0 - -- ISTATE: I1:ALIVE - -- WRITER: W0:I1 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := HANDLE_NIL; - cc.payload := gen_payload(kh1,10); - cc.src_timestamp := gen_duration(2,0); - - -- TEST: SAMPLE WITHOUT KEY_HASH - -- TEST: NORMAL SAMPLE [KNOWN INSTANCE] - - Log("RTPS Operation ADD_CACHE_CHANGE [NO KEY_HASH, Instance 1, Writer 0, Aligned Payload] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - rtps.ret_code := OK; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - s.inst := kh1; - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S1, I1S2, 0, 0 - -- ISTATE: I1:ALIVE - -- WRITER: W0:I1 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh1; - cc.payload := gen_payload(kh1,18); - cc.src_timestamp := gen_duration(3,0); - - -- TEST: SAMPLE WITH UNALIGNED PAYLOAD [>1 SLOT] - -- TEST: ADD SAMPLE ON MAX_SAMPLES_PER_INSTANCE - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Unaligned Payload (2 Slots)] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - rtps.ret_code := OK; - remove_sample(0,mem); - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S2, I1S3+, 0, 0 - -- ISTATE: I1:ALIVE - -- WRITER: W0:I1 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - -- VALIDATE STATE - - Log("DDS Operation READ [MAX_SAMPLES 4, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ; - dds.max_samples := 4; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - start_dds; - wait_on_dds; - wait_on_idle; - -- MEM: I1S2, I1S3+, 0, 0 - -- ISTATE: I1:ALIVE - -- WRITER: W0:I1 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - Log("DDS Operation TAKE [MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE; - dds.max_samples := 1; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - start_dds; - wait_on_dds; - wait_on_idle; - -- MEM: I1S3+, 0, 0, 0 - -- ISTATE: I1:ALIVE - -- WRITER: W0:I1 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_DISPOSED; - cc.instance := kh1; - cc.payload := gen_payload(kh1,5); - cc.src_timestamp := gen_duration(4,0); - - -- TEST: DISPOSE SAMPLE [KNOWN INSTANCE] - -- TEST: SAMPLE WITH SERIALIZED KEY [WITH KEY_HASH] - -- TEST: SAMPLE WITH UNALIGNED PAYLOAD [<1 SLOT] - - Log("RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Instance 1, Writer 0] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - rtps.ret_code := OK; - s := to_sample(cc,NOT_ALIVE_DISPOSED_INSTANCE_STATE); - s.inst := kh1; - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S3+, I1S4-, 0, 0 - -- ISTATE: I1:DISPOSED - -- WRITER: W0:I1 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh2; - cc.payload := gen_payload(kh2,20); - cc.src_timestamp := gen_duration(5,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 2, Writer 1, Aligned Payload (2 Slots)] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 1; - rtps.ret_code := OK; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S3+, I1S4-, I2S1+, 0 - -- ISTATE: I1:DISPOSED, I2:ALIVE - -- WRITER: W0:I1, W1:I2 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh3; - cc.payload := gen_payload(kh3,10); - cc.src_timestamp := gen_duration(6,0); - - -- TEST: TEST SAMPLE WITH SERIALIZED KEY EFFECT ON PAYLOAD MEMORY FULLNESS - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 3, Writer 1, Aligned Payload] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 1; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S3+, I1S4-, I2S1+, I3S1 - -- ISTATE: I1:DISPOSED, I2:ALIVE, I3:ALIVE - -- WRITER: W0:I1, W1:I2,I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - -- TEST: REMOVE_WRITER [UNKNOWN WRITER] - - Log("RTPS Operation REMOVE_WRITER [Writer 2] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := REMOVE_WRITER; - rtps.writer_pos := 2; - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S3+, I1S4-, I2S1+, I3S1 - -- ISTATE: I1:DISPOSED, I2:ALIVE, I3:ALIVE - -- WRITER: W0:I1, W1:I2,I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - Log("DDS Operation TAKE [MAX_SAMPLES 1, NOT_READ_SAMPLE_STATE, NOT_ALIVE_DISPOSED_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE; - dds.max_samples := 1; - dds.sstate := NOT_READ_SAMPLE_STATE; - dds.istate := NOT_ALIVE_DISPOSED_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - start_dds; - wait_on_dds; - wait_on_idle; - -- MEM: I1S3+, I2S1+, I3S1, 0 - -- ISTATE: I1:DISPOSED, I2:ALIVE, I3:ALIVE - -- WRITER: W0:I1, W1:I2,I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh3; - cc.payload := gen_payload(kh3,10); - cc.src_timestamp := gen_duration(7,0); - - -- TEST: ADD_CACHE_CHANGE ON PAYLOAD MEMORY FULL - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 3, Writer 2, Aligned Payload] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 2; - remove_sample(0,mem); - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I2S1+, I3S1, I3S2, 0 - -- ISTATE: I1:DISPOSED, I2:ALIVE, I3:ALIVE - -- WRITER: W0:I1, W1:I2,I3, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh4; - cc.payload := gen_payload(kh4,10); - cc.src_timestamp := gen_duration(8,0); - - -- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKOWN INSTANCE, WITHOUT STALE INSTANCE, WITH EMPTY INSTANCE] - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 4, Writer 1, Aligned Payload] (REJECTED: MAX_INSTANCES exceeded)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 1; - rtps.ret_code := REJECTED; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I2S1+, I3S1, I3S2, 0 - -- ISTATE: I1:DISPOSED, I2:ALIVE, I3:ALIVE - -- WRITER: W0:I1, W1:I2,I3, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - -- TEST: REMOVE_WRITER [KNOWN WRITER (1 Instance)] - - Log("RTPS Operation REMOVE_WRITER [Writer 0] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := REMOVE_WRITER; - rtps.writer_pos := 0; - change_istate(kh1, NOT_ALIVE_NO_WRITERS_INSTANCE_STATE, mem); - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I2S1+, I3S1, I3S2, 0 - -- ISTATE: I1:DISPOSED, I2:ALIVE, I3:ALIVE - -- WRITER: W1:I2,I3, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - -- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKOWN INSTANCE, WITH STALE INSTANCE] - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 4, Writer 1, Aligned Payload] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 1; - remove_inst(kh1, mem); - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I2S1+, I3S1, I3S2, I4S1 - -- ISTATE: I2:ALIVE, I3:ALIVE, I4:ALIVE - -- WRITER: W1:I2,I3,I4, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - -- VALIDATE STATE - - Log("DDS Operation READ [MAX_SAMPLES 4, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ; - dds.max_samples := 4; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - start_dds; - wait_on_dds; - wait_on_idle; - -- MEM: I2S1+, I3S1, I3S2, I4S1 - -- ISTATE: I2:ALIVE, I3:ALIVE, I4:ALIVE - -- WRITER: W1:I2,I3,I4, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - Log("DDS Operation TAKE [MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE; - dds.max_samples := 1; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - start_dds; - wait_on_dds; - wait_on_idle; - -- MEM: I3S1, I3S2, I4S1, 0 - -- ISTATE: I2:ALIVE, I3:ALIVE, I4:ALIVE - -- WRITER: W1:I2,I3,I4, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh1; - cc.payload := gen_payload(kh1,10); - cc.src_timestamp := gen_duration(9,0); - - -- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKOWN INSTANCE, WITHOUT STALE INSTANCE] - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Aligned Payload] (REJECTED: MAX_INSTANCES exceeded)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - rtps.ret_code := REJECTED; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I3S1, I3S2, I4S1, 0 - -- ISTATE: I2:ALIVE, I3:ALIVE, I4:ALIVE - -- WRITER: W1:I2,I3,I4, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh4; - cc.payload := gen_payload(kh4,10); - cc.src_timestamp := gen_duration(10,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 4, Writer 1, Aligned Payload] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 1; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I3S1, I3S2, I4S1, I4S2 - -- ISTATE: I2:ALIVE, I3:ALIVE, I4:ALIVE - -- WRITER: W1:I2,I3,I4, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh1; - cc.payload := gen_payload(kh1,10); - cc.src_timestamp := gen_duration(11,0); - - -- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE, WITHOUT STALE INSTANCE] - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Aligned Payload] (REJECTED: MAX_INSTANCES exceeded)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - rtps.ret_code := REJECTED; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I3S1, I3S2, I4S1, I4S2 - -- ISTATE: I2:ALIVE, I3:ALIVE, I4:ALIVE - -- WRITER: W1:I2,I3,I4, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - Log("DDS Operation READ [MAX_SAMPLES 4, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ; - dds.max_samples := 4; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - start_dds; - wait_on_dds; - wait_on_idle; - -- MEM: I3S1, I3S2, I4S1, I4S2 - -- ISTATE: I2:ALIVE, I3:ALIVE, I4:ALIVE - -- WRITER: W1:I2,I3,I4, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - -- TEST: REMOVE_WRITER [KNOWN WRITER (>1 Instances)] - -- TEST: REMOVE_WRITER [NOT_ALIVE_NO_WRITERS Transition] - -- TEST: REMOVE_WRITER ON MAX_SAMPLES [NOT_ALIVE_NO_WRITERS Transition] - -- TEST: REMOVE_WRITER ON MAX_SAMPLES_PER_INSTANCE [NOT_ALIVE_NO_WRITERS Transition] - -- TEST: REMOVE_WRITER [Multiple Pending NOT_ALIVE_NO_WRITERS Transitions] - - Log("RTPS Operation REMOVE_WRITER [Writer 1] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := REMOVE_WRITER; - rtps.writer_pos := 1; - remove_sample(0,mem); - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_UNREGISTERED; - cc.instance := kh2; - cc.src_timestamp := check_time; - s := to_sample(cc,NOT_ALIVE_NO_WRITERS_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - remove_sample(1,mem); - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_UNREGISTERED; - cc.instance := kh4; - cc.src_timestamp := check_time; - s := to_sample(cc,NOT_ALIVE_NO_WRITERS_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I3S2, I4S2, I2S2-, I4S3- - -- ISTATE: I2:NO_WRITERS, I3:ALIVE, I4:NO_WRITERS - -- WRITER: W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - Log("DDS Operation TAKE_INSTANCE [Instance 2, MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE_INSTANCE; - dds.max_samples := 1; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.inst := kh2; - start_dds; - wait_on_dds; - wait_on_idle; - -- MEM: I3S2, I4S2, I4S3-, 0 - -- ISTATE: I2:NO_WRITERS, I3:ALIVE, I4:NO_WRITERS - -- WRITER: W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh3; - cc.payload := gen_payload(kh3,10); - cc.src_timestamp := gen_duration(12,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 3, Writer 2, Aligned Payload] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 2; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I3S2, I4S2, I4S3-, I3S3 - -- ISTATE: I2:NO_WRITERS, I3:ALIVE, I4:NO_WRITERS - -- WRITER: W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - Log("DDS Operation READ [MAX_SAMPLES 4, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ; - dds.max_samples := 4; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - start_dds; - wait_on_dds; - wait_on_idle; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh1; - cc.payload := gen_payload(kh1,10); - cc.src_timestamp := gen_duration(13,0); - - -- TEST: ADD SAMPLE ON MAX_SAMPLES [UNKNOWN INSTANCE] - -- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE, WITH STALE INSTANCE] - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Aligned Payload] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - remove_inst(kh2,mem); - remove_sample(0,mem); - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I4S2, I4S3-, I3S3, I1S1 - -- ISTATE: I1:ALIVE, I3:ALIVE, I4:NO_WRITERS - -- WRITER: W0:I1, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh3; - cc.payload := gen_payload(kh3,10); - cc.src_timestamp := gen_duration(14,0); - - -- TEST: ADD SAMPLE ON MAX_SAMPLES [KNOWN INSTANCE] - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 3, Writer 2, Aligned Payload] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 2; - remove_sample(0,mem); - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I4S3-, I3S3, I1S1, I3S4 - -- ISTATE: I1:ALIVE, I3:ALIVE, I4:NO_WRITERS - -- WRITER: W0:I1, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - -- VALIDATE STATE - - Log("DDS Operation READ [MAX_SAMPLES 4, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ; - dds.max_samples := 4; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - start_dds; - wait_on_dds; - wait_on_idle; - -- MEM: I4S3-, I3S3, I1S1, I3S4 - -- ISTATE: I1:ALIVE, I3:ALIVE, I4:NO_WRITERS - -- WRITER: W0:I1, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh1; - cc.payload := gen_payload(kh1,10); - cc.src_timestamp := gen_duration(15,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Aligned Payload] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - remove_sample(0,mem); - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I3S3, I1S1, I3S4, I1S2 - -- ISTATE: I1:ALIVE, I3:ALIVE, I4:NO_WRITERS - -- WRITER: W0:I1, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh1; - cc.payload := gen_payload(kh1,10); - cc.src_timestamp := gen_duration(16,0); - - -- TEST: ADD SAMPLE ON PAYLOAD MEMORY FULL & MAX_SAMPLES_PER_INSTANCE (Induce Double Remove) - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Aligned Payload] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - remove_sample(1,mem); - remove_sample(0,mem); - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I3S4, I1S2, I1S3, 0 - -- ISTATE: I1:ALIVE, I3:ALIVE, I4:NO_WRITERS - -- WRITER: W0:I1, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh3; - cc.payload := gen_payload(kh3,30); - cc.src_timestamp := gen_duration(17,0); - - -- TEST: ADD SAMPLE BIGGER THAN AVAILABLE MEMORY SPACE - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 3, Writer 0, Aligned Payload (3 Slots)] (REJECTED: Payload memory Full)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - rtps.ret_code := REJECTED; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I3S4, I1S2, I1S3, 0 - -- ISTATE: I1:ALIVE, I3:ALIVE, I4:NO_WRITERS - -- WRITER: W0:I1, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_DISPOSED; - cc.instance := HANDLE_NIL; - cc.payload := gen_payload(kh4,5); - cc.src_timestamp := gen_duration(18,0); - - -- TEST: DISPOSE SAMPLE [NOT_ALIVE_NO_WRITERS INSTANCE] - -- TEST: SAMPLE WITH SERIALIZED KEY [WITHOUT KEY_HASH] - - Log("RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Instance 4, Writer 1] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 1; - s := to_sample(cc,NOT_ALIVE_DISPOSED_INSTANCE_STATE); - s.inst := kh4; - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I3S4, I1S2, I1S3, I4S4- - -- ISTATE: I1:ALIVE, I3:ALIVE, I4:DISPOSED - -- WRITER: W0:I1, W1:I4, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - -- VALIDATE STATE - - Log("DDS Operation TAKE [MAX_SAMPLES 4, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE; - dds.max_samples := 4; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - start_dds; - wait_on_dds; - wait_on_idle; - -- MEM: 0, 0, 0, 0 - -- ISTATE: I1:ALIVE, I3:ALIVE, I4:DISPOSED - -- WRITER: W0:I1, W1:I4, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_DISPOSED; - cc.instance := kh4; - cc.payload := gen_payload(kh4,5); - cc.src_timestamp := gen_duration(19,0); - - -- TEST: DISPOSE SAMPLE [NOT_ALIVE_DISPOSED INSTANCE] - - Log("RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Instance 4, Writer 0] (IGNORED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: 0, 0, 0, 0 - -- ISTATE: I1:ALIVE, I3:ALIVE, I4:DISPOSED - -- WRITER: W0:I1,I4 W1:I4, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_UNREGISTERED; - cc.instance := kh4; - cc.payload := gen_payload(kh4,5); - cc.src_timestamp := gen_duration(20,0); - - -- TEST: UNREGISTER SAMPLE [KNOWN INSTANCE, KNOWN WRITER] - -- TEST: UNREGISTER SAMPLE [NOT_ALIVE_DISPOSED INSTANCE] - - Log("RTPS Operation ADD_CACHE_CHANGE [UNREGISTER, Instance 4, Writer 0] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: 0, 0, 0, 0 - -- ISTATE: I1:ALIVE, I3:ALIVE, I4:DISPOSED - -- WRITER: W0:I1, W1:I4, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_UNREGISTERED; - cc.instance := kh1; - cc.payload := gen_payload(kh1,5); - cc.src_timestamp := gen_duration(21,0); - - -- TEST: UNREGISTER SAMPLE [KNOWN INSTANCE, UNKNOWN WRITER] - - Log("RTPS Operation ADD_CACHE_CHANGE [UNREGISTER, Instance 1, Writer 1] (IGNORED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 1; - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: 0, 0, 0, 0 - -- ISTATE: I1:ALIVE, I3:ALIVE, I4:DISPOSED - -- WRITER: W0:I1, W1:I4, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_UNREGISTERED; - cc.instance := kh2; - cc.payload := gen_payload(kh2,5); - cc.src_timestamp := gen_duration(22,0); - - -- TEST: UNREGISTER SAMPLE [UNKNOWN INSTANCE] - - Log("RTPS Operation ADD_CACHE_CHANGE [UNREGISTER, Instance 2, Writer 1] (IGNORED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 1; - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: 0, 0, 0, 0 - -- ISTATE: I1:ALIVE, I3:ALIVE, I4:DISPOSED - -- WRITER: W0:I1, W1:I4, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_UNREGISTERED; - cc.instance := kh1; - cc.payload := gen_payload(kh1,5); - cc.src_timestamp := gen_duration(23,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [UNREGISTER, Instance 1, Writer 0] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - s := to_sample(cc,NOT_ALIVE_NO_WRITERS_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S4-, 0, 0, 0 - -- ISTATE: I1:NO_WRITERS, I3:ALIVE, I4:DISPOSED - -- WRITER: W1:I4, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_UNREGISTERED; - cc.instance := kh1; - cc.payload := gen_payload(kh1,5); - cc.src_timestamp := gen_duration(24,0); - - -- TEST: UNREGISTER SAMPLE [NOT_ALIVE_NO_WRITERS INSTANCE] - - Log("RTPS Operation ADD_CACHE_CHANGE [UNREGISTER, Instance 1, Writer 2] (IGNORED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 2; - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S4-, 0, 0, 0 - -- ISTATE: I1:NO_WRITERS, I3:ALIVE, I4:DISPOSED - -- WRITER: W1:I4, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := ALIVE_FILTERED; - cc.instance := kh1; - cc.payload := gen_payload(kh1,5); - cc.src_timestamp := gen_duration(25,0); - - -- TEST: FILTER SAMPLE [KNOWN INSTANCE] - -- TEST: FILTER SAMPLE [NOT_ALIVE_NO_WRITERS INSTANCE] - - Log("RTPS Operation ADD_CACHE_CHANGE [FILTERED, Instance 1, Writer 2] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - rtps.writer_pos := 2; - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S4-, I1S5-, 0, 0 - -- ISTATE: I1:ALIVE, I3:ALIVE, I4:DISPOSED - -- WRITER: W1:I4, W2:I1,I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_UNREGISTERED; - cc.instance := kh4; - cc.payload := gen_payload(kh1,5); - cc.src_timestamp := gen_duration(26,0); - - -- TEST: UNREGISTER SAMPLE [NOT_ALIVE_DISPOSED INSTANCE, STALE INSTANCE TRANSITION] - - Log("RTPS Operation ADD_CACHE_CHANGE [UNREGISTER, Instance 4, Writer 1] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 1; - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S4-, I1S5-, 0, 0 - -- ISTATE: I1:ALIVE, I3:ALIVE, I4:DISPOSED - -- WRITER: W2:I1,I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh2; - cc.payload := gen_payload(kh2,10); - cc.src_timestamp := gen_duration(27,0); - - -- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKOWN INSTANCE, NOT_ALIVE_DISPOSED & STALE INSTANCE] - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 2, Writer 0, Aligned Payload] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - remove_inst(kh4, mem); - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S4-, I1S5-, I2S1, 0 - -- ISTATE: I1:ALIVE, I2:ALIVE, I3:ALIVE - -- WRITER: W0:I2, W2:I1,I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - -- VALIDATE STATE - - Log("DDS Operation TAKE [MAX_SAMPLES 4, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE; - dds.max_samples := 4; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - start_dds; - wait_on_dds; - wait_on_idle; - -- MEM: 0, 0, 0, 0 - -- ISTATE: I1:ALIVE, I2:ALIVE, I3:ALIVE - -- WRITER: W0:I2, W2:I1,I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_DISPOSED; - cc.instance := kh1; - cc.payload := gen_payload(kh1,5); - cc.src_timestamp := gen_duration(28,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Instance 1, Writer 2] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 2; - s := to_sample(cc,NOT_ALIVE_DISPOSED_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S6-, 0, 0, 0 - -- ISTATE: I1:DISPOSED, I2:ALIVE, I3:ALIVE - -- WRITER: W0:I2, W2:I1,I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := ALIVE_FILTERED; - cc.instance := kh1; - cc.payload := gen_payload(kh1,5); - cc.src_timestamp := gen_duration(29,0); - - -- TEST: FILTER SAMPLE [NOT_ALIVE_DISPOSED INSTANCE] - - Log("RTPS Operation ADD_CACHE_CHANGE [FILTERED, Instance 1, Writer 2] (ACCEPT)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - rtps.writer_pos := 2; - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S6-, I1S7-, 0, 0 - -- ISTATE: I1:ALIVE, I2:ALIVE, I3:ALIVE - -- WRITER: W0:I2, W2:I1,I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := ALIVE_FILTERED; - cc.instance := kh4; - cc.payload := gen_payload(kh4,5); - cc.src_timestamp := gen_duration(30,0); - - -- TEST: FILTER SAMPLE [UNKNOWN INSTANCE] - - Log("RTPS Operation ADD_CACHE_CHANGE [FILTERED, Instance 4, Writer 1] (IGNORED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 1; - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S6-, I1S7-, 0, 0 - -- ISTATE: I1:ALIVE, I2:ALIVE, I3:ALIVE - -- WRITER: W0:I2, W2:I1,I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh3; - cc.payload := gen_payload(kh3,10); - cc.src_timestamp := gen_duration(10,0); - - -- TEST: SAMPLE WITH EARLY TIMESTAMP [TIMESTAMP EARLIER THAN LAST READ] - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 3, Writer 2, Aligned Payload] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 2; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S6-, I1S7-, I3S5, 0 - -- ISTATE: I1:ALIVE, I2:ALIVE, I3:ALIVE - -- WRITER: W0:I2, W2:I1,I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_UNREGISTERED; - cc.instance := kh2; - cc.payload := gen_payload(kh2,5); - cc.src_timestamp := gen_duration(31,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [UNREGISTER, Instance 2, Writer 0] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - s := to_sample(cc,NOT_ALIVE_NO_WRITERS_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S6-, I1S7-, I3S5, I2S2- - -- ISTATE: I1:ALIVE, I2:NO_WRITERS, I3: ALIVE - -- WRITER: W2:I1,I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - -- VALIDATE STATE - - Log("DDS Operation TAKE [MAX_SAMPLES 4, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE; - dds.max_samples := 4; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - start_dds; - wait_on_dds; - wait_on_idle; - -- MEM: 0, 0, 0, 0 - -- ISTATE: I1:ALIVE, I2:NO_WRITERS, I3: ALIVE - -- WRITER: W2:I1,I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_DISPOSED; - cc.instance := kh4; - cc.payload := gen_payload(kh4,5); - cc.src_timestamp := gen_duration(32,0); - - -- TEST: DISPOSE SAMPLE [UNKNOWN INSTANCE] - - Log("RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Instance 4, Writer 1] (ACCPETED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 1; - s := to_sample(cc,NOT_ALIVE_DISPOSED_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I4S1-, 0, 0, 0 - -- ISTATE: I1:ALIVE, I3: ALIVE, I4:DISPOSED - -- WRITER: W1:I4, W2:I1,I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - -- VALIDATE STATE - - Log("DDS Operation READ [MAX_SAMPLES 4, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE; - dds.max_samples := 4; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := NOT_ALIVE_DISPOSED_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - start_dds; - wait_on_dds; - wait_on_idle; - -- MEM: I4S1-, 0, 0, 0 - -- ISTATE: I1:ALIVE, I3: ALIVE, I4:DISPOSED - -- WRITER: W1:I4, W2:I1,I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - wait_on_completion; - TranscriptOpen(RESULTS_FILE, APPEND_MODE); - SetTranscriptMirror; - ReportAlerts; - TranscriptClose; - std.env.stop; - wait; - end process; - - clock_prc : process - begin - clk <= '0'; - wait for 25 ns; - clk <= '1'; - wait for 25 ns; - end process; - - alert_prc : process(all) - begin - if rising_edge(clk) then - -- TODO - end if; - end process; - - dds_prc : process(all) - variable col : COLLECTION_TYPE := DEFAULT_COLLECTION; - begin - if rising_edge(clk) then - dds_done <= '0'; - case (dds_stage ) is - when IDLE => - if (dds_start = '1') then - dds_stage <= START; - else - dds_done <= '1'; - end if; - when START => - if (ack_dds = '1') then - dds_stage <= DONE; - dds_cnt <= 0; - end if; - when DONE => - if (done_dds = '1') then - AffirmIfEqual(ret_id, return_code_dds, dds.ret_code); - case (dds.ret_code) is - when RETCODE_OK => - gen_collection(mem, col, dds, INSTANCE_PRESENTATION_QOS, FALSE); - dds_stage <= CHECK_SI; - dds_cnt <= 0; - when others => - dds_stage <= IDLE; - end case; - end if; - when CHECK_SI => - if (si_valid = '1') then - AffirmIfEqual(sstate_id, si_sample_state, col.s(dds_cnt).sstate); - AffirmIfEqual(vstate_id, si_view_state, col.s(dds_cnt).vstate); - AffirmIfEqual(istate_id, si_instance_state, col.s(dds_cnt).istate); - AffirmIfEqual(ts_id, to_unsigned(si_source_timestamp), to_unsigned(col.s(dds_cnt).ts)); - AffirmIfEqual(inst_id, to_unsigned(si_instance_handle), to_unsigned(col.s(dds_cnt).inst)); - AffirmIfEqual(pub_id, to_unsigned(si_publication_handle), to_unsigned(HANDLE_NIL)); - AffirmIfEqual(dis_gen_cnt_id, si_disposed_generation_count, std_logic_vector(to_unsigned(col.s(dds_cnt).dis_gen_cnt,WORD_WIDTH))); - AffirmIfEqual(no_w_gen_cnt_id, si_no_writers_generation_count, std_logic_vector(to_unsigned(col.s(dds_cnt).no_w_gen_cnt,WORD_WIDTH))); - AffirmIfEqual(srank_id, si_sample_rank, std_logic_vector(to_unsigned(col.s(dds_cnt).srank,WORD_WIDTH))); - AffirmIfEqual(grank_id, si_generation_rank, std_logic_vector(to_unsigned(col.s(dds_cnt).grank,WORD_WIDTH))); - AffirmIfEqual(agrank_id, si_absolute_generation_rank, std_logic_vector(to_unsigned(col.s(dds_cnt).agrank,WORD_WIDTH))); - if (si_valid_data = '1') then - AffirmIf(valid_id, col.s(dds_cnt).data /= EMPTY_TEST_PACKET, "Sample with Data not expected"); - dds_stage <= CHECK_DATA; - dds_cnt2 <= 0; - else - AffirmIf(valid_id, col.s(dds_cnt).data = EMPTY_TEST_PACKET, "Sample with Data expected"); - if (dds_cnt = col.len-1) then - -- DONE - dds_stage <= WAIT_EOC; - else - dds_cnt <= dds_cnt + 1; - end if; - end if; - end if; - AffirmIf(eoc_id, eoc = '0', "EOC pulled high"); - when CHECK_DATA => - if (valid_out_dds = '1') then - AffirmIfEqual(data_id, data_out_dds, col.s(dds_cnt).data.data(dds_cnt2)); - dds_cnt2 <= dds_cnt2 + 1; - if (dds_cnt2 = col.s(dds_cnt).data.length-1) then - AlertIf(data_id, last_word_out_dds /= '1', "Last Word Signal not pulled High", ERROR); - if (dds_cnt = col.len-1) then - -- DONE - dds_stage <= WAIT_EOC; - else - dds_stage <= CHECK_SI; - dds_cnt <= dds_cnt + 1; - end if; - end if; - end if; - when WAIT_EOC => - if (eoc = '1') then - dds_stage <= IDLE; - end if; - end case; - end if; - - -- DEFAULT - start_dds <= '0'; - opcode_dds <= NOP; - instance_state_dds <= ANY_INSTANCE_STATE; - view_state_dds <= ANY_VIEW_STATE; - sample_state_dds <= ANY_SAMPLE_STATE; - instance_handle_dds <= HANDLE_NIL; - max_samples_dds <= (others => '0'); - get_data_dds <= '0'; - ready_out_dds <= '0'; - - - case (dds_stage ) is - when START => - start_dds <= '1'; - opcode_dds <= dds.opcode; - instance_state_dds <= dds.istate; - view_state_dds <= dds.vstate; - sample_state_dds <= dds.sstate; - instance_handle_dds <= dds.inst; - max_samples_dds <= std_logic_vector(to_unsigned(dds.max_samples, WORD_WIDTH)); - when CHECK_SI => - if (si_valid = '1' and si_valid_data = '1') then - get_data_dds <= '1'; - end if; - when CHECK_DATA => - ready_out_dds <= '1'; - when others => - null; - end case; - end process; - - rtps_prc : process(all) - variable stimulus : TEST_PACKET_TYPE := EMPTY_TEST_PACKET; - begin - if rising_edge(clk) then - rtps_done <= '0'; - case (rtps_stage) is - when IDLE => - if (rtps_start = '1') then - rtps_stage <= START; - else - rtps_done <= '1'; - end if; - when START => - if (ack_rtps = '1') then - case (rtps.opcode) is - when ADD_CACHE_CHANGE => - gen_add_cache_change_dds(rtps.cc, rtps.lifespan, rtps.writer_pos, stimulus); - rtps_stage <= PUSH; - when others => - rtps_stage <= DONE; - end case; - end if; - when PUSH => - if (ready_in_rtps = '1') then - rtps_cnt <= rtps_cnt + 1; - if (rtps_cnt = stimulus.length-1) then - rtps_stage <= DONE; - end if; - end if; - when DONE => - if (done_rtps = '1') then - AffirmIfEqual(ret_id, HISTORY_CACHE_RESPONSE_TYPE'pos(ret_rtps), HISTORY_CACHE_RESPONSE_TYPE'pos(rtps.ret_code)); - rtps_stage <= IDLE; - end if; - end case; - end if; - - -- DEFAULT - start_rtps <= '0'; - opcode_rtps <= NOP; - valid_in_rtps <= '0'; - last_word_in_rtps <= '0'; - data_in_rtps <= (others => '0'); - - case (rtps_stage) is - when START => - start_rtps <= '1'; - opcode_rtps <= rtps.opcode; - case (rtps.opcode) is - when REMOVE_WRITER => - data_in_rtps <= std_logic_vector(to_unsigned(rtps.writer_pos,WORD_WIDTH)); - when others => - null; - end case; - when PUSH => - valid_in_rtps <= '1'; - data_in_rtps <= stimulus.data(rtps_cnt); - last_word_in_rtps <= stimulus.last(rtps_cnt); - when others => - null; - end case; - end process; - - watchdog : process - begin - wait for 1 ms; - Alert("Test timeout", FAILURE); - std.env.stop; - end process; - -end architecture; \ No newline at end of file diff --git a/src/Tests/Level_0/L0_dds_reader_test1_arzkriu.vhd b/src/Tests/Level_0/L0_dds_reader_test1_arzkriu.vhd deleted file mode 100644 index b8c4a65..0000000 --- a/src/Tests/Level_0/L0_dds_reader_test1_arzkriu.vhd +++ /dev/null @@ -1,1696 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library osvvm; -- Utility Library -context osvvm.OsvvmContext; - -use work.rtps_package.all; -use work.user_config.all; -use work.rtps_config_package.all; -use work.rtps_test_package.all; - --- This testbench tests the RTPS handling of the DDS Reader. It tests the correctness of the RTPS ADD_CACHE_CHANGE, and REMOVE_WRITER Operations. --- Implicitly some DDS Operations are also tested, since they are used for state checking. --- More specifically the testbench covers following tests: --- TEST: NORMAL ADD_CACHE_CHANGE --- TEST: ADD_CACHE_CHANGE ON PAYLOAD MEMORY FULL --- TEST: REMOVE_WRITER [UNKNOWN WRITER] --- TEST: REMOVE_WRITER [KNOWN WRITER (1 Instance)] --- TEST: REMOVE_WRITER [KNOWN WRITER (>1 Instances)] --- TEST: REMOVE_WRITER [NOT_ALIVE_NO_WRITERS Transition] --- TEST: REMOVE_WRITER [Multiple Pending NOT_ALIVE_NO_WRITERS Transitions] --- TEST: REMOVE_WRITER ON MAX_SAMPLES [NOT_ALIVE_NO_WRITERS Transition] --- TEST: REMOVE_WRITER ON MAX_SAMPLES_PER_INSTANCE [NOT_ALIVE_NO_WRITERS Transition] --- TEST: SAMPLE WITH ALIGNED PAYLOAD --- TEST: SAMPLE WITH UNALIGNED PAYLOAD [>1 SLOT] --- TEST: SAMPLE WITH UNALIGNED PAYLOAD [<1 SLOT] --- TEST: NORMAL SAMPLE [KNOWN INSTANCE] --- TEST: NORMAL SAMPLE [UNKNOWN INSTANCE] --- TEST: UNREGISTER SAMPLE [KNOWN INSTANCE, KNOWN WRITER] --- TEST: UNREGISTER SAMPLE [KNOWN INSTANCE, UNKNOWN WRITER] --- TEST: UNREGISTER SAMPLE [UNKNOWN INSTANCE] --- TEST: UNREGISTER SAMPLE [NOT_ALIVE_NO_WRITERS INSTANCE] --- TEST: UNREGISTER SAMPLE [NOT_ALIVE_DISPOSED INSTANCE] --- TEST: UNREGISTER SAMPLE [NOT_ALIVE_DISPOSED INSTANCE, STALE INSTANCE TRANSITION] --- TEST: DISPOSE SAMPLE [KNOWN INSTANCE] --- TEST: DISPOSE SAMPLE [UNKNOWN INSTANCE] --- TEST: DISPOSE SAMPLE [NOT_ALIVE_NO_WRITERS INSTANCE] --- TEST: DISPOSE SAMPLE [NOT_ALIVE_DISPOSED INSTANCE] --- TEST: FILTER SAMPLE [KNOWN INSTANCE] --- TEST: FILTER SAMPLE [UNKNOWN INSTANCE] --- TEST: FILTER SAMPLE [NOT_ALIVE_DISPOSED INSTANCE] --- TEST: FILTER SAMPLE [NOT_ALIVE_NO_WRITERS INSTANCE] --- TEST: SAMPLE WITH KEY_HASH --- TEST: SAMPLE WITHOUT KEY_HASH --- TEST: SAMPLE WITH SERIALIZED KEY [WITH KEY_HASH] --- TEST: SAMPLE WITH SERIALIZED KEY [WITHOUT KEY_HASH] --- TEST: SAMPLE WITH EARLY TIMESTAMP [TIMESTAMP EARLIER THAN LAST READ] --- TEST: TEST SAMPLE WITH SERIALIZED KEY EFFECT ON PAYLOAD MEMORY FULLNESS --- TEST: ADD SAMPLE ON MAX_SAMPLES_PER_INSTANCE --- TEST: ADD SAMPLE ON MAX_SAMPLES [KNOWN INSTANCE] --- TEST: ADD SAMPLE ON MAX_SAMPLES [UNKNOWN INSTANCE] --- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKOWN INSTANCE, WITH STALE INSTANCE] --- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKOWN INSTANCE, WITHOUT STALE INSTANCE] --- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKOWN INSTANCE, WITHOUT STALE INSTANCE, WITH EMPTY INSTANCE] --- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKOWN INSTANCE, NOT_ALIVE_DISPOSED & STALE INSTANCE] --- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE, WITH STALE INSTANCE] --- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE, WITHOUT STALE INSTANCE] --- TEST: ADD SAMPLE BIGGER THAN AVAILABLE MEMORY SPACE - -entity L0_dds_reader_test1_arzkriu is -end entity; - - -architecture testbench of L0_dds_reader_test1_arzkriu is - - -- *CONSTANT DECLARATION* - constant MAX_REMOTE_ENDPOINTS : natural := 3; - - -- *TYPE DECLARATION* - type DDS_STAGE_TYPE is (IDLE, START, DONE, CHECK_SI, CHECK_DATA, WAIT_EOC); - type RTPS_STAGE_TYPE is (IDLE, START, PUSH, DONE); - - -- *SIGNAL DECLARATION* - signal clk : std_logic := '0'; - signal reset : std_logic := '1'; - signal check_time : TIME_TYPE := TIME_ZERO; - signal start_rtps, start_dds, ack_rtps, ack_dds, done_rtps, done_dds : std_logic := '0'; - signal opcode_rtps : HISTORY_CACHE_OPCODE_TYPE := NOP; - signal opcode_dds : DDS_READER_OPCODE_TYPE := NOP; - signal ret_rtps : HISTORY_CACHE_RESPONSE_TYPE := ERROR; - signal ready_in_rtps, valid_in_rtps, last_word_in_rtps : std_logic := '0'; - signal ready_out_dds, valid_out_dds, last_word_out_dds : std_logic := '0'; - signal data_in_rtps, data_out_dds : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); - signal get_data_dds, si_valid_data, si_valid, eoc : std_logic := '0'; - signal return_code_dds : std_logic_vector(RETURN_CODE_WIDTH-1 downto 0) := (others => '0'); - signal status : std_logic_vector(STATUS_KIND_WIDTH-1 downto 0) := (others => '0'); - signal instance_state_dds, si_instance_state : std_logic_vector(INSTANCE_STATE_KIND_WIDTH-1 downto 0) := ANY_INSTANCE_STATE; - signal view_state_dds, si_view_state : std_logic_vector(VIEW_STATE_KIND_WIDTH-1 downto 0) := ANY_VIEW_STATE; - signal sample_state_dds, si_sample_state : std_logic_vector(SAMPLE_STATE_KIND_WIDTH-1 downto 0) := ANY_SAMPLE_STATE; - signal instance_handle_dds, si_instance_handle : INSTANCE_HANDLE_TYPE := HANDLE_NIL; - signal max_samples_dds : std_logic_vector(MAX_SAMPLES_WIDTH-1 downto 0) := (others => '0'); - signal si_source_timestamp : TIME_TYPE := TIME_INVALID; - signal si_publication_handle : INSTANCE_HANDLE_TYPE := HANDLE_NIL; - signal si_disposed_generation_count : std_logic_vector(DISPOSED_GENERATION_COUNT_WIDTH-1 downto 0) := (others => '0'); - signal si_no_writers_generation_count : std_logic_vector(NO_WRITERS_GENERATION_COUNT_WIDTH-1 downto 0) := (others => '0'); - signal si_sample_rank : std_logic_vector(SAMPLE_RANK_WIDTH-1 downto 0) := (others => '0'); - signal si_generation_rank : std_logic_vector(GENERATION_RANK_WIDTH-1 downto 0) := (others => '0'); - signal si_absolute_generation_rank: std_logic_vector(ABSOLUTE_GENERATION_COUNT_WIDTH-1 downto 0) := (others => '0'); - - signal dds_start , dds_done , rtps_start, rtps_done : std_logic := '0'; - signal dds_cnt, dds_cnt2, rtps_cnt : natural := 0; - signal dds_stage : DDS_STAGE_TYPE := IDLE; - signal rtps_stage : RTPS_STAGE_TYPE := IDLE; - shared variable dds : DDS_READER_TEST_TYPE := DEFAULT_DDS_READER_TEST; - shared variable rtps : RTPS_READER_TEST_TYPE := DEFAULT_RTPS_READER_TEST; - shared variable mem : DDS_READER_MEM_TYPE := DEFAULT_DDS_READER_MEM; - signal data_id, ret_id, sstate_id, vstate_id, istate_id, inst_id, ts_id, pub_id, dis_gen_cnt_id, no_w_gen_cnt_id, srank_id, grank_id, agrank_id, eoc_id, valid_id, status_id : AlertLogIDType; - - -- *FUNCTION DECLARATION* - function extract_key_hash (payload : TEST_PACKET_TYPE) return INSTANCE_HANDLE_TYPE is - variable ret : INSTANCE_HANDLE_TYPE := HANDLE_NIL; - begin - for i in 0 to 3 loop - ret(i) := not payload.data(i); - end loop; - - return ret; - end function; - - function gen_sn(input : natural) return SEQUENCENUMBER_TYPE is - variable ret : SEQUENCENUMBER_TYPE; - begin - ret(0) := (others => '0'); - ret(1) := unsigned(int(input, WORD_WIDTH)); - return ret; - end function; - -begin - - -- Unit Under Test - uut : entity work.dds_reader(arch) - generic map ( - TIME_BASED_FILTER_QOS => DURATION_ZERO, - DEADLINE_QOS => DURATION_INFINITE, - MAX_SAMPLES => std_logic_vector(to_unsigned(4,CDR_LONG_WIDTH)), - MAX_INSTANCES => std_logic_vector(to_unsigned(3,CDR_LONG_WIDTH)), - MAX_SAMPLES_PER_INSTANCE => std_logic_vector(to_unsigned(2,CDR_LONG_WIDTH)), - HISTORY_QOS => KEEP_ALL_HISTORY_QOS, - RELIABILITY_QOS => RELIABLE_RELIABILITY_QOS, - PRESENTATION_QOS => INSTANCE_PRESENTATION_QOS, - DESTINATION_ORDER_QOS => BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS, - COHERENT_ACCESS => FALSE, - ORDERED_ACCESS => FALSE, - WITH_KEY => TRUE, - PAYLOAD_FRAME_SIZE => 11, - MAX_REMOTE_ENDPOINTS => MAX_REMOTE_ENDPOINTS - ) - port map ( - clk => clk, - reset => reset, - time => check_time, - start_rtps => start_rtps, - opcode_rtps => opcode_rtps, - ack_rtps => ack_rtps, - done_rtps => done_rtps, - ret_rtps => ret_rtps, - data_in_rtps => data_in_rtps, - valid_in_rtps => valid_in_rtps, - ready_in_rtps => ready_in_rtps, - last_word_in_rtps => last_word_in_rtps, - start_dds => start_dds, - ack_dds => ack_dds, - opcode_dds => opcode_dds, - instance_state_dds => instance_state_dds, - view_state_dds => view_state_dds, - sample_state_dds => sample_state_dds, - instance_handle_dds => instance_handle_dds, - max_samples_dds => max_samples_dds, - get_data_dds => get_data_dds, - done_dds => done_dds, - return_code_dds => return_code_dds, - ready_out_dds => ready_out_dds, - valid_out_dds => valid_out_dds, - data_out_dds => data_out_dds, - last_word_out_dds => last_word_out_dds, - sample_info.sample_state => si_sample_state, - sample_info.view_state => si_view_state, - sample_info.instance_state => si_instance_state, - sample_info.source_timestamp => si_source_timestamp, - sample_info.instance_handle => si_instance_handle, - sample_info.publication_handle => si_publication_handle, - sample_info.disposed_generation_count => si_disposed_generation_count, - sample_info.no_writers_generation_count => si_no_writers_generation_count, - sample_info.sample_rank => si_sample_rank, - sample_info.generation_rank => si_generation_rank, - sample_info.absolute_generation_rank => si_absolute_generation_rank, - sample_info.valid_data => si_valid_data, - sample_info_valid => si_valid, - sample_info_ack => '1', - eoc => eoc, - status => status - ); - - stimulus_prc : process - variable RV : RandomPType; - variable cc : CACHE_CHANGE_TYPE := DEFAULT_CACHE_CHANGE; - variable s : SAMPLE_TYPE := DEFAULT_SAMPLE; - variable kh1, kh2, kh3, kh4, kh5 : INSTANCE_HANDLE_TYPE := HANDLE_NIL; - - alias idle_sig is <>; - - impure function gen_payload(key_hash : INSTANCE_HANDLE_TYPE; len : natural) return TEST_PACKET_TYPE is - variable ret : TEST_PACKET_TYPE := EMPTY_TEST_PACKET; - begin - assert (len >= 4) report "Payload length has to be at least 16 Bytes long" severity FAILURE; - - for i in 0 to len-1 loop - if (i < 4) then - -- NOTE: Beginning of payload is negated key to allow deterministic Key Hash generation from the kh_prc - ret.data(ret.length) := not key_hash(i); - else - ret.data(ret.length) := RV.RandSlv(WORD_WIDTH); - end if; - ret.length := ret.length + 1; - end loop; - ret.last(ret.length-1) := '1'; - - return ret; - end function; - - impure function gen_key_hash return KEY_HASH_TYPE is - variable ret : KEY_HASH_TYPE := KEY_HASH_NIL; - begin - for i in 0 to KEY_HASH_TYPE'length-1 loop - ret(i) := RV.RandSlv(WORD_WIDTH); - end loop; - return ret; - end function; - - procedure start_dds is - begin - dds_start <= '1'; - wait until rising_edge(clk); - dds_start <= '0'; - wait until rising_edge(clk); - end procedure; - - procedure start_rtps is - begin - rtps_start <= '1'; - wait until rising_edge(clk); - rtps_start <= '0'; - wait until rising_edge(clk); - end procedure; - - procedure wait_on_dds is - begin - if (dds_done /= '1') then - wait until dds_done = '1'; - end if; - end procedure; - - procedure wait_on_rtps is - begin - if (rtps_done /= '1') then - wait until rtps_done = '1'; - end if; - end procedure; - - procedure wait_on_completion is - begin - if (rtps_done /= '1' or dds_done /= '1') then - wait until rtps_done = '1' and dds_done = '1'; - end if; - end procedure; - - -- NOTE: This procedure waits until the idle_sig is high for at least - -- two consecutive clock cycles. - procedure wait_on_idle is - variable first : boolean := TRUE; - begin - loop - if (idle_sig /= '1') then - wait until idle_sig = '1'; - elsif (not first) then - exit; - end if; - wait until rising_edge(clk); - wait until rising_edge(clk); - first := FALSE; - end loop; - end procedure; - - begin - - SetAlertLogName("L0_dds_reader_test1_arzkriu - (KEEP ALL, Reliable, Zero TIME_BASED_FILTER, Keyed, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER, ACCESS SCOPE Instance, Unordered) - RTPS Handling"); - SetAlertEnable(FAILURE, TRUE); - SetAlertEnable(ERROR, TRUE); - SetAlertEnable(WARNING, TRUE); - SetLogEnable(DEBUG, FALSE); - SetLogEnable(PASSED, FALSE); - SetLogEnable(INFO, TRUE); - RV.InitSeed(RV'instance_name); - sstate_id <= GetAlertLogID("Sample State", ALERTLOG_BASE_ID); - vstate_id <= GetAlertLogID("View State", ALERTLOG_BASE_ID); - istate_id <= GetAlertLogID("Instance State", ALERTLOG_BASE_ID); - ts_id <= GetAlertLogID("Source Timestamp", ALERTLOG_BASE_ID); - inst_id <= GetAlertLogID("Instance Handle", ALERTLOG_BASE_ID); - pub_id <= GetAlertLogID("Publication Hanlde", ALERTLOG_BASE_ID); - dis_gen_cnt_id <= GetAlertLogID("Disposed Generation Count", ALERTLOG_BASE_ID); - no_w_gen_cnt_id <= GetAlertLogID("No Writers Generation Count", ALERTLOG_BASE_ID); - srank_id <= GetAlertLogID("Sample Rank", ALERTLOG_BASE_ID); - grank_id <= GetAlertLogID("Generation Rank", ALERTLOG_BASE_ID); - agrank_id <= GetAlertLogID("Absolute Generation Rank", ALERTLOG_BASE_ID); - eoc_id <= GetAlertLogID("End of Collection", ALERTLOG_BASE_ID); - valid_id <= GetAlertLogID("Valid Data", ALERTLOG_BASE_ID); - data_id <= GetAlertLogID("Data Out", ALERTLOG_BASE_ID); - ret_id <= GetAlertLogID("Return Code", ALERTLOG_BASE_ID); - status_id <= GetAlertLogID("Communication Status", ALERTLOG_BASE_ID); - - -- Key Hashes - kh3 := (x"0CEAB0C6", x"FA04B9AD", x"A96EB495", x"4E0EB999"); - kh4 := (x"A7EB605C", x"FF4BEF3A", x"3C5E8724", x"CCA0CA67"); - kh2 := (x"BC070AC4", x"0BAB5811", x"14EA8D61", x"F669189B"); - kh1 := (x"F12C31DA", x"E3FE0F3F", x"01F36685", x"446518CA"); - kh5 := gen_key_hash; - - - - Log("Initiating Test", INFO); - reset <= '1'; - wait until rising_edge(clk); - wait until rising_edge(clk); - reset <= '0'; - -- MEM: 0, 0, 0, 0 - -- ISTATE: - - -- WRITER: - - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh1; - cc.payload := gen_payload(kh1,10); - cc.src_timestamp := gen_duration(1,0); - - -- TEST: NORMAL ADD_CACHE_CHANGE - -- TEST: SAMPLE WITH ALIGNED PAYLOAD - -- TEST: NORMAL SAMPLE [UNKNOWN INSTANCE] - -- TEST: SAMPLE WITH KEY_HASH - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Aligned Payload] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - rtps.ret_code := OK; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S1, 0, 0, 0 - -- ISTATE: I1:ALIVE - -- WRITER: W0:I1 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := HANDLE_NIL; - cc.payload := gen_payload(kh1,18); - cc.src_timestamp := gen_duration(2,0); - - -- TEST: SAMPLE WITHOUT KEY_HASH - -- TEST: SAMPLE WITH UNALIGNED PAYLOAD [>1 SLOT] - -- TEST: NORMAL SAMPLE [KNOWN INSTANCE] - - Log("RTPS Operation ADD_CACHE_CHANGE [NO KEY_HASH, Instance 1, Writer 0, Unaligned Payload (2 Slots)] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - rtps.ret_code := OK; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - s.inst := kh1; - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S1, I1S2+, 0, 0 - -- ISTATE: I1:ALIVE - -- WRITER: W0:I1 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - -- VAILDATE STATE - - Log("DDS Operation READ [MAX_SAMPLES 4, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ; - dds.max_samples := 4; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - start_dds; - wait_on_dds; - wait_on_idle; - -- MEM: I1S1, I1S2+, 0, 0 - -- ISTATE: I1:ALIVE - -- WRITER: W0:I1 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_DISPOSED; - cc.instance := kh1; - cc.payload := gen_payload(kh1,5); - cc.src_timestamp := gen_duration(3,0); - - -- TEST: ADD SAMPLE ON MAX_SAMPLES_PER_INSTANCE - - Log("RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Instance 1, Writer 0] (REJECTED: MAX_SAMPLES_PER_INSTANCE exceeded)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - rtps.ret_code := REJECTED; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S1, I1S2+, 0, 0 - -- ISTATE: I1:ALIVE - -- WRITER: W0:I1 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - Log("DDS Operation TAKE [MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE; - dds.max_samples := 1; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - start_dds; - wait_on_dds; - wait_on_idle; - -- MEM: I1S2+, 0, 0, 0 - -- ISTATE: I1:ALIVE - -- WRITER: W0:I1 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - -- TEST: DISPOSE SAMPLE [KNOWN INSTANCE] - -- TEST: SAMPLE WITH SERIALIZED KEY [WITH KEY_HASH] - -- TEST: SAMPLE WITH UNALIGNED PAYLOAD [<1 SLOT] - - Log("RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Instance 1, Writer 0] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - rtps.ret_code := OK; - s := to_sample(cc,NOT_ALIVE_DISPOSED_INSTANCE_STATE); - s.inst := kh1; - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S2+, I1S3-, 0, 0 - -- ISTATE: I1:DISPOSED - -- WRITER: W0:I1 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh2; - cc.payload := gen_payload(kh2,20); - cc.src_timestamp := gen_duration(4,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 2, Writer 1, Aligned Payload (2 Slots)] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 1; - rtps.ret_code := OK; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S2+, I1S3-, I2S1+, 0 - -- ISTATE: I1:DISPOSED, I2:ALIVE - -- WRITER: W0:I1, W1:I2 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh3; - cc.payload := gen_payload(kh3,10); - cc.src_timestamp := gen_duration(5,0); - - -- TEST: TEST SAMPLE WITH SERIALIZED KEY EFFECT ON PAYLOAD MEMORY FULLNESS - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 3, Writer 1, Aligned Payload] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 1; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S2+, I1S3-, I2S1+, I3S1 - -- ISTATE: I1:DISPOSED, I2:ALIVE, I3: ALIVE - -- WRITER: W0:I1, W1:I2,I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - -- TEST: REMOVE_WRITER [UNKNOWN WRITER] - - Log("RTPS Operation REMOVE_WRITER [Writer 2] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := REMOVE_WRITER; - rtps.writer_pos := 2; - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S2+, I1S3-, I2S1+, I3S1 - -- ISTATE: I1:DISPOSED, I2:ALIVE, I3: ALIVE - -- WRITER: W0:I1, W1:I2,I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - Log("DDS Operation TAKE [MAX_SAMPLES 1, NOT_READ_SAMPLE_STATE, NOT_ALIVE_DISPOSED_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE; - dds.max_samples := 1; - dds.sstate := NOT_READ_SAMPLE_STATE; - dds.istate := NOT_ALIVE_DISPOSED_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - start_dds; - wait_on_dds; - wait_on_idle; - -- MEM: I1S2+, I2S1+, I3S1, 0 - -- ISTATE: I1:DISPOSED, I2:ALIVE, I3: ALIVE - -- WRITER: W0:I1, W1:I2,I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh3; - cc.payload := gen_payload(kh3,10); - cc.src_timestamp := gen_duration(6,0); - - -- TEST: ADD_CACHE_CHANGE ON PAYLOAD MEMORY FULL - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 3, Writer 2, Aligned Payload] (REJECTED: Payload Memory Full)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 2; - rtps.ret_code := REJECTED; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S2+, I2S1+, I3S1, 0 - -- ISTATE: I1:DISPOSED, I2:ALIVE, I3: ALIVE - -- WRITER: W0:I1, W1:I2,I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - Log("DDS Operation TAKE [MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE; - dds.max_samples := 1; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - start_dds; - wait_on_dds; - wait_on_idle; - -- MEM: I2S1+, I3S1, 0, 0 - -- ISTATE: I1:DISPOSED, I2:ALIVE, I3: ALIVE - -- WRITER: W0:I1, W1:I2,I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 3, Writer 2, Aligned Payload] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 2; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I2S1+, I3S1, I3S2, 0 - -- ISTATE: I1:DISPOSED, I2:ALIVE, I3: ALIVE - -- WRITER: W0:I1, W1:I2,I3, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh4; - cc.payload := gen_payload(kh4,10); - cc.src_timestamp := gen_duration(7,0); - - -- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKOWN INSTANCE, WITHOUT STALE INSTANCE, WITH EMPTY INSTANCE] - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 4, Writer 1, Aligned Payload] (REJECTED: MAX_INSTANCES exceeded)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 1; - rtps.ret_code := REJECTED; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I2S1+, I3S1, I3S2, 0 - -- ISTATE: I1:DISPOSED, I2:ALIVE, I3: ALIVE - -- WRITER: W0:I1, W1:I2,I3, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - -- TEST: REMOVE_WRITER [KNOWN WRITER (1 Instance)] - - Log("RTPS Operation REMOVE_WRITER [Writer 0] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := REMOVE_WRITER; - rtps.writer_pos := 0; - change_istate(kh1, NOT_ALIVE_NO_WRITERS_INSTANCE_STATE, mem); - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I2S1+, I3S1, I3S2, 0 - -- ISTATE: I1:DISPOSED, I2:ALIVE, I3: ALIVE - -- WRITER: W1:I2,I3, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - -- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKOWN INSTANCE, WITH STALE INSTANCE] - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 4, Writer 1, Aligned Payload] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 1; - remove_inst(kh1, mem); - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I2S1+, I3S1, I3S2, I4S1 - -- ISTATE: I2:ALIVE, I3: ALIVE, I4:ALIVE - -- WRITER: W1:I2,I3,I4, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - -- VALIDATE STATE - - Log("DDS Operation READ [MAX_SAMPLES 4, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ; - dds.max_samples := 4; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - start_dds; - wait_on_dds; - wait_on_idle; - -- MEM: I2S1+, I3S1, I3S2, I4S1 - -- ISTATE: I2:ALIVE, I3: ALIVE, I4:ALIVE - -- WRITER: W1:I2,I3,I4, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - Log("DDS Operation TAKE [MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE; - dds.max_samples := 1; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - start_dds; - wait_on_dds; - wait_on_idle; - -- MEM: I3S1, I3S2, I4S1, 0 - -- ISTATE: I2:ALIVE, I3: ALIVE, I4:ALIVE - -- WRITER: W1:I2,I3,I4, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh1; - cc.payload := gen_payload(kh1,10); - cc.src_timestamp := gen_duration(8,0); - - -- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKOWN INSTANCE, WITHOUT STALE INSTANCE] - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Aligned Payload] (REJECTED: MAX_INSTANCES exceeded)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - rtps.ret_code := REJECTED; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I3S1, I3S2, I4S1, 0 - -- ISTATE: I2:ALIVE, I3: ALIVE, I4:ALIVE - -- WRITER: W1:I2,I3,I4, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh4; - cc.payload := gen_payload(kh4,10); - cc.src_timestamp := gen_duration(9,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 4, Writer 1, Aligned Payload] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 1; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I3S1, I3S2, I4S1, I4S2 - -- ISTATE: I2:ALIVE, I3: ALIVE, I4:ALIVE - -- WRITER: W1:I2,I3,I4, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh2; - cc.payload := gen_payload(kh2,10); - cc.src_timestamp := gen_duration(10,0); - - -- TEST: ADD SAMPLE ON MAX_SAMPLES [KNOWN INSTANCE] - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 2, Writer 1, Aligned Payload] (REJECTED: MAX_SAMPLES exceeded)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 1; - rtps.ret_code := REJECTED; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I3S1, I3S2, I4S1, I4S2 - -- ISTATE: I2:ALIVE, I3: ALIVE, I4:ALIVE - -- WRITER: W1:I2,I3,I4, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh1; - cc.payload := gen_payload(kh1,10); - cc.src_timestamp := gen_duration(11,0); - - -- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE, WITHOUT STALE INSTANCE] - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Aligned Payload] (REJECTED: MAX_SAMPLES exceeded)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - rtps.ret_code := REJECTED; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I3S1, I3S2, I4S1, I4S2 - -- ISTATE: I2:ALIVE, I3: ALIVE, I4:ALIVE - -- WRITER: W1:I2,I3,I4, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - -- TEST: REMOVE_WRITER [KNOWN WRITER (>1 Instances)] - -- TEST: REMOVE_WRITER [NOT_ALIVE_NO_WRITERS Transition] - -- TEST: REMOVE_WRITER [Multiple Pending NOT_ALIVE_NO_WRITERS Transitions] - -- TEST: REMOVE_WRITER ON MAX_SAMPLES [NOT_ALIVE_NO_WRITERS Transition] - -- TEST: REMOVE_WRITER ON MAX_SAMPLES_PER_INSTANCE [NOT_ALIVE_NO_WRITERS Transition] - - Log("RTPS Operation REMOVE_WRITER [Writer 1] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := REMOVE_WRITER; - rtps.writer_pos := 1; - change_istate(kh2, NOT_ALIVE_NO_WRITERS_INSTANCE_STATE, mem); - change_istate(kh4, NOT_ALIVE_NO_WRITERS_INSTANCE_STATE, mem); - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I3S1, I3S2, I4S1, I4S2 - -- ISTATE: I2:NO_WRITER, I3: ALIVE, I4:NO_WRITER - -- WRITER: W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_UNREGISTERED; - cc.instance := kh2; - cc.src_timestamp := check_time; - - Log("DDS Operation TAKE [MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE; - dds.max_samples := 1; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - s := to_sample(cc,NOT_ALIVE_NO_WRITERS_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_dds; - wait_on_dds; - wait_on_idle; - -- MEM: I3S2, I4S1, I4S2, I2S2- - -- ISTATE: I2:NO_WRITER, I3: ALIVE, I4:NO_WRITER - -- WRITER: W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - -- NOTE: We read the current KH4 Samples, so that we can easiy remove the new KH4 Sample - Log("DDS Operation READ_INSTANCE [Instance 4, MAX_SAMPLES 2, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ_INSTANCE; - dds.max_samples := 2; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.inst := kh4; - start_dds; - wait_on_dds; - wait_on_idle; - -- MEM: I3S2, I4S1, I4S2, I2S2- - -- ISTATE: I2:NO_WRITER, I3: ALIVE, I4:NO_WRITER - -- WRITER: W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_UNREGISTERED; - cc.instance := kh4; - cc.src_timestamp := check_time; - - Log("DDS Operation TAKE_INSTANCE [Instance 4, MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE_INSTANCE; - dds.max_samples := 1; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.inst := kh4; - s := to_sample(cc,NOT_ALIVE_NO_WRITERS_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_dds; - wait_on_dds; - wait_on_idle; - -- MEM: I3S2, I4S2, I2S2-, I4S3- - -- ISTATE: I2:NO_WRITER, I3: ALIVE, I4:NO_WRITER - -- WRITER: W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - Log("DDS Operation TAKE_INSTANCE [Instance 4, MAX_SAMPLES 1, NOT_READ_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE_INSTANCE; - dds.max_samples := 1; - dds.sstate := NOT_READ_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.inst := kh4; - start_dds; - wait_on_dds; - wait_on_idle; - -- MEM: I3S2, I4S2, I2S2-, 0 - -- ISTATE: I2:NO_WRITER, I3: ALIVE, I4:NO_WRITER - -- WRITER: W2:I3 - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_DISPOSED; - cc.instance := HANDLE_NIL; - cc.payload := gen_payload(kh4,5); - cc.src_timestamp := gen_duration(12,0); - - -- TEST: DISPOSE SAMPLE [NOT_ALIVE_NO_WRITERS INSTANCE] - -- TEST: SAMPLE WITH SERIALIZED KEY [WITHOUT KEY_HASH] - - Log("RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Instance 4, Writer 1] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 1; - s := to_sample(cc,NOT_ALIVE_DISPOSED_INSTANCE_STATE); - s.inst := kh4; - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I3S2, I4S2, I2S2-, I4S4- - -- ISTATE: I2:NO_WRITER, I3: ALIVE, I4:DISPOSED - -- WRITER: W1:I4, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh1; - cc.payload := gen_payload(kh1,10); - cc.src_timestamp := gen_duration(13,0); - - -- TEST: ADD SAMPLE ON MAX_SAMPLES [UNKNOWN INSTANCE] - -- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE, WITH STALE INSTANCE] - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Aligned Payload] (REJECTED: MAX_SAMPLES exceeded)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - rtps.ret_code := REJECTED; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I3S2, I4S2, I2S2-, I4S4- - -- ISTATE: I2:NO_WRITER, I3: ALIVE, I4:DISPOSED - -- WRITER: W1:I4, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - Log("DDS Operation TAKE [MAX_SAMPLES 2, NOT_READ_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE; - dds.max_samples := 2; - dds.sstate := NOT_READ_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - start_dds; - wait_on_dds; - wait_on_idle; - -- MEM: I3S2, I4S2, 0, 0 - -- ISTATE: I2:NO_WRITER, I3: ALIVE, I4:DISPOSED - -- WRITER: W1:I4, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh3; - cc.payload := gen_payload(kh3,10); - cc.src_timestamp := gen_duration(14,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 3, Writer 2, Aligned Payload] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 2; - rtps.ret_code := OK; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I3S2, I4S2, I3S3, 0 - -- ISTATE: I2:NO_WRITER, I3: ALIVE, I4:DISPOSED - -- WRITER: W1:I4, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh1; - cc.payload := gen_payload(kh1,30); - cc.src_timestamp := gen_duration(15,0); - - -- TEST: ADD SAMPLE BIGGER THAN AVAILABLE MEMORY SPACE - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Aligned Payload (3 Slots)] (REJECTED: Payload Memory Full)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - rtps.ret_code := REJECTED; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I3S2, I4S2, I3S3, 0 - -- ISTATE: I2:NO_WRITER, I3: ALIVE, I4:DISPOSED - -- WRITER: W1:I4, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh1; - cc.payload := gen_payload(kh1,20); - cc.src_timestamp := gen_duration(16,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Aligned Payload (2 Slots)] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - remove_inst(kh2, mem); - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I3S2, I4S2, I3S3, I1S1+ - -- ISTATE: I1:ALIVE, I3: ALIVE, I4:DISPOSED - -- WRITER: W0:I1, W1:I4, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - -- VALIDATE STATE - - Log("DDS Operation TAKE [MAX_SAMPLES 4, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE; - dds.max_samples := 4; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - start_dds; - wait_on_dds; - wait_on_idle; - -- MEM: 0, 0, 0, 0 - -- ISTATE: I1:ALIVE, I3: ALIVE, I4:DISPOSED - -- WRITER: W0:I1, W1:I4, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_DISPOSED; - cc.instance := kh4; - cc.payload := gen_payload(kh4,5); - cc.src_timestamp := gen_duration(17,0); - - -- TEST: DISPOSE SAMPLE [NOT_ALIVE_DISPOSED INSTANCE] - - Log("RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Instance 4, Writer 0] (IGNORED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: 0, 0, 0, 0 - -- ISTATE: I1:ALIVE, I3: ALIVE, I4:DISPOSED - -- WRITER: W0:I1,I4 W1:I4, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_UNREGISTERED; - cc.instance := kh4; - cc.payload := gen_payload(kh4,5); - cc.src_timestamp := gen_duration(18,0); - - -- TEST: UNREGISTER SAMPLE [KNOWN INSTANCE, KNOWN WRITER] - -- TEST: UNREGISTER SAMPLE [NOT_ALIVE_DISPOSED INSTANCE] - - Log("RTPS Operation ADD_CACHE_CHANGE [UNREGISTER, Instance 4, Writer 0] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: 0, 0, 0, 0 - -- ISTATE: I1:ALIVE, I3: ALIVE, I4:DISPOSED - -- WRITER: W0:I1 W1:I4, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_UNREGISTERED; - cc.instance := kh1; - cc.payload := gen_payload(kh1,5); - cc.src_timestamp := gen_duration(19,0); - - -- TEST: UNREGISTER SAMPLE [KNOWN INSTANCE, UNKNOWN WRITER] - - Log("RTPS Operation ADD_CACHE_CHANGE [UNREGISTER, Instance 1, Writer 1] (IGNORED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 1; - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: 0, 0, 0, 0 - -- ISTATE: I1:ALIVE, I3: ALIVE, I4:DISPOSED - -- WRITER: W0:I1 W1:I4, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_UNREGISTERED; - cc.instance := kh2; - cc.payload := gen_payload(kh2,5); - cc.src_timestamp := gen_duration(20,0); - - -- TEST: UNREGISTER SAMPLE [UNKNOWN INSTANCE] - - Log("RTPS Operation ADD_CACHE_CHANGE [UNREGISTER, Instance 2, Writer 1] (IGNORED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 1; - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: 0, 0, 0, 0 - -- ISTATE: I1:ALIVE, I3: ALIVE, I4:DISPOSED - -- WRITER: W0:I1 W1:I4, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_UNREGISTERED; - cc.instance := kh1; - cc.payload := gen_payload(kh1,5); - cc.src_timestamp := gen_duration(21,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [UNREGISTER, Instance 1, Writer 0] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - s := to_sample(cc,NOT_ALIVE_NO_WRITERS_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S2-, 0, 0, 0 - -- ISTATE: I1:NO_WRITERS, I3: ALIVE, I4:DISPOSED - -- WRITER: W1:I4, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_UNREGISTERED; - cc.instance := kh1; - cc.payload := gen_payload(kh1,5); - cc.src_timestamp := gen_duration(22,0); - - -- TEST: UNREGISTER SAMPLE [NOT_ALIVE_NO_WRITERS INSTANCE] - - Log("RTPS Operation ADD_CACHE_CHANGE [UNREGISTER, Instance 1, Writer 2] (IGNORED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 2; - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S2-, 0, 0, 0 - -- ISTATE: I1:NO_WRITERS, I3: ALIVE, I4:DISPOSED - -- WRITER: W1:I4, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := ALIVE_FILTERED; - cc.instance := kh1; - cc.payload := gen_payload(kh1,5); - cc.src_timestamp := gen_duration(23,0); - - -- TEST: FILTER SAMPLE [KNOWN INSTANCE] - -- TEST: FILTER SAMPLE [NOT_ALIVE_NO_WRITERS INSTANCE] - - Log("RTPS Operation ADD_CACHE_CHANGE [FILTERED, Instance 1, Writer 2] (ACCEPT)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - rtps.writer_pos := 2; - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S2-, I1S3-, 0, 0 - -- ISTATE: I1:ALIVE, I3: ALIVE, I4:DISPOSED - -- WRITER: W1:I4, W2:I1,I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_UNREGISTERED; - cc.instance := kh4; - cc.payload := gen_payload(kh1,5); - cc.src_timestamp := gen_duration(24,0); - - -- TEST: UNREGISTER SAMPLE [NOT_ALIVE_DISPOSED INSTANCE, STALE INSTANCE TRANSITION] - - Log("RTPS Operation ADD_CACHE_CHANGE [UNREGISTER, Instance 4, Writer 1] (ACCEPT)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 1; - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S2-, I1S3-, 0, 0 - -- ISTATE: I1:ALIVE, I3: ALIVE, I4:DISPOSED - -- WRITER: W2:I1,I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh2; - cc.payload := gen_payload(kh2,10); - cc.src_timestamp := gen_duration(25,0); - - -- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKOWN INSTANCE, NOT_ALIVE_DISPOSED & STALE INSTANCE] - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 2, Writer 0, Aligned Payload] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - remove_inst(kh4, mem); - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S2-, I1S3-, I2S1, 0 - -- ISTATE: I1:ALIVE, I2:ALIVE, I3: ALIVE - -- WRITER: W0:I2, W2:I1,I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - -- VALIDATE STATE - - Log("DDS Operation TAKE [MAX_SAMPLES 4, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE; - dds.max_samples := 4; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - start_dds; - wait_on_dds; - wait_on_idle; - -- MEM: 0, 0, 0, 0 - -- ISTATE: I1:ALIVE, I2:ALIVE, I3: ALIVE - -- WRITER: W0:I2, W2:I1,I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_DISPOSED; - cc.instance := kh1; - cc.payload := gen_payload(kh1,5); - cc.src_timestamp := gen_duration(26,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Instance 1, Writer 2] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 2; - s := to_sample(cc,NOT_ALIVE_DISPOSED_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S4-, 0, 0, 0 - -- ISTATE: I1:DISPOSED, I2:ALIVE, I3: ALIVE - -- WRITER: W0:I2, W2:I1,I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := ALIVE_FILTERED; - cc.instance := kh1; - cc.payload := gen_payload(kh1,5); - cc.src_timestamp := gen_duration(27,0); - - -- TEST: FILTER SAMPLE [NOT_ALIVE_DISPOSED INSTANCE] - - Log("RTPS Operation ADD_CACHE_CHANGE [FILTERED, Instance 1, Writer 2] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - rtps.writer_pos := 2; - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S4-, I1S5-, 0, 0 - -- ISTATE: I1:ALIVE, I2:ALIVE, I3: ALIVE - -- WRITER: W0:I2, W2:I1,I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := ALIVE_FILTERED; - cc.instance := kh4; - cc.payload := gen_payload(kh4,5); - cc.src_timestamp := gen_duration(28,0); - - -- TEST: FILTER SAMPLE [UNKNOWN INSTANCE] - - Log("RTPS Operation ADD_CACHE_CHANGE [FILTERED, Instance 4, Writer 1] (IGNORED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 1; - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S4-, I1S5-, 0, 0 - -- ISTATE: I1:ALIVE, I2:ALIVE, I3: ALIVE - -- WRITER: W0:I2, W2:I1,I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - -- TEST: SAMPLE WITH EARLY TIMESTAMP [TIMESTAMP EARLIER THAN LAST READ] - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh3; - cc.payload := gen_payload(kh3,10); - cc.src_timestamp := gen_duration(10,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 3, Writer 2, Aligned Payload] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 2; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S4-, I1S5-, I3S4, 0 - -- ISTATE: I1:ALIVE, I2:ALIVE, I3: ALIVE - -- WRITER: W0:I2, W2:I1,I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_UNREGISTERED; - cc.instance := kh2; - cc.payload := gen_payload(kh2,5); - cc.src_timestamp := gen_duration(29,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [UNREGISTER, Instance 2, Writer 0] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - s := to_sample(cc,NOT_ALIVE_NO_WRITERS_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S4-, I1S5-, I3S4, I2S2- - -- ISTATE: I1:ALIVE, I2:NO_WRITERS, I3: ALIVE - -- WRITER: W2:I1,I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - -- VALIDATE STATE - - Log("DDS Operation TAKE [MAX_SAMPLES 4, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE; - dds.max_samples := 4; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - start_dds; - wait_on_dds; - wait_on_idle; - -- MEM: 0, 0, 0, 0 - -- ISTATE: I1:ALIVE, I2:NO_WRITERS, I3: ALIVE - -- WRITER: W2:I1,I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_DISPOSED; - cc.instance := kh4; - cc.payload := gen_payload(kh4,5); - cc.src_timestamp := gen_duration(30,0); - - -- TEST: DISPOSE SAMPLE [UNKNOWN INSTANCE] - - Log("RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Instance 4, Writer 1] (ACCPETED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 1; - s := to_sample(cc,NOT_ALIVE_DISPOSED_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I4S1-, 0, 0, 0 - -- ISTATE: I1:ALIVE, I3: ALIVE, I4:DISPOSED - -- WRITER: W1:I4, W2:I1,I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - -- VALIDATE STATE - - Log("DDS Operation READ [MAX_SAMPLES 4, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE; - dds.max_samples := 4; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := NOT_ALIVE_DISPOSED_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - start_dds; - wait_on_dds; - wait_on_idle; - -- MEM: I4S1-, 0, 0, 0 - -- ISTATE: I1:ALIVE, I3: ALIVE, I4:DISPOSED - -- WRITER: W1:I4, W2:I1,I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - wait_on_completion; - TranscriptOpen(RESULTS_FILE, APPEND_MODE); - SetTranscriptMirror; - ReportAlerts; - TranscriptClose; - std.env.stop; - wait; - end process; - - clock_prc : process - begin - clk <= '0'; - wait for 25 ns; - clk <= '1'; - wait for 25 ns; - end process; - - alert_prc : process(all) - begin - if rising_edge(clk) then - -- TODO - end if; - end process; - - dds_prc : process(all) - variable col : COLLECTION_TYPE := DEFAULT_COLLECTION; - begin - if rising_edge(clk) then - dds_done <= '0'; - case (dds_stage ) is - when IDLE => - if (dds_start = '1') then - dds_stage <= START; - else - dds_done <= '1'; - end if; - when START => - if (ack_dds = '1') then - dds_stage <= DONE; - dds_cnt <= 0; - end if; - when DONE => - if (done_dds = '1') then - AffirmIfEqual(ret_id, return_code_dds, dds.ret_code); - case (dds.ret_code) is - when RETCODE_OK => - gen_collection(mem, col, dds, INSTANCE_PRESENTATION_QOS, FALSE); - dds_stage <= CHECK_SI; - dds_cnt <= 0; - when others => - dds_stage <= IDLE; - end case; - end if; - when CHECK_SI => - if (si_valid = '1') then - AffirmIfEqual(sstate_id, si_sample_state, col.s(dds_cnt).sstate); - AffirmIfEqual(vstate_id, si_view_state, col.s(dds_cnt).vstate); - AffirmIfEqual(istate_id, si_instance_state, col.s(dds_cnt).istate); - AffirmIfEqual(ts_id, to_unsigned(si_source_timestamp), to_unsigned(col.s(dds_cnt).ts)); - AffirmIfEqual(inst_id, to_unsigned(si_instance_handle), to_unsigned(col.s(dds_cnt).inst)); - AffirmIfEqual(pub_id, to_unsigned(si_publication_handle), to_unsigned(HANDLE_NIL)); - AffirmIfEqual(dis_gen_cnt_id, si_disposed_generation_count, std_logic_vector(to_unsigned(col.s(dds_cnt).dis_gen_cnt,WORD_WIDTH))); - AffirmIfEqual(no_w_gen_cnt_id, si_no_writers_generation_count, std_logic_vector(to_unsigned(col.s(dds_cnt).no_w_gen_cnt,WORD_WIDTH))); - AffirmIfEqual(srank_id, si_sample_rank, std_logic_vector(to_unsigned(col.s(dds_cnt).srank,WORD_WIDTH))); - AffirmIfEqual(grank_id, si_generation_rank, std_logic_vector(to_unsigned(col.s(dds_cnt).grank,WORD_WIDTH))); - AffirmIfEqual(agrank_id, si_absolute_generation_rank, std_logic_vector(to_unsigned(col.s(dds_cnt).agrank,WORD_WIDTH))); - if (si_valid_data = '1') then - AffirmIf(valid_id, col.s(dds_cnt).data /= EMPTY_TEST_PACKET, "Sample with Data not expected"); - dds_stage <= CHECK_DATA; - dds_cnt2 <= 0; - else - AffirmIf(valid_id, col.s(dds_cnt).data = EMPTY_TEST_PACKET, "Sample with Data expected"); - if (dds_cnt = col.len-1) then - -- DONE - dds_stage <= WAIT_EOC; - else - dds_cnt <= dds_cnt + 1; - end if; - end if; - end if; - AffirmIf(eoc_id, eoc = '0', "EOC pulled high"); - when CHECK_DATA => - if (valid_out_dds = '1') then - AffirmIfEqual(data_id, data_out_dds, col.s(dds_cnt).data.data(dds_cnt2)); - dds_cnt2 <= dds_cnt2 + 1; - if (dds_cnt2 = col.s(dds_cnt).data.length-1) then - AlertIf(data_id, last_word_out_dds /= '1', "Last Word Signal not pulled High", ERROR); - if (dds_cnt = col.len-1) then - -- DONE - dds_stage <= WAIT_EOC; - else - dds_stage <= CHECK_SI; - dds_cnt <= dds_cnt + 1; - end if; - end if; - end if; - when WAIT_EOC => - if (eoc = '1') then - dds_stage <= IDLE; - end if; - end case; - end if; - - -- DEFAULT - start_dds <= '0'; - opcode_dds <= NOP; - instance_state_dds <= ANY_INSTANCE_STATE; - view_state_dds <= ANY_VIEW_STATE; - sample_state_dds <= ANY_SAMPLE_STATE; - instance_handle_dds <= HANDLE_NIL; - max_samples_dds <= (others => '0'); - get_data_dds <= '0'; - ready_out_dds <= '0'; - - - case (dds_stage ) is - when START => - start_dds <= '1'; - opcode_dds <= dds.opcode; - instance_state_dds <= dds.istate; - view_state_dds <= dds.vstate; - sample_state_dds <= dds.sstate; - instance_handle_dds <= dds.inst; - max_samples_dds <= std_logic_vector(to_unsigned(dds.max_samples, WORD_WIDTH)); - when CHECK_SI => - if (si_valid = '1' and si_valid_data = '1') then - get_data_dds <= '1'; - end if; - when CHECK_DATA => - ready_out_dds <= '1'; - when others => - null; - end case; - end process; - - rtps_prc : process(all) - variable stimulus : TEST_PACKET_TYPE := EMPTY_TEST_PACKET; - begin - if rising_edge(clk) then - rtps_done <= '0'; - case (rtps_stage) is - when IDLE => - if (rtps_start = '1') then - rtps_stage <= START; - else - rtps_done <= '1'; - end if; - when START => - if (ack_rtps = '1') then - case (rtps.opcode) is - when ADD_CACHE_CHANGE => - gen_add_cache_change_dds(rtps.cc, rtps.lifespan, rtps.writer_pos, stimulus); - rtps_stage <= PUSH; - when others => - rtps_stage <= DONE; - end case; - end if; - when PUSH => - if (ready_in_rtps = '1') then - rtps_cnt <= rtps_cnt + 1; - if (rtps_cnt = stimulus.length-1) then - rtps_stage <= DONE; - end if; - end if; - when DONE => - if (done_rtps = '1') then - AffirmIfEqual(ret_id, HISTORY_CACHE_RESPONSE_TYPE'pos(ret_rtps), HISTORY_CACHE_RESPONSE_TYPE'pos(rtps.ret_code)); - rtps_stage <= IDLE; - end if; - end case; - end if; - - -- DEFAULT - start_rtps <= '0'; - opcode_rtps <= NOP; - valid_in_rtps <= '0'; - last_word_in_rtps <= '0'; - data_in_rtps <= (others => '0'); - - case (rtps_stage) is - when START => - start_rtps <= '1'; - opcode_rtps <= rtps.opcode; - case (rtps.opcode) is - when REMOVE_WRITER => - data_in_rtps <= std_logic_vector(to_unsigned(rtps.writer_pos,WORD_WIDTH)); - when others => - null; - end case; - when PUSH => - valid_in_rtps <= '1'; - data_in_rtps <= stimulus.data(rtps_cnt); - last_word_in_rtps <= stimulus.last(rtps_cnt); - when others => - null; - end case; - end process; - - watchdog : process - begin - wait for 1 ms; - Alert("Test timeout", FAILURE); - std.env.stop; - end process; - -end architecture; \ No newline at end of file diff --git a/src/Tests/Level_0/L0_dds_reader_test1_arzksiu.vhd b/src/Tests/Level_0/L0_dds_reader_test1_arzksiu.vhd deleted file mode 100644 index bdc1256..0000000 --- a/src/Tests/Level_0/L0_dds_reader_test1_arzksiu.vhd +++ /dev/null @@ -1,1694 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library osvvm; -- Utility Library -context osvvm.OsvvmContext; - -use work.rtps_package.all; -use work.user_config.all; -use work.rtps_config_package.all; -use work.rtps_test_package.all; - --- This testbench tests the RTPS handling of the DDS Reader. It tests the correctness of the RTPS ADD_CACHE_CHANGE, and REMOVE_WRITER Operations. --- Implicitly some DDS Operations are also tested, since they are used for state checking. --- More specifically the testbench covers following tests: --- TEST: NORMAL ADD_CACHE_CHANGE --- TEST: ADD_CACHE_CHANGE ON PAYLOAD MEMORY FULL --- TEST: REMOVE_WRITER [UNKNOWN WRITER] --- TEST: REMOVE_WRITER [KNOWN WRITER (1 Instance)] --- TEST: REMOVE_WRITER [KNOWN WRITER (>1 Instances)] --- TEST: REMOVE_WRITER [NOT_ALIVE_NO_WRITERS Transition] --- TEST: REMOVE_WRITER [Multiple Pending NOT_ALIVE_NO_WRITERS Transitions] --- TEST: REMOVE_WRITER ON MAX_SAMPLES [NOT_ALIVE_NO_WRITERS Transition] --- TEST: REMOVE_WRITER ON MAX_SAMPLES_PER_INSTANCE [NOT_ALIVE_NO_WRITERS Transition] --- TEST: SAMPLE WITH ALIGNED PAYLOAD --- TEST: SAMPLE WITH UNALIGNED PAYLOAD [>1 SLOT] --- TEST: SAMPLE WITH UNALIGNED PAYLOAD [<1 SLOT] --- TEST: NORMAL SAMPLE [KNOWN INSTANCE] --- TEST: NORMAL SAMPLE [UNKNOWN INSTANCE] --- TEST: UNREGISTER SAMPLE [KNOWN INSTANCE, KNOWN WRITER] --- TEST: UNREGISTER SAMPLE [KNOWN INSTANCE, UNKNOWN WRITER] --- TEST: UNREGISTER SAMPLE [UNKNOWN INSTANCE] --- TEST: UNREGISTER SAMPLE [NOT_ALIVE_NO_WRITERS INSTANCE] --- TEST: UNREGISTER SAMPLE [NOT_ALIVE_DISPOSED INSTANCE] --- TEST: UNREGISTER SAMPLE [NOT_ALIVE_DISPOSED INSTANCE, STALE INSTANCE TRANSITION] --- TEST: DISPOSE SAMPLE [KNOWN INSTANCE] --- TEST: DISPOSE SAMPLE [UNKNOWN INSTANCE] --- TEST: DISPOSE SAMPLE [NOT_ALIVE_NO_WRITERS INSTANCE] --- TEST: DISPOSE SAMPLE [NOT_ALIVE_DISPOSED INSTANCE] --- TEST: FILTER SAMPLE [KNOWN INSTANCE] --- TEST: FILTER SAMPLE [UNKNOWN INSTANCE] --- TEST: FILTER SAMPLE [NOT_ALIVE_DISPOSED INSTANCE] --- TEST: FILTER SAMPLE [NOT_ALIVE_NO_WRITERS INSTANCE] --- TEST: SAMPLE WITH KEY_HASH --- TEST: SAMPLE WITHOUT KEY_HASH --- TEST: SAMPLE WITH SERIALIZED KEY [WITH KEY_HASH] --- TEST: SAMPLE WITH SERIALIZED KEY [WITHOUT KEY_HASH] --- TEST: SAMPLE WITH EARLY TIMESTAMP [TIMESTAMP EARLIER THAN LAST READ] --- TEST: TEST SAMPLE WITH SERIALIZED KEY EFFECT ON PAYLOAD MEMORY FULLNESS --- TEST: ADD SAMPLE ON MAX_SAMPLES_PER_INSTANCE --- TEST: ADD SAMPLE ON MAX_SAMPLES [KNOWN INSTANCE] --- TEST: ADD SAMPLE ON MAX_SAMPLES [UNKNOWN INSTANCE] --- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKOWN INSTANCE, WITH STALE INSTANCE] --- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKOWN INSTANCE, WITHOUT STALE INSTANCE] --- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKOWN INSTANCE, WITHOUT STALE INSTANCE, WITH EMPTY INSTANCE] --- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKOWN INSTANCE, NOT_ALIVE_DISPOSED & STALE INSTANCE] --- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE, WITH STALE INSTANCE] --- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE, WITHOUT STALE INSTANCE] --- TEST: ADD SAMPLE BIGGER THAN AVAILABLE MEMORY SPACE - -entity L0_dds_reader_test1_arzksiu is -end entity; - - -architecture testbench of L0_dds_reader_test1_arzksiu is - - -- *CONSTANT DECLARATION* - constant MAX_REMOTE_ENDPOINTS : natural := 3; - - -- *TYPE DECLARATION* - type DDS_STAGE_TYPE is (IDLE, START, DONE, CHECK_SI, CHECK_DATA, WAIT_EOC); - type RTPS_STAGE_TYPE is (IDLE, START, PUSH, DONE); - - -- *SIGNAL DECLARATION* - signal clk : std_logic := '0'; - signal reset : std_logic := '1'; - signal check_time : TIME_TYPE := TIME_ZERO; - signal start_rtps, start_dds, ack_rtps, ack_dds, done_rtps, done_dds : std_logic := '0'; - signal opcode_rtps : HISTORY_CACHE_OPCODE_TYPE := NOP; - signal opcode_dds : DDS_READER_OPCODE_TYPE := NOP; - signal ret_rtps : HISTORY_CACHE_RESPONSE_TYPE := ERROR; - signal ready_in_rtps, valid_in_rtps, last_word_in_rtps : std_logic := '0'; - signal ready_out_dds, valid_out_dds, last_word_out_dds : std_logic := '0'; - signal data_in_rtps, data_out_dds : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); - signal get_data_dds, si_valid_data, si_valid, eoc : std_logic := '0'; - signal return_code_dds : std_logic_vector(RETURN_CODE_WIDTH-1 downto 0) := (others => '0'); - signal status : std_logic_vector(STATUS_KIND_WIDTH-1 downto 0) := (others => '0'); - signal instance_state_dds, si_instance_state : std_logic_vector(INSTANCE_STATE_KIND_WIDTH-1 downto 0) := ANY_INSTANCE_STATE; - signal view_state_dds, si_view_state : std_logic_vector(VIEW_STATE_KIND_WIDTH-1 downto 0) := ANY_VIEW_STATE; - signal sample_state_dds, si_sample_state : std_logic_vector(SAMPLE_STATE_KIND_WIDTH-1 downto 0) := ANY_SAMPLE_STATE; - signal instance_handle_dds, si_instance_handle : INSTANCE_HANDLE_TYPE := HANDLE_NIL; - signal max_samples_dds : std_logic_vector(MAX_SAMPLES_WIDTH-1 downto 0) := (others => '0'); - signal si_source_timestamp : TIME_TYPE := TIME_INVALID; - signal si_publication_handle : INSTANCE_HANDLE_TYPE := HANDLE_NIL; - signal si_disposed_generation_count : std_logic_vector(DISPOSED_GENERATION_COUNT_WIDTH-1 downto 0) := (others => '0'); - signal si_no_writers_generation_count : std_logic_vector(NO_WRITERS_GENERATION_COUNT_WIDTH-1 downto 0) := (others => '0'); - signal si_sample_rank : std_logic_vector(SAMPLE_RANK_WIDTH-1 downto 0) := (others => '0'); - signal si_generation_rank : std_logic_vector(GENERATION_RANK_WIDTH-1 downto 0) := (others => '0'); - signal si_absolute_generation_rank: std_logic_vector(ABSOLUTE_GENERATION_COUNT_WIDTH-1 downto 0) := (others => '0'); - - signal dds_start , dds_done , rtps_start, rtps_done : std_logic := '0'; - signal dds_cnt, dds_cnt2, rtps_cnt : natural := 0; - signal dds_stage : DDS_STAGE_TYPE := IDLE; - signal rtps_stage : RTPS_STAGE_TYPE := IDLE; - shared variable dds : DDS_READER_TEST_TYPE := DEFAULT_DDS_READER_TEST; - shared variable rtps : RTPS_READER_TEST_TYPE := DEFAULT_RTPS_READER_TEST; - shared variable mem : DDS_READER_MEM_TYPE := DEFAULT_DDS_READER_MEM; - signal data_id, ret_id, sstate_id, vstate_id, istate_id, inst_id, ts_id, pub_id, dis_gen_cnt_id, no_w_gen_cnt_id, srank_id, grank_id, agrank_id, eoc_id, valid_id, status_id : AlertLogIDType; - - -- *FUNCTION DECLARATION* - function extract_key_hash (payload : TEST_PACKET_TYPE) return INSTANCE_HANDLE_TYPE is - variable ret : INSTANCE_HANDLE_TYPE := HANDLE_NIL; - begin - for i in 0 to 3 loop - ret(i) := not payload.data(i); - end loop; - - return ret; - end function; - - function gen_sn(input : natural) return SEQUENCENUMBER_TYPE is - variable ret : SEQUENCENUMBER_TYPE; - begin - ret(0) := (others => '0'); - ret(1) := unsigned(int(input, WORD_WIDTH)); - return ret; - end function; - -begin - - -- Unit Under Test - uut : entity work.dds_reader(arch) - generic map ( - TIME_BASED_FILTER_QOS => DURATION_ZERO, - DEADLINE_QOS => DURATION_INFINITE, - MAX_SAMPLES => std_logic_vector(to_unsigned(4,CDR_LONG_WIDTH)), - MAX_INSTANCES => std_logic_vector(to_unsigned(3,CDR_LONG_WIDTH)), - MAX_SAMPLES_PER_INSTANCE => std_logic_vector(to_unsigned(2,CDR_LONG_WIDTH)), - HISTORY_QOS => KEEP_ALL_HISTORY_QOS, - RELIABILITY_QOS => RELIABLE_RELIABILITY_QOS, - PRESENTATION_QOS => INSTANCE_PRESENTATION_QOS, - DESTINATION_ORDER_QOS => BY_SOURCE_TIMESTAMP_DESTINATION_ORDER_QOS, - COHERENT_ACCESS => FALSE, - ORDERED_ACCESS => FALSE, - WITH_KEY => TRUE, - PAYLOAD_FRAME_SIZE => 11, - MAX_REMOTE_ENDPOINTS => MAX_REMOTE_ENDPOINTS - ) - port map ( - clk => clk, - reset => reset, - time => check_time, - start_rtps => start_rtps, - opcode_rtps => opcode_rtps, - ack_rtps => ack_rtps, - done_rtps => done_rtps, - ret_rtps => ret_rtps, - data_in_rtps => data_in_rtps, - valid_in_rtps => valid_in_rtps, - ready_in_rtps => ready_in_rtps, - last_word_in_rtps => last_word_in_rtps, - start_dds => start_dds, - ack_dds => ack_dds, - opcode_dds => opcode_dds, - instance_state_dds => instance_state_dds, - view_state_dds => view_state_dds, - sample_state_dds => sample_state_dds, - instance_handle_dds => instance_handle_dds, - max_samples_dds => max_samples_dds, - get_data_dds => get_data_dds, - done_dds => done_dds, - return_code_dds => return_code_dds, - ready_out_dds => ready_out_dds, - valid_out_dds => valid_out_dds, - data_out_dds => data_out_dds, - last_word_out_dds => last_word_out_dds, - sample_info.sample_state => si_sample_state, - sample_info.view_state => si_view_state, - sample_info.instance_state => si_instance_state, - sample_info.source_timestamp => si_source_timestamp, - sample_info.instance_handle => si_instance_handle, - sample_info.publication_handle => si_publication_handle, - sample_info.disposed_generation_count => si_disposed_generation_count, - sample_info.no_writers_generation_count => si_no_writers_generation_count, - sample_info.sample_rank => si_sample_rank, - sample_info.generation_rank => si_generation_rank, - sample_info.absolute_generation_rank => si_absolute_generation_rank, - sample_info.valid_data => si_valid_data, - sample_info_valid => si_valid, - sample_info_ack => '1', - eoc => eoc, - status => status - ); - - stimulus_prc : process - variable RV : RandomPType; - variable cc : CACHE_CHANGE_TYPE := DEFAULT_CACHE_CHANGE; - variable s : SAMPLE_TYPE := DEFAULT_SAMPLE; - variable kh1, kh2, kh3, kh4, kh5 : INSTANCE_HANDLE_TYPE := HANDLE_NIL; - - alias idle_sig is <>; - - impure function gen_payload(key_hash : INSTANCE_HANDLE_TYPE; len : natural) return TEST_PACKET_TYPE is - variable ret : TEST_PACKET_TYPE := EMPTY_TEST_PACKET; - begin - assert (len >= 4) report "Payload length has to be at least 16 Bytes long" severity FAILURE; - - for i in 0 to len-1 loop - if (i < 4) then - -- NOTE: Beginning of payload is negated key to allow deterministic Key Hash generation from the kh_prc - ret.data(ret.length) := not key_hash(i); - else - ret.data(ret.length) := RV.RandSlv(WORD_WIDTH); - end if; - ret.length := ret.length + 1; - end loop; - ret.last(ret.length-1) := '1'; - - return ret; - end function; - - impure function gen_key_hash return KEY_HASH_TYPE is - variable ret : KEY_HASH_TYPE := KEY_HASH_NIL; - begin - for i in 0 to KEY_HASH_TYPE'length-1 loop - ret(i) := RV.RandSlv(WORD_WIDTH); - end loop; - return ret; - end function; - - procedure start_dds is - begin - dds_start <= '1'; - wait until rising_edge(clk); - dds_start <= '0'; - wait until rising_edge(clk); - end procedure; - - procedure start_rtps is - begin - rtps_start <= '1'; - wait until rising_edge(clk); - rtps_start <= '0'; - wait until rising_edge(clk); - end procedure; - - procedure wait_on_dds is - begin - if (dds_done /= '1') then - wait until dds_done = '1'; - end if; - end procedure; - - procedure wait_on_rtps is - begin - if (rtps_done /= '1') then - wait until rtps_done = '1'; - end if; - end procedure; - - procedure wait_on_completion is - begin - if (rtps_done /= '1' or dds_done /= '1') then - wait until rtps_done = '1' and dds_done = '1'; - end if; - end procedure; - - -- NOTE: This procedure waits until the idle_sig is high for at least - -- two consecutive clock cycles. - procedure wait_on_idle is - variable first : boolean := TRUE; - begin - loop - if (idle_sig /= '1') then - wait until idle_sig = '1'; - elsif (not first) then - exit; - end if; - wait until rising_edge(clk); - wait until rising_edge(clk); - first := FALSE; - end loop; - end procedure; - - begin - - SetAlertLogName("L0_dds_reader_test1_arzksiu - (KEEP ALL, Reliable, Zero TIME_BASED_FILTER, Keyed, BY_SOURCE_TIMESTAMP_DESTINATION_ORDER_QOS, ACCESS SCOPE Instance, Unordered) - RTPS Handling"); - SetAlertEnable(FAILURE, TRUE); - SetAlertEnable(ERROR, TRUE); - SetAlertEnable(WARNING, TRUE); - SetLogEnable(DEBUG, FALSE); - SetLogEnable(PASSED, FALSE); - SetLogEnable(INFO, TRUE); - RV.InitSeed(RV'instance_name); - sstate_id <= GetAlertLogID("Sample State", ALERTLOG_BASE_ID); - vstate_id <= GetAlertLogID("View State", ALERTLOG_BASE_ID); - istate_id <= GetAlertLogID("Instance State", ALERTLOG_BASE_ID); - ts_id <= GetAlertLogID("Source Timestamp", ALERTLOG_BASE_ID); - inst_id <= GetAlertLogID("Instance Handle", ALERTLOG_BASE_ID); - pub_id <= GetAlertLogID("Publication Hanlde", ALERTLOG_BASE_ID); - dis_gen_cnt_id <= GetAlertLogID("Disposed Generation Count", ALERTLOG_BASE_ID); - no_w_gen_cnt_id <= GetAlertLogID("No Writers Generation Count", ALERTLOG_BASE_ID); - srank_id <= GetAlertLogID("Sample Rank", ALERTLOG_BASE_ID); - grank_id <= GetAlertLogID("Generation Rank", ALERTLOG_BASE_ID); - agrank_id <= GetAlertLogID("Absolute Generation Rank", ALERTLOG_BASE_ID); - eoc_id <= GetAlertLogID("End of Collection", ALERTLOG_BASE_ID); - valid_id <= GetAlertLogID("Valid Data", ALERTLOG_BASE_ID); - data_id <= GetAlertLogID("Data Out", ALERTLOG_BASE_ID); - ret_id <= GetAlertLogID("Return Code", ALERTLOG_BASE_ID); - status_id <= GetAlertLogID("Communication Status", ALERTLOG_BASE_ID); - - -- Key Hashes - kh3 := (x"0CEAB0C6", x"FA04B9AD", x"A96EB495", x"4E0EB999"); - kh4 := (x"A7EB605C", x"FF4BEF3A", x"3C5E8724", x"CCA0CA67"); - kh2 := (x"BC070AC4", x"0BAB5811", x"14EA8D61", x"F669189B"); - kh1 := (x"F12C31DA", x"E3FE0F3F", x"01F36685", x"446518CA"); - kh5 := gen_key_hash; - - - - Log("Initiating Test", INFO); - reset <= '1'; - wait until rising_edge(clk); - wait until rising_edge(clk); - reset <= '0'; - -- MEM: 0, 0, 0, 0 - -- ISTATE: - - -- WRITER: - - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh1; - cc.payload := gen_payload(kh1,10); - cc.src_timestamp := gen_duration(1,0); - - -- TEST: NORMAL ADD_CACHE_CHANGE - -- TEST: SAMPLE WITH ALIGNED PAYLOAD - -- TEST: NORMAL SAMPLE [UNKNOWN INSTANCE] - -- TEST: SAMPLE WITH KEY_HASH - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Aligned Payload] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - rtps.ret_code := OK; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S1, 0, 0, 0 - -- ISTATE: I1:ALIVE - -- WRITER: W0:I1 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := HANDLE_NIL; - cc.payload := gen_payload(kh1,18); - cc.src_timestamp := gen_duration(2,0); - - -- TEST: SAMPLE WITHOUT KEY_HASH - -- TEST: SAMPLE WITH UNALIGNED PAYLOAD [>1 SLOT] - -- TEST: NORMAL SAMPLE [KNOWN INSTANCE] - - Log("RTPS Operation ADD_CACHE_CHANGE [NO KEY_HASH, Instance 1, Writer 0, Unaligned Payload (2 Slots)] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - rtps.ret_code := OK; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - s.inst := kh1; - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S1, I1S2+, 0, 0 - -- ISTATE: I1:ALIVE - -- WRITER: W0:I1 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - -- VAILDATE STATE - - Log("DDS Operation READ [MAX_SAMPLES 4, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ; - dds.max_samples := 4; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - start_dds; - wait_on_dds; - wait_on_idle; - -- MEM: I1S1, I1S2+, 0, 0 - -- ISTATE: I1:ALIVE - -- WRITER: W0:I1 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_DISPOSED; - cc.instance := kh1; - cc.payload := gen_payload(kh1,5); - cc.src_timestamp := gen_duration(3,0); - - -- TEST: ADD SAMPLE ON MAX_SAMPLES_PER_INSTANCE - - Log("RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Instance 1, Writer 0] (REJECTED: MAX_SAMPLES_PER_INSTANCE exceeded)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - rtps.ret_code := REJECTED; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S1, I1S2+, 0, 0 - -- ISTATE: I1:ALIVE - -- WRITER: W0:I1 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - Log("DDS Operation TAKE [MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE; - dds.max_samples := 1; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - start_dds; - wait_on_dds; - wait_on_idle; - -- MEM: I1S2+, 0, 0, 0 - -- ISTATE: I1:ALIVE - -- WRITER: W0:I1 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - -- TEST: DISPOSE SAMPLE [KNOWN INSTANCE] - -- TEST: SAMPLE WITH SERIALIZED KEY [WITH KEY_HASH] - -- TEST: SAMPLE WITH UNALIGNED PAYLOAD [<1 SLOT] - - Log("RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Instance 1, Writer 0] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - rtps.ret_code := OK; - s := to_sample(cc,NOT_ALIVE_DISPOSED_INSTANCE_STATE); - s.inst := kh1; - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S2+, I1S3-, 0, 0 - -- ISTATE: I1:DISPOSED - -- WRITER: W0:I1 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh2; - cc.payload := gen_payload(kh2,20); - cc.src_timestamp := gen_duration(4,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 2, Writer 1, Aligned Payload (2 Slots)] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 1; - rtps.ret_code := OK; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S2+, I1S3-, I2S1+, 0 - -- ISTATE: I1:DISPOSED, I2:ALIVE - -- WRITER: W0:I1, W1:I2 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh3; - cc.payload := gen_payload(kh3,10); - cc.src_timestamp := gen_duration(5,0); - - -- TEST: TEST SAMPLE WITH SERIALIZED KEY EFFECT ON PAYLOAD MEMORY FULLNESS - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 3, Writer 1, Aligned Payload] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 1; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S2+, I1S3-, I2S1+, I3S1 - -- ISTATE: I1:DISPOSED, I2:ALIVE, I3: ALIVE - -- WRITER: W0:I1, W1:I2,I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - -- TEST: REMOVE_WRITER [UNKNOWN WRITER] - - Log("RTPS Operation REMOVE_WRITER [Writer 2] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := REMOVE_WRITER; - rtps.writer_pos := 2; - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S2+, I1S3-, I2S1+, I3S1 - -- ISTATE: I1:DISPOSED, I2:ALIVE, I3: ALIVE - -- WRITER: W0:I1, W1:I2,I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - Log("DDS Operation TAKE [MAX_SAMPLES 1, NOT_READ_SAMPLE_STATE, NOT_ALIVE_DISPOSED_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE; - dds.max_samples := 1; - dds.sstate := NOT_READ_SAMPLE_STATE; - dds.istate := NOT_ALIVE_DISPOSED_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - start_dds; - wait_on_dds; - wait_on_idle; - -- MEM: I1S2+, I2S1+, I3S1, 0 - -- ISTATE: I1:DISPOSED, I2:ALIVE, I3: ALIVE - -- WRITER: W0:I1, W1:I2,I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh3; - cc.payload := gen_payload(kh3,10); - cc.src_timestamp := gen_duration(6,0); - - -- TEST: ADD_CACHE_CHANGE ON PAYLOAD MEMORY FULL - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 3, Writer 2, Aligned Payload] (REJECTED: Payload Memory Full)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 2; - rtps.ret_code := REJECTED; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S2+, I2S1+, I3S1, 0 - -- ISTATE: I1:DISPOSED, I2:ALIVE, I3: ALIVE - -- WRITER: W0:I1, W1:I2,I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - Log("DDS Operation TAKE [MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE; - dds.max_samples := 1; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - start_dds; - wait_on_dds; - wait_on_idle; - -- MEM: I2S1+, I3S1, 0, 0 - -- ISTATE: I1:DISPOSED, I2:ALIVE, I3: ALIVE - -- WRITER: W0:I1, W1:I2,I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 3, Writer 2, Aligned Payload] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 2; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I2S1+, I3S1, I3S2, 0 - -- ISTATE: I1:DISPOSED, I2:ALIVE, I3: ALIVE - -- WRITER: W0:I1, W1:I2,I3, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh4; - cc.payload := gen_payload(kh4,10); - cc.src_timestamp := gen_duration(7,0); - - -- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKOWN INSTANCE, WITHOUT STALE INSTANCE, WITH EMPTY INSTANCE] - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 4, Writer 1, Aligned Payload] (REJECTED: MAX_INSTANCES exceeded)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 1; - rtps.ret_code := REJECTED; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I2S1+, I3S1, I3S2, 0 - -- ISTATE: I1:DISPOSED, I2:ALIVE, I3: ALIVE - -- WRITER: W0:I1, W1:I2,I3, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - -- TEST: REMOVE_WRITER [KNOWN WRITER (1 Instance)] - - Log("RTPS Operation REMOVE_WRITER [Writer 0] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := REMOVE_WRITER; - rtps.writer_pos := 0; - change_istate(kh1, NOT_ALIVE_NO_WRITERS_INSTANCE_STATE, mem); - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I2S1+, I3S1, I3S2, 0 - -- ISTATE: I1:DISPOSED, I2:ALIVE, I3: ALIVE - -- WRITER: W1:I2,I3, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - -- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKOWN INSTANCE, WITH STALE INSTANCE] - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 4, Writer 1, Aligned Payload] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 1; - remove_inst(kh1, mem); - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I2S1+, I3S1, I3S2, I4S1 - -- ISTATE: I2:ALIVE, I3: ALIVE, I4:ALIVE - -- WRITER: W1:I2,I3,I4, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - -- VALIDATE STATE - - Log("DDS Operation READ [MAX_SAMPLES 4, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ; - dds.max_samples := 4; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - start_dds; - wait_on_dds; - wait_on_idle; - -- MEM: I2S1+, I3S1, I3S2, I4S1 - -- ISTATE: I2:ALIVE, I3: ALIVE, I4:ALIVE - -- WRITER: W1:I2,I3,I4, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - Log("DDS Operation TAKE [MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE; - dds.max_samples := 1; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - start_dds; - wait_on_dds; - wait_on_idle; - -- MEM: I3S1, I3S2, I4S1, 0 - -- ISTATE: I2:ALIVE, I3: ALIVE, I4:ALIVE - -- WRITER: W1:I2,I3,I4, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh1; - cc.payload := gen_payload(kh1,10); - cc.src_timestamp := gen_duration(8,0); - - -- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKOWN INSTANCE, WITHOUT STALE INSTANCE] - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Aligned Payload] (REJECTED: MAX_INSTANCES exceeded)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - rtps.ret_code := REJECTED; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I3S1, I3S2, I4S1, 0 - -- ISTATE: I2:ALIVE, I3: ALIVE, I4:ALIVE - -- WRITER: W1:I2,I3,I4, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh4; - cc.payload := gen_payload(kh4,10); - cc.src_timestamp := gen_duration(9,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 4, Writer 1, Aligned Payload] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 1; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I3S1, I3S2, I4S1, I4S2 - -- ISTATE: I2:ALIVE, I3: ALIVE, I4:ALIVE - -- WRITER: W1:I2,I3,I4, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh2; - cc.payload := gen_payload(kh2,10); - cc.src_timestamp := gen_duration(10,0); - - -- TEST: ADD SAMPLE ON MAX_SAMPLES [KNOWN INSTANCE] - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 2, Writer 1, Aligned Payload] (REJECTED: MAX_SAMPLES exceeded)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 1; - rtps.ret_code := REJECTED; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I3S1, I3S2, I4S1, I4S2 - -- ISTATE: I2:ALIVE, I3: ALIVE, I4:ALIVE - -- WRITER: W1:I2,I3,I4, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh1; - cc.payload := gen_payload(kh1,10); - cc.src_timestamp := gen_duration(11,0); - - -- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE, WITHOUT STALE INSTANCE] - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Aligned Payload] (REJECTED: MAX_SAMPLES exceeded)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - rtps.ret_code := REJECTED; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I3S1, I3S2, I4S1, I4S2 - -- ISTATE: I2:ALIVE, I3: ALIVE, I4:ALIVE - -- WRITER: W1:I2,I3,I4, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - -- TEST: REMOVE_WRITER [KNOWN WRITER (>1 Instances)] - -- TEST: REMOVE_WRITER [NOT_ALIVE_NO_WRITERS Transition] - -- TEST: REMOVE_WRITER [Multiple Pending NOT_ALIVE_NO_WRITERS Transitions] - -- TEST: REMOVE_WRITER ON MAX_SAMPLES [NOT_ALIVE_NO_WRITERS Transition] - -- TEST: REMOVE_WRITER ON MAX_SAMPLES_PER_INSTANCE [NOT_ALIVE_NO_WRITERS Transition] - - Log("RTPS Operation REMOVE_WRITER [Writer 1] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := REMOVE_WRITER; - rtps.writer_pos := 1; - change_istate(kh2, NOT_ALIVE_NO_WRITERS_INSTANCE_STATE, mem); - change_istate(kh4, NOT_ALIVE_NO_WRITERS_INSTANCE_STATE, mem); - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I3S1, I3S2, I4S1, I4S2 - -- ISTATE: I2:NO_WRITER, I3: ALIVE, I4:NO_WRITER - -- WRITER: W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_UNREGISTERED; - cc.instance := kh2; - cc.src_timestamp := check_time; - - Log("DDS Operation TAKE [MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE; - dds.max_samples := 1; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - s := to_sample(cc,NOT_ALIVE_NO_WRITERS_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_dds; - wait_on_dds; - wait_on_idle; - -- MEM: I3S2, I4S1, I4S2, I2S2- - -- ISTATE: I2:NO_WRITER, I3: ALIVE, I4:NO_WRITER - -- WRITER: W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - -- NOTE: We read the current KH4 Samples, so that we can easiy remove the new KH4 Sample - Log("DDS Operation READ_INSTANCE [Instance 4, MAX_SAMPLES 2, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ_INSTANCE; - dds.max_samples := 2; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.inst := kh4; - start_dds; - wait_on_dds; - wait_on_idle; - -- MEM: I3S2, I4S1, I4S2, I2S2- - -- ISTATE: I2:NO_WRITER, I3: ALIVE, I4:NO_WRITER - -- WRITER: W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_UNREGISTERED; - cc.instance := kh4; - cc.src_timestamp := check_time; - - Log("DDS Operation TAKE_INSTANCE [Instance 4, MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE_INSTANCE; - dds.max_samples := 1; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.inst := kh4; - s := to_sample(cc,NOT_ALIVE_NO_WRITERS_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_dds; - wait_on_dds; - wait_on_idle; - -- MEM: I3S2, I4S2, I2S2-, I4S3- - -- ISTATE: I2:NO_WRITER, I3: ALIVE, I4:NO_WRITER - -- WRITER: W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - Log("DDS Operation TAKE_INSTANCE [Instance 4, MAX_SAMPLES 1, NOT_READ_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE_INSTANCE; - dds.max_samples := 1; - dds.sstate := NOT_READ_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.inst := kh4; - start_dds; - wait_on_dds; - wait_on_idle; - -- MEM: I3S2, I4S2, I2S2-, 0 - -- ISTATE: I2:NO_WRITER, I3: ALIVE, I4:NO_WRITER - -- WRITER: W2:I3 - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_DISPOSED; - cc.instance := HANDLE_NIL; - cc.payload := gen_payload(kh4,5); - cc.src_timestamp := gen_duration(12,0); - - -- TEST: DISPOSE SAMPLE [NOT_ALIVE_NO_WRITERS INSTANCE] - -- TEST: SAMPLE WITH SERIALIZED KEY [WITHOUT KEY_HASH] - - Log("RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Instance 4, Writer 1] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 1; - s := to_sample(cc,NOT_ALIVE_DISPOSED_INSTANCE_STATE); - s.inst := kh4; - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I3S2, I4S2, I2S2-, I4S4- - -- ISTATE: I2:NO_WRITER, I3: ALIVE, I4:DISPOSED - -- WRITER: W1:I4, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh1; - cc.payload := gen_payload(kh1,10); - cc.src_timestamp := gen_duration(13,0); - - -- TEST: ADD SAMPLE ON MAX_SAMPLES [UNKNOWN INSTANCE] - -- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE, WITH STALE INSTANCE] - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Aligned Payload] (REJECTED: MAX_SAMPLES exceeded)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - rtps.ret_code := REJECTED; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I3S2, I4S2, I2S2-, I4S4- - -- ISTATE: I2:NO_WRITER, I3: ALIVE, I4:DISPOSED - -- WRITER: W1:I4, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - Log("DDS Operation TAKE [MAX_SAMPLES 2, NOT_READ_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE; - dds.max_samples := 2; - dds.sstate := NOT_READ_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - start_dds; - wait_on_dds; - wait_on_idle; - -- MEM: I3S2, I4S2, 0, 0 - -- ISTATE: I2:NO_WRITER, I3: ALIVE, I4:DISPOSED - -- WRITER: W1:I4, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh3; - cc.payload := gen_payload(kh3,10); - cc.src_timestamp := gen_duration(14,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 3, Writer 2, Aligned Payload] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 2; - rtps.ret_code := OK; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I3S2, I4S2, I3S3, 0 - -- ISTATE: I2:NO_WRITER, I3: ALIVE, I4:DISPOSED - -- WRITER: W1:I4, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh1; - cc.payload := gen_payload(kh1,30); - cc.src_timestamp := gen_duration(15,0); - - -- TEST: ADD SAMPLE BIGGER THAN AVAILABLE MEMORY SPACE - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Aligned Payload (3 Slots)] (REJECTED: Payload Memory Full)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - rtps.ret_code := REJECTED; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I3S2, I4S2, I3S3, 0 - -- ISTATE: I2:NO_WRITER, I3: ALIVE, I4:DISPOSED - -- WRITER: W1:I4, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh1; - cc.payload := gen_payload(kh1,20); - cc.src_timestamp := gen_duration(16,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Aligned Payload (2 Slots)] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - remove_inst(kh2, mem); - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I3S2, I4S2, I3S3, I1S1+ - -- ISTATE: I1:ALIVE, I3: ALIVE, I4:DISPOSED - -- WRITER: W0:I1, W1:I4, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - -- VALIDATE STATE - - Log("DDS Operation TAKE [MAX_SAMPLES 4, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE; - dds.max_samples := 4; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - start_dds; - wait_on_dds; - wait_on_idle; - -- MEM: 0, 0, 0, 0 - -- ISTATE: I1:ALIVE, I3: ALIVE, I4:DISPOSED - -- WRITER: W0:I1, W1:I4, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_DISPOSED; - cc.instance := kh4; - cc.payload := gen_payload(kh4,5); - cc.src_timestamp := gen_duration(17,0); - - -- TEST: DISPOSE SAMPLE [NOT_ALIVE_DISPOSED INSTANCE] - - Log("RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Instance 4, Writer 0] (IGNORED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: 0, 0, 0, 0 - -- ISTATE: I1:ALIVE, I3: ALIVE, I4:DISPOSED - -- WRITER: W0:I1,I4 W1:I4, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_UNREGISTERED; - cc.instance := kh4; - cc.payload := gen_payload(kh4,5); - cc.src_timestamp := gen_duration(18,0); - - -- TEST: UNREGISTER SAMPLE [KNOWN INSTANCE, KNOWN WRITER] - -- TEST: UNREGISTER SAMPLE [NOT_ALIVE_DISPOSED INSTANCE] - - Log("RTPS Operation ADD_CACHE_CHANGE [UNREGISTER, Instance 4, Writer 0] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: 0, 0, 0, 0 - -- ISTATE: I1:ALIVE, I3: ALIVE, I4:DISPOSED - -- WRITER: W0:I1 W1:I4, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_UNREGISTERED; - cc.instance := kh1; - cc.payload := gen_payload(kh1,5); - cc.src_timestamp := gen_duration(19,0); - - -- TEST: UNREGISTER SAMPLE [KNOWN INSTANCE, UNKNOWN WRITER] - - Log("RTPS Operation ADD_CACHE_CHANGE [UNREGISTER, Instance 1, Writer 1] (IGNORED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 1; - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: 0, 0, 0, 0 - -- ISTATE: I1:ALIVE, I3: ALIVE, I4:DISPOSED - -- WRITER: W0:I1 W1:I4, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_UNREGISTERED; - cc.instance := kh2; - cc.payload := gen_payload(kh2,5); - cc.src_timestamp := gen_duration(20,0); - - -- TEST: UNREGISTER SAMPLE [UNKNOWN INSTANCE] - - Log("RTPS Operation ADD_CACHE_CHANGE [UNREGISTER, Instance 2, Writer 1] (IGNORED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 1; - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: 0, 0, 0, 0 - -- ISTATE: I1:ALIVE, I3: ALIVE, I4:DISPOSED - -- WRITER: W0:I1 W1:I4, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_UNREGISTERED; - cc.instance := kh1; - cc.payload := gen_payload(kh1,5); - cc.src_timestamp := gen_duration(21,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [UNREGISTER, Instance 1, Writer 0] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - s := to_sample(cc,NOT_ALIVE_NO_WRITERS_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S2-, 0, 0, 0 - -- ISTATE: I1:NO_WRITERS, I3: ALIVE, I4:DISPOSED - -- WRITER: W1:I4, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_UNREGISTERED; - cc.instance := kh1; - cc.payload := gen_payload(kh1,5); - cc.src_timestamp := gen_duration(22,0); - - -- TEST: UNREGISTER SAMPLE [NOT_ALIVE_NO_WRITERS INSTANCE] - - Log("RTPS Operation ADD_CACHE_CHANGE [UNREGISTER, Instance 1, Writer 2] (IGNORED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 2; - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S2-, 0, 0, 0 - -- ISTATE: I1:NO_WRITERS, I3: ALIVE, I4:DISPOSED - -- WRITER: W1:I4, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := ALIVE_FILTERED; - cc.instance := kh1; - cc.payload := gen_payload(kh1,5); - cc.src_timestamp := gen_duration(23,0); - - -- TEST: FILTER SAMPLE [KNOWN INSTANCE] - -- TEST: FILTER SAMPLE [NOT_ALIVE_NO_WRITERS INSTANCE] - - Log("RTPS Operation ADD_CACHE_CHANGE [FILTERED, Instance 1, Writer 2] (ACCEPT)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - rtps.writer_pos := 2; - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S2-, I1S3-, 0, 0 - -- ISTATE: I1:ALIVE, I3: ALIVE, I4:DISPOSED - -- WRITER: W1:I4, W2:I1,I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_UNREGISTERED; - cc.instance := kh4; - cc.payload := gen_payload(kh1,5); - cc.src_timestamp := gen_duration(24,0); - - -- TEST: UNREGISTER SAMPLE [NOT_ALIVE_DISPOSED INSTANCE, STALE INSTANCE TRANSITION] - - Log("RTPS Operation ADD_CACHE_CHANGE [UNREGISTER, Instance 4, Writer 1] (ACCEPT)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 1; - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S2-, I1S3-, 0, 0 - -- ISTATE: I1:ALIVE, I3: ALIVE, I4:DISPOSED - -- WRITER: W2:I1,I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh2; - cc.payload := gen_payload(kh2,10); - cc.src_timestamp := gen_duration(25,0); - - -- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKOWN INSTANCE, NOT_ALIVE_DISPOSED & STALE INSTANCE] - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 2, Writer 0, Aligned Payload] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - remove_inst(kh4, mem); - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S2-, I1S3-, I2S1, 0 - -- ISTATE: I1:ALIVE, I2:ALIVE, I3: ALIVE - -- WRITER: W0:I2, W2:I1,I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - -- VALIDATE STATE - - Log("DDS Operation TAKE [MAX_SAMPLES 4, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE; - dds.max_samples := 4; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - start_dds; - wait_on_dds; - wait_on_idle; - -- MEM: 0, 0, 0, 0 - -- ISTATE: I1:ALIVE, I2:ALIVE, I3: ALIVE - -- WRITER: W0:I2, W2:I1,I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_DISPOSED; - cc.instance := kh1; - cc.payload := gen_payload(kh1,5); - cc.src_timestamp := gen_duration(26,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Instance 1, Writer 2] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 2; - s := to_sample(cc,NOT_ALIVE_DISPOSED_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S4-, 0, 0, 0 - -- ISTATE: I1:DISPOSED, I2:ALIVE, I3: ALIVE - -- WRITER: W0:I2, W2:I1,I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := ALIVE_FILTERED; - cc.instance := kh1; - cc.payload := gen_payload(kh1,5); - cc.src_timestamp := gen_duration(27,0); - - -- TEST: FILTER SAMPLE [NOT_ALIVE_DISPOSED INSTANCE] - - Log("RTPS Operation ADD_CACHE_CHANGE [FILTERED, Instance 1, Writer 2] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - rtps.writer_pos := 2; - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S4-, I1S5-, 0, 0 - -- ISTATE: I1:ALIVE, I2:ALIVE, I3: ALIVE - -- WRITER: W0:I2, W2:I1,I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := ALIVE_FILTERED; - cc.instance := kh4; - cc.payload := gen_payload(kh4,5); - cc.src_timestamp := gen_duration(28,0); - - -- TEST: FILTER SAMPLE [UNKNOWN INSTANCE] - - Log("RTPS Operation ADD_CACHE_CHANGE [FILTERED, Instance 4, Writer 1] (IGNORED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 1; - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S4-, I1S5-, 0, 0 - -- ISTATE: I1:ALIVE, I2:ALIVE, I3: ALIVE - -- WRITER: W0:I2, W2:I1,I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - -- TEST: SAMPLE WITH EARLY TIMESTAMP [TIMESTAMP EARLIER THAN LAST READ] - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh3; - cc.payload := gen_payload(kh3,10); - cc.src_timestamp := gen_duration(10,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 3, Writer 2, Aligned Payload] (IGNORED: Timestamp earlier than last read)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 2; - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S4-, I1S5-, 0, 0 - -- ISTATE: I1:ALIVE, I2:ALIVE, I3: ALIVE - -- WRITER: W0:I2, W2:I1,I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_UNREGISTERED; - cc.instance := kh2; - cc.payload := gen_payload(kh2,5); - cc.src_timestamp := gen_duration(29,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [UNREGISTER, Instance 2, Writer 0] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - s := to_sample(cc,NOT_ALIVE_NO_WRITERS_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S4-, I1S5-, I2S2-, 0 - -- ISTATE: I1:ALIVE, I2:NO_WRITERS, I3: ALIVE - -- WRITER: W2:I1,I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - -- VALIDATE STATE - - Log("DDS Operation TAKE [MAX_SAMPLES 4, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE; - dds.max_samples := 4; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - start_dds; - wait_on_dds; - wait_on_idle; - -- MEM: 0, 0, 0, 0 - -- ISTATE: I1:ALIVE, I2:NO_WRITERS, I3: ALIVE - -- WRITER: W2:I1,I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_DISPOSED; - cc.instance := kh4; - cc.payload := gen_payload(kh4,5); - cc.src_timestamp := gen_duration(30,0); - - -- TEST: DISPOSE SAMPLE [UNKNOWN INSTANCE] - - Log("RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Instance 4, Writer 1] (ACCPETED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 1; - s := to_sample(cc,NOT_ALIVE_DISPOSED_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I4S1-, 0, 0, 0 - -- ISTATE: I1:ALIVE, I3: ALIVE, I4:DISPOSED - -- WRITER: W1:I4, W2:I1,I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - -- VALIDATE STATE - - Log("DDS Operation READ [MAX_SAMPLES 4, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE; - dds.max_samples := 4; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := NOT_ALIVE_DISPOSED_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - start_dds; - wait_on_dds; - wait_on_idle; - -- MEM: I4S1-, 0, 0, 0 - -- ISTATE: I1:ALIVE, I3: ALIVE, I4:DISPOSED - -- WRITER: W1:I4, W2:I1,I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - wait_on_completion; - TranscriptOpen(RESULTS_FILE, APPEND_MODE); - SetTranscriptMirror; - ReportAlerts; - TranscriptClose; - std.env.stop; - wait; - end process; - - clock_prc : process - begin - clk <= '0'; - wait for 25 ns; - clk <= '1'; - wait for 25 ns; - end process; - - alert_prc : process(all) - begin - if rising_edge(clk) then - -- TODO - end if; - end process; - - dds_prc : process(all) - variable col : COLLECTION_TYPE := DEFAULT_COLLECTION; - begin - if rising_edge(clk) then - dds_done <= '0'; - case (dds_stage ) is - when IDLE => - if (dds_start = '1') then - dds_stage <= START; - else - dds_done <= '1'; - end if; - when START => - if (ack_dds = '1') then - dds_stage <= DONE; - dds_cnt <= 0; - end if; - when DONE => - if (done_dds = '1') then - AffirmIfEqual(ret_id, return_code_dds, dds.ret_code); - case (dds.ret_code) is - when RETCODE_OK => - gen_collection(mem, col, dds, INSTANCE_PRESENTATION_QOS, FALSE); - dds_stage <= CHECK_SI; - dds_cnt <= 0; - when others => - dds_stage <= IDLE; - end case; - end if; - when CHECK_SI => - if (si_valid = '1') then - AffirmIfEqual(sstate_id, si_sample_state, col.s(dds_cnt).sstate); - AffirmIfEqual(vstate_id, si_view_state, col.s(dds_cnt).vstate); - AffirmIfEqual(istate_id, si_instance_state, col.s(dds_cnt).istate); - AffirmIfEqual(ts_id, to_unsigned(si_source_timestamp), to_unsigned(col.s(dds_cnt).ts)); - AffirmIfEqual(inst_id, to_unsigned(si_instance_handle), to_unsigned(col.s(dds_cnt).inst)); - AffirmIfEqual(pub_id, to_unsigned(si_publication_handle), to_unsigned(HANDLE_NIL)); - AffirmIfEqual(dis_gen_cnt_id, si_disposed_generation_count, std_logic_vector(to_unsigned(col.s(dds_cnt).dis_gen_cnt,WORD_WIDTH))); - AffirmIfEqual(no_w_gen_cnt_id, si_no_writers_generation_count, std_logic_vector(to_unsigned(col.s(dds_cnt).no_w_gen_cnt,WORD_WIDTH))); - AffirmIfEqual(srank_id, si_sample_rank, std_logic_vector(to_unsigned(col.s(dds_cnt).srank,WORD_WIDTH))); - AffirmIfEqual(grank_id, si_generation_rank, std_logic_vector(to_unsigned(col.s(dds_cnt).grank,WORD_WIDTH))); - AffirmIfEqual(agrank_id, si_absolute_generation_rank, std_logic_vector(to_unsigned(col.s(dds_cnt).agrank,WORD_WIDTH))); - if (si_valid_data = '1') then - AffirmIf(valid_id, col.s(dds_cnt).data /= EMPTY_TEST_PACKET, "Sample with Data not expected"); - dds_stage <= CHECK_DATA; - dds_cnt2 <= 0; - else - AffirmIf(valid_id, col.s(dds_cnt).data = EMPTY_TEST_PACKET, "Sample with Data expected"); - if (dds_cnt = col.len-1) then - -- DONE - dds_stage <= WAIT_EOC; - else - dds_cnt <= dds_cnt + 1; - end if; - end if; - end if; - AffirmIf(eoc_id, eoc = '0', "EOC pulled high"); - when CHECK_DATA => - if (valid_out_dds = '1') then - AffirmIfEqual(data_id, data_out_dds, col.s(dds_cnt).data.data(dds_cnt2)); - dds_cnt2 <= dds_cnt2 + 1; - if (dds_cnt2 = col.s(dds_cnt).data.length-1) then - AlertIf(data_id, last_word_out_dds /= '1', "Last Word Signal not pulled High", ERROR); - if (dds_cnt = col.len-1) then - -- DONE - dds_stage <= WAIT_EOC; - else - dds_stage <= CHECK_SI; - dds_cnt <= dds_cnt + 1; - end if; - end if; - end if; - when WAIT_EOC => - if (eoc = '1') then - dds_stage <= IDLE; - end if; - end case; - end if; - - -- DEFAULT - start_dds <= '0'; - opcode_dds <= NOP; - instance_state_dds <= ANY_INSTANCE_STATE; - view_state_dds <= ANY_VIEW_STATE; - sample_state_dds <= ANY_SAMPLE_STATE; - instance_handle_dds <= HANDLE_NIL; - max_samples_dds <= (others => '0'); - get_data_dds <= '0'; - ready_out_dds <= '0'; - - - case (dds_stage ) is - when START => - start_dds <= '1'; - opcode_dds <= dds.opcode; - instance_state_dds <= dds.istate; - view_state_dds <= dds.vstate; - sample_state_dds <= dds.sstate; - instance_handle_dds <= dds.inst; - max_samples_dds <= std_logic_vector(to_unsigned(dds.max_samples, WORD_WIDTH)); - when CHECK_SI => - if (si_valid = '1' and si_valid_data = '1') then - get_data_dds <= '1'; - end if; - when CHECK_DATA => - ready_out_dds <= '1'; - when others => - null; - end case; - end process; - - rtps_prc : process(all) - variable stimulus : TEST_PACKET_TYPE := EMPTY_TEST_PACKET; - begin - if rising_edge(clk) then - rtps_done <= '0'; - case (rtps_stage) is - when IDLE => - if (rtps_start = '1') then - rtps_stage <= START; - else - rtps_done <= '1'; - end if; - when START => - if (ack_rtps = '1') then - case (rtps.opcode) is - when ADD_CACHE_CHANGE => - gen_add_cache_change_dds(rtps.cc, rtps.lifespan, rtps.writer_pos, stimulus); - rtps_stage <= PUSH; - when others => - rtps_stage <= DONE; - end case; - end if; - when PUSH => - if (ready_in_rtps = '1') then - rtps_cnt <= rtps_cnt + 1; - if (rtps_cnt = stimulus.length-1) then - rtps_stage <= DONE; - end if; - end if; - when DONE => - if (done_rtps = '1') then - AffirmIfEqual(ret_id, HISTORY_CACHE_RESPONSE_TYPE'pos(ret_rtps), HISTORY_CACHE_RESPONSE_TYPE'pos(rtps.ret_code)); - rtps_stage <= IDLE; - end if; - end case; - end if; - - -- DEFAULT - start_rtps <= '0'; - opcode_rtps <= NOP; - valid_in_rtps <= '0'; - last_word_in_rtps <= '0'; - data_in_rtps <= (others => '0'); - - case (rtps_stage) is - when START => - start_rtps <= '1'; - opcode_rtps <= rtps.opcode; - case (rtps.opcode) is - when REMOVE_WRITER => - data_in_rtps <= std_logic_vector(to_unsigned(rtps.writer_pos,WORD_WIDTH)); - when others => - null; - end case; - when PUSH => - valid_in_rtps <= '1'; - data_in_rtps <= stimulus.data(rtps_cnt); - last_word_in_rtps <= stimulus.last(rtps_cnt); - when others => - null; - end case; - end process; - - watchdog : process - begin - wait for 1 ms; - Alert("Test timeout", FAILURE); - std.env.stop; - end process; - -end architecture; \ No newline at end of file diff --git a/src/Tests/Level_0/L0_dds_reader_test1_arznriu.vhd b/src/Tests/Level_0/L0_dds_reader_test1_arznriu.vhd deleted file mode 100644 index 85602dd..0000000 --- a/src/Tests/Level_0/L0_dds_reader_test1_arznriu.vhd +++ /dev/null @@ -1,1145 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library osvvm; -- Utility Library -context osvvm.OsvvmContext; - -use work.rtps_package.all; -use work.user_config.all; -use work.rtps_config_package.all; -use work.rtps_test_package.all; - --- This testbench tests the RTPS handling of the DDS Reader. It tests the correctness of the RTPS ADD_CACHE_CHANGE, and REMOVE_WRITER Operations. --- Implicitly some DDS Operations are also tested, since they are used for state checking. --- More specifically the testbench covers following tests: --- TEST: NORMAL ADD_CACHE_CHANGE --- TEST: ADD_CACHE_CHANGE ON PAYLOAD MEMORY FULL --- TEST: REMOVE_WRITER [UNKNOWN WRITER] --- TEST: REMOVE_WRITER [KNOWN WRITER] --- TEST: REMOVE_WRITER [NOT_ALIVE_NO_WRITERS Transition] --- TEST: REMOVE_WRITER ON MAX_SAMPLES [NOT_ALIVE_NO_WRITERS Transition] --- TEST: SAMPLE WITH ALIGNED PAYLOAD --- TEST: SAMPLE WITH UNALIGNED PAYLOAD [<1 SLOT] --- TEST: SAMPLE WITH UNALIGNED PAYLOAD [>1 SLOT] --- TEST: NORMAL SAMPLE --- TEST: UNREGISTER SAMPLE [UNKNOWN WRITER] --- TEST: UNREGISTER SAMPLE [KNOWN WRITER] --- TEST: UNREGISTER SAMPLE [NOT_ALIVE_NO_WRITERS INSTANCE] --- TEST: UNREGISTER SAMPLE [NOT_ALIVE_DISPOSED INSTANCE] --- TEST: DISPOSE SAMPLE --- TEST: DISPOSE SAMPLE [NOT_ALIVE_NO_WRITERS INSTANCE] --- TEST: DISPOSE SAMPLE [NOT_ALIVE_DISPOSED INSTANCE] --- TEST: FILTER SAMPLE --- TEST: FILTER SAMPLE [NOT_ALIVE_DISPOSED INSTANCE] --- TEST: FILTER SAMPLE [NOT_ALIVE_NO_WRITERS INSTANCE] --- TEST: SAMPLE WITH EARLY TIMESTAMP [TIMESTAMP EARLIER THAN LAST READ] --- TEST: ADD SAMPLE ON MAX_SAMPLES --- TEST: ADD SAMPLE BIGGER THAN AVAILABLE MEMORY SPACE - -entity L0_dds_reader_test1_arznriu is -end entity; - - -architecture testbench of L0_dds_reader_test1_arznriu is - - -- *CONSTANT DECLARATION* - constant MAX_REMOTE_ENDPOINTS : natural := 3; - - -- *TYPE DECLARATION* - type DDS_STAGE_TYPE is (IDLE, START, DONE, CHECK_SI, CHECK_DATA, WAIT_EOC); - type RTPS_STAGE_TYPE is (IDLE, START, PUSH, DONE); - - -- *SIGNAL DECLARATION* - signal clk : std_logic := '0'; - signal reset : std_logic := '1'; - signal check_time : TIME_TYPE := TIME_ZERO; - signal start_rtps, start_dds, ack_rtps, ack_dds, done_rtps, done_dds : std_logic := '0'; - signal opcode_rtps : HISTORY_CACHE_OPCODE_TYPE := NOP; - signal opcode_dds : DDS_READER_OPCODE_TYPE := NOP; - signal ret_rtps : HISTORY_CACHE_RESPONSE_TYPE := ERROR; - signal ready_in_rtps, valid_in_rtps, last_word_in_rtps : std_logic := '0'; - signal ready_out_dds, valid_out_dds, last_word_out_dds : std_logic := '0'; - signal data_in_rtps, data_out_dds : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); - signal get_data_dds, si_valid_data, si_valid, eoc : std_logic := '0'; - signal return_code_dds : std_logic_vector(RETURN_CODE_WIDTH-1 downto 0) := (others => '0'); - signal status : std_logic_vector(STATUS_KIND_WIDTH-1 downto 0) := (others => '0'); - signal instance_state_dds, si_instance_state : std_logic_vector(INSTANCE_STATE_KIND_WIDTH-1 downto 0) := ANY_INSTANCE_STATE; - signal view_state_dds, si_view_state : std_logic_vector(VIEW_STATE_KIND_WIDTH-1 downto 0) := ANY_VIEW_STATE; - signal sample_state_dds, si_sample_state : std_logic_vector(SAMPLE_STATE_KIND_WIDTH-1 downto 0) := ANY_SAMPLE_STATE; - signal instance_handle_dds, si_instance_handle : INSTANCE_HANDLE_TYPE := HANDLE_NIL; - signal max_samples_dds : std_logic_vector(MAX_SAMPLES_WIDTH-1 downto 0) := (others => '0'); - signal si_source_timestamp : TIME_TYPE := TIME_INVALID; - signal si_publication_handle : INSTANCE_HANDLE_TYPE := HANDLE_NIL; - signal si_disposed_generation_count : std_logic_vector(DISPOSED_GENERATION_COUNT_WIDTH-1 downto 0) := (others => '0'); - signal si_no_writers_generation_count : std_logic_vector(NO_WRITERS_GENERATION_COUNT_WIDTH-1 downto 0) := (others => '0'); - signal si_sample_rank : std_logic_vector(SAMPLE_RANK_WIDTH-1 downto 0) := (others => '0'); - signal si_generation_rank : std_logic_vector(GENERATION_RANK_WIDTH-1 downto 0) := (others => '0'); - signal si_absolute_generation_rank: std_logic_vector(ABSOLUTE_GENERATION_COUNT_WIDTH-1 downto 0) := (others => '0'); - - signal dds_start , dds_done , rtps_start, rtps_done : std_logic := '0'; - signal dds_cnt, dds_cnt2, rtps_cnt : natural := 0; - signal dds_stage : DDS_STAGE_TYPE := IDLE; - signal rtps_stage : RTPS_STAGE_TYPE := IDLE; - shared variable dds : DDS_READER_TEST_TYPE := DEFAULT_DDS_READER_TEST; - shared variable rtps : RTPS_READER_TEST_TYPE := DEFAULT_RTPS_READER_TEST; - shared variable mem : DDS_READER_MEM_TYPE := DEFAULT_DDS_READER_MEM; - signal data_id, ret_id, sstate_id, vstate_id, istate_id, inst_id, ts_id, pub_id, dis_gen_cnt_id, no_w_gen_cnt_id, srank_id, grank_id, agrank_id, eoc_id, valid_id, status_id : AlertLogIDType; - - -- *FUNCTION DECLARATION* - function extract_key_hash (payload : TEST_PACKET_TYPE) return INSTANCE_HANDLE_TYPE is - variable ret : INSTANCE_HANDLE_TYPE := HANDLE_NIL; - begin - for i in 0 to 3 loop - ret(i) := not payload.data(i); - end loop; - - return ret; - end function; - - function gen_sn(input : natural) return SEQUENCENUMBER_TYPE is - variable ret : SEQUENCENUMBER_TYPE; - begin - ret(0) := (others => '0'); - ret(1) := unsigned(int(input, WORD_WIDTH)); - return ret; - end function; - -begin - - -- Unit Under Test - uut : entity work.dds_reader(arch) - generic map ( - TIME_BASED_FILTER_QOS => DURATION_ZERO, - DEADLINE_QOS => DURATION_INFINITE, - MAX_SAMPLES => std_logic_vector(to_unsigned(2,CDR_LONG_WIDTH)), - MAX_INSTANCES => std_logic_vector(to_unsigned(3,CDR_LONG_WIDTH)), - MAX_SAMPLES_PER_INSTANCE => std_logic_vector(to_unsigned(2,CDR_LONG_WIDTH)), - HISTORY_QOS => KEEP_ALL_HISTORY_QOS, - RELIABILITY_QOS => RELIABLE_RELIABILITY_QOS, - PRESENTATION_QOS => INSTANCE_PRESENTATION_QOS, - DESTINATION_ORDER_QOS => BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS, - COHERENT_ACCESS => FALSE, - ORDERED_ACCESS => FALSE, - WITH_KEY => FALSE, - PAYLOAD_FRAME_SIZE => 11, - MAX_REMOTE_ENDPOINTS => MAX_REMOTE_ENDPOINTS - ) - port map ( - clk => clk, - reset => reset, - time => check_time, - start_rtps => start_rtps, - opcode_rtps => opcode_rtps, - ack_rtps => ack_rtps, - done_rtps => done_rtps, - ret_rtps => ret_rtps, - data_in_rtps => data_in_rtps, - valid_in_rtps => valid_in_rtps, - ready_in_rtps => ready_in_rtps, - last_word_in_rtps => last_word_in_rtps, - start_dds => start_dds, - ack_dds => ack_dds, - opcode_dds => opcode_dds, - instance_state_dds => instance_state_dds, - view_state_dds => view_state_dds, - sample_state_dds => sample_state_dds, - instance_handle_dds => instance_handle_dds, - max_samples_dds => max_samples_dds, - get_data_dds => get_data_dds, - done_dds => done_dds, - return_code_dds => return_code_dds, - ready_out_dds => ready_out_dds, - valid_out_dds => valid_out_dds, - data_out_dds => data_out_dds, - last_word_out_dds => last_word_out_dds, - sample_info.sample_state => si_sample_state, - sample_info.view_state => si_view_state, - sample_info.instance_state => si_instance_state, - sample_info.source_timestamp => si_source_timestamp, - sample_info.instance_handle => si_instance_handle, - sample_info.publication_handle => si_publication_handle, - sample_info.disposed_generation_count => si_disposed_generation_count, - sample_info.no_writers_generation_count => si_no_writers_generation_count, - sample_info.sample_rank => si_sample_rank, - sample_info.generation_rank => si_generation_rank, - sample_info.absolute_generation_rank => si_absolute_generation_rank, - sample_info.valid_data => si_valid_data, - sample_info_valid => si_valid, - sample_info_ack => '1', - eoc => eoc, - status => status - ); - - stimulus_prc : process - variable RV : RandomPType; - variable cc : CACHE_CHANGE_TYPE := DEFAULT_CACHE_CHANGE; - variable s : SAMPLE_TYPE := DEFAULT_SAMPLE; - variable kh1: INSTANCE_HANDLE_TYPE := HANDLE_NIL; - - alias idle_sig is <>; - - impure function gen_payload(key_hash : INSTANCE_HANDLE_TYPE; len : natural) return TEST_PACKET_TYPE is - variable ret : TEST_PACKET_TYPE := EMPTY_TEST_PACKET; - begin - assert (len >= 4) report "Payload length has to be at least 16 Bytes long" severity FAILURE; - - for i in 0 to len-1 loop - if (i < 4) then - -- NOTE: Beginning of payload is negated key to allow deterministic Key Hash generation from the kh_prc - ret.data(ret.length) := not key_hash(i); - else - ret.data(ret.length) := RV.RandSlv(WORD_WIDTH); - end if; - ret.length := ret.length + 1; - end loop; - ret.last(ret.length-1) := '1'; - - return ret; - end function; - - impure function gen_key_hash return KEY_HASH_TYPE is - variable ret : KEY_HASH_TYPE := KEY_HASH_NIL; - begin - for i in 0 to KEY_HASH_TYPE'length-1 loop - ret(i) := RV.RandSlv(WORD_WIDTH); - end loop; - return ret; - end function; - - procedure start_dds is - begin - dds_start <= '1'; - wait until rising_edge(clk); - dds_start <= '0'; - wait until rising_edge(clk); - end procedure; - - procedure start_rtps is - begin - rtps_start <= '1'; - wait until rising_edge(clk); - rtps_start <= '0'; - wait until rising_edge(clk); - end procedure; - - procedure wait_on_dds is - begin - if (dds_done /= '1') then - wait until dds_done = '1'; - end if; - end procedure; - - procedure wait_on_rtps is - begin - if (rtps_done /= '1') then - wait until rtps_done = '1'; - end if; - end procedure; - - procedure wait_on_completion is - begin - if (rtps_done /= '1' or dds_done /= '1') then - wait until rtps_done = '1' and dds_done = '1'; - end if; - end procedure; - - -- NOTE: This procedure waits until the idle_sig is high for at least - -- two consecutive clock cycles. - procedure wait_on_idle is - variable first : boolean := TRUE; - begin - loop - if (idle_sig /= '1') then - wait until idle_sig = '1'; - elsif (not first) then - exit; - end if; - wait until rising_edge(clk); - wait until rising_edge(clk); - first := FALSE; - end loop; - end procedure; - - begin - - SetAlertLogName("L0_dds_reader_test1_arznriu - (KEEP ALL, Reliable, Zero TIME_BASED_FILTER, Keyless, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER, ACCESS SCOPE Instance, Unordered) - RTPS Handling"); - SetAlertEnable(FAILURE, TRUE); - SetAlertEnable(ERROR, TRUE); - SetAlertEnable(WARNING, TRUE); - SetLogEnable(DEBUG, FALSE); - SetLogEnable(PASSED, FALSE); - SetLogEnable(INFO, TRUE); - RV.InitSeed(RV'instance_name); - sstate_id <= GetAlertLogID("Sample State", ALERTLOG_BASE_ID); - vstate_id <= GetAlertLogID("View State", ALERTLOG_BASE_ID); - istate_id <= GetAlertLogID("Instance State", ALERTLOG_BASE_ID); - ts_id <= GetAlertLogID("Source Timestamp", ALERTLOG_BASE_ID); - inst_id <= GetAlertLogID("Instance Handle", ALERTLOG_BASE_ID); - pub_id <= GetAlertLogID("Publication Hanlde", ALERTLOG_BASE_ID); - dis_gen_cnt_id <= GetAlertLogID("Disposed Generation Count", ALERTLOG_BASE_ID); - no_w_gen_cnt_id <= GetAlertLogID("No Writers Generation Count", ALERTLOG_BASE_ID); - srank_id <= GetAlertLogID("Sample Rank", ALERTLOG_BASE_ID); - grank_id <= GetAlertLogID("Generation Rank", ALERTLOG_BASE_ID); - agrank_id <= GetAlertLogID("Absolute Generation Rank", ALERTLOG_BASE_ID); - eoc_id <= GetAlertLogID("End of Collection", ALERTLOG_BASE_ID); - valid_id <= GetAlertLogID("Valid Data", ALERTLOG_BASE_ID); - data_id <= GetAlertLogID("Data Out", ALERTLOG_BASE_ID); - ret_id <= GetAlertLogID("Return Code", ALERTLOG_BASE_ID); - status_id <= GetAlertLogID("Communication Status", ALERTLOG_BASE_ID); - - -- Key Hashes - kh1 := gen_key_hash; - - Log("Initiating Test", INFO); - reset <= '1'; - wait until rising_edge(clk); - wait until rising_edge(clk); - reset <= '0'; - -- MEM: 0, 0 - -- ISTATE: - - -- WRITER: - - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.payload := gen_payload(KEY_HASH_NIL,10); - cc.src_timestamp := gen_duration(1,0); - - -- TEST: NORMAL ADD_CACHE_CHANGE - -- TEST: NORMAL SAMPLE - -- TEST: SAMPLE WITH ALIGNED PAYLOAD - - Log("RTPS Operation ADD_CACHE_CHANGE [Writer 0, Aligned Payload] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - rtps.ret_code := OK; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: S1, 0 - -- ISTATE: ALIVE - -- WRITER: W0 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.payload := gen_payload(KEY_HASH_NIL,30); - cc.src_timestamp := gen_duration(2,0); - - -- TEST: ADD SAMPLE BIGGER THAN AVAILABLE MEMORY SPACE - - Log("RTPS Operation ADD_CACHE_CHANGE [Writer 0, Aligned Payload (3 Slots)] (REJECTED: Payload Memory exceeded)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - rtps.ret_code := REJECTED; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: S1, 0 - -- ISTATE: ALIVE - -- WRITER: W0 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.payload := gen_payload(KEY_HASH_NIL,18); - cc.src_timestamp := gen_duration(3,0); - - -- TEST: SAMPLE WITH UNALIGNED PAYLOAD [>1 SLOT] - - Log("RTPS Operation ADD_CACHE_CHANGE [Writer 0, Unaligned Payload (2 Slots)] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - rtps.ret_code := OK; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: S1, S2 - -- ISTATE: ALIVE - -- WRITER: W0 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.payload := gen_payload(KEY_HASH_NIL,10); - cc.src_timestamp := gen_duration(4,0); - - -- TEST: ADD SAMPLE ON MAX_SAMPLES - - Log("RTPS Operation ADD_CACHE_CHANGE [Writer 0, Aligned Payload] (REJECTED: MAX_SAMPLES exceeded)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - rtps.ret_code := REJECTED; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: S1, S2 - -- ISTATE: ALIVE - -- WRITER: W0 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - -- VALIDATE STATE - - Log("DDS Operation TAKE [MAX_SAMPLES 2, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE; - dds.max_samples := 2; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - start_dds; - wait_on_dds; - wait_on_idle; - -- MEM: 0, 0 - -- ISTATE: ALIVE - -- WRITER: W0 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := NOT_ALIVE_DISPOSED; - cc.src_timestamp := gen_duration(5,0); - - -- TEST: DISPOSE SAMPLE - - Log("RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Writer 0] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - rtps.ret_code := OK; - s := to_sample(cc,NOT_ALIVE_DISPOSED_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: S3-, 0 - -- ISTATE: DISPOSED - -- WRITER: W0 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := NOT_ALIVE_DISPOSED; - cc.src_timestamp := gen_duration(6,0); - - -- TEST: DISPOSE SAMPLE [NOT_ALIVE_DISPOSED INSTANCE] - - Log("RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Writer 0] (IGNORED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: S3-, 0 - -- ISTATE: DISPOSED - -- WRITER: W0 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE_FILTERED; - cc.src_timestamp := gen_duration(7,0); - - -- TEST: FILTER SAMPLE - -- TEST: FILTER SAMPLE [NOT_ALIVE_DISPOSED INSTANCE] - - Log("RTPS Operation ADD_CACHE_CHANGE [FILTERED, Writer 0] (IGNORED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - rtps.ret_code := OK; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: S3-, S4- - -- ISTATE: ALIVE - -- WRITER: W0 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - -- VALIDATE STATE - - Log("DDS Operation TAKE [MAX_SAMPLES 2, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE; - dds.max_samples := 2; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - start_dds; - wait_on_dds; - wait_on_idle; - -- MEM: 0, 0 - -- ISTATE: ALIVE - -- WRITER: W0 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.payload := gen_payload(KEY_HASH_NIL,30); - cc.src_timestamp := gen_duration(8,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [Writer 0, Aligned Payload (3 Slots)] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - rtps.ret_code := OK; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: S5++, 0 - -- ISTATE: ALIVE - -- WRITER: W0 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.payload := gen_payload(KEY_HASH_NIL,10); - cc.src_timestamp := gen_duration(9,0); - - -- TEST: ADD_CACHE_CHANGE ON PAYLOAD MEMORY FULL - - Log("RTPS Operation ADD_CACHE_CHANGE [Writer 0, Aligned Payload] (REJECTED: Payload Memory Full)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - rtps.ret_code := REJECTED; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: S5++, 0 - -- ISTATE: ALIVE - -- WRITER: W0 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - -- TEST: REMOVE_WRITER [UNKNOWN WRITER] - - Log("RTPS Operation REMOVE_WRITER [Writer 1] (IGNORED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := REMOVE_WRITER; - rtps.writer_pos := 1; - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: S5++, 0 - -- ISTATE: ALIVE - -- WRITER: W0 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - -- VALIDATE STATE - - Log("DDS Operation TAKE [MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE; - dds.max_samples := 1; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - start_dds; - wait_on_dds; - wait_on_idle; - -- MEM: 0, 0 - -- ISTATE: ALIVE - -- WRITER: W0 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - --------------------------------------------------------------------------- - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.payload := gen_payload(KEY_HASH_NIL,10); - cc.src_timestamp := gen_duration(10,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [Writer 0, Aligned Payload] (ACCPETED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - rtps.ret_code := OK; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: S6, 0 - -- ISTATE: ALIVE - -- WRITER: W0 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.payload := gen_payload(KEY_HASH_NIL,10); - cc.src_timestamp := gen_duration(11,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [Writer 0, Aligned Payload] (ACCPETED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - rtps.ret_code := OK; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: S6, S7 - -- ISTATE: ALIVE - -- WRITER: W0 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - -- TEST: REMOVE_WRITER [KNOWN WRITER] - -- TEST: REMOVE_WRITER [NOT_ALIVE_NO_WRITERS Transition] - -- TEST: REMOVE_WRITER ON MAX_SAMPLES [NOT_ALIVE_NO_WRITERS Transition] - - Log("RTPS Operation REMOVE_WRITER [Writer 0] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := REMOVE_WRITER; - rtps.writer_pos := 0; - change_istate(HANDLE_NIL, NOT_ALIVE_NO_WRITERS_INSTANCE_STATE, mem); - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: S6, S7 - -- ISTATE: NO_WRITERS - -- WRITER: - - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_UNREGISTERED; - cc.src_timestamp := check_time; - - Log("DDS Operation TAKE [MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE; - dds.max_samples := 1; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - s := to_sample(cc,NOT_ALIVE_NO_WRITERS_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_dds; - wait_on_dds; - wait_on_idle; - -- MEM: S7, S8- - -- ISTATE: NO_WRITERS - -- WRITER: - - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - Log("DDS Operation TAKE [MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE; - dds.max_samples := 1; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - start_dds; - wait_on_dds; - wait_on_idle; - -- MEM: S8-, 0 - -- ISTATE: NO_WRITERS - -- WRITER: - - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - -- TEST: FILTER SAMPLE [NOT_ALIVE_NO_WRITERS INSTANCE] - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE_FILTERED; - cc.src_timestamp := gen_duration(12,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [FILTERED, Writer 1] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 1; - rtps.ret_code := OK; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: S8-, S9- - -- ISTATE: ALIVE - -- WRITER: W1 - - -------------------------------------------------------------------------------------- - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - -- VALIDATE STATE - - Log("DDS Operation TAKE [MAX_SAMPLES 2, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE; - dds.max_samples := 2; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - start_dds; - wait_on_dds; - wait_on_idle; - -- MEM: 0, 0 - -- ISTATE: ALIVE - -- WRITER: W1 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := NOT_ALIVE_UNREGISTERED; - cc.src_timestamp := gen_duration(13,0); - - -- TEST: UNREGISTER SAMPLE [UNKNOWN WRITER] - - Log("RTPS Operation ADD_CACHE_CHANGE [UNREGISTER, Writer 0] (IGNORED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: 0, 0 - -- ISTATE: ALIVE - -- WRITER: W1 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := NOT_ALIVE_UNREGISTERED; - cc.src_timestamp := gen_duration(14,0); - - -- TEST: UNREGISTER SAMPLE [KNOWN WRITER] - - Log("RTPS Operation ADD_CACHE_CHANGE [UNREGISTER, Writer 1] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 1; - rtps.ret_code := OK; - s := to_sample(cc,NOT_ALIVE_NO_WRITERS_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: S10-, 0 - -- ISTATE: NO_WRITERS - -- WRITER: - - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := NOT_ALIVE_UNREGISTERED; - cc.src_timestamp := gen_duration(15,0); - - -- TEST: UNREGISTER SAMPLE [NOT_ALIVE_NO_WRITERS INSTANCE] - - Log("RTPS Operation ADD_CACHE_CHANGE [UNREGISTER, Writer 0] (IGNORED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: S10-, 0 - -- ISTATE: NO_WRITERS - -- WRITER: - - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := NOT_ALIVE_DISPOSED; - cc.src_timestamp := gen_duration(16,0); - - -- TEST: DISPOSE SAMPLE [NOT_ALIVE_NO_WRITERS INSTANCE] - - Log("RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Writer 0] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - rtps.ret_code := OK; - s := to_sample(cc,NOT_ALIVE_DISPOSED_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: S10-, S11- - -- ISTATE: DISPOSED - -- WRITER: W0 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - -- VALIDATE STATE - - Log("DDS Operation TAKE [MAX_SAMPLES 2, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE; - dds.max_samples := 2; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - start_dds; - wait_on_dds; - wait_on_idle; - -- MEM: 0, 0 - -- ISTATE: DISPOSED - -- WRITER: W0 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := NOT_ALIVE_UNREGISTERED; - cc.src_timestamp := gen_duration(17,0); - - -- TEST: UNREGISTER SAMPLE [NOT_ALIVE_DISPOSED INSTANCE] - - Log("RTPS Operation ADD_CACHE_CHANGE [UNREGISTER, Writer 0] (IGNORED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: 0, 0 - -- ISTATE: DISPOSED - -- WRITER: - - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.payload := gen_payload(KEY_HASH_NIL,6); - cc.src_timestamp := gen_duration(18,0); - - -- TEST: SAMPLE WITH UNALIGNED PAYLOAD [<1 SLOT] - - Log("RTPS Operation ADD_CACHE_CHANGE [Writer 2, Unaligned Payload (1 Slot)] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 2; - rtps.ret_code := OK; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: S12, 0 - -- ISTATE: ALIVE - -- WRITER: W2 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.payload := gen_payload(KEY_HASH_NIL,10); - cc.src_timestamp := gen_duration(19,0); - - -- TEST: SAMPLE WITH EARLY TIMESTAMP [TIMESTAMP EARLIER THAN LAST READ] - - Log("RTPS Operation ADD_CACHE_CHANGE [Writer 1, Aligned Payload] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 1; - rtps.ret_code := OK; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: S12, S13 - -- ISTATE: ALIVE - -- WRITER: W1, W2 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - -- VALIDATE STATE - - Log("DDS Operation READ [MAX_SAMPLES 2, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ; - dds.max_samples := 2; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - start_dds; - wait_on_dds; - wait_on_idle; - -- MEM: S12, S13 - -- ISTATE: ALIVE - -- WRITER: W1, W2 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - wait_on_completion; - TranscriptOpen(RESULTS_FILE, APPEND_MODE); - SetTranscriptMirror; - ReportAlerts; - TranscriptClose; - std.env.stop; - wait; - end process; - - clock_prc : process - begin - clk <= '0'; - wait for 25 ns; - clk <= '1'; - wait for 25 ns; - end process; - - alert_prc : process(all) - begin - if rising_edge(clk) then - -- TODO - end if; - end process; - - dds_prc : process(all) - variable col : COLLECTION_TYPE := DEFAULT_COLLECTION; - begin - if rising_edge(clk) then - dds_done <= '0'; - case (dds_stage ) is - when IDLE => - if (dds_start = '1') then - dds_stage <= START; - else - dds_done <= '1'; - end if; - when START => - if (ack_dds = '1') then - dds_stage <= DONE; - dds_cnt <= 0; - end if; - when DONE => - if (done_dds = '1') then - AffirmIfEqual(ret_id, return_code_dds, dds.ret_code); - case (dds.ret_code) is - when RETCODE_OK => - gen_collection(mem, col, dds, INSTANCE_PRESENTATION_QOS, FALSE); - dds_stage <= CHECK_SI; - dds_cnt <= 0; - when others => - dds_stage <= IDLE; - end case; - end if; - when CHECK_SI => - if (si_valid = '1') then - AffirmIfEqual(sstate_id, si_sample_state, col.s(dds_cnt).sstate); - AffirmIfEqual(vstate_id, si_view_state, col.s(dds_cnt).vstate); - AffirmIfEqual(istate_id, si_instance_state, col.s(dds_cnt).istate); - AffirmIfEqual(ts_id, to_unsigned(si_source_timestamp), to_unsigned(col.s(dds_cnt).ts)); - AffirmIfEqual(inst_id, to_unsigned(si_instance_handle), to_unsigned(col.s(dds_cnt).inst)); - AffirmIfEqual(pub_id, to_unsigned(si_publication_handle), to_unsigned(HANDLE_NIL)); - AffirmIfEqual(dis_gen_cnt_id, si_disposed_generation_count, std_logic_vector(to_unsigned(col.s(dds_cnt).dis_gen_cnt,WORD_WIDTH))); - AffirmIfEqual(no_w_gen_cnt_id, si_no_writers_generation_count, std_logic_vector(to_unsigned(col.s(dds_cnt).no_w_gen_cnt,WORD_WIDTH))); - AffirmIfEqual(srank_id, si_sample_rank, std_logic_vector(to_unsigned(col.s(dds_cnt).srank,WORD_WIDTH))); - AffirmIfEqual(grank_id, si_generation_rank, std_logic_vector(to_unsigned(col.s(dds_cnt).grank,WORD_WIDTH))); - AffirmIfEqual(agrank_id, si_absolute_generation_rank, std_logic_vector(to_unsigned(col.s(dds_cnt).agrank,WORD_WIDTH))); - if (si_valid_data = '1') then - AffirmIf(valid_id, col.s(dds_cnt).data /= EMPTY_TEST_PACKET, "Sample with Data not expected"); - dds_stage <= CHECK_DATA; - dds_cnt2 <= 0; - else - AffirmIf(valid_id, col.s(dds_cnt).data = EMPTY_TEST_PACKET, "Sample with Data expected"); - if (dds_cnt = col.len-1) then - -- DONE - dds_stage <= WAIT_EOC; - else - dds_cnt <= dds_cnt + 1; - end if; - end if; - end if; - AffirmIf(eoc_id, eoc = '0', "EOC pulled high"); - when CHECK_DATA => - if (valid_out_dds = '1') then - AffirmIfEqual(data_id, data_out_dds, col.s(dds_cnt).data.data(dds_cnt2)); - dds_cnt2 <= dds_cnt2 + 1; - if (dds_cnt2 = col.s(dds_cnt).data.length-1) then - AlertIf(data_id, last_word_out_dds /= '1', "Last Word Signal not pulled High", ERROR); - if (dds_cnt = col.len-1) then - -- DONE - dds_stage <= WAIT_EOC; - else - dds_stage <= CHECK_SI; - dds_cnt <= dds_cnt + 1; - end if; - end if; - end if; - when WAIT_EOC => - if (eoc = '1') then - dds_stage <= IDLE; - end if; - end case; - end if; - - -- DEFAULT - start_dds <= '0'; - opcode_dds <= NOP; - instance_state_dds <= ANY_INSTANCE_STATE; - view_state_dds <= ANY_VIEW_STATE; - sample_state_dds <= ANY_SAMPLE_STATE; - instance_handle_dds <= HANDLE_NIL; - max_samples_dds <= (others => '0'); - get_data_dds <= '0'; - ready_out_dds <= '0'; - - - case (dds_stage ) is - when START => - start_dds <= '1'; - opcode_dds <= dds.opcode; - instance_state_dds <= dds.istate; - view_state_dds <= dds.vstate; - sample_state_dds <= dds.sstate; - instance_handle_dds <= dds.inst; - max_samples_dds <= std_logic_vector(to_unsigned(dds.max_samples, WORD_WIDTH)); - when CHECK_SI => - if (si_valid = '1' and si_valid_data = '1') then - get_data_dds <= '1'; - end if; - when CHECK_DATA => - ready_out_dds <= '1'; - when others => - null; - end case; - end process; - - rtps_prc : process(all) - variable stimulus : TEST_PACKET_TYPE := EMPTY_TEST_PACKET; - begin - if rising_edge(clk) then - rtps_done <= '0'; - case (rtps_stage) is - when IDLE => - if (rtps_start = '1') then - rtps_stage <= START; - else - rtps_done <= '1'; - end if; - when START => - if (ack_rtps = '1') then - case (rtps.opcode) is - when ADD_CACHE_CHANGE => - gen_add_cache_change_dds(rtps.cc, rtps.lifespan, rtps.writer_pos, stimulus); - rtps_stage <= PUSH; - when others => - rtps_stage <= DONE; - end case; - end if; - when PUSH => - if (ready_in_rtps = '1') then - rtps_cnt <= rtps_cnt + 1; - if (rtps_cnt = stimulus.length-1) then - rtps_stage <= DONE; - end if; - end if; - when DONE => - if (done_rtps = '1') then - AffirmIfEqual(ret_id, HISTORY_CACHE_RESPONSE_TYPE'pos(ret_rtps), HISTORY_CACHE_RESPONSE_TYPE'pos(rtps.ret_code)); - rtps_stage <= IDLE; - end if; - end case; - end if; - - -- DEFAULT - start_rtps <= '0'; - opcode_rtps <= NOP; - valid_in_rtps <= '0'; - last_word_in_rtps <= '0'; - data_in_rtps <= (others => '0'); - - case (rtps_stage) is - when START => - start_rtps <= '1'; - opcode_rtps <= rtps.opcode; - case (rtps.opcode) is - when REMOVE_WRITER => - data_in_rtps <= std_logic_vector(to_unsigned(rtps.writer_pos,WORD_WIDTH)); - when others => - null; - end case; - when PUSH => - valid_in_rtps <= '1'; - data_in_rtps <= stimulus.data(rtps_cnt); - last_word_in_rtps <= stimulus.last(rtps_cnt); - when others => - null; - end case; - end process; - - watchdog : process - begin - wait for 1 ms; - Alert("Test timeout", FAILURE); - std.env.stop; - end process; - -end architecture; \ No newline at end of file diff --git a/src/Tests/Level_0/L0_dds_reader_test1_lbzkriu.vhd b/src/Tests/Level_0/L0_dds_reader_test1_lbzkriu.vhd deleted file mode 100644 index 5142e9d..0000000 --- a/src/Tests/Level_0/L0_dds_reader_test1_lbzkriu.vhd +++ /dev/null @@ -1,1690 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library osvvm; -- Utility Library -context osvvm.OsvvmContext; - -use work.rtps_package.all; -use work.user_config.all; -use work.rtps_config_package.all; -use work.rtps_test_package.all; - --- This testbench tests the RTPS handling of the DDS Reader. It tests the correctness of the RTPS ADD_CACHE_CHANGE, and REMOVE_WRITER Operations. --- Implicitly some DDS Operations are also tested, since they are used for state checking. --- More specifically the testbench covers following tests: --- TEST: NORMAL ADD_CACHE_CHANGE --- TEST: ADD_CACHE_CHANGE ON PAYLOAD MEMORY FULL --- TEST: REMOVE_WRITER [UNKNOWN WRITER] --- TEST: REMOVE_WRITER [KNOWN WRITER (1 Instance)] --- TEST: REMOVE_WRITER [KNOWN WRITER (>1 Instances)] --- TEST: REMOVE_WRITER [NOT_ALIVE_NO_WRITERS Transition] --- TEST: REMOVE_WRITER ON MAX_SAMPLES [NOT_ALIVE_NO_WRITERS Transition] --- TEST: REMOVE_WRITER ON MAX_SAMPLES_PER_INSTANCE [NOT_ALIVE_NO_WRITERS Transition] --- TEST: REMOVE_WRITER [Multiple Pending NOT_ALIVE_NO_WRITERS Transitions] --- TEST: SAMPLE WITH ALIGNED PAYLOAD --- TEST: SAMPLE WITH UNALIGNED PAYLOAD [>1 SLOT] --- TEST: SAMPLE WITH UNALIGNED PAYLOAD [<1 SLOT] --- TEST: NORMAL SAMPLE [KNOWN INSTANCE] --- TEST: NORMAL SAMPLE [UNKNOWN INSTANCE] --- TEST: UNREGISTER SAMPLE [KNOWN INSTANCE, KNOWN WRITER] --- TEST: UNREGISTER SAMPLE [KNOWN INSTANCE, UNKNOWN WRITER] --- TEST: UNREGISTER SAMPLE [UNKNOWN INSTANCE] --- TEST: UNREGISTER SAMPLE [NOT_ALIVE_NO_WRITERS INSTANCE] --- TEST: UNREGISTER SAMPLE [NOT_ALIVE_DISPOSED INSTANCE] --- TEST: UNREGISTER SAMPLE [NOT_ALIVE_DISPOSED INSTANCE, STALE INSTANCE TRANSITION] --- TEST: DISPOSE SAMPLE [KNOWN INSTANCE] --- TEST: DISPOSE SAMPLE [UNKNOWN INSTANCE] --- TEST: DISPOSE SAMPLE [NOT_ALIVE_NO_WRITERS INSTANCE] --- TEST: DISPOSE SAMPLE [NOT_ALIVE_DISPOSED INSTANCE] --- TEST: FILTER SAMPLE [KNOWN INSTANCE] --- TEST: FILTER SAMPLE [UNKNOWN INSTANCE] --- TEST: FILTER SAMPLE [NOT_ALIVE_DISPOSED INSTANCE] --- TEST: FILTER SAMPLE [NOT_ALIVE_NO_WRITERS INSTANCE] --- TEST: SAMPLE WITH KEY_HASH --- TEST: SAMPLE WITHOUT KEY_HASH --- TEST: SAMPLE WITH SERIALIZED KEY [WITH KEY_HASH] --- TEST: SAMPLE WITH SERIALIZED KEY [WITHOUT KEY_HASH] --- TEST: SAMPLE WITH EARLY TIMESTAMP [TIMESTAMP EARLIER THAN LAST READ] --- TEST: TEST SAMPLE WITH SERIALIZED KEY EFFECT ON PAYLOAD MEMORY FULLNESS --- TEST: ADD SAMPLE ON MAX_SAMPLES_PER_INSTANCE --- TEST: ADD SAMPLE ON MAX_SAMPLES [KNOWN INSTANCE] --- TEST: ADD SAMPLE ON MAX_SAMPLES [UNKNOWN INSTANCE] --- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKOWN INSTANCE, WITH STALE INSTANCE] --- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKOWN INSTANCE, WITHOUT STALE INSTANCE] --- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKOWN INSTANCE, WITHOUT STALE INSTANCE, WITH EMPTY INSTANCE] --- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKOWN INSTANCE, NOT_ALIVE_DISPOSED & STALE INSTANCE] --- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE, WITH STALE INSTANCE] --- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE, WITHOUT STALE INSTANCE] --- TEST: ADD SAMPLE BIGGER THAN AVAILABLE MEMORY SPACE --- TEST: ADD SAMPLE ON PAYLOAD MEMORY FULL & MAX_SAMPLES_PER_INSTANCE (Induce Double Remove) - -entity L0_dds_reader_test1_lbzkriu is -end entity; - - -architecture testbench of L0_dds_reader_test1_lbzkriu is - - -- *CONSTANT DECLARATION* - constant MAX_REMOTE_ENDPOINTS : natural := 3; - - -- *TYPE DECLARATION* - type DDS_STAGE_TYPE is (IDLE, START, DONE, CHECK_SI, CHECK_DATA, WAIT_EOC); - type RTPS_STAGE_TYPE is (IDLE, START, PUSH, DONE); - - -- *SIGNAL DECLARATION* - signal clk : std_logic := '0'; - signal reset : std_logic := '1'; - signal check_time : TIME_TYPE := TIME_ZERO; - signal start_rtps, start_dds, ack_rtps, ack_dds, done_rtps, done_dds : std_logic := '0'; - signal opcode_rtps : HISTORY_CACHE_OPCODE_TYPE := NOP; - signal opcode_dds : DDS_READER_OPCODE_TYPE := NOP; - signal ret_rtps : HISTORY_CACHE_RESPONSE_TYPE := ERROR; - signal ready_in_rtps, valid_in_rtps, last_word_in_rtps : std_logic := '0'; - signal ready_out_dds, valid_out_dds, last_word_out_dds : std_logic := '0'; - signal data_in_rtps, data_out_dds : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); - signal get_data_dds, si_valid_data, si_valid, eoc : std_logic := '0'; - signal return_code_dds : std_logic_vector(RETURN_CODE_WIDTH-1 downto 0) := (others => '0'); - signal status : std_logic_vector(STATUS_KIND_WIDTH-1 downto 0) := (others => '0'); - signal instance_state_dds, si_instance_state : std_logic_vector(INSTANCE_STATE_KIND_WIDTH-1 downto 0) := ANY_INSTANCE_STATE; - signal view_state_dds, si_view_state : std_logic_vector(VIEW_STATE_KIND_WIDTH-1 downto 0) := ANY_VIEW_STATE; - signal sample_state_dds, si_sample_state : std_logic_vector(SAMPLE_STATE_KIND_WIDTH-1 downto 0) := ANY_SAMPLE_STATE; - signal instance_handle_dds, si_instance_handle : INSTANCE_HANDLE_TYPE := HANDLE_NIL; - signal max_samples_dds : std_logic_vector(MAX_SAMPLES_WIDTH-1 downto 0) := (others => '0'); - signal si_source_timestamp : TIME_TYPE := TIME_INVALID; - signal si_publication_handle : INSTANCE_HANDLE_TYPE := HANDLE_NIL; - signal si_disposed_generation_count : std_logic_vector(DISPOSED_GENERATION_COUNT_WIDTH-1 downto 0) := (others => '0'); - signal si_no_writers_generation_count : std_logic_vector(NO_WRITERS_GENERATION_COUNT_WIDTH-1 downto 0) := (others => '0'); - signal si_sample_rank : std_logic_vector(SAMPLE_RANK_WIDTH-1 downto 0) := (others => '0'); - signal si_generation_rank : std_logic_vector(GENERATION_RANK_WIDTH-1 downto 0) := (others => '0'); - signal si_absolute_generation_rank: std_logic_vector(ABSOLUTE_GENERATION_COUNT_WIDTH-1 downto 0) := (others => '0'); - - signal dds_start , dds_done , rtps_start, rtps_done : std_logic := '0'; - signal dds_cnt, dds_cnt2, rtps_cnt : natural := 0; - signal dds_stage : DDS_STAGE_TYPE := IDLE; - signal rtps_stage : RTPS_STAGE_TYPE := IDLE; - shared variable dds : DDS_READER_TEST_TYPE := DEFAULT_DDS_READER_TEST; - shared variable rtps : RTPS_READER_TEST_TYPE := DEFAULT_RTPS_READER_TEST; - shared variable mem : DDS_READER_MEM_TYPE := DEFAULT_DDS_READER_MEM; - signal data_id, ret_id, sstate_id, vstate_id, istate_id, inst_id, ts_id, pub_id, dis_gen_cnt_id, no_w_gen_cnt_id, srank_id, grank_id, agrank_id, eoc_id, valid_id, status_id : AlertLogIDType; - - -- *FUNCTION DECLARATION* - function extract_key_hash (payload : TEST_PACKET_TYPE) return INSTANCE_HANDLE_TYPE is - variable ret : INSTANCE_HANDLE_TYPE := HANDLE_NIL; - begin - for i in 0 to 3 loop - ret(i) := not payload.data(i); - end loop; - - return ret; - end function; - - function gen_sn(input : natural) return SEQUENCENUMBER_TYPE is - variable ret : SEQUENCENUMBER_TYPE; - begin - ret(0) := (others => '0'); - ret(1) := unsigned(int(input, WORD_WIDTH)); - return ret; - end function; - -begin - - -- Unit Under Test - uut : entity work.dds_reader(arch) - generic map ( - TIME_BASED_FILTER_QOS => DURATION_ZERO, - DEADLINE_QOS => DURATION_INFINITE, - MAX_SAMPLES => std_logic_vector(to_unsigned(4,CDR_LONG_WIDTH)), - MAX_INSTANCES => std_logic_vector(to_unsigned(3,CDR_LONG_WIDTH)), - MAX_SAMPLES_PER_INSTANCE => std_logic_vector(to_unsigned(2,CDR_LONG_WIDTH)), - HISTORY_QOS => KEEP_LAST_HISTORY_QOS, - RELIABILITY_QOS => BEST_EFFORT_RELIABILITY_QOS, - PRESENTATION_QOS => INSTANCE_PRESENTATION_QOS, - DESTINATION_ORDER_QOS => BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS, - COHERENT_ACCESS => FALSE, - ORDERED_ACCESS => FALSE, - WITH_KEY => TRUE, - PAYLOAD_FRAME_SIZE => 11, - MAX_REMOTE_ENDPOINTS => MAX_REMOTE_ENDPOINTS - ) - port map ( - clk => clk, - reset => reset, - time => check_time, - start_rtps => start_rtps, - opcode_rtps => opcode_rtps, - ack_rtps => ack_rtps, - done_rtps => done_rtps, - ret_rtps => ret_rtps, - data_in_rtps => data_in_rtps, - valid_in_rtps => valid_in_rtps, - ready_in_rtps => ready_in_rtps, - last_word_in_rtps => last_word_in_rtps, - start_dds => start_dds, - ack_dds => ack_dds, - opcode_dds => opcode_dds, - instance_state_dds => instance_state_dds, - view_state_dds => view_state_dds, - sample_state_dds => sample_state_dds, - instance_handle_dds => instance_handle_dds, - max_samples_dds => max_samples_dds, - get_data_dds => get_data_dds, - done_dds => done_dds, - return_code_dds => return_code_dds, - ready_out_dds => ready_out_dds, - valid_out_dds => valid_out_dds, - data_out_dds => data_out_dds, - last_word_out_dds => last_word_out_dds, - sample_info.sample_state => si_sample_state, - sample_info.view_state => si_view_state, - sample_info.instance_state => si_instance_state, - sample_info.source_timestamp => si_source_timestamp, - sample_info.instance_handle => si_instance_handle, - sample_info.publication_handle => si_publication_handle, - sample_info.disposed_generation_count => si_disposed_generation_count, - sample_info.no_writers_generation_count => si_no_writers_generation_count, - sample_info.sample_rank => si_sample_rank, - sample_info.generation_rank => si_generation_rank, - sample_info.absolute_generation_rank => si_absolute_generation_rank, - sample_info.valid_data => si_valid_data, - sample_info_valid => si_valid, - sample_info_ack => '1', - eoc => eoc, - status => status - ); - - stimulus_prc : process - variable RV : RandomPType; - variable cc : CACHE_CHANGE_TYPE := DEFAULT_CACHE_CHANGE; - variable s : SAMPLE_TYPE := DEFAULT_SAMPLE; - variable kh1, kh2, kh3, kh4, kh5 : INSTANCE_HANDLE_TYPE := HANDLE_NIL; - - alias idle_sig is <>; - - impure function gen_payload(key_hash : INSTANCE_HANDLE_TYPE; len : natural) return TEST_PACKET_TYPE is - variable ret : TEST_PACKET_TYPE := EMPTY_TEST_PACKET; - begin - assert (len >= 4) report "Payload length has to be at least 16 Bytes long" severity FAILURE; - - for i in 0 to len-1 loop - if (i < 4) then - -- NOTE: Beginning of payload is negated key to allow deterministic Key Hash generation from the kh_prc - ret.data(ret.length) := not key_hash(i); - else - ret.data(ret.length) := RV.RandSlv(WORD_WIDTH); - end if; - ret.length := ret.length + 1; - end loop; - ret.last(ret.length-1) := '1'; - - return ret; - end function; - - impure function gen_key_hash return KEY_HASH_TYPE is - variable ret : KEY_HASH_TYPE := KEY_HASH_NIL; - begin - for i in 0 to KEY_HASH_TYPE'length-1 loop - ret(i) := RV.RandSlv(WORD_WIDTH); - end loop; - return ret; - end function; - - procedure start_dds is - begin - dds_start <= '1'; - wait until rising_edge(clk); - dds_start <= '0'; - wait until rising_edge(clk); - end procedure; - - procedure start_rtps is - begin - rtps_start <= '1'; - wait until rising_edge(clk); - rtps_start <= '0'; - wait until rising_edge(clk); - end procedure; - - procedure wait_on_dds is - begin - if (dds_done /= '1') then - wait until dds_done = '1'; - end if; - end procedure; - - procedure wait_on_rtps is - begin - if (rtps_done /= '1') then - wait until rtps_done = '1'; - end if; - end procedure; - - procedure wait_on_completion is - begin - if (rtps_done /= '1' or dds_done /= '1') then - wait until rtps_done = '1' and dds_done = '1'; - end if; - end procedure; - - -- NOTE: This procedure waits until the idle_sig is high for at least - -- two consecutive clock cycles. - procedure wait_on_idle is - variable first : boolean := TRUE; - begin - loop - if (idle_sig /= '1') then - wait until idle_sig = '1'; - elsif (not first) then - exit; - end if; - wait until rising_edge(clk); - wait until rising_edge(clk); - first := FALSE; - end loop; - end procedure; - - begin - - SetAlertLogName("L0_dds_reader_test1_lbzkriu - (KEEP LAST, Best Effort, Zero TIME_BASED_FILTER, Keyed, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER, ACCESS SCOPE Instance, Unordered) - RTPS Handling"); - SetAlertEnable(FAILURE, TRUE); - SetAlertEnable(ERROR, TRUE); - SetAlertEnable(WARNING, TRUE); - SetLogEnable(DEBUG, FALSE); - SetLogEnable(PASSED, FALSE); - SetLogEnable(INFO, TRUE); - RV.InitSeed(RV'instance_name); - sstate_id <= GetAlertLogID("Sample State", ALERTLOG_BASE_ID); - vstate_id <= GetAlertLogID("View State", ALERTLOG_BASE_ID); - istate_id <= GetAlertLogID("Instance State", ALERTLOG_BASE_ID); - ts_id <= GetAlertLogID("Source Timestamp", ALERTLOG_BASE_ID); - inst_id <= GetAlertLogID("Instance Handle", ALERTLOG_BASE_ID); - pub_id <= GetAlertLogID("Publication Hanlde", ALERTLOG_BASE_ID); - dis_gen_cnt_id <= GetAlertLogID("Disposed Generation Count", ALERTLOG_BASE_ID); - no_w_gen_cnt_id <= GetAlertLogID("No Writers Generation Count", ALERTLOG_BASE_ID); - srank_id <= GetAlertLogID("Sample Rank", ALERTLOG_BASE_ID); - grank_id <= GetAlertLogID("Generation Rank", ALERTLOG_BASE_ID); - agrank_id <= GetAlertLogID("Absolute Generation Rank", ALERTLOG_BASE_ID); - eoc_id <= GetAlertLogID("End of Collection", ALERTLOG_BASE_ID); - valid_id <= GetAlertLogID("Valid Data", ALERTLOG_BASE_ID); - data_id <= GetAlertLogID("Data Out", ALERTLOG_BASE_ID); - ret_id <= GetAlertLogID("Return Code", ALERTLOG_BASE_ID); - status_id <= GetAlertLogID("Communication Status", ALERTLOG_BASE_ID); - - -- Key Hashes - kh3 := (x"0CEAB0C6", x"FA04B9AD", x"A96EB495", x"4E0EB999"); - kh4 := (x"A7EB605C", x"FF4BEF3A", x"3C5E8724", x"CCA0CA67"); - kh2 := (x"BC070AC4", x"0BAB5811", x"14EA8D61", x"F669189B"); - kh1 := (x"F12C31DA", x"E3FE0F3F", x"01F36685", x"446518CA"); - kh5 := gen_key_hash; - - - - Log("Initiating Test", INFO); - reset <= '1'; - wait until rising_edge(clk); - wait until rising_edge(clk); - reset <= '0'; - -- MEM: 0, 0, 0, 0 - -- ISTATE: - - -- WRITER: - - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh1; - cc.payload := gen_payload(kh1,10); - cc.src_timestamp := gen_duration(1,0); - - -- TEST: NORMAL ADD_CACHE_CHANGE - -- TEST: SAMPLE WITH ALIGNED PAYLOAD - -- TEST: NORMAL SAMPLE [UNKNOWN INSTANCE] - -- TEST: SAMPLE WITH KEY_HASH - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Aligned Payload] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - rtps.ret_code := OK; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S1, 0, 0, 0 - -- ISTATE: I1:ALIVE - -- WRITER: W0:I1 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := HANDLE_NIL; - cc.payload := gen_payload(kh1,10); - cc.src_timestamp := gen_duration(2,0); - - -- TEST: SAMPLE WITHOUT KEY_HASH - -- TEST: NORMAL SAMPLE [KNOWN INSTANCE] - - Log("RTPS Operation ADD_CACHE_CHANGE [NO KEY_HASH, Instance 1, Writer 0, Aligned Payload] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - rtps.ret_code := OK; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - s.inst := kh1; - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S1, I1S2, 0, 0 - -- ISTATE: I1:ALIVE - -- WRITER: W0:I1 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh1; - cc.payload := gen_payload(kh1,18); - cc.src_timestamp := gen_duration(3,0); - - -- TEST: SAMPLE WITH UNALIGNED PAYLOAD [>1 SLOT] - -- TEST: ADD SAMPLE ON MAX_SAMPLES_PER_INSTANCE - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Unaligned Payload (2 Slots)] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - rtps.ret_code := OK; - remove_sample(0,mem); - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S2, I1S3+, 0, 0 - -- ISTATE: I1:ALIVE - -- WRITER: W0:I1 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - -- VALIDATE STATE - - Log("DDS Operation READ [MAX_SAMPLES 4, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ; - dds.max_samples := 4; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - start_dds; - wait_on_dds; - wait_on_idle; - -- MEM: I1S2, I1S3+, 0, 0 - -- ISTATE: I1:ALIVE - -- WRITER: W0:I1 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - Log("DDS Operation TAKE [MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE; - dds.max_samples := 1; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - start_dds; - wait_on_dds; - wait_on_idle; - -- MEM: I1S3+, 0, 0, 0 - -- ISTATE: I1:ALIVE - -- WRITER: W0:I1 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_DISPOSED; - cc.instance := kh1; - cc.payload := gen_payload(kh1,5); - cc.src_timestamp := gen_duration(4,0); - - -- TEST: DISPOSE SAMPLE [KNOWN INSTANCE] - -- TEST: SAMPLE WITH SERIALIZED KEY [WITH KEY_HASH] - -- TEST: SAMPLE WITH UNALIGNED PAYLOAD [<1 SLOT] - - Log("RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Instance 1, Writer 0] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - rtps.ret_code := OK; - s := to_sample(cc,NOT_ALIVE_DISPOSED_INSTANCE_STATE); - s.inst := kh1; - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S3+, I1S4-, 0, 0 - -- ISTATE: I1:DISPOSED - -- WRITER: W0:I1 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh2; - cc.payload := gen_payload(kh2,20); - cc.src_timestamp := gen_duration(5,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 2, Writer 1, Aligned Payload (2 Slots)] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 1; - rtps.ret_code := OK; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S3+, I1S4-, I2S1+, 0 - -- ISTATE: I1:DISPOSED, I2:ALIVE - -- WRITER: W0:I1, W1:I2 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh3; - cc.payload := gen_payload(kh3,10); - cc.src_timestamp := gen_duration(6,0); - - -- TEST: TEST SAMPLE WITH SERIALIZED KEY EFFECT ON PAYLOAD MEMORY FULLNESS - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 3, Writer 1, Aligned Payload] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 1; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S3+, I1S4-, I2S1+, I3S1 - -- ISTATE: I1:DISPOSED, I2:ALIVE, I3:ALIVE - -- WRITER: W0:I1, W1:I2,I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - -- TEST: REMOVE_WRITER [UNKNOWN WRITER] - - Log("RTPS Operation REMOVE_WRITER [Writer 2] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := REMOVE_WRITER; - rtps.writer_pos := 2; - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S3+, I1S4-, I2S1+, I3S1 - -- ISTATE: I1:DISPOSED, I2:ALIVE, I3:ALIVE - -- WRITER: W0:I1, W1:I2,I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - Log("DDS Operation TAKE [MAX_SAMPLES 1, NOT_READ_SAMPLE_STATE, NOT_ALIVE_DISPOSED_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE; - dds.max_samples := 1; - dds.sstate := NOT_READ_SAMPLE_STATE; - dds.istate := NOT_ALIVE_DISPOSED_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - start_dds; - wait_on_dds; - wait_on_idle; - -- MEM: I1S3+, I2S1+, I3S1, 0 - -- ISTATE: I1:DISPOSED, I2:ALIVE, I3:ALIVE - -- WRITER: W0:I1, W1:I2,I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh3; - cc.payload := gen_payload(kh3,10); - cc.src_timestamp := gen_duration(7,0); - - -- TEST: ADD_CACHE_CHANGE ON PAYLOAD MEMORY FULL - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 3, Writer 2, Aligned Payload] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 2; - remove_sample(0,mem); - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I2S1+, I3S1, I3S2, 0 - -- ISTATE: I1:DISPOSED, I2:ALIVE, I3:ALIVE - -- WRITER: W0:I1, W1:I2,I3, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh4; - cc.payload := gen_payload(kh4,10); - cc.src_timestamp := gen_duration(8,0); - - -- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKOWN INSTANCE, WITHOUT STALE INSTANCE, WITH EMPTY INSTANCE] - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 4, Writer 1, Aligned Payload] (REJECTED: MAX_INSTANCES exceeded)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 1; - rtps.ret_code := REJECTED; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I2S1+, I3S1, I3S2, 0 - -- ISTATE: I1:DISPOSED, I2:ALIVE, I3:ALIVE - -- WRITER: W0:I1, W1:I2,I3, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - -- TEST: REMOVE_WRITER [KNOWN WRITER (1 Instance)] - - Log("RTPS Operation REMOVE_WRITER [Writer 0] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := REMOVE_WRITER; - rtps.writer_pos := 0; - change_istate(kh1, NOT_ALIVE_NO_WRITERS_INSTANCE_STATE, mem); - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I2S1+, I3S1, I3S2, 0 - -- ISTATE: I1:DISPOSED, I2:ALIVE, I3:ALIVE - -- WRITER: W1:I2,I3, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - -- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKOWN INSTANCE, WITH STALE INSTANCE] - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 4, Writer 1, Aligned Payload] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 1; - remove_inst(kh1, mem); - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I2S1+, I3S1, I3S2, I4S1 - -- ISTATE: I2:ALIVE, I3:ALIVE, I4:ALIVE - -- WRITER: W1:I2,I3,I4, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - -- VALIDATE STATE - - Log("DDS Operation READ [MAX_SAMPLES 4, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ; - dds.max_samples := 4; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - start_dds; - wait_on_dds; - wait_on_idle; - -- MEM: I2S1+, I3S1, I3S2, I4S1 - -- ISTATE: I2:ALIVE, I3:ALIVE, I4:ALIVE - -- WRITER: W1:I2,I3,I4, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - Log("DDS Operation TAKE [MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE; - dds.max_samples := 1; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - start_dds; - wait_on_dds; - wait_on_idle; - -- MEM: I3S1, I3S2, I4S1, 0 - -- ISTATE: I2:ALIVE, I3:ALIVE, I4:ALIVE - -- WRITER: W1:I2,I3,I4, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh1; - cc.payload := gen_payload(kh1,10); - cc.src_timestamp := gen_duration(9,0); - - -- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKOWN INSTANCE, WITHOUT STALE INSTANCE] - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Aligned Payload] (REJECTED: MAX_INSTANCES exceeded)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - rtps.ret_code := REJECTED; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I3S1, I3S2, I4S1, 0 - -- ISTATE: I2:ALIVE, I3:ALIVE, I4:ALIVE - -- WRITER: W1:I2,I3,I4, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh4; - cc.payload := gen_payload(kh4,10); - cc.src_timestamp := gen_duration(10,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 4, Writer 1, Aligned Payload] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 1; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I3S1, I3S2, I4S1, I4S2 - -- ISTATE: I2:ALIVE, I3:ALIVE, I4:ALIVE - -- WRITER: W1:I2,I3,I4, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh1; - cc.payload := gen_payload(kh1,10); - cc.src_timestamp := gen_duration(11,0); - - -- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE, WITHOUT STALE INSTANCE] - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Aligned Payload] (REJECTED: MAX_INSTANCES exceeded)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - rtps.ret_code := REJECTED; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I3S1, I3S2, I4S1, I4S2 - -- ISTATE: I2:ALIVE, I3:ALIVE, I4:ALIVE - -- WRITER: W1:I2,I3,I4, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - Log("DDS Operation READ [MAX_SAMPLES 4, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ; - dds.max_samples := 4; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - start_dds; - wait_on_dds; - wait_on_idle; - -- MEM: I3S1, I3S2, I4S1, I4S2 - -- ISTATE: I2:ALIVE, I3:ALIVE, I4:ALIVE - -- WRITER: W1:I2,I3,I4, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - -- TEST: REMOVE_WRITER [KNOWN WRITER (>1 Instances)] - -- TEST: REMOVE_WRITER [NOT_ALIVE_NO_WRITERS Transition] - -- TEST: REMOVE_WRITER ON MAX_SAMPLES [NOT_ALIVE_NO_WRITERS Transition] - -- TEST: REMOVE_WRITER ON MAX_SAMPLES_PER_INSTANCE [NOT_ALIVE_NO_WRITERS Transition] - -- TEST: REMOVE_WRITER [Multiple Pending NOT_ALIVE_NO_WRITERS Transitions] - - Log("RTPS Operation REMOVE_WRITER [Writer 1] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := REMOVE_WRITER; - rtps.writer_pos := 1; - remove_sample(0,mem); - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_UNREGISTERED; - cc.instance := kh2; - cc.src_timestamp := check_time; - s := to_sample(cc,NOT_ALIVE_NO_WRITERS_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - remove_sample(1,mem); - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_UNREGISTERED; - cc.instance := kh4; - cc.src_timestamp := check_time; - s := to_sample(cc,NOT_ALIVE_NO_WRITERS_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I3S2, I4S2, I2S2-, I4S3- - -- ISTATE: I2:NO_WRITERS, I3:ALIVE, I4:NO_WRITERS - -- WRITER: W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - Log("DDS Operation TAKE_INSTANCE [Instance 2, MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE_INSTANCE; - dds.max_samples := 1; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.inst := kh2; - start_dds; - wait_on_dds; - wait_on_idle; - -- MEM: I3S2, I4S2, I4S3-, 0 - -- ISTATE: I2:NO_WRITERS, I3:ALIVE, I4:NO_WRITERS - -- WRITER: W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh3; - cc.payload := gen_payload(kh3,10); - cc.src_timestamp := gen_duration(12,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 3, Writer 2, Aligned Payload] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 2; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I3S2, I4S2, I4S3-, I3S3 - -- ISTATE: I2:NO_WRITERS, I3:ALIVE, I4:NO_WRITERS - -- WRITER: W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - Log("DDS Operation READ [MAX_SAMPLES 4, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ; - dds.max_samples := 4; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - start_dds; - wait_on_dds; - wait_on_idle; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh1; - cc.payload := gen_payload(kh1,10); - cc.src_timestamp := gen_duration(13,0); - - -- TEST: ADD SAMPLE ON MAX_SAMPLES [UNKNOWN INSTANCE] - -- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE, WITH STALE INSTANCE] - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Aligned Payload] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - remove_inst(kh2,mem); - remove_sample(0,mem); - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I4S2, I4S3-, I3S3, I1S1 - -- ISTATE: I1:ALIVE, I3:ALIVE, I4:NO_WRITERS - -- WRITER: W0:I1, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh3; - cc.payload := gen_payload(kh3,10); - cc.src_timestamp := gen_duration(14,0); - - -- TEST: ADD SAMPLE ON MAX_SAMPLES [KNOWN INSTANCE] - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 3, Writer 2, Aligned Payload] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 2; - remove_sample(0,mem); - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I4S3-, I3S3, I1S1, I3S4 - -- ISTATE: I1:ALIVE, I3:ALIVE, I4:NO_WRITERS - -- WRITER: W0:I1, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - -- VALIDATE STATE - - Log("DDS Operation READ [MAX_SAMPLES 4, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ; - dds.max_samples := 4; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - start_dds; - wait_on_dds; - wait_on_idle; - -- MEM: I4S3-, I3S3, I1S1, I3S4 - -- ISTATE: I1:ALIVE, I3:ALIVE, I4:NO_WRITERS - -- WRITER: W0:I1, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh1; - cc.payload := gen_payload(kh1,10); - cc.src_timestamp := gen_duration(15,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Aligned Payload] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - remove_sample(0,mem); - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I3S3, I1S1, I3S4, I1S2 - -- ISTATE: I1:ALIVE, I3:ALIVE, I4:NO_WRITERS - -- WRITER: W0:I1, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh1; - cc.payload := gen_payload(kh1,10); - cc.src_timestamp := gen_duration(16,0); - - -- TEST: ADD SAMPLE ON PAYLOAD MEMORY FULL & MAX_SAMPLES_PER_INSTANCE (Induce Double Remove) - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Aligned Payload] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - remove_sample(1,mem); - remove_sample(0,mem); - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I3S4, I1S2, I1S3, 0 - -- ISTATE: I1:ALIVE, I3:ALIVE, I4:NO_WRITERS - -- WRITER: W0:I1, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh3; - cc.payload := gen_payload(kh3,30); - cc.src_timestamp := gen_duration(17,0); - - -- TEST: ADD SAMPLE BIGGER THAN AVAILABLE MEMORY SPACE - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 3, Writer 0, Aligned Payload (3 Slots)] (REJECTED: Payload memory Full)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - rtps.ret_code := REJECTED; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I3S4, I1S2, I1S3, 0 - -- ISTATE: I1:ALIVE, I3:ALIVE, I4:NO_WRITERS - -- WRITER: W0:I1, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_DISPOSED; - cc.instance := HANDLE_NIL; - cc.payload := gen_payload(kh4,5); - cc.src_timestamp := gen_duration(18,0); - - -- TEST: DISPOSE SAMPLE [NOT_ALIVE_NO_WRITERS INSTANCE] - -- TEST: SAMPLE WITH SERIALIZED KEY [WITHOUT KEY_HASH] - - Log("RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Instance 4, Writer 1] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 1; - s := to_sample(cc,NOT_ALIVE_DISPOSED_INSTANCE_STATE); - s.inst := kh4; - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I3S4, I1S2, I1S3, I4S4- - -- ISTATE: I1:ALIVE, I3:ALIVE, I4:DISPOSED - -- WRITER: W0:I1, W1:I4, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - -- VALIDATE STATE - - Log("DDS Operation TAKE [MAX_SAMPLES 4, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE; - dds.max_samples := 4; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - start_dds; - wait_on_dds; - wait_on_idle; - -- MEM: 0, 0, 0, 0 - -- ISTATE: I1:ALIVE, I3:ALIVE, I4:DISPOSED - -- WRITER: W0:I1, W1:I4, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_DISPOSED; - cc.instance := kh4; - cc.payload := gen_payload(kh4,5); - cc.src_timestamp := gen_duration(19,0); - - -- TEST: DISPOSE SAMPLE [NOT_ALIVE_DISPOSED INSTANCE] - - Log("RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Instance 4, Writer 0] (IGNORED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: 0, 0, 0, 0 - -- ISTATE: I1:ALIVE, I3:ALIVE, I4:DISPOSED - -- WRITER: W0:I1,I4 W1:I4, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_UNREGISTERED; - cc.instance := kh4; - cc.payload := gen_payload(kh4,5); - cc.src_timestamp := gen_duration(20,0); - - -- TEST: UNREGISTER SAMPLE [KNOWN INSTANCE, KNOWN WRITER] - -- TEST: UNREGISTER SAMPLE [NOT_ALIVE_DISPOSED INSTANCE] - - Log("RTPS Operation ADD_CACHE_CHANGE [UNREGISTER, Instance 4, Writer 0] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: 0, 0, 0, 0 - -- ISTATE: I1:ALIVE, I3:ALIVE, I4:DISPOSED - -- WRITER: W0:I1, W1:I4, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_UNREGISTERED; - cc.instance := kh1; - cc.payload := gen_payload(kh1,5); - cc.src_timestamp := gen_duration(21,0); - - -- TEST: UNREGISTER SAMPLE [KNOWN INSTANCE, UNKNOWN WRITER] - - Log("RTPS Operation ADD_CACHE_CHANGE [UNREGISTER, Instance 1, Writer 1] (IGNORED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 1; - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: 0, 0, 0, 0 - -- ISTATE: I1:ALIVE, I3:ALIVE, I4:DISPOSED - -- WRITER: W0:I1, W1:I4, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_UNREGISTERED; - cc.instance := kh2; - cc.payload := gen_payload(kh2,5); - cc.src_timestamp := gen_duration(22,0); - - -- TEST: UNREGISTER SAMPLE [UNKNOWN INSTANCE] - - Log("RTPS Operation ADD_CACHE_CHANGE [UNREGISTER, Instance 2, Writer 1] (IGNORED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 1; - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: 0, 0, 0, 0 - -- ISTATE: I1:ALIVE, I3:ALIVE, I4:DISPOSED - -- WRITER: W0:I1, W1:I4, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_UNREGISTERED; - cc.instance := kh1; - cc.payload := gen_payload(kh1,5); - cc.src_timestamp := gen_duration(23,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [UNREGISTER, Instance 1, Writer 0] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - s := to_sample(cc,NOT_ALIVE_NO_WRITERS_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S4-, 0, 0, 0 - -- ISTATE: I1:NO_WRITERS, I3:ALIVE, I4:DISPOSED - -- WRITER: W1:I4, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_UNREGISTERED; - cc.instance := kh1; - cc.payload := gen_payload(kh1,5); - cc.src_timestamp := gen_duration(24,0); - - -- TEST: UNREGISTER SAMPLE [NOT_ALIVE_NO_WRITERS INSTANCE] - - Log("RTPS Operation ADD_CACHE_CHANGE [UNREGISTER, Instance 1, Writer 2] (IGNORED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 2; - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S4-, 0, 0, 0 - -- ISTATE: I1:NO_WRITERS, I3:ALIVE, I4:DISPOSED - -- WRITER: W1:I4, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := ALIVE_FILTERED; - cc.instance := kh1; - cc.payload := gen_payload(kh1,5); - cc.src_timestamp := gen_duration(25,0); - - -- TEST: FILTER SAMPLE [KNOWN INSTANCE] - -- TEST: FILTER SAMPLE [NOT_ALIVE_NO_WRITERS INSTANCE] - - Log("RTPS Operation ADD_CACHE_CHANGE [FILTERED, Instance 1, Writer 2] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - rtps.writer_pos := 2; - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S4-, I1S5-, 0, 0 - -- ISTATE: I1:ALIVE, I3:ALIVE, I4:DISPOSED - -- WRITER: W1:I4, W2:I1,I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_UNREGISTERED; - cc.instance := kh4; - cc.payload := gen_payload(kh1,5); - cc.src_timestamp := gen_duration(26,0); - - -- TEST: UNREGISTER SAMPLE [NOT_ALIVE_DISPOSED INSTANCE, STALE INSTANCE TRANSITION] - - Log("RTPS Operation ADD_CACHE_CHANGE [UNREGISTER, Instance 4, Writer 1] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 1; - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S4-, I1S5-, 0, 0 - -- ISTATE: I1:ALIVE, I3:ALIVE, I4:DISPOSED - -- WRITER: W2:I1,I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh2; - cc.payload := gen_payload(kh2,10); - cc.src_timestamp := gen_duration(27,0); - - -- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKOWN INSTANCE, NOT_ALIVE_DISPOSED & STALE INSTANCE] - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 2, Writer 0, Aligned Payload] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - remove_inst(kh4, mem); - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S4-, I1S5-, I2S1, 0 - -- ISTATE: I1:ALIVE, I2:ALIVE, I3:ALIVE - -- WRITER: W0:I2, W2:I1,I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - -- VALIDATE STATE - - Log("DDS Operation TAKE [MAX_SAMPLES 4, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE; - dds.max_samples := 4; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - start_dds; - wait_on_dds; - wait_on_idle; - -- MEM: 0, 0, 0, 0 - -- ISTATE: I1:ALIVE, I2:ALIVE, I3:ALIVE - -- WRITER: W0:I2, W2:I1,I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_DISPOSED; - cc.instance := kh1; - cc.payload := gen_payload(kh1,5); - cc.src_timestamp := gen_duration(28,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Instance 1, Writer 2] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 2; - s := to_sample(cc,NOT_ALIVE_DISPOSED_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S6-, 0, 0, 0 - -- ISTATE: I1:DISPOSED, I2:ALIVE, I3:ALIVE - -- WRITER: W0:I2, W2:I1,I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := ALIVE_FILTERED; - cc.instance := kh1; - cc.payload := gen_payload(kh1,5); - cc.src_timestamp := gen_duration(29,0); - - -- TEST: FILTER SAMPLE [NOT_ALIVE_DISPOSED INSTANCE] - - Log("RTPS Operation ADD_CACHE_CHANGE [FILTERED, Instance 1, Writer 2] (ACCEPT)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - rtps.writer_pos := 2; - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S6-, I1S7-, 0, 0 - -- ISTATE: I1:ALIVE, I2:ALIVE, I3:ALIVE - -- WRITER: W0:I2, W2:I1,I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := ALIVE_FILTERED; - cc.instance := kh4; - cc.payload := gen_payload(kh4,5); - cc.src_timestamp := gen_duration(30,0); - - -- TEST: FILTER SAMPLE [UNKNOWN INSTANCE] - - Log("RTPS Operation ADD_CACHE_CHANGE [FILTERED, Instance 4, Writer 1] (IGNORED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 1; - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S6-, I1S7-, 0, 0 - -- ISTATE: I1:ALIVE, I2:ALIVE, I3:ALIVE - -- WRITER: W0:I2, W2:I1,I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh3; - cc.payload := gen_payload(kh3,10); - cc.src_timestamp := gen_duration(10,0); - - -- TEST: SAMPLE WITH EARLY TIMESTAMP [TIMESTAMP EARLIER THAN LAST READ] - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 3, Writer 2, Aligned Payload] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 2; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S6-, I1S7-, I3S5, 0 - -- ISTATE: I1:ALIVE, I2:ALIVE, I3:ALIVE - -- WRITER: W0:I2, W2:I1,I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_UNREGISTERED; - cc.instance := kh2; - cc.payload := gen_payload(kh2,5); - cc.src_timestamp := gen_duration(31,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [UNREGISTER, Instance 2, Writer 0] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - s := to_sample(cc,NOT_ALIVE_NO_WRITERS_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S6-, I1S7-, I3S5, I2S2- - -- ISTATE: I1:ALIVE, I2:NO_WRITERS, I3: ALIVE - -- WRITER: W2:I1,I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - -- VALIDATE STATE - - Log("DDS Operation TAKE [MAX_SAMPLES 4, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE; - dds.max_samples := 4; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - start_dds; - wait_on_dds; - wait_on_idle; - -- MEM: 0, 0, 0, 0 - -- ISTATE: I1:ALIVE, I2:NO_WRITERS, I3: ALIVE - -- WRITER: W2:I1,I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_DISPOSED; - cc.instance := kh4; - cc.payload := gen_payload(kh4,5); - cc.src_timestamp := gen_duration(32,0); - - -- TEST: DISPOSE SAMPLE [UNKNOWN INSTANCE] - - Log("RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Instance 4, Writer 1] (ACCPETED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 1; - s := to_sample(cc,NOT_ALIVE_DISPOSED_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I4S1-, 0, 0, 0 - -- ISTATE: I1:ALIVE, I3: ALIVE, I4:DISPOSED - -- WRITER: W1:I4, W2:I1,I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - -- VALIDATE STATE - - Log("DDS Operation READ [MAX_SAMPLES 4, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE; - dds.max_samples := 4; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := NOT_ALIVE_DISPOSED_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - start_dds; - wait_on_dds; - wait_on_idle; - -- MEM: I4S1-, 0, 0, 0 - -- ISTATE: I1:ALIVE, I3: ALIVE, I4:DISPOSED - -- WRITER: W1:I4, W2:I1,I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - wait_on_completion; - TranscriptOpen(RESULTS_FILE, APPEND_MODE); - SetTranscriptMirror; - ReportAlerts; - TranscriptClose; - std.env.stop; - wait; - end process; - - clock_prc : process - begin - clk <= '0'; - wait for 25 ns; - clk <= '1'; - wait for 25 ns; - end process; - - alert_prc : process(all) - begin - if rising_edge(clk) then - -- TODO - end if; - end process; - - dds_prc : process(all) - variable col : COLLECTION_TYPE := DEFAULT_COLLECTION; - begin - if rising_edge(clk) then - dds_done <= '0'; - case (dds_stage ) is - when IDLE => - if (dds_start = '1') then - dds_stage <= START; - else - dds_done <= '1'; - end if; - when START => - if (ack_dds = '1') then - dds_stage <= DONE; - dds_cnt <= 0; - end if; - when DONE => - if (done_dds = '1') then - AffirmIfEqual(ret_id, return_code_dds, dds.ret_code); - case (dds.ret_code) is - when RETCODE_OK => - gen_collection(mem, col, dds, INSTANCE_PRESENTATION_QOS, FALSE); - dds_stage <= CHECK_SI; - dds_cnt <= 0; - when others => - dds_stage <= IDLE; - end case; - end if; - when CHECK_SI => - if (si_valid = '1') then - AffirmIfEqual(sstate_id, si_sample_state, col.s(dds_cnt).sstate); - AffirmIfEqual(vstate_id, si_view_state, col.s(dds_cnt).vstate); - AffirmIfEqual(istate_id, si_instance_state, col.s(dds_cnt).istate); - AffirmIfEqual(ts_id, to_unsigned(si_source_timestamp), to_unsigned(col.s(dds_cnt).ts)); - AffirmIfEqual(inst_id, to_unsigned(si_instance_handle), to_unsigned(col.s(dds_cnt).inst)); - AffirmIfEqual(pub_id, to_unsigned(si_publication_handle), to_unsigned(HANDLE_NIL)); - AffirmIfEqual(dis_gen_cnt_id, si_disposed_generation_count, std_logic_vector(to_unsigned(col.s(dds_cnt).dis_gen_cnt,WORD_WIDTH))); - AffirmIfEqual(no_w_gen_cnt_id, si_no_writers_generation_count, std_logic_vector(to_unsigned(col.s(dds_cnt).no_w_gen_cnt,WORD_WIDTH))); - AffirmIfEqual(srank_id, si_sample_rank, std_logic_vector(to_unsigned(col.s(dds_cnt).srank,WORD_WIDTH))); - AffirmIfEqual(grank_id, si_generation_rank, std_logic_vector(to_unsigned(col.s(dds_cnt).grank,WORD_WIDTH))); - AffirmIfEqual(agrank_id, si_absolute_generation_rank, std_logic_vector(to_unsigned(col.s(dds_cnt).agrank,WORD_WIDTH))); - if (si_valid_data = '1') then - AffirmIf(valid_id, col.s(dds_cnt).data /= EMPTY_TEST_PACKET, "Sample with Data not expected"); - dds_stage <= CHECK_DATA; - dds_cnt2 <= 0; - else - AffirmIf(valid_id, col.s(dds_cnt).data = EMPTY_TEST_PACKET, "Sample with Data expected"); - if (dds_cnt = col.len-1) then - -- DONE - dds_stage <= WAIT_EOC; - else - dds_cnt <= dds_cnt + 1; - end if; - end if; - end if; - AffirmIf(eoc_id, eoc = '0', "EOC pulled high"); - when CHECK_DATA => - if (valid_out_dds = '1') then - AffirmIfEqual(data_id, data_out_dds, col.s(dds_cnt).data.data(dds_cnt2)); - dds_cnt2 <= dds_cnt2 + 1; - if (dds_cnt2 = col.s(dds_cnt).data.length-1) then - AlertIf(data_id, last_word_out_dds /= '1', "Last Word Signal not pulled High", ERROR); - if (dds_cnt = col.len-1) then - -- DONE - dds_stage <= WAIT_EOC; - else - dds_stage <= CHECK_SI; - dds_cnt <= dds_cnt + 1; - end if; - end if; - end if; - when WAIT_EOC => - if (eoc = '1') then - dds_stage <= IDLE; - end if; - end case; - end if; - - -- DEFAULT - start_dds <= '0'; - opcode_dds <= NOP; - instance_state_dds <= ANY_INSTANCE_STATE; - view_state_dds <= ANY_VIEW_STATE; - sample_state_dds <= ANY_SAMPLE_STATE; - instance_handle_dds <= HANDLE_NIL; - max_samples_dds <= (others => '0'); - get_data_dds <= '0'; - ready_out_dds <= '0'; - - - case (dds_stage ) is - when START => - start_dds <= '1'; - opcode_dds <= dds.opcode; - instance_state_dds <= dds.istate; - view_state_dds <= dds.vstate; - sample_state_dds <= dds.sstate; - instance_handle_dds <= dds.inst; - max_samples_dds <= std_logic_vector(to_unsigned(dds.max_samples, WORD_WIDTH)); - when CHECK_SI => - if (si_valid = '1' and si_valid_data = '1') then - get_data_dds <= '1'; - end if; - when CHECK_DATA => - ready_out_dds <= '1'; - when others => - null; - end case; - end process; - - rtps_prc : process(all) - variable stimulus : TEST_PACKET_TYPE := EMPTY_TEST_PACKET; - begin - if rising_edge(clk) then - rtps_done <= '0'; - case (rtps_stage) is - when IDLE => - if (rtps_start = '1') then - rtps_stage <= START; - else - rtps_done <= '1'; - end if; - when START => - if (ack_rtps = '1') then - case (rtps.opcode) is - when ADD_CACHE_CHANGE => - gen_add_cache_change_dds(rtps.cc, rtps.lifespan, rtps.writer_pos, stimulus); - rtps_stage <= PUSH; - when others => - rtps_stage <= DONE; - end case; - end if; - when PUSH => - if (ready_in_rtps = '1') then - rtps_cnt <= rtps_cnt + 1; - if (rtps_cnt = stimulus.length-1) then - rtps_stage <= DONE; - end if; - end if; - when DONE => - if (done_rtps = '1') then - AffirmIfEqual(ret_id, HISTORY_CACHE_RESPONSE_TYPE'pos(ret_rtps), HISTORY_CACHE_RESPONSE_TYPE'pos(rtps.ret_code)); - rtps_stage <= IDLE; - end if; - end case; - end if; - - -- DEFAULT - start_rtps <= '0'; - opcode_rtps <= NOP; - valid_in_rtps <= '0'; - last_word_in_rtps <= '0'; - data_in_rtps <= (others => '0'); - - case (rtps_stage) is - when START => - start_rtps <= '1'; - opcode_rtps <= rtps.opcode; - case (rtps.opcode) is - when REMOVE_WRITER => - data_in_rtps <= std_logic_vector(to_unsigned(rtps.writer_pos,WORD_WIDTH)); - when others => - null; - end case; - when PUSH => - valid_in_rtps <= '1'; - data_in_rtps <= stimulus.data(rtps_cnt); - last_word_in_rtps <= stimulus.last(rtps_cnt); - when others => - null; - end case; - end process; - - watchdog : process - begin - wait for 1 ms; - Alert("Test timeout", FAILURE); - std.env.stop; - end process; - -end architecture; \ No newline at end of file diff --git a/src/Tests/Level_0/L0_dds_reader_test1_lrzkriu.vhd b/src/Tests/Level_0/L0_dds_reader_test1_lrzkriu.vhd deleted file mode 100644 index 0488cd5..0000000 --- a/src/Tests/Level_0/L0_dds_reader_test1_lrzkriu.vhd +++ /dev/null @@ -1,1690 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library osvvm; -- Utility Library -context osvvm.OsvvmContext; - -use work.rtps_package.all; -use work.user_config.all; -use work.rtps_config_package.all; -use work.rtps_test_package.all; - --- This testbench tests the RTPS handling of the DDS Reader. It tests the correctness of the RTPS ADD_CACHE_CHANGE, and REMOVE_WRITER Operations. --- Implicitly some DDS Operations are also tested, since they are used for state checking. --- More specifically the testbench covers following tests: --- TEST: NORMAL ADD_CACHE_CHANGE --- TEST: ADD_CACHE_CHANGE ON PAYLOAD MEMORY FULL --- TEST: REMOVE_WRITER [UNKNOWN WRITER] --- TEST: REMOVE_WRITER [KNOWN WRITER (1 Instance)] --- TEST: REMOVE_WRITER [KNOWN WRITER (>1 Instances)] --- TEST: REMOVE_WRITER [NOT_ALIVE_NO_WRITERS Transition] --- TEST: REMOVE_WRITER ON MAX_SAMPLES [NOT_ALIVE_NO_WRITERS Transition] --- TEST: REMOVE_WRITER ON MAX_SAMPLES_PER_INSTANCE [NOT_ALIVE_NO_WRITERS Transition] --- TEST: REMOVE_WRITER [Multiple Pending NOT_ALIVE_NO_WRITERS Transitions] --- TEST: SAMPLE WITH ALIGNED PAYLOAD --- TEST: SAMPLE WITH UNALIGNED PAYLOAD [>1 SLOT] --- TEST: SAMPLE WITH UNALIGNED PAYLOAD [<1 SLOT] --- TEST: NORMAL SAMPLE [KNOWN INSTANCE] --- TEST: NORMAL SAMPLE [UNKNOWN INSTANCE] --- TEST: UNREGISTER SAMPLE [KNOWN INSTANCE, KNOWN WRITER] --- TEST: UNREGISTER SAMPLE [KNOWN INSTANCE, UNKNOWN WRITER] --- TEST: UNREGISTER SAMPLE [UNKNOWN INSTANCE] --- TEST: UNREGISTER SAMPLE [NOT_ALIVE_NO_WRITERS INSTANCE] --- TEST: UNREGISTER SAMPLE [NOT_ALIVE_DISPOSED INSTANCE] --- TEST: UNREGISTER SAMPLE [NOT_ALIVE_DISPOSED INSTANCE, STALE INSTANCE TRANSITION] --- TEST: DISPOSE SAMPLE [KNOWN INSTANCE] --- TEST: DISPOSE SAMPLE [UNKNOWN INSTANCE] --- TEST: DISPOSE SAMPLE [NOT_ALIVE_NO_WRITERS INSTANCE] --- TEST: DISPOSE SAMPLE [NOT_ALIVE_DISPOSED INSTANCE] --- TEST: FILTER SAMPLE [KNOWN INSTANCE] --- TEST: FILTER SAMPLE [UNKNOWN INSTANCE] --- TEST: FILTER SAMPLE [NOT_ALIVE_DISPOSED INSTANCE] --- TEST: FILTER SAMPLE [NOT_ALIVE_NO_WRITERS INSTANCE] --- TEST: SAMPLE WITH KEY_HASH --- TEST: SAMPLE WITHOUT KEY_HASH --- TEST: SAMPLE WITH SERIALIZED KEY [WITH KEY_HASH] --- TEST: SAMPLE WITH SERIALIZED KEY [WITHOUT KEY_HASH] --- TEST: SAMPLE WITH EARLY TIMESTAMP [TIMESTAMP EARLIER THAN LAST READ] --- TEST: TEST SAMPLE WITH SERIALIZED KEY EFFECT ON PAYLOAD MEMORY FULLNESS --- TEST: ADD SAMPLE ON MAX_SAMPLES_PER_INSTANCE --- TEST: ADD SAMPLE ON MAX_SAMPLES [KNOWN INSTANCE] --- TEST: ADD SAMPLE ON MAX_SAMPLES [UNKNOWN INSTANCE] --- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKOWN INSTANCE, WITH STALE INSTANCE] --- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKOWN INSTANCE, WITHOUT STALE INSTANCE] --- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKOWN INSTANCE, WITHOUT STALE INSTANCE, WITH EMPTY INSTANCE] --- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKOWN INSTANCE, NOT_ALIVE_DISPOSED & STALE INSTANCE] --- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE, WITH STALE INSTANCE] --- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE, WITHOUT STALE INSTANCE] --- TEST: ADD SAMPLE BIGGER THAN AVAILABLE MEMORY SPACE --- TEST: ADD SAMPLE ON PAYLOAD MEMORY FULL & MAX_SAMPLES_PER_INSTANCE (Induce Double Remove) - -entity L0_dds_reader_test1_lrzkriu is -end entity; - - -architecture testbench of L0_dds_reader_test1_lrzkriu is - - -- *CONSTANT DECLARATION* - constant MAX_REMOTE_ENDPOINTS : natural := 3; - - -- *TYPE DECLARATION* - type DDS_STAGE_TYPE is (IDLE, START, DONE, CHECK_SI, CHECK_DATA, WAIT_EOC); - type RTPS_STAGE_TYPE is (IDLE, START, PUSH, DONE); - - -- *SIGNAL DECLARATION* - signal clk : std_logic := '0'; - signal reset : std_logic := '1'; - signal check_time : TIME_TYPE := TIME_ZERO; - signal start_rtps, start_dds, ack_rtps, ack_dds, done_rtps, done_dds : std_logic := '0'; - signal opcode_rtps : HISTORY_CACHE_OPCODE_TYPE := NOP; - signal opcode_dds : DDS_READER_OPCODE_TYPE := NOP; - signal ret_rtps : HISTORY_CACHE_RESPONSE_TYPE := ERROR; - signal ready_in_rtps, valid_in_rtps, last_word_in_rtps : std_logic := '0'; - signal ready_out_dds, valid_out_dds, last_word_out_dds : std_logic := '0'; - signal data_in_rtps, data_out_dds : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); - signal get_data_dds, si_valid_data, si_valid, eoc : std_logic := '0'; - signal return_code_dds : std_logic_vector(RETURN_CODE_WIDTH-1 downto 0) := (others => '0'); - signal status : std_logic_vector(STATUS_KIND_WIDTH-1 downto 0) := (others => '0'); - signal instance_state_dds, si_instance_state : std_logic_vector(INSTANCE_STATE_KIND_WIDTH-1 downto 0) := ANY_INSTANCE_STATE; - signal view_state_dds, si_view_state : std_logic_vector(VIEW_STATE_KIND_WIDTH-1 downto 0) := ANY_VIEW_STATE; - signal sample_state_dds, si_sample_state : std_logic_vector(SAMPLE_STATE_KIND_WIDTH-1 downto 0) := ANY_SAMPLE_STATE; - signal instance_handle_dds, si_instance_handle : INSTANCE_HANDLE_TYPE := HANDLE_NIL; - signal max_samples_dds : std_logic_vector(MAX_SAMPLES_WIDTH-1 downto 0) := (others => '0'); - signal si_source_timestamp : TIME_TYPE := TIME_INVALID; - signal si_publication_handle : INSTANCE_HANDLE_TYPE := HANDLE_NIL; - signal si_disposed_generation_count : std_logic_vector(DISPOSED_GENERATION_COUNT_WIDTH-1 downto 0) := (others => '0'); - signal si_no_writers_generation_count : std_logic_vector(NO_WRITERS_GENERATION_COUNT_WIDTH-1 downto 0) := (others => '0'); - signal si_sample_rank : std_logic_vector(SAMPLE_RANK_WIDTH-1 downto 0) := (others => '0'); - signal si_generation_rank : std_logic_vector(GENERATION_RANK_WIDTH-1 downto 0) := (others => '0'); - signal si_absolute_generation_rank: std_logic_vector(ABSOLUTE_GENERATION_COUNT_WIDTH-1 downto 0) := (others => '0'); - - signal dds_start , dds_done , rtps_start, rtps_done : std_logic := '0'; - signal dds_cnt, dds_cnt2, rtps_cnt : natural := 0; - signal dds_stage : DDS_STAGE_TYPE := IDLE; - signal rtps_stage : RTPS_STAGE_TYPE := IDLE; - shared variable dds : DDS_READER_TEST_TYPE := DEFAULT_DDS_READER_TEST; - shared variable rtps : RTPS_READER_TEST_TYPE := DEFAULT_RTPS_READER_TEST; - shared variable mem : DDS_READER_MEM_TYPE := DEFAULT_DDS_READER_MEM; - signal data_id, ret_id, sstate_id, vstate_id, istate_id, inst_id, ts_id, pub_id, dis_gen_cnt_id, no_w_gen_cnt_id, srank_id, grank_id, agrank_id, eoc_id, valid_id, status_id : AlertLogIDType; - - -- *FUNCTION DECLARATION* - function extract_key_hash (payload : TEST_PACKET_TYPE) return INSTANCE_HANDLE_TYPE is - variable ret : INSTANCE_HANDLE_TYPE := HANDLE_NIL; - begin - for i in 0 to 3 loop - ret(i) := not payload.data(i); - end loop; - - return ret; - end function; - - function gen_sn(input : natural) return SEQUENCENUMBER_TYPE is - variable ret : SEQUENCENUMBER_TYPE; - begin - ret(0) := (others => '0'); - ret(1) := unsigned(int(input, WORD_WIDTH)); - return ret; - end function; - -begin - - -- Unit Under Test - uut : entity work.dds_reader(arch) - generic map ( - TIME_BASED_FILTER_QOS => DURATION_ZERO, - DEADLINE_QOS => DURATION_INFINITE, - MAX_SAMPLES => std_logic_vector(to_unsigned(4,CDR_LONG_WIDTH)), - MAX_INSTANCES => std_logic_vector(to_unsigned(3,CDR_LONG_WIDTH)), - MAX_SAMPLES_PER_INSTANCE => std_logic_vector(to_unsigned(2,CDR_LONG_WIDTH)), - HISTORY_QOS => KEEP_LAST_HISTORY_QOS, - RELIABILITY_QOS => RELIABLE_RELIABILITY_QOS, - PRESENTATION_QOS => INSTANCE_PRESENTATION_QOS, - DESTINATION_ORDER_QOS => BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS, - COHERENT_ACCESS => FALSE, - ORDERED_ACCESS => FALSE, - WITH_KEY => TRUE, - PAYLOAD_FRAME_SIZE => 11, - MAX_REMOTE_ENDPOINTS => MAX_REMOTE_ENDPOINTS - ) - port map ( - clk => clk, - reset => reset, - time => check_time, - start_rtps => start_rtps, - opcode_rtps => opcode_rtps, - ack_rtps => ack_rtps, - done_rtps => done_rtps, - ret_rtps => ret_rtps, - data_in_rtps => data_in_rtps, - valid_in_rtps => valid_in_rtps, - ready_in_rtps => ready_in_rtps, - last_word_in_rtps => last_word_in_rtps, - start_dds => start_dds, - ack_dds => ack_dds, - opcode_dds => opcode_dds, - instance_state_dds => instance_state_dds, - view_state_dds => view_state_dds, - sample_state_dds => sample_state_dds, - instance_handle_dds => instance_handle_dds, - max_samples_dds => max_samples_dds, - get_data_dds => get_data_dds, - done_dds => done_dds, - return_code_dds => return_code_dds, - ready_out_dds => ready_out_dds, - valid_out_dds => valid_out_dds, - data_out_dds => data_out_dds, - last_word_out_dds => last_word_out_dds, - sample_info.sample_state => si_sample_state, - sample_info.view_state => si_view_state, - sample_info.instance_state => si_instance_state, - sample_info.source_timestamp => si_source_timestamp, - sample_info.instance_handle => si_instance_handle, - sample_info.publication_handle => si_publication_handle, - sample_info.disposed_generation_count => si_disposed_generation_count, - sample_info.no_writers_generation_count => si_no_writers_generation_count, - sample_info.sample_rank => si_sample_rank, - sample_info.generation_rank => si_generation_rank, - sample_info.absolute_generation_rank => si_absolute_generation_rank, - sample_info.valid_data => si_valid_data, - sample_info_valid => si_valid, - sample_info_ack => '1', - eoc => eoc, - status => status - ); - - stimulus_prc : process - variable RV : RandomPType; - variable cc : CACHE_CHANGE_TYPE := DEFAULT_CACHE_CHANGE; - variable s : SAMPLE_TYPE := DEFAULT_SAMPLE; - variable kh1, kh2, kh3, kh4, kh5 : INSTANCE_HANDLE_TYPE := HANDLE_NIL; - - alias idle_sig is <>; - - impure function gen_payload(key_hash : INSTANCE_HANDLE_TYPE; len : natural) return TEST_PACKET_TYPE is - variable ret : TEST_PACKET_TYPE := EMPTY_TEST_PACKET; - begin - assert (len >= 4) report "Payload length has to be at least 16 Bytes long" severity FAILURE; - - for i in 0 to len-1 loop - if (i < 4) then - -- NOTE: Beginning of payload is negated key to allow deterministic Key Hash generation from the kh_prc - ret.data(ret.length) := not key_hash(i); - else - ret.data(ret.length) := RV.RandSlv(WORD_WIDTH); - end if; - ret.length := ret.length + 1; - end loop; - ret.last(ret.length-1) := '1'; - - return ret; - end function; - - impure function gen_key_hash return KEY_HASH_TYPE is - variable ret : KEY_HASH_TYPE := KEY_HASH_NIL; - begin - for i in 0 to KEY_HASH_TYPE'length-1 loop - ret(i) := RV.RandSlv(WORD_WIDTH); - end loop; - return ret; - end function; - - procedure start_dds is - begin - dds_start <= '1'; - wait until rising_edge(clk); - dds_start <= '0'; - wait until rising_edge(clk); - end procedure; - - procedure start_rtps is - begin - rtps_start <= '1'; - wait until rising_edge(clk); - rtps_start <= '0'; - wait until rising_edge(clk); - end procedure; - - procedure wait_on_dds is - begin - if (dds_done /= '1') then - wait until dds_done = '1'; - end if; - end procedure; - - procedure wait_on_rtps is - begin - if (rtps_done /= '1') then - wait until rtps_done = '1'; - end if; - end procedure; - - procedure wait_on_completion is - begin - if (rtps_done /= '1' or dds_done /= '1') then - wait until rtps_done = '1' and dds_done = '1'; - end if; - end procedure; - - -- NOTE: This procedure waits until the idle_sig is high for at least - -- two consecutive clock cycles. - procedure wait_on_idle is - variable first : boolean := TRUE; - begin - loop - if (idle_sig /= '1') then - wait until idle_sig = '1'; - elsif (not first) then - exit; - end if; - wait until rising_edge(clk); - wait until rising_edge(clk); - first := FALSE; - end loop; - end procedure; - - begin - - SetAlertLogName("L0_dds_reader_test1_lrzkriu - (KEEP LAST, Reliable, Zero TIME_BASED_FILTER, Keyed, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER, ACCESS SCOPE Instance, Unordered) - RTPS Handling"); - SetAlertEnable(FAILURE, TRUE); - SetAlertEnable(ERROR, TRUE); - SetAlertEnable(WARNING, TRUE); - SetLogEnable(DEBUG, FALSE); - SetLogEnable(PASSED, FALSE); - SetLogEnable(INFO, TRUE); - RV.InitSeed(RV'instance_name); - sstate_id <= GetAlertLogID("Sample State", ALERTLOG_BASE_ID); - vstate_id <= GetAlertLogID("View State", ALERTLOG_BASE_ID); - istate_id <= GetAlertLogID("Instance State", ALERTLOG_BASE_ID); - ts_id <= GetAlertLogID("Source Timestamp", ALERTLOG_BASE_ID); - inst_id <= GetAlertLogID("Instance Handle", ALERTLOG_BASE_ID); - pub_id <= GetAlertLogID("Publication Hanlde", ALERTLOG_BASE_ID); - dis_gen_cnt_id <= GetAlertLogID("Disposed Generation Count", ALERTLOG_BASE_ID); - no_w_gen_cnt_id <= GetAlertLogID("No Writers Generation Count", ALERTLOG_BASE_ID); - srank_id <= GetAlertLogID("Sample Rank", ALERTLOG_BASE_ID); - grank_id <= GetAlertLogID("Generation Rank", ALERTLOG_BASE_ID); - agrank_id <= GetAlertLogID("Absolute Generation Rank", ALERTLOG_BASE_ID); - eoc_id <= GetAlertLogID("End of Collection", ALERTLOG_BASE_ID); - valid_id <= GetAlertLogID("Valid Data", ALERTLOG_BASE_ID); - data_id <= GetAlertLogID("Data Out", ALERTLOG_BASE_ID); - ret_id <= GetAlertLogID("Return Code", ALERTLOG_BASE_ID); - status_id <= GetAlertLogID("Communication Status", ALERTLOG_BASE_ID); - - -- Key Hashes - kh3 := (x"0CEAB0C6", x"FA04B9AD", x"A96EB495", x"4E0EB999"); - kh4 := (x"A7EB605C", x"FF4BEF3A", x"3C5E8724", x"CCA0CA67"); - kh2 := (x"BC070AC4", x"0BAB5811", x"14EA8D61", x"F669189B"); - kh1 := (x"F12C31DA", x"E3FE0F3F", x"01F36685", x"446518CA"); - kh5 := gen_key_hash; - - - - Log("Initiating Test", INFO); - reset <= '1'; - wait until rising_edge(clk); - wait until rising_edge(clk); - reset <= '0'; - -- MEM: 0, 0, 0, 0 - -- ISTATE: - - -- WRITER: - - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh1; - cc.payload := gen_payload(kh1,10); - cc.src_timestamp := gen_duration(1,0); - - -- TEST: NORMAL ADD_CACHE_CHANGE - -- TEST: SAMPLE WITH ALIGNED PAYLOAD - -- TEST: NORMAL SAMPLE [UNKNOWN INSTANCE] - -- TEST: SAMPLE WITH KEY_HASH - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Aligned Payload] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - rtps.ret_code := OK; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S1, 0, 0, 0 - -- ISTATE: I1:ALIVE - -- WRITER: W0:I1 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := HANDLE_NIL; - cc.payload := gen_payload(kh1,10); - cc.src_timestamp := gen_duration(2,0); - - -- TEST: SAMPLE WITHOUT KEY_HASH - -- TEST: NORMAL SAMPLE [KNOWN INSTANCE] - - Log("RTPS Operation ADD_CACHE_CHANGE [NO KEY_HASH, Instance 1, Writer 0, Aligned Payload] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - rtps.ret_code := OK; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - s.inst := kh1; - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S1, I1S2, 0, 0 - -- ISTATE: I1:ALIVE - -- WRITER: W0:I1 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh1; - cc.payload := gen_payload(kh1,18); - cc.src_timestamp := gen_duration(3,0); - - -- TEST: SAMPLE WITH UNALIGNED PAYLOAD [>1 SLOT] - -- TEST: ADD SAMPLE ON MAX_SAMPLES_PER_INSTANCE - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Unaligned Payload (2 Slots)] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - rtps.ret_code := OK; - remove_sample(0,mem); - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S2, I1S3+, 0, 0 - -- ISTATE: I1:ALIVE - -- WRITER: W0:I1 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - -- VALIDATE STATE - - Log("DDS Operation READ [MAX_SAMPLES 4, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ; - dds.max_samples := 4; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - start_dds; - wait_on_dds; - wait_on_idle; - -- MEM: I1S2, I1S3+, 0, 0 - -- ISTATE: I1:ALIVE - -- WRITER: W0:I1 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - Log("DDS Operation TAKE [MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE; - dds.max_samples := 1; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - start_dds; - wait_on_dds; - wait_on_idle; - -- MEM: I1S3+, 0, 0, 0 - -- ISTATE: I1:ALIVE - -- WRITER: W0:I1 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_DISPOSED; - cc.instance := kh1; - cc.payload := gen_payload(kh1,5); - cc.src_timestamp := gen_duration(4,0); - - -- TEST: DISPOSE SAMPLE [KNOWN INSTANCE] - -- TEST: SAMPLE WITH SERIALIZED KEY [WITH KEY_HASH] - -- TEST: SAMPLE WITH UNALIGNED PAYLOAD [<1 SLOT] - - Log("RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Instance 1, Writer 0] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - rtps.ret_code := OK; - s := to_sample(cc,NOT_ALIVE_DISPOSED_INSTANCE_STATE); - s.inst := kh1; - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S3+, I1S4-, 0, 0 - -- ISTATE: I1:DISPOSED - -- WRITER: W0:I1 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh2; - cc.payload := gen_payload(kh2,20); - cc.src_timestamp := gen_duration(5,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 2, Writer 1, Aligned Payload (2 Slots)] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 1; - rtps.ret_code := OK; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S3+, I1S4-, I2S1+, 0 - -- ISTATE: I1:DISPOSED, I2:ALIVE - -- WRITER: W0:I1, W1:I2 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh3; - cc.payload := gen_payload(kh3,10); - cc.src_timestamp := gen_duration(6,0); - - -- TEST: TEST SAMPLE WITH SERIALIZED KEY EFFECT ON PAYLOAD MEMORY FULLNESS - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 3, Writer 1, Aligned Payload] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 1; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S3+, I1S4-, I2S1+, I3S1 - -- ISTATE: I1:DISPOSED, I2:ALIVE, I3:ALIVE - -- WRITER: W0:I1, W1:I2,I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - -- TEST: REMOVE_WRITER [UNKNOWN WRITER] - - Log("RTPS Operation REMOVE_WRITER [Writer 2] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := REMOVE_WRITER; - rtps.writer_pos := 2; - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S3+, I1S4-, I2S1+, I3S1 - -- ISTATE: I1:DISPOSED, I2:ALIVE, I3:ALIVE - -- WRITER: W0:I1, W1:I2,I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - Log("DDS Operation TAKE [MAX_SAMPLES 1, NOT_READ_SAMPLE_STATE, NOT_ALIVE_DISPOSED_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE; - dds.max_samples := 1; - dds.sstate := NOT_READ_SAMPLE_STATE; - dds.istate := NOT_ALIVE_DISPOSED_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - start_dds; - wait_on_dds; - wait_on_idle; - -- MEM: I1S3+, I2S1+, I3S1, 0 - -- ISTATE: I1:DISPOSED, I2:ALIVE, I3:ALIVE - -- WRITER: W0:I1, W1:I2,I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh3; - cc.payload := gen_payload(kh3,10); - cc.src_timestamp := gen_duration(7,0); - - -- TEST: ADD_CACHE_CHANGE ON PAYLOAD MEMORY FULL - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 3, Writer 2, Aligned Payload] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 2; - remove_sample(0,mem); - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I2S1+, I3S1, I3S2, 0 - -- ISTATE: I1:DISPOSED, I2:ALIVE, I3:ALIVE - -- WRITER: W0:I1, W1:I2,I3, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh4; - cc.payload := gen_payload(kh4,10); - cc.src_timestamp := gen_duration(8,0); - - -- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKOWN INSTANCE, WITHOUT STALE INSTANCE, WITH EMPTY INSTANCE] - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 4, Writer 1, Aligned Payload] (REJECTED: MAX_INSTANCES exceeded)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 1; - rtps.ret_code := REJECTED; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I2S1+, I3S1, I3S2, 0 - -- ISTATE: I1:DISPOSED, I2:ALIVE, I3:ALIVE - -- WRITER: W0:I1, W1:I2,I3, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - -- TEST: REMOVE_WRITER [KNOWN WRITER (1 Instance)] - - Log("RTPS Operation REMOVE_WRITER [Writer 0] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := REMOVE_WRITER; - rtps.writer_pos := 0; - change_istate(kh1, NOT_ALIVE_NO_WRITERS_INSTANCE_STATE, mem); - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I2S1+, I3S1, I3S2, 0 - -- ISTATE: I1:DISPOSED, I2:ALIVE, I3:ALIVE - -- WRITER: W1:I2,I3, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - -- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKOWN INSTANCE, WITH STALE INSTANCE] - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 4, Writer 1, Aligned Payload] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 1; - remove_inst(kh1, mem); - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I2S1+, I3S1, I3S2, I4S1 - -- ISTATE: I2:ALIVE, I3:ALIVE, I4:ALIVE - -- WRITER: W1:I2,I3,I4, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - -- VALIDATE STATE - - Log("DDS Operation READ [MAX_SAMPLES 4, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ; - dds.max_samples := 4; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - start_dds; - wait_on_dds; - wait_on_idle; - -- MEM: I2S1+, I3S1, I3S2, I4S1 - -- ISTATE: I2:ALIVE, I3:ALIVE, I4:ALIVE - -- WRITER: W1:I2,I3,I4, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - Log("DDS Operation TAKE [MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE; - dds.max_samples := 1; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - start_dds; - wait_on_dds; - wait_on_idle; - -- MEM: I3S1, I3S2, I4S1, 0 - -- ISTATE: I2:ALIVE, I3:ALIVE, I4:ALIVE - -- WRITER: W1:I2,I3,I4, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh1; - cc.payload := gen_payload(kh1,10); - cc.src_timestamp := gen_duration(9,0); - - -- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKOWN INSTANCE, WITHOUT STALE INSTANCE] - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Aligned Payload] (REJECTED: MAX_INSTANCES exceeded)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - rtps.ret_code := REJECTED; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I3S1, I3S2, I4S1, 0 - -- ISTATE: I2:ALIVE, I3:ALIVE, I4:ALIVE - -- WRITER: W1:I2,I3,I4, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh4; - cc.payload := gen_payload(kh4,10); - cc.src_timestamp := gen_duration(10,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 4, Writer 1, Aligned Payload] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 1; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I3S1, I3S2, I4S1, I4S2 - -- ISTATE: I2:ALIVE, I3:ALIVE, I4:ALIVE - -- WRITER: W1:I2,I3,I4, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh1; - cc.payload := gen_payload(kh1,10); - cc.src_timestamp := gen_duration(11,0); - - -- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE, WITHOUT STALE INSTANCE] - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Aligned Payload] (REJECTED: MAX_INSTANCES exceeded)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - rtps.ret_code := REJECTED; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I3S1, I3S2, I4S1, I4S2 - -- ISTATE: I2:ALIVE, I3:ALIVE, I4:ALIVE - -- WRITER: W1:I2,I3,I4, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - Log("DDS Operation READ [MAX_SAMPLES 4, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ; - dds.max_samples := 4; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - start_dds; - wait_on_dds; - wait_on_idle; - -- MEM: I3S1, I3S2, I4S1, I4S2 - -- ISTATE: I2:ALIVE, I3:ALIVE, I4:ALIVE - -- WRITER: W1:I2,I3,I4, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - -- TEST: REMOVE_WRITER [KNOWN WRITER (>1 Instances)] - -- TEST: REMOVE_WRITER [NOT_ALIVE_NO_WRITERS Transition] - -- TEST: REMOVE_WRITER ON MAX_SAMPLES [NOT_ALIVE_NO_WRITERS Transition] - -- TEST: REMOVE_WRITER ON MAX_SAMPLES_PER_INSTANCE [NOT_ALIVE_NO_WRITERS Transition] - -- TEST: REMOVE_WRITER [Multiple Pending NOT_ALIVE_NO_WRITERS Transitions] - - Log("RTPS Operation REMOVE_WRITER [Writer 1] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := REMOVE_WRITER; - rtps.writer_pos := 1; - remove_sample(0,mem); - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_UNREGISTERED; - cc.instance := kh2; - cc.src_timestamp := check_time; - s := to_sample(cc,NOT_ALIVE_NO_WRITERS_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - remove_sample(1,mem); - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_UNREGISTERED; - cc.instance := kh4; - cc.src_timestamp := check_time; - s := to_sample(cc,NOT_ALIVE_NO_WRITERS_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I3S2, I4S2, I2S2-, I4S3- - -- ISTATE: I2:NO_WRITERS, I3:ALIVE, I4:NO_WRITERS - -- WRITER: W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - Log("DDS Operation TAKE_INSTANCE [Instance 2, MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE_INSTANCE; - dds.max_samples := 1; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.inst := kh2; - start_dds; - wait_on_dds; - wait_on_idle; - -- MEM: I3S2, I4S2, I4S3-, 0 - -- ISTATE: I2:NO_WRITERS, I3:ALIVE, I4:NO_WRITERS - -- WRITER: W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh3; - cc.payload := gen_payload(kh3,10); - cc.src_timestamp := gen_duration(12,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 3, Writer 2, Aligned Payload] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 2; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I3S2, I4S2, I4S3-, I3S3 - -- ISTATE: I2:NO_WRITERS, I3:ALIVE, I4:NO_WRITERS - -- WRITER: W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - Log("DDS Operation READ [MAX_SAMPLES 4, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ; - dds.max_samples := 4; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - start_dds; - wait_on_dds; - wait_on_idle; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh1; - cc.payload := gen_payload(kh1,10); - cc.src_timestamp := gen_duration(13,0); - - -- TEST: ADD SAMPLE ON MAX_SAMPLES [UNKNOWN INSTANCE] - -- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE, WITH STALE INSTANCE] - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Aligned Payload] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - remove_inst(kh2,mem); - remove_sample(0,mem); - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I4S2, I4S3-, I3S3, I1S1 - -- ISTATE: I1:ALIVE, I3:ALIVE, I4:NO_WRITERS - -- WRITER: W0:I1, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh3; - cc.payload := gen_payload(kh3,10); - cc.src_timestamp := gen_duration(14,0); - - -- TEST: ADD SAMPLE ON MAX_SAMPLES [KNOWN INSTANCE] - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 3, Writer 2, Aligned Payload] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 2; - remove_sample(0,mem); - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I4S3-, I3S3, I1S1, I3S4 - -- ISTATE: I1:ALIVE, I3:ALIVE, I4:NO_WRITERS - -- WRITER: W0:I1, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - -- VALIDATE STATE - - Log("DDS Operation READ [MAX_SAMPLES 4, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ; - dds.max_samples := 4; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - start_dds; - wait_on_dds; - wait_on_idle; - -- MEM: I4S3-, I3S3, I1S1, I3S4 - -- ISTATE: I1:ALIVE, I3:ALIVE, I4:NO_WRITERS - -- WRITER: W0:I1, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh1; - cc.payload := gen_payload(kh1,10); - cc.src_timestamp := gen_duration(15,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Aligned Payload] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - remove_sample(0,mem); - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I3S3, I1S1, I3S4, I1S2 - -- ISTATE: I1:ALIVE, I3:ALIVE, I4:NO_WRITERS - -- WRITER: W0:I1, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh1; - cc.payload := gen_payload(kh1,10); - cc.src_timestamp := gen_duration(16,0); - - -- TEST: ADD SAMPLE ON PAYLOAD MEMORY FULL & MAX_SAMPLES_PER_INSTANCE (Induce Double Remove) - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Aligned Payload] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - remove_sample(1,mem); - remove_sample(0,mem); - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I3S4, I1S2, I1S3, 0 - -- ISTATE: I1:ALIVE, I3:ALIVE, I4:NO_WRITERS - -- WRITER: W0:I1, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh3; - cc.payload := gen_payload(kh3,30); - cc.src_timestamp := gen_duration(17,0); - - -- TEST: ADD SAMPLE BIGGER THAN AVAILABLE MEMORY SPACE - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 3, Writer 0, Aligned Payload (3 Slots)] (REJECTED: Payload memory Full)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - rtps.ret_code := REJECTED; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I3S4, I1S2, I1S3, 0 - -- ISTATE: I1:ALIVE, I3:ALIVE, I4:NO_WRITERS - -- WRITER: W0:I1, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_DISPOSED; - cc.instance := HANDLE_NIL; - cc.payload := gen_payload(kh4,5); - cc.src_timestamp := gen_duration(18,0); - - -- TEST: DISPOSE SAMPLE [NOT_ALIVE_NO_WRITERS INSTANCE] - -- TEST: SAMPLE WITH SERIALIZED KEY [WITHOUT KEY_HASH] - - Log("RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Instance 4, Writer 1] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 1; - s := to_sample(cc,NOT_ALIVE_DISPOSED_INSTANCE_STATE); - s.inst := kh4; - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I3S4, I1S2, I1S3, I4S4- - -- ISTATE: I1:ALIVE, I3:ALIVE, I4:DISPOSED - -- WRITER: W0:I1, W1:I4, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - -- VALIDATE STATE - - Log("DDS Operation TAKE [MAX_SAMPLES 4, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE; - dds.max_samples := 4; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - start_dds; - wait_on_dds; - wait_on_idle; - -- MEM: 0, 0, 0, 0 - -- ISTATE: I1:ALIVE, I3:ALIVE, I4:DISPOSED - -- WRITER: W0:I1, W1:I4, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_DISPOSED; - cc.instance := kh4; - cc.payload := gen_payload(kh4,5); - cc.src_timestamp := gen_duration(19,0); - - -- TEST: DISPOSE SAMPLE [NOT_ALIVE_DISPOSED INSTANCE] - - Log("RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Instance 4, Writer 0] (IGNORED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: 0, 0, 0, 0 - -- ISTATE: I1:ALIVE, I3:ALIVE, I4:DISPOSED - -- WRITER: W0:I1,I4 W1:I4, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_UNREGISTERED; - cc.instance := kh4; - cc.payload := gen_payload(kh4,5); - cc.src_timestamp := gen_duration(20,0); - - -- TEST: UNREGISTER SAMPLE [KNOWN INSTANCE, KNOWN WRITER] - -- TEST: UNREGISTER SAMPLE [NOT_ALIVE_DISPOSED INSTANCE] - - Log("RTPS Operation ADD_CACHE_CHANGE [UNREGISTER, Instance 4, Writer 0] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: 0, 0, 0, 0 - -- ISTATE: I1:ALIVE, I3:ALIVE, I4:DISPOSED - -- WRITER: W0:I1, W1:I4, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_UNREGISTERED; - cc.instance := kh1; - cc.payload := gen_payload(kh1,5); - cc.src_timestamp := gen_duration(21,0); - - -- TEST: UNREGISTER SAMPLE [KNOWN INSTANCE, UNKNOWN WRITER] - - Log("RTPS Operation ADD_CACHE_CHANGE [UNREGISTER, Instance 1, Writer 1] (IGNORED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 1; - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: 0, 0, 0, 0 - -- ISTATE: I1:ALIVE, I3:ALIVE, I4:DISPOSED - -- WRITER: W0:I1, W1:I4, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_UNREGISTERED; - cc.instance := kh2; - cc.payload := gen_payload(kh2,5); - cc.src_timestamp := gen_duration(22,0); - - -- TEST: UNREGISTER SAMPLE [UNKNOWN INSTANCE] - - Log("RTPS Operation ADD_CACHE_CHANGE [UNREGISTER, Instance 2, Writer 1] (IGNORED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 1; - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: 0, 0, 0, 0 - -- ISTATE: I1:ALIVE, I3:ALIVE, I4:DISPOSED - -- WRITER: W0:I1, W1:I4, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_UNREGISTERED; - cc.instance := kh1; - cc.payload := gen_payload(kh1,5); - cc.src_timestamp := gen_duration(23,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [UNREGISTER, Instance 1, Writer 0] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - s := to_sample(cc,NOT_ALIVE_NO_WRITERS_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S4-, 0, 0, 0 - -- ISTATE: I1:NO_WRITERS, I3:ALIVE, I4:DISPOSED - -- WRITER: W1:I4, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_UNREGISTERED; - cc.instance := kh1; - cc.payload := gen_payload(kh1,5); - cc.src_timestamp := gen_duration(24,0); - - -- TEST: UNREGISTER SAMPLE [NOT_ALIVE_NO_WRITERS INSTANCE] - - Log("RTPS Operation ADD_CACHE_CHANGE [UNREGISTER, Instance 1, Writer 2] (IGNORED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 2; - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S4-, 0, 0, 0 - -- ISTATE: I1:NO_WRITERS, I3:ALIVE, I4:DISPOSED - -- WRITER: W1:I4, W2:I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := ALIVE_FILTERED; - cc.instance := kh1; - cc.payload := gen_payload(kh1,5); - cc.src_timestamp := gen_duration(25,0); - - -- TEST: FILTER SAMPLE [KNOWN INSTANCE] - -- TEST: FILTER SAMPLE [NOT_ALIVE_NO_WRITERS INSTANCE] - - Log("RTPS Operation ADD_CACHE_CHANGE [FILTERED, Instance 1, Writer 2] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - rtps.writer_pos := 2; - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S4-, I1S5-, 0, 0 - -- ISTATE: I1:ALIVE, I3:ALIVE, I4:DISPOSED - -- WRITER: W1:I4, W2:I1,I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_UNREGISTERED; - cc.instance := kh4; - cc.payload := gen_payload(kh1,5); - cc.src_timestamp := gen_duration(26,0); - - -- TEST: UNREGISTER SAMPLE [NOT_ALIVE_DISPOSED INSTANCE, STALE INSTANCE TRANSITION] - - Log("RTPS Operation ADD_CACHE_CHANGE [UNREGISTER, Instance 4, Writer 1] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 1; - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S4-, I1S5-, 0, 0 - -- ISTATE: I1:ALIVE, I3:ALIVE, I4:DISPOSED - -- WRITER: W2:I1,I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh2; - cc.payload := gen_payload(kh2,10); - cc.src_timestamp := gen_duration(27,0); - - -- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKOWN INSTANCE, NOT_ALIVE_DISPOSED & STALE INSTANCE] - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 2, Writer 0, Aligned Payload] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - remove_inst(kh4, mem); - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S4-, I1S5-, I2S1, 0 - -- ISTATE: I1:ALIVE, I2:ALIVE, I3:ALIVE - -- WRITER: W0:I2, W2:I1,I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - -- VALIDATE STATE - - Log("DDS Operation TAKE [MAX_SAMPLES 4, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE; - dds.max_samples := 4; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - start_dds; - wait_on_dds; - wait_on_idle; - -- MEM: 0, 0, 0, 0 - -- ISTATE: I1:ALIVE, I2:ALIVE, I3:ALIVE - -- WRITER: W0:I2, W2:I1,I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_DISPOSED; - cc.instance := kh1; - cc.payload := gen_payload(kh1,5); - cc.src_timestamp := gen_duration(28,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Instance 1, Writer 2] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 2; - s := to_sample(cc,NOT_ALIVE_DISPOSED_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S6-, 0, 0, 0 - -- ISTATE: I1:DISPOSED, I2:ALIVE, I3:ALIVE - -- WRITER: W0:I2, W2:I1,I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := ALIVE_FILTERED; - cc.instance := kh1; - cc.payload := gen_payload(kh1,5); - cc.src_timestamp := gen_duration(29,0); - - -- TEST: FILTER SAMPLE [NOT_ALIVE_DISPOSED INSTANCE] - - Log("RTPS Operation ADD_CACHE_CHANGE [FILTERED, Instance 1, Writer 2] (ACCEPT)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - rtps.writer_pos := 2; - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S6-, I1S7-, 0, 0 - -- ISTATE: I1:ALIVE, I2:ALIVE, I3:ALIVE - -- WRITER: W0:I2, W2:I1,I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := ALIVE_FILTERED; - cc.instance := kh4; - cc.payload := gen_payload(kh4,5); - cc.src_timestamp := gen_duration(30,0); - - -- TEST: FILTER SAMPLE [UNKNOWN INSTANCE] - - Log("RTPS Operation ADD_CACHE_CHANGE [FILTERED, Instance 4, Writer 1] (IGNORED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 1; - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S6-, I1S7-, 0, 0 - -- ISTATE: I1:ALIVE, I2:ALIVE, I3:ALIVE - -- WRITER: W0:I2, W2:I1,I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh3; - cc.payload := gen_payload(kh3,10); - cc.src_timestamp := gen_duration(10,0); - - -- TEST: SAMPLE WITH EARLY TIMESTAMP [TIMESTAMP EARLIER THAN LAST READ] - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 3, Writer 2, Aligned Payload] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 2; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S6-, I1S7-, I3S5, 0 - -- ISTATE: I1:ALIVE, I2:ALIVE, I3:ALIVE - -- WRITER: W0:I2, W2:I1,I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_UNREGISTERED; - cc.instance := kh2; - cc.payload := gen_payload(kh2,5); - cc.src_timestamp := gen_duration(31,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [UNREGISTER, Instance 2, Writer 0] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - s := to_sample(cc,NOT_ALIVE_NO_WRITERS_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S6-, I1S7-, I3S5, I2S2- - -- ISTATE: I1:ALIVE, I2:NO_WRITERS, I3: ALIVE - -- WRITER: W2:I1,I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - -- VALIDATE STATE - - Log("DDS Operation TAKE [MAX_SAMPLES 4, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE; - dds.max_samples := 4; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - start_dds; - wait_on_dds; - wait_on_idle; - -- MEM: 0, 0, 0, 0 - -- ISTATE: I1:ALIVE, I2:NO_WRITERS, I3: ALIVE - -- WRITER: W2:I1,I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_DISPOSED; - cc.instance := kh4; - cc.payload := gen_payload(kh4,5); - cc.src_timestamp := gen_duration(32,0); - - -- TEST: DISPOSE SAMPLE [UNKNOWN INSTANCE] - - Log("RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Instance 4, Writer 1] (ACCPETED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 1; - s := to_sample(cc,NOT_ALIVE_DISPOSED_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I4S1-, 0, 0, 0 - -- ISTATE: I1:ALIVE, I3: ALIVE, I4:DISPOSED - -- WRITER: W1:I4, W2:I1,I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS, "Expected: 1", "Received: 0"); - - -- VALIDATE STATE - - Log("DDS Operation READ [MAX_SAMPLES 4, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE; - dds.max_samples := 4; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := NOT_ALIVE_DISPOSED_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - start_dds; - wait_on_dds; - wait_on_idle; - -- MEM: I4S1-, 0, 0, 0 - -- ISTATE: I1:ALIVE, I3: ALIVE, I4:DISPOSED - -- WRITER: W1:I4, W2:I1,I3 - - AffirmIf(status_id,(status and DATA_AVAILABLE_STATUS) /= DATA_AVAILABLE_STATUS, "Expected: 0", "Received: 1"); - - wait_on_completion; - TranscriptOpen(RESULTS_FILE, APPEND_MODE); - SetTranscriptMirror; - ReportAlerts; - TranscriptClose; - std.env.stop; - wait; - end process; - - clock_prc : process - begin - clk <= '0'; - wait for 25 ns; - clk <= '1'; - wait for 25 ns; - end process; - - alert_prc : process(all) - begin - if rising_edge(clk) then - -- TODO - end if; - end process; - - dds_prc : process(all) - variable col : COLLECTION_TYPE := DEFAULT_COLLECTION; - begin - if rising_edge(clk) then - dds_done <= '0'; - case (dds_stage ) is - when IDLE => - if (dds_start = '1') then - dds_stage <= START; - else - dds_done <= '1'; - end if; - when START => - if (ack_dds = '1') then - dds_stage <= DONE; - dds_cnt <= 0; - end if; - when DONE => - if (done_dds = '1') then - AffirmIfEqual(ret_id, return_code_dds, dds.ret_code); - case (dds.ret_code) is - when RETCODE_OK => - gen_collection(mem, col, dds, INSTANCE_PRESENTATION_QOS, FALSE); - dds_stage <= CHECK_SI; - dds_cnt <= 0; - when others => - dds_stage <= IDLE; - end case; - end if; - when CHECK_SI => - if (si_valid = '1') then - AffirmIfEqual(sstate_id, si_sample_state, col.s(dds_cnt).sstate); - AffirmIfEqual(vstate_id, si_view_state, col.s(dds_cnt).vstate); - AffirmIfEqual(istate_id, si_instance_state, col.s(dds_cnt).istate); - AffirmIfEqual(ts_id, to_unsigned(si_source_timestamp), to_unsigned(col.s(dds_cnt).ts)); - AffirmIfEqual(inst_id, to_unsigned(si_instance_handle), to_unsigned(col.s(dds_cnt).inst)); - AffirmIfEqual(pub_id, to_unsigned(si_publication_handle), to_unsigned(HANDLE_NIL)); - AffirmIfEqual(dis_gen_cnt_id, si_disposed_generation_count, std_logic_vector(to_unsigned(col.s(dds_cnt).dis_gen_cnt,WORD_WIDTH))); - AffirmIfEqual(no_w_gen_cnt_id, si_no_writers_generation_count, std_logic_vector(to_unsigned(col.s(dds_cnt).no_w_gen_cnt,WORD_WIDTH))); - AffirmIfEqual(srank_id, si_sample_rank, std_logic_vector(to_unsigned(col.s(dds_cnt).srank,WORD_WIDTH))); - AffirmIfEqual(grank_id, si_generation_rank, std_logic_vector(to_unsigned(col.s(dds_cnt).grank,WORD_WIDTH))); - AffirmIfEqual(agrank_id, si_absolute_generation_rank, std_logic_vector(to_unsigned(col.s(dds_cnt).agrank,WORD_WIDTH))); - if (si_valid_data = '1') then - AffirmIf(valid_id, col.s(dds_cnt).data /= EMPTY_TEST_PACKET, "Sample with Data not expected"); - dds_stage <= CHECK_DATA; - dds_cnt2 <= 0; - else - AffirmIf(valid_id, col.s(dds_cnt).data = EMPTY_TEST_PACKET, "Sample with Data expected"); - if (dds_cnt = col.len-1) then - -- DONE - dds_stage <= WAIT_EOC; - else - dds_cnt <= dds_cnt + 1; - end if; - end if; - end if; - AffirmIf(eoc_id, eoc = '0', "EOC pulled high"); - when CHECK_DATA => - if (valid_out_dds = '1') then - AffirmIfEqual(data_id, data_out_dds, col.s(dds_cnt).data.data(dds_cnt2)); - dds_cnt2 <= dds_cnt2 + 1; - if (dds_cnt2 = col.s(dds_cnt).data.length-1) then - AlertIf(data_id, last_word_out_dds /= '1', "Last Word Signal not pulled High", ERROR); - if (dds_cnt = col.len-1) then - -- DONE - dds_stage <= WAIT_EOC; - else - dds_stage <= CHECK_SI; - dds_cnt <= dds_cnt + 1; - end if; - end if; - end if; - when WAIT_EOC => - if (eoc = '1') then - dds_stage <= IDLE; - end if; - end case; - end if; - - -- DEFAULT - start_dds <= '0'; - opcode_dds <= NOP; - instance_state_dds <= ANY_INSTANCE_STATE; - view_state_dds <= ANY_VIEW_STATE; - sample_state_dds <= ANY_SAMPLE_STATE; - instance_handle_dds <= HANDLE_NIL; - max_samples_dds <= (others => '0'); - get_data_dds <= '0'; - ready_out_dds <= '0'; - - - case (dds_stage ) is - when START => - start_dds <= '1'; - opcode_dds <= dds.opcode; - instance_state_dds <= dds.istate; - view_state_dds <= dds.vstate; - sample_state_dds <= dds.sstate; - instance_handle_dds <= dds.inst; - max_samples_dds <= std_logic_vector(to_unsigned(dds.max_samples, WORD_WIDTH)); - when CHECK_SI => - if (si_valid = '1' and si_valid_data = '1') then - get_data_dds <= '1'; - end if; - when CHECK_DATA => - ready_out_dds <= '1'; - when others => - null; - end case; - end process; - - rtps_prc : process(all) - variable stimulus : TEST_PACKET_TYPE := EMPTY_TEST_PACKET; - begin - if rising_edge(clk) then - rtps_done <= '0'; - case (rtps_stage) is - when IDLE => - if (rtps_start = '1') then - rtps_stage <= START; - else - rtps_done <= '1'; - end if; - when START => - if (ack_rtps = '1') then - case (rtps.opcode) is - when ADD_CACHE_CHANGE => - gen_add_cache_change_dds(rtps.cc, rtps.lifespan, rtps.writer_pos, stimulus); - rtps_stage <= PUSH; - when others => - rtps_stage <= DONE; - end case; - end if; - when PUSH => - if (ready_in_rtps = '1') then - rtps_cnt <= rtps_cnt + 1; - if (rtps_cnt = stimulus.length-1) then - rtps_stage <= DONE; - end if; - end if; - when DONE => - if (done_rtps = '1') then - AffirmIfEqual(ret_id, HISTORY_CACHE_RESPONSE_TYPE'pos(ret_rtps), HISTORY_CACHE_RESPONSE_TYPE'pos(rtps.ret_code)); - rtps_stage <= IDLE; - end if; - end case; - end if; - - -- DEFAULT - start_rtps <= '0'; - opcode_rtps <= NOP; - valid_in_rtps <= '0'; - last_word_in_rtps <= '0'; - data_in_rtps <= (others => '0'); - - case (rtps_stage) is - when START => - start_rtps <= '1'; - opcode_rtps <= rtps.opcode; - case (rtps.opcode) is - when REMOVE_WRITER => - data_in_rtps <= std_logic_vector(to_unsigned(rtps.writer_pos,WORD_WIDTH)); - when others => - null; - end case; - when PUSH => - valid_in_rtps <= '1'; - data_in_rtps <= stimulus.data(rtps_cnt); - last_word_in_rtps <= stimulus.last(rtps_cnt); - when others => - null; - end case; - end process; - - watchdog : process - begin - wait for 1 ms; - Alert("Test timeout", FAILURE); - std.env.stop; - end process; - -end architecture; \ No newline at end of file diff --git a/src/Tests/Level_0/L0_dds_reader_test2.vhd b/src/Tests/Level_0/L0_dds_reader_test2.vhd new file mode 100644 index 0000000..3cdaaae --- /dev/null +++ b/src/Tests/Level_0/L0_dds_reader_test2.vhd @@ -0,0 +1,776 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library osvvm; -- Utility Library +context osvvm.OsvvmContext; + +use work.rtps_package.all; +use work.user_config.all; +use work.rtps_config_package.all; +use work.rtps_test_package.all; + +-- This testbench tests the handling of the TIME_BASED_FILTER QoS of the DDS Reader. + +entity L0_dds_reader_test2 is +end entity; + + +architecture testbench of L0_dds_reader_test2 is + + -- *CONSTANT DECLARATION* + constant MAX_REMOTE_ENDPOINTS : natural := 3; + constant NUM_READERS : natural := 2; + + impure function gen_test_config return CONFIG_ARRAY_TYPE is + variable ret : CONFIG_ARRAY_TYPE(0 to NUM_READERS-1) := (others => DEFAULT_WRITER_CONFIG); + begin + -- arpkriu + ret(0).TIME_BASED_FILTER_QOS := gen_duration(2 sec); + ret(0).DEADLINE_QOS := DURATION_INFINITE; + ret(0).MAX_SAMPLES := std_logic_vector(to_unsigned(4,CDR_LONG_WIDTH)); + ret(0).MAX_INSTANCES := std_logic_vector(to_unsigned(3,CDR_LONG_WIDTH)); + ret(0).MAX_SAMPLES_PER_INSTANCE := std_logic_vector(to_unsigned(2,CDR_LONG_WIDTH)); + ret(0).HISTORY_QOS := KEEP_ALL_HISTORY_QOS; + ret(0).RELIABILITY_QOS := RELIABLE_RELIABILITY_QOS; + ret(0).PRESENTATION_QOS := INSTANCE_PRESENTATION_QOS; + ret(0).DESTINATION_ORDER_QOS := BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS; + ret(0).COHERENT_ACCESS := FALSE; + ret(0).ORDERED_ACCESS := FALSE; + ret(0).WITH_KEY := TRUE; + ret(0).MAX_PAYLOAD_SIZE := 40; + -- arpkriu + ret(1).TIME_BASED_FILTER_QOS := gen_duration(1 sec); + ret(1).DEADLINE_QOS := DURATION_INFINITE; + ret(1).MAX_SAMPLES := std_logic_vector(to_unsigned(4,CDR_LONG_WIDTH)); + ret(1).MAX_INSTANCES := std_logic_vector(to_unsigned(3,CDR_LONG_WIDTH)); + ret(1).MAX_SAMPLES_PER_INSTANCE := std_logic_vector(to_unsigned(2,CDR_LONG_WIDTH)); + ret(1).HISTORY_QOS := KEEP_ALL_HISTORY_QOS; + ret(1).RELIABILITY_QOS := RELIABLE_RELIABILITY_QOS; + ret(1).PRESENTATION_QOS := INSTANCE_PRESENTATION_QOS; + ret(1).DESTINATION_ORDER_QOS := BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS; + ret(1).COHERENT_ACCESS := FALSE; + ret(1).ORDERED_ACCESS := FALSE; + ret(1).WITH_KEY := TRUE; + ret(1).MAX_PAYLOAD_SIZE := 40; + return ret; + end function; + constant TEST_CONFIG : CONFIG_ARRAY_TYPE := gen_test_config; + + -- *TYPE DECLARATION* + type DDS_STAGE_TYPE is (IDLE, START, DONE, CHECK_SI, CHECK_DATA, WAIT_EOC); + type RTPS_STAGE_TYPE is (IDLE, START, PUSH, DONE); + type EMPTY_HEAD_SIG_ARRAY_TYPE is array (0 to NUM_READERS-1) of natural; + type DDS_READER_MEM_ARRAY_TYPE is array (0 to NUM_READERS-1) of DDS_READER_MEM_TYPE; + + -- *SIGNAL DECLARATION* + signal clk : std_logic := '0'; + signal reset : std_logic := '1'; + signal check_time : TIME_TYPE := TIME_ZERO; + signal start_rtps, start_dds, ack_rtps, ack_dds, done_rtps, done_dds : std_logic_vector(0 to NUM_READERS-1) := (others => '0'); + signal opcode_rtps : HISTORY_CACHE_OPCODE_ARRAY_TYPE(0 to NUM_READERS-1) := (others => NOP); + signal opcode_dds : DDS_READER_OPCODE_ARRAY_TYPE(0 to NUM_READERS-1) := (others => NOP); + signal ret_rtps : HISTORY_CACHE_RESPONSE_ARRAY_TYPE(0 to NUM_READERS-1) := (others => ERROR); + signal ready_in_rtps, valid_in_rtps, last_word_in_rtps : std_logic_vector(0 to NUM_READERS-1) := (others => '0'); + signal ready_out_dds, valid_out_dds, last_word_out_dds : std_logic_vector(0 to NUM_READERS-1) := (others => '0'); + signal data_in_rtps, data_out_dds : WORD_ARRAY_TYPE(0 to NUM_READERS-1) := (others => (others => '0')); + signal get_data_dds, si_valid, eoc : std_logic_vector(0 to NUM_READERS-1) := (others => '0'); + signal return_code_dds : RETURN_CODE_ARRAY_TYPE(0 to NUM_READERS-1) := (others => (others => '0')); + signal status : STATUS_KIND_ARRAY_TYPE(0 to NUM_READERS-1) := (others => (others => '0')); + signal instance_state_dds : INSTANCE_STATE_ARRAY_TYPE(0 to NUM_READERS-1) := (others => ANY_INSTANCE_STATE); + signal view_state_dds : VIEW_STATE_ARRAY_TYPE(0 to NUM_READERS-1) := (others => ANY_VIEW_STATE); + signal sample_state_dds : SAMPLE_STATE_ARRAY_TYPE(0 to NUM_READERS-1) := (others => ANY_SAMPLE_STATE); + signal instance_handle_dds : INSTANCE_HANDLE_ARRAY_TYPE(0 to NUM_READERS-1) := (others => HANDLE_NIL); + signal max_samples_dds : MAX_SAMPLES_ARRAY_TYPE(0 to NUM_READERS-1) := (others => (others => '0')); + signal sample_info : SAMPLE_INFO_ARRAY_TYPE(0 to NUM_READERS-1); + + signal ind : natural := 0; + signal dds_start , dds_done , rtps_start, rtps_done : std_logic := '0'; + signal dds_cnt, dds_cnt2, rtps_cnt : natural := 0; + signal dds_stage : DDS_STAGE_TYPE := IDLE; + signal rtps_stage : RTPS_STAGE_TYPE := IDLE; + shared variable dds : DDS_READER_TEST_TYPE := DEFAULT_DDS_READER_TEST; + shared variable rtps : RTPS_READER_TEST_TYPE := DEFAULT_RTPS_READER_TEST; + shared variable mem : DDS_READER_MEM_ARRAY_TYPE := (others => DEFAULT_DDS_READER_MEM); + signal data_id, ret_id, sstate_id, vstate_id, istate_id, inst_id, ts_id, pub_id, dis_gen_cnt_id, no_w_gen_cnt_id, srank_id, grank_id, agrank_id, eoc_id, valid_id : AlertLogIDType; + + -- *FUNCTION DECLARATION* + function extract_key_hash (payload : TEST_PACKET_TYPE) return INSTANCE_HANDLE_TYPE is + variable ret : INSTANCE_HANDLE_TYPE := HANDLE_NIL; + begin + for i in 0 to 3 loop + ret(i) := not payload.data(i); + end loop; + + return ret; + end function; + + function gen_sn(input : natural) return SEQUENCENUMBER_TYPE is + variable ret : SEQUENCENUMBER_TYPE; + begin + ret(0) := (others => '0'); + ret(1) := unsigned(int(input, WORD_WIDTH)); + return ret; + end function; + + procedure wait_on_sig(signal sig : std_logic) is + begin + if (sig /= '1') then + wait on sig until sig = '1'; + end if; + end procedure; + +begin + + -- Unit Under Test + uut : entity work.dds_reader(arch) + generic map ( + NUM_READERS => NUM_READERS, + CONFIG_ARRAY => to_QUARTUS_CONFIG_ARRAY_TYPE(TEST_CONFIG), + MAX_REMOTE_ENDPOINTS => MAX_REMOTE_ENDPOINTS + ) + port map ( + clk => clk, + reset => reset, + time => check_time, + start_rtps => start_rtps, + opcode_rtps => opcode_rtps, + ack_rtps => ack_rtps, + done_rtps => done_rtps, + ret_rtps => ret_rtps, + data_in_rtps => data_in_rtps, + valid_in_rtps => valid_in_rtps, + ready_in_rtps => ready_in_rtps, + last_word_in_rtps => last_word_in_rtps, + start_dds => start_dds, + ack_dds => ack_dds, + opcode_dds => opcode_dds, + instance_state_dds => instance_state_dds, + view_state_dds => view_state_dds, + sample_state_dds => sample_state_dds, + instance_handle_dds => instance_handle_dds, + max_samples_dds => max_samples_dds, + get_data_dds => get_data_dds, + done_dds => done_dds, + return_code_dds => return_code_dds, + ready_out_dds => ready_out_dds, + valid_out_dds => valid_out_dds, + data_out_dds => data_out_dds, + last_word_out_dds => last_word_out_dds, + sample_info => sample_info, + sample_info_valid => si_valid, + sample_info_ack => (others => '1'), + eoc => eoc, + status => status + ); + + stimulus_prc : process + variable RV : RandomPType; + variable cc : CACHE_CHANGE_TYPE := DEFAULT_CACHE_CHANGE; + variable s : SAMPLE_TYPE := DEFAULT_SAMPLE; + variable kh1, kh2, kh3, kh4, kh5 : INSTANCE_HANDLE_TYPE := HANDLE_NIL; + + alias idle_sig is <>; + alias inst_op_done is <>; + alias empty_inst_head is <>; + alias empty_sample_head is <>; + alias empty_payload_head is <>; + + impure function gen_payload(key_hash : INSTANCE_HANDLE_TYPE; len : natural) return TEST_PACKET_TYPE is + variable ret : TEST_PACKET_TYPE := EMPTY_TEST_PACKET; + begin + assert (len >= 4) report "Payload length has to be at least 16 Bytes long" severity FAILURE; + + for i in 0 to len-1 loop + if (i < 4) then + -- NOTE: Beginning of payload is negated key to allow deterministic Key Hash generation from the kh_prc + ret.data(ret.length) := not key_hash(i); + else + ret.data(ret.length) := RV.RandSlv(WORD_WIDTH); + end if; + ret.length := ret.length + 1; + end loop; + ret.last(ret.length-1) := '1'; + + return ret; + end function; + + impure function gen_key_hash return KEY_HASH_TYPE is + variable ret : KEY_HASH_TYPE := KEY_HASH_NIL; + begin + for i in 0 to KEY_HASH_TYPE'length-1 loop + ret(i) := RV.RandSlv(WORD_WIDTH); + end loop; + return ret; + end function; + + procedure start_dds is + begin + dds_start <= '1'; + wait until rising_edge(clk); + dds_start <= '0'; + wait until rising_edge(clk); + end procedure; + + procedure start_rtps is + begin + rtps_start <= '1'; + wait until rising_edge(clk); + rtps_start <= '0'; + wait until rising_edge(clk); + end procedure; + + procedure wait_on_completion is + begin + if (rtps_done /= '1' or dds_done /= '1') then + wait until rtps_done = '1' and dds_done = '1'; + end if; + end procedure; + + -- NOTE: This procedure waits until the idle_sig is high for at least + -- two consecutive clock cycles. + procedure wait_on_idle is + variable first : boolean := TRUE; + begin + loop + if (idle_sig /= '1') then + wait until idle_sig = '1'; + elsif (not first) then + exit; + end if; + wait until rising_edge(clk); + wait until rising_edge(clk); + first := FALSE; + end loop; + wait_on_sig(inst_op_done); + end procedure; + + begin + + SetAlertLogName("L0_dds_reader_test2 - TIME_BASED_FILTER QoS Handling"); + SetAlertEnable(FAILURE, TRUE); + SetAlertEnable(ERROR, TRUE); + SetAlertEnable(WARNING, TRUE); + SetLogEnable(DEBUG, FALSE); + SetLogEnable(PASSED, FALSE); + SetLogEnable(INFO, TRUE); + RV.InitSeed(RV'instance_name); + sstate_id <= GetAlertLogID("Sample State", ALERTLOG_BASE_ID); + vstate_id <= GetAlertLogID("View State", ALERTLOG_BASE_ID); + istate_id <= GetAlertLogID("Instance State", ALERTLOG_BASE_ID); + ts_id <= GetAlertLogID("Source Timestamp", ALERTLOG_BASE_ID); + inst_id <= GetAlertLogID("Instance Handle", ALERTLOG_BASE_ID); + pub_id <= GetAlertLogID("Publication Hanlde", ALERTLOG_BASE_ID); + dis_gen_cnt_id <= GetAlertLogID("Disposed Generation Count", ALERTLOG_BASE_ID); + no_w_gen_cnt_id <= GetAlertLogID("No Writers Generation Count", ALERTLOG_BASE_ID); + srank_id <= GetAlertLogID("Sample Rank", ALERTLOG_BASE_ID); + grank_id <= GetAlertLogID("Generation Rank", ALERTLOG_BASE_ID); + agrank_id <= GetAlertLogID("Absolute Generation Rank", ALERTLOG_BASE_ID); + eoc_id <= GetAlertLogID("End Of Collection", ALERTLOG_BASE_ID); + valid_id <= GetAlertLogID("Valid Data", ALERTLOG_BASE_ID); + data_id <= GetAlertLogID("Data Out", ALERTLOG_BASE_ID); + ret_id <= GetAlertLogID("Return Code", ALERTLOG_BASE_ID); + + -- Key Hashes + kh3 := (x"0CEAB0C6", x"FA04B9AD", x"A96EB495", x"4E0EB999"); + kh4 := (x"A7EB605C", x"FF4BEF3A", x"3C5E8724", x"CCA0CA67"); + kh2 := (x"BC070AC4", x"0BAB5811", x"14EA8D61", x"F669189B"); + kh1 := (x"F12C31DA", x"E3FE0F3F", x"01F36685", x"446518CA"); + + + Log("Initiating Test", INFO); + Log("Current Time: 0s", INFO); + check_time <= TIME_ZERO; + reset <= '1'; + wait until rising_edge(clk); + wait until rising_edge(clk); + reset <= '0'; + wait_on_idle; + -- READER 0 + AlertIf(empty_sample_head(0) /= 0, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 0, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 0, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: -/0,11,22,33,44 + -- PAYLOAD MEMORY: -/0,11,22,33,44 + -- INSTANCE MEMORY: -/0,13,26 + -- ISTATE: - + -- WRITER: - + -- READER 1 + AlertIf(empty_sample_head(1) /= 0, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(1) /= 0, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(1) /= 0, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: -/0,11,22,33,44 + -- PAYLOAD MEMORY: -/0,11,22,33,44 + -- INSTANCE MEMORY: -/0,13,26 + -- ISTATE: - + -- WRITER: - + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh1; + cc.payload := gen_payload(kh1,10); + + Log("R0,R1: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Aligned Payload] (ACCEPTED)", INFO); + Log("R0,R1: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 0; + rtps.ret_code := OK; + s := to_sample(cc,ALIVE_INSTANCE_STATE); + add_sample(s,mem(0), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(1), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + -- READER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- READER 1 + ind <= 1; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 0 + AlertIf(empty_sample_head(0) /= 11, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 11, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 13, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I1S1)/11,22,33,44 + -- PAYLOAD MEMORY: 0(I1S1)/11,22,33,44 + -- INSTANCE MEMORY: 0(I1)/13,26 + -- ISTATE: I1:ALIVE + -- WRITER: W0:I1 + -- READER 1 + AlertIf(empty_sample_head(1) /= 11, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(1) /= 11, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(1) /= 13, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I1S1)/11,22,33,44 + -- PAYLOAD MEMORY: 0(I1S1)/11,22,33,44 + -- INSTANCE MEMORY: 0(I1)/13,26 + -- ISTATE: I1:ALIVE + -- WRITER: W0:I1 + + Log("Current Time: 1s", INFO); + check_time <= gen_duration(1 sec); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait_on_idle; + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh1; + cc.payload := gen_payload(kh1,10); + + Log("R0,R1: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Aligned Payload]", INFO); + Log("R0: DROPPED [Time Based Filter]", DEBUG); + Log("R0: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 0; + rtps.ret_code := OK; + s := to_sample(cc,ALIVE_INSTANCE_STATE); + add_sample(s,mem(1), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + -- READER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- READER 1 + ind <= 1; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 0 + AlertIf(empty_sample_head(0) /= 11, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 11, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 13, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I1S1)/11,22,33,44 + -- PAYLOAD MEMORY: 0(I1S1)/11,22,33,44 + -- INSTANCE MEMORY: 0(I1)/13,26 + -- ISTATE: I1:ALIVE + -- WRITER: W0:I1 + -- READER 1 + AlertIf(empty_sample_head(1) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(1) /= 22, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(1) /= 13, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I1S1),11(I1S2)/22,33,44 + -- PAYLOAD MEMORY: 0(I1S1),11(I1S2)/22,33,44 + -- INSTANCE MEMORY: 0(I1)/13,26 + -- ISTATE: I1:ALIVE + -- WRITER: W0:I1 + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh2; + cc.payload := gen_payload(kh2,10); + + Log("R0,R1: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 2, Writer 1, Aligned Payload]", INFO); + Log("R0,R1: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 1; + rtps.ret_code := OK; + s := to_sample(cc,ALIVE_INSTANCE_STATE); + add_sample(s,mem(0), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(1), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + -- READER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- READER 1 + ind <= 1; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 0 + AlertIf(empty_sample_head(0) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 22, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I1S1),11(I2S1)/22,33,44 + -- PAYLOAD MEMORY: 0(I1S1),11(I2S1)/22,33,44 + -- INSTANCE MEMORY: 0(I1),13(I2)/26 + -- ISTATE: I1:ALIVE, I2:ALIVE + -- WRITER: W0:I1, W1:I2 + -- READER 1 + AlertIf(empty_sample_head(1) /= 33, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(1) /= 33, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(1) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I1S1),11(I1S2),22(I2S1)/33,44 + -- PAYLOAD MEMORY: 0(I1S1),11(I1S2),22(I2S1)/33,44 + -- INSTANCE MEMORY: 0(I1),13(I2)/26 + -- ISTATE: I1:ALIVE, I2:ALIVE + -- WRITER: W0:I1, W1:I2 + + Log("Current Time: 2s", INFO); + check_time <= gen_duration(2 sec); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait_on_idle; + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh2; + cc.payload := gen_payload(kh2,10); + + Log("R0,R1: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 2, Writer 0, Aligned Payload]", INFO); + Log("R0: DROPPED [Time Based Filter]", DEBUG); + Log("R1: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 1; + rtps.ret_code := OK; + s := to_sample(cc,ALIVE_INSTANCE_STATE); + add_sample(s,mem(1), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + -- READER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- READER 1 + ind <= 1; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 0 + AlertIf(empty_sample_head(0) /= 22, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 22, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I1S1),11(I2S1)/22,33,44 + -- PAYLOAD MEMORY: 0(I1S1),11(I2S1)/22,33,44 + -- INSTANCE MEMORY: 0(I1),13(I2)/26 + -- ISTATE: I1:ALIVE, I2:ALIVE + -- WRITER: W0:I1, W1:I2 + -- READER 1 + AlertIf(empty_sample_head(1) /= 44, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(1) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(1) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I1S1),11(I1S2),22(I2S1),33(I2S2)/44 + -- PAYLOAD MEMORY: 0(I1S1),11(I1S2),22(I2S1),33(I2S2)/44 + -- INSTANCE MEMORY: 0(I1),13(I2)/26 + -- ISTATE: I1:ALIVE, I2:ALIVE + -- WRITER: W0:I1, W1:I2 + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh1; + cc.payload := gen_payload(kh1,10); + + Log("R0,R1: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Aligned Payload]", INFO); + Log("R0: ACCEPTED", DEBUG); + Log("R1: REJECTED [MAX_SAMPLES_PER_INSTANCE/MAX_SAMPLES exceeded]", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 0; + -- READER 0 + rtps.ret_code := OK; + s := to_sample(cc,ALIVE_INSTANCE_STATE); + add_sample(s,mem(0), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- READER 1 + rtps.ret_code := REJECTED; + ind <= 1; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- READER 0 + AlertIf(empty_sample_head(0) /= 33, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 33, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I1S1),11(I2S1),22(I1S2)/33,44 + -- PAYLOAD MEMORY: 0(I1S1),11(I2S1),22(I1S2)/33,44 + -- INSTANCE MEMORY: 0(I1),13(I2)/26 + -- ISTATE: I1:ALIVE, I2:ALIVE + -- WRITER: W0:I1, W1:I2 + -- READER 1 + AlertIf(empty_sample_head(1) /= 44, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(1) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(1) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I1S1),11(I1S2),22(I2S1),33(I2S2)/44 + -- PAYLOAD MEMORY: 0(I1S1),11(I1S2),22(I2S1),33(I2S2)/44 + -- INSTANCE MEMORY: 0(I1),13(I2)/26 + -- ISTATE: I1:ALIVE, I2:ALIVE + -- WRITER: W0:I1, W1:I2 + + -- VAILDATE STATE + + Log("R0,R1: DDS Operation READ [MAX_SAMPLES 4, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := READ; + dds.max_samples := 4; + dds.sstate := ANY_SAMPLE_STATE; + dds.istate := ANY_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + -- READER 0 + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- READER 1 + ind <= 1; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- READER 0 + AlertIf(empty_sample_head(0) /= 33, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(0) /= 33, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(0) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I1S1),11(I2S1),22(I1S2)/33,44 + -- PAYLOAD MEMORY: 0(I1S1),11(I2S1),22(I1S2)/33,44 + -- INSTANCE MEMORY: 0(I1),13(I2)/26 + -- ISTATE: I1:ALIVE, I2:ALIVE + -- WRITER: W0:I1, W1:I2 + -- READER 1 + AlertIf(empty_sample_head(1) /= 44, "Sample Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_payload_head(1) /= 44, "Payload Memory Empty List Head incorrect", FAILURE); + AlertIf(empty_inst_head(1) /= 26, "Instance Memory Empty List Head incorrect", FAILURE); + -- SAMPLE MEMORY: 0(I1S1),11(I1S2),22(I2S1),33(I2S2)/44 + -- PAYLOAD MEMORY: 0(I1S1),11(I1S2),22(I2S1),33(I2S2)/44 + -- INSTANCE MEMORY: 0(I1),13(I2)/26 + -- ISTATE: I1:ALIVE, I2:ALIVE + -- WRITER: W0:I1, W1:I2 + + wait_on_completion; + TranscriptOpen(RESULTS_FILE, APPEND_MODE); + SetTranscriptMirror; + ReportAlerts; + TranscriptClose; + std.env.stop; + wait; + end process; + + clock_prc : process + begin + clk <= '0'; + wait for 25 ns; + clk <= '1'; + wait for 25 ns; + end process; + + dds_prc : process(all) + variable col : COLLECTION_TYPE := DEFAULT_COLLECTION; + begin + if rising_edge(clk) then + dds_done <= '0'; + case (dds_stage ) is + when IDLE => + if (dds_start = '1') then + dds_stage <= START; + else + dds_done <= '1'; + end if; + when START => + if (ack_dds(ind) = '1') then + dds_stage <= DONE; + dds_cnt <= 0; + end if; + when DONE => + if (done_dds(ind) = '1') then + AffirmIfEqual(ret_id, return_code_dds(ind), dds.ret_code); + case (dds.ret_code) is + when RETCODE_OK => + gen_collection(mem(ind), col, dds, TEST_CONFIG(ind).PRESENTATION_QOS, TEST_CONFIG(ind).ORDERED_ACCESS); + dds_stage <= CHECK_SI; + dds_cnt <= 0; + when others => + dds_stage <= IDLE; + end case; + end if; + when CHECK_SI => + if (si_valid(ind) = '1') then + AffirmIfEqual(sstate_id, sample_info(ind).sample_state, col.s(dds_cnt).sstate); + AffirmIfEqual(vstate_id, sample_info(ind).view_state, col.s(dds_cnt).vstate); + AffirmIfEqual(istate_id, sample_info(ind).instance_state, col.s(dds_cnt).istate); + AffirmIfEqual(ts_id, to_unsigned(sample_info(ind).source_timestamp), to_unsigned(col.s(dds_cnt).ts)); + AffirmIfEqual(inst_id, to_unsigned(sample_info(ind).instance_handle), to_unsigned(col.s(dds_cnt).inst)); + AffirmIfEqual(pub_id, to_unsigned(sample_info(ind).publication_handle), to_unsigned(HANDLE_NIL)); + AffirmIfEqual(dis_gen_cnt_id, sample_info(ind).disposed_generation_count, std_logic_vector(to_unsigned(col.s(dds_cnt).dis_gen_cnt,WORD_WIDTH))); + AffirmIfEqual(no_w_gen_cnt_id, sample_info(ind).no_writers_generation_count, std_logic_vector(to_unsigned(col.s(dds_cnt).no_w_gen_cnt,WORD_WIDTH))); + AffirmIfEqual(srank_id, sample_info(ind).sample_rank, std_logic_vector(to_unsigned(col.s(dds_cnt).srank,WORD_WIDTH))); + AffirmIfEqual(grank_id, sample_info(ind).generation_rank, std_logic_vector(to_unsigned(col.s(dds_cnt).grank,WORD_WIDTH))); + AffirmIfEqual(agrank_id, sample_info(ind).absolute_generation_rank, std_logic_vector(to_unsigned(col.s(dds_cnt).agrank,WORD_WIDTH))); + if (sample_info(ind).valid_data = '1') then + AffirmIf(valid_id, col.s(dds_cnt).data /= EMPTY_TEST_PACKET, "Sample with Data not expected"); + dds_stage <= CHECK_DATA; + dds_cnt2 <= 0; + else + AffirmIf(valid_id, col.s(dds_cnt).data = EMPTY_TEST_PACKET, "Sample with Data expected"); + if (dds_cnt = col.len-1) then + -- DONE + dds_stage <= WAIT_EOC; + else + dds_cnt <= dds_cnt + 1; + end if; + end if; + end if; + AffirmIf(eoc_id, eoc(ind) = '0', "EOC pulled high"); + when CHECK_DATA => + if (valid_out_dds(ind) = '1') then + AffirmIfEqual(data_id, data_out_dds(ind), col.s(dds_cnt).data.data(dds_cnt2)); + dds_cnt2 <= dds_cnt2 + 1; + if (dds_cnt2 = col.s(dds_cnt).data.length-1) then + AlertIf(data_id, last_word_out_dds(ind) /= '1', "Last Word Signal not pulled High", ERROR); + if (dds_cnt = col.len-1) then + -- DONE + dds_stage <= WAIT_EOC; + else + dds_stage <= CHECK_SI; + dds_cnt <= dds_cnt + 1; + end if; + end if; + end if; + when WAIT_EOC => + if (eoc(ind) = '1') then + dds_stage <= IDLE; + end if; + end case; + end if; + + -- DEFAULT + start_dds <= (others => '0'); + opcode_dds <= (others => NOP); + instance_state_dds <= (others => ANY_INSTANCE_STATE); + view_state_dds <= (others => ANY_VIEW_STATE); + sample_state_dds <= (others => ANY_SAMPLE_STATE); + instance_handle_dds <= (others => HANDLE_NIL); + max_samples_dds <= (others => (others => '0')); + get_data_dds <= (others => '0'); + ready_out_dds <= (others => '0'); + + + case (dds_stage ) is + when START => + start_dds(ind) <= '1'; + opcode_dds(ind) <= dds.opcode; + instance_state_dds(ind) <= dds.istate; + view_state_dds(ind) <= dds.vstate; + sample_state_dds(ind) <= dds.sstate; + instance_handle_dds(ind) <= dds.inst; + max_samples_dds(ind) <= std_logic_vector(to_unsigned(dds.max_samples, WORD_WIDTH)); + when CHECK_SI => + if (si_valid(ind) = '1' and sample_info(ind).valid_data = '1') then + get_data_dds(ind) <= '1'; + end if; + when CHECK_DATA => + ready_out_dds(ind) <= '1'; + when others => + null; + end case; + end process; + + rtps_prc : process(all) + variable stimulus : TEST_PACKET_TYPE := EMPTY_TEST_PACKET; + begin + if rising_edge(clk) then + rtps_done <= '0'; + case (rtps_stage) is + when IDLE => + if (rtps_start = '1') then + rtps_stage <= START; + else + rtps_done <= '1'; + end if; + when START => + if (ack_rtps(ind) = '1') then + case (rtps.opcode) is + when ADD_CACHE_CHANGE => + gen_add_cache_change_dds(rtps.cc, rtps.lifespan, rtps.writer_pos, stimulus); + rtps_stage <= PUSH; + when others => + rtps_stage <= DONE; + end case; + end if; + when PUSH => + if (ready_in_rtps(ind) = '1') then + rtps_cnt <= rtps_cnt + 1; + if (rtps_cnt = stimulus.length-1) then + rtps_stage <= DONE; + end if; + end if; + when DONE => + if (done_rtps(ind) = '1') then + AffirmIfEqual(ret_id, HISTORY_CACHE_RESPONSE_TYPE'pos(ret_rtps(ind)), HISTORY_CACHE_RESPONSE_TYPE'pos(rtps.ret_code)); + rtps_stage <= IDLE; + end if; + end case; + end if; + + -- DEFAULT + start_rtps <= (others => '0'); + opcode_rtps <= (others => NOP); + valid_in_rtps <= (others => '0'); + last_word_in_rtps <= (others => '0'); + data_in_rtps <= (others => (others => '0')); + + case (rtps_stage) is + when START => + start_rtps(ind) <= '1'; + opcode_rtps(ind) <= rtps.opcode; + case (rtps.opcode) is + when REMOVE_WRITER => + data_in_rtps(ind) <= std_logic_vector(to_unsigned(rtps.writer_pos,WORD_WIDTH)); + when others => + null; + end case; + when PUSH => + valid_in_rtps(ind) <= '1'; + data_in_rtps(ind) <= stimulus.data(rtps_cnt); + last_word_in_rtps(ind) <= stimulus.last(rtps_cnt); + when others => + null; + end case; + end process; + + watchdog : process + begin + wait for 1 ms; + Alert("Test timeout", FAILURE); + std.env.stop; + end process; + +end architecture; \ No newline at end of file diff --git a/src/Tests/Level_0/L0_dds_reader_test3.vhd b/src/Tests/Level_0/L0_dds_reader_test3.vhd new file mode 100644 index 0000000..c6792af --- /dev/null +++ b/src/Tests/Level_0/L0_dds_reader_test3.vhd @@ -0,0 +1,4026 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library osvvm; -- Utility Library +context osvvm.OsvvmContext; + +use work.rtps_package.all; +use work.user_config.all; +use work.rtps_config_package.all; +use work.rtps_test_package.all; + +-- This testbench tests the DDS handling of the DDS Reader. It tests the correctness of the DDS READ, TAKE, READ_NEXT_SAMPLE, TAKE_NEXT_SAMPLE, +-- READ_INSTANCE, TAKE_INSTANCE, READ_NEXT_INSTANCE, TAKE_NEXT_INSTANCE Operations. +-- More specifically the testbench covers following tests: +-- TEST: READ [NO COMPATIBLE SAMPLES] +-- TEST: READ [NO SAMPLES] +-- TEST: READ [MAX_SAMPLES < SAMPLES] +-- TEST: READ [MAX_SAMPLES > SAMPLES] +-- TEST: TAKE [NO SAMPLES] +-- TEST: TAKE +-- TEST: READ [ANY SSTATE, ANY ISTATE, ANY VIEW] +-- TEST: READ [ANY SSTATE, ANY ISTATE, SPECIFIED VIEW] +-- TEST: READ [ANY SSTATE, SPECIFIED ISTATE, ANY VIEW] +-- TEST: READ [ANY SSTATE, SPECIFIED ISTATE, SPECIFIED VIEW] +-- TEST: READ [SPECIFIED SSTATE, ANY ISTATE, ANY VIEW] +-- TEST: READ [SPECIFIED SSTATE, ANY ISTATE, SPECIFIED VIEW] +-- TEST: READ [SPECIFIED SSTATE, SPECIFIED ISTATE, ANY VIEW] +-- TEST: READ [SPECIFIED SSTATE, SPECIFIED ISTATE, SPECIFIED VIEW] +-- TEST: READ_NEXT_SAMPLE [WITH UNREAD SAMPLE] +-- TEST: READ_NEXT_SAMPLE [WITHOUT UNREAD SAMPLE] +-- TEST: READ_NEXT_SAMPLE [NO SAMPLE] +-- TEST: TAKE_NEXT_SAMPLE [NO SAMPLE] +-- TEST: TAKE_NEXT_SAMPLE +-- TEST: READ_INSTANCE [UNKNOWN INSTANCE] +-- TEST: READ_INSTANCE [KNOWN INSTANCE, UNCOMPATIBLE SAMPLES] +-- TEST: READ_INSTANCE [KNOWN INSTANCE, COMPATIBLE SAMPLES] +-- TEST: READ_INSTANCE [NO SAMPLES] +-- TEST: TAKE_INSTANCE [NO SAMPLES] +-- TEST: TAKE_INSTANCE +-- TEST: READ_NEXT_INSTANCE [WITH SAMPLES, WITHOUT NEXT INSTANCE] +-- TEST: READ_NEXT_INSTANCE [WITH NEXT INSTANCE, UNCOMPATIBLE SAMPLES] +-- TEST: READ_NEXT_INSTANCE [WITH NEXT INSTANCE, COMPATIBLE SAMPLES] +-- TEST: READ_NEXT_INSTANCE [HANDLE_NIL] +-- TEST: READ_NEXT_INSTANCE [WITH NEXT INSTANCE, WITH COMPATIBLE SAMPLE, NOT DIRECT NEXT INSTANCE] +-- TEST: READ_NEXT_INSTANCE [NO SAMPLE] +-- TEST: TAKE_NEXT_INSTANCE [NO SAMPLE] +-- TEST: TAKE_NEXT_INSTANCE +-- TEST: GET ALL DATA WITH READ_NEXT_INSTANCE +-- TEST: READ MARKS SAMPLES AS READ +-- TEST: TAKE REMOVES SAMPLE +-- TEST: READ MODIFIES VIEW STATE [READ PREVIOUS GENERATION] +-- TEST: READ MODIFIES VIEW STATE [READ CURRENT GENERATION] + +entity L0_dds_reader_test3 is +end entity; + + +architecture testbench of L0_dds_reader_test3 is + + -- *CONSTANT DECLARATION* + constant MAX_REMOTE_ENDPOINTS : natural := 3; + constant NUM_READERS : natural := 6; + + impure function gen_test_config return CONFIG_ARRAY_TYPE is + variable ret : CONFIG_ARRAY_TYPE(0 to NUM_READERS-1) := (others => DEFAULT_WRITER_CONFIG); + begin + -- arzkriu + ret(0).TIME_BASED_FILTER_QOS := DURATION_ZERO; + ret(0).DEADLINE_QOS := DURATION_INFINITE; + ret(0).MAX_SAMPLES := std_logic_vector(to_unsigned(15,CDR_LONG_WIDTH)); + ret(0).MAX_INSTANCES := std_logic_vector(to_unsigned(4,CDR_LONG_WIDTH)); + ret(0).MAX_SAMPLES_PER_INSTANCE := std_logic_vector(to_unsigned(15,CDR_LONG_WIDTH)); + ret(0).HISTORY_QOS := KEEP_ALL_HISTORY_QOS; + ret(0).RELIABILITY_QOS := RELIABLE_RELIABILITY_QOS; + ret(0).PRESENTATION_QOS := INSTANCE_PRESENTATION_QOS; + ret(0).DESTINATION_ORDER_QOS := BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS; + ret(0).COHERENT_ACCESS := FALSE; + ret(0).ORDERED_ACCESS := FALSE; + ret(0).WITH_KEY := TRUE; + ret(0).MAX_PAYLOAD_SIZE := 40; + -- arzkrio + ret(1).TIME_BASED_FILTER_QOS := DURATION_ZERO; + ret(1).DEADLINE_QOS := DURATION_INFINITE; + ret(1).MAX_SAMPLES := std_logic_vector(to_unsigned(15,CDR_LONG_WIDTH)); + ret(1).MAX_INSTANCES := std_logic_vector(to_unsigned(4,CDR_LONG_WIDTH)); + ret(1).MAX_SAMPLES_PER_INSTANCE := std_logic_vector(to_unsigned(15,CDR_LONG_WIDTH)); + ret(1).HISTORY_QOS := KEEP_ALL_HISTORY_QOS; + ret(1).RELIABILITY_QOS := RELIABLE_RELIABILITY_QOS; + ret(1).PRESENTATION_QOS := INSTANCE_PRESENTATION_QOS; + ret(1).DESTINATION_ORDER_QOS := BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS; + ret(1).COHERENT_ACCESS := FALSE; + ret(1).ORDERED_ACCESS := TRUE; + ret(1).WITH_KEY := TRUE; + ret(1).MAX_PAYLOAD_SIZE := 40; + -- arzkrtu + ret(2).TIME_BASED_FILTER_QOS := DURATION_ZERO; + ret(2).DEADLINE_QOS := DURATION_INFINITE; + ret(2).MAX_SAMPLES := std_logic_vector(to_unsigned(15,CDR_LONG_WIDTH)); + ret(2).MAX_INSTANCES := std_logic_vector(to_unsigned(4,CDR_LONG_WIDTH)); + ret(2).MAX_SAMPLES_PER_INSTANCE := std_logic_vector(to_unsigned(15,CDR_LONG_WIDTH)); + ret(2).HISTORY_QOS := KEEP_ALL_HISTORY_QOS; + ret(2).RELIABILITY_QOS := RELIABLE_RELIABILITY_QOS; + ret(2).PRESENTATION_QOS := TOPIC_PRESENTATION_QOS; + ret(2).DESTINATION_ORDER_QOS := BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS; + ret(2).COHERENT_ACCESS := FALSE; + ret(2).ORDERED_ACCESS := FALSE; + ret(2).WITH_KEY := TRUE; + ret(2).MAX_PAYLOAD_SIZE := 40; + -- arzkrto + ret(3).TIME_BASED_FILTER_QOS := DURATION_ZERO; + ret(3).DEADLINE_QOS := DURATION_INFINITE; + ret(3).MAX_SAMPLES := std_logic_vector(to_unsigned(15,CDR_LONG_WIDTH)); + ret(3).MAX_INSTANCES := std_logic_vector(to_unsigned(4,CDR_LONG_WIDTH)); + ret(3).MAX_SAMPLES_PER_INSTANCE := std_logic_vector(to_unsigned(15,CDR_LONG_WIDTH)); + ret(3).HISTORY_QOS := KEEP_ALL_HISTORY_QOS; + ret(3).RELIABILITY_QOS := RELIABLE_RELIABILITY_QOS; + ret(3).PRESENTATION_QOS := TOPIC_PRESENTATION_QOS; + ret(3).DESTINATION_ORDER_QOS := BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS; + ret(3).COHERENT_ACCESS := FALSE; + ret(3).ORDERED_ACCESS := TRUE; + ret(3).WITH_KEY := TRUE; + ret(3).MAX_PAYLOAD_SIZE := 40; + -- arznriu + ret(4).TIME_BASED_FILTER_QOS := DURATION_ZERO; + ret(4).DEADLINE_QOS := DURATION_INFINITE; + ret(4).MAX_SAMPLES := std_logic_vector(to_unsigned(15,CDR_LONG_WIDTH)); + ret(4).MAX_INSTANCES := std_logic_vector(to_unsigned(4,CDR_LONG_WIDTH)); + ret(4).MAX_SAMPLES_PER_INSTANCE := std_logic_vector(to_unsigned(15,CDR_LONG_WIDTH)); + ret(4).HISTORY_QOS := KEEP_ALL_HISTORY_QOS; + ret(4).RELIABILITY_QOS := RELIABLE_RELIABILITY_QOS; + ret(4).PRESENTATION_QOS := INSTANCE_PRESENTATION_QOS; + ret(4).DESTINATION_ORDER_QOS := BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS; + ret(4).COHERENT_ACCESS := FALSE; + ret(4).ORDERED_ACCESS := FALSE; + ret(4).WITH_KEY := FALSE; + ret(4).MAX_PAYLOAD_SIZE := 40; + -- arzksto + ret(5).TIME_BASED_FILTER_QOS := DURATION_ZERO; + ret(5).DEADLINE_QOS := DURATION_INFINITE; + ret(5).MAX_SAMPLES := std_logic_vector(to_unsigned(15,CDR_LONG_WIDTH)); + ret(5).MAX_INSTANCES := std_logic_vector(to_unsigned(4,CDR_LONG_WIDTH)); + ret(5).MAX_SAMPLES_PER_INSTANCE := std_logic_vector(to_unsigned(15,CDR_LONG_WIDTH)); + ret(5).HISTORY_QOS := KEEP_ALL_HISTORY_QOS; + ret(5).RELIABILITY_QOS := RELIABLE_RELIABILITY_QOS; + ret(5).PRESENTATION_QOS := TOPIC_PRESENTATION_QOS; + ret(5).DESTINATION_ORDER_QOS := BY_SOURCE_TIMESTAMP_DESTINATION_ORDER_QOS; + ret(5).COHERENT_ACCESS := FALSE; + ret(5).ORDERED_ACCESS := TRUE; + ret(5).WITH_KEY := TRUE; + ret(5).MAX_PAYLOAD_SIZE := 40; + return ret; + end function; + constant TEST_CONFIG : CONFIG_ARRAY_TYPE := gen_test_config; + + -- *TYPE DECLARATION* + type DDS_STAGE_TYPE is (IDLE, START, DONE, CHECK_SI, CHECK_DATA, WAIT_EOC); + type RTPS_STAGE_TYPE is (IDLE, START, PUSH, DONE); + type DDS_READER_MEM_ARRAY_TYPE is array (0 to NUM_READERS-1) of DDS_READER_MEM_TYPE; + + -- *SIGNAL DECLARATION* + signal clk : std_logic := '0'; + signal reset : std_logic := '1'; + signal check_time : TIME_TYPE := TIME_ZERO; + signal start_rtps, start_dds, ack_rtps, ack_dds, done_rtps, done_dds : std_logic_vector(0 to NUM_READERS-1) := (others => '0'); + signal opcode_rtps : HISTORY_CACHE_OPCODE_ARRAY_TYPE(0 to NUM_READERS-1) := (others => NOP); + signal opcode_dds : DDS_READER_OPCODE_ARRAY_TYPE(0 to NUM_READERS-1) := (others => NOP); + signal ret_rtps : HISTORY_CACHE_RESPONSE_ARRAY_TYPE(0 to NUM_READERS-1) := (others => ERROR); + signal ready_in_rtps, valid_in_rtps, last_word_in_rtps : std_logic_vector(0 to NUM_READERS-1) := (others => '0'); + signal ready_out_dds, valid_out_dds, last_word_out_dds : std_logic_vector(0 to NUM_READERS-1) := (others => '0'); + signal data_in_rtps, data_out_dds : WORD_ARRAY_TYPE(0 to NUM_READERS-1) := (others => (others => '0')); + signal get_data_dds, si_valid, eoc : std_logic_vector(0 to NUM_READERS-1) := (others => '0'); + signal return_code_dds : RETURN_CODE_ARRAY_TYPE(0 to NUM_READERS-1) := (others => (others => '0')); + signal status : STATUS_KIND_ARRAY_TYPE(0 to NUM_READERS-1) := (others => (others => '0')); + signal instance_state_dds : INSTANCE_STATE_ARRAY_TYPE(0 to NUM_READERS-1) := (others => ANY_INSTANCE_STATE); + signal view_state_dds : VIEW_STATE_ARRAY_TYPE(0 to NUM_READERS-1) := (others => ANY_VIEW_STATE); + signal sample_state_dds : SAMPLE_STATE_ARRAY_TYPE(0 to NUM_READERS-1) := (others => ANY_SAMPLE_STATE); + signal instance_handle_dds : INSTANCE_HANDLE_ARRAY_TYPE(0 to NUM_READERS-1) := (others => HANDLE_NIL); + signal max_samples_dds : MAX_SAMPLES_ARRAY_TYPE(0 to NUM_READERS-1) := (others => (others => '0')); + signal sample_info : SAMPLE_INFO_ARRAY_TYPE(0 to NUM_READERS-1); + + signal ind : natural := 0; + signal dds_start , dds_done , rtps_start, rtps_done : std_logic := '0'; + signal dds_cnt, dds_cnt2, rtps_cnt : natural := 0; + signal dds_stage : DDS_STAGE_TYPE := IDLE; + signal rtps_stage : RTPS_STAGE_TYPE := IDLE; + shared variable dds : DDS_READER_TEST_TYPE := DEFAULT_DDS_READER_TEST; + shared variable rtps : RTPS_READER_TEST_TYPE := DEFAULT_RTPS_READER_TEST; + shared variable mem : DDS_READER_MEM_ARRAY_TYPE := (others => DEFAULT_DDS_READER_MEM); + signal data_id, ret_id, sstate_id, vstate_id, istate_id, inst_id, ts_id, pub_id, dis_gen_cnt_id, no_w_gen_cnt_id, srank_id, grank_id, agrank_id, eoc_id, valid_id, status_id : AlertLogIDType; + + -- *FUNCTION DECLARATION* + function extract_key_hash (payload : TEST_PACKET_TYPE) return INSTANCE_HANDLE_TYPE is + variable ret : INSTANCE_HANDLE_TYPE := HANDLE_NIL; + begin + for i in 0 to 3 loop + ret(i) := not payload.data(i); + end loop; + + return ret; + end function; + + function gen_sn(input : natural) return SEQUENCENUMBER_TYPE is + variable ret : SEQUENCENUMBER_TYPE; + begin + ret(0) := (others => '0'); + ret(1) := unsigned(int(input, WORD_WIDTH)); + return ret; + end function; + + procedure wait_on_sig(signal sig : std_logic) is + begin + if (sig /= '1') then + wait on sig until sig = '1'; + end if; + end procedure; + +begin + + -- Unit Under Test + uut : entity work.dds_reader(arch) + generic map ( + NUM_READERS => NUM_READERS, + CONFIG_ARRAY => to_QUARTUS_CONFIG_ARRAY_TYPE(TEST_CONFIG), + MAX_REMOTE_ENDPOINTS => MAX_REMOTE_ENDPOINTS + ) + port map ( + clk => clk, + reset => reset, + time => check_time, + start_rtps => start_rtps, + opcode_rtps => opcode_rtps, + ack_rtps => ack_rtps, + done_rtps => done_rtps, + ret_rtps => ret_rtps, + data_in_rtps => data_in_rtps, + valid_in_rtps => valid_in_rtps, + ready_in_rtps => ready_in_rtps, + last_word_in_rtps => last_word_in_rtps, + start_dds => start_dds, + ack_dds => ack_dds, + opcode_dds => opcode_dds, + instance_state_dds => instance_state_dds, + view_state_dds => view_state_dds, + sample_state_dds => sample_state_dds, + instance_handle_dds => instance_handle_dds, + max_samples_dds => max_samples_dds, + get_data_dds => get_data_dds, + done_dds => done_dds, + return_code_dds => return_code_dds, + ready_out_dds => ready_out_dds, + valid_out_dds => valid_out_dds, + data_out_dds => data_out_dds, + last_word_out_dds => last_word_out_dds, + sample_info => sample_info, + sample_info_valid => si_valid, + sample_info_ack => (others => '1'), + eoc => eoc, + status => status + ); + + stimulus_prc : process + variable RV : RandomPType; + variable cc : CACHE_CHANGE_TYPE := DEFAULT_CACHE_CHANGE; + variable s : SAMPLE_TYPE := DEFAULT_SAMPLE; + variable kh1, kh2, kh3, kh4, kh5 : INSTANCE_HANDLE_TYPE := HANDLE_NIL; + + alias idle_sig is <>; + + impure function gen_payload(key_hash : INSTANCE_HANDLE_TYPE; len : natural) return TEST_PACKET_TYPE is + variable ret : TEST_PACKET_TYPE := EMPTY_TEST_PACKET; + begin + assert (len >= 4) report "Payload length has to be at least 16 Bytes long" severity FAILURE; + + for i in 0 to len-1 loop + if (i < 4) then + -- NOTE: Beginning of payload is negated key to allow deterministic Key Hash generation from the kh_prc + ret.data(ret.length) := not key_hash(i); + else + ret.data(ret.length) := RV.RandSlv(WORD_WIDTH); + end if; + ret.length := ret.length + 1; + end loop; + ret.last(ret.length-1) := '1'; + + return ret; + end function; + + impure function gen_key_hash return KEY_HASH_TYPE is + variable ret : KEY_HASH_TYPE := KEY_HASH_NIL; + begin + for i in 0 to KEY_HASH_TYPE'length-1 loop + ret(i) := RV.RandSlv(WORD_WIDTH); + end loop; + return ret; + end function; + + procedure start_dds is + begin + dds_start <= '1'; + wait until rising_edge(clk); + dds_start <= '0'; + wait until rising_edge(clk); + end procedure; + + procedure start_rtps is + begin + rtps_start <= '1'; + wait until rising_edge(clk); + rtps_start <= '0'; + wait until rising_edge(clk); + end procedure; + + procedure wait_on_completion is + begin + if (rtps_done /= '1' or dds_done /= '1') then + wait until rtps_done = '1' and dds_done = '1'; + end if; + end procedure; + + -- NOTE: This procedure waits until the idle_sig is high for at least + -- two consecutive clock cycles. + procedure wait_on_idle is + variable first : boolean := TRUE; + begin + loop + if (idle_sig /= '1') then + wait until idle_sig = '1'; + elsif (not first) then + exit; + end if; + wait until rising_edge(clk); + wait until rising_edge(clk); + first := FALSE; + end loop; + end procedure; + + begin + + SetAlertLogName("L0_dds_reader_test3 - DDS Handling"); + SetAlertEnable(FAILURE, TRUE); + SetAlertEnable(ERROR, TRUE); + SetAlertEnable(WARNING, TRUE); + SetLogEnable(DEBUG, TRUE); + SetLogEnable(PASSED, FALSE); + SetLogEnable(INFO, TRUE); + RV.InitSeed(RV'instance_name); + sstate_id <= GetAlertLogID("Sample State", ALERTLOG_BASE_ID); + vstate_id <= GetAlertLogID("View State", ALERTLOG_BASE_ID); + istate_id <= GetAlertLogID("Instance State", ALERTLOG_BASE_ID); + ts_id <= GetAlertLogID("Source Timestamp", ALERTLOG_BASE_ID); + inst_id <= GetAlertLogID("Instance Handle", ALERTLOG_BASE_ID); + pub_id <= GetAlertLogID("Publication Hanlde", ALERTLOG_BASE_ID); + dis_gen_cnt_id <= GetAlertLogID("Disposed Generation Count", ALERTLOG_BASE_ID); + no_w_gen_cnt_id <= GetAlertLogID("No Writers Generation Count", ALERTLOG_BASE_ID); + srank_id <= GetAlertLogID("Sample Rank", ALERTLOG_BASE_ID); + grank_id <= GetAlertLogID("Generation Rank", ALERTLOG_BASE_ID); + agrank_id <= GetAlertLogID("Absolute Generation Rank", ALERTLOG_BASE_ID); + eoc_id <= GetAlertLogID("End Of Collection", ALERTLOG_BASE_ID); + valid_id <= GetAlertLogID("Valid Data", ALERTLOG_BASE_ID); + data_id <= GetAlertLogID("Data Out", ALERTLOG_BASE_ID); + ret_id <= GetAlertLogID("Return Code", ALERTLOG_BASE_ID); + + -- Key Hashes + kh3 := (x"0CEAB0C6", x"FA04B9AD", x"A96EB495", x"4E0EB999"); + kh4 := (x"A7EB605C", x"FF4BEF3A", x"3C5E8724", x"CCA0CA67"); + kh2 := (x"BC070AC4", x"0BAB5811", x"14EA8D61", x"F669189B"); + kh1 := (x"F12C31DA", x"E3FE0F3F", x"01F36685", x"446518CA"); + kh5 := gen_key_hash; + + + Log("Initiating Test", INFO); + Log("Current Time: 0s", INFO); + check_time <= TIME_ZERO; + reset <= '1'; + wait until rising_edge(clk); + wait until rising_edge(clk); + reset <= '0'; + wait_on_idle; + + Log("*READER 0 / READER 1 / READER 2 / READER 3*", INFO); + -- MEM: - + -- ISTATE: - + -- VIEW: - + -- WRITER: - + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh1; + cc.payload := gen_payload(kh1,10); + cc.src_timestamp := gen_duration(0 sec); + + Log("R0,R1,R2,R3: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Aligned Payload, ID 0] (ACCEPTED)", INFO); + Log("R0,R1,R2,R3: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 0; + rtps.ret_code := OK; + s := to_sample(cc,ALIVE_INSTANCE_STATE); + add_sample(s,mem(0), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(1), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(2), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(3), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + -- READER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- READER 1 + ind <= 1; + start_rtps; + wait_on_sig(rtps_done); + -- READER 2 + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + -- READER 3 + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- MEM: I1S1(0) + -- ISTATE: I1:ALIVE + -- VIEW: I1:NEW + -- WRITER: W0:I1 + + Log("Current Time: 1s", INFO); + check_time <= gen_duration(1 sec); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait_on_idle; + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := TRUE; + cc.kind := NOT_ALIVE_DISPOSED; + cc.instance := kh1; + cc.payload := gen_payload(kh1,5); + cc.src_timestamp := gen_duration(1 sec); + + Log("R0,R1,R2,R3: RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Instance 1, Writer 0, ID 1]", INFO); + Log("R0,R1,R2,R3: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 0; + rtps.ret_code := OK; + s := to_sample(cc,NOT_ALIVE_DISPOSED_INSTANCE_STATE); + add_sample(s,mem(0), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(1), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(2), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(3), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + -- READER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- READER 1 + ind <= 1; + start_rtps; + wait_on_sig(rtps_done); + -- READER 2 + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + -- READER 3 + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- MEM: I1S1(0), I1S2-(1) + -- ISTATE: I1:DISPOSED + -- VIEW: I1:NEW + -- WRITER: W0:I1 + + Log("Current Time: 2s", INFO); + check_time <= gen_duration(2 sec); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait_on_idle; + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh2; + cc.payload := gen_payload(kh2,10); + cc.src_timestamp := gen_duration(2 sec); + + Log("R0,R1,R2,R3: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 2, Writer 1, Aligned Payload, ID 2]", INFO); + Log("R0,R1,R2,R3: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 1; + rtps.ret_code := OK; + s := to_sample(cc,ALIVE_INSTANCE_STATE); + add_sample(s,mem(0), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(1), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(2), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(3), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + -- READER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- READER 1 + ind <= 1; + start_rtps; + wait_on_sig(rtps_done); + -- READER 2 + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + -- READER 3 + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- MEM: I1S1(0), I1S2-(1), I2S1(2) + -- ISTATE: I1:DISPOSED, I2:ALIVE + -- VIEW: I1:NEW, I2:NEW + -- WRITER: W0:I1, W1:I2 + + Log("Current Time: 3s", INFO); + check_time <= gen_duration(3 sec); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait_on_idle; + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh3; + cc.payload := gen_payload(kh3,10); + cc.src_timestamp := gen_duration(3 sec); + + Log("R0,R1,R2,R3: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 3, Writer 2, Aligned Payload, ID 3]", INFO); + Log("R0,R1,R2,R3: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 2; + rtps.ret_code := OK; + s := to_sample(cc,ALIVE_INSTANCE_STATE); + add_sample(s,mem(0), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(1), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(2), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(3), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + -- READER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- READER 1 + ind <= 1; + start_rtps; + wait_on_sig(rtps_done); + -- READER 2 + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + -- READER 3 + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3) + -- ISTATE: I1:DISPOSED, I2:ALIVE, I3:ALIVE + -- VIEW: I1:NEW, I2:NEW, I3:NEW + -- WRITER: W0:I1, W1:I2, W2:I3 + + Log("Current Time: 4s", INFO); + check_time <= gen_duration(4 sec); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait_on_idle; + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh4; + cc.payload := gen_payload(kh4,10); + cc.src_timestamp := gen_duration(4 sec); + + Log("R0,R1,R2,R3: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 4, Writer 2, Aligned Payload, ID 4]", INFO); + Log("R0,R1,R2,R3: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 2; + rtps.ret_code := OK; + s := to_sample(cc,ALIVE_INSTANCE_STATE); + add_sample(s,mem(0), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(1), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(2), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(3), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + -- READER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- READER 1 + ind <= 1; + start_rtps; + wait_on_sig(rtps_done); + -- READER 2 + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + -- READER 3 + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), + -- ISTATE: I1:DISPOSED, I2:ALIVE, I3:ALIVE, I4:ALIVE + -- VIEW: I1:NEW, I2:NEW, I3:NEW, I4:NEW + -- WRITER: W0:I1, W1:I2, W2:I3,I4 + + Log("Current Time: 5s", INFO); + check_time <= gen_duration(5 sec); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait_on_idle; + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := TRUE; + cc.kind := NOT_ALIVE_DISPOSED; + cc.instance := kh2; + cc.payload := gen_payload(kh2,5); + cc.src_timestamp := gen_duration(5 sec); + + Log("R0,R1,R2,R3: RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Instance 2, Writer 1, ID 5]", INFO); + Log("R0,R1,R2,R3: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 1; + rtps.ret_code := OK; + s := to_sample(cc,NOT_ALIVE_DISPOSED_INSTANCE_STATE); + add_sample(s,mem(0), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(1), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(2), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(3), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + -- READER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- READER 1 + ind <= 1; + start_rtps; + wait_on_sig(rtps_done); + -- READER 2 + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + -- READER 3 + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5) + -- ISTATE: I1:DISPOSED, I2:DISPOSED, I3:ALIVE, I4:ALIVE + -- VIEW: I1:NEW, I2:NEW, I3:NEW, I4:NEW + -- WRITER: W0:I1, W1:I2, W2:I3,I4 + + Log("Current Time: 6s", INFO); + check_time <= gen_duration(6 sec); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait_on_idle; + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := TRUE; + cc.kind := NOT_ALIVE_DISPOSED; + cc.instance := kh3; + cc.payload := gen_payload(kh3,5); + cc.src_timestamp := gen_duration(6 sec); + + Log("R0,R1,R2,R3: RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Instance 3, Writer 2, ID 6]", INFO); + Log("R0,R1,R2,R3: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 2; + rtps.ret_code := OK; + s := to_sample(cc,NOT_ALIVE_DISPOSED_INSTANCE_STATE); + add_sample(s,mem(0), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(1), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(2), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(3), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + -- READER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- READER 1 + ind <= 1; + start_rtps; + wait_on_sig(rtps_done); + -- READER 2 + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + -- READER 3 + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6) + -- ISTATE: I1:DISPOSED, I2:DISPOSED, I3:DISPOSED, I4:ALIVE + -- VIEW: I1:NEW, I2:NEW, I3:NEW, I4:NEW + -- WRITER: W0:I1, W1:I2, W2:I3,I4 + + Log("Current Time: 7s", INFO); + check_time <= gen_duration(7 sec); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait_on_idle; + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := TRUE; + cc.kind := NOT_ALIVE_DISPOSED; + cc.instance := kh4; + cc.payload := gen_payload(kh4,5); + cc.src_timestamp := gen_duration(7 sec); + + Log("R0,R1,R2,R3: RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Instance 4, Writer 2, ID 7]", INFO); + Log("R0,R1,R2,R3: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 2; + rtps.ret_code := OK; + s := to_sample(cc,NOT_ALIVE_DISPOSED_INSTANCE_STATE); + add_sample(s,mem(0), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(1), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(2), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(3), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + -- READER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- READER 1 + ind <= 1; + start_rtps; + wait_on_sig(rtps_done); + -- READER 2 + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + -- READER 3 + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7) + -- ISTATE: I1:DISPOSED, I2:DISPOSED, I3:DISPOSED, I4:DISPOSED + -- VIEW: I1:NEW, I2:NEW, I3:NEW, I4:NEW + -- WRITER: W0:I1, W1:I2, W2:I3,I4 + + Log("Current Time: 8s", INFO); + check_time <= gen_duration(8 sec); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait_on_idle; + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh4; + cc.payload := gen_payload(kh4,10); + cc.src_timestamp := gen_duration(8 sec); + + Log("R0,R1,R2,R3: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 4, Writer 2, Aligned Payload, ID 8]", INFO); + Log("R0,R1,R2,R3: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 2; + rtps.ret_code := OK; + s := to_sample(cc,ALIVE_INSTANCE_STATE); + add_sample(s,mem(0), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(1), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(2), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(3), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + -- READER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- READER 1 + ind <= 1; + start_rtps; + wait_on_sig(rtps_done); + -- READER 2 + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + -- READER 3 + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8) + -- ISTATE: I1:DISPOSED, I2:DISPOSED, I3:DISPOSED, I4:ALIVE + -- VIEW: I1:NEW, I2:NEW, I3:NEW, I4:NEW + -- WRITER: W0:I1, W1:I2, W2:I3,I4 + + Log("Current Time: 9s", INFO); + check_time <= gen_duration(9 sec); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait_on_idle; + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh1; + cc.payload := gen_payload(kh1,10); + cc.src_timestamp := gen_duration(9 sec); + + Log("R0,R1,R2,R3: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Aligned Payload, ID 9]", INFO); + Log("R0,R1,R2,R3: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 0; + rtps.ret_code := OK; + s := to_sample(cc,ALIVE_INSTANCE_STATE); + add_sample(s,mem(0), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(1), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(2), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(3), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + -- READER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- READER 1 + ind <= 1; + start_rtps; + wait_on_sig(rtps_done); + -- READER 2 + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + -- READER 3 + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9) + -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE + -- VIEW: I1:NEW, I2:NEW, I3:NEW, I4:NEW + -- WRITER: W0:I1, W1:I2, W2:I3,I4 + + Log("Current Time: 10s", INFO); + check_time <= gen_duration(10 sec); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait_on_idle; + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh2; + cc.payload := gen_payload(kh2,10); + cc.src_timestamp := gen_duration(10 sec); + + Log("R0,R1,R2,R3: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 2, Writer 1, Aligned Payload, ID 10]", INFO); + Log("R0,R1,R2,R3: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 1; + rtps.ret_code := OK; + s := to_sample(cc,ALIVE_INSTANCE_STATE); + add_sample(s,mem(0), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(1), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(2), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(3), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + -- READER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- READER 1 + ind <= 1; + start_rtps; + wait_on_sig(rtps_done); + -- READER 2 + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + -- READER 3 + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10) + -- ISTATE: I1:ALIVE, I2:ALIVE, I3:DISPOSED, I4:ALIVE + -- VIEW: I1:NEW, I2:NEW, I3:NEW, I4:NEW + -- WRITER: W0:I1, W1:I2, W2:I3,I4 + + Log("Current Time: 11s", INFO); + check_time <= gen_duration(11 sec); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait_on_idle; + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := TRUE; + cc.kind := NOT_ALIVE_DISPOSED; + cc.instance := kh2; + cc.payload := gen_payload(kh2,5); + cc.src_timestamp := gen_duration(11 sec); + + Log("R0,R1,R2,R3: RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Instance 2, Writer 1, ID 11]", INFO); + Log("R0,R1,R2,R3: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 1; + rtps.ret_code := OK; + s := to_sample(cc,NOT_ALIVE_DISPOSED_INSTANCE_STATE); + add_sample(s,mem(0), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(1), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(2), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(3), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + -- READER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- READER 1 + ind <= 1; + start_rtps; + wait_on_sig(rtps_done); + -- READER 2 + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + -- READER 3 + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) + -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE + -- VIEW: I1:NEW, I2:NEW, I3:NEW, I4:NEW + -- WRITER: W0:I1, W1:I2, W2:I3,I4 + + -- TEST: READ [MAX_SAMPLES < SAMPLES] + -- TEST: READ [ANY SSTATE, ANY ISTATE, ANY VIEW] + + Log("R0,R1,R2,R3: DDS Operation READ [MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := READ; + dds.max_samples := 3; + dds.sstate := ANY_SAMPLE_STATE; + dds.istate := ANY_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + -- READER 0 + Log("R0: Expected ID0,ID1,ID9", DEBUG); + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- READER 1 + Log("R1: Expected ID0,ID1,ID9", DEBUG); + ind <= 1; + start_dds; + wait_on_sig(dds_done); + -- READER 2 + Log("R2: Expected ID0,ID1,ID9", DEBUG); + ind <= 2; + start_dds; + wait_on_sig(dds_done); + -- READER 3 + Log("R3: Expected ID0,ID1,ID2", DEBUG); + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- READER 0 / READER 1 / READER 2 + -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) + -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE + -- VIEW: I1:NOT_NEW, I2:NEW, I3:NEW, I4:NEW + -- WRITER: W0:I1, W1:I2, W2:I3,I4 + -- READER 3 + -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) + -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE + -- VIEW: I1:NEW, I2:NEW, I3:NEW, I4:NEW + -- WRITER: W0:I1, W1:I2, W2:I3,I4 + + -- TEST: READ MARKS SAMPLES AS READ + -- TEST: READ_NEXT_SAMPLE [WITH UNREAD SAMPLE] + + Log("R0,R1,R2,R3: DDS Operation READ_NEXT_SAMPLE", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := READ_NEXT_SAMPLE; + -- READER 0 + Log("R0: Expected ID2", DEBUG); + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- READER 1 + Log("R1: Expected ID2", DEBUG); + ind <= 1; + start_dds; + wait_on_sig(dds_done); + -- READER 2 + Log("R2: Expected ID2", DEBUG); + ind <= 2; + start_dds; + wait_on_sig(dds_done); + -- READER 3 + Log("R3: Expected ID3", DEBUG); + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- READER 0 / READER 1 / READER 2 + -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) + -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE + -- VIEW: I1:NOT_NEW, I2:NEW, I3:NEW, I4:NEW + -- WRITER: W0:I1, W1:I2, W2:I3,I4 + -- READER 3 + -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) + -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE + -- VIEW: I1:NEW, I2:NEW, I3:NOT_NEW, I4:NEW + -- WRITER: W0:I1, W1:I2, W2:I3,I4 + + -- TEST: READ_INSTANCE [KNOWN INSTANCE, COMPATIBLE SAMPLES] + + Log("R0,R1,R2: DDS Operation READ_INSTANCE [MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Instance 3]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := READ_INSTANCE; + dds.max_samples := 1; + dds.sstate := ANY_SAMPLE_STATE; + dds.istate := ANY_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + dds.inst := kh3; + -- READER 0 + Log("R0: Expected ID3", DEBUG); + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- READER 1 + Log("R1: Expected ID3", DEBUG); + ind <= 1; + start_dds; + wait_on_sig(dds_done); + -- READER 2 + Log("R2: Expected ID3", DEBUG); + ind <= 2; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) + -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE + -- VIEW: I1:NOT_NEW, I2:NEW, I3:NOT_NEW, I4:NEW + -- WRITER: W0:I1, W1:I2, W2:I3,I4 + + Log("R3: DDS Operation READ_INSTANCE [MAX_SAMPLES 1, NOT_READ_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Instance 3] (Expected ID9)", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := READ_INSTANCE; + dds.max_samples := 1; + dds.sstate := NOT_READ_SAMPLE_STATE; + dds.istate := ANY_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + dds.inst := kh1; + -- READER 3 + Log("R3: Expected ID9", DEBUG); + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) + -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE + -- VIEW: I1:NOT_NEW, I2:NEW, I3:NOT_NEW, I4:NEW + -- WRITER: W0:I1, W1:I2, W2:I3,I4 + + -- TEST: READ_NEXT_INSTANCE [WITH NEXT INSTANCE, COMPATIBLE SAMPLES] + + Log("R0,R1,R2,R3: DDS Operation READ_NEXT_INSTANCE [MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Instance 3]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := READ_NEXT_INSTANCE; + dds.max_samples := 1; + dds.sstate := ANY_SAMPLE_STATE; + dds.istate := ANY_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + dds.inst := kh3; + -- READER 0 + Log("R0: Expected ID4", DEBUG); + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- READER 1 + Log("R1: Expected ID4", DEBUG); + ind <= 1; + start_dds; + wait_on_sig(dds_done); + -- READER 2 + Log("R2: Expected ID4", DEBUG); + ind <= 2; + start_dds; + wait_on_sig(dds_done); + -- READER 3 + Log("R3: Expected ID4", DEBUG); + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) + -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE + -- VIEW: I1:NOT_NEW, I2:NEW, I3:NOT_NEW, I4:NEW + -- WRITER: W0:I1, W1:I2, W2:I3,I4 + + -- TEST: READ [SPECIFIED SSTATE, ANY ISTATE, ANY VIEW] + -- TEST: READ [MAX_SAMPLES > SAMPLES] + + Log("R0,R1,R2,R3: DDS Operation READ [MAX_SAMPLES 20, READ_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := READ; + dds.max_samples := 20; + dds.sstate := READ_SAMPLE_STATE; + dds.istate := ANY_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + -- READER 0 + Log("R0: Expected ID0,ID1,ID9,ID2,ID3,ID4", DEBUG); + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- READER 1 + Log("R1: Expected ID0,ID1,ID9,ID2,ID3,ID4", DEBUG); + ind <= 1; + start_dds; + wait_on_sig(dds_done); + -- READER 2 + Log("R2: Expected ID0,ID1,ID9,ID2,ID3,ID4", DEBUG); + ind <= 2; + start_dds; + wait_on_sig(dds_done); + -- READER 3 + Log("R3: Expected ID0,ID1,ID2,ID3,ID4,ID9", DEBUG); + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) + -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE + -- VIEW: I1:NOT_NEW, I2:NEW, I3:NOT_NEW, I4:NEW + -- WRITER: W0:I1, W1:I2, W2:I3,I4 + + -- TEST: READ [SPECIFIED SSTATE, SPECIFIED ISTATE, ANY VIEW] + + Log("R0,R1,R2,R3: DDS Operation READ [MAX_SAMPLES 20, READ_SAMPLE_STATE, NOT_ALIVE_DISPOSED_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := READ; + dds.max_samples := 20; + dds.sstate := READ_SAMPLE_STATE; + dds.istate := NOT_ALIVE_DISPOSED_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + -- READER 0 + Log("R0: Expected ID2,ID3", DEBUG); + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- READER 1 + Log("R1: Expected ID2,ID3", DEBUG); + ind <= 1; + start_dds; + wait_on_sig(dds_done); + -- READER 2 + Log("R2: Expected ID2,ID3", DEBUG); + ind <= 2; + start_dds; + wait_on_sig(dds_done); + -- READER 3 + Log("R3: Expected ID2,ID3", DEBUG); + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) + -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE + -- VIEW: I1:NOT_NEW, I2:NEW, I3:NOT_NEW, I4:NEW + -- WRITER: W0:I1, W1:I2, W2:I3,I4 + + -- TEST: READ [SPECIFIED SSTATE, ANY ISTATE, SPECIFIED VIEW] + -- TEST: READ MODIFIES VIEW STATE [READ CURRENT GENERATION] + -- TEST: READ MODIFIES VIEW STATE [READ PREVIOUS GENERATION] + + Log("R0,R1,R2,R3: DDS Operation READ [MAX_SAMPLES 20, READ_SAMPLE_STATE, ANY_INSTANCE_STATE, NEW_VIEW_STATE]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := READ; + dds.max_samples := 20; + dds.sstate := READ_SAMPLE_STATE; + dds.istate := ANY_INSTANCE_STATE; + dds.vstate := NEW_VIEW_STATE; + -- READER 0 + Log("R0: Expected ID2,ID4", DEBUG); + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- READER 1 + Log("R1: Expected ID2,ID4", DEBUG); + ind <= 1; + start_dds; + wait_on_sig(dds_done); + -- READER 2 + Log("R2: Expected ID2,ID4", DEBUG); + ind <= 2; + start_dds; + wait_on_sig(dds_done); + -- READER 3 + Log("R3: Expected ID2,ID4", DEBUG); + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) + -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE + -- VIEW: I1:NOT_NEW, I2:NEW, I3:NOT_NEW, I4:NEW + -- WRITER: W0:I1, W1:I2, W2:I3,I4 + + -- TEST: READ [SPECIFIED SSTATE, SPECIFIED ISTATE, SPECIFIED VIEW] + + Log("R0,R1,R2,R3: DDS Operation READ [MAX_SAMPLES 20, READ_SAMPLE_STATE, NOT_ALIVE_DISPOSED_INSTANCE_STATE, NEW_VIEW_STATE]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := READ; + dds.max_samples := 20; + dds.sstate := READ_SAMPLE_STATE; + dds.istate := NOT_ALIVE_DISPOSED_INSTANCE_STATE; + dds.vstate := NEW_VIEW_STATE; + -- READER 0 + Log("R0: Expected ID2", DEBUG); + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- READER 1 + Log("R1: Expected ID2", DEBUG); + ind <= 1; + start_dds; + wait_on_sig(dds_done); + -- READER 2 + Log("R2: Expected ID2", DEBUG); + ind <= 2; + start_dds; + wait_on_sig(dds_done); + -- READER 3 + Log("R3: Expected ID2", DEBUG); + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) + -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE + -- VIEW: I1:NOT_NEW, I2:NEW, I3:NOT_NEW, I4:NEW + -- WRITER: W0:I1, W1:I2, W2:I3,I4 + + -- TEST: READ [ANY SSTATE, ANY ISTATE, SPECIFIED VIEW] + + Log("R0,R1,R2,R3: DDS Operation READ [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, NOT_NEW_VIEW_STATE]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := READ; + dds.max_samples := 20; + dds.sstate := ANY_SAMPLE_STATE; + dds.istate := ANY_INSTANCE_STATE; + dds.vstate := NOT_NEW_VIEW_STATE; + -- READER 0 + Log("R0: Expected ID0,ID1,ID9,ID3,ID6", DEBUG); + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- READER 1 + Log("R1: Expected ID0,ID1,ID9,ID3,ID6", DEBUG); + ind <= 1; + start_dds; + wait_on_sig(dds_done); + -- READER 2 + Log("R2: Expected ID0,ID1,ID9,ID3,ID6", DEBUG); + ind <= 2; + start_dds; + wait_on_sig(dds_done); + -- READER 3 + Log("R3: Expected ID0,ID1,ID3,ID6,ID9", DEBUG); + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) + -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE + -- VIEW: I1:NOT_NEW, I2:NEW, I3:NOT_NEW, I4:NEW + -- WRITER: W0:I1, W1:I2, W2:I3,I4 + + -- TEST: READ [ANY SSTATE, SPECIFIED ISTATE, SPECIFIED VIEW] + + Log("R0,R1,R2,R3: DDS Operation READ [MAX_SAMPLES 20, ANY_SAMPLE_STATE, NOT_ALIVE_DISPOSED_INSTANCE_STATE, NOT_NEW_VIEW_STATE]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := READ; + dds.max_samples := 20; + dds.sstate := ANY_SAMPLE_STATE; + dds.istate := NOT_ALIVE_DISPOSED_INSTANCE_STATE; + dds.vstate := NOT_NEW_VIEW_STATE; + -- READER 0 + Log("R0: Expected ID3,ID6", DEBUG); + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- READER 1 + Log("R1: Expected ID3,ID6", DEBUG); + ind <= 1; + start_dds; + wait_on_sig(dds_done); + -- READER 2 + Log("R2: Expected ID3,ID6", DEBUG); + ind <= 2; + start_dds; + wait_on_sig(dds_done); + -- READER 3 + Log("R3: Expected ID3,ID6", DEBUG); + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) + -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE + -- VIEW: I1:NOT_NEW, I2:NEW, I3:NOT_NEW, I4:NEW + -- WRITER: W0:I1, W1:I2, W2:I3,I4 + + -- TEST: READ [ANY SSTATE, SPECIFIED ISTATE, ANY VIEW] + + Log("R0,R1,R2,R3: DDS Operation READ [MAX_SAMPLES 20, ANY_SAMPLE_STATE, NOT_ALIVE_DISPOSED_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := READ; + dds.max_samples := 20; + dds.sstate := ANY_SAMPLE_STATE; + dds.istate := NOT_ALIVE_DISPOSED_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + -- READER 0 + Log("R0: Expected ID2,ID5,ID10,ID11,ID3,ID6", DEBUG); + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- READER 1 + Log("R1: Expected ID2,ID5,ID10,ID11,ID3,ID6", DEBUG); + ind <= 1; + start_dds; + wait_on_sig(dds_done); + -- READER 2 + Log("R2: Expected ID2,ID5,ID10,ID11,ID3,ID6", DEBUG); + ind <= 2; + start_dds; + wait_on_sig(dds_done); + -- READER 3 + Log("R3: Expected ID2,ID3,ID5,ID6,ID10,ID11", DEBUG); + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) + -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE + -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NEW + -- WRITER: W0:I1, W1:I2, W2:I3,I4 + + -- TEST: READ_INSTANCE [UNKNOWN INSTANCE] + + Log("R0,R1,R2,R3: DDS Operation READ_INSTANCE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Unknown Instance]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := READ_INSTANCE; + dds.max_samples := 20; + dds.sstate := ANY_SAMPLE_STATE; + dds.istate := ANY_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + dds.inst := kh5; + dds.ret_code := RETCODE_BAD_PARAMETER; + -- READER 0 + Log("R0: Bad Parameter", DEBUG); + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- READER 1 + Log("R1: Bad Parameter", DEBUG); + ind <= 1; + start_dds; + wait_on_sig(dds_done); + -- READER 2 + Log("R2: Bad Parameter", DEBUG); + ind <= 2; + start_dds; + wait_on_sig(dds_done); + -- READER 3 + Log("R3: Bad Parameter", DEBUG); + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) + -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE + -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NEW + -- WRITER: W0:I1, W1:I2, W2:I3,I4 + + -- TEST: READ_INSTANCE [KNOWN INSTANCE, UNCOMPATIBLE SAMPLES] + + Log("R0,R1,R2,R3: DDS Operation READ_INSTANCE [MAX_SAMPLES 20, NOT_READ_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Instance 1]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := READ_INSTANCE; + dds.max_samples := 20; + dds.sstate := NOT_READ_SAMPLE_STATE; + dds.istate := ANY_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + dds.inst := kh1; + dds.ret_code := RETCODE_NO_DATA; + -- READER 0 + Log("R0: No Data", DEBUG); + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- READER 1 + Log("R1: No Data", DEBUG); + ind <= 1; + start_dds; + wait_on_sig(dds_done); + -- READER 2 + Log("R2: No Data", DEBUG); + ind <= 2; + start_dds; + wait_on_sig(dds_done); + -- READER 3 + Log("R3: No Data", DEBUG); + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) + -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE + -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NEW + -- WRITER: W0:I1, W1:I2, W2:I3,I4 + + -- TEST: READ_NEXT_INSTANCE [WITH NEXT INSTANCE, UNCOMPATIBLE SAMPLES] + + Log("R0,R1,R2,R3: DDS Operation READ_NEXT_INSTANCE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, NOT_ALIVE_DISPOSED_INSTANCE_STATE, ANY_VIEW_STATE, Instance 2]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := READ_NEXT_INSTANCE; + dds.max_samples := 20; + dds.sstate := ANY_SAMPLE_STATE; + dds.istate := NOT_ALIVE_DISPOSED_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + dds.inst := kh2; + dds.ret_code := RETCODE_NO_DATA; + -- READER 0 + Log("R0: No Data", DEBUG); + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- READER 1 + Log("R1: No Data", DEBUG); + ind <= 1; + start_dds; + wait_on_sig(dds_done); + -- READER 2 + Log("R2: No Data", DEBUG); + ind <= 2; + start_dds; + wait_on_sig(dds_done); + -- READER 3 + Log("R3: No Data", DEBUG); + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) + -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE + -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NEW + -- WRITER: W0:I1, W1:I2, W2:I3,I4 + + -- TEST: READ_NEXT_INSTANCE [WITH NEXT INSTANCE, WITH COMPATIBLE SAMPLE, NOT DIRECT NEXT INSTANCE] + + Log("R0,R1,R2,R3: DDS Operation READ_NEXT_INSTANCE [MAX_SAMPLES 20, NOT_READ_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Instance 3]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := READ_NEXT_INSTANCE; + dds.max_samples := 20; + dds.sstate := NOT_READ_SAMPLE_STATE; + dds.istate := ANY_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + dds.inst := kh3; + dds.ret_code := RETCODE_OK; + -- READER 0 + Log("R0: Expected ID7,ID8", DEBUG); + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- READER 1 + Log("R1: Expected ID7,ID8", DEBUG); + ind <= 1; + start_dds; + wait_on_sig(dds_done); + -- READER 2 + Log("R2: Expected ID7,ID8", DEBUG); + ind <= 2; + start_dds; + wait_on_sig(dds_done); + -- READER 3 + Log("R3: Expected ID7,ID8", DEBUG); + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) + -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE + -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW + -- WRITER: W0:I1, W1:I2, W2:I3,I4 + + -- TEST: READ [NO COMPATIBLE SAMPLES] + + Log("R0,R1,R2,R3: DDS Operation READ [MAX_SAMPLES 20, ANY_SAMPLE_STATE, NOT_ALIVE_NO_WRITERS_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := READ; + dds.max_samples := 20; + dds.sstate := ANY_SAMPLE_STATE; + dds.istate := NOT_ALIVE_NO_WRITERS_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + dds.ret_code := RETCODE_NO_DATA; + -- READER 0 + Log("R0: No Data", DEBUG); + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- READER 1 + Log("R1: No Data", DEBUG); + ind <= 1; + start_dds; + wait_on_sig(dds_done); + -- READER 2 + Log("R2: No Data", DEBUG); + ind <= 2; + start_dds; + wait_on_sig(dds_done); + -- READER 3 + Log("R3: No Data", DEBUG); + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) + -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE + -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW + -- WRITER: W0:I1, W1:I2, W2:I3,I4 + + -- TEST: READ_NEXT_SAMPLE [WITHOUT UNREAD SAMPLE] + + Log("R0,R1,R2,R3: DDS Operation READ_NEXT_SAMPLE", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := READ_NEXT_SAMPLE; + dds.ret_code := RETCODE_NO_DATA; + -- READER 0 + Log("R0: No Data", DEBUG); + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- READER 1 + Log("R1: No Data", DEBUG); + ind <= 1; + start_dds; + wait_on_sig(dds_done); + -- READER 2 + Log("R2: No Data", DEBUG); + ind <= 2; + start_dds; + wait_on_sig(dds_done); + -- READER 3 + Log("R3: No Data", DEBUG); + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) + -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE + -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW + -- WRITER: W0:I1, W1:I2, W2:I3,I4 + + -- TEST: TAKE + + Log("R0,R1,R2,R3: DDS Operation TAKE [MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := TAKE; + dds.max_samples := 1; + dds.sstate := ANY_SAMPLE_STATE; + dds.istate := ANY_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + dds.ret_code := RETCODE_OK; + -- READER 0 + Log("R0: Expected ID0", DEBUG); + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- READER 1 + Log("R1: Expected ID0", DEBUG); + ind <= 1; + start_dds; + wait_on_sig(dds_done); + -- READER 2 + Log("R2: Expected ID0", DEBUG); + ind <= 2; + start_dds; + wait_on_sig(dds_done); + -- READER 3 + Log("R3: Expected ID0", DEBUG); + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- MEM: I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) + -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE + -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW + -- WRITER: W0:I1, W1:I2, W2:I3,I4 + + -- TEST: TAKE_INSTANCE + + Log("R0,R1,R2,R3: DDS Operation TAKE_INSTANCE [MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Instance 2]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := TAKE_INSTANCE; + dds.max_samples := 1; + dds.sstate := ANY_SAMPLE_STATE; + dds.istate := ANY_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + dds.inst := kh2; + dds.ret_code := RETCODE_OK; + -- READER 0 + Log("R0: Expected ID2", DEBUG); + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- READER 1 + Log("R1: Expected ID2", DEBUG); + ind <= 1; + start_dds; + wait_on_sig(dds_done); + -- READER 2 + Log("R2: Expected ID2", DEBUG); + ind <= 2; + start_dds; + wait_on_sig(dds_done); + -- READER 3 + Log("R3: Expected ID2", DEBUG); + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- MEM: I1S2-(1), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) + -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE + -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW + -- WRITER: W0:I1, W1:I2, W2:I3,I4 + + -- TEST: TAKE_NEXT_INSTANCE + -- TEST: READ_NEXT_INSTANCE [HANDLE_NIL] + + Log("R0,R1,R2,R3: DDS Operation TAKE_NEXT_INSTANCE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, HANDLE_NIL]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := TAKE_NEXT_INSTANCE; + dds.max_samples := 20; + dds.sstate := ANY_SAMPLE_STATE; + dds.istate := ANY_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + dds.inst := HANDLE_NIL; + dds.ret_code := RETCODE_OK; + -- READER 0 + Log("R0: Expected ID3,ID6", DEBUG); + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- READER 1 + Log("R1: Expected ID3,ID6", DEBUG); + ind <= 1; + start_dds; + wait_on_sig(dds_done); + -- READER 2 + Log("R2: Expected ID3,ID6", DEBUG); + ind <= 2; + start_dds; + wait_on_sig(dds_done); + -- READER 3 + Log("R3: Expected ID3,ID6", DEBUG); + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- MEM: I1S2-(1), I4S1(4), I2S2-(5), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) + -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE + -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW + -- WRITER: W0:I1, W1:I2, W2:I3,I4 + + -- TEST: TAKE REMOVES SAMPLE + -- TEST: READ_INSTANCE [NO SAMPLES] + + Log("R0,R1,R2,R3: DDS Operation READ_INSTANCE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Instance 3]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := READ_INSTANCE; + dds.max_samples := 20; + dds.sstate := ANY_SAMPLE_STATE; + dds.istate := ANY_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + dds.inst := kh3; + dds.ret_code := RETCODE_NO_DATA; + -- READER 0 + Log("R0: No Data", DEBUG); + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- READER 1 + Log("R1: No Data", DEBUG); + ind <= 1; + start_dds; + wait_on_sig(dds_done); + -- READER 2 + Log("R2: No Data", DEBUG); + ind <= 2; + start_dds; + wait_on_sig(dds_done); + -- READER 3 + Log("R3: No Data", DEBUG); + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- MEM: I1S2-(1), I4S1(4), I2S2-(5), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) + -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE + -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW + -- WRITER: W0:I1, W1:I2, W2:I3,I4 + + Log("R0,R1,R2,R3: DDS Operation TAKE_NEXT_INSTANCE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Instance 3]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := TAKE_NEXT_INSTANCE; + dds.max_samples := 20; + dds.sstate := ANY_SAMPLE_STATE; + dds.istate := ANY_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + dds.inst := kh3; + dds.ret_code := RETCODE_OK; + -- READER 0 + Log("R0: Expected ID4,ID7,ID8", DEBUG); + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- READER 1 + Log("R1: Expected ID4,ID7,ID8", DEBUG); + ind <= 1; + start_dds; + wait_on_sig(dds_done); + -- READER 2 + Log("R2: Expected ID4,ID7,ID8", DEBUG); + ind <= 2; + start_dds; + wait_on_sig(dds_done); + -- READER 3 + Log("R3: Expected ID4,ID7,ID8", DEBUG); + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- MEM: I1S2-(1), I2S2-(5), I1S3(9), I2S3(10), I2S4-(11) + -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE + -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW + -- WRITER: W0:I1, W1:I2, W2:I3,I4 + + -- TEST: TAKE_INSTANCE [NO SAMPLES] + + Log("R0,R1,R2,R3: DDS Operation TAKE_INSTANCE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Instance 4]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := TAKE_INSTANCE; + dds.max_samples := 20; + dds.sstate := ANY_SAMPLE_STATE; + dds.istate := ANY_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + dds.inst := kh4; + dds.ret_code := RETCODE_NO_DATA; + -- READER 0 + Log("R0: No Data", DEBUG); + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- READER 1 + Log("R1: No Data", DEBUG); + ind <= 1; + start_dds; + wait_on_sig(dds_done); + -- READER 2 + Log("R2: No Data", DEBUG); + ind <= 2; + start_dds; + wait_on_sig(dds_done); + -- READER 3 + Log("R3: No Data", DEBUG); + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- MEM: I1S2-(1), I2S2-(5), I1S3(9), I2S3(10), I2S4-(11) + -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE + -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW + -- WRITER: W0:I1, W1:I2, W2:I3,I4 + + Log("R0,R1,R2,R3: DDS Operation TAKE_NEXT_INSTANCE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Instance 4]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := TAKE_NEXT_INSTANCE; + dds.max_samples := 20; + dds.sstate := ANY_SAMPLE_STATE; + dds.istate := ANY_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + dds.inst := kh4; + dds.ret_code := RETCODE_OK; + -- READER 0 + Log("R0: Expected ID5,ID10,ID11", DEBUG); + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- READER 1 + Log("R1: Expected ID5,ID10,ID11", DEBUG); + ind <= 1; + start_dds; + wait_on_sig(dds_done); + -- READER 2 + Log("R2: Expected ID5,ID10,ID11", DEBUG); + ind <= 2; + start_dds; + wait_on_sig(dds_done); + -- READER 3 + Log("R3: Expected ID5,ID10,ID11", DEBUG); + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- MEM: I1S2-(1), I1S3(9) + -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE + -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW + -- WRITER: W0:I1, W1:I2, W2:I3,I4 + + Log("R0,R1,R2,R3: DDS Operation READ_INSTANCE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Instance 2]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := READ_INSTANCE; + dds.max_samples := 20; + dds.sstate := ANY_SAMPLE_STATE; + dds.istate := ANY_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + dds.inst := kh2; + dds.ret_code := RETCODE_NO_DATA; + -- READER 0 + Log("R0: No Data", DEBUG); + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- READER 1 + Log("R1: No Data", DEBUG); + ind <= 1; + start_dds; + wait_on_sig(dds_done); + -- READER 2 + Log("R2: No Data", DEBUG); + ind <= 2; + start_dds; + wait_on_sig(dds_done); + -- READER 3 + Log("R3: No Data", DEBUG); + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- MEM: I1S2-(1), I1S3(9) + -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE + -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW + -- WRITER: W0:I1, W1:I2, W2:I3,I4 + + -- TEST: READ_NEXT_INSTANCE [WITH SAMPLES, WITHOUT NEXT INSTANCE] + + Log("R0,R1,R2,R3: DDS Operation READ_NEXT_INSTANCE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Instance 1]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := READ_NEXT_INSTANCE; + dds.max_samples := 20; + dds.sstate := ANY_SAMPLE_STATE; + dds.istate := ANY_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + dds.inst := kh1; + dds.ret_code := RETCODE_NO_DATA; + -- READER 0 + Log("R0: No Data", DEBUG); + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- READER 1 + Log("R1: No Data", DEBUG); + ind <= 1; + start_dds; + wait_on_sig(dds_done); + -- READER 2 + Log("R2: No Data", DEBUG); + ind <= 2; + start_dds; + wait_on_sig(dds_done); + -- READER 3 + Log("R3: No Data", DEBUG); + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- MEM: I1S2-(1), I1S3(9) + -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE + -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW + -- WRITER: W0:I1, W1:I2, W2:I3,I4 + + Log("R0,R1,R2,R3: DDS Operation TAKE_NEXT_INSTANCE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Instance 2]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := TAKE_NEXT_INSTANCE; + dds.max_samples := 20; + dds.sstate := ANY_SAMPLE_STATE; + dds.istate := ANY_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + dds.inst := kh2; + dds.ret_code := RETCODE_OK; + -- READER 0 + Log("R0: Expected ID1,ID9", DEBUG); + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- READER 1 + Log("R1: Expected ID1,ID9", DEBUG); + ind <= 1; + start_dds; + wait_on_sig(dds_done); + -- READER 2 + Log("R2: Expected ID1,ID9", DEBUG); + ind <= 2; + start_dds; + wait_on_sig(dds_done); + -- READER 3 + Log("R3: Expected ID1,ID9", DEBUG); + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- MEM: - + -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE + -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW + -- WRITER: W0:I1, W1:I2, W2:I3,I4 + + -- TEST: GET ALL DATA WITH READ_NEXT_INSTANCE + -- TEST: READ [NO SAMPLES] + + Log("R0,R1,R2,R3: DDS Operation READ [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := READ; + dds.max_samples := 20; + dds.sstate := ANY_SAMPLE_STATE; + dds.istate := ANY_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + dds.ret_code := RETCODE_NO_DATA; + -- READER 0 + Log("R0: No Data", DEBUG); + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- READER 1 + Log("R1: No Data", DEBUG); + ind <= 1; + start_dds; + wait_on_sig(dds_done); + -- READER 2 + Log("R2: No Data", DEBUG); + ind <= 2; + start_dds; + wait_on_sig(dds_done); + -- READER 3 + Log("R3: No Data", DEBUG); + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- MEM: - + -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE + -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW + -- WRITER: W0:I1, W1:I2, W2:I3,I4 + + -- TEST: TAKE [NO SAMPLES] + + Log("R0,R1,R2,R3: DDS Operation TAKE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := TAKE; + dds.max_samples := 20; + dds.sstate := ANY_SAMPLE_STATE; + dds.istate := ANY_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + dds.ret_code := RETCODE_NO_DATA; + -- READER 0 + Log("R0: No Data", DEBUG); + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- READER 1 + Log("R1: No Data", DEBUG); + ind <= 1; + start_dds; + wait_on_sig(dds_done); + -- READER 2 + Log("R2: No Data", DEBUG); + ind <= 2; + start_dds; + wait_on_sig(dds_done); + -- READER 3 + Log("R3: No Data", DEBUG); + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- MEM: - + -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE + -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW + -- WRITER: W0:I1, W1:I2, W2:I3,I4 + + -- TEST: READ_NEXT_INSTANCE [NO SAMPLE] + + Log("R0,R1,R2,R3: DDS Operation READ_NEXT_INSTANCE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, HANDLE_NIL]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := READ_NEXT_INSTANCE; + dds.max_samples := 20; + dds.sstate := ANY_SAMPLE_STATE; + dds.istate := ANY_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + dds.inst := HANDLE_NIL; + dds.ret_code := RETCODE_NO_DATA; + -- READER 0 + Log("R0: No Data", DEBUG); + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- READER 1 + Log("R1: No Data", DEBUG); + ind <= 1; + start_dds; + wait_on_sig(dds_done); + -- READER 2 + Log("R2: No Data", DEBUG); + ind <= 2; + start_dds; + wait_on_sig(dds_done); + -- READER 3 + Log("R3: No Data", DEBUG); + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- MEM: - + -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE + -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW + -- WRITER: W0:I1, W1:I2, W2:I3,I4 + + -- TEST: TAKE_NEXT_INSTANCE [NO SAMPLE] + + Log("R0,R1,R2,R3: DDS Operation TAKE_NEXT_INSTANCE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, HANDLE_NIL]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := TAKE_NEXT_INSTANCE; + dds.max_samples := 20; + dds.sstate := ANY_SAMPLE_STATE; + dds.istate := ANY_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + dds.inst := HANDLE_NIL; + dds.ret_code := RETCODE_NO_DATA; + -- READER 0 + Log("R0: No Data", DEBUG); + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- READER 1 + Log("R1: No Data", DEBUG); + ind <= 1; + start_dds; + wait_on_sig(dds_done); + -- READER 2 + Log("R2: No Data", DEBUG); + ind <= 2; + start_dds; + wait_on_sig(dds_done); + -- READER 3 + Log("R3: No Data", DEBUG); + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- MEM: - + -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE + -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW + -- WRITER: W0:I1, W1:I2, W2:I3,I4 + + -- TEST: READ_NEXT_SAMPLE [NO SAMPLE] + + Log("R0,R1,R2,R3: DDS Operation READ_NEXT_SAMPLE", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := READ_NEXT_SAMPLE; + dds.ret_code := RETCODE_NO_DATA; + -- READER 0 + Log("R0: No Data", DEBUG); + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- READER 1 + Log("R1: No Data", DEBUG); + ind <= 1; + start_dds; + wait_on_sig(dds_done); + -- READER 2 + Log("R2: No Data", DEBUG); + ind <= 2; + start_dds; + wait_on_sig(dds_done); + -- READER 3 + Log("R3: No Data", DEBUG); + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- MEM: - + -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE + -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW + -- WRITER: W0:I1, W1:I2, W2:I3,I4 + + -- TEST: TAKE_NEXT_SAMPLE [NO SAMPLE] + + Log("R0,R1,R2,R3: DDS Operation TAKE_NEXT_SAMPLE", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := TAKE_NEXT_SAMPLE; + dds.ret_code := RETCODE_NO_DATA; + -- READER 0 + Log("R0: No Data", DEBUG); + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- READER 1 + Log("R1: No Data", DEBUG); + ind <= 1; + start_dds; + wait_on_sig(dds_done); + -- READER 2 + Log("R2: No Data", DEBUG); + ind <= 2; + start_dds; + wait_on_sig(dds_done); + -- READER 3 + Log("R3: No Data", DEBUG); + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- MEM: - + -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE + -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW + -- WRITER: W0:I1, W1:I2, W2:I3,I4 + + Log("Current Time: 12s", INFO); + check_time <= gen_duration(12 sec); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait_on_idle; + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh2; + cc.payload := gen_payload(kh2,10); + cc.src_timestamp := gen_duration(12 sec); + + Log("R0,R1,R2,R3: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 2, Writer 1, Aligned Payload, ID 12]", INFO); + Log("R0,R1,R2,R3: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 1; + rtps.ret_code := OK; + s := to_sample(cc,ALIVE_INSTANCE_STATE); + add_sample(s,mem(0), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(1), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(2), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(3), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + -- READER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- READER 1 + ind <= 1; + start_rtps; + wait_on_sig(rtps_done); + -- READER 2 + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + -- READER 3 + ind <= 3; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- MEM: I2S5(12) + -- ISTATE: I1:ALIVE, I2:ALIVE, I3:DISPOSED, I4:ALIVE + -- VIEW: I1:NOT_NEW, I2:NEW, I3:NOT_NEW, I4:NOT_NEW + -- WRITER: W0:I1, W1:I2, W2:I3,I4 + + -- TEST: TAKE_NEXT_SAMPLE + + Log("R0,R1,R2,R3: DDS Operation TAKE_NEXT_SAMPLE", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := TAKE_NEXT_SAMPLE; + dds.ret_code := RETCODE_OK; + -- READER 0 + Log("R0: Expected ID12", DEBUG); + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- READER 1 + Log("R1: Expected ID12", DEBUG); + ind <= 1; + start_dds; + wait_on_sig(dds_done); + -- READER 2 + Log("R2: Expected ID12", DEBUG); + ind <= 2; + start_dds; + wait_on_sig(dds_done); + -- READER 3 + Log("R3: Expected ID12", DEBUG); + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- MEM: - + -- ISTATE: I1:ALIVE, I2:ALIVE, I3:DISPOSED, I4:ALIVE + -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW + -- WRITER: W0:I1, W1:I2, W2:I3,I4 + + Log("R0,R1,R2,R3: DDS Operation READ [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := READ; + dds.max_samples := 20; + dds.sstate := ANY_SAMPLE_STATE; + dds.istate := ANY_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + dds.ret_code := RETCODE_NO_DATA; + -- READER 0 + Log("R0: No Data", DEBUG); + ind <= 0; + start_dds; + wait_on_sig(dds_done); + -- READER 1 + Log("R1: No Data", DEBUG); + ind <= 1; + start_dds; + wait_on_sig(dds_done); + -- READER 2 + Log("R2: No Data", DEBUG); + ind <= 2; + start_dds; + wait_on_sig(dds_done); + -- READER 3 + Log("R3: No Data", DEBUG); + ind <= 3; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- MEM: - + -- ISTATE: I1:ALIVE, I2:ALIVE, I3:DISPOSED, I4:ALIVE + -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW + -- WRITER: W0:I1, W1:I2, W2:I3,I4 + + Log("*READER 4*", INFO); + -- MEM: - + -- ISTATE: - + -- VIEW: - + -- WRITER: - + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.payload := gen_payload(KEY_HASH_NIL,10); + cc.src_timestamp := gen_duration(0 sec); + + Log("R4: RTPS Operation ADD_CACHE_CHANGE [Writer 0, Aligned Payload]", INFO); + Log("R4: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 0; + rtps.ret_code := OK; + s := to_sample(cc,ALIVE_INSTANCE_STATE); + add_sample(s,mem(4), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + -- READER 4 + ind <= 4; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- MEM: S0 + -- ISTATE: ALIVE + -- VIEW: NEW + -- WRITER: 0 + + Log("Current Time: 1s", INFO); + check_time <= gen_duration(1,0); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait_on_idle; + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := NOT_ALIVE_DISPOSED; + cc.src_timestamp := gen_duration(1 sec); + + Log("R4: RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Writer 0, Aligned Payload]", INFO); + Log("R4: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 0; + rtps.ret_code := OK; + s := to_sample(cc,NOT_ALIVE_DISPOSED_INSTANCE_STATE); + add_sample(s,mem(4), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + -- READER 4 + ind <= 4; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- MEM: S0, S1- + -- ISTATE: DISPOSED + -- VIEW: NEW + -- WRITER: 0 + + -- TEST: READ [MAX_SAMPLES < SAMPLES] + + Log("R4: DDS Operation READ [MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); + Log("R4: Expected ID0", DEBUG); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := READ; + dds.max_samples := 1; + dds.sstate := ANY_SAMPLE_STATE; + dds.istate := ANY_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + -- READER 4 + ind <= 4; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- MEM: S0, S1- + -- ISTATE: DISPOSED + -- VIEW: NOT_NEW + -- WRITER: 0 + + -- TEST: READ [NO COMPATIBLE SAMPLES] + -- TEST: READ MODIFIES VIEW STATE [READ CURRENT GENERATION] + + Log("R4: DDS Operation READ [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, NEW_VIEW_STATE]", INFO); + Log("R4: No Data", DEBUG); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := READ; + dds.max_samples := 20; + dds.sstate := ANY_SAMPLE_STATE; + dds.istate := ANY_INSTANCE_STATE; + dds.vstate := NEW_VIEW_STATE; + dds.ret_code := RETCODE_NO_DATA; + -- READER 4 + ind <= 4; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- MEM: S0, S1- + -- ISTATE: DISPOSED + -- VIEW: NOT_NEW + -- WRITER: 0 + + Log("Current Time: 2s", INFO); + check_time <= gen_duration(2,0); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait_on_idle; + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.payload := gen_payload(KEY_HASH_NIL,10); + cc.src_timestamp := gen_duration(2 sec); + + Log("R4: RTPS Operation ADD_CACHE_CHANGE [Writer 0, Aligned Payload]", INFO); + Log("R4: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 0; + rtps.ret_code := OK; + s := to_sample(cc,ALIVE_INSTANCE_STATE); + add_sample(s,mem(4), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + -- READER 4 + ind <= 4; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- MEM: S0, S1-, S2 + -- ISTATE: ALIVE + -- VIEW: NEW + -- WRITER: 0 + + -- TEST: READ_NEXT_SAMPLE [WITH UNREAD SAMPLE] + + Log("R4: DDS Operation READ_NEXT_SAMPLE", INFO); + Log("R4: Expected ID1", DEBUG); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := READ_NEXT_SAMPLE; + -- READER 4 + ind <= 4; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- MEM: S0, S1-, S2 + -- ISTATE: ALIVE + -- VIEW: NEW + -- WRITER: 0 + + -- TEST: READ MARKS SAMPLES AS READ + -- TEST: READ MODIFIES VIEW STATE [READ PREVIOUS GENERATION] + -- TEST: READ [MAX_SAMPLES > SAMPLES] + + Log("R4: DDS Operation READ [MAX_SAMPLES 20, READ_SAMPLE_STATE, ALIVE_INSTANCE_STATE, NEW_VIEW_STATE]", INFO); + Log("R4: Expected ID0,ID1", DEBUG); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := READ; + dds.max_samples := 20; + dds.sstate := READ_SAMPLE_STATE; + dds.istate := ALIVE_INSTANCE_STATE; + dds.vstate := NEW_VIEW_STATE; + -- READER 4 + ind <= 4; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- MEM: S0, S1-, S2 + -- ISTATE: ALIVE + -- VIEW: NEW + -- WRITER: 0 + + -- TEST: TAKE + + Log("R4: DDS Operation TAKE [MAX_SAMPLES 1, READ_SAMPLE_STATE, ALIVE_INSTANCE_STATE, NEW_VIEW_STATE]", INFO); + Log("R4: Expected ID0", DEBUG); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := TAKE; + dds.max_samples := 1; + dds.sstate := READ_SAMPLE_STATE; + dds.istate := ALIVE_INSTANCE_STATE; + dds.vstate := NEW_VIEW_STATE; + -- READER 4 + ind <= 4; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- MEM: S1-, S2 + -- ISTATE: ALIVE + -- VIEW: NEW + -- WRITER: 0 + + -- TEST: TAKE_NEXT_SAMPLE + + Log("R4: DDS Operation TAKE_NEXT_SAMPLE", INFO); + Log("R4: Expected ID2", DEBUG); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := TAKE_NEXT_SAMPLE; + -- READER 4 + ind <= 4; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- MEM: S1- + -- ISTATE: ALIVE + -- VIEW: NOT_NEW + -- WRITER: 0 + + -- TEST: READ_NEXT_SAMPLE [WITHOUT UNREAD SAMPLE] + + Log("R4: DDS Operation READ_NEXT_SAMPLE", INFO); + Log("R4: No Data", DEBUG); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := READ_NEXT_SAMPLE; + dds.ret_code := RETCODE_NO_DATA; + -- READER 4 + ind <= 4; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- MEM: S1- + -- ISTATE: ALIVE + -- VIEW: NOT_NEW + -- WRITER: 0 + + Log("R4: DDS Operation TAKE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); + Log("R4: Expected ID1", DEBUG); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := TAKE; + dds.max_samples := 20; + dds.sstate := ANY_SAMPLE_STATE; + dds.istate := ANY_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + -- READER 4 + ind <= 4; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- MEM: - + -- ISTATE: ALIVE + -- VIEW: NOT_NEW + -- WRITER: 0 + + -- TEST: TAKE REMOVES SAMPLE + -- TEST: TAKE [NO SAMPLES] + + Log("R4: DDS Operation TAKE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); + Log("R4: No Data", DEBUG); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := TAKE; + dds.max_samples := 20; + dds.sstate := ANY_SAMPLE_STATE; + dds.istate := ANY_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + dds.ret_code := RETCODE_NO_DATA; + -- READER 4 + ind <= 4; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- MEM: - + -- ISTATE: ALIVE + -- VIEW: NOT_NEW + -- WRITER: 0 + + -- TEST: READ [NO SAMPLES] + + Log("R4: DDS Operation READ [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); + Log("R4: No Data", DEBUG); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := READ; + dds.max_samples := 20; + dds.sstate := ANY_SAMPLE_STATE; + dds.istate := ANY_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + dds.ret_code := RETCODE_NO_DATA; + -- READER 4 + ind <= 4; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- MEM: - + -- ISTATE: ALIVE + -- VIEW: NOT_NEW + -- WRITER: 0 + + -- TEST: READ_NEXT_SAMPLE [NO SAMPLE] + + Log("R4: DDS Operation READ_NEXT_SAMPLE", INFO); + Log("R4: No Data", DEBUG); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := READ_NEXT_SAMPLE; + dds.ret_code := RETCODE_NO_DATA; + -- READER 4 + ind <= 4; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- MEM: - + -- ISTATE: ALIVE + -- VIEW: NOT_NEW + -- WRITER: 0 + + -- TEST: TAKE_NEXT_SAMPLE [NO SAMPLE] + + Log("R4: DDS Operation TAKE_NEXT_SAMPLE", INFO); + Log("R4: No Data", DEBUG); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := TAKE_NEXT_SAMPLE; + dds.ret_code := RETCODE_NO_DATA; + -- READER 4 + ind <= 4; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- MEM: - + -- ISTATE: ALIVE + -- VIEW: NOT_NEW + -- WRITER: 0 + + -- TEST: READ_INSTANCE + + Log("R4: DDS Operation READ_INSTANCE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Instance 1]", INFO); + Log("R4: Illegal Operation", DEBUG); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := READ_INSTANCE; + dds.max_samples := 20; + dds.sstate := ANY_SAMPLE_STATE; + dds.istate := ANY_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + dds.inst := kh1; + dds.ret_code := RETCODE_ILLEGAL_OPERATION; + -- READER 4 + ind <= 4; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- MEM: - + -- ISTATE: ALIVE + -- VIEW: NOT_NEW + -- WRITER: 0 + + -- TEST: TAKE_INSTANCE + + Log("R4: DDS Operation TAKE_INSTANCE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Instance 1]", INFO); + Log("R4: Illegal Operation", DEBUG); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := TAKE_INSTANCE; + dds.max_samples := 20; + dds.sstate := ANY_SAMPLE_STATE; + dds.istate := ANY_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + dds.inst := kh1; + dds.ret_code := RETCODE_ILLEGAL_OPERATION; + -- READER 4 + ind <= 4; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- MEM: - + -- ISTATE: ALIVE + -- VIEW: NOT_NEW + -- WRITER: 0 + + -- TEST: READ_NEXT_INSTANCE + + Log("R4: DDS Operation READ_NEXT_INSTANCE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Instance 1]", INFO); + Log("R4: Illegal Operation", DEBUG); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := READ_NEXT_INSTANCE; + dds.max_samples := 20; + dds.sstate := ANY_SAMPLE_STATE; + dds.istate := ANY_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + dds.inst := kh1; + dds.ret_code := RETCODE_ILLEGAL_OPERATION; + -- READER 4 + ind <= 4; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- MEM: - + -- ISTATE: ALIVE + -- VIEW: NOT_NEW + -- WRITER: 0 + + -- TEST: TAKE_NEXT_INSTANCE + + Log("R4: DDS Operation TAKE_NEXT_INSTANCE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Instance 1]", INFO); + Log("R4: Illegal Operation", DEBUG); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := TAKE_NEXT_INSTANCE; + dds.max_samples := 20; + dds.sstate := ANY_SAMPLE_STATE; + dds.istate := ANY_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + dds.inst := kh1; + dds.ret_code := RETCODE_ILLEGAL_OPERATION; + -- READER 4 + ind <= 4; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- MEM: - + -- ISTATE: ALIVE + -- VIEW: NOT_NEW + -- WRITER: 0 + + Log("*READER 5*", INFO); + -- MEM: - + -- ISTATE: - + -- VIEW: - + -- WRITER: - + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := TRUE; + cc.kind := NOT_ALIVE_DISPOSED; + cc.instance := kh4; + cc.payload := gen_payload(kh4,5); + cc.src_timestamp := gen_duration(7 sec); + + Log("R5: RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Instance 4, Writer 2, ID 7]", INFO); + Log("R5: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 2; + rtps.ret_code := OK; + s := to_sample(cc,NOT_ALIVE_DISPOSED_INSTANCE_STATE); + add_sample(s,mem(5), BY_SOURCE_TIMESTAMP_DESTINATION_ORDER_QOS); + -- READER 5 + ind <= 5; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- MEM: I4S2-(7) + -- ISTATE: I4:DISOSED + -- VIEW: I4:NEW + -- WRITER: W2:I4 + + Log("Current Time: 1s", INFO); + check_time <= gen_duration(1 sec); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait_on_idle; + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh1; + cc.payload := gen_payload(kh1,10); + cc.src_timestamp := gen_duration(0,0); + + Log("R5: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Aligned Payload, ID 0]", INFO); + Log("R5: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 0; + rtps.ret_code := OK; + s := to_sample(cc,ALIVE_INSTANCE_STATE); + add_sample(s,mem(5), BY_SOURCE_TIMESTAMP_DESTINATION_ORDER_QOS); + -- READER 5 + ind <= 5; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- MEM: I1S1(0), I4S2-(7) + -- ISTATE: I1:ALIVE, I4:DISOSED + -- VIEW: I1:NEW, I4:NEW + -- WRITER: W0:I1, W2:I4 + + Log("Current Time: 2s", INFO); + check_time <= gen_duration(2 sec); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait_on_idle; + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := TRUE; + cc.kind := NOT_ALIVE_DISPOSED; + cc.instance := kh1; + cc.payload := gen_payload(kh1,5); + cc.src_timestamp := gen_duration(1,0); + + Log("R5: RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Instance 1, Writer 0, ID 1]", INFO); + Log("R5: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 0; + rtps.ret_code := OK; + s := to_sample(cc,NOT_ALIVE_DISPOSED_INSTANCE_STATE); + add_sample(s,mem(5), BY_SOURCE_TIMESTAMP_DESTINATION_ORDER_QOS); + -- READER 5 + ind <= 5; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- MEM: I1S1(0), I1S2-(1), I4S2-(7) + -- ISTATE: I1:DISPOSED, I4:DISOSED + -- VIEW: I1:NEW, I4:NEW + -- WRITER: W0:I1, W2:I4 + + Log("Current Time: 3s", INFO); + check_time <= gen_duration(3 sec); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait_on_idle; + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh1; + cc.payload := gen_payload(kh1,10); + cc.src_timestamp := gen_duration(9 sec); + + Log("R5: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Aligned Payload, ID 9]", INFO); + Log("R5: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 0; + rtps.ret_code := OK; + s := to_sample(cc,ALIVE_INSTANCE_STATE); + add_sample(s,mem(5), BY_SOURCE_TIMESTAMP_DESTINATION_ORDER_QOS); + -- READER 5 + ind <= 5; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- MEM: I1S1(0), I1S2-(1), I4S2-(7), I1S3(9) + -- ISTATE: I1:ALIVE, I4:DISOSED + -- VIEW: I1:NEW, I4:NEW + -- WRITER: W0:I1, W2:I4 + + Log("Current Time: 4s", INFO); + check_time <= gen_duration(4 sec); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait_on_idle; + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh4; + cc.payload := gen_payload(kh4,10); + cc.src_timestamp := gen_duration(4 sec); + + Log("R5: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 4, Writer 2, Aligned Payload, ID 4]", INFO); + Log("R5: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 2; + rtps.ret_code := OK; + s := to_sample(cc,NOT_ALIVE_DISPOSED_INSTANCE_STATE); + add_sample(s,mem(5), BY_SOURCE_TIMESTAMP_DESTINATION_ORDER_QOS); + -- READER 5 + ind <= 5; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- MEM: I1S1(0), I1S2-(1), I4S1(4), I4S2-(7), I1S3(9) + -- ISTATE: I1:ALIVE, I4:DISOSED + -- VIEW: I1:NEW, I4:NEW + -- WRITER: W0:I1, W2:I4 + + -- TEST: OUT OF ORDER SAMPLE AFTER DISPOSE + + Log("R5: DDS Operation READ_INSTANCE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ALIVE_INSTANCE_STATE, ANY_VIEW_STATE, Instance 4]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := READ_INSTANCE; + dds.max_samples := 20; + dds.sstate := ANY_SAMPLE_STATE; + dds.istate := ALIVE_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + dds.inst := kh4; + dds.ret_code := RETCODE_NO_DATA; + -- READER 5 + Log("R5: No Data", DEBUG); + ind <= 5; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- MEM: I1S1(0), I1S2-(1), I4S1(4), I4S2-(7), I1S3(9) + -- ISTATE: I1:ALIVE, I4:DISOSED + -- VIEW: I1:NEW, I4:NEW + -- WRITER: W0:I1, W2:I4 + + Log("Current Time: 5s", INFO); + check_time <= gen_duration(5 sec); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait_on_idle; + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh3; + cc.payload := gen_payload(kh3,10); + cc.src_timestamp := gen_duration(3 sec); + + Log("R5: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 3, Writer 2, Aligned Payload, ID 3]", INFO); + Log("R5: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 2; + rtps.ret_code := OK; + s := to_sample(cc,ALIVE_INSTANCE_STATE); + add_sample(s,mem(5), BY_SOURCE_TIMESTAMP_DESTINATION_ORDER_QOS); + -- READER 5 + ind <= 5; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- MEM: I1S1(0), I1S2-(1), I3S1(3), I4S1(4), I4S2-(7), I1S3(9) + -- ISTATE: I1:ALIVE, I3:ALIVE, I4:DISOSED + -- VIEW: I1:NEW, I3:NEW, I4:NEW + -- WRITER: W0:I1, W2:I3,I4 + + Log("Current Time: 6s", INFO); + check_time <= gen_duration(6 sec); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait_on_idle; + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh2; + cc.payload := gen_payload(kh2,10); + cc.src_timestamp := gen_duration(2 sec); + + Log("R5: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 2, Writer 1, Aligned Payload, ID 2]", INFO); + Log("R5: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 1; + rtps.ret_code := OK; + s := to_sample(cc,ALIVE_INSTANCE_STATE); + add_sample(s,mem(5), BY_SOURCE_TIMESTAMP_DESTINATION_ORDER_QOS); + -- READER 5 + ind <= 5; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I4S2-(7), I1S3(9) + -- ISTATE: I1:ALIVE, I2:ALIVE, I3:ALIVE, I4:DISOSED + -- VIEW: I1:NEW, I2:NEW, I3:NEW, I4:NEW + -- WRITER: W0:I1, W2:I3,I4 + + Log("Current Time: 7s", INFO); + check_time <= gen_duration(7 sec); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait_on_idle; + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := TRUE; + cc.kind := NOT_ALIVE_DISPOSED; + cc.instance := kh2; + cc.payload := gen_payload(kh2,5); + cc.src_timestamp := gen_duration(5 sec); + + Log("R5: RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Instance 2, Writer 1, ID 5]", INFO); + Log("R5: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 1; + rtps.ret_code := OK; + s := to_sample(cc,NOT_ALIVE_DISPOSED_INSTANCE_STATE); + add_sample(s,mem(5), BY_SOURCE_TIMESTAMP_DESTINATION_ORDER_QOS); + -- READER 5 + ind <= 5; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I4S2-(7), I1S3(9) + -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:ALIVE, I4:DISOSED + -- VIEW: I1:NEW, I2:NEW, I3:NEW, I4:NEW + -- WRITER: W0:I1, W2:I3,I4 + + Log("Current Time: 8s", INFO); + check_time <= gen_duration(8 sec); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait_on_idle; + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := TRUE; + cc.kind := NOT_ALIVE_DISPOSED; + cc.instance := kh3; + cc.payload := gen_payload(kh3,5); + cc.src_timestamp := gen_duration(6 sec); + + Log("R5: RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Instance 3, Writer 2, ID 6]", INFO); + Log("R5: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 2; + rtps.ret_code := OK; + s := to_sample(cc,NOT_ALIVE_DISPOSED_INSTANCE_STATE); + add_sample(s,mem(5), BY_SOURCE_TIMESTAMP_DESTINATION_ORDER_QOS); + -- READER 5 + ind <= 5; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I1S3(9) + -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:DISOSED + -- VIEW: I1:NEW, I2:NEW, I3:NEW, I4:NEW + -- WRITER: W0:I1, W2:I3,I4 + + Log("Current Time: 9s", INFO); + check_time <= gen_duration(9 sec); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait_on_idle; + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh4; + cc.payload := gen_payload(kh4,10); + cc.src_timestamp := gen_duration(8 sec); + + Log("R5: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 4, Writer 2, Aligned Payload, ID 8]", INFO); + Log("R5: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 2; + rtps.ret_code := OK; + s := to_sample(cc,ALIVE_INSTANCE_STATE); + add_sample(s,mem(5), BY_SOURCE_TIMESTAMP_DESTINATION_ORDER_QOS); + -- READER 5 + ind <= 5; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9) + -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE + -- VIEW: I1:NEW, I2:NEW, I3:NEW, I4:NEW + -- WRITER: W0:I1, W2:I3,I4 + + Log("Current Time: 10s", INFO); + check_time <= gen_duration(10 sec); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait_on_idle; + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh2; + cc.payload := gen_payload(kh2,10); + cc.src_timestamp := gen_duration(10 sec); + + Log("R5: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 2, Writer 1, Aligned Payload, ID 10]", INFO); + Log("R5: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 1; + rtps.ret_code := OK; + s := to_sample(cc,ALIVE_INSTANCE_STATE); + add_sample(s,mem(5), BY_SOURCE_TIMESTAMP_DESTINATION_ORDER_QOS); + -- READER 5 + ind <= 5; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10) + -- ISTATE: I1:ALIVE, I2:ALIVE, I3:DISPOSED, I4:ALIVE + -- VIEW: I1:NEW, I2:NEW, I3:NEW, I4:NEW + -- WRITER: W0:I1, W2:I3,I4 + + Log("Current Time: 11s", INFO); + check_time <= gen_duration(11 sec); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait_on_idle; + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := TRUE; + cc.kind := NOT_ALIVE_DISPOSED; + cc.instance := kh2; + cc.payload := gen_payload(kh2,5); + cc.src_timestamp := gen_duration(11 sec); + + Log("R5: RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Instance 2, Writer 1, ID 11]", INFO); + Log("R5: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 1; + rtps.ret_code := OK; + s := to_sample(cc,NOT_ALIVE_DISPOSED_INSTANCE_STATE); + add_sample(s,mem(5), BY_SOURCE_TIMESTAMP_DESTINATION_ORDER_QOS); + -- READER 5 + ind <= 5; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) + -- ISTATE: I1:ALIVE, I2:DISPSOED, I3:DISPOSED, I4:ALIVE + -- VIEW: I1:NEW, I2:NEW, I3:NEW, I4:NEW + -- WRITER: W0:I1, W2:I3,I4 + + -- TEST: READ [MAX_SAMPLES < SAMPLES] + -- TEST: READ [ANY SSTATE, ANY ISTATE, ANY VIEW] + + Log("R5: DDS Operation READ [MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := READ; + dds.max_samples := 3; + dds.sstate := ANY_SAMPLE_STATE; + dds.istate := ANY_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + -- READER 5 + Log("R5: Expected ID0,ID1,ID2", DEBUG); + ind <= 5; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) + -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE + -- VIEW: I1:NEW, I2:NEW, I3:NEW, I4:NEW + -- WRITER: W0:I1, W1:I2, W2:I3,I4 + + -- TEST: READ MARKS SAMPLES AS READ + -- TEST: READ_NEXT_SAMPLE [WITH UNREAD SAMPLE] + + Log("R5: DDS Operation READ_NEXT_SAMPLE", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := READ_NEXT_SAMPLE; + -- READER 5 + Log("R5: Expected ID3", DEBUG); + ind <= 5; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) + -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE + -- VIEW: I1:NEW, I2:NEW, I3:NOT_NEW, I4:NEW + -- WRITER: W0:I1, W1:I2, W2:I3,I4 + + -- TEST: READ_INSTANCE [KNOWN INSTANCE, COMPATIBLE SAMPLES] + + Log("R5: DDS Operation READ_INSTANCE [MAX_SAMPLES 1, NOT_READ_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Instance 3]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := READ_INSTANCE; + dds.max_samples := 1; + dds.sstate := NOT_READ_SAMPLE_STATE; + dds.istate := ANY_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + dds.inst := kh1; + -- READER 5 + Log("R5: Expected ID9", DEBUG); + ind <= 5; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) + -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE + -- VIEW: I1:NOT_NEW, I2:NEW, I3:NOT_NEW, I4:NEW + -- WRITER: W0:I1, W1:I2, W2:I3,I4 + + -- TEST: READ_NEXT_INSTANCE [WITH NEXT INSTANCE, COMPATIBLE SAMPLES] + + Log("R5: DDS Operation READ_NEXT_INSTANCE [MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Instance 3]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := READ_NEXT_INSTANCE; + dds.max_samples := 1; + dds.sstate := ANY_SAMPLE_STATE; + dds.istate := ANY_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + dds.inst := kh3; + -- READER 5 + Log("R5: Expected ID4", DEBUG); + ind <= 5; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) + -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE + -- VIEW: I1:NOT_NEW, I2:NEW, I3:NOT_NEW, I4:NEW + -- WRITER: W0:I1, W1:I2, W2:I3,I4 + + -- TEST: READ [SPECIFIED SSTATE, ANY ISTATE, ANY VIEW] + -- TEST: READ [MAX_SAMPLES > SAMPLES] + + Log("R5: DDS Operation READ [MAX_SAMPLES 20, READ_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := READ; + dds.max_samples := 20; + dds.sstate := READ_SAMPLE_STATE; + dds.istate := ANY_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + -- READER 5 + Log("R5: Expected ID0,ID1,ID2,ID3,ID4,ID9", DEBUG); + ind <= 5; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) + -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE + -- VIEW: I1:NOT_NEW, I2:NEW, I3:NOT_NEW, I4:NEW + -- WRITER: W0:I1, W1:I2, W2:I3,I4 + + -- TEST: READ [SPECIFIED SSTATE, SPECIFIED ISTATE, ANY VIEW] + + Log("R5: DDS Operation READ [MAX_SAMPLES 20, READ_SAMPLE_STATE, NOT_ALIVE_DISPOSED_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := READ; + dds.max_samples := 20; + dds.sstate := READ_SAMPLE_STATE; + dds.istate := NOT_ALIVE_DISPOSED_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + -- READER 5 + Log("R5: Expected ID2,ID3", DEBUG); + ind <= 5; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) + -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE + -- VIEW: I1:NOT_NEW, I2:NEW, I3:NOT_NEW, I4:NEW + -- WRITER: W0:I1, W1:I2, W2:I3,I4 + + -- TEST: READ [SPECIFIED SSTATE, ANY ISTATE, SPECIFIED VIEW] + -- TEST: READ MODIFIES VIEW STATE [READ CURRENT GENERATION] + -- TEST: READ MODIFIES VIEW STATE [READ PREVIOUS GENERATION] + + Log("R5: DDS Operation READ [MAX_SAMPLES 20, READ_SAMPLE_STATE, ANY_INSTANCE_STATE, NEW_VIEW_STATE]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := READ; + dds.max_samples := 20; + dds.sstate := READ_SAMPLE_STATE; + dds.istate := ANY_INSTANCE_STATE; + dds.vstate := NEW_VIEW_STATE; + -- READER 5 + Log("R5: Expected ID2,ID4", DEBUG); + ind <= 5; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) + -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE + -- VIEW: I1:NOT_NEW, I2:NEW, I3:NOT_NEW, I4:NEW + -- WRITER: W0:I1, W1:I2, W2:I3,I4 + + -- TEST: READ [SPECIFIED SSTATE, SPECIFIED ISTATE, SPECIFIED VIEW] + + Log("R5: DDS Operation READ [MAX_SAMPLES 20, READ_SAMPLE_STATE, NOT_ALIVE_DISPOSED_INSTANCE_STATE, NEW_VIEW_STATE]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := READ; + dds.max_samples := 20; + dds.sstate := READ_SAMPLE_STATE; + dds.istate := NOT_ALIVE_DISPOSED_INSTANCE_STATE; + dds.vstate := NEW_VIEW_STATE; + -- READER 5 + Log("R5: Expected ID2", DEBUG); + ind <= 5; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) + -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE + -- VIEW: I1:NOT_NEW, I2:NEW, I3:NOT_NEW, I4:NEW + -- WRITER: W0:I1, W1:I2, W2:I3,I4 + + -- TEST: READ [ANY SSTATE, ANY ISTATE, SPECIFIED VIEW] + + Log("R5: DDS Operation READ [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, NOT_NEW_VIEW_STATE]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := READ; + dds.max_samples := 20; + dds.sstate := ANY_SAMPLE_STATE; + dds.istate := ANY_INSTANCE_STATE; + dds.vstate := NOT_NEW_VIEW_STATE; + -- READER 5 + Log("R5: Expected ID0,ID1,ID3,ID6,ID9", DEBUG); + ind <= 5; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) + -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE + -- VIEW: I1:NOT_NEW, I2:NEW, I3:NOT_NEW, I4:NEW + -- WRITER: W0:I1, W1:I2, W2:I3,I4 + + -- TEST: READ [ANY SSTATE, SPECIFIED ISTATE, SPECIFIED VIEW] + + Log("R5: DDS Operation READ [MAX_SAMPLES 20, ANY_SAMPLE_STATE, NOT_ALIVE_DISPOSED_INSTANCE_STATE, NOT_NEW_VIEW_STATE]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := READ; + dds.max_samples := 20; + dds.sstate := ANY_SAMPLE_STATE; + dds.istate := NOT_ALIVE_DISPOSED_INSTANCE_STATE; + dds.vstate := NOT_NEW_VIEW_STATE; + -- READER 5 + Log("R5: Expected ID3,ID6", DEBUG); + ind <= 5; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) + -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE + -- VIEW: I1:NOT_NEW, I2:NEW, I3:NOT_NEW, I4:NEW + -- WRITER: W0:I1, W1:I2, W2:I3,I4 + + -- TEST: READ [ANY SSTATE, SPECIFIED ISTATE, ANY VIEW] + + Log("R5: DDS Operation READ [MAX_SAMPLES 20, ANY_SAMPLE_STATE, NOT_ALIVE_DISPOSED_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := READ; + dds.max_samples := 20; + dds.sstate := ANY_SAMPLE_STATE; + dds.istate := NOT_ALIVE_DISPOSED_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + -- READER 5 + Log("R5: Expected ID2,ID3,ID5,ID6,ID10,ID11", DEBUG); + ind <= 5; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) + -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE + -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NEW + -- WRITER: W0:I1, W1:I2, W2:I3,I4 + + -- TEST: READ_INSTANCE [UNKNOWN INSTANCE] + + Log("R5: DDS Operation READ_INSTANCE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Unknown Instance]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := READ_INSTANCE; + dds.max_samples := 20; + dds.sstate := ANY_SAMPLE_STATE; + dds.istate := ANY_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + dds.inst := kh5; + dds.ret_code := RETCODE_BAD_PARAMETER; + -- READER 5 + Log("R5: Bad Parameter", DEBUG); + ind <= 5; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) + -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE + -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NEW + -- WRITER: W0:I1, W1:I2, W2:I3,I4 + + -- TEST: READ_INSTANCE [KNOWN INSTANCE, UNCOMPATIBLE SAMPLES] + + Log("R5: DDS Operation READ_INSTANCE [MAX_SAMPLES 20, NOT_READ_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Instance 1]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := READ_INSTANCE; + dds.max_samples := 20; + dds.sstate := NOT_READ_SAMPLE_STATE; + dds.istate := ANY_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + dds.inst := kh1; + dds.ret_code := RETCODE_NO_DATA; + -- READER 5 + Log("R5: No Data", DEBUG); + ind <= 5; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) + -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE + -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NEW + -- WRITER: W0:I1, W1:I2, W2:I3,I4 + + -- TEST: READ_NEXT_INSTANCE [WITH NEXT INSTANCE, UNCOMPATIBLE SAMPLES] + + Log("R5: DDS Operation READ_NEXT_INSTANCE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, NOT_ALIVE_DISPOSED_INSTANCE_STATE, ANY_VIEW_STATE, Instance 2]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := READ_NEXT_INSTANCE; + dds.max_samples := 20; + dds.sstate := ANY_SAMPLE_STATE; + dds.istate := NOT_ALIVE_DISPOSED_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + dds.inst := kh2; + dds.ret_code := RETCODE_NO_DATA; + -- READER 5 + Log("R5: No Data", DEBUG); + ind <= 5; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) + -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE + -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NEW + -- WRITER: W0:I1, W1:I2, W2:I3,I4 + + -- TEST: READ_NEXT_INSTANCE [WITH NEXT INSTANCE, WITH COMPATIBLE SAMPLE, NOT DIRECT NEXT INSTANCE] + + Log("R5: DDS Operation READ_NEXT_INSTANCE [MAX_SAMPLES 20, NOT_READ_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Instance 3]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := READ_NEXT_INSTANCE; + dds.max_samples := 20; + dds.sstate := NOT_READ_SAMPLE_STATE; + dds.istate := ANY_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + dds.inst := kh3; + dds.ret_code := RETCODE_OK; + -- READER 5 + Log("R5: Expected ID7,ID8", DEBUG); + ind <= 5; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) + -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE + -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW + -- WRITER: W0:I1, W1:I2, W2:I3,I4 + + -- TEST: READ [NO COMPATIBLE SAMPLES] + + Log("R5: DDS Operation READ [MAX_SAMPLES 20, ANY_SAMPLE_STATE, NOT_ALIVE_NO_WRITERS_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := READ; + dds.max_samples := 20; + dds.sstate := ANY_SAMPLE_STATE; + dds.istate := NOT_ALIVE_NO_WRITERS_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + dds.ret_code := RETCODE_NO_DATA; + -- READER 5 + Log("R5: No Data", DEBUG); + ind <= 5; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) + -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE + -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW + -- WRITER: W0:I1, W1:I2, W2:I3,I4 + + -- TEST: READ_NEXT_SAMPLE [WITHOUT UNREAD SAMPLE] + + Log("R5: DDS Operation READ_NEXT_SAMPLE", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := READ_NEXT_SAMPLE; + dds.ret_code := RETCODE_NO_DATA; + -- READER 5 + Log("R5: No Data", DEBUG); + ind <= 5; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) + -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE + -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW + -- WRITER: W0:I1, W1:I2, W2:I3,I4 + + -- TEST: TAKE + + Log("R5: DDS Operation TAKE [MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := TAKE; + dds.max_samples := 1; + dds.sstate := ANY_SAMPLE_STATE; + dds.istate := ANY_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + dds.ret_code := RETCODE_OK; + -- READER 5 + Log("R5: Expected ID0", DEBUG); + ind <= 5; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- MEM: I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) + -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE + -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW + -- WRITER: W0:I1, W1:I2, W2:I3,I4 + + -- TEST: TAKE_INSTANCE + + Log("R5: DDS Operation TAKE_INSTANCE [MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Instance 2]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := TAKE_INSTANCE; + dds.max_samples := 1; + dds.sstate := ANY_SAMPLE_STATE; + dds.istate := ANY_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + dds.inst := kh2; + dds.ret_code := RETCODE_OK; + -- READER 5 + Log("R5: Expected ID2", DEBUG); + ind <= 5; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- MEM: I1S2-(1), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) + -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE + -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW + -- WRITER: W0:I1, W1:I2, W2:I3,I4 + + -- TEST: TAKE_NEXT_INSTANCE + -- TEST: READ_NEXT_INSTANCE [HANDLE_NIL] + + Log("R5: DDS Operation TAKE_NEXT_INSTANCE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, HANDLE_NIL]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := TAKE_NEXT_INSTANCE; + dds.max_samples := 20; + dds.sstate := ANY_SAMPLE_STATE; + dds.istate := ANY_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + dds.inst := HANDLE_NIL; + dds.ret_code := RETCODE_OK; + -- READER 5 + Log("R5: Expected ID3,ID6", DEBUG); + ind <= 5; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- MEM: I1S2-(1), I4S1(4), I2S2-(5), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) + -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE + -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW + -- WRITER: W0:I1, W1:I2, W2:I3,I4 + + -- TEST: TAKE REMOVES SAMPLE + -- TEST: READ_INSTANCE [NO SAMPLES] + + Log("R5: DDS Operation READ_INSTANCE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Instance 3]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := READ_INSTANCE; + dds.max_samples := 20; + dds.sstate := ANY_SAMPLE_STATE; + dds.istate := ANY_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + dds.inst := kh3; + dds.ret_code := RETCODE_NO_DATA; + -- READER 5 + Log("R5: No Data", DEBUG); + ind <= 5; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- MEM: I1S2-(1), I4S1(4), I2S2-(5), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) + -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE + -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW + -- WRITER: W0:I1, W1:I2, W2:I3,I4 + + Log("R5: DDS Operation TAKE_NEXT_INSTANCE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Instance 3]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := TAKE_NEXT_INSTANCE; + dds.max_samples := 20; + dds.sstate := ANY_SAMPLE_STATE; + dds.istate := ANY_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + dds.inst := kh3; + dds.ret_code := RETCODE_OK; + -- READER 5 + Log("R5: Expected ID4,ID7,ID8", DEBUG); + ind <= 5; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- MEM: I1S2-(1), I2S2-(5), I1S3(9), I2S3(10), I2S4-(11) + -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE + -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW + -- WRITER: W0:I1, W1:I2, W2:I3,I4 + + -- TEST: TAKE_INSTANCE [NO SAMPLES] + + Log("R5: DDS Operation TAKE_INSTANCE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Instance 4]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := TAKE_INSTANCE; + dds.max_samples := 20; + dds.sstate := ANY_SAMPLE_STATE; + dds.istate := ANY_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + dds.inst := kh4; + dds.ret_code := RETCODE_NO_DATA; + -- READER 5 + Log("R5: No Data", DEBUG); + ind <= 5; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- MEM: I1S2-(1), I2S2-(5), I1S3(9), I2S3(10), I2S4-(11) + -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE + -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW + -- WRITER: W0:I1, W1:I2, W2:I3,I4 + + Log("R5: DDS Operation TAKE_NEXT_INSTANCE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Instance 4]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := TAKE_NEXT_INSTANCE; + dds.max_samples := 20; + dds.sstate := ANY_SAMPLE_STATE; + dds.istate := ANY_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + dds.inst := kh4; + dds.ret_code := RETCODE_OK; + -- READER 5 + Log("R5: Expected ID5,ID10,ID11", DEBUG); + ind <= 5; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- MEM: I1S2-(1), I1S3(9) + -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE + -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW + -- WRITER: W0:I1, W1:I2, W2:I3,I4 + + Log("R5: DDS Operation READ_INSTANCE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Instance 2]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := READ_INSTANCE; + dds.max_samples := 20; + dds.sstate := ANY_SAMPLE_STATE; + dds.istate := ANY_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + dds.inst := kh2; + dds.ret_code := RETCODE_NO_DATA; + -- READER 5 + Log("R5: No Data", DEBUG); + ind <= 5; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- MEM: I1S2-(1), I1S3(9) + -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE + -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW + -- WRITER: W0:I1, W1:I2, W2:I3,I4 + + -- TEST: READ_NEXT_INSTANCE [WITH SAMPLES, WITHOUT NEXT INSTANCE] + + Log("R5: DDS Operation READ_NEXT_INSTANCE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Instance 1]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := READ_NEXT_INSTANCE; + dds.max_samples := 20; + dds.sstate := ANY_SAMPLE_STATE; + dds.istate := ANY_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + dds.inst := kh1; + dds.ret_code := RETCODE_NO_DATA; + -- READER 5 + Log("R5: No Data", DEBUG); + ind <= 5; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- MEM: I1S2-(1), I1S3(9) + -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE + -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW + -- WRITER: W0:I1, W1:I2, W2:I3,I4 + + Log("R5: DDS Operation TAKE_NEXT_INSTANCE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Instance 2]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := TAKE_NEXT_INSTANCE; + dds.max_samples := 20; + dds.sstate := ANY_SAMPLE_STATE; + dds.istate := ANY_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + dds.inst := kh2; + dds.ret_code := RETCODE_OK; + -- READER 5 + Log("R5: Expected ID1,ID9", DEBUG); + ind <= 5; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- MEM: - + -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE + -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW + -- WRITER: W0:I1, W1:I2, W2:I3,I4 + + -- TEST: GET ALL DATA WITH READ_NEXT_INSTANCE + -- TEST: READ [NO SAMPLES] + + Log("R5: DDS Operation READ [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := READ; + dds.max_samples := 20; + dds.sstate := ANY_SAMPLE_STATE; + dds.istate := ANY_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + dds.ret_code := RETCODE_NO_DATA; + -- READER 5 + Log("R5: No Data", DEBUG); + ind <= 5; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- MEM: - + -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE + -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW + -- WRITER: W0:I1, W1:I2, W2:I3,I4 + + -- TEST: TAKE [NO SAMPLES] + + Log("R5: DDS Operation TAKE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := TAKE; + dds.max_samples := 20; + dds.sstate := ANY_SAMPLE_STATE; + dds.istate := ANY_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + dds.ret_code := RETCODE_NO_DATA; + -- READER 5 + Log("R5: No Data", DEBUG); + ind <= 5; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- MEM: - + -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE + -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW + -- WRITER: W0:I1, W1:I2, W2:I3,I4 + + -- TEST: READ_NEXT_INSTANCE [NO SAMPLE] + + Log("R5: DDS Operation READ_NEXT_INSTANCE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, HANDLE_NIL]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := READ_NEXT_INSTANCE; + dds.max_samples := 20; + dds.sstate := ANY_SAMPLE_STATE; + dds.istate := ANY_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + dds.inst := HANDLE_NIL; + dds.ret_code := RETCODE_NO_DATA; + -- READER 5 + Log("R5: No Data", DEBUG); + ind <= 5; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- MEM: - + -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE + -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW + -- WRITER: W0:I1, W1:I2, W2:I3,I4 + + -- TEST: TAKE_NEXT_INSTANCE [NO SAMPLE] + + Log("R5: DDS Operation TAKE_NEXT_INSTANCE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, HANDLE_NIL]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := TAKE_NEXT_INSTANCE; + dds.max_samples := 20; + dds.sstate := ANY_SAMPLE_STATE; + dds.istate := ANY_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + dds.inst := HANDLE_NIL; + dds.ret_code := RETCODE_NO_DATA; + -- READER 5 + ind <= 5; + Log("R5: No Data", DEBUG); + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- MEM: - + -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE + -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW + -- WRITER: W0:I1, W1:I2, W2:I3,I4 + + -- TEST: READ_NEXT_SAMPLE [NO SAMPLE] + + Log("R5: DDS Operation READ_NEXT_SAMPLE", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := READ_NEXT_SAMPLE; + dds.ret_code := RETCODE_NO_DATA; + -- READER 5 + Log("R5: No Data", DEBUG); + ind <= 5; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- MEM: - + -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE + -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW + -- WRITER: W0:I1, W1:I2, W2:I3,I4 + + -- TEST: TAKE_NEXT_SAMPLE [NO SAMPLE] + + Log("R5: DDS Operation TAKE_NEXT_SAMPLE", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := TAKE_NEXT_SAMPLE; + dds.ret_code := RETCODE_NO_DATA; + -- READER 5 + Log("R5: No Data", DEBUG); + ind <= 5; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- MEM: - + -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE + -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW + -- WRITER: W0:I1, W1:I2, W2:I3,I4 + + Log("Current Time: 12s", INFO); + check_time <= gen_duration(12 sec); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait_on_idle; + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh2; + cc.payload := gen_payload(kh2,10); + cc.src_timestamp := gen_duration(12 sec); + + Log("R5: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 2, Writer 1, Aligned Payload, ID 12]", INFO); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 1; + rtps.ret_code := OK; + s := to_sample(cc,ALIVE_INSTANCE_STATE); + add_sample(s,mem(5), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + -- READER 5 + Log("R5: ACCEPTED", DEBUG); + ind <= 5; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- MEM: I2S5(12) + -- ISTATE: I1:ALIVE, I2:ALIVE, I3:DISPOSED, I4:ALIVE + -- VIEW: I1:NOT_NEW, I2:NEW, I3:NOT_NEW, I4:NOT_NEW + -- WRITER: W0:I1, W1:I2, W2:I3,I4 + + -- TEST: TAKE_NEXT_SAMPLE + + Log("R5: DDS Operation TAKE_NEXT_SAMPLE", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := TAKE_NEXT_SAMPLE; + dds.ret_code := RETCODE_OK; + -- READER 5 + Log("R5: Expected ID12", DEBUG); + ind <= 5; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- MEM: - + -- ISTATE: I1:ALIVE, I2:ALIVE, I3:DISPOSED, I4:ALIVE + -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW + -- WRITER: W0:I1, W1:I2, W2:I3,I4 + + Log("R5: DDS Operation READ [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := READ; + dds.max_samples := 20; + dds.sstate := ANY_SAMPLE_STATE; + dds.istate := ANY_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + dds.ret_code := RETCODE_NO_DATA; + -- READER 5 + Log("R5: No Data", DEBUG); + ind <= 5; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- MEM: - + -- ISTATE: I1:ALIVE, I2:ALIVE, I3:DISPOSED, I4:ALIVE + -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW + -- WRITER: W0:I1, W1:I2, W2:I3,I4 + + wait_on_completion; + TranscriptOpen(RESULTS_FILE, APPEND_MODE); + SetTranscriptMirror; + ReportAlerts; + TranscriptClose; + std.env.stop; + wait; + end process; + + clock_prc : process + begin + clk <= '0'; + wait for 25 ns; + clk <= '1'; + wait for 25 ns; + end process; + + dds_prc : process(all) + variable col : COLLECTION_TYPE := DEFAULT_COLLECTION; + begin + if rising_edge(clk) then + dds_done <= '0'; + case (dds_stage ) is + when IDLE => + if (dds_start = '1') then + dds_stage <= START; + else + dds_done <= '1'; + end if; + when START => + if (ack_dds(ind) = '1') then + dds_stage <= DONE; + dds_cnt <= 0; + end if; + when DONE => + if (done_dds(ind) = '1') then + AffirmIfEqual(ret_id, return_code_dds(ind), dds.ret_code); + case (dds.ret_code) is + when RETCODE_OK => + gen_collection(mem(ind), col, dds, TEST_CONFIG(ind).PRESENTATION_QOS, TEST_CONFIG(ind).ORDERED_ACCESS); + dds_stage <= CHECK_SI; + dds_cnt <= 0; + when others => + dds_stage <= IDLE; + end case; + end if; + when CHECK_SI => + if (si_valid(ind) = '1') then + Log("Read Sample ID" & to_string(to_integer(sample_info(ind).source_timestamp(0))), DEBUG); + AffirmIfEqual(sstate_id, sample_info(ind).sample_state, col.s(dds_cnt).sstate); + AffirmIfEqual(vstate_id, sample_info(ind).view_state, col.s(dds_cnt).vstate); + AffirmIfEqual(istate_id, sample_info(ind).instance_state, col.s(dds_cnt).istate); + AffirmIfEqual(ts_id, to_unsigned(sample_info(ind).source_timestamp), to_unsigned(col.s(dds_cnt).ts)); + AffirmIfEqual(inst_id, to_unsigned(sample_info(ind).instance_handle), to_unsigned(col.s(dds_cnt).inst)); + AffirmIfEqual(pub_id, to_unsigned(sample_info(ind).publication_handle), to_unsigned(HANDLE_NIL)); + AffirmIfEqual(dis_gen_cnt_id, sample_info(ind).disposed_generation_count, std_logic_vector(to_unsigned(col.s(dds_cnt).dis_gen_cnt,WORD_WIDTH))); + AffirmIfEqual(no_w_gen_cnt_id, sample_info(ind).no_writers_generation_count, std_logic_vector(to_unsigned(col.s(dds_cnt).no_w_gen_cnt,WORD_WIDTH))); + AffirmIfEqual(srank_id, sample_info(ind).sample_rank, std_logic_vector(to_unsigned(col.s(dds_cnt).srank,WORD_WIDTH))); + AffirmIfEqual(grank_id, sample_info(ind).generation_rank, std_logic_vector(to_unsigned(col.s(dds_cnt).grank,WORD_WIDTH))); + AffirmIfEqual(agrank_id, sample_info(ind).absolute_generation_rank, std_logic_vector(to_unsigned(col.s(dds_cnt).agrank,WORD_WIDTH))); + if (sample_info(ind).valid_data = '1') then + AffirmIf(valid_id, col.s(dds_cnt).data /= EMPTY_TEST_PACKET, "Sample with Data not expected"); + dds_stage <= CHECK_DATA; + dds_cnt2 <= 0; + else + AffirmIf(valid_id, col.s(dds_cnt).data = EMPTY_TEST_PACKET, "Sample with Data expected"); + if (dds_cnt = col.len-1) then + -- DONE + dds_stage <= WAIT_EOC; + else + dds_cnt <= dds_cnt + 1; + end if; + end if; + end if; + AffirmIf(eoc_id, eoc(ind) = '0', "EOC pulled high"); + when CHECK_DATA => + if (valid_out_dds(ind) = '1') then + AffirmIfEqual(data_id, data_out_dds(ind), col.s(dds_cnt).data.data(dds_cnt2)); + dds_cnt2 <= dds_cnt2 + 1; + if (dds_cnt2 = col.s(dds_cnt).data.length-1) then + AlertIf(data_id, last_word_out_dds(ind) /= '1', "Last Word Signal not pulled High", ERROR); + if (dds_cnt = col.len-1) then + -- DONE + dds_stage <= WAIT_EOC; + else + dds_stage <= CHECK_SI; + dds_cnt <= dds_cnt + 1; + end if; + end if; + end if; + when WAIT_EOC => + if (eoc(ind) = '1') then + dds_stage <= IDLE; + end if; + end case; + end if; + + -- DEFAULT + start_dds <= (others => '0'); + opcode_dds <= (others => NOP); + instance_state_dds <= (others => ANY_INSTANCE_STATE); + view_state_dds <= (others => ANY_VIEW_STATE); + sample_state_dds <= (others => ANY_SAMPLE_STATE); + instance_handle_dds <= (others => HANDLE_NIL); + max_samples_dds <= (others => (others => '0')); + get_data_dds <= (others => '0'); + ready_out_dds <= (others => '0'); + + + case (dds_stage ) is + when START => + start_dds(ind) <= '1'; + opcode_dds(ind) <= dds.opcode; + instance_state_dds(ind) <= dds.istate; + view_state_dds(ind) <= dds.vstate; + sample_state_dds(ind) <= dds.sstate; + instance_handle_dds(ind) <= dds.inst; + max_samples_dds(ind) <= std_logic_vector(to_unsigned(dds.max_samples, WORD_WIDTH)); + when CHECK_SI => + if (si_valid(ind) = '1' and sample_info(ind).valid_data = '1') then + get_data_dds(ind) <= '1'; + end if; + when CHECK_DATA => + ready_out_dds(ind) <= '1'; + when others => + null; + end case; + end process; + + rtps_prc : process(all) + variable stimulus : TEST_PACKET_TYPE := EMPTY_TEST_PACKET; + begin + if rising_edge(clk) then + rtps_done <= '0'; + case (rtps_stage) is + when IDLE => + if (rtps_start = '1') then + rtps_stage <= START; + else + rtps_done <= '1'; + end if; + when START => + if (ack_rtps(ind) = '1') then + case (rtps.opcode) is + when ADD_CACHE_CHANGE => + gen_add_cache_change_dds(rtps.cc, rtps.lifespan, rtps.writer_pos, stimulus); + rtps_stage <= PUSH; + when others => + rtps_stage <= DONE; + end case; + end if; + when PUSH => + if (ready_in_rtps(ind) = '1') then + rtps_cnt <= rtps_cnt + 1; + if (rtps_cnt = stimulus.length-1) then + rtps_stage <= DONE; + end if; + end if; + when DONE => + if (done_rtps(ind) = '1') then + AffirmIfEqual(ret_id, HISTORY_CACHE_RESPONSE_TYPE'pos(ret_rtps(ind)), HISTORY_CACHE_RESPONSE_TYPE'pos(rtps.ret_code)); + rtps_stage <= IDLE; + end if; + end case; + end if; + + -- DEFAULT + start_rtps <= (others => '0'); + opcode_rtps <= (others => NOP); + valid_in_rtps <= (others => '0'); + last_word_in_rtps <= (others => '0'); + data_in_rtps <= (others => (others => '0')); + + case (rtps_stage) is + when START => + start_rtps(ind) <= '1'; + opcode_rtps(ind) <= rtps.opcode; + case (rtps.opcode) is + when REMOVE_WRITER => + data_in_rtps(ind) <= std_logic_vector(to_unsigned(rtps.writer_pos,WORD_WIDTH)); + when others => + null; + end case; + when PUSH => + valid_in_rtps(ind) <= '1'; + data_in_rtps(ind) <= stimulus.data(rtps_cnt); + last_word_in_rtps(ind) <= stimulus.last(rtps_cnt); + when others => + null; + end case; + end process; + + watchdog : process + begin + wait for 2 ms; + Alert("Test timeout", FAILURE); + std.env.stop; + end process; + +end architecture; \ No newline at end of file diff --git a/src/Tests/Level_0/L0_dds_reader_test3_arzkrio.vhd b/src/Tests/Level_0/L0_dds_reader_test3_arzkrio.vhd deleted file mode 100644 index 6a77272..0000000 --- a/src/Tests/Level_0/L0_dds_reader_test3_arzkrio.vhd +++ /dev/null @@ -1,1482 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library osvvm; -- Utility Library -context osvvm.OsvvmContext; - -use work.rtps_package.all; -use work.user_config.all; -use work.rtps_config_package.all; -use work.rtps_test_package.all; - --- This testbench tests the DDS handling of the DDS Reader. It tests the correctness of the DDS READ, TAKE, READ_NEXT_SAMPLE, TAKE_NEXT_SAMPLE, --- READ_INSTANCE, TAKE_INSTANCE, READ_NEXT_INSTANCE, TAKE_NEXT_INSTANCE Operations. --- More specifically the testbench covers following tests: --- TEST: READ [NO COMPATIBLE SAMPLES] --- TEST: READ [NO SAMPLES] --- TEST: READ [MAX_SAMPLES < SAMPLES] --- TEST: READ [MAX_SAMPLES > SAMPLES] --- TEST: TAKE [NO SAMPLES] --- TEST: TAKE --- TEST: READ [ANY SSTATE, ANY ISTATE, ANY VIEW] --- TEST: READ [ANY SSTATE, ANY ISTATE, SPECIFIED VIEW] --- TEST: READ [ANY SSTATE, SPECIFIED ISTATE, ANY VIEW] --- TEST: READ [ANY SSTATE, SPECIFIED ISTATE, SPECIFIED VIEW] --- TEST: READ [SPECIFIED SSTATE, ANY ISTATE, ANY VIEW] --- TEST: READ [SPECIFIED SSTATE, ANY ISTATE, SPECIFIED VIEW] --- TEST: READ [SPECIFIED SSTATE, SPECIFIED ISTATE, ANY VIEW] --- TEST: READ [SPECIFIED SSTATE, SPECIFIED ISTATE, SPECIFIED VIEW] --- TEST: READ_NEXT_SAMPLE [WITH UNREAD SAMPLE] --- TEST: READ_NEXT_SAMPLE [WITHOUT UNREAD SAMPLE] --- TEST: READ_NEXT_SAMPLE [NO SAMPLE] --- TEST: TAKE_NEXT_SAMPLE [NO SAMPLE] --- TEST: TAKE_NEXT_SAMPLE --- TEST: READ_INSTANCE [UNKNOWN INSTANCE] --- TEST: READ_INSTANCE [KNOWN INSTANCE, UNCOMPATIBLE SAMPLES] --- TEST: READ_INSTANCE [KNOWN INSTANCE, COMPATIBLE SAMPLES] --- TEST: READ_INSTANCE [NO SAMPLES] --- TEST: TAKE_INSTANCE [NO SAMPLES] --- TEST: TAKE_INSTANCE --- TEST: READ_NEXT_INSTANCE [WITH SAMPLES, WITHOUT NEXT INSTANCE] --- TEST: READ_NEXT_INSTANCE [WITH NEXT INSTANCE, UNCOMPATIBLE SAMPLES] --- TEST: READ_NEXT_INSTANCE [WITH NEXT INSTANCE, COMPATIBLE SAMPLES] --- TEST: READ_NEXT_INSTANCE [HANDLE_NIL] --- TEST: READ_NEXT_INSTANCE [WITH NEXT INSTANCE, WITH COMPATIBLE SAMPLE, NOT DIRECT NEXT INSTANCE] --- TEST: READ_NEXT_INSTANCE [NO SAMPLE] --- TEST: TAKE_NEXT_INSTANCE [NO SAMPLE] --- TEST: TAKE_NEXT_INSTANCE --- TEST: GET ALL DATA WITH READ_NEXT_INSTANCE --- TEST: READ MARKS SAMPLES AS READ --- TEST: TAKE REMOVES SAMPLE --- TEST: READ MODIFIES VIEW STATE [READ PREVIOUS GENERATION] --- TEST: READ MODIFIES VIEW STATE [READ CURRENT GENERATION] - -entity L0_dds_reader_test3_arzkrio is -end entity; - - -architecture testbench of L0_dds_reader_test3_arzkrio is - - -- *CONSTANT DECLARATION* - constant MAX_REMOTE_ENDPOINTS : natural := 3; - - -- *TYPE DECLARATION* - type DDS_STAGE_TYPE is (IDLE, START, DONE, CHECK_SI, CHECK_DATA, WAIT_EOC); - type RTPS_STAGE_TYPE is (IDLE, START, PUSH, DONE); - - -- *SIGNAL DECLARATION* - signal clk : std_logic := '0'; - signal reset : std_logic := '1'; - signal check_time : TIME_TYPE := TIME_ZERO; - signal start_rtps, start_dds, ack_rtps, ack_dds, done_rtps, done_dds : std_logic := '0'; - signal opcode_rtps : HISTORY_CACHE_OPCODE_TYPE := NOP; - signal opcode_dds : DDS_READER_OPCODE_TYPE := NOP; - signal ret_rtps : HISTORY_CACHE_RESPONSE_TYPE := ERROR; - signal ready_in_rtps, valid_in_rtps, last_word_in_rtps : std_logic := '0'; - signal ready_out_dds, valid_out_dds, last_word_out_dds : std_logic := '0'; - signal data_in_rtps, data_out_dds : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); - signal get_data_dds, si_valid_data, si_valid, eoc : std_logic := '0'; - signal return_code_dds : std_logic_vector(RETURN_CODE_WIDTH-1 downto 0) := (others => '0'); - signal status : std_logic_vector(STATUS_KIND_WIDTH-1 downto 0) := (others => '0'); - signal instance_state_dds, si_instance_state : std_logic_vector(INSTANCE_STATE_KIND_WIDTH-1 downto 0) := ANY_INSTANCE_STATE; - signal view_state_dds, si_view_state : std_logic_vector(VIEW_STATE_KIND_WIDTH-1 downto 0) := ANY_VIEW_STATE; - signal sample_state_dds, si_sample_state : std_logic_vector(SAMPLE_STATE_KIND_WIDTH-1 downto 0) := ANY_SAMPLE_STATE; - signal instance_handle_dds, si_instance_handle : INSTANCE_HANDLE_TYPE := HANDLE_NIL; - signal max_samples_dds : std_logic_vector(MAX_SAMPLES_WIDTH-1 downto 0) := (others => '0'); - signal si_source_timestamp : TIME_TYPE := TIME_INVALID; - signal si_publication_handle : INSTANCE_HANDLE_TYPE := HANDLE_NIL; - signal si_disposed_generation_count : std_logic_vector(DISPOSED_GENERATION_COUNT_WIDTH-1 downto 0) := (others => '0'); - signal si_no_writers_generation_count : std_logic_vector(NO_WRITERS_GENERATION_COUNT_WIDTH-1 downto 0) := (others => '0'); - signal si_sample_rank : std_logic_vector(SAMPLE_RANK_WIDTH-1 downto 0) := (others => '0'); - signal si_generation_rank : std_logic_vector(GENERATION_RANK_WIDTH-1 downto 0) := (others => '0'); - signal si_absolute_generation_rank: std_logic_vector(ABSOLUTE_GENERATION_COUNT_WIDTH-1 downto 0) := (others => '0'); - - signal dds_start , dds_done , rtps_start, rtps_done : std_logic := '0'; - signal dds_cnt, dds_cnt2, rtps_cnt : natural := 0; - signal dds_stage : DDS_STAGE_TYPE := IDLE; - signal rtps_stage : RTPS_STAGE_TYPE := IDLE; - shared variable dds : DDS_READER_TEST_TYPE := DEFAULT_DDS_READER_TEST; - shared variable rtps : RTPS_READER_TEST_TYPE := DEFAULT_RTPS_READER_TEST; - shared variable mem : DDS_READER_MEM_TYPE := DEFAULT_DDS_READER_MEM; - signal data_id, ret_id, sstate_id, vstate_id, istate_id, inst_id, ts_id, pub_id, dis_gen_cnt_id, no_w_gen_cnt_id, srank_id, grank_id, agrank_id, eoc_id, valid_id : AlertLogIDType; - - -- *FUNCTION DECLARATION* - function extract_key_hash (payload : TEST_PACKET_TYPE) return INSTANCE_HANDLE_TYPE is - variable ret : INSTANCE_HANDLE_TYPE := HANDLE_NIL; - begin - for i in 0 to 3 loop - ret(i) := not payload.data(i); - end loop; - - return ret; - end function; - - function gen_sn(input : natural) return SEQUENCENUMBER_TYPE is - variable ret : SEQUENCENUMBER_TYPE; - begin - ret(0) := (others => '0'); - ret(1) := unsigned(int(input, WORD_WIDTH)); - return ret; - end function; - -begin - - -- Unit Under Test - uut : entity work.dds_reader(arch) - generic map ( - TIME_BASED_FILTER_QOS => DURATION_ZERO, - DEADLINE_QOS => DURATION_INFINITE, - MAX_SAMPLES => std_logic_vector(to_unsigned(15,CDR_LONG_WIDTH)), - MAX_INSTANCES => std_logic_vector(to_unsigned(4,CDR_LONG_WIDTH)), - MAX_SAMPLES_PER_INSTANCE => std_logic_vector(to_unsigned(15,CDR_LONG_WIDTH)), - HISTORY_QOS => KEEP_ALL_HISTORY_QOS, - RELIABILITY_QOS => RELIABLE_RELIABILITY_QOS, - PRESENTATION_QOS => INSTANCE_PRESENTATION_QOS, - DESTINATION_ORDER_QOS => BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS, - COHERENT_ACCESS => FALSE, - ORDERED_ACCESS => TRUE, - WITH_KEY => TRUE, - PAYLOAD_FRAME_SIZE => 11, - MAX_REMOTE_ENDPOINTS => MAX_REMOTE_ENDPOINTS - ) - port map ( - clk => clk, - reset => reset, - time => check_time, - start_rtps => start_rtps, - opcode_rtps => opcode_rtps, - ack_rtps => ack_rtps, - done_rtps => done_rtps, - ret_rtps => ret_rtps, - data_in_rtps => data_in_rtps, - valid_in_rtps => valid_in_rtps, - ready_in_rtps => ready_in_rtps, - last_word_in_rtps => last_word_in_rtps, - start_dds => start_dds, - ack_dds => ack_dds, - opcode_dds => opcode_dds, - instance_state_dds => instance_state_dds, - view_state_dds => view_state_dds, - sample_state_dds => sample_state_dds, - instance_handle_dds => instance_handle_dds, - max_samples_dds => max_samples_dds, - get_data_dds => get_data_dds, - done_dds => done_dds, - return_code_dds => return_code_dds, - ready_out_dds => ready_out_dds, - valid_out_dds => valid_out_dds, - data_out_dds => data_out_dds, - last_word_out_dds => last_word_out_dds, - sample_info.sample_state => si_sample_state, - sample_info.view_state => si_view_state, - sample_info.instance_state => si_instance_state, - sample_info.source_timestamp => si_source_timestamp, - sample_info.instance_handle => si_instance_handle, - sample_info.publication_handle => si_publication_handle, - sample_info.disposed_generation_count => si_disposed_generation_count, - sample_info.no_writers_generation_count => si_no_writers_generation_count, - sample_info.sample_rank => si_sample_rank, - sample_info.generation_rank => si_generation_rank, - sample_info.absolute_generation_rank => si_absolute_generation_rank, - sample_info.valid_data => si_valid_data, - sample_info_valid => si_valid, - sample_info_ack => '1', - eoc => eoc, - status => status - ); - - stimulus_prc : process - variable RV : RandomPType; - variable cc : CACHE_CHANGE_TYPE := DEFAULT_CACHE_CHANGE; - variable s : SAMPLE_TYPE := DEFAULT_SAMPLE; - variable kh1, kh2, kh3, kh4, kh5 : INSTANCE_HANDLE_TYPE := HANDLE_NIL; - - alias idle_sig is <>; - - impure function gen_payload(key_hash : INSTANCE_HANDLE_TYPE; len : natural) return TEST_PACKET_TYPE is - variable ret : TEST_PACKET_TYPE := EMPTY_TEST_PACKET; - begin - assert (len >= 4) report "Payload length has to be at least 16 Bytes long" severity FAILURE; - - for i in 0 to len-1 loop - if (i < 4) then - -- NOTE: Beginning of payload is negated key to allow deterministic Key Hash generation from the kh_prc - ret.data(ret.length) := not key_hash(i); - else - ret.data(ret.length) := RV.RandSlv(WORD_WIDTH); - end if; - ret.length := ret.length + 1; - end loop; - ret.last(ret.length-1) := '1'; - - return ret; - end function; - - impure function gen_key_hash return KEY_HASH_TYPE is - variable ret : KEY_HASH_TYPE := KEY_HASH_NIL; - begin - for i in 0 to KEY_HASH_TYPE'length-1 loop - ret(i) := RV.RandSlv(WORD_WIDTH); - end loop; - return ret; - end function; - - procedure start_dds is - begin - dds_start <= '1'; - wait until rising_edge(clk); - dds_start <= '0'; - wait until rising_edge(clk); - end procedure; - - procedure start_rtps is - begin - rtps_start <= '1'; - wait until rising_edge(clk); - rtps_start <= '0'; - wait until rising_edge(clk); - end procedure; - - procedure wait_on_dds is - begin - if (dds_done /= '1') then - wait until dds_done = '1'; - end if; - end procedure; - - procedure wait_on_rtps is - begin - if (rtps_done /= '1') then - wait until rtps_done = '1'; - end if; - end procedure; - - procedure wait_on_completion is - begin - if (rtps_done /= '1' or dds_done /= '1') then - wait until rtps_done = '1' and dds_done = '1'; - end if; - end procedure; - - -- NOTE: This procedure waits until the idle_sig is high for at least - -- two consecutive clock cycles. - procedure wait_on_idle is - variable first : boolean := TRUE; - begin - loop - if (idle_sig /= '1') then - wait until idle_sig = '1'; - elsif (not first) then - exit; - end if; - wait until rising_edge(clk); - wait until rising_edge(clk); - first := FALSE; - end loop; - end procedure; - - begin - - SetAlertLogName("L0_dds_reader_test3_arzkrio - (KEEP ALL, Reliable, Zero TIME_BASED_FILTER, Keyed, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER, ACCESS SCOPE Instance, Ordered) - DDS Handling"); - SetAlertEnable(FAILURE, TRUE); - SetAlertEnable(ERROR, TRUE); - SetAlertEnable(WARNING, TRUE); - SetLogEnable(DEBUG, TRUE); - SetLogEnable(PASSED, FALSE); - SetLogEnable(INFO, TRUE); - RV.InitSeed(RV'instance_name); - sstate_id <= GetAlertLogID("Sample State", ALERTLOG_BASE_ID); - vstate_id <= GetAlertLogID("View State", ALERTLOG_BASE_ID); - istate_id <= GetAlertLogID("Instance State", ALERTLOG_BASE_ID); - ts_id <= GetAlertLogID("Source Timestamp", ALERTLOG_BASE_ID); - inst_id <= GetAlertLogID("Instance Handle", ALERTLOG_BASE_ID); - pub_id <= GetAlertLogID("Publication Hanlde", ALERTLOG_BASE_ID); - dis_gen_cnt_id <= GetAlertLogID("Disposed Generation Count", ALERTLOG_BASE_ID); - no_w_gen_cnt_id <= GetAlertLogID("No Writers Generation Count", ALERTLOG_BASE_ID); - srank_id <= GetAlertLogID("Sample Rank", ALERTLOG_BASE_ID); - grank_id <= GetAlertLogID("Generation Rank", ALERTLOG_BASE_ID); - agrank_id <= GetAlertLogID("Absolute Generation Rank", ALERTLOG_BASE_ID); - eoc_id <= GetAlertLogID("End Of Collection", ALERTLOG_BASE_ID); - valid_id <= GetAlertLogID("Valid Data", ALERTLOG_BASE_ID); - data_id <= GetAlertLogID("Data Out", ALERTLOG_BASE_ID); - ret_id <= GetAlertLogID("Return Code", ALERTLOG_BASE_ID); - - -- Key Hashes - kh1 := (x"F12C31DA", x"E3FE0F3F", x"01F36685", x"446518CA"); - kh2 := (x"BC070AC4", x"0BAB5811", x"14EA8D61", x"F669189B"); - kh3 := (x"0CEAB0C6", x"FA04B9AD", x"A96EB495", x"4E0EB999"); - kh4 := (x"A7EB605C", x"FF4BEF3A", x"3C5E8724", x"CCA0CA67"); - kh5 := gen_key_hash; - - - - Log("Initiating Test", INFO); - Log("Current Time: 0s", INFO); - check_time <= TIME_ZERO; - reset <= '1'; - wait until rising_edge(clk); - wait until rising_edge(clk); - reset <= '0'; - -- MEM: - - -- ISTATE: - - -- VIEW: - - -- WRITER: - - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh1; - cc.payload := gen_payload(kh1,10); - cc.src_timestamp := gen_duration(0,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Aligned Payload, ID 0] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - rtps.ret_code := OK; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S1(0) - -- ISTATE: I1:ALIVE - -- VIEW: I1:NEW - -- WRITER: W0:I1 - - Log("Current Time: 1s", INFO); - check_time <= gen_duration(1,0); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait_on_idle; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_DISPOSED; - cc.instance := kh1; - cc.payload := gen_payload(kh1,5); - cc.src_timestamp := gen_duration(1,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Instance 1, Writer 0, ID 1] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - rtps.ret_code := OK; - s := to_sample(cc,NOT_ALIVE_DISPOSED_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S1(0), I1S2-(1) - -- ISTATE: I1:DISPOSED - -- VIEW: I1:NEW - -- WRITER: W0:I1 - - Log("Current Time: 2s", INFO); - check_time <= gen_duration(2,0); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait_on_idle; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh2; - cc.payload := gen_payload(kh2,10); - cc.src_timestamp := gen_duration(2,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 2, Writer 1, Aligned Payload, ID 2] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 1; - rtps.ret_code := OK; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S1(0), I1S2-(1), I2S1(2) - -- ISTATE: I1:DISPOSED, I2:ALIVE - -- VIEW: I1:NEW, I2:NEW - -- WRITER: W0:I1, W1:I2 - - Log("Current Time: 3s", INFO); - check_time <= gen_duration(3,0); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait_on_idle; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh3; - cc.payload := gen_payload(kh3,10); - cc.src_timestamp := gen_duration(3,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 3, Writer 2, Aligned Payload, ID 3] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 2; - rtps.ret_code := OK; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3) - -- ISTATE: I1:DISPOSED, I2:ALIVE, I3:ALIVE - -- VIEW: I1:NEW, I2:NEW, I3:NEW - -- WRITER: W0:I1, W1:I2, W2:I3 - - Log("Current Time: 4s", INFO); - check_time <= gen_duration(4,0); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait_on_idle; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh4; - cc.payload := gen_payload(kh4,10); - cc.src_timestamp := gen_duration(4,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 4, Writer 2, Aligned Payload, ID 4] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 2; - rtps.ret_code := OK; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), - -- ISTATE: I1:DISPOSED, I2:ALIVE, I3:ALIVE, I4:ALIVE - -- VIEW: I1:NEW, I2:NEW, I3:NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - Log("Current Time: 5s", INFO); - check_time <= gen_duration(5,0); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait_on_idle; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_DISPOSED; - cc.instance := kh2; - cc.payload := gen_payload(kh2,5); - cc.src_timestamp := gen_duration(5,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Instance 2, Writer 1, ID 5] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 1; - rtps.ret_code := OK; - s := to_sample(cc,NOT_ALIVE_DISPOSED_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5) - -- ISTATE: I1:DISPOSED, I2:DISPOSED, I3:ALIVE, I4:ALIVE - -- VIEW: I1:NEW, I2:NEW, I3:NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - Log("Current Time: 6s", INFO); - check_time <= gen_duration(6,0); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait_on_idle; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_DISPOSED; - cc.instance := kh3; - cc.payload := gen_payload(kh3,5); - cc.src_timestamp := gen_duration(6,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Instance 3, Writer 2, ID 6] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 2; - rtps.ret_code := OK; - s := to_sample(cc,NOT_ALIVE_DISPOSED_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6) - -- ISTATE: I1:DISPOSED, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NEW, I2:NEW, I3:NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - Log("Current Time: 7s", INFO); - check_time <= gen_duration(7,0); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait_on_idle; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_DISPOSED; - cc.instance := kh4; - cc.payload := gen_payload(kh4,5); - cc.src_timestamp := gen_duration(7,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Instance 4, Writer 2, ID 7] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 2; - rtps.ret_code := OK; - s := to_sample(cc,NOT_ALIVE_DISPOSED_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7) - -- ISTATE: I1:DISPOSED, I2:DISPOSED, I3:DISPOSED, I4:DISPOSED - -- VIEW: I1:NEW, I2:NEW, I3:NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - Log("Current Time: 8s", INFO); - check_time <= gen_duration(8,0); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait_on_idle; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh4; - cc.payload := gen_payload(kh4,10); - cc.src_timestamp := gen_duration(8,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 4, Writer 2, Aligned Payload, ID 8] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 2; - rtps.ret_code := OK; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8) - -- ISTATE: I1:DISPOSED, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NEW, I2:NEW, I3:NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - Log("Current Time: 9s", INFO); - check_time <= gen_duration(9,0); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait_on_idle; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh1; - cc.payload := gen_payload(kh1,10); - cc.src_timestamp := gen_duration(9,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Aligned Payload, ID 9] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - rtps.ret_code := OK; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NEW, I2:NEW, I3:NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - Log("Current Time: 10s", INFO); - check_time <= gen_duration(10,0); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait_on_idle; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh2; - cc.payload := gen_payload(kh2,10); - cc.src_timestamp := gen_duration(10,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 2, Writer 1, Aligned Payload, ID 10] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 1; - rtps.ret_code := OK; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10) - -- ISTATE: I1:ALIVE, I2:ALIVE, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NEW, I2:NEW, I3:NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - Log("Current Time: 11s", INFO); - check_time <= gen_duration(11,0); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait_on_idle; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_DISPOSED; - cc.instance := kh2; - cc.payload := gen_payload(kh2,5); - cc.src_timestamp := gen_duration(11,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Instance 2, Writer 1, ID 11] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 1; - rtps.ret_code := OK; - s := to_sample(cc,NOT_ALIVE_DISPOSED_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NEW, I2:NEW, I3:NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: READ [MAX_SAMPLES < SAMPLES] - -- TEST: READ [ANY SSTATE, ANY ISTATE, ANY VIEW] - - Log("DDS Operation READ [MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE] (Expected ID0,ID1,ID9)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ; - dds.max_samples := 3; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - start_dds; - wait_on_dds; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NEW, I3:NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: READ MARKS SAMPLES AS READ - -- TEST: READ_NEXT_SAMPLE [WITH UNREAD SAMPLE] - - Log("DDS Operation READ_NEXT_SAMPLE (Expected ID2)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ_NEXT_SAMPLE; - start_dds; - wait_on_dds; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NEW, I3:NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: READ_INSTANCE [KNOWN INSTANCE, COMPATIBLE SAMPLES] - - Log("DDS Operation READ_INSTANCE [MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Instance 3] (Expected ID3)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ_INSTANCE; - dds.max_samples := 1; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.inst := kh3; - start_dds; - wait_on_dds; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NEW, I3:NOT_NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: READ_NEXT_INSTANCE [WITH NEXT INSTANCE, COMPATIBLE SAMPLES] - - Log("DDS Operation READ_NEXT_INSTANCE [MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Instance 3] (Expected ID4)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ_NEXT_INSTANCE; - dds.max_samples := 1; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.inst := kh3; - start_dds; - wait_on_dds; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NEW, I3:NOT_NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: READ [SPECIFIED SSTATE, ANY ISTATE, ANY VIEW] - -- TEST: READ [MAX_SAMPLES > SAMPLES] - - Log("DDS Operation READ [MAX_SAMPLES 20, READ_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE] (Expected ID0,ID1,ID9,ID2,ID3,ID4)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ; - dds.max_samples := 20; - dds.sstate := READ_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - start_dds; - wait_on_dds; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NEW, I3:NOT_NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: READ [SPECIFIED SSTATE, SPECIFIED ISTATE, ANY VIEW] - - Log("DDS Operation READ [MAX_SAMPLES 20, READ_SAMPLE_STATE, NOT_ALIVE_DISPOSED_INSTANCE_STATE, ANY_VIEW_STATE] (Expected ID2,ID3)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ; - dds.max_samples := 20; - dds.sstate := READ_SAMPLE_STATE; - dds.istate := NOT_ALIVE_DISPOSED_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - start_dds; - wait_on_dds; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NEW, I3:NOT_NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: READ [SPECIFIED SSTATE, ANY ISTATE, SPECIFIED VIEW] - -- TEST: READ MODIFIES VIEW STATE [READ CURRENT GENERATION] - -- TEST: READ MODIFIES VIEW STATE [READ PREVIOUS GENERATION] - - Log("DDS Operation READ [MAX_SAMPLES 20, READ_SAMPLE_STATE, ANY_INSTANCE_STATE, NEW_VIEW_STATE] (Expected ID2,ID4)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ; - dds.max_samples := 20; - dds.sstate := READ_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := NEW_VIEW_STATE; - start_dds; - wait_on_dds; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NEW, I3:NOT_NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: READ [SPECIFIED SSTATE, SPECIFIED ISTATE, SPECIFIED VIEW] - - Log("DDS Operation READ [MAX_SAMPLES 20, READ_SAMPLE_STATE, NOT_ALIVE_DISPOSED_INSTANCE_STATE, NEW_VIEW_STATE] (Expected ID2)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ; - dds.max_samples := 20; - dds.sstate := READ_SAMPLE_STATE; - dds.istate := NOT_ALIVE_DISPOSED_INSTANCE_STATE; - dds.vstate := NEW_VIEW_STATE; - start_dds; - wait_on_dds; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NEW, I3:NOT_NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: READ [ANY SSTATE, ANY ISTATE, SPECIFIED VIEW] - - Log("DDS Operation READ [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, NOT_NEW_VIEW_STATE] (Expected ID0,ID1,ID9,ID3,ID6)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := NOT_NEW_VIEW_STATE; - start_dds; - wait_on_dds; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NEW, I3:NOT_NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: READ [ANY SSTATE, SPECIFIED ISTATE, SPECIFIED VIEW] - - Log("DDS Operation READ [MAX_SAMPLES 20, ANY_SAMPLE_STATE, NOT_ALIVE_DISPOSED_INSTANCE_STATE, NOT_NEW_VIEW_STATE] (Expected ID3,ID6)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := NOT_ALIVE_DISPOSED_INSTANCE_STATE; - dds.vstate := NOT_NEW_VIEW_STATE; - start_dds; - wait_on_dds; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NEW, I3:NOT_NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: READ [ANY SSTATE, SPECIFIED ISTATE, ANY VIEW] - - Log("DDS Operation READ [MAX_SAMPLES 20, ANY_SAMPLE_STATE, NOT_ALIVE_DISPOSED_INSTANCE_STATE, ANY_VIEW_STATE] (Expected ID2,ID5,ID10,ID11,ID3,ID6)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := NOT_ALIVE_DISPOSED_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - start_dds; - wait_on_dds; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: READ_INSTANCE [UNKNOWN INSTANCE] - - Log("DDS Operation READ_INSTANCE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Unknown Instance] (Bad Parameter)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ_INSTANCE; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.inst := kh5; - dds.ret_code := RETCODE_BAD_PARAMETER; - start_dds; - wait_on_dds; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: READ_INSTANCE [KNOWN INSTANCE, UNCOMPATIBLE SAMPLES] - - Log("DDS Operation READ_INSTANCE [MAX_SAMPLES 20, NOT_READ_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Instance 1] (No Data)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ_INSTANCE; - dds.max_samples := 20; - dds.sstate := NOT_READ_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.inst := kh1; - dds.ret_code := RETCODE_NO_DATA; - start_dds; - wait_on_dds; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: READ_NEXT_INSTANCE [WITH NEXT INSTANCE, UNCOMPATIBLE SAMPLES] - - Log("DDS Operation READ_NEXT_INSTANCE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, NOT_ALIVE_DISPOSED_INSTANCE_STATE, ANY_VIEW_STATE, Instance 2] (No Data)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ_NEXT_INSTANCE; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := NOT_ALIVE_DISPOSED_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.inst := kh2; - dds.ret_code := RETCODE_NO_DATA; - start_dds; - wait_on_dds; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: READ_NEXT_INSTANCE [WITH NEXT INSTANCE, WITH COMPATIBLE SAMPLE, NOT DIRECT NEXT INSTANCE] - - Log("DDS Operation READ_NEXT_INSTANCE [MAX_SAMPLES 20, NOT_READ_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Instance 3] (Expected ID7,ID8)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ_NEXT_INSTANCE; - dds.max_samples := 20; - dds.sstate := NOT_READ_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.inst := kh3; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: READ [NO COMPATIBLE SAMPLES] - - Log("DDS Operation READ [MAX_SAMPLES 20, ANY_SAMPLE_STATE, NOT_ALIVE_NO_WRITERS_INSTANCE_STATE, ANY_VIEW_STATE] (No Data)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := NOT_ALIVE_NO_WRITERS_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.ret_code := RETCODE_NO_DATA; - start_dds; - wait_on_dds; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: READ_NEXT_SAMPLE [WITHOUT UNREAD SAMPLE] - - Log("DDS Operation READ_NEXT_SAMPLE (No Data)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ_NEXT_SAMPLE; - dds.ret_code := RETCODE_NO_DATA; - start_dds; - wait_on_dds; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: TAKE - - Log("DDS Operation TAKE [MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE] (Expected ID0)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE; - dds.max_samples := 1; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - -- MEM: I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: TAKE_INSTANCE - - Log("DDS Operation TAKE_INSTANCE [MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Instance 2] (Expected ID2)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE_INSTANCE; - dds.max_samples := 1; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.inst := kh2; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - -- MEM: I1S2-(1), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: TAKE_NEXT_INSTANCE - -- TEST: READ_NEXT_INSTANCE [HANDLE_NIL] - - Log("DDS Operation TAKE_NEXT_INSTANCE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, HANDLE_NIL] (Expected ID3,ID6)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE_NEXT_INSTANCE; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.inst := HANDLE_NIL; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - -- MEM: I1S2-(1), I4S1(4), I2S2-(5), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: TAKE REMOVES SAMPLE - -- TEST: READ_INSTANCE [NO SAMPLES] - - Log("DDS Operation READ_INSTANCE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Instance 3] (No Data)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ_INSTANCE; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.inst := kh3; - dds.ret_code := RETCODE_NO_DATA; - start_dds; - wait_on_dds; - -- MEM: I1S2-(1), I4S1(4), I2S2-(5), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - Log("DDS Operation TAKE_NEXT_INSTANCE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Instance 3] (Expected ID4,ID7,ID8)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE_NEXT_INSTANCE; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.inst := kh3; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - -- MEM: I1S2-(1), I2S2-(5), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: TAKE_INSTANCE [NO SAMPLES] - - Log("DDS Operation TAKE_INSTANCE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Instance 4] (No Data)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE_INSTANCE; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.inst := kh4; - dds.ret_code := RETCODE_NO_DATA; - start_dds; - wait_on_dds; - -- MEM: I1S2-(1), I2S2-(5), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - Log("DDS Operation TAKE_NEXT_INSTANCE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Instance 4] (Expected ID5,ID10,ID11)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE_NEXT_INSTANCE; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.inst := kh4; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - -- MEM: I1S2-(1), I1S3(9) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - Log("DDS Operation READ_INSTANCE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Instance 2] (No Data)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ_INSTANCE; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.inst := kh2; - dds.ret_code := RETCODE_NO_DATA; - start_dds; - wait_on_dds; - -- MEM: I1S2-(1), I1S3(9) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: READ_NEXT_INSTANCE [WITH SAMPLES, WITHOUT NEXT INSTANCE] - - Log("DDS Operation READ_NEXT_INSTANCE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Instance 1] (No Data)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ_NEXT_INSTANCE; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.inst := kh1; - dds.ret_code := RETCODE_NO_DATA; - start_dds; - wait_on_dds; - -- MEM: I1S2-(1), I1S3(9) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - Log("DDS Operation TAKE_NEXT_INSTANCE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Instance 2] (Expected ID1,ID9)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE_NEXT_INSTANCE; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.inst := kh2; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - -- MEM: - - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: GET ALL DATA WITH READ_NEXT_INSTANCE - -- TEST: READ [NO SAMPLES] - - Log("DDS Operation READ [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE] (No Data)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.ret_code := RETCODE_NO_DATA; - start_dds; - wait_on_dds; - -- MEM: - - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: TAKE [NO SAMPLES] - - Log("DDS Operation TAKE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE] (No Data)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.ret_code := RETCODE_NO_DATA; - start_dds; - wait_on_dds; - -- MEM: - - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: READ_NEXT_INSTANCE [NO SAMPLE] - - Log("DDS Operation READ_NEXT_INSTANCE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, HANDLE_NIL] (No Data)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ_NEXT_INSTANCE; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.inst := HANDLE_NIL; - dds.ret_code := RETCODE_NO_DATA; - start_dds; - wait_on_dds; - -- MEM: - - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: TAKE_NEXT_INSTANCE [NO SAMPLE] - - Log("DDS Operation TAKE_NEXT_INSTANCE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, HANDLE_NIL] (No Data)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE_NEXT_INSTANCE; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.inst := HANDLE_NIL; - dds.ret_code := RETCODE_NO_DATA; - start_dds; - wait_on_dds; - -- MEM: - - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: READ_NEXT_SAMPLE [NO SAMPLE] - - Log("DDS Operation READ_NEXT_SAMPLE (No Data)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ_NEXT_SAMPLE; - dds.ret_code := RETCODE_NO_DATA; - start_dds; - wait_on_dds; - -- MEM: - - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: TAKE_NEXT_SAMPLE [NO SAMPLE] - - Log("DDS Operation TAKE_NEXT_SAMPLE (No Data)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE_NEXT_SAMPLE; - dds.ret_code := RETCODE_NO_DATA; - start_dds; - wait_on_dds; - -- MEM: - - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - Log("Current Time: 12s", INFO); - check_time <= gen_duration(12,0); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait_on_idle; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh2; - cc.payload := gen_payload(kh2,10); - cc.src_timestamp := gen_duration(12,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 2, Writer 1, Aligned Payload, ID 12] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 1; - rtps.ret_code := OK; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I2S5(12) - -- ISTATE: I1:ALIVE, I2:ALIVE, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: TAKE_NEXT_SAMPLE - - Log("DDS Operation TAKE_NEXT_SAMPLE (Expected ID12)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE_NEXT_SAMPLE; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - -- MEM: - - -- ISTATE: I1:ALIVE, I2:ALIVE, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - Log("DDS Operation READ [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE] (No Data)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.ret_code := RETCODE_NO_DATA; - start_dds; - wait_on_dds; - -- MEM: - - -- ISTATE: I1:ALIVE, I2:ALIVE, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - wait_on_completion; - TranscriptOpen(RESULTS_FILE, APPEND_MODE); - SetTranscriptMirror; - ReportAlerts; - TranscriptClose; - std.env.stop; - wait; - end process; - - clock_prc : process - begin - clk <= '0'; - wait for 25 ns; - clk <= '1'; - wait for 25 ns; - end process; - - alert_prc : process(all) - begin - if rising_edge(clk) then - -- TODO - end if; - end process; - - dds_prc : process(all) - variable col : COLLECTION_TYPE := DEFAULT_COLLECTION; - begin - if rising_edge(clk) then - dds_done <= '0'; - case (dds_stage ) is - when IDLE => - if (dds_start = '1') then - dds_stage <= START; - else - dds_done <= '1'; - end if; - when START => - if (ack_dds = '1') then - dds_stage <= DONE; - dds_cnt <= 0; - end if; - when DONE => - if (done_dds = '1') then - AffirmIfEqual(ret_id, return_code_dds, dds.ret_code); - case (dds.ret_code) is - when RETCODE_OK => - gen_collection(mem, col, dds, INSTANCE_PRESENTATION_QOS, TRUE); - dds_stage <= CHECK_SI; - dds_cnt <= 0; - when others => - dds_stage <= IDLE; - end case; - end if; - when CHECK_SI => - if (si_valid = '1') then - Log("Read Sample ID" & to_string(to_integer(si_source_timestamp(0))), DEBUG); - AffirmIfEqual(sstate_id, si_sample_state, col.s(dds_cnt).sstate); - AffirmIfEqual(vstate_id, si_view_state, col.s(dds_cnt).vstate); - AffirmIfEqual(istate_id, si_instance_state, col.s(dds_cnt).istate); - AffirmIfEqual(ts_id, to_unsigned(si_source_timestamp), to_unsigned(col.s(dds_cnt).ts)); - AffirmIfEqual(inst_id, to_unsigned(si_instance_handle), to_unsigned(col.s(dds_cnt).inst)); - AffirmIfEqual(pub_id, to_unsigned(si_publication_handle), to_unsigned(HANDLE_NIL)); - AffirmIfEqual(dis_gen_cnt_id, si_disposed_generation_count, std_logic_vector(to_unsigned(col.s(dds_cnt).dis_gen_cnt,WORD_WIDTH))); - AffirmIfEqual(no_w_gen_cnt_id, si_no_writers_generation_count, std_logic_vector(to_unsigned(col.s(dds_cnt).no_w_gen_cnt,WORD_WIDTH))); - AffirmIfEqual(srank_id, si_sample_rank, std_logic_vector(to_unsigned(col.s(dds_cnt).srank,WORD_WIDTH))); - AffirmIfEqual(grank_id, si_generation_rank, std_logic_vector(to_unsigned(col.s(dds_cnt).grank,WORD_WIDTH))); - AffirmIfEqual(agrank_id, si_absolute_generation_rank, std_logic_vector(to_unsigned(col.s(dds_cnt).agrank,WORD_WIDTH))); - if (si_valid_data = '1') then - AffirmIf(valid_id, col.s(dds_cnt).data /= EMPTY_TEST_PACKET, "Sample with Data not expected"); - dds_stage <= CHECK_DATA; - dds_cnt2 <= 0; - else - AffirmIf(valid_id, col.s(dds_cnt).data = EMPTY_TEST_PACKET, "Sample with Data expected"); - if (dds_cnt = col.len-1) then - -- DONE - dds_stage <= WAIT_EOC; - else - dds_cnt <= dds_cnt + 1; - end if; - end if; - end if; - AffirmIf(eoc_id, eoc = '0', "EOC pulled high"); - when CHECK_DATA => - if (valid_out_dds = '1') then - AffirmIfEqual(data_id, data_out_dds, col.s(dds_cnt).data.data(dds_cnt2)); - dds_cnt2 <= dds_cnt2 + 1; - if (dds_cnt2 = col.s(dds_cnt).data.length-1) then - AlertIf(data_id, last_word_out_dds /= '1', "Last Word Signal not pulled High", ERROR); - if (dds_cnt = col.len-1) then - -- DONE - dds_stage <= WAIT_EOC; - else - dds_stage <= CHECK_SI; - dds_cnt <= dds_cnt + 1; - end if; - end if; - end if; - when WAIT_EOC => - if (eoc = '1') then - dds_stage <= IDLE; - end if; - end case; - end if; - - -- DEFAULT - start_dds <= '0'; - opcode_dds <= NOP; - instance_state_dds <= ANY_INSTANCE_STATE; - view_state_dds <= ANY_VIEW_STATE; - sample_state_dds <= ANY_SAMPLE_STATE; - instance_handle_dds <= HANDLE_NIL; - max_samples_dds <= (others => '0'); - get_data_dds <= '0'; - ready_out_dds <= '0'; - - - case (dds_stage ) is - when START => - start_dds <= '1'; - opcode_dds <= dds.opcode; - instance_state_dds <= dds.istate; - view_state_dds <= dds.vstate; - sample_state_dds <= dds.sstate; - instance_handle_dds <= dds.inst; - max_samples_dds <= std_logic_vector(to_unsigned(dds.max_samples, WORD_WIDTH)); - when CHECK_SI => - if (si_valid = '1' and si_valid_data = '1') then - get_data_dds <= '1'; - end if; - when CHECK_DATA => - ready_out_dds <= '1'; - when others => - null; - end case; - end process; - - rtps_prc : process(all) - variable stimulus : TEST_PACKET_TYPE := EMPTY_TEST_PACKET; - begin - if rising_edge(clk) then - rtps_done <= '0'; - case (rtps_stage) is - when IDLE => - if (rtps_start = '1') then - rtps_stage <= START; - else - rtps_done <= '1'; - end if; - when START => - if (ack_rtps = '1') then - case (rtps.opcode) is - when ADD_CACHE_CHANGE => - gen_add_cache_change_dds(rtps.cc, rtps.lifespan, rtps.writer_pos, stimulus); - rtps_stage <= PUSH; - when others => - rtps_stage <= DONE; - end case; - end if; - when PUSH => - if (ready_in_rtps = '1') then - rtps_cnt <= rtps_cnt + 1; - if (rtps_cnt = stimulus.length-1) then - rtps_stage <= DONE; - end if; - end if; - when DONE => - if (done_rtps = '1') then - AffirmIfEqual(ret_id, HISTORY_CACHE_RESPONSE_TYPE'pos(ret_rtps), HISTORY_CACHE_RESPONSE_TYPE'pos(rtps.ret_code)); - rtps_stage <= IDLE; - end if; - end case; - end if; - - -- DEFAULT - start_rtps <= '0'; - opcode_rtps <= NOP; - valid_in_rtps <= '0'; - last_word_in_rtps <= '0'; - data_in_rtps <= (others => '0'); - - case (rtps_stage) is - when START => - start_rtps <= '1'; - opcode_rtps <= rtps.opcode; - case (rtps.opcode) is - when REMOVE_WRITER => - data_in_rtps <= std_logic_vector(to_unsigned(rtps.writer_pos,WORD_WIDTH)); - when others => - null; - end case; - when PUSH => - valid_in_rtps <= '1'; - data_in_rtps <= stimulus.data(rtps_cnt); - last_word_in_rtps <= stimulus.last(rtps_cnt); - when others => - null; - end case; - end process; - - watchdog : process - begin - wait for 1 ms; - Alert("Test timeout", FAILURE); - std.env.stop; - end process; - -end architecture; \ No newline at end of file diff --git a/src/Tests/Level_0/L0_dds_reader_test3_arzkriu.vhd b/src/Tests/Level_0/L0_dds_reader_test3_arzkriu.vhd deleted file mode 100644 index 5071bf8..0000000 --- a/src/Tests/Level_0/L0_dds_reader_test3_arzkriu.vhd +++ /dev/null @@ -1,1481 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library osvvm; -- Utility Library -context osvvm.OsvvmContext; - -use work.rtps_package.all; -use work.user_config.all; -use work.rtps_config_package.all; -use work.rtps_test_package.all; - --- This testbench tests the DDS handling of the DDS Reader. It tests the correctness of the DDS READ, TAKE, READ_NEXT_SAMPLE, TAKE_NEXT_SAMPLE, --- READ_INSTANCE, TAKE_INSTANCE, READ_NEXT_INSTANCE, TAKE_NEXT_INSTANCE Operations. --- More specifically the testbench covers following tests: --- TEST: READ [NO COMPATIBLE SAMPLES] --- TEST: READ [NO SAMPLES] --- TEST: READ [MAX_SAMPLES < SAMPLES] --- TEST: READ [MAX_SAMPLES > SAMPLES] --- TEST: TAKE [NO SAMPLES] --- TEST: TAKE --- TEST: READ [ANY SSTATE, ANY ISTATE, ANY VIEW] --- TEST: READ [ANY SSTATE, ANY ISTATE, SPECIFIED VIEW] --- TEST: READ [ANY SSTATE, SPECIFIED ISTATE, ANY VIEW] --- TEST: READ [ANY SSTATE, SPECIFIED ISTATE, SPECIFIED VIEW] --- TEST: READ [SPECIFIED SSTATE, ANY ISTATE, ANY VIEW] --- TEST: READ [SPECIFIED SSTATE, ANY ISTATE, SPECIFIED VIEW] --- TEST: READ [SPECIFIED SSTATE, SPECIFIED ISTATE, ANY VIEW] --- TEST: READ [SPECIFIED SSTATE, SPECIFIED ISTATE, SPECIFIED VIEW] --- TEST: READ_NEXT_SAMPLE [WITH UNREAD SAMPLE] --- TEST: READ_NEXT_SAMPLE [WITHOUT UNREAD SAMPLE] --- TEST: READ_NEXT_SAMPLE [NO SAMPLE] --- TEST: TAKE_NEXT_SAMPLE [NO SAMPLE] --- TEST: TAKE_NEXT_SAMPLE --- TEST: READ_INSTANCE [UNKNOWN INSTANCE] --- TEST: READ_INSTANCE [KNOWN INSTANCE, UNCOMPATIBLE SAMPLES] --- TEST: READ_INSTANCE [KNOWN INSTANCE, COMPATIBLE SAMPLES] --- TEST: READ_INSTANCE [NO SAMPLES] --- TEST: TAKE_INSTANCE [NO SAMPLES] --- TEST: TAKE_INSTANCE --- TEST: READ_NEXT_INSTANCE [WITH SAMPLES, WITHOUT NEXT INSTANCE] --- TEST: READ_NEXT_INSTANCE [WITH NEXT INSTANCE, UNCOMPATIBLE SAMPLES] --- TEST: READ_NEXT_INSTANCE [WITH NEXT INSTANCE, COMPATIBLE SAMPLES] --- TEST: READ_NEXT_INSTANCE [HANDLE_NIL] --- TEST: READ_NEXT_INSTANCE [WITH NEXT INSTANCE, WITH COMPATIBLE SAMPLE, NOT DIRECT NEXT INSTANCE] --- TEST: READ_NEXT_INSTANCE [NO SAMPLE] --- TEST: TAKE_NEXT_INSTANCE [NO SAMPLE] --- TEST: TAKE_NEXT_INSTANCE --- TEST: GET ALL DATA WITH READ_NEXT_INSTANCE --- TEST: READ MARKS SAMPLES AS READ --- TEST: TAKE REMOVES SAMPLE --- TEST: READ MODIFIES VIEW STATE [READ PREVIOUS GENERATION] --- TEST: READ MODIFIES VIEW STATE [READ CURRENT GENERATION] - -entity L0_dds_reader_test3_arzkriu is -end entity; - - -architecture testbench of L0_dds_reader_test3_arzkriu is - - -- *CONSTANT DECLARATION* - constant MAX_REMOTE_ENDPOINTS : natural := 3; - - -- *TYPE DECLARATION* - type DDS_STAGE_TYPE is (IDLE, START, DONE, CHECK_SI, CHECK_DATA, WAIT_EOC); - type RTPS_STAGE_TYPE is (IDLE, START, PUSH, DONE); - - -- *SIGNAL DECLARATION* - signal clk : std_logic := '0'; - signal reset : std_logic := '1'; - signal check_time : TIME_TYPE := TIME_ZERO; - signal start_rtps, start_dds, ack_rtps, ack_dds, done_rtps, done_dds : std_logic := '0'; - signal opcode_rtps : HISTORY_CACHE_OPCODE_TYPE := NOP; - signal opcode_dds : DDS_READER_OPCODE_TYPE := NOP; - signal ret_rtps : HISTORY_CACHE_RESPONSE_TYPE := ERROR; - signal ready_in_rtps, valid_in_rtps, last_word_in_rtps : std_logic := '0'; - signal ready_out_dds, valid_out_dds, last_word_out_dds : std_logic := '0'; - signal data_in_rtps, data_out_dds : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); - signal get_data_dds, si_valid_data, si_valid, eoc : std_logic := '0'; - signal return_code_dds : std_logic_vector(RETURN_CODE_WIDTH-1 downto 0) := (others => '0'); - signal status : std_logic_vector(STATUS_KIND_WIDTH-1 downto 0) := (others => '0'); - signal instance_state_dds, si_instance_state : std_logic_vector(INSTANCE_STATE_KIND_WIDTH-1 downto 0) := ANY_INSTANCE_STATE; - signal view_state_dds, si_view_state : std_logic_vector(VIEW_STATE_KIND_WIDTH-1 downto 0) := ANY_VIEW_STATE; - signal sample_state_dds, si_sample_state : std_logic_vector(SAMPLE_STATE_KIND_WIDTH-1 downto 0) := ANY_SAMPLE_STATE; - signal instance_handle_dds, si_instance_handle : INSTANCE_HANDLE_TYPE := HANDLE_NIL; - signal max_samples_dds : std_logic_vector(MAX_SAMPLES_WIDTH-1 downto 0) := (others => '0'); - signal si_source_timestamp : TIME_TYPE := TIME_INVALID; - signal si_publication_handle : INSTANCE_HANDLE_TYPE := HANDLE_NIL; - signal si_disposed_generation_count : std_logic_vector(DISPOSED_GENERATION_COUNT_WIDTH-1 downto 0) := (others => '0'); - signal si_no_writers_generation_count : std_logic_vector(NO_WRITERS_GENERATION_COUNT_WIDTH-1 downto 0) := (others => '0'); - signal si_sample_rank : std_logic_vector(SAMPLE_RANK_WIDTH-1 downto 0) := (others => '0'); - signal si_generation_rank : std_logic_vector(GENERATION_RANK_WIDTH-1 downto 0) := (others => '0'); - signal si_absolute_generation_rank: std_logic_vector(ABSOLUTE_GENERATION_COUNT_WIDTH-1 downto 0) := (others => '0'); - - signal dds_start , dds_done , rtps_start, rtps_done : std_logic := '0'; - signal dds_cnt, dds_cnt2, rtps_cnt : natural := 0; - signal dds_stage : DDS_STAGE_TYPE := IDLE; - signal rtps_stage : RTPS_STAGE_TYPE := IDLE; - shared variable dds : DDS_READER_TEST_TYPE := DEFAULT_DDS_READER_TEST; - shared variable rtps : RTPS_READER_TEST_TYPE := DEFAULT_RTPS_READER_TEST; - shared variable mem : DDS_READER_MEM_TYPE := DEFAULT_DDS_READER_MEM; - signal data_id, ret_id, sstate_id, vstate_id, istate_id, inst_id, ts_id, pub_id, dis_gen_cnt_id, no_w_gen_cnt_id, srank_id, grank_id, agrank_id, eoc_id, valid_id : AlertLogIDType; - - -- *FUNCTION DECLARATION* - function extract_key_hash (payload : TEST_PACKET_TYPE) return INSTANCE_HANDLE_TYPE is - variable ret : INSTANCE_HANDLE_TYPE := HANDLE_NIL; - begin - for i in 0 to 3 loop - ret(i) := not payload.data(i); - end loop; - - return ret; - end function; - - function gen_sn(input : natural) return SEQUENCENUMBER_TYPE is - variable ret : SEQUENCENUMBER_TYPE; - begin - ret(0) := (others => '0'); - ret(1) := unsigned(int(input, WORD_WIDTH)); - return ret; - end function; - -begin - - -- Unit Under Test - uut : entity work.dds_reader(arch) - generic map ( - TIME_BASED_FILTER_QOS => DURATION_ZERO, - DEADLINE_QOS => DURATION_INFINITE, - MAX_SAMPLES => std_logic_vector(to_unsigned(15,CDR_LONG_WIDTH)), - MAX_INSTANCES => std_logic_vector(to_unsigned(4,CDR_LONG_WIDTH)), - MAX_SAMPLES_PER_INSTANCE => std_logic_vector(to_unsigned(15,CDR_LONG_WIDTH)), - HISTORY_QOS => KEEP_ALL_HISTORY_QOS, - RELIABILITY_QOS => RELIABLE_RELIABILITY_QOS, - PRESENTATION_QOS => INSTANCE_PRESENTATION_QOS, - DESTINATION_ORDER_QOS => BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS, - COHERENT_ACCESS => FALSE, - ORDERED_ACCESS => FALSE, - WITH_KEY => TRUE, - PAYLOAD_FRAME_SIZE => 11, - MAX_REMOTE_ENDPOINTS => MAX_REMOTE_ENDPOINTS - ) - port map ( - clk => clk, - reset => reset, - time => check_time, - start_rtps => start_rtps, - opcode_rtps => opcode_rtps, - ack_rtps => ack_rtps, - done_rtps => done_rtps, - ret_rtps => ret_rtps, - data_in_rtps => data_in_rtps, - valid_in_rtps => valid_in_rtps, - ready_in_rtps => ready_in_rtps, - last_word_in_rtps => last_word_in_rtps, - start_dds => start_dds, - ack_dds => ack_dds, - opcode_dds => opcode_dds, - instance_state_dds => instance_state_dds, - view_state_dds => view_state_dds, - sample_state_dds => sample_state_dds, - instance_handle_dds => instance_handle_dds, - max_samples_dds => max_samples_dds, - get_data_dds => get_data_dds, - done_dds => done_dds, - return_code_dds => return_code_dds, - ready_out_dds => ready_out_dds, - valid_out_dds => valid_out_dds, - data_out_dds => data_out_dds, - last_word_out_dds => last_word_out_dds, - sample_info.sample_state => si_sample_state, - sample_info.view_state => si_view_state, - sample_info.instance_state => si_instance_state, - sample_info.source_timestamp => si_source_timestamp, - sample_info.instance_handle => si_instance_handle, - sample_info.publication_handle => si_publication_handle, - sample_info.disposed_generation_count => si_disposed_generation_count, - sample_info.no_writers_generation_count => si_no_writers_generation_count, - sample_info.sample_rank => si_sample_rank, - sample_info.generation_rank => si_generation_rank, - sample_info.absolute_generation_rank => si_absolute_generation_rank, - sample_info.valid_data => si_valid_data, - sample_info_valid => si_valid, - sample_info_ack => '1', - eoc => eoc, - status => status - ); - - stimulus_prc : process - variable RV : RandomPType; - variable cc : CACHE_CHANGE_TYPE := DEFAULT_CACHE_CHANGE; - variable s : SAMPLE_TYPE := DEFAULT_SAMPLE; - variable kh1, kh2, kh3, kh4, kh5 : INSTANCE_HANDLE_TYPE := HANDLE_NIL; - - alias idle_sig is <>; - - impure function gen_payload(key_hash : INSTANCE_HANDLE_TYPE; len : natural) return TEST_PACKET_TYPE is - variable ret : TEST_PACKET_TYPE := EMPTY_TEST_PACKET; - begin - assert (len >= 4) report "Payload length has to be at least 16 Bytes long" severity FAILURE; - - for i in 0 to len-1 loop - if (i < 4) then - -- NOTE: Beginning of payload is negated key to allow deterministic Key Hash generation from the kh_prc - ret.data(ret.length) := not key_hash(i); - else - ret.data(ret.length) := RV.RandSlv(WORD_WIDTH); - end if; - ret.length := ret.length + 1; - end loop; - ret.last(ret.length-1) := '1'; - - return ret; - end function; - - impure function gen_key_hash return KEY_HASH_TYPE is - variable ret : KEY_HASH_TYPE := KEY_HASH_NIL; - begin - for i in 0 to KEY_HASH_TYPE'length-1 loop - ret(i) := RV.RandSlv(WORD_WIDTH); - end loop; - return ret; - end function; - - procedure start_dds is - begin - dds_start <= '1'; - wait until rising_edge(clk); - dds_start <= '0'; - wait until rising_edge(clk); - end procedure; - - procedure start_rtps is - begin - rtps_start <= '1'; - wait until rising_edge(clk); - rtps_start <= '0'; - wait until rising_edge(clk); - end procedure; - - procedure wait_on_dds is - begin - if (dds_done /= '1') then - wait until dds_done = '1'; - end if; - end procedure; - - procedure wait_on_rtps is - begin - if (rtps_done /= '1') then - wait until rtps_done = '1'; - end if; - end procedure; - - procedure wait_on_completion is - begin - if (rtps_done /= '1' or dds_done /= '1') then - wait until rtps_done = '1' and dds_done = '1'; - end if; - end procedure; - - -- NOTE: This procedure waits until the idle_sig is high for at least - -- two consecutive clock cycles. - procedure wait_on_idle is - variable first : boolean := TRUE; - begin - loop - if (idle_sig /= '1') then - wait until idle_sig = '1'; - elsif (not first) then - exit; - end if; - wait until rising_edge(clk); - wait until rising_edge(clk); - first := FALSE; - end loop; - end procedure; - - begin - - SetAlertLogName("L0_dds_reader_test3_arzkriu - (KEEP ALL, Reliable, Zero TIME_BASED_FILTER, Keyed, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER, ACCESS SCOPE Instance, Unordered) - DDS Handling"); - SetAlertEnable(FAILURE, TRUE); - SetAlertEnable(ERROR, TRUE); - SetAlertEnable(WARNING, TRUE); - SetLogEnable(DEBUG, TRUE); - SetLogEnable(PASSED, FALSE); - SetLogEnable(INFO, TRUE); - RV.InitSeed(RV'instance_name); - sstate_id <= GetAlertLogID("Sample State", ALERTLOG_BASE_ID); - vstate_id <= GetAlertLogID("View State", ALERTLOG_BASE_ID); - istate_id <= GetAlertLogID("Instance State", ALERTLOG_BASE_ID); - ts_id <= GetAlertLogID("Source Timestamp", ALERTLOG_BASE_ID); - inst_id <= GetAlertLogID("Instance Handle", ALERTLOG_BASE_ID); - pub_id <= GetAlertLogID("Publication Hanlde", ALERTLOG_BASE_ID); - dis_gen_cnt_id <= GetAlertLogID("Disposed Generation Count", ALERTLOG_BASE_ID); - no_w_gen_cnt_id <= GetAlertLogID("No Writers Generation Count", ALERTLOG_BASE_ID); - srank_id <= GetAlertLogID("Sample Rank", ALERTLOG_BASE_ID); - grank_id <= GetAlertLogID("Generation Rank", ALERTLOG_BASE_ID); - agrank_id <= GetAlertLogID("Absolute Generation Rank", ALERTLOG_BASE_ID); - eoc_id <= GetAlertLogID("End Of Collection", ALERTLOG_BASE_ID); - valid_id <= GetAlertLogID("Valid Data", ALERTLOG_BASE_ID); - data_id <= GetAlertLogID("Data Out", ALERTLOG_BASE_ID); - ret_id <= GetAlertLogID("Return Code", ALERTLOG_BASE_ID); - - -- Key Hashes - kh3 := (x"0CEAB0C6", x"FA04B9AD", x"A96EB495", x"4E0EB999"); - kh4 := (x"A7EB605C", x"FF4BEF3A", x"3C5E8724", x"CCA0CA67"); - kh2 := (x"BC070AC4", x"0BAB5811", x"14EA8D61", x"F669189B"); - kh1 := (x"F12C31DA", x"E3FE0F3F", x"01F36685", x"446518CA"); - kh5 := gen_key_hash; - - - Log("Initiating Test", INFO); - Log("Current Time: 0s", INFO); - check_time <= TIME_ZERO; - reset <= '1'; - wait until rising_edge(clk); - wait until rising_edge(clk); - reset <= '0'; - -- MEM: - - -- ISTATE: - - -- VIEW: - - -- WRITER: - - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh1; - cc.payload := gen_payload(kh1,10); - cc.src_timestamp := gen_duration(0,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Aligned Payload, ID 0] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - rtps.ret_code := OK; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S1(0) - -- ISTATE: I1:ALIVE - -- VIEW: I1:NEW - -- WRITER: W0:I1 - - Log("Current Time: 1s", INFO); - check_time <= gen_duration(1,0); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait_on_idle; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_DISPOSED; - cc.instance := kh1; - cc.payload := gen_payload(kh1,5); - cc.src_timestamp := gen_duration(1,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Instance 1, Writer 0, ID 1] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - rtps.ret_code := OK; - s := to_sample(cc,NOT_ALIVE_DISPOSED_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S1(0), I1S2-(1) - -- ISTATE: I1:DISPOSED - -- VIEW: I1:NEW - -- WRITER: W0:I1 - - Log("Current Time: 2s", INFO); - check_time <= gen_duration(2,0); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait_on_idle; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh2; - cc.payload := gen_payload(kh2,10); - cc.src_timestamp := gen_duration(2,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 2, Writer 1, Aligned Payload, ID 2] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 1; - rtps.ret_code := OK; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S1(0), I1S2-(1), I2S1(2) - -- ISTATE: I1:DISPOSED, I2:ALIVE - -- VIEW: I1:NEW, I2:NEW - -- WRITER: W0:I1, W1:I2 - - Log("Current Time: 3s", INFO); - check_time <= gen_duration(3,0); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait_on_idle; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh3; - cc.payload := gen_payload(kh3,10); - cc.src_timestamp := gen_duration(3,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 3, Writer 2, Aligned Payload, ID 3] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 2; - rtps.ret_code := OK; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3) - -- ISTATE: I1:DISPOSED, I2:ALIVE, I3:ALIVE - -- VIEW: I1:NEW, I2:NEW, I3:NEW - -- WRITER: W0:I1, W1:I2, W2:I3 - - Log("Current Time: 4s", INFO); - check_time <= gen_duration(4,0); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait_on_idle; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh4; - cc.payload := gen_payload(kh4,10); - cc.src_timestamp := gen_duration(4,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 4, Writer 2, Aligned Payload, ID 4] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 2; - rtps.ret_code := OK; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), - -- ISTATE: I1:DISPOSED, I2:ALIVE, I3:ALIVE, I4:ALIVE - -- VIEW: I1:NEW, I2:NEW, I3:NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - Log("Current Time: 5s", INFO); - check_time <= gen_duration(5,0); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait_on_idle; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_DISPOSED; - cc.instance := kh2; - cc.payload := gen_payload(kh2,5); - cc.src_timestamp := gen_duration(5,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Instance 2, Writer 1, ID 5] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 1; - rtps.ret_code := OK; - s := to_sample(cc,NOT_ALIVE_DISPOSED_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5) - -- ISTATE: I1:DISPOSED, I2:DISPOSED, I3:ALIVE, I4:ALIVE - -- VIEW: I1:NEW, I2:NEW, I3:NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - Log("Current Time: 6s", INFO); - check_time <= gen_duration(6,0); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait_on_idle; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_DISPOSED; - cc.instance := kh3; - cc.payload := gen_payload(kh3,5); - cc.src_timestamp := gen_duration(6,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Instance 3, Writer 2, ID 6] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 2; - rtps.ret_code := OK; - s := to_sample(cc,NOT_ALIVE_DISPOSED_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6) - -- ISTATE: I1:DISPOSED, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NEW, I2:NEW, I3:NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - Log("Current Time: 7s", INFO); - check_time <= gen_duration(7,0); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait_on_idle; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_DISPOSED; - cc.instance := kh4; - cc.payload := gen_payload(kh4,5); - cc.src_timestamp := gen_duration(7,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Instance 4, Writer 2, ID 7] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 2; - rtps.ret_code := OK; - s := to_sample(cc,NOT_ALIVE_DISPOSED_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7) - -- ISTATE: I1:DISPOSED, I2:DISPOSED, I3:DISPOSED, I4:DISPOSED - -- VIEW: I1:NEW, I2:NEW, I3:NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - Log("Current Time: 8s", INFO); - check_time <= gen_duration(8,0); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait_on_idle; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh4; - cc.payload := gen_payload(kh4,10); - cc.src_timestamp := gen_duration(8,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 4, Writer 2, Aligned Payload, ID 8] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 2; - rtps.ret_code := OK; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8) - -- ISTATE: I1:DISPOSED, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NEW, I2:NEW, I3:NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - Log("Current Time: 9s", INFO); - check_time <= gen_duration(9,0); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait_on_idle; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh1; - cc.payload := gen_payload(kh1,10); - cc.src_timestamp := gen_duration(9,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Aligned Payload, ID 9] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - rtps.ret_code := OK; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NEW, I2:NEW, I3:NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - Log("Current Time: 10s", INFO); - check_time <= gen_duration(10,0); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait_on_idle; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh2; - cc.payload := gen_payload(kh2,10); - cc.src_timestamp := gen_duration(10,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 2, Writer 1, Aligned Payload, ID 10] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 1; - rtps.ret_code := OK; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10) - -- ISTATE: I1:ALIVE, I2:ALIVE, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NEW, I2:NEW, I3:NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - Log("Current Time: 11s", INFO); - check_time <= gen_duration(11,0); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait_on_idle; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_DISPOSED; - cc.instance := kh2; - cc.payload := gen_payload(kh2,5); - cc.src_timestamp := gen_duration(11,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Instance 2, Writer 1, ID 11] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 1; - rtps.ret_code := OK; - s := to_sample(cc,NOT_ALIVE_DISPOSED_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NEW, I2:NEW, I3:NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: READ [MAX_SAMPLES < SAMPLES] - -- TEST: READ [ANY SSTATE, ANY ISTATE, ANY VIEW] - - Log("DDS Operation READ [MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE] (Expected ID0,ID1,ID9)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ; - dds.max_samples := 3; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - start_dds; - wait_on_dds; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NEW, I3:NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: READ MARKS SAMPLES AS READ - -- TEST: READ_NEXT_SAMPLE [WITH UNREAD SAMPLE] - - Log("DDS Operation READ_NEXT_SAMPLE (Expected ID2)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ_NEXT_SAMPLE; - start_dds; - wait_on_dds; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NEW, I3:NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: READ_INSTANCE [KNOWN INSTANCE, COMPATIBLE SAMPLES] - - Log("DDS Operation READ_INSTANCE [MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Instance 3] (Expected ID3)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ_INSTANCE; - dds.max_samples := 1; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.inst := kh3; - start_dds; - wait_on_dds; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NEW, I3:NOT_NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: READ_NEXT_INSTANCE [WITH NEXT INSTANCE, COMPATIBLE SAMPLES] - - Log("DDS Operation READ_NEXT_INSTANCE [MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Instance 3] (Expected ID4)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ_NEXT_INSTANCE; - dds.max_samples := 1; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.inst := kh3; - start_dds; - wait_on_dds; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NEW, I3:NOT_NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: READ [SPECIFIED SSTATE, ANY ISTATE, ANY VIEW] - -- TEST: READ [MAX_SAMPLES > SAMPLES] - - Log("DDS Operation READ [MAX_SAMPLES 20, READ_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE] (Expected ID0,ID1,ID9,ID2,ID3,ID4)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ; - dds.max_samples := 20; - dds.sstate := READ_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - start_dds; - wait_on_dds; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NEW, I3:NOT_NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: READ [SPECIFIED SSTATE, SPECIFIED ISTATE, ANY VIEW] - - Log("DDS Operation READ [MAX_SAMPLES 20, READ_SAMPLE_STATE, NOT_ALIVE_DISPOSED_INSTANCE_STATE, ANY_VIEW_STATE] (Expected ID2,ID3)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ; - dds.max_samples := 20; - dds.sstate := READ_SAMPLE_STATE; - dds.istate := NOT_ALIVE_DISPOSED_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - start_dds; - wait_on_dds; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NEW, I3:NOT_NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: READ [SPECIFIED SSTATE, ANY ISTATE, SPECIFIED VIEW] - -- TEST: READ MODIFIES VIEW STATE [READ CURRENT GENERATION] - -- TEST: READ MODIFIES VIEW STATE [READ PREVIOUS GENERATION] - - Log("DDS Operation READ [MAX_SAMPLES 20, READ_SAMPLE_STATE, ANY_INSTANCE_STATE, NEW_VIEW_STATE] (Expected ID2,ID4)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ; - dds.max_samples := 20; - dds.sstate := READ_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := NEW_VIEW_STATE; - start_dds; - wait_on_dds; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NEW, I3:NOT_NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: READ [SPECIFIED SSTATE, SPECIFIED ISTATE, SPECIFIED VIEW] - - Log("DDS Operation READ [MAX_SAMPLES 20, READ_SAMPLE_STATE, NOT_ALIVE_DISPOSED_INSTANCE_STATE, NEW_VIEW_STATE] (Expected ID2)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ; - dds.max_samples := 20; - dds.sstate := READ_SAMPLE_STATE; - dds.istate := NOT_ALIVE_DISPOSED_INSTANCE_STATE; - dds.vstate := NEW_VIEW_STATE; - start_dds; - wait_on_dds; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NEW, I3:NOT_NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: READ [ANY SSTATE, ANY ISTATE, SPECIFIED VIEW] - - Log("DDS Operation READ [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, NOT_NEW_VIEW_STATE] (Expected ID0,ID1,ID9,ID3,ID6)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := NOT_NEW_VIEW_STATE; - start_dds; - wait_on_dds; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NEW, I3:NOT_NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: READ [ANY SSTATE, SPECIFIED ISTATE, SPECIFIED VIEW] - - Log("DDS Operation READ [MAX_SAMPLES 20, ANY_SAMPLE_STATE, NOT_ALIVE_DISPOSED_INSTANCE_STATE, NOT_NEW_VIEW_STATE] (Expected ID3,ID6)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := NOT_ALIVE_DISPOSED_INSTANCE_STATE; - dds.vstate := NOT_NEW_VIEW_STATE; - start_dds; - wait_on_dds; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NEW, I3:NOT_NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: READ [ANY SSTATE, SPECIFIED ISTATE, ANY VIEW] - - Log("DDS Operation READ [MAX_SAMPLES 20, ANY_SAMPLE_STATE, NOT_ALIVE_DISPOSED_INSTANCE_STATE, ANY_VIEW_STATE] (Expected ID2,ID5,ID10,ID11,ID3,ID6)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := NOT_ALIVE_DISPOSED_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - start_dds; - wait_on_dds; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: READ_INSTANCE [UNKNOWN INSTANCE] - - Log("DDS Operation READ_INSTANCE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Unknown Instance] (Bad Parameter)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ_INSTANCE; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.inst := kh5; - dds.ret_code := RETCODE_BAD_PARAMETER; - start_dds; - wait_on_dds; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: READ_INSTANCE [KNOWN INSTANCE, UNCOMPATIBLE SAMPLES] - - Log("DDS Operation READ_INSTANCE [MAX_SAMPLES 20, NOT_READ_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Instance 1] (No Data)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ_INSTANCE; - dds.max_samples := 20; - dds.sstate := NOT_READ_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.inst := kh1; - dds.ret_code := RETCODE_NO_DATA; - start_dds; - wait_on_dds; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: READ_NEXT_INSTANCE [WITH NEXT INSTANCE, UNCOMPATIBLE SAMPLES] - - Log("DDS Operation READ_NEXT_INSTANCE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, NOT_ALIVE_DISPOSED_INSTANCE_STATE, ANY_VIEW_STATE, Instance 2] (No Data)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ_NEXT_INSTANCE; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := NOT_ALIVE_DISPOSED_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.inst := kh2; - dds.ret_code := RETCODE_NO_DATA; - start_dds; - wait_on_dds; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: READ_NEXT_INSTANCE [WITH NEXT INSTANCE, WITH COMPATIBLE SAMPLE, NOT DIRECT NEXT INSTANCE] - - Log("DDS Operation READ_NEXT_INSTANCE [MAX_SAMPLES 20, NOT_READ_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Instance 3] (Expected ID7,ID8)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ_NEXT_INSTANCE; - dds.max_samples := 20; - dds.sstate := NOT_READ_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.inst := kh3; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: READ [NO COMPATIBLE SAMPLES] - - Log("DDS Operation READ [MAX_SAMPLES 20, ANY_SAMPLE_STATE, NOT_ALIVE_NO_WRITERS_INSTANCE_STATE, ANY_VIEW_STATE] (No Data)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := NOT_ALIVE_NO_WRITERS_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.ret_code := RETCODE_NO_DATA; - start_dds; - wait_on_dds; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: READ_NEXT_SAMPLE [WITHOUT UNREAD SAMPLE] - - Log("DDS Operation READ_NEXT_SAMPLE (No Data)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ_NEXT_SAMPLE; - dds.ret_code := RETCODE_NO_DATA; - start_dds; - wait_on_dds; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: TAKE - - Log("DDS Operation TAKE [MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE] (Expected ID0)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE; - dds.max_samples := 1; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - -- MEM: I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: TAKE_INSTANCE - - Log("DDS Operation TAKE_INSTANCE [MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Instance 2] (Expected ID2)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE_INSTANCE; - dds.max_samples := 1; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.inst := kh2; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - -- MEM: I1S2-(1), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: TAKE_NEXT_INSTANCE - -- TEST: READ_NEXT_INSTANCE [HANDLE_NIL] - - Log("DDS Operation TAKE_NEXT_INSTANCE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, HANDLE_NIL] (Expected ID3,ID6)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE_NEXT_INSTANCE; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.inst := HANDLE_NIL; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - -- MEM: I1S2-(1), I4S1(4), I2S2-(5), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: TAKE REMOVES SAMPLE - -- TEST: READ_INSTANCE [NO SAMPLES] - - Log("DDS Operation READ_INSTANCE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Instance 3] (No Data)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ_INSTANCE; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.inst := kh3; - dds.ret_code := RETCODE_NO_DATA; - start_dds; - wait_on_dds; - -- MEM: I1S2-(1), I4S1(4), I2S2-(5), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - Log("DDS Operation TAKE_NEXT_INSTANCE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Instance 3] (Expected ID4,ID7,ID8)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE_NEXT_INSTANCE; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.inst := kh3; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - -- MEM: I1S2-(1), I2S2-(5), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: TAKE_INSTANCE [NO SAMPLES] - - Log("DDS Operation TAKE_INSTANCE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Instance 4] (No Data)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE_INSTANCE; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.inst := kh4; - dds.ret_code := RETCODE_NO_DATA; - start_dds; - wait_on_dds; - -- MEM: I1S2-(1), I2S2-(5), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - Log("DDS Operation TAKE_NEXT_INSTANCE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Instance 4] (Expected ID5,ID10,ID11)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE_NEXT_INSTANCE; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.inst := kh4; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - -- MEM: I1S2-(1), I1S3(9) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - Log("DDS Operation READ_INSTANCE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Instance 2] (No Data)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ_INSTANCE; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.inst := kh2; - dds.ret_code := RETCODE_NO_DATA; - start_dds; - wait_on_dds; - -- MEM: I1S2-(1), I1S3(9) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: READ_NEXT_INSTANCE [WITH SAMPLES, WITHOUT NEXT INSTANCE] - - Log("DDS Operation READ_NEXT_INSTANCE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Instance 1] (No Data)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ_NEXT_INSTANCE; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.inst := kh1; - dds.ret_code := RETCODE_NO_DATA; - start_dds; - wait_on_dds; - -- MEM: I1S2-(1), I1S3(9) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - Log("DDS Operation TAKE_NEXT_INSTANCE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Instance 2] (Expected ID1,ID9)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE_NEXT_INSTANCE; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.inst := kh2; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - -- MEM: - - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: GET ALL DATA WITH READ_NEXT_INSTANCE - -- TEST: READ [NO SAMPLES] - - Log("DDS Operation READ [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE] (No Data)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.ret_code := RETCODE_NO_DATA; - start_dds; - wait_on_dds; - -- MEM: - - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: TAKE [NO SAMPLES] - - Log("DDS Operation TAKE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE] (No Data)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.ret_code := RETCODE_NO_DATA; - start_dds; - wait_on_dds; - -- MEM: - - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: READ_NEXT_INSTANCE [NO SAMPLE] - - Log("DDS Operation READ_NEXT_INSTANCE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, HANDLE_NIL] (No Data)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ_NEXT_INSTANCE; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.inst := HANDLE_NIL; - dds.ret_code := RETCODE_NO_DATA; - start_dds; - wait_on_dds; - -- MEM: - - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: TAKE_NEXT_INSTANCE [NO SAMPLE] - - Log("DDS Operation TAKE_NEXT_INSTANCE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, HANDLE_NIL] (No Data)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE_NEXT_INSTANCE; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.inst := HANDLE_NIL; - dds.ret_code := RETCODE_NO_DATA; - start_dds; - wait_on_dds; - -- MEM: - - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: READ_NEXT_SAMPLE [NO SAMPLE] - - Log("DDS Operation READ_NEXT_SAMPLE (No Data)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ_NEXT_SAMPLE; - dds.ret_code := RETCODE_NO_DATA; - start_dds; - wait_on_dds; - -- MEM: - - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: TAKE_NEXT_SAMPLE [NO SAMPLE] - - Log("DDS Operation TAKE_NEXT_SAMPLE (No Data)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE_NEXT_SAMPLE; - dds.ret_code := RETCODE_NO_DATA; - start_dds; - wait_on_dds; - -- MEM: - - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - Log("Current Time: 12s", INFO); - check_time <= gen_duration(12,0); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait_on_idle; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh2; - cc.payload := gen_payload(kh2,10); - cc.src_timestamp := gen_duration(12,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 2, Writer 1, Aligned Payload, ID 12] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 1; - rtps.ret_code := OK; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I2S5(12) - -- ISTATE: I1:ALIVE, I2:ALIVE, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: TAKE_NEXT_SAMPLE - - Log("DDS Operation TAKE_NEXT_SAMPLE (Expected ID12)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE_NEXT_SAMPLE; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - -- MEM: - - -- ISTATE: I1:ALIVE, I2:ALIVE, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - Log("DDS Operation READ [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE] (No Data)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.ret_code := RETCODE_NO_DATA; - start_dds; - wait_on_dds; - -- MEM: - - -- ISTATE: I1:ALIVE, I2:ALIVE, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - wait_on_completion; - TranscriptOpen(RESULTS_FILE, APPEND_MODE); - SetTranscriptMirror; - ReportAlerts; - TranscriptClose; - std.env.stop; - wait; - end process; - - clock_prc : process - begin - clk <= '0'; - wait for 25 ns; - clk <= '1'; - wait for 25 ns; - end process; - - alert_prc : process(all) - begin - if rising_edge(clk) then - -- TODO - end if; - end process; - - dds_prc : process(all) - variable col : COLLECTION_TYPE := DEFAULT_COLLECTION; - begin - if rising_edge(clk) then - dds_done <= '0'; - case (dds_stage ) is - when IDLE => - if (dds_start = '1') then - dds_stage <= START; - else - dds_done <= '1'; - end if; - when START => - if (ack_dds = '1') then - dds_stage <= DONE; - dds_cnt <= 0; - end if; - when DONE => - if (done_dds = '1') then - AffirmIfEqual(ret_id, return_code_dds, dds.ret_code); - case (dds.ret_code) is - when RETCODE_OK => - gen_collection(mem, col, dds, INSTANCE_PRESENTATION_QOS, FALSE); - dds_stage <= CHECK_SI; - dds_cnt <= 0; - when others => - dds_stage <= IDLE; - end case; - end if; - when CHECK_SI => - if (si_valid = '1') then - Log("Read Sample ID" & to_string(to_integer(si_source_timestamp(0))), DEBUG); - AffirmIfEqual(sstate_id, si_sample_state, col.s(dds_cnt).sstate); - AffirmIfEqual(vstate_id, si_view_state, col.s(dds_cnt).vstate); - AffirmIfEqual(istate_id, si_instance_state, col.s(dds_cnt).istate); - AffirmIfEqual(ts_id, to_unsigned(si_source_timestamp), to_unsigned(col.s(dds_cnt).ts)); - AffirmIfEqual(inst_id, to_unsigned(si_instance_handle), to_unsigned(col.s(dds_cnt).inst)); - AffirmIfEqual(pub_id, to_unsigned(si_publication_handle), to_unsigned(HANDLE_NIL)); - AffirmIfEqual(dis_gen_cnt_id, si_disposed_generation_count, std_logic_vector(to_unsigned(col.s(dds_cnt).dis_gen_cnt,WORD_WIDTH))); - AffirmIfEqual(no_w_gen_cnt_id, si_no_writers_generation_count, std_logic_vector(to_unsigned(col.s(dds_cnt).no_w_gen_cnt,WORD_WIDTH))); - AffirmIfEqual(srank_id, si_sample_rank, std_logic_vector(to_unsigned(col.s(dds_cnt).srank,WORD_WIDTH))); - AffirmIfEqual(grank_id, si_generation_rank, std_logic_vector(to_unsigned(col.s(dds_cnt).grank,WORD_WIDTH))); - AffirmIfEqual(agrank_id, si_absolute_generation_rank, std_logic_vector(to_unsigned(col.s(dds_cnt).agrank,WORD_WIDTH))); - if (si_valid_data = '1') then - AffirmIf(valid_id, col.s(dds_cnt).data /= EMPTY_TEST_PACKET, "Sample with Data not expected"); - dds_stage <= CHECK_DATA; - dds_cnt2 <= 0; - else - AffirmIf(valid_id, col.s(dds_cnt).data = EMPTY_TEST_PACKET, "Sample with Data expected"); - if (dds_cnt = col.len-1) then - -- DONE - dds_stage <= WAIT_EOC; - else - dds_cnt <= dds_cnt + 1; - end if; - end if; - end if; - AffirmIf(eoc_id, eoc = '0', "EOC pulled high"); - when CHECK_DATA => - if (valid_out_dds = '1') then - AffirmIfEqual(data_id, data_out_dds, col.s(dds_cnt).data.data(dds_cnt2)); - dds_cnt2 <= dds_cnt2 + 1; - if (dds_cnt2 = col.s(dds_cnt).data.length-1) then - AlertIf(data_id, last_word_out_dds /= '1', "Last Word Signal not pulled High", ERROR); - if (dds_cnt = col.len-1) then - -- DONE - dds_stage <= WAIT_EOC; - else - dds_stage <= CHECK_SI; - dds_cnt <= dds_cnt + 1; - end if; - end if; - end if; - when WAIT_EOC => - if (eoc = '1') then - dds_stage <= IDLE; - end if; - end case; - end if; - - -- DEFAULT - start_dds <= '0'; - opcode_dds <= NOP; - instance_state_dds <= ANY_INSTANCE_STATE; - view_state_dds <= ANY_VIEW_STATE; - sample_state_dds <= ANY_SAMPLE_STATE; - instance_handle_dds <= HANDLE_NIL; - max_samples_dds <= (others => '0'); - get_data_dds <= '0'; - ready_out_dds <= '0'; - - - case (dds_stage ) is - when START => - start_dds <= '1'; - opcode_dds <= dds.opcode; - instance_state_dds <= dds.istate; - view_state_dds <= dds.vstate; - sample_state_dds <= dds.sstate; - instance_handle_dds <= dds.inst; - max_samples_dds <= std_logic_vector(to_unsigned(dds.max_samples, WORD_WIDTH)); - when CHECK_SI => - if (si_valid = '1' and si_valid_data = '1') then - get_data_dds <= '1'; - end if; - when CHECK_DATA => - ready_out_dds <= '1'; - when others => - null; - end case; - end process; - - rtps_prc : process(all) - variable stimulus : TEST_PACKET_TYPE := EMPTY_TEST_PACKET; - begin - if rising_edge(clk) then - rtps_done <= '0'; - case (rtps_stage) is - when IDLE => - if (rtps_start = '1') then - rtps_stage <= START; - else - rtps_done <= '1'; - end if; - when START => - if (ack_rtps = '1') then - case (rtps.opcode) is - when ADD_CACHE_CHANGE => - gen_add_cache_change_dds(rtps.cc, rtps.lifespan, rtps.writer_pos, stimulus); - rtps_stage <= PUSH; - when others => - rtps_stage <= DONE; - end case; - end if; - when PUSH => - if (ready_in_rtps = '1') then - rtps_cnt <= rtps_cnt + 1; - if (rtps_cnt = stimulus.length-1) then - rtps_stage <= DONE; - end if; - end if; - when DONE => - if (done_rtps = '1') then - AffirmIfEqual(ret_id, HISTORY_CACHE_RESPONSE_TYPE'pos(ret_rtps), HISTORY_CACHE_RESPONSE_TYPE'pos(rtps.ret_code)); - rtps_stage <= IDLE; - end if; - end case; - end if; - - -- DEFAULT - start_rtps <= '0'; - opcode_rtps <= NOP; - valid_in_rtps <= '0'; - last_word_in_rtps <= '0'; - data_in_rtps <= (others => '0'); - - case (rtps_stage) is - when START => - start_rtps <= '1'; - opcode_rtps <= rtps.opcode; - case (rtps.opcode) is - when REMOVE_WRITER => - data_in_rtps <= std_logic_vector(to_unsigned(rtps.writer_pos,WORD_WIDTH)); - when others => - null; - end case; - when PUSH => - valid_in_rtps <= '1'; - data_in_rtps <= stimulus.data(rtps_cnt); - last_word_in_rtps <= stimulus.last(rtps_cnt); - when others => - null; - end case; - end process; - - watchdog : process - begin - wait for 1 ms; - Alert("Test timeout", FAILURE); - std.env.stop; - end process; - -end architecture; \ No newline at end of file diff --git a/src/Tests/Level_0/L0_dds_reader_test3_arzkrto.vhd b/src/Tests/Level_0/L0_dds_reader_test3_arzkrto.vhd deleted file mode 100644 index f96971e..0000000 --- a/src/Tests/Level_0/L0_dds_reader_test3_arzkrto.vhd +++ /dev/null @@ -1,1481 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library osvvm; -- Utility Library -context osvvm.OsvvmContext; - -use work.rtps_package.all; -use work.user_config.all; -use work.rtps_config_package.all; -use work.rtps_test_package.all; - --- This testbench tests the DDS handling of the DDS Reader. It tests the correctness of the DDS READ, TAKE, READ_NEXT_SAMPLE, TAKE_NEXT_SAMPLE, --- READ_INSTANCE, TAKE_INSTANCE, READ_NEXT_INSTANCE, TAKE_NEXT_INSTANCE Operations. --- More specifically the testbench covers following tests: --- TEST: READ [NO COMPATIBLE SAMPLES] --- TEST: READ [NO SAMPLES] --- TEST: READ [MAX_SAMPLES < SAMPLES] --- TEST: READ [MAX_SAMPLES > SAMPLES] --- TEST: TAKE [NO SAMPLES] --- TEST: TAKE --- TEST: READ [ANY SSTATE, ANY ISTATE, ANY VIEW] --- TEST: READ [ANY SSTATE, ANY ISTATE, SPECIFIED VIEW] --- TEST: READ [ANY SSTATE, SPECIFIED ISTATE, ANY VIEW] --- TEST: READ [ANY SSTATE, SPECIFIED ISTATE, SPECIFIED VIEW] --- TEST: READ [SPECIFIED SSTATE, ANY ISTATE, ANY VIEW] --- TEST: READ [SPECIFIED SSTATE, ANY ISTATE, SPECIFIED VIEW] --- TEST: READ [SPECIFIED SSTATE, SPECIFIED ISTATE, ANY VIEW] --- TEST: READ [SPECIFIED SSTATE, SPECIFIED ISTATE, SPECIFIED VIEW] --- TEST: READ_NEXT_SAMPLE [WITH UNREAD SAMPLE] --- TEST: READ_NEXT_SAMPLE [WITHOUT UNREAD SAMPLE] --- TEST: READ_NEXT_SAMPLE [NO SAMPLE] --- TEST: TAKE_NEXT_SAMPLE [NO SAMPLE] --- TEST: TAKE_NEXT_SAMPLE --- TEST: READ_INSTANCE [UNKNOWN INSTANCE] --- TEST: READ_INSTANCE [KNOWN INSTANCE, UNCOMPATIBLE SAMPLES] --- TEST: READ_INSTANCE [KNOWN INSTANCE, COMPATIBLE SAMPLES] --- TEST: READ_INSTANCE [NO SAMPLES] --- TEST: TAKE_INSTANCE [NO SAMPLES] --- TEST: TAKE_INSTANCE --- TEST: READ_NEXT_INSTANCE [WITH SAMPLES, WITHOUT NEXT INSTANCE] --- TEST: READ_NEXT_INSTANCE [WITH NEXT INSTANCE, UNCOMPATIBLE SAMPLES] --- TEST: READ_NEXT_INSTANCE [WITH NEXT INSTANCE, COMPATIBLE SAMPLES] --- TEST: READ_NEXT_INSTANCE [HANDLE_NIL] --- TEST: READ_NEXT_INSTANCE [WITH NEXT INSTANCE, WITH COMPATIBLE SAMPLE, NOT DIRECT NEXT INSTANCE] --- TEST: READ_NEXT_INSTANCE [NO SAMPLE] --- TEST: TAKE_NEXT_INSTANCE [NO SAMPLE] --- TEST: TAKE_NEXT_INSTANCE --- TEST: GET ALL DATA WITH READ_NEXT_INSTANCE --- TEST: READ MARKS SAMPLES AS READ --- TEST: TAKE REMOVES SAMPLE --- TEST: READ MODIFIES VIEW STATE [READ PREVIOUS GENERATION] --- TEST: READ MODIFIES VIEW STATE [READ CURRENT GENERATION] - -entity L0_dds_reader_test3_arzkrto is -end entity; - - -architecture testbench of L0_dds_reader_test3_arzkrto is - - -- *CONSTANT DECLARATION* - constant MAX_REMOTE_ENDPOINTS : natural := 3; - - -- *TYPE DECLARATION* - type DDS_STAGE_TYPE is (IDLE, START, DONE, CHECK_SI, CHECK_DATA, WAIT_EOC); - type RTPS_STAGE_TYPE is (IDLE, START, PUSH, DONE); - - -- *SIGNAL DECLARATION* - signal clk : std_logic := '0'; - signal reset : std_logic := '1'; - signal check_time : TIME_TYPE := TIME_ZERO; - signal start_rtps, start_dds, ack_rtps, ack_dds, done_rtps, done_dds : std_logic := '0'; - signal opcode_rtps : HISTORY_CACHE_OPCODE_TYPE := NOP; - signal opcode_dds : DDS_READER_OPCODE_TYPE := NOP; - signal ret_rtps : HISTORY_CACHE_RESPONSE_TYPE := ERROR; - signal ready_in_rtps, valid_in_rtps, last_word_in_rtps : std_logic := '0'; - signal ready_out_dds, valid_out_dds, last_word_out_dds : std_logic := '0'; - signal data_in_rtps, data_out_dds : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); - signal get_data_dds, si_valid_data, si_valid, eoc : std_logic := '0'; - signal return_code_dds : std_logic_vector(RETURN_CODE_WIDTH-1 downto 0) := (others => '0'); - signal status : std_logic_vector(STATUS_KIND_WIDTH-1 downto 0) := (others => '0'); - signal instance_state_dds, si_instance_state : std_logic_vector(INSTANCE_STATE_KIND_WIDTH-1 downto 0) := ANY_INSTANCE_STATE; - signal view_state_dds, si_view_state : std_logic_vector(VIEW_STATE_KIND_WIDTH-1 downto 0) := ANY_VIEW_STATE; - signal sample_state_dds, si_sample_state : std_logic_vector(SAMPLE_STATE_KIND_WIDTH-1 downto 0) := ANY_SAMPLE_STATE; - signal instance_handle_dds, si_instance_handle : INSTANCE_HANDLE_TYPE := HANDLE_NIL; - signal max_samples_dds : std_logic_vector(MAX_SAMPLES_WIDTH-1 downto 0) := (others => '0'); - signal si_source_timestamp : TIME_TYPE := TIME_INVALID; - signal si_publication_handle : INSTANCE_HANDLE_TYPE := HANDLE_NIL; - signal si_disposed_generation_count : std_logic_vector(DISPOSED_GENERATION_COUNT_WIDTH-1 downto 0) := (others => '0'); - signal si_no_writers_generation_count : std_logic_vector(NO_WRITERS_GENERATION_COUNT_WIDTH-1 downto 0) := (others => '0'); - signal si_sample_rank : std_logic_vector(SAMPLE_RANK_WIDTH-1 downto 0) := (others => '0'); - signal si_generation_rank : std_logic_vector(GENERATION_RANK_WIDTH-1 downto 0) := (others => '0'); - signal si_absolute_generation_rank: std_logic_vector(ABSOLUTE_GENERATION_COUNT_WIDTH-1 downto 0) := (others => '0'); - - signal dds_start , dds_done , rtps_start, rtps_done : std_logic := '0'; - signal dds_cnt, dds_cnt2, rtps_cnt : natural := 0; - signal dds_stage : DDS_STAGE_TYPE := IDLE; - signal rtps_stage : RTPS_STAGE_TYPE := IDLE; - shared variable dds : DDS_READER_TEST_TYPE := DEFAULT_DDS_READER_TEST; - shared variable rtps : RTPS_READER_TEST_TYPE := DEFAULT_RTPS_READER_TEST; - shared variable mem : DDS_READER_MEM_TYPE := DEFAULT_DDS_READER_MEM; - signal data_id, ret_id, sstate_id, vstate_id, istate_id, inst_id, ts_id, pub_id, dis_gen_cnt_id, no_w_gen_cnt_id, srank_id, grank_id, agrank_id, eoc_id, valid_id : AlertLogIDType; - - -- *FUNCTION DECLARATION* - function extract_key_hash (payload : TEST_PACKET_TYPE) return INSTANCE_HANDLE_TYPE is - variable ret : INSTANCE_HANDLE_TYPE := HANDLE_NIL; - begin - for i in 0 to 3 loop - ret(i) := not payload.data(i); - end loop; - - return ret; - end function; - - function gen_sn(input : natural) return SEQUENCENUMBER_TYPE is - variable ret : SEQUENCENUMBER_TYPE; - begin - ret(0) := (others => '0'); - ret(1) := unsigned(int(input, WORD_WIDTH)); - return ret; - end function; - -begin - - -- Unit Under Test - uut : entity work.dds_reader(arch) - generic map ( - TIME_BASED_FILTER_QOS => DURATION_ZERO, - DEADLINE_QOS => DURATION_INFINITE, - MAX_SAMPLES => std_logic_vector(to_unsigned(15,CDR_LONG_WIDTH)), - MAX_INSTANCES => std_logic_vector(to_unsigned(4,CDR_LONG_WIDTH)), - MAX_SAMPLES_PER_INSTANCE => std_logic_vector(to_unsigned(15,CDR_LONG_WIDTH)), - HISTORY_QOS => KEEP_ALL_HISTORY_QOS, - RELIABILITY_QOS => RELIABLE_RELIABILITY_QOS, - PRESENTATION_QOS => TOPIC_PRESENTATION_QOS, - DESTINATION_ORDER_QOS => BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS, - COHERENT_ACCESS => FALSE, - ORDERED_ACCESS => TRUE, - WITH_KEY => TRUE, - PAYLOAD_FRAME_SIZE => 11, - MAX_REMOTE_ENDPOINTS => MAX_REMOTE_ENDPOINTS - ) - port map ( - clk => clk, - reset => reset, - time => check_time, - start_rtps => start_rtps, - opcode_rtps => opcode_rtps, - ack_rtps => ack_rtps, - done_rtps => done_rtps, - ret_rtps => ret_rtps, - data_in_rtps => data_in_rtps, - valid_in_rtps => valid_in_rtps, - ready_in_rtps => ready_in_rtps, - last_word_in_rtps => last_word_in_rtps, - start_dds => start_dds, - ack_dds => ack_dds, - opcode_dds => opcode_dds, - instance_state_dds => instance_state_dds, - view_state_dds => view_state_dds, - sample_state_dds => sample_state_dds, - instance_handle_dds => instance_handle_dds, - max_samples_dds => max_samples_dds, - get_data_dds => get_data_dds, - done_dds => done_dds, - return_code_dds => return_code_dds, - ready_out_dds => ready_out_dds, - valid_out_dds => valid_out_dds, - data_out_dds => data_out_dds, - last_word_out_dds => last_word_out_dds, - sample_info.sample_state => si_sample_state, - sample_info.view_state => si_view_state, - sample_info.instance_state => si_instance_state, - sample_info.source_timestamp => si_source_timestamp, - sample_info.instance_handle => si_instance_handle, - sample_info.publication_handle => si_publication_handle, - sample_info.disposed_generation_count => si_disposed_generation_count, - sample_info.no_writers_generation_count => si_no_writers_generation_count, - sample_info.sample_rank => si_sample_rank, - sample_info.generation_rank => si_generation_rank, - sample_info.absolute_generation_rank => si_absolute_generation_rank, - sample_info.valid_data => si_valid_data, - sample_info_valid => si_valid, - sample_info_ack => '1', - eoc => eoc, - status => status - ); - - stimulus_prc : process - variable RV : RandomPType; - variable cc : CACHE_CHANGE_TYPE := DEFAULT_CACHE_CHANGE; - variable s : SAMPLE_TYPE := DEFAULT_SAMPLE; - variable kh1, kh2, kh3, kh4, kh5 : INSTANCE_HANDLE_TYPE := HANDLE_NIL; - - alias idle_sig is <>; - - impure function gen_payload(key_hash : INSTANCE_HANDLE_TYPE; len : natural) return TEST_PACKET_TYPE is - variable ret : TEST_PACKET_TYPE := EMPTY_TEST_PACKET; - begin - assert (len >= 4) report "Payload length has to be at least 16 Bytes long" severity FAILURE; - - for i in 0 to len-1 loop - if (i < 4) then - -- NOTE: Beginning of payload is negated key to allow deterministic Key Hash generation from the kh_prc - ret.data(ret.length) := not key_hash(i); - else - ret.data(ret.length) := RV.RandSlv(WORD_WIDTH); - end if; - ret.length := ret.length + 1; - end loop; - ret.last(ret.length-1) := '1'; - - return ret; - end function; - - impure function gen_key_hash return KEY_HASH_TYPE is - variable ret : KEY_HASH_TYPE := KEY_HASH_NIL; - begin - for i in 0 to KEY_HASH_TYPE'length-1 loop - ret(i) := RV.RandSlv(WORD_WIDTH); - end loop; - return ret; - end function; - - procedure start_dds is - begin - dds_start <= '1'; - wait until rising_edge(clk); - dds_start <= '0'; - wait until rising_edge(clk); - end procedure; - - procedure start_rtps is - begin - rtps_start <= '1'; - wait until rising_edge(clk); - rtps_start <= '0'; - wait until rising_edge(clk); - end procedure; - - procedure wait_on_dds is - begin - if (dds_done /= '1') then - wait until dds_done = '1'; - end if; - end procedure; - - procedure wait_on_rtps is - begin - if (rtps_done /= '1') then - wait until rtps_done = '1'; - end if; - end procedure; - - procedure wait_on_completion is - begin - if (rtps_done /= '1' or dds_done /= '1') then - wait until rtps_done = '1' and dds_done = '1'; - end if; - end procedure; - - -- NOTE: This procedure waits until the idle_sig is high for at least - -- two consecutive clock cycles. - procedure wait_on_idle is - variable first : boolean := TRUE; - begin - loop - if (idle_sig /= '1') then - wait until idle_sig = '1'; - elsif (not first) then - exit; - end if; - wait until rising_edge(clk); - wait until rising_edge(clk); - first := FALSE; - end loop; - end procedure; - - begin - - SetAlertLogName("L0_dds_reader_test3_arzkrto - (KEEP ALL, Reliable, Zero TIME_BASED_FILTER, Keyed, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER, ACCESS SCOPE Topic, Ordered) - DDS Handling"); - SetAlertEnable(FAILURE, TRUE); - SetAlertEnable(ERROR, TRUE); - SetAlertEnable(WARNING, TRUE); - SetLogEnable(DEBUG, TRUE); - SetLogEnable(PASSED, FALSE); - SetLogEnable(INFO, TRUE); - RV.InitSeed(RV'instance_name); - sstate_id <= GetAlertLogID("Sample State", ALERTLOG_BASE_ID); - vstate_id <= GetAlertLogID("View State", ALERTLOG_BASE_ID); - istate_id <= GetAlertLogID("Instance State", ALERTLOG_BASE_ID); - ts_id <= GetAlertLogID("Source Timestamp", ALERTLOG_BASE_ID); - inst_id <= GetAlertLogID("Instance Handle", ALERTLOG_BASE_ID); - pub_id <= GetAlertLogID("Publication Hanlde", ALERTLOG_BASE_ID); - dis_gen_cnt_id <= GetAlertLogID("Disposed Generation Count", ALERTLOG_BASE_ID); - no_w_gen_cnt_id <= GetAlertLogID("No Writers Generation Count", ALERTLOG_BASE_ID); - srank_id <= GetAlertLogID("Sample Rank", ALERTLOG_BASE_ID); - grank_id <= GetAlertLogID("Generation Rank", ALERTLOG_BASE_ID); - agrank_id <= GetAlertLogID("Absolute Generation Rank", ALERTLOG_BASE_ID); - eoc_id <= GetAlertLogID("End Of Collection", ALERTLOG_BASE_ID); - valid_id <= GetAlertLogID("Valid Data", ALERTLOG_BASE_ID); - data_id <= GetAlertLogID("Data Out", ALERTLOG_BASE_ID); - ret_id <= GetAlertLogID("Return Code", ALERTLOG_BASE_ID); - - -- Key Hashes - kh1 := (x"F12C31DA", x"E3FE0F3F", x"01F36685", x"446518CA"); - kh2 := (x"BC070AC4", x"0BAB5811", x"14EA8D61", x"F669189B"); - kh3 := (x"0CEAB0C6", x"FA04B9AD", x"A96EB495", x"4E0EB999"); - kh4 := (x"A7EB605C", x"FF4BEF3A", x"3C5E8724", x"CCA0CA67"); - kh5 := gen_key_hash; - - - Log("Initiating Test", INFO); - Log("Current Time: 0s", INFO); - check_time <= TIME_ZERO; - reset <= '1'; - wait until rising_edge(clk); - wait until rising_edge(clk); - reset <= '0'; - -- MEM: - - -- ISTATE: - - -- VIEW: - - -- WRITER: - - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh1; - cc.payload := gen_payload(kh1,10); - cc.src_timestamp := gen_duration(0,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Aligned Payload, ID 0] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - rtps.ret_code := OK; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S1(0) - -- ISTATE: I1:ALIVE - -- VIEW: I1:NEW - -- WRITER: W0:I1 - - Log("Current Time: 1s", INFO); - check_time <= gen_duration(1,0); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait_on_idle; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_DISPOSED; - cc.instance := kh1; - cc.payload := gen_payload(kh1,5); - cc.src_timestamp := gen_duration(1,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Instance 1, Writer 0, ID 1] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - rtps.ret_code := OK; - s := to_sample(cc,NOT_ALIVE_DISPOSED_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S1(0), I1S2-(1) - -- ISTATE: I1:DISPOSED - -- VIEW: I1:NEW - -- WRITER: W0:I1 - - Log("Current Time: 2s", INFO); - check_time <= gen_duration(2,0); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait_on_idle; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh2; - cc.payload := gen_payload(kh2,10); - cc.src_timestamp := gen_duration(2,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 2, Writer 1, Aligned Payload, ID 2] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 1; - rtps.ret_code := OK; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S1(0), I1S2-(1), I2S1(2) - -- ISTATE: I1:DISPOSED, I2:ALIVE - -- VIEW: I1:NEW, I2:NEW - -- WRITER: W0:I1, W1:I2 - - Log("Current Time: 3s", INFO); - check_time <= gen_duration(3,0); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait_on_idle; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh3; - cc.payload := gen_payload(kh3,10); - cc.src_timestamp := gen_duration(3,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 3, Writer 2, Aligned Payload, ID 3] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 2; - rtps.ret_code := OK; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3) - -- ISTATE: I1:DISPOSED, I2:ALIVE, I3:ALIVE - -- VIEW: I1:NEW, I2:NEW, I3:NEW - -- WRITER: W0:I1, W1:I2, W2:I3 - - Log("Current Time: 4s", INFO); - check_time <= gen_duration(4,0); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait_on_idle; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh4; - cc.payload := gen_payload(kh4,10); - cc.src_timestamp := gen_duration(4,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 4, Writer 2, Aligned Payload, ID 4] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 2; - rtps.ret_code := OK; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), - -- ISTATE: I1:DISPOSED, I2:ALIVE, I3:ALIVE, I4:ALIVE - -- VIEW: I1:NEW, I2:NEW, I3:NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - Log("Current Time: 5s", INFO); - check_time <= gen_duration(5,0); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait_on_idle; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_DISPOSED; - cc.instance := kh2; - cc.payload := gen_payload(kh2,5); - cc.src_timestamp := gen_duration(5,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Instance 2, Writer 1, ID 5] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 1; - rtps.ret_code := OK; - s := to_sample(cc,NOT_ALIVE_DISPOSED_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5) - -- ISTATE: I1:DISPOSED, I2:DISPOSED, I3:ALIVE, I4:ALIVE - -- VIEW: I1:NEW, I2:NEW, I3:NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - Log("Current Time: 6s", INFO); - check_time <= gen_duration(6,0); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait_on_idle; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_DISPOSED; - cc.instance := kh3; - cc.payload := gen_payload(kh3,5); - cc.src_timestamp := gen_duration(6,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Instance 3, Writer 2, ID 6] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 2; - rtps.ret_code := OK; - s := to_sample(cc,NOT_ALIVE_DISPOSED_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6) - -- ISTATE: I1:DISPOSED, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NEW, I2:NEW, I3:NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - Log("Current Time: 7s", INFO); - check_time <= gen_duration(7,0); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait_on_idle; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_DISPOSED; - cc.instance := kh4; - cc.payload := gen_payload(kh4,5); - cc.src_timestamp := gen_duration(7,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Instance 4, Writer 2, ID 7] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 2; - rtps.ret_code := OK; - s := to_sample(cc,NOT_ALIVE_DISPOSED_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7) - -- ISTATE: I1:DISPOSED, I2:DISPOSED, I3:DISPOSED, I4:DISPOSED - -- VIEW: I1:NEW, I2:NEW, I3:NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - Log("Current Time: 8s", INFO); - check_time <= gen_duration(8,0); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait_on_idle; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh4; - cc.payload := gen_payload(kh4,10); - cc.src_timestamp := gen_duration(8,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 4, Writer 2, Aligned Payload, ID 8] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 2; - rtps.ret_code := OK; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8) - -- ISTATE: I1:DISPOSED, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NEW, I2:NEW, I3:NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - Log("Current Time: 9s", INFO); - check_time <= gen_duration(9,0); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait_on_idle; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh1; - cc.payload := gen_payload(kh1,10); - cc.src_timestamp := gen_duration(9,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Aligned Payload, ID 9] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - rtps.ret_code := OK; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NEW, I2:NEW, I3:NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - Log("Current Time: 10s", INFO); - check_time <= gen_duration(10,0); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait_on_idle; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh2; - cc.payload := gen_payload(kh2,10); - cc.src_timestamp := gen_duration(10,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 2, Writer 1, Aligned Payload, ID 10] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 1; - rtps.ret_code := OK; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10) - -- ISTATE: I1:ALIVE, I2:ALIVE, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NEW, I2:NEW, I3:NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - Log("Current Time: 11s", INFO); - check_time <= gen_duration(11,0); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait_on_idle; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_DISPOSED; - cc.instance := kh2; - cc.payload := gen_payload(kh2,5); - cc.src_timestamp := gen_duration(11,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Instance 2, Writer 1, ID 11] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 1; - rtps.ret_code := OK; - s := to_sample(cc,NOT_ALIVE_DISPOSED_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NEW, I2:NEW, I3:NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: READ [MAX_SAMPLES < SAMPLES] - -- TEST: READ [ANY SSTATE, ANY ISTATE, ANY VIEW] - - Log("DDS Operation READ [MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE] (Expected ID0,ID1,ID2)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ; - dds.max_samples := 3; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - start_dds; - wait_on_dds; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NEW, I2:NEW, I3:NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: READ MARKS SAMPLES AS READ - -- TEST: READ_NEXT_SAMPLE [WITH UNREAD SAMPLE] - - Log("DDS Operation READ_NEXT_SAMPLE (Expected ID3)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ_NEXT_SAMPLE; - start_dds; - wait_on_dds; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NEW, I2:NEW, I3:NOT_NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: READ_INSTANCE [KNOWN INSTANCE, COMPATIBLE SAMPLES] - - Log("DDS Operation READ_INSTANCE [MAX_SAMPLES 1, NOT_READ_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Instance 3] (Expected ID9)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ_INSTANCE; - dds.max_samples := 1; - dds.sstate := NOT_READ_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.inst := kh1; - start_dds; - wait_on_dds; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NEW, I3:NOT_NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: READ_NEXT_INSTANCE [WITH NEXT INSTANCE, COMPATIBLE SAMPLES] - - Log("DDS Operation READ_NEXT_INSTANCE [MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Instance 3] (Expected ID4)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ_NEXT_INSTANCE; - dds.max_samples := 1; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.inst := kh3; - start_dds; - wait_on_dds; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NEW, I3:NOT_NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: READ [SPECIFIED SSTATE, ANY ISTATE, ANY VIEW] - -- TEST: READ [MAX_SAMPLES > SAMPLES] - - Log("DDS Operation READ [MAX_SAMPLES 20, READ_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE] (Expected ID0,ID1,ID2,ID3,ID4,ID9)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ; - dds.max_samples := 20; - dds.sstate := READ_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - start_dds; - wait_on_dds; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NEW, I3:NOT_NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: READ [SPECIFIED SSTATE, SPECIFIED ISTATE, ANY VIEW] - - Log("DDS Operation READ [MAX_SAMPLES 20, READ_SAMPLE_STATE, NOT_ALIVE_DISPOSED_INSTANCE_STATE, ANY_VIEW_STATE] (Expected ID2,ID3)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ; - dds.max_samples := 20; - dds.sstate := READ_SAMPLE_STATE; - dds.istate := NOT_ALIVE_DISPOSED_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - start_dds; - wait_on_dds; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NEW, I3:NOT_NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: READ [SPECIFIED SSTATE, ANY ISTATE, SPECIFIED VIEW] - -- TEST: READ MODIFIES VIEW STATE [READ CURRENT GENERATION] - -- TEST: READ MODIFIES VIEW STATE [READ PREVIOUS GENERATION] - - Log("DDS Operation READ [MAX_SAMPLES 20, READ_SAMPLE_STATE, ANY_INSTANCE_STATE, NEW_VIEW_STATE] (Expected ID2,ID4)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ; - dds.max_samples := 20; - dds.sstate := READ_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := NEW_VIEW_STATE; - start_dds; - wait_on_dds; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NEW, I3:NOT_NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: READ [SPECIFIED SSTATE, SPECIFIED ISTATE, SPECIFIED VIEW] - - Log("DDS Operation READ [MAX_SAMPLES 20, READ_SAMPLE_STATE, NOT_ALIVE_DISPOSED_INSTANCE_STATE, NEW_VIEW_STATE] (Expected ID2)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ; - dds.max_samples := 20; - dds.sstate := READ_SAMPLE_STATE; - dds.istate := NOT_ALIVE_DISPOSED_INSTANCE_STATE; - dds.vstate := NEW_VIEW_STATE; - start_dds; - wait_on_dds; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NEW, I3:NOT_NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: READ [ANY SSTATE, ANY ISTATE, SPECIFIED VIEW] - - Log("DDS Operation READ [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, NOT_NEW_VIEW_STATE] (Expected ID0,ID1,ID3,ID6,ID9)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := NOT_NEW_VIEW_STATE; - start_dds; - wait_on_dds; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NEW, I3:NOT_NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: READ [ANY SSTATE, SPECIFIED ISTATE, SPECIFIED VIEW] - - Log("DDS Operation READ [MAX_SAMPLES 20, ANY_SAMPLE_STATE, NOT_ALIVE_DISPOSED_INSTANCE_STATE, NOT_NEW_VIEW_STATE] (Expected ID3,ID6)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := NOT_ALIVE_DISPOSED_INSTANCE_STATE; - dds.vstate := NOT_NEW_VIEW_STATE; - start_dds; - wait_on_dds; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NEW, I3:NOT_NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: READ [ANY SSTATE, SPECIFIED ISTATE, ANY VIEW] - - Log("DDS Operation READ [MAX_SAMPLES 20, ANY_SAMPLE_STATE, NOT_ALIVE_DISPOSED_INSTANCE_STATE, ANY_VIEW_STATE] (Expected ID2,ID3,ID5,ID6,ID10,ID11)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := NOT_ALIVE_DISPOSED_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - start_dds; - wait_on_dds; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: READ_INSTANCE [UNKNOWN INSTANCE] - - Log("DDS Operation READ_INSTANCE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Unknown Instance] (Bad Parameter)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ_INSTANCE; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.inst := kh5; - dds.ret_code := RETCODE_BAD_PARAMETER; - start_dds; - wait_on_dds; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: READ_INSTANCE [KNOWN INSTANCE, UNCOMPATIBLE SAMPLES] - - Log("DDS Operation READ_INSTANCE [MAX_SAMPLES 20, NOT_READ_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Instance 1] (No Data)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ_INSTANCE; - dds.max_samples := 20; - dds.sstate := NOT_READ_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.inst := kh1; - dds.ret_code := RETCODE_NO_DATA; - start_dds; - wait_on_dds; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: READ_NEXT_INSTANCE [WITH NEXT INSTANCE, UNCOMPATIBLE SAMPLES] - - Log("DDS Operation READ_NEXT_INSTANCE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, NOT_ALIVE_DISPOSED_INSTANCE_STATE, ANY_VIEW_STATE, Instance 2] (No Data)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ_NEXT_INSTANCE; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := NOT_ALIVE_DISPOSED_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.inst := kh2; - dds.ret_code := RETCODE_NO_DATA; - start_dds; - wait_on_dds; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: READ_NEXT_INSTANCE [WITH NEXT INSTANCE, WITH COMPATIBLE SAMPLE, NOT DIRECT NEXT INSTANCE] - - Log("DDS Operation READ_NEXT_INSTANCE [MAX_SAMPLES 20, NOT_READ_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Instance 3] (Expected ID7,ID8)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ_NEXT_INSTANCE; - dds.max_samples := 20; - dds.sstate := NOT_READ_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.inst := kh3; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: READ [NO COMPATIBLE SAMPLES] - - Log("DDS Operation READ [MAX_SAMPLES 20, ANY_SAMPLE_STATE, NOT_ALIVE_NO_WRITERS_INSTANCE_STATE, ANY_VIEW_STATE] (No Data)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := NOT_ALIVE_NO_WRITERS_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.ret_code := RETCODE_NO_DATA; - start_dds; - wait_on_dds; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: READ_NEXT_SAMPLE [WITHOUT UNREAD SAMPLE] - - Log("DDS Operation READ_NEXT_SAMPLE (No Data)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ_NEXT_SAMPLE; - dds.ret_code := RETCODE_NO_DATA; - start_dds; - wait_on_dds; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: TAKE - - Log("DDS Operation TAKE [MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE] (Expected ID0)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE; - dds.max_samples := 1; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - -- MEM: I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: TAKE_INSTANCE - - Log("DDS Operation TAKE_INSTANCE [MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Instance 2] (Expected ID2)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE_INSTANCE; - dds.max_samples := 1; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.inst := kh2; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - -- MEM: I1S2-(1), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: TAKE_NEXT_INSTANCE - -- TEST: READ_NEXT_INSTANCE [HANDLE_NIL] - - Log("DDS Operation TAKE_NEXT_INSTANCE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, HANDLE_NIL] (Expected ID3,ID6)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE_NEXT_INSTANCE; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.inst := HANDLE_NIL; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - -- MEM: I1S2-(1), I4S1(4), I2S2-(5), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: TAKE REMOVES SAMPLE - -- TEST: READ_INSTANCE [NO SAMPLES] - - Log("DDS Operation READ_INSTANCE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Instance 3] (No Data)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ_INSTANCE; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.inst := kh3; - dds.ret_code := RETCODE_NO_DATA; - start_dds; - wait_on_dds; - -- MEM: I1S2-(1), I4S1(4), I2S2-(5), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - Log("DDS Operation TAKE_NEXT_INSTANCE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Instance 3] (Expected ID4,ID7,ID8)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE_NEXT_INSTANCE; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.inst := kh3; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - -- MEM: I1S2-(1), I2S2-(5), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: TAKE_INSTANCE [NO SAMPLES] - - Log("DDS Operation TAKE_INSTANCE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Instance 4] (No Data)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE_INSTANCE; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.inst := kh4; - dds.ret_code := RETCODE_NO_DATA; - start_dds; - wait_on_dds; - -- MEM: I1S2-(1), I2S2-(5), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - Log("DDS Operation TAKE_NEXT_INSTANCE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Instance 4] (Expected ID5,ID10,ID11)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE_NEXT_INSTANCE; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.inst := kh4; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - -- MEM: I1S2-(1), I1S3(9) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - Log("DDS Operation READ_INSTANCE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Instance 2] (No Data)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ_INSTANCE; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.inst := kh2; - dds.ret_code := RETCODE_NO_DATA; - start_dds; - wait_on_dds; - -- MEM: I1S2-(1), I1S3(9) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: READ_NEXT_INSTANCE [WITH SAMPLES, WITHOUT NEXT INSTANCE] - - Log("DDS Operation READ_NEXT_INSTANCE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Instance 1] (No Data)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ_NEXT_INSTANCE; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.inst := kh1; - dds.ret_code := RETCODE_NO_DATA; - start_dds; - wait_on_dds; - -- MEM: I1S2-(1), I1S3(9) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - Log("DDS Operation TAKE_NEXT_INSTANCE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Instance 2] (Expected ID1,ID9)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE_NEXT_INSTANCE; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.inst := kh2; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - -- MEM: - - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: GET ALL DATA WITH READ_NEXT_INSTANCE - -- TEST: READ [NO SAMPLES] - - Log("DDS Operation READ [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE] (No Data)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.ret_code := RETCODE_NO_DATA; - start_dds; - wait_on_dds; - -- MEM: - - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: TAKE [NO SAMPLES] - - Log("DDS Operation TAKE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE] (No Data)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.ret_code := RETCODE_NO_DATA; - start_dds; - wait_on_dds; - -- MEM: - - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: READ_NEXT_INSTANCE [NO SAMPLE] - - Log("DDS Operation READ_NEXT_INSTANCE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, HANDLE_NIL] (No Data)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ_NEXT_INSTANCE; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.inst := HANDLE_NIL; - dds.ret_code := RETCODE_NO_DATA; - start_dds; - wait_on_dds; - -- MEM: - - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: TAKE_NEXT_INSTANCE [NO SAMPLE] - - Log("DDS Operation TAKE_NEXT_INSTANCE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, HANDLE_NIL] (No Data)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE_NEXT_INSTANCE; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.inst := HANDLE_NIL; - dds.ret_code := RETCODE_NO_DATA; - start_dds; - wait_on_dds; - -- MEM: - - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: READ_NEXT_SAMPLE [NO SAMPLE] - - Log("DDS Operation READ_NEXT_SAMPLE (No Data)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ_NEXT_SAMPLE; - dds.ret_code := RETCODE_NO_DATA; - start_dds; - wait_on_dds; - -- MEM: - - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: TAKE_NEXT_SAMPLE [NO SAMPLE] - - Log("DDS Operation TAKE_NEXT_SAMPLE (No Data)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE_NEXT_SAMPLE; - dds.ret_code := RETCODE_NO_DATA; - start_dds; - wait_on_dds; - -- MEM: - - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - Log("Current Time: 12s", INFO); - check_time <= gen_duration(12,0); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait_on_idle; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh2; - cc.payload := gen_payload(kh2,10); - cc.src_timestamp := gen_duration(12,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 2, Writer 1, Aligned Payload, ID 12] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 1; - rtps.ret_code := OK; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I2S5(12) - -- ISTATE: I1:ALIVE, I2:ALIVE, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: TAKE_NEXT_SAMPLE - - Log("DDS Operation TAKE_NEXT_SAMPLE (Expected ID12)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE_NEXT_SAMPLE; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - -- MEM: - - -- ISTATE: I1:ALIVE, I2:ALIVE, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - Log("DDS Operation READ [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE] (No Data)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.ret_code := RETCODE_NO_DATA; - start_dds; - wait_on_dds; - -- MEM: - - -- ISTATE: I1:ALIVE, I2:ALIVE, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - wait_on_completion; - TranscriptOpen(RESULTS_FILE, APPEND_MODE); - SetTranscriptMirror; - ReportAlerts; - TranscriptClose; - std.env.stop; - wait; - end process; - - clock_prc : process - begin - clk <= '0'; - wait for 25 ns; - clk <= '1'; - wait for 25 ns; - end process; - - alert_prc : process(all) - begin - if rising_edge(clk) then - -- TODO - end if; - end process; - - dds_prc : process(all) - variable col : COLLECTION_TYPE := DEFAULT_COLLECTION; - begin - if rising_edge(clk) then - dds_done <= '0'; - case (dds_stage ) is - when IDLE => - if (dds_start = '1') then - dds_stage <= START; - else - dds_done <= '1'; - end if; - when START => - if (ack_dds = '1') then - dds_stage <= DONE; - dds_cnt <= 0; - end if; - when DONE => - if (done_dds = '1') then - AffirmIfEqual(ret_id, return_code_dds, dds.ret_code); - case (dds.ret_code) is - when RETCODE_OK => - gen_collection(mem, col, dds, TOPIC_PRESENTATION_QOS, TRUE); - dds_stage <= CHECK_SI; - dds_cnt <= 0; - when others => - dds_stage <= IDLE; - end case; - end if; - when CHECK_SI => - if (si_valid = '1') then - Log("Read Sample ID" & to_string(to_integer(si_source_timestamp(0))), DEBUG); - AffirmIfEqual(sstate_id, si_sample_state, col.s(dds_cnt).sstate); - AffirmIfEqual(vstate_id, si_view_state, col.s(dds_cnt).vstate); - AffirmIfEqual(istate_id, si_instance_state, col.s(dds_cnt).istate); - AffirmIfEqual(ts_id, to_unsigned(si_source_timestamp), to_unsigned(col.s(dds_cnt).ts)); - AffirmIfEqual(inst_id, to_unsigned(si_instance_handle), to_unsigned(col.s(dds_cnt).inst)); - AffirmIfEqual(pub_id, to_unsigned(si_publication_handle), to_unsigned(HANDLE_NIL)); - AffirmIfEqual(dis_gen_cnt_id, si_disposed_generation_count, std_logic_vector(to_unsigned(col.s(dds_cnt).dis_gen_cnt,WORD_WIDTH))); - AffirmIfEqual(no_w_gen_cnt_id, si_no_writers_generation_count, std_logic_vector(to_unsigned(col.s(dds_cnt).no_w_gen_cnt,WORD_WIDTH))); - AffirmIfEqual(srank_id, si_sample_rank, std_logic_vector(to_unsigned(col.s(dds_cnt).srank,WORD_WIDTH))); - AffirmIfEqual(grank_id, si_generation_rank, std_logic_vector(to_unsigned(col.s(dds_cnt).grank,WORD_WIDTH))); - AffirmIfEqual(agrank_id, si_absolute_generation_rank, std_logic_vector(to_unsigned(col.s(dds_cnt).agrank,WORD_WIDTH))); - if (si_valid_data = '1') then - AffirmIf(valid_id, col.s(dds_cnt).data /= EMPTY_TEST_PACKET, "Sample with Data not expected"); - dds_stage <= CHECK_DATA; - dds_cnt2 <= 0; - else - AffirmIf(valid_id, col.s(dds_cnt).data = EMPTY_TEST_PACKET, "Sample with Data expected"); - if (dds_cnt = col.len-1) then - -- DONE - dds_stage <= WAIT_EOC; - else - dds_cnt <= dds_cnt + 1; - end if; - end if; - end if; - AffirmIf(eoc_id, eoc = '0', "EOC pulled high"); - when CHECK_DATA => - if (valid_out_dds = '1') then - AffirmIfEqual(data_id, data_out_dds, col.s(dds_cnt).data.data(dds_cnt2)); - dds_cnt2 <= dds_cnt2 + 1; - if (dds_cnt2 = col.s(dds_cnt).data.length-1) then - AlertIf(data_id, last_word_out_dds /= '1', "Last Word Signal not pulled High", ERROR); - if (dds_cnt = col.len-1) then - -- DONE - dds_stage <= WAIT_EOC; - else - dds_stage <= CHECK_SI; - dds_cnt <= dds_cnt + 1; - end if; - end if; - end if; - when WAIT_EOC => - if (eoc = '1') then - dds_stage <= IDLE; - end if; - end case; - end if; - - -- DEFAULT - start_dds <= '0'; - opcode_dds <= NOP; - instance_state_dds <= ANY_INSTANCE_STATE; - view_state_dds <= ANY_VIEW_STATE; - sample_state_dds <= ANY_SAMPLE_STATE; - instance_handle_dds <= HANDLE_NIL; - max_samples_dds <= (others => '0'); - get_data_dds <= '0'; - ready_out_dds <= '0'; - - - case (dds_stage ) is - when START => - start_dds <= '1'; - opcode_dds <= dds.opcode; - instance_state_dds <= dds.istate; - view_state_dds <= dds.vstate; - sample_state_dds <= dds.sstate; - instance_handle_dds <= dds.inst; - max_samples_dds <= std_logic_vector(to_unsigned(dds.max_samples, WORD_WIDTH)); - when CHECK_SI => - if (si_valid = '1' and si_valid_data = '1') then - get_data_dds <= '1'; - end if; - when CHECK_DATA => - ready_out_dds <= '1'; - when others => - null; - end case; - end process; - - rtps_prc : process(all) - variable stimulus : TEST_PACKET_TYPE := EMPTY_TEST_PACKET; - begin - if rising_edge(clk) then - rtps_done <= '0'; - case (rtps_stage) is - when IDLE => - if (rtps_start = '1') then - rtps_stage <= START; - else - rtps_done <= '1'; - end if; - when START => - if (ack_rtps = '1') then - case (rtps.opcode) is - when ADD_CACHE_CHANGE => - gen_add_cache_change_dds(rtps.cc, rtps.lifespan, rtps.writer_pos, stimulus); - rtps_stage <= PUSH; - when others => - rtps_stage <= DONE; - end case; - end if; - when PUSH => - if (ready_in_rtps = '1') then - rtps_cnt <= rtps_cnt + 1; - if (rtps_cnt = stimulus.length-1) then - rtps_stage <= DONE; - end if; - end if; - when DONE => - if (done_rtps = '1') then - AffirmIfEqual(ret_id, HISTORY_CACHE_RESPONSE_TYPE'pos(ret_rtps), HISTORY_CACHE_RESPONSE_TYPE'pos(rtps.ret_code)); - rtps_stage <= IDLE; - end if; - end case; - end if; - - -- DEFAULT - start_rtps <= '0'; - opcode_rtps <= NOP; - valid_in_rtps <= '0'; - last_word_in_rtps <= '0'; - data_in_rtps <= (others => '0'); - - case (rtps_stage) is - when START => - start_rtps <= '1'; - opcode_rtps <= rtps.opcode; - case (rtps.opcode) is - when REMOVE_WRITER => - data_in_rtps <= std_logic_vector(to_unsigned(rtps.writer_pos,WORD_WIDTH)); - when others => - null; - end case; - when PUSH => - valid_in_rtps <= '1'; - data_in_rtps <= stimulus.data(rtps_cnt); - last_word_in_rtps <= stimulus.last(rtps_cnt); - when others => - null; - end case; - end process; - - watchdog : process - begin - wait for 1 ms; - Alert("Test timeout", FAILURE); - std.env.stop; - end process; - -end architecture; \ No newline at end of file diff --git a/src/Tests/Level_0/L0_dds_reader_test3_arzkrtu.vhd b/src/Tests/Level_0/L0_dds_reader_test3_arzkrtu.vhd deleted file mode 100644 index c14a2eb..0000000 --- a/src/Tests/Level_0/L0_dds_reader_test3_arzkrtu.vhd +++ /dev/null @@ -1,1481 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library osvvm; -- Utility Library -context osvvm.OsvvmContext; - -use work.rtps_package.all; -use work.user_config.all; -use work.rtps_config_package.all; -use work.rtps_test_package.all; - --- This testbench tests the DDS handling of the DDS Reader. It tests the correctness of the DDS READ, TAKE, READ_NEXT_SAMPLE, TAKE_NEXT_SAMPLE, --- READ_INSTANCE, TAKE_INSTANCE, READ_NEXT_INSTANCE, TAKE_NEXT_INSTANCE Operations. --- More specifically the testbench covers following tests: --- TEST: READ [NO COMPATIBLE SAMPLES] --- TEST: READ [NO SAMPLES] --- TEST: READ [MAX_SAMPLES < SAMPLES] --- TEST: READ [MAX_SAMPLES > SAMPLES] --- TEST: TAKE [NO SAMPLES] --- TEST: TAKE --- TEST: READ [ANY SSTATE, ANY ISTATE, ANY VIEW] --- TEST: READ [ANY SSTATE, ANY ISTATE, SPECIFIED VIEW] --- TEST: READ [ANY SSTATE, SPECIFIED ISTATE, ANY VIEW] --- TEST: READ [ANY SSTATE, SPECIFIED ISTATE, SPECIFIED VIEW] --- TEST: READ [SPECIFIED SSTATE, ANY ISTATE, ANY VIEW] --- TEST: READ [SPECIFIED SSTATE, ANY ISTATE, SPECIFIED VIEW] --- TEST: READ [SPECIFIED SSTATE, SPECIFIED ISTATE, ANY VIEW] --- TEST: READ [SPECIFIED SSTATE, SPECIFIED ISTATE, SPECIFIED VIEW] --- TEST: READ_NEXT_SAMPLE [WITH UNREAD SAMPLE] --- TEST: READ_NEXT_SAMPLE [WITHOUT UNREAD SAMPLE] --- TEST: READ_NEXT_SAMPLE [NO SAMPLE] --- TEST: TAKE_NEXT_SAMPLE [NO SAMPLE] --- TEST: TAKE_NEXT_SAMPLE --- TEST: READ_INSTANCE [UNKNOWN INSTANCE] --- TEST: READ_INSTANCE [KNOWN INSTANCE, UNCOMPATIBLE SAMPLES] --- TEST: READ_INSTANCE [KNOWN INSTANCE, COMPATIBLE SAMPLES] --- TEST: READ_INSTANCE [NO SAMPLES] --- TEST: TAKE_INSTANCE [NO SAMPLES] --- TEST: TAKE_INSTANCE --- TEST: READ_NEXT_INSTANCE [WITH SAMPLES, WITHOUT NEXT INSTANCE] --- TEST: READ_NEXT_INSTANCE [WITH NEXT INSTANCE, UNCOMPATIBLE SAMPLES] --- TEST: READ_NEXT_INSTANCE [WITH NEXT INSTANCE, COMPATIBLE SAMPLES] --- TEST: READ_NEXT_INSTANCE [HANDLE_NIL] --- TEST: READ_NEXT_INSTANCE [WITH NEXT INSTANCE, WITH COMPATIBLE SAMPLE, NOT DIRECT NEXT INSTANCE] --- TEST: READ_NEXT_INSTANCE [NO SAMPLE] --- TEST: TAKE_NEXT_INSTANCE [NO SAMPLE] --- TEST: TAKE_NEXT_INSTANCE --- TEST: GET ALL DATA WITH READ_NEXT_INSTANCE --- TEST: READ MARKS SAMPLES AS READ --- TEST: TAKE REMOVES SAMPLE --- TEST: READ MODIFIES VIEW STATE [READ PREVIOUS GENERATION] --- TEST: READ MODIFIES VIEW STATE [READ CURRENT GENERATION] - -entity L0_dds_reader_test3_arzkrtu is -end entity; - - -architecture testbench of L0_dds_reader_test3_arzkrtu is - - -- *CONSTANT DECLARATION* - constant MAX_REMOTE_ENDPOINTS : natural := 3; - - -- *TYPE DECLARATION* - type DDS_STAGE_TYPE is (IDLE, START, DONE, CHECK_SI, CHECK_DATA, WAIT_EOC); - type RTPS_STAGE_TYPE is (IDLE, START, PUSH, DONE); - - -- *SIGNAL DECLARATION* - signal clk : std_logic := '0'; - signal reset : std_logic := '1'; - signal check_time : TIME_TYPE := TIME_ZERO; - signal start_rtps, start_dds, ack_rtps, ack_dds, done_rtps, done_dds : std_logic := '0'; - signal opcode_rtps : HISTORY_CACHE_OPCODE_TYPE := NOP; - signal opcode_dds : DDS_READER_OPCODE_TYPE := NOP; - signal ret_rtps : HISTORY_CACHE_RESPONSE_TYPE := ERROR; - signal ready_in_rtps, valid_in_rtps, last_word_in_rtps : std_logic := '0'; - signal ready_out_dds, valid_out_dds, last_word_out_dds : std_logic := '0'; - signal data_in_rtps, data_out_dds : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); - signal get_data_dds, si_valid_data, si_valid, eoc : std_logic := '0'; - signal return_code_dds : std_logic_vector(RETURN_CODE_WIDTH-1 downto 0) := (others => '0'); - signal status : std_logic_vector(STATUS_KIND_WIDTH-1 downto 0) := (others => '0'); - signal instance_state_dds, si_instance_state : std_logic_vector(INSTANCE_STATE_KIND_WIDTH-1 downto 0) := ANY_INSTANCE_STATE; - signal view_state_dds, si_view_state : std_logic_vector(VIEW_STATE_KIND_WIDTH-1 downto 0) := ANY_VIEW_STATE; - signal sample_state_dds, si_sample_state : std_logic_vector(SAMPLE_STATE_KIND_WIDTH-1 downto 0) := ANY_SAMPLE_STATE; - signal instance_handle_dds, si_instance_handle : INSTANCE_HANDLE_TYPE := HANDLE_NIL; - signal max_samples_dds : std_logic_vector(MAX_SAMPLES_WIDTH-1 downto 0) := (others => '0'); - signal si_source_timestamp : TIME_TYPE := TIME_INVALID; - signal si_publication_handle : INSTANCE_HANDLE_TYPE := HANDLE_NIL; - signal si_disposed_generation_count : std_logic_vector(DISPOSED_GENERATION_COUNT_WIDTH-1 downto 0) := (others => '0'); - signal si_no_writers_generation_count : std_logic_vector(NO_WRITERS_GENERATION_COUNT_WIDTH-1 downto 0) := (others => '0'); - signal si_sample_rank : std_logic_vector(SAMPLE_RANK_WIDTH-1 downto 0) := (others => '0'); - signal si_generation_rank : std_logic_vector(GENERATION_RANK_WIDTH-1 downto 0) := (others => '0'); - signal si_absolute_generation_rank: std_logic_vector(ABSOLUTE_GENERATION_COUNT_WIDTH-1 downto 0) := (others => '0'); - - signal dds_start , dds_done , rtps_start, rtps_done : std_logic := '0'; - signal dds_cnt, dds_cnt2, rtps_cnt : natural := 0; - signal dds_stage : DDS_STAGE_TYPE := IDLE; - signal rtps_stage : RTPS_STAGE_TYPE := IDLE; - shared variable dds : DDS_READER_TEST_TYPE := DEFAULT_DDS_READER_TEST; - shared variable rtps : RTPS_READER_TEST_TYPE := DEFAULT_RTPS_READER_TEST; - shared variable mem : DDS_READER_MEM_TYPE := DEFAULT_DDS_READER_MEM; - signal data_id, ret_id, sstate_id, vstate_id, istate_id, inst_id, ts_id, pub_id, dis_gen_cnt_id, no_w_gen_cnt_id, srank_id, grank_id, agrank_id, eoc_id, valid_id : AlertLogIDType; - - -- *FUNCTION DECLARATION* - function extract_key_hash (payload : TEST_PACKET_TYPE) return INSTANCE_HANDLE_TYPE is - variable ret : INSTANCE_HANDLE_TYPE := HANDLE_NIL; - begin - for i in 0 to 3 loop - ret(i) := not payload.data(i); - end loop; - - return ret; - end function; - - function gen_sn(input : natural) return SEQUENCENUMBER_TYPE is - variable ret : SEQUENCENUMBER_TYPE; - begin - ret(0) := (others => '0'); - ret(1) := unsigned(int(input, WORD_WIDTH)); - return ret; - end function; - -begin - - -- Unit Under Test - uut : entity work.dds_reader(arch) - generic map ( - TIME_BASED_FILTER_QOS => DURATION_ZERO, - DEADLINE_QOS => DURATION_INFINITE, - MAX_SAMPLES => std_logic_vector(to_unsigned(15,CDR_LONG_WIDTH)), - MAX_INSTANCES => std_logic_vector(to_unsigned(4,CDR_LONG_WIDTH)), - MAX_SAMPLES_PER_INSTANCE => std_logic_vector(to_unsigned(15,CDR_LONG_WIDTH)), - HISTORY_QOS => KEEP_ALL_HISTORY_QOS, - RELIABILITY_QOS => RELIABLE_RELIABILITY_QOS, - PRESENTATION_QOS => TOPIC_PRESENTATION_QOS, - DESTINATION_ORDER_QOS => BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS, - COHERENT_ACCESS => FALSE, - ORDERED_ACCESS => FALSE, - WITH_KEY => TRUE, - PAYLOAD_FRAME_SIZE => 11, - MAX_REMOTE_ENDPOINTS => MAX_REMOTE_ENDPOINTS - ) - port map ( - clk => clk, - reset => reset, - time => check_time, - start_rtps => start_rtps, - opcode_rtps => opcode_rtps, - ack_rtps => ack_rtps, - done_rtps => done_rtps, - ret_rtps => ret_rtps, - data_in_rtps => data_in_rtps, - valid_in_rtps => valid_in_rtps, - ready_in_rtps => ready_in_rtps, - last_word_in_rtps => last_word_in_rtps, - start_dds => start_dds, - ack_dds => ack_dds, - opcode_dds => opcode_dds, - instance_state_dds => instance_state_dds, - view_state_dds => view_state_dds, - sample_state_dds => sample_state_dds, - instance_handle_dds => instance_handle_dds, - max_samples_dds => max_samples_dds, - get_data_dds => get_data_dds, - done_dds => done_dds, - return_code_dds => return_code_dds, - ready_out_dds => ready_out_dds, - valid_out_dds => valid_out_dds, - data_out_dds => data_out_dds, - last_word_out_dds => last_word_out_dds, - sample_info.sample_state => si_sample_state, - sample_info.view_state => si_view_state, - sample_info.instance_state => si_instance_state, - sample_info.source_timestamp => si_source_timestamp, - sample_info.instance_handle => si_instance_handle, - sample_info.publication_handle => si_publication_handle, - sample_info.disposed_generation_count => si_disposed_generation_count, - sample_info.no_writers_generation_count => si_no_writers_generation_count, - sample_info.sample_rank => si_sample_rank, - sample_info.generation_rank => si_generation_rank, - sample_info.absolute_generation_rank => si_absolute_generation_rank, - sample_info.valid_data => si_valid_data, - sample_info_valid => si_valid, - sample_info_ack => '1', - eoc => eoc, - status => status - ); - - stimulus_prc : process - variable RV : RandomPType; - variable cc : CACHE_CHANGE_TYPE := DEFAULT_CACHE_CHANGE; - variable s : SAMPLE_TYPE := DEFAULT_SAMPLE; - variable kh1, kh2, kh3, kh4, kh5 : INSTANCE_HANDLE_TYPE := HANDLE_NIL; - - alias idle_sig is <>; - - impure function gen_payload(key_hash : INSTANCE_HANDLE_TYPE; len : natural) return TEST_PACKET_TYPE is - variable ret : TEST_PACKET_TYPE := EMPTY_TEST_PACKET; - begin - assert (len >= 4) report "Payload length has to be at least 16 Bytes long" severity FAILURE; - - for i in 0 to len-1 loop - if (i < 4) then - -- NOTE: Beginning of payload is negated key to allow deterministic Key Hash generation from the kh_prc - ret.data(ret.length) := not key_hash(i); - else - ret.data(ret.length) := RV.RandSlv(WORD_WIDTH); - end if; - ret.length := ret.length + 1; - end loop; - ret.last(ret.length-1) := '1'; - - return ret; - end function; - - impure function gen_key_hash return KEY_HASH_TYPE is - variable ret : KEY_HASH_TYPE := KEY_HASH_NIL; - begin - for i in 0 to KEY_HASH_TYPE'length-1 loop - ret(i) := RV.RandSlv(WORD_WIDTH); - end loop; - return ret; - end function; - - procedure start_dds is - begin - dds_start <= '1'; - wait until rising_edge(clk); - dds_start <= '0'; - wait until rising_edge(clk); - end procedure; - - procedure start_rtps is - begin - rtps_start <= '1'; - wait until rising_edge(clk); - rtps_start <= '0'; - wait until rising_edge(clk); - end procedure; - - procedure wait_on_dds is - begin - if (dds_done /= '1') then - wait until dds_done = '1'; - end if; - end procedure; - - procedure wait_on_rtps is - begin - if (rtps_done /= '1') then - wait until rtps_done = '1'; - end if; - end procedure; - - procedure wait_on_completion is - begin - if (rtps_done /= '1' or dds_done /= '1') then - wait until rtps_done = '1' and dds_done = '1'; - end if; - end procedure; - - -- NOTE: This procedure waits until the idle_sig is high for at least - -- two consecutive clock cycles. - procedure wait_on_idle is - variable first : boolean := TRUE; - begin - loop - if (idle_sig /= '1') then - wait until idle_sig = '1'; - elsif (not first) then - exit; - end if; - wait until rising_edge(clk); - wait until rising_edge(clk); - first := FALSE; - end loop; - end procedure; - - begin - - SetAlertLogName("L0_dds_reader_test3_arzkrtu - (KEEP ALL, Reliable, Zero TIME_BASED_FILTER, Keyed, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER, ACCESS SCOPE Topic, Unordered) - DDS Handling"); - SetAlertEnable(FAILURE, TRUE); - SetAlertEnable(ERROR, TRUE); - SetAlertEnable(WARNING, TRUE); - SetLogEnable(DEBUG, TRUE); - SetLogEnable(PASSED, FALSE); - SetLogEnable(INFO, TRUE); - RV.InitSeed(RV'instance_name); - sstate_id <= GetAlertLogID("Sample State", ALERTLOG_BASE_ID); - vstate_id <= GetAlertLogID("View State", ALERTLOG_BASE_ID); - istate_id <= GetAlertLogID("Instance State", ALERTLOG_BASE_ID); - ts_id <= GetAlertLogID("Source Timestamp", ALERTLOG_BASE_ID); - inst_id <= GetAlertLogID("Instance Handle", ALERTLOG_BASE_ID); - pub_id <= GetAlertLogID("Publication Hanlde", ALERTLOG_BASE_ID); - dis_gen_cnt_id <= GetAlertLogID("Disposed Generation Count", ALERTLOG_BASE_ID); - no_w_gen_cnt_id <= GetAlertLogID("No Writers Generation Count", ALERTLOG_BASE_ID); - srank_id <= GetAlertLogID("Sample Rank", ALERTLOG_BASE_ID); - grank_id <= GetAlertLogID("Generation Rank", ALERTLOG_BASE_ID); - agrank_id <= GetAlertLogID("Absolute Generation Rank", ALERTLOG_BASE_ID); - eoc_id <= GetAlertLogID("End Of Collection", ALERTLOG_BASE_ID); - valid_id <= GetAlertLogID("Valid Data", ALERTLOG_BASE_ID); - data_id <= GetAlertLogID("Data Out", ALERTLOG_BASE_ID); - ret_id <= GetAlertLogID("Return Code", ALERTLOG_BASE_ID); - - -- Key Hashes - kh1 := (x"F12C31DA", x"E3FE0F3F", x"01F36685", x"446518CA"); - kh2 := (x"BC070AC4", x"0BAB5811", x"14EA8D61", x"F669189B"); - kh3 := (x"0CEAB0C6", x"FA04B9AD", x"A96EB495", x"4E0EB999"); - kh4 := (x"A7EB605C", x"FF4BEF3A", x"3C5E8724", x"CCA0CA67"); - kh5 := gen_key_hash; - - - Log("Initiating Test", INFO); - Log("Current Time: 0s", INFO); - check_time <= TIME_ZERO; - reset <= '1'; - wait until rising_edge(clk); - wait until rising_edge(clk); - reset <= '0'; - -- MEM: - - -- ISTATE: - - -- VIEW: - - -- WRITER: - - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh1; - cc.payload := gen_payload(kh1,10); - cc.src_timestamp := gen_duration(0,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Aligned Payload, ID 0] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - rtps.ret_code := OK; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S1(0) - -- ISTATE: I1:ALIVE - -- VIEW: I1:NEW - -- WRITER: W0:I1 - - Log("Current Time: 1s", INFO); - check_time <= gen_duration(1,0); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait_on_idle; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_DISPOSED; - cc.instance := kh1; - cc.payload := gen_payload(kh1,5); - cc.src_timestamp := gen_duration(1,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Instance 1, Writer 0, ID 1] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - rtps.ret_code := OK; - s := to_sample(cc,NOT_ALIVE_DISPOSED_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S1(0), I1S2-(1) - -- ISTATE: I1:DISPOSED - -- VIEW: I1:NEW - -- WRITER: W0:I1 - - Log("Current Time: 2s", INFO); - check_time <= gen_duration(2,0); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait_on_idle; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh2; - cc.payload := gen_payload(kh2,10); - cc.src_timestamp := gen_duration(2,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 2, Writer 1, Aligned Payload, ID 2] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 1; - rtps.ret_code := OK; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S1(0), I1S2-(1), I2S1(2) - -- ISTATE: I1:DISPOSED, I2:ALIVE - -- VIEW: I1:NEW, I2:NEW - -- WRITER: W0:I1, W1:I2 - - Log("Current Time: 3s", INFO); - check_time <= gen_duration(3,0); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait_on_idle; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh3; - cc.payload := gen_payload(kh3,10); - cc.src_timestamp := gen_duration(3,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 3, Writer 2, Aligned Payload, ID 3] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 2; - rtps.ret_code := OK; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3) - -- ISTATE: I1:DISPOSED, I2:ALIVE, I3:ALIVE - -- VIEW: I1:NEW, I2:NEW, I3:NEW - -- WRITER: W0:I1, W1:I2, W2:I3 - - Log("Current Time: 4s", INFO); - check_time <= gen_duration(4,0); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait_on_idle; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh4; - cc.payload := gen_payload(kh4,10); - cc.src_timestamp := gen_duration(4,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 4, Writer 2, Aligned Payload, ID 4] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 2; - rtps.ret_code := OK; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), - -- ISTATE: I1:DISPOSED, I2:ALIVE, I3:ALIVE, I4:ALIVE - -- VIEW: I1:NEW, I2:NEW, I3:NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - Log("Current Time: 5s", INFO); - check_time <= gen_duration(5,0); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait_on_idle; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_DISPOSED; - cc.instance := kh2; - cc.payload := gen_payload(kh2,5); - cc.src_timestamp := gen_duration(5,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Instance 2, Writer 1, ID 5] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 1; - rtps.ret_code := OK; - s := to_sample(cc,NOT_ALIVE_DISPOSED_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5) - -- ISTATE: I1:DISPOSED, I2:DISPOSED, I3:ALIVE, I4:ALIVE - -- VIEW: I1:NEW, I2:NEW, I3:NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - Log("Current Time: 6s", INFO); - check_time <= gen_duration(6,0); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait_on_idle; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_DISPOSED; - cc.instance := kh3; - cc.payload := gen_payload(kh3,5); - cc.src_timestamp := gen_duration(6,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Instance 3, Writer 2, ID 6] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 2; - rtps.ret_code := OK; - s := to_sample(cc,NOT_ALIVE_DISPOSED_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6) - -- ISTATE: I1:DISPOSED, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NEW, I2:NEW, I3:NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - Log("Current Time: 7s", INFO); - check_time <= gen_duration(7,0); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait_on_idle; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_DISPOSED; - cc.instance := kh4; - cc.payload := gen_payload(kh4,5); - cc.src_timestamp := gen_duration(7,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Instance 4, Writer 2, ID 7] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 2; - rtps.ret_code := OK; - s := to_sample(cc,NOT_ALIVE_DISPOSED_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7) - -- ISTATE: I1:DISPOSED, I2:DISPOSED, I3:DISPOSED, I4:DISPOSED - -- VIEW: I1:NEW, I2:NEW, I3:NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - Log("Current Time: 8s", INFO); - check_time <= gen_duration(8,0); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait_on_idle; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh4; - cc.payload := gen_payload(kh4,10); - cc.src_timestamp := gen_duration(8,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 4, Writer 2, Aligned Payload, ID 8] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 2; - rtps.ret_code := OK; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8) - -- ISTATE: I1:DISPOSED, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NEW, I2:NEW, I3:NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - Log("Current Time: 9s", INFO); - check_time <= gen_duration(9,0); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait_on_idle; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh1; - cc.payload := gen_payload(kh1,10); - cc.src_timestamp := gen_duration(9,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Aligned Payload, ID 9] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - rtps.ret_code := OK; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NEW, I2:NEW, I3:NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - Log("Current Time: 10s", INFO); - check_time <= gen_duration(10,0); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait_on_idle; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh2; - cc.payload := gen_payload(kh2,10); - cc.src_timestamp := gen_duration(10,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 2, Writer 1, Aligned Payload, ID 10] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 1; - rtps.ret_code := OK; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10) - -- ISTATE: I1:ALIVE, I2:ALIVE, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NEW, I2:NEW, I3:NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - Log("Current Time: 11s", INFO); - check_time <= gen_duration(11,0); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait_on_idle; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_DISPOSED; - cc.instance := kh2; - cc.payload := gen_payload(kh2,5); - cc.src_timestamp := gen_duration(11,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Instance 2, Writer 1, ID 11] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 1; - rtps.ret_code := OK; - s := to_sample(cc,NOT_ALIVE_DISPOSED_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NEW, I2:NEW, I3:NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: READ [MAX_SAMPLES < SAMPLES] - -- TEST: READ [ANY SSTATE, ANY ISTATE, ANY VIEW] - - Log("DDS Operation READ [MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE] (Expected ID0,ID1,ID9)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ; - dds.max_samples := 3; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - start_dds; - wait_on_dds; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NEW, I3:NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: READ MARKS SAMPLES AS READ - -- TEST: READ_NEXT_SAMPLE [WITH UNREAD SAMPLE] - - Log("DDS Operation READ_NEXT_SAMPLE (Expected ID2)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ_NEXT_SAMPLE; - start_dds; - wait_on_dds; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NEW, I3:NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: READ_INSTANCE [KNOWN INSTANCE, COMPATIBLE SAMPLES] - - Log("DDS Operation READ_INSTANCE [MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Instance 3] (Expected ID3)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ_INSTANCE; - dds.max_samples := 1; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.inst := kh3; - start_dds; - wait_on_dds; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NEW, I3:NOT_NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: READ_NEXT_INSTANCE [WITH NEXT INSTANCE, COMPATIBLE SAMPLES] - - Log("DDS Operation READ_NEXT_INSTANCE [MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Instance 3] (Expected ID4)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ_NEXT_INSTANCE; - dds.max_samples := 1; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.inst := kh3; - start_dds; - wait_on_dds; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NEW, I3:NOT_NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: READ [SPECIFIED SSTATE, ANY ISTATE, ANY VIEW] - -- TEST: READ [MAX_SAMPLES > SAMPLES] - - Log("DDS Operation READ [MAX_SAMPLES 20, READ_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE] (Expected ID0,ID1,ID9,ID2,ID3,ID4)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ; - dds.max_samples := 20; - dds.sstate := READ_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - start_dds; - wait_on_dds; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NEW, I3:NOT_NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: READ [SPECIFIED SSTATE, SPECIFIED ISTATE, ANY VIEW] - - Log("DDS Operation READ [MAX_SAMPLES 20, READ_SAMPLE_STATE, NOT_ALIVE_DISPOSED_INSTANCE_STATE, ANY_VIEW_STATE] (Expected ID2,ID3)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ; - dds.max_samples := 20; - dds.sstate := READ_SAMPLE_STATE; - dds.istate := NOT_ALIVE_DISPOSED_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - start_dds; - wait_on_dds; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NEW, I3:NOT_NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: READ [SPECIFIED SSTATE, ANY ISTATE, SPECIFIED VIEW] - -- TEST: READ MODIFIES VIEW STATE [READ CURRENT GENERATION] - -- TEST: READ MODIFIES VIEW STATE [READ PREVIOUS GENERATION] - - Log("DDS Operation READ [MAX_SAMPLES 20, READ_SAMPLE_STATE, ANY_INSTANCE_STATE, NEW_VIEW_STATE] (Expected ID2,ID4)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ; - dds.max_samples := 20; - dds.sstate := READ_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := NEW_VIEW_STATE; - start_dds; - wait_on_dds; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NEW, I3:NOT_NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: READ [SPECIFIED SSTATE, SPECIFIED ISTATE, SPECIFIED VIEW] - - Log("DDS Operation READ [MAX_SAMPLES 20, READ_SAMPLE_STATE, NOT_ALIVE_DISPOSED_INSTANCE_STATE, NEW_VIEW_STATE] (Expected ID2)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ; - dds.max_samples := 20; - dds.sstate := READ_SAMPLE_STATE; - dds.istate := NOT_ALIVE_DISPOSED_INSTANCE_STATE; - dds.vstate := NEW_VIEW_STATE; - start_dds; - wait_on_dds; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NEW, I3:NOT_NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: READ [ANY SSTATE, ANY ISTATE, SPECIFIED VIEW] - - Log("DDS Operation READ [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, NOT_NEW_VIEW_STATE] (Expected ID0,ID1,ID9,ID3,ID6)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := NOT_NEW_VIEW_STATE; - start_dds; - wait_on_dds; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NEW, I3:NOT_NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: READ [ANY SSTATE, SPECIFIED ISTATE, SPECIFIED VIEW] - - Log("DDS Operation READ [MAX_SAMPLES 20, ANY_SAMPLE_STATE, NOT_ALIVE_DISPOSED_INSTANCE_STATE, NOT_NEW_VIEW_STATE] (Expected ID3,ID6)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := NOT_ALIVE_DISPOSED_INSTANCE_STATE; - dds.vstate := NOT_NEW_VIEW_STATE; - start_dds; - wait_on_dds; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NEW, I3:NOT_NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: READ [ANY SSTATE, SPECIFIED ISTATE, ANY VIEW] - - Log("DDS Operation READ [MAX_SAMPLES 20, ANY_SAMPLE_STATE, NOT_ALIVE_DISPOSED_INSTANCE_STATE, ANY_VIEW_STATE] (Expected ID2,ID5,ID10,ID11,ID3,ID6)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := NOT_ALIVE_DISPOSED_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - start_dds; - wait_on_dds; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: READ_INSTANCE [UNKNOWN INSTANCE] - - Log("DDS Operation READ_INSTANCE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Unknown Instance] (Bad Parameter)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ_INSTANCE; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.inst := kh5; - dds.ret_code := RETCODE_BAD_PARAMETER; - start_dds; - wait_on_dds; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: READ_INSTANCE [KNOWN INSTANCE, UNCOMPATIBLE SAMPLES] - - Log("DDS Operation READ_INSTANCE [MAX_SAMPLES 20, NOT_READ_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Instance 1] (No Data)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ_INSTANCE; - dds.max_samples := 20; - dds.sstate := NOT_READ_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.inst := kh1; - dds.ret_code := RETCODE_NO_DATA; - start_dds; - wait_on_dds; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: READ_NEXT_INSTANCE [WITH NEXT INSTANCE, UNCOMPATIBLE SAMPLES] - - Log("DDS Operation READ_NEXT_INSTANCE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, NOT_ALIVE_DISPOSED_INSTANCE_STATE, ANY_VIEW_STATE, Instance 2] (No Data)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ_NEXT_INSTANCE; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := NOT_ALIVE_DISPOSED_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.inst := kh2; - dds.ret_code := RETCODE_NO_DATA; - start_dds; - wait_on_dds; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: READ_NEXT_INSTANCE [WITH NEXT INSTANCE, WITH COMPATIBLE SAMPLE, NOT DIRECT NEXT INSTANCE] - - Log("DDS Operation READ_NEXT_INSTANCE [MAX_SAMPLES 20, NOT_READ_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Instance 3] (Expected ID7,ID8)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ_NEXT_INSTANCE; - dds.max_samples := 20; - dds.sstate := NOT_READ_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.inst := kh3; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: READ [NO COMPATIBLE SAMPLES] - - Log("DDS Operation READ [MAX_SAMPLES 20, ANY_SAMPLE_STATE, NOT_ALIVE_NO_WRITERS_INSTANCE_STATE, ANY_VIEW_STATE] (No Data)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := NOT_ALIVE_NO_WRITERS_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.ret_code := RETCODE_NO_DATA; - start_dds; - wait_on_dds; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: READ_NEXT_SAMPLE [WITHOUT UNREAD SAMPLE] - - Log("DDS Operation READ_NEXT_SAMPLE (No Data)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ_NEXT_SAMPLE; - dds.ret_code := RETCODE_NO_DATA; - start_dds; - wait_on_dds; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: TAKE - - Log("DDS Operation TAKE [MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE] (Expected ID0)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE; - dds.max_samples := 1; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - -- MEM: I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: TAKE_INSTANCE - - Log("DDS Operation TAKE_INSTANCE [MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Instance 2] (Expected ID2)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE_INSTANCE; - dds.max_samples := 1; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.inst := kh2; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - -- MEM: I1S2-(1), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: TAKE_NEXT_INSTANCE - -- TEST: READ_NEXT_INSTANCE [HANDLE_NIL] - - Log("DDS Operation TAKE_NEXT_INSTANCE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, HANDLE_NIL] (Expected ID3,ID6)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE_NEXT_INSTANCE; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.inst := HANDLE_NIL; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - -- MEM: I1S2-(1), I4S1(4), I2S2-(5), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: TAKE REMOVES SAMPLE - -- TEST: READ_INSTANCE [NO SAMPLES] - - Log("DDS Operation READ_INSTANCE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Instance 3] (No Data)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ_INSTANCE; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.inst := kh3; - dds.ret_code := RETCODE_NO_DATA; - start_dds; - wait_on_dds; - -- MEM: I1S2-(1), I4S1(4), I2S2-(5), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - Log("DDS Operation TAKE_NEXT_INSTANCE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Instance 3] (Expected ID4,ID7,ID8)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE_NEXT_INSTANCE; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.inst := kh3; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - -- MEM: I1S2-(1), I2S2-(5), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: TAKE_INSTANCE [NO SAMPLES] - - Log("DDS Operation TAKE_INSTANCE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Instance 4] (No Data)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE_INSTANCE; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.inst := kh4; - dds.ret_code := RETCODE_NO_DATA; - start_dds; - wait_on_dds; - -- MEM: I1S2-(1), I2S2-(5), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - Log("DDS Operation TAKE_NEXT_INSTANCE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Instance 4] (Expected ID5,ID10,ID11)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE_NEXT_INSTANCE; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.inst := kh4; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - -- MEM: I1S2-(1), I1S3(9) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - Log("DDS Operation READ_INSTANCE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Instance 2] (No Data)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ_INSTANCE; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.inst := kh2; - dds.ret_code := RETCODE_NO_DATA; - start_dds; - wait_on_dds; - -- MEM: I1S2-(1), I1S3(9) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: READ_NEXT_INSTANCE [WITH SAMPLES, WITHOUT NEXT INSTANCE] - - Log("DDS Operation READ_NEXT_INSTANCE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Instance 1] (No Data)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ_NEXT_INSTANCE; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.inst := kh1; - dds.ret_code := RETCODE_NO_DATA; - start_dds; - wait_on_dds; - -- MEM: I1S2-(1), I1S3(9) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - Log("DDS Operation TAKE_NEXT_INSTANCE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Instance 2] (Expected ID1,ID9)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE_NEXT_INSTANCE; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.inst := kh2; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - -- MEM: - - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: GET ALL DATA WITH READ_NEXT_INSTANCE - -- TEST: READ [NO SAMPLES] - - Log("DDS Operation READ [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE] (No Data)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.ret_code := RETCODE_NO_DATA; - start_dds; - wait_on_dds; - -- MEM: - - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: TAKE [NO SAMPLES] - - Log("DDS Operation TAKE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE] (No Data)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.ret_code := RETCODE_NO_DATA; - start_dds; - wait_on_dds; - -- MEM: - - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: READ_NEXT_INSTANCE [NO SAMPLE] - - Log("DDS Operation READ_NEXT_INSTANCE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, HANDLE_NIL] (No Data)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ_NEXT_INSTANCE; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.inst := HANDLE_NIL; - dds.ret_code := RETCODE_NO_DATA; - start_dds; - wait_on_dds; - -- MEM: - - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: TAKE_NEXT_INSTANCE [NO SAMPLE] - - Log("DDS Operation TAKE_NEXT_INSTANCE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, HANDLE_NIL] (No Data)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE_NEXT_INSTANCE; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.inst := HANDLE_NIL; - dds.ret_code := RETCODE_NO_DATA; - start_dds; - wait_on_dds; - -- MEM: - - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: READ_NEXT_SAMPLE [NO SAMPLE] - - Log("DDS Operation READ_NEXT_SAMPLE (No Data)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ_NEXT_SAMPLE; - dds.ret_code := RETCODE_NO_DATA; - start_dds; - wait_on_dds; - -- MEM: - - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: TAKE_NEXT_SAMPLE [NO SAMPLE] - - Log("DDS Operation TAKE_NEXT_SAMPLE (No Data)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE_NEXT_SAMPLE; - dds.ret_code := RETCODE_NO_DATA; - start_dds; - wait_on_dds; - -- MEM: - - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - Log("Current Time: 12s", INFO); - check_time <= gen_duration(12,0); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait_on_idle; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh2; - cc.payload := gen_payload(kh2,10); - cc.src_timestamp := gen_duration(12,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 2, Writer 1, Aligned Payload, ID 12] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 1; - rtps.ret_code := OK; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I2S5(12) - -- ISTATE: I1:ALIVE, I2:ALIVE, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: TAKE_NEXT_SAMPLE - - Log("DDS Operation TAKE_NEXT_SAMPLE (Expected ID12)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE_NEXT_SAMPLE; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - -- MEM: - - -- ISTATE: I1:ALIVE, I2:ALIVE, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - Log("DDS Operation READ [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE] (No Data)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.ret_code := RETCODE_NO_DATA; - start_dds; - wait_on_dds; - -- MEM: - - -- ISTATE: I1:ALIVE, I2:ALIVE, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - wait_on_completion; - TranscriptOpen(RESULTS_FILE, APPEND_MODE); - SetTranscriptMirror; - ReportAlerts; - TranscriptClose; - std.env.stop; - wait; - end process; - - clock_prc : process - begin - clk <= '0'; - wait for 25 ns; - clk <= '1'; - wait for 25 ns; - end process; - - alert_prc : process(all) - begin - if rising_edge(clk) then - -- TODO - end if; - end process; - - dds_prc : process(all) - variable col : COLLECTION_TYPE := DEFAULT_COLLECTION; - begin - if rising_edge(clk) then - dds_done <= '0'; - case (dds_stage ) is - when IDLE => - if (dds_start = '1') then - dds_stage <= START; - else - dds_done <= '1'; - end if; - when START => - if (ack_dds = '1') then - dds_stage <= DONE; - dds_cnt <= 0; - end if; - when DONE => - if (done_dds = '1') then - AffirmIfEqual(ret_id, return_code_dds, dds.ret_code); - case (dds.ret_code) is - when RETCODE_OK => - gen_collection(mem, col, dds, TOPIC_PRESENTATION_QOS, FALSE); - dds_stage <= CHECK_SI; - dds_cnt <= 0; - when others => - dds_stage <= IDLE; - end case; - end if; - when CHECK_SI => - if (si_valid = '1') then - Log("Read Sample ID" & to_string(to_integer(si_source_timestamp(0))), DEBUG); - AffirmIfEqual(sstate_id, si_sample_state, col.s(dds_cnt).sstate); - AffirmIfEqual(vstate_id, si_view_state, col.s(dds_cnt).vstate); - AffirmIfEqual(istate_id, si_instance_state, col.s(dds_cnt).istate); - AffirmIfEqual(ts_id, to_unsigned(si_source_timestamp), to_unsigned(col.s(dds_cnt).ts)); - AffirmIfEqual(inst_id, to_unsigned(si_instance_handle), to_unsigned(col.s(dds_cnt).inst)); - AffirmIfEqual(pub_id, to_unsigned(si_publication_handle), to_unsigned(HANDLE_NIL)); - AffirmIfEqual(dis_gen_cnt_id, si_disposed_generation_count, std_logic_vector(to_unsigned(col.s(dds_cnt).dis_gen_cnt,WORD_WIDTH))); - AffirmIfEqual(no_w_gen_cnt_id, si_no_writers_generation_count, std_logic_vector(to_unsigned(col.s(dds_cnt).no_w_gen_cnt,WORD_WIDTH))); - AffirmIfEqual(srank_id, si_sample_rank, std_logic_vector(to_unsigned(col.s(dds_cnt).srank,WORD_WIDTH))); - AffirmIfEqual(grank_id, si_generation_rank, std_logic_vector(to_unsigned(col.s(dds_cnt).grank,WORD_WIDTH))); - AffirmIfEqual(agrank_id, si_absolute_generation_rank, std_logic_vector(to_unsigned(col.s(dds_cnt).agrank,WORD_WIDTH))); - if (si_valid_data = '1') then - AffirmIf(valid_id, col.s(dds_cnt).data /= EMPTY_TEST_PACKET, "Sample with Data not expected"); - dds_stage <= CHECK_DATA; - dds_cnt2 <= 0; - else - AffirmIf(valid_id, col.s(dds_cnt).data = EMPTY_TEST_PACKET, "Sample with Data expected"); - if (dds_cnt = col.len-1) then - -- DONE - dds_stage <= WAIT_EOC; - else - dds_cnt <= dds_cnt + 1; - end if; - end if; - end if; - AffirmIf(eoc_id, eoc = '0', "EOC pulled high"); - when CHECK_DATA => - if (valid_out_dds = '1') then - AffirmIfEqual(data_id, data_out_dds, col.s(dds_cnt).data.data(dds_cnt2)); - dds_cnt2 <= dds_cnt2 + 1; - if (dds_cnt2 = col.s(dds_cnt).data.length-1) then - AlertIf(data_id, last_word_out_dds /= '1', "Last Word Signal not pulled High", ERROR); - if (dds_cnt = col.len-1) then - -- DONE - dds_stage <= WAIT_EOC; - else - dds_stage <= CHECK_SI; - dds_cnt <= dds_cnt + 1; - end if; - end if; - end if; - when WAIT_EOC => - if (eoc = '1') then - dds_stage <= IDLE; - end if; - end case; - end if; - - -- DEFAULT - start_dds <= '0'; - opcode_dds <= NOP; - instance_state_dds <= ANY_INSTANCE_STATE; - view_state_dds <= ANY_VIEW_STATE; - sample_state_dds <= ANY_SAMPLE_STATE; - instance_handle_dds <= HANDLE_NIL; - max_samples_dds <= (others => '0'); - get_data_dds <= '0'; - ready_out_dds <= '0'; - - - case (dds_stage ) is - when START => - start_dds <= '1'; - opcode_dds <= dds.opcode; - instance_state_dds <= dds.istate; - view_state_dds <= dds.vstate; - sample_state_dds <= dds.sstate; - instance_handle_dds <= dds.inst; - max_samples_dds <= std_logic_vector(to_unsigned(dds.max_samples, WORD_WIDTH)); - when CHECK_SI => - if (si_valid = '1' and si_valid_data = '1') then - get_data_dds <= '1'; - end if; - when CHECK_DATA => - ready_out_dds <= '1'; - when others => - null; - end case; - end process; - - rtps_prc : process(all) - variable stimulus : TEST_PACKET_TYPE := EMPTY_TEST_PACKET; - begin - if rising_edge(clk) then - rtps_done <= '0'; - case (rtps_stage) is - when IDLE => - if (rtps_start = '1') then - rtps_stage <= START; - else - rtps_done <= '1'; - end if; - when START => - if (ack_rtps = '1') then - case (rtps.opcode) is - when ADD_CACHE_CHANGE => - gen_add_cache_change_dds(rtps.cc, rtps.lifespan, rtps.writer_pos, stimulus); - rtps_stage <= PUSH; - when others => - rtps_stage <= DONE; - end case; - end if; - when PUSH => - if (ready_in_rtps = '1') then - rtps_cnt <= rtps_cnt + 1; - if (rtps_cnt = stimulus.length-1) then - rtps_stage <= DONE; - end if; - end if; - when DONE => - if (done_rtps = '1') then - AffirmIfEqual(ret_id, HISTORY_CACHE_RESPONSE_TYPE'pos(ret_rtps), HISTORY_CACHE_RESPONSE_TYPE'pos(rtps.ret_code)); - rtps_stage <= IDLE; - end if; - end case; - end if; - - -- DEFAULT - start_rtps <= '0'; - opcode_rtps <= NOP; - valid_in_rtps <= '0'; - last_word_in_rtps <= '0'; - data_in_rtps <= (others => '0'); - - case (rtps_stage) is - when START => - start_rtps <= '1'; - opcode_rtps <= rtps.opcode; - case (rtps.opcode) is - when REMOVE_WRITER => - data_in_rtps <= std_logic_vector(to_unsigned(rtps.writer_pos,WORD_WIDTH)); - when others => - null; - end case; - when PUSH => - valid_in_rtps <= '1'; - data_in_rtps <= stimulus.data(rtps_cnt); - last_word_in_rtps <= stimulus.last(rtps_cnt); - when others => - null; - end case; - end process; - - watchdog : process - begin - wait for 1 ms; - Alert("Test timeout", FAILURE); - std.env.stop; - end process; - -end architecture; \ No newline at end of file diff --git a/src/Tests/Level_0/L0_dds_reader_test3_arzksto.vhd b/src/Tests/Level_0/L0_dds_reader_test3_arzksto.vhd deleted file mode 100644 index 0eea62d..0000000 --- a/src/Tests/Level_0/L0_dds_reader_test3_arzksto.vhd +++ /dev/null @@ -1,1500 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library osvvm; -- Utility Library -context osvvm.OsvvmContext; - -use work.rtps_package.all; -use work.user_config.all; -use work.rtps_config_package.all; -use work.rtps_test_package.all; - --- This testbench tests the DDS handling of the DDS Reader. It tests the correctness of the DDS READ, TAKE, READ_NEXT_SAMPLE, TAKE_NEXT_SAMPLE, --- READ_INSTANCE, TAKE_INSTANCE, READ_NEXT_INSTANCE, TAKE_NEXT_INSTANCE Operations. --- More specifically the testbench covers following tests: --- TEST: READ [NO COMPATIBLE SAMPLES] --- TEST: READ [NO SAMPLES] --- TEST: READ [MAX_SAMPLES < SAMPLES] --- TEST: READ [MAX_SAMPLES > SAMPLES] --- TEST: TAKE [NO SAMPLES] --- TEST: TAKE --- TEST: READ [ANY SSTATE, ANY ISTATE, ANY VIEW] --- TEST: READ [ANY SSTATE, ANY ISTATE, SPECIFIED VIEW] --- TEST: READ [ANY SSTATE, SPECIFIED ISTATE, ANY VIEW] --- TEST: READ [ANY SSTATE, SPECIFIED ISTATE, SPECIFIED VIEW] --- TEST: READ [SPECIFIED SSTATE, ANY ISTATE, ANY VIEW] --- TEST: READ [SPECIFIED SSTATE, ANY ISTATE, SPECIFIED VIEW] --- TEST: READ [SPECIFIED SSTATE, SPECIFIED ISTATE, ANY VIEW] --- TEST: READ [SPECIFIED SSTATE, SPECIFIED ISTATE, SPECIFIED VIEW] --- TEST: READ_NEXT_SAMPLE [WITH UNREAD SAMPLE] --- TEST: READ_NEXT_SAMPLE [WITHOUT UNREAD SAMPLE] --- TEST: READ_NEXT_SAMPLE [NO SAMPLE] --- TEST: TAKE_NEXT_SAMPLE [NO SAMPLE] --- TEST: TAKE_NEXT_SAMPLE --- TEST: READ_INSTANCE [UNKNOWN INSTANCE] --- TEST: READ_INSTANCE [KNOWN INSTANCE, UNCOMPATIBLE SAMPLES] --- TEST: READ_INSTANCE [KNOWN INSTANCE, COMPATIBLE SAMPLES] --- TEST: READ_INSTANCE [NO SAMPLES] --- TEST: TAKE_INSTANCE [NO SAMPLES] --- TEST: TAKE_INSTANCE --- TEST: READ_NEXT_INSTANCE [WITH SAMPLES, WITHOUT NEXT INSTANCE] --- TEST: READ_NEXT_INSTANCE [WITH NEXT INSTANCE, UNCOMPATIBLE SAMPLES] --- TEST: READ_NEXT_INSTANCE [WITH NEXT INSTANCE, COMPATIBLE SAMPLES] --- TEST: READ_NEXT_INSTANCE [HANDLE_NIL] --- TEST: READ_NEXT_INSTANCE [WITH NEXT INSTANCE, WITH COMPATIBLE SAMPLE, NOT DIRECT NEXT INSTANCE] --- TEST: READ_NEXT_INSTANCE [NO SAMPLE] --- TEST: TAKE_NEXT_INSTANCE [NO SAMPLE] --- TEST: TAKE_NEXT_INSTANCE --- TEST: GET ALL DATA WITH READ_NEXT_INSTANCE --- TEST: READ MARKS SAMPLES AS READ --- TEST: TAKE REMOVES SAMPLE --- TEST: READ MODIFIES VIEW STATE [READ PREVIOUS GENERATION] --- TEST: READ MODIFIES VIEW STATE [READ CURRENT GENERATION] --- TEST: OUT OF ORDER SAMPLE AFTER DISPOSE - -entity L0_dds_reader_test3_arzksto is -end entity; - - -architecture testbench of L0_dds_reader_test3_arzksto is - - -- *CONSTANT DECLARATION* - constant MAX_REMOTE_ENDPOINTS : natural := 3; - - -- *TYPE DECLARATION* - type DDS_STAGE_TYPE is (IDLE, START, DONE, CHECK_SI, CHECK_DATA, WAIT_EOC); - type RTPS_STAGE_TYPE is (IDLE, START, PUSH, DONE); - - -- *SIGNAL DECLARATION* - signal clk : std_logic := '0'; - signal reset : std_logic := '1'; - signal check_time : TIME_TYPE := TIME_ZERO; - signal start_rtps, start_dds, ack_rtps, ack_dds, done_rtps, done_dds : std_logic := '0'; - signal opcode_rtps : HISTORY_CACHE_OPCODE_TYPE := NOP; - signal opcode_dds : DDS_READER_OPCODE_TYPE := NOP; - signal ret_rtps : HISTORY_CACHE_RESPONSE_TYPE := ERROR; - signal ready_in_rtps, valid_in_rtps, last_word_in_rtps : std_logic := '0'; - signal ready_out_dds, valid_out_dds, last_word_out_dds : std_logic := '0'; - signal data_in_rtps, data_out_dds : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); - signal get_data_dds, si_valid_data, si_valid, eoc : std_logic := '0'; - signal return_code_dds : std_logic_vector(RETURN_CODE_WIDTH-1 downto 0) := (others => '0'); - signal status : std_logic_vector(STATUS_KIND_WIDTH-1 downto 0) := (others => '0'); - signal instance_state_dds, si_instance_state : std_logic_vector(INSTANCE_STATE_KIND_WIDTH-1 downto 0) := ANY_INSTANCE_STATE; - signal view_state_dds, si_view_state : std_logic_vector(VIEW_STATE_KIND_WIDTH-1 downto 0) := ANY_VIEW_STATE; - signal sample_state_dds, si_sample_state : std_logic_vector(SAMPLE_STATE_KIND_WIDTH-1 downto 0) := ANY_SAMPLE_STATE; - signal instance_handle_dds, si_instance_handle : INSTANCE_HANDLE_TYPE := HANDLE_NIL; - signal max_samples_dds : std_logic_vector(MAX_SAMPLES_WIDTH-1 downto 0) := (others => '0'); - signal si_source_timestamp : TIME_TYPE := TIME_INVALID; - signal si_publication_handle : INSTANCE_HANDLE_TYPE := HANDLE_NIL; - signal si_disposed_generation_count : std_logic_vector(DISPOSED_GENERATION_COUNT_WIDTH-1 downto 0) := (others => '0'); - signal si_no_writers_generation_count : std_logic_vector(NO_WRITERS_GENERATION_COUNT_WIDTH-1 downto 0) := (others => '0'); - signal si_sample_rank : std_logic_vector(SAMPLE_RANK_WIDTH-1 downto 0) := (others => '0'); - signal si_generation_rank : std_logic_vector(GENERATION_RANK_WIDTH-1 downto 0) := (others => '0'); - signal si_absolute_generation_rank: std_logic_vector(ABSOLUTE_GENERATION_COUNT_WIDTH-1 downto 0) := (others => '0'); - - signal dds_start , dds_done , rtps_start, rtps_done : std_logic := '0'; - signal dds_cnt, dds_cnt2, rtps_cnt : natural := 0; - signal dds_stage : DDS_STAGE_TYPE := IDLE; - signal rtps_stage : RTPS_STAGE_TYPE := IDLE; - shared variable dds : DDS_READER_TEST_TYPE := DEFAULT_DDS_READER_TEST; - shared variable rtps : RTPS_READER_TEST_TYPE := DEFAULT_RTPS_READER_TEST; - shared variable mem : DDS_READER_MEM_TYPE := DEFAULT_DDS_READER_MEM; - signal data_id, ret_id, sstate_id, vstate_id, istate_id, inst_id, ts_id, pub_id, dis_gen_cnt_id, no_w_gen_cnt_id, srank_id, grank_id, agrank_id, eoc_id, valid_id : AlertLogIDType; - - -- *FUNCTION DECLARATION* - function extract_key_hash (payload : TEST_PACKET_TYPE) return INSTANCE_HANDLE_TYPE is - variable ret : INSTANCE_HANDLE_TYPE := HANDLE_NIL; - begin - for i in 0 to 3 loop - ret(i) := not payload.data(i); - end loop; - - return ret; - end function; - - function gen_sn(input : natural) return SEQUENCENUMBER_TYPE is - variable ret : SEQUENCENUMBER_TYPE; - begin - ret(0) := (others => '0'); - ret(1) := unsigned(int(input, WORD_WIDTH)); - return ret; - end function; - -begin - - -- Unit Under Test - uut : entity work.dds_reader(arch) - generic map ( - TIME_BASED_FILTER_QOS => DURATION_ZERO, - DEADLINE_QOS => DURATION_INFINITE, - MAX_SAMPLES => std_logic_vector(to_unsigned(15,CDR_LONG_WIDTH)), - MAX_INSTANCES => std_logic_vector(to_unsigned(4,CDR_LONG_WIDTH)), - MAX_SAMPLES_PER_INSTANCE => std_logic_vector(to_unsigned(15,CDR_LONG_WIDTH)), - HISTORY_QOS => KEEP_ALL_HISTORY_QOS, - RELIABILITY_QOS => RELIABLE_RELIABILITY_QOS, - PRESENTATION_QOS => TOPIC_PRESENTATION_QOS, - DESTINATION_ORDER_QOS => BY_SOURCE_TIMESTAMP_DESTINATION_ORDER_QOS, - COHERENT_ACCESS => FALSE, - ORDERED_ACCESS => TRUE, - WITH_KEY => TRUE, - PAYLOAD_FRAME_SIZE => 11, - MAX_REMOTE_ENDPOINTS => MAX_REMOTE_ENDPOINTS - ) - port map ( - clk => clk, - reset => reset, - time => check_time, - start_rtps => start_rtps, - opcode_rtps => opcode_rtps, - ack_rtps => ack_rtps, - done_rtps => done_rtps, - ret_rtps => ret_rtps, - data_in_rtps => data_in_rtps, - valid_in_rtps => valid_in_rtps, - ready_in_rtps => ready_in_rtps, - last_word_in_rtps => last_word_in_rtps, - start_dds => start_dds, - ack_dds => ack_dds, - opcode_dds => opcode_dds, - instance_state_dds => instance_state_dds, - view_state_dds => view_state_dds, - sample_state_dds => sample_state_dds, - instance_handle_dds => instance_handle_dds, - max_samples_dds => max_samples_dds, - get_data_dds => get_data_dds, - done_dds => done_dds, - return_code_dds => return_code_dds, - ready_out_dds => ready_out_dds, - valid_out_dds => valid_out_dds, - data_out_dds => data_out_dds, - last_word_out_dds => last_word_out_dds, - sample_info.sample_state => si_sample_state, - sample_info.view_state => si_view_state, - sample_info.instance_state => si_instance_state, - sample_info.source_timestamp => si_source_timestamp, - sample_info.instance_handle => si_instance_handle, - sample_info.publication_handle => si_publication_handle, - sample_info.disposed_generation_count => si_disposed_generation_count, - sample_info.no_writers_generation_count => si_no_writers_generation_count, - sample_info.sample_rank => si_sample_rank, - sample_info.generation_rank => si_generation_rank, - sample_info.absolute_generation_rank => si_absolute_generation_rank, - sample_info.valid_data => si_valid_data, - sample_info_valid => si_valid, - sample_info_ack => '1', - eoc => eoc, - status => status - ); - - stimulus_prc : process - variable RV : RandomPType; - variable cc : CACHE_CHANGE_TYPE := DEFAULT_CACHE_CHANGE; - variable s : SAMPLE_TYPE := DEFAULT_SAMPLE; - variable kh1, kh2, kh3, kh4, kh5 : INSTANCE_HANDLE_TYPE := HANDLE_NIL; - - alias idle_sig is <>; - - impure function gen_payload(key_hash : INSTANCE_HANDLE_TYPE; len : natural) return TEST_PACKET_TYPE is - variable ret : TEST_PACKET_TYPE := EMPTY_TEST_PACKET; - begin - assert (len >= 4) report "Payload length has to be at least 16 Bytes long" severity FAILURE; - - for i in 0 to len-1 loop - if (i < 4) then - -- NOTE: Beginning of payload is negated key to allow deterministic Key Hash generation from the kh_prc - ret.data(ret.length) := not key_hash(i); - else - ret.data(ret.length) := RV.RandSlv(WORD_WIDTH); - end if; - ret.length := ret.length + 1; - end loop; - ret.last(ret.length-1) := '1'; - - return ret; - end function; - - impure function gen_key_hash return KEY_HASH_TYPE is - variable ret : KEY_HASH_TYPE := KEY_HASH_NIL; - begin - for i in 0 to KEY_HASH_TYPE'length-1 loop - ret(i) := RV.RandSlv(WORD_WIDTH); - end loop; - return ret; - end function; - - procedure start_dds is - begin - dds_start <= '1'; - wait until rising_edge(clk); - dds_start <= '0'; - wait until rising_edge(clk); - end procedure; - - procedure start_rtps is - begin - rtps_start <= '1'; - wait until rising_edge(clk); - rtps_start <= '0'; - wait until rising_edge(clk); - end procedure; - - procedure wait_on_dds is - begin - if (dds_done /= '1') then - wait until dds_done = '1'; - end if; - end procedure; - - procedure wait_on_rtps is - begin - if (rtps_done /= '1') then - wait until rtps_done = '1'; - end if; - end procedure; - - procedure wait_on_completion is - begin - if (rtps_done /= '1' or dds_done /= '1') then - wait until rtps_done = '1' and dds_done = '1'; - end if; - end procedure; - - -- NOTE: This procedure waits until the idle_sig is high for at least - -- two consecutive clock cycles. - procedure wait_on_idle is - variable first : boolean := TRUE; - begin - loop - if (idle_sig /= '1') then - wait until idle_sig = '1'; - elsif (not first) then - exit; - end if; - wait until rising_edge(clk); - wait until rising_edge(clk); - first := FALSE; - end loop; - end procedure; - - begin - - SetAlertLogName("L0_dds_reader_test3_arzksto - (KEEP ALL, Reliable, Zero TIME_BASED_FILTER, Keyed, BY_SOURCE_TIMESTAMP_DESTINATION_ORDER_QOS, ACCESS SCOPE Topic, Ordered) - DDS Handling"); - SetAlertEnable(FAILURE, TRUE); - SetAlertEnable(ERROR, TRUE); - SetAlertEnable(WARNING, TRUE); - SetLogEnable(DEBUG, TRUE); - SetLogEnable(PASSED, FALSE); - SetLogEnable(INFO, TRUE); - RV.InitSeed(RV'instance_name); - sstate_id <= GetAlertLogID("Sample State", ALERTLOG_BASE_ID); - vstate_id <= GetAlertLogID("View State", ALERTLOG_BASE_ID); - istate_id <= GetAlertLogID("Instance State", ALERTLOG_BASE_ID); - ts_id <= GetAlertLogID("Source Timestamp", ALERTLOG_BASE_ID); - inst_id <= GetAlertLogID("Instance Handle", ALERTLOG_BASE_ID); - pub_id <= GetAlertLogID("Publication Hanlde", ALERTLOG_BASE_ID); - dis_gen_cnt_id <= GetAlertLogID("Disposed Generation Count", ALERTLOG_BASE_ID); - no_w_gen_cnt_id <= GetAlertLogID("No Writers Generation Count", ALERTLOG_BASE_ID); - srank_id <= GetAlertLogID("Sample Rank", ALERTLOG_BASE_ID); - grank_id <= GetAlertLogID("Generation Rank", ALERTLOG_BASE_ID); - agrank_id <= GetAlertLogID("Absolute Generation Rank", ALERTLOG_BASE_ID); - eoc_id <= GetAlertLogID("End Of Collection", ALERTLOG_BASE_ID); - valid_id <= GetAlertLogID("Valid Data", ALERTLOG_BASE_ID); - data_id <= GetAlertLogID("Data Out", ALERTLOG_BASE_ID); - ret_id <= GetAlertLogID("Return Code", ALERTLOG_BASE_ID); - - -- Key Hashes - kh1 := (x"F12C31DA", x"E3FE0F3F", x"01F36685", x"446518CA"); - kh2 := (x"BC070AC4", x"0BAB5811", x"14EA8D61", x"F669189B"); - kh3 := (x"0CEAB0C6", x"FA04B9AD", x"A96EB495", x"4E0EB999"); - kh4 := (x"A7EB605C", x"FF4BEF3A", x"3C5E8724", x"CCA0CA67"); - kh5 := gen_key_hash; - - - Log("Initiating Test", INFO); - Log("Current Time: 0s", INFO); - check_time <= TIME_ZERO; - reset <= '1'; - wait until rising_edge(clk); - wait until rising_edge(clk); - reset <= '0'; - -- MEM: - - -- ISTATE: - - -- VIEW: - - -- WRITER: - - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_DISPOSED; - cc.instance := kh4; - cc.payload := gen_payload(kh4,5); - cc.src_timestamp := gen_duration(7,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Instance 4, Writer 2, ID 7] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 2; - rtps.ret_code := OK; - s := to_sample(cc,NOT_ALIVE_DISPOSED_INSTANCE_STATE); - add_sample(s,mem, BY_SOURCE_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I4S2-(7) - -- ISTATE: I4:DISOSED - -- VIEW: I4:NEW - -- WRITER: W2:I4 - - Log("Current Time: 1s", INFO); - check_time <= gen_duration(1,0); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait_on_idle; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh1; - cc.payload := gen_payload(kh1,10); - cc.src_timestamp := gen_duration(0,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Aligned Payload, ID 0] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - rtps.ret_code := OK; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_SOURCE_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S1(0), I4S2-(7) - -- ISTATE: I1:ALIVE, I4:DISOSED - -- VIEW: I1:NEW, I4:NEW - -- WRITER: W0:I1, W2:I4 - - Log("Current Time: 2s", INFO); - check_time <= gen_duration(2,0); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait_on_idle; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_DISPOSED; - cc.instance := kh1; - cc.payload := gen_payload(kh1,5); - cc.src_timestamp := gen_duration(1,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Instance 1, Writer 0, ID 1] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - rtps.ret_code := OK; - s := to_sample(cc,NOT_ALIVE_DISPOSED_INSTANCE_STATE); - add_sample(s,mem, BY_SOURCE_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S1(0), I1S2-(1), I4S2-(7) - -- ISTATE: I1:DISPOSED, I4:DISOSED - -- VIEW: I1:NEW, I4:NEW - -- WRITER: W0:I1, W2:I4 - - Log("Current Time: 3s", INFO); - check_time <= gen_duration(3,0); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait_on_idle; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh1; - cc.payload := gen_payload(kh1,10); - cc.src_timestamp := gen_duration(9,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Aligned Payload, ID 9] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - rtps.ret_code := OK; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_SOURCE_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S1(0), I1S2-(1), I4S2-(7), I1S3(9) - -- ISTATE: I1:ALIVE, I4:DISOSED - -- VIEW: I1:NEW, I4:NEW - -- WRITER: W0:I1, W2:I4 - - Log("Current Time: 4s", INFO); - check_time <= gen_duration(4,0); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait_on_idle; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh4; - cc.payload := gen_payload(kh4,10); - cc.src_timestamp := gen_duration(4,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 4, Writer 2, Aligned Payload, ID 4] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 2; - rtps.ret_code := OK; - s := to_sample(cc,NOT_ALIVE_DISPOSED_INSTANCE_STATE); - add_sample(s,mem, BY_SOURCE_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S1(0), I1S2-(1), I4S1(4), I4S2-(7), I1S3(9) - -- ISTATE: I1:ALIVE, I4:DISOSED - -- VIEW: I1:NEW, I4:NEW - -- WRITER: W0:I1, W2:I4 - - -- TEST: OUT OF ORDER SAMPLE AFTER DISPOSE - - Log("DDS Operation READ_INSTANCE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ALIVE_INSTANCE_STATE, ANY_VIEW_STATE, Instance 4] (No Data)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ_INSTANCE; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ALIVE_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.inst := kh4; - dds.ret_code := RETCODE_NO_DATA; - start_dds; - wait_on_dds; - -- MEM: I1S1(0), I1S2-(1), I4S1(4), I4S2-(7), I1S3(9) - -- ISTATE: I1:ALIVE, I4:DISOSED - -- VIEW: I1:NEW, I4:NEW - -- WRITER: W0:I1, W2:I4 - - Log("Current Time: 5s", INFO); - check_time <= gen_duration(5,0); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait_on_idle; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh3; - cc.payload := gen_payload(kh3,10); - cc.src_timestamp := gen_duration(3,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 3, Writer 2, Aligned Payload, ID 3] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 2; - rtps.ret_code := OK; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_SOURCE_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S1(0), I1S2-(1), I3S1(3), I4S1(4), I4S2-(7), I1S3(9) - -- ISTATE: I1:ALIVE, I3:ALIVE, I4:DISOSED - -- VIEW: I1:NEW, I3:NEW, I4:NEW - -- WRITER: W0:I1, W2:I3,I4 - - Log("Current Time: 6s", INFO); - check_time <= gen_duration(6,0); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait_on_idle; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh2; - cc.payload := gen_payload(kh2,10); - cc.src_timestamp := gen_duration(2,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 2, Writer 1, Aligned Payload, ID 2] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 1; - rtps.ret_code := OK; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_SOURCE_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I4S2-(7), I1S3(9) - -- ISTATE: I1:ALIVE, I2:ALIVE, I3:ALIVE, I4:DISOSED - -- VIEW: I1:NEW, I2:NEW, I3:NEW, I4:NEW - -- WRITER: W0:I1, W2:I3,I4 - - Log("Current Time: 7s", INFO); - check_time <= gen_duration(7,0); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait_on_idle; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_DISPOSED; - cc.instance := kh2; - cc.payload := gen_payload(kh2,5); - cc.src_timestamp := gen_duration(5,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Instance 2, Writer 1, ID 5] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 1; - rtps.ret_code := OK; - s := to_sample(cc,NOT_ALIVE_DISPOSED_INSTANCE_STATE); - add_sample(s,mem, BY_SOURCE_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I4S2-(7), I1S3(9) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:ALIVE, I4:DISOSED - -- VIEW: I1:NEW, I2:NEW, I3:NEW, I4:NEW - -- WRITER: W0:I1, W2:I3,I4 - - Log("Current Time: 8s", INFO); - check_time <= gen_duration(8,0); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait_on_idle; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_DISPOSED; - cc.instance := kh3; - cc.payload := gen_payload(kh3,5); - cc.src_timestamp := gen_duration(6,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Instance 3, Writer 2, ID 6] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 2; - rtps.ret_code := OK; - s := to_sample(cc,NOT_ALIVE_DISPOSED_INSTANCE_STATE); - add_sample(s,mem, BY_SOURCE_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I1S3(9) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:DISOSED - -- VIEW: I1:NEW, I2:NEW, I3:NEW, I4:NEW - -- WRITER: W0:I1, W2:I3,I4 - - Log("Current Time: 9s", INFO); - check_time <= gen_duration(9,0); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait_on_idle; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh4; - cc.payload := gen_payload(kh4,10); - cc.src_timestamp := gen_duration(8,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 4, Writer 2, Aligned Payload, ID 8] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 2; - rtps.ret_code := OK; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_SOURCE_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NEW, I2:NEW, I3:NEW, I4:NEW - -- WRITER: W0:I1, W2:I3,I4 - - Log("Current Time: 10s", INFO); - check_time <= gen_duration(10,0); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait_on_idle; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh2; - cc.payload := gen_payload(kh2,10); - cc.src_timestamp := gen_duration(10,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 2, Writer 1, Aligned Payload, ID 10] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 1; - rtps.ret_code := OK; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_SOURCE_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10) - -- ISTATE: I1:ALIVE, I2:ALIVE, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NEW, I2:NEW, I3:NEW, I4:NEW - -- WRITER: W0:I1, W2:I3,I4 - - Log("Current Time: 11s", INFO); - check_time <= gen_duration(11,0); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait_on_idle; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := TRUE; - cc.kind := NOT_ALIVE_DISPOSED; - cc.instance := kh2; - cc.payload := gen_payload(kh2,5); - cc.src_timestamp := gen_duration(11,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Instance 2, Writer 1, ID 11] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 1; - rtps.ret_code := OK; - s := to_sample(cc,NOT_ALIVE_DISPOSED_INSTANCE_STATE); - add_sample(s,mem, BY_SOURCE_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPSOED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NEW, I2:NEW, I3:NEW, I4:NEW - -- WRITER: W0:I1, W2:I3,I4 - - -- TEST: READ [MAX_SAMPLES < SAMPLES] - -- TEST: READ [ANY SSTATE, ANY ISTATE, ANY VIEW] - - Log("DDS Operation READ [MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE] (Expected ID0,ID1,ID2)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ; - dds.max_samples := 3; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - start_dds; - wait_on_dds; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NEW, I2:NEW, I3:NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: READ MARKS SAMPLES AS READ - -- TEST: READ_NEXT_SAMPLE [WITH UNREAD SAMPLE] - - Log("DDS Operation READ_NEXT_SAMPLE (Expected ID3)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ_NEXT_SAMPLE; - start_dds; - wait_on_dds; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NEW, I2:NEW, I3:NOT_NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: READ_INSTANCE [KNOWN INSTANCE, COMPATIBLE SAMPLES] - - Log("DDS Operation READ_INSTANCE [MAX_SAMPLES 1, NOT_READ_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Instance 3] (Expected ID9)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ_INSTANCE; - dds.max_samples := 1; - dds.sstate := NOT_READ_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.inst := kh1; - start_dds; - wait_on_dds; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NEW, I3:NOT_NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: READ_NEXT_INSTANCE [WITH NEXT INSTANCE, COMPATIBLE SAMPLES] - - Log("DDS Operation READ_NEXT_INSTANCE [MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Instance 3] (Expected ID4)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ_NEXT_INSTANCE; - dds.max_samples := 1; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.inst := kh3; - start_dds; - wait_on_dds; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NEW, I3:NOT_NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: READ [SPECIFIED SSTATE, ANY ISTATE, ANY VIEW] - -- TEST: READ [MAX_SAMPLES > SAMPLES] - - Log("DDS Operation READ [MAX_SAMPLES 20, READ_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE] (Expected ID0,ID1,ID2,ID3,ID4,ID9)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ; - dds.max_samples := 20; - dds.sstate := READ_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - start_dds; - wait_on_dds; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NEW, I3:NOT_NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: READ [SPECIFIED SSTATE, SPECIFIED ISTATE, ANY VIEW] - - Log("DDS Operation READ [MAX_SAMPLES 20, READ_SAMPLE_STATE, NOT_ALIVE_DISPOSED_INSTANCE_STATE, ANY_VIEW_STATE] (Expected ID2,ID3)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ; - dds.max_samples := 20; - dds.sstate := READ_SAMPLE_STATE; - dds.istate := NOT_ALIVE_DISPOSED_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - start_dds; - wait_on_dds; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NEW, I3:NOT_NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: READ [SPECIFIED SSTATE, ANY ISTATE, SPECIFIED VIEW] - -- TEST: READ MODIFIES VIEW STATE [READ CURRENT GENERATION] - -- TEST: READ MODIFIES VIEW STATE [READ PREVIOUS GENERATION] - - Log("DDS Operation READ [MAX_SAMPLES 20, READ_SAMPLE_STATE, ANY_INSTANCE_STATE, NEW_VIEW_STATE] (Expected ID2,ID4)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ; - dds.max_samples := 20; - dds.sstate := READ_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := NEW_VIEW_STATE; - start_dds; - wait_on_dds; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NEW, I3:NOT_NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: READ [SPECIFIED SSTATE, SPECIFIED ISTATE, SPECIFIED VIEW] - - Log("DDS Operation READ [MAX_SAMPLES 20, READ_SAMPLE_STATE, NOT_ALIVE_DISPOSED_INSTANCE_STATE, NEW_VIEW_STATE] (Expected ID2)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ; - dds.max_samples := 20; - dds.sstate := READ_SAMPLE_STATE; - dds.istate := NOT_ALIVE_DISPOSED_INSTANCE_STATE; - dds.vstate := NEW_VIEW_STATE; - start_dds; - wait_on_dds; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NEW, I3:NOT_NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: READ [ANY SSTATE, ANY ISTATE, SPECIFIED VIEW] - - Log("DDS Operation READ [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, NOT_NEW_VIEW_STATE] (Expected ID0,ID1,ID3,ID6,ID9)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := NOT_NEW_VIEW_STATE; - start_dds; - wait_on_dds; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NEW, I3:NOT_NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: READ [ANY SSTATE, SPECIFIED ISTATE, SPECIFIED VIEW] - - Log("DDS Operation READ [MAX_SAMPLES 20, ANY_SAMPLE_STATE, NOT_ALIVE_DISPOSED_INSTANCE_STATE, NOT_NEW_VIEW_STATE] (Expected ID3,ID6)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := NOT_ALIVE_DISPOSED_INSTANCE_STATE; - dds.vstate := NOT_NEW_VIEW_STATE; - start_dds; - wait_on_dds; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NEW, I3:NOT_NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: READ [ANY SSTATE, SPECIFIED ISTATE, ANY VIEW] - - Log("DDS Operation READ [MAX_SAMPLES 20, ANY_SAMPLE_STATE, NOT_ALIVE_DISPOSED_INSTANCE_STATE, ANY_VIEW_STATE] (Expected ID2,ID3,ID5,ID6,ID10,ID11)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := NOT_ALIVE_DISPOSED_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - start_dds; - wait_on_dds; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: READ_INSTANCE [UNKNOWN INSTANCE] - - Log("DDS Operation READ_INSTANCE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Unknown Instance] (Bad Parameter)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ_INSTANCE; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.inst := kh5; - dds.ret_code := RETCODE_BAD_PARAMETER; - start_dds; - wait_on_dds; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: READ_INSTANCE [KNOWN INSTANCE, UNCOMPATIBLE SAMPLES] - - Log("DDS Operation READ_INSTANCE [MAX_SAMPLES 20, NOT_READ_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Instance 1] (No Data)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ_INSTANCE; - dds.max_samples := 20; - dds.sstate := NOT_READ_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.inst := kh1; - dds.ret_code := RETCODE_NO_DATA; - start_dds; - wait_on_dds; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: READ_NEXT_INSTANCE [WITH NEXT INSTANCE, UNCOMPATIBLE SAMPLES] - - Log("DDS Operation READ_NEXT_INSTANCE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, NOT_ALIVE_DISPOSED_INSTANCE_STATE, ANY_VIEW_STATE, Instance 2] (No Data)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ_NEXT_INSTANCE; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := NOT_ALIVE_DISPOSED_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.inst := kh2; - dds.ret_code := RETCODE_NO_DATA; - start_dds; - wait_on_dds; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: READ_NEXT_INSTANCE [WITH NEXT INSTANCE, WITH COMPATIBLE SAMPLE, NOT DIRECT NEXT INSTANCE] - - Log("DDS Operation READ_NEXT_INSTANCE [MAX_SAMPLES 20, NOT_READ_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Instance 3] (Expected ID7,ID8)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ_NEXT_INSTANCE; - dds.max_samples := 20; - dds.sstate := NOT_READ_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.inst := kh3; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: READ [NO COMPATIBLE SAMPLES] - - Log("DDS Operation READ [MAX_SAMPLES 20, ANY_SAMPLE_STATE, NOT_ALIVE_NO_WRITERS_INSTANCE_STATE, ANY_VIEW_STATE] (No Data)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := NOT_ALIVE_NO_WRITERS_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.ret_code := RETCODE_NO_DATA; - start_dds; - wait_on_dds; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: READ_NEXT_SAMPLE [WITHOUT UNREAD SAMPLE] - - Log("DDS Operation READ_NEXT_SAMPLE (No Data)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ_NEXT_SAMPLE; - dds.ret_code := RETCODE_NO_DATA; - start_dds; - wait_on_dds; - -- MEM: I1S1(0), I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: TAKE - - Log("DDS Operation TAKE [MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE] (Expected ID0)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE; - dds.max_samples := 1; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - -- MEM: I1S2-(1), I2S1(2), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: TAKE_INSTANCE - - Log("DDS Operation TAKE_INSTANCE [MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Instance 2] (Expected ID2)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE_INSTANCE; - dds.max_samples := 1; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.inst := kh2; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - -- MEM: I1S2-(1), I3S1(3), I4S1(4), I2S2-(5), I3S2-(6), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: TAKE_NEXT_INSTANCE - -- TEST: READ_NEXT_INSTANCE [HANDLE_NIL] - - Log("DDS Operation TAKE_NEXT_INSTANCE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, HANDLE_NIL] (Expected ID3,ID6)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE_NEXT_INSTANCE; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.inst := HANDLE_NIL; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - -- MEM: I1S2-(1), I4S1(4), I2S2-(5), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: TAKE REMOVES SAMPLE - -- TEST: READ_INSTANCE [NO SAMPLES] - - Log("DDS Operation READ_INSTANCE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Instance 3] (No Data)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ_INSTANCE; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.inst := kh3; - dds.ret_code := RETCODE_NO_DATA; - start_dds; - wait_on_dds; - -- MEM: I1S2-(1), I4S1(4), I2S2-(5), I4S2-(7), I4S3(8), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - Log("DDS Operation TAKE_NEXT_INSTANCE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Instance 3] (Expected ID4,ID7,ID8)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE_NEXT_INSTANCE; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.inst := kh3; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - -- MEM: I1S2-(1), I2S2-(5), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: TAKE_INSTANCE [NO SAMPLES] - - Log("DDS Operation TAKE_INSTANCE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Instance 4] (No Data)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE_INSTANCE; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.inst := kh4; - dds.ret_code := RETCODE_NO_DATA; - start_dds; - wait_on_dds; - -- MEM: I1S2-(1), I2S2-(5), I1S3(9), I2S3(10), I2S4-(11) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - Log("DDS Operation TAKE_NEXT_INSTANCE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Instance 4] (Expected ID5,ID10,ID11)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE_NEXT_INSTANCE; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.inst := kh4; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - -- MEM: I1S2-(1), I1S3(9) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - Log("DDS Operation READ_INSTANCE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Instance 2] (No Data)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ_INSTANCE; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.inst := kh2; - dds.ret_code := RETCODE_NO_DATA; - start_dds; - wait_on_dds; - -- MEM: I1S2-(1), I1S3(9) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: READ_NEXT_INSTANCE [WITH SAMPLES, WITHOUT NEXT INSTANCE] - - Log("DDS Operation READ_NEXT_INSTANCE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Instance 1] (No Data)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ_NEXT_INSTANCE; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.inst := kh1; - dds.ret_code := RETCODE_NO_DATA; - start_dds; - wait_on_dds; - -- MEM: I1S2-(1), I1S3(9) - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - Log("DDS Operation TAKE_NEXT_INSTANCE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Instance 2] (Expected ID1,ID9)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE_NEXT_INSTANCE; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.inst := kh2; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - -- MEM: - - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: GET ALL DATA WITH READ_NEXT_INSTANCE - -- TEST: READ [NO SAMPLES] - - Log("DDS Operation READ [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE] (No Data)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.ret_code := RETCODE_NO_DATA; - start_dds; - wait_on_dds; - -- MEM: - - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: TAKE [NO SAMPLES] - - Log("DDS Operation TAKE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE] (No Data)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.ret_code := RETCODE_NO_DATA; - start_dds; - wait_on_dds; - -- MEM: - - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: READ_NEXT_INSTANCE [NO SAMPLE] - - Log("DDS Operation READ_NEXT_INSTANCE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, HANDLE_NIL] (No Data)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ_NEXT_INSTANCE; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.inst := HANDLE_NIL; - dds.ret_code := RETCODE_NO_DATA; - start_dds; - wait_on_dds; - -- MEM: - - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: TAKE_NEXT_INSTANCE [NO SAMPLE] - - Log("DDS Operation TAKE_NEXT_INSTANCE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, HANDLE_NIL] (No Data)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE_NEXT_INSTANCE; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.inst := HANDLE_NIL; - dds.ret_code := RETCODE_NO_DATA; - start_dds; - wait_on_dds; - -- MEM: - - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: READ_NEXT_SAMPLE [NO SAMPLE] - - Log("DDS Operation READ_NEXT_SAMPLE (No Data)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ_NEXT_SAMPLE; - dds.ret_code := RETCODE_NO_DATA; - start_dds; - wait_on_dds; - -- MEM: - - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: TAKE_NEXT_SAMPLE [NO SAMPLE] - - Log("DDS Operation TAKE_NEXT_SAMPLE (No Data)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE_NEXT_SAMPLE; - dds.ret_code := RETCODE_NO_DATA; - start_dds; - wait_on_dds; - -- MEM: - - -- ISTATE: I1:ALIVE, I2:DISPOSED, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - Log("Current Time: 12s", INFO); - check_time <= gen_duration(12,0); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait_on_idle; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh2; - cc.payload := gen_payload(kh2,10); - cc.src_timestamp := gen_duration(12,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 2, Writer 1, Aligned Payload, ID 12] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 1; - rtps.ret_code := OK; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I2S5(12) - -- ISTATE: I1:ALIVE, I2:ALIVE, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - -- TEST: TAKE_NEXT_SAMPLE - - Log("DDS Operation TAKE_NEXT_SAMPLE (Expected ID12)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE_NEXT_SAMPLE; - dds.ret_code := RETCODE_OK; - start_dds; - wait_on_dds; - -- MEM: - - -- ISTATE: I1:ALIVE, I2:ALIVE, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - Log("DDS Operation READ [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE] (No Data)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.ret_code := RETCODE_NO_DATA; - start_dds; - wait_on_dds; - -- MEM: - - -- ISTATE: I1:ALIVE, I2:ALIVE, I3:DISPOSED, I4:ALIVE - -- VIEW: I1:NOT_NEW, I2:NOT_NEW, I3:NOT_NEW, I4:NOT_NEW - -- WRITER: W0:I1, W1:I2, W2:I3,I4 - - wait_on_completion; - TranscriptOpen(RESULTS_FILE, APPEND_MODE); - SetTranscriptMirror; - ReportAlerts; - TranscriptClose; - std.env.stop; - wait; - end process; - - clock_prc : process - begin - clk <= '0'; - wait for 25 ns; - clk <= '1'; - wait for 25 ns; - end process; - - alert_prc : process(all) - begin - if rising_edge(clk) then - -- TODO - end if; - end process; - - dds_prc : process(all) - variable col : COLLECTION_TYPE := DEFAULT_COLLECTION; - begin - if rising_edge(clk) then - dds_done <= '0'; - case (dds_stage ) is - when IDLE => - if (dds_start = '1') then - dds_stage <= START; - else - dds_done <= '1'; - end if; - when START => - if (ack_dds = '1') then - dds_stage <= DONE; - dds_cnt <= 0; - end if; - when DONE => - if (done_dds = '1') then - AffirmIfEqual(ret_id, return_code_dds, dds.ret_code); - case (dds.ret_code) is - when RETCODE_OK => - gen_collection(mem, col, dds, TOPIC_PRESENTATION_QOS, TRUE); - dds_stage <= CHECK_SI; - dds_cnt <= 0; - when others => - dds_stage <= IDLE; - end case; - end if; - when CHECK_SI => - if (si_valid = '1') then - Log("Read Sample ID" & to_string(to_integer(si_source_timestamp(0))), DEBUG); - AffirmIfEqual(sstate_id, si_sample_state, col.s(dds_cnt).sstate); - AffirmIfEqual(vstate_id, si_view_state, col.s(dds_cnt).vstate); - AffirmIfEqual(istate_id, si_instance_state, col.s(dds_cnt).istate); - AffirmIfEqual(ts_id, to_unsigned(si_source_timestamp), to_unsigned(col.s(dds_cnt).ts)); - AffirmIfEqual(inst_id, to_unsigned(si_instance_handle), to_unsigned(col.s(dds_cnt).inst)); - AffirmIfEqual(pub_id, to_unsigned(si_publication_handle), to_unsigned(HANDLE_NIL)); - AffirmIfEqual(dis_gen_cnt_id, si_disposed_generation_count, std_logic_vector(to_unsigned(col.s(dds_cnt).dis_gen_cnt,WORD_WIDTH))); - AffirmIfEqual(no_w_gen_cnt_id, si_no_writers_generation_count, std_logic_vector(to_unsigned(col.s(dds_cnt).no_w_gen_cnt,WORD_WIDTH))); - AffirmIfEqual(srank_id, si_sample_rank, std_logic_vector(to_unsigned(col.s(dds_cnt).srank,WORD_WIDTH))); - AffirmIfEqual(grank_id, si_generation_rank, std_logic_vector(to_unsigned(col.s(dds_cnt).grank,WORD_WIDTH))); - AffirmIfEqual(agrank_id, si_absolute_generation_rank, std_logic_vector(to_unsigned(col.s(dds_cnt).agrank,WORD_WIDTH))); - if (si_valid_data = '1') then - AffirmIf(valid_id, col.s(dds_cnt).data /= EMPTY_TEST_PACKET, "Sample with Data not expected"); - dds_stage <= CHECK_DATA; - dds_cnt2 <= 0; - else - AffirmIf(valid_id, col.s(dds_cnt).data = EMPTY_TEST_PACKET, "Sample with Data expected"); - if (dds_cnt = col.len-1) then - -- DONE - dds_stage <= WAIT_EOC; - else - dds_cnt <= dds_cnt + 1; - end if; - end if; - end if; - AffirmIf(eoc_id, eoc = '0', "EOC pulled high"); - when CHECK_DATA => - if (valid_out_dds = '1') then - AffirmIfEqual(data_id, data_out_dds, col.s(dds_cnt).data.data(dds_cnt2)); - dds_cnt2 <= dds_cnt2 + 1; - if (dds_cnt2 = col.s(dds_cnt).data.length-1) then - AlertIf(data_id, last_word_out_dds /= '1', "Last Word Signal not pulled High", ERROR); - if (dds_cnt = col.len-1) then - -- DONE - dds_stage <= WAIT_EOC; - else - dds_stage <= CHECK_SI; - dds_cnt <= dds_cnt + 1; - end if; - end if; - end if; - when WAIT_EOC => - if (eoc = '1') then - dds_stage <= IDLE; - end if; - end case; - end if; - - -- DEFAULT - start_dds <= '0'; - opcode_dds <= NOP; - instance_state_dds <= ANY_INSTANCE_STATE; - view_state_dds <= ANY_VIEW_STATE; - sample_state_dds <= ANY_SAMPLE_STATE; - instance_handle_dds <= HANDLE_NIL; - max_samples_dds <= (others => '0'); - get_data_dds <= '0'; - ready_out_dds <= '0'; - - - case (dds_stage ) is - when START => - start_dds <= '1'; - opcode_dds <= dds.opcode; - instance_state_dds <= dds.istate; - view_state_dds <= dds.vstate; - sample_state_dds <= dds.sstate; - instance_handle_dds <= dds.inst; - max_samples_dds <= std_logic_vector(to_unsigned(dds.max_samples, WORD_WIDTH)); - when CHECK_SI => - if (si_valid = '1' and si_valid_data = '1') then - get_data_dds <= '1'; - end if; - when CHECK_DATA => - ready_out_dds <= '1'; - when others => - null; - end case; - end process; - - rtps_prc : process(all) - variable stimulus : TEST_PACKET_TYPE := EMPTY_TEST_PACKET; - begin - if rising_edge(clk) then - rtps_done <= '0'; - case (rtps_stage) is - when IDLE => - if (rtps_start = '1') then - rtps_stage <= START; - else - rtps_done <= '1'; - end if; - when START => - if (ack_rtps = '1') then - case (rtps.opcode) is - when ADD_CACHE_CHANGE => - gen_add_cache_change_dds(rtps.cc, rtps.lifespan, rtps.writer_pos, stimulus); - rtps_stage <= PUSH; - when others => - rtps_stage <= DONE; - end case; - end if; - when PUSH => - if (ready_in_rtps = '1') then - rtps_cnt <= rtps_cnt + 1; - if (rtps_cnt = stimulus.length-1) then - rtps_stage <= DONE; - end if; - end if; - when DONE => - if (done_rtps = '1') then - AffirmIfEqual(ret_id, HISTORY_CACHE_RESPONSE_TYPE'pos(ret_rtps), HISTORY_CACHE_RESPONSE_TYPE'pos(rtps.ret_code)); - rtps_stage <= IDLE; - end if; - end case; - end if; - - -- DEFAULT - start_rtps <= '0'; - opcode_rtps <= NOP; - valid_in_rtps <= '0'; - last_word_in_rtps <= '0'; - data_in_rtps <= (others => '0'); - - case (rtps_stage) is - when START => - start_rtps <= '1'; - opcode_rtps <= rtps.opcode; - case (rtps.opcode) is - when REMOVE_WRITER => - data_in_rtps <= std_logic_vector(to_unsigned(rtps.writer_pos,WORD_WIDTH)); - when others => - null; - end case; - when PUSH => - valid_in_rtps <= '1'; - data_in_rtps <= stimulus.data(rtps_cnt); - last_word_in_rtps <= stimulus.last(rtps_cnt); - when others => - null; - end case; - end process; - - watchdog : process - begin - wait for 1 ms; - Alert("Test timeout", FAILURE); - std.env.stop; - end process; - -end architecture; \ No newline at end of file diff --git a/src/Tests/Level_0/L0_dds_reader_test3_arznriu.vhd b/src/Tests/Level_0/L0_dds_reader_test3_arznriu.vhd deleted file mode 100644 index 6f5625b..0000000 --- a/src/Tests/Level_0/L0_dds_reader_test3_arznriu.vhd +++ /dev/null @@ -1,841 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library osvvm; -- Utility Library -context osvvm.OsvvmContext; - -use work.rtps_package.all; -use work.user_config.all; -use work.rtps_config_package.all; -use work.rtps_test_package.all; - --- This testbench tests the DDS handling of the DDS Reader. It tests the correctness of the DDS READ, TAKE, READ_NEXT_SAMPLE, TAKE_NEXT_SAMPLE, --- READ_INSTANCE, TAKE_INSTANCE, READ_NEXT_INSTANCE, TAKE_NEXT_INSTANCE Operations. --- More specifically the testbench covers following tests: --- TEST: READ [MAX_SAMPLES < SAMPLES] --- TEST: READ [MAX_SAMPLES > SAMPLES] --- TEST: READ [NO COMPATIBLE SAMPLES] --- TEST: READ [NO SAMPLES] --- TEST: TAKE --- TEST: TAKE [NO SAMPLES] --- TEST: TAKE_NEXT_SAMPLE --- TEST: TAKE_NEXT_SAMPLE [NO SAMPLE] --- TEST: READ_NEXT_SAMPLE [WITH UNREAD SAMPLE] --- TEST: READ_NEXT_SAMPLE [WITHOUT UNREAD SAMPLE] --- TEST: READ_NEXT_SAMPLE [NO SAMPLE] --- TEST: READ_INSTANCE --- TEST: TAKE_INSTANCE --- TEST: READ_NEXT_INSTANCE --- TEST: TAKE_NEXT_INSTANCE --- TEST: READ MARKS SAMPLES AS READ --- TEST: TAKE REMOVES SAMPLE --- TEST: READ MODIFIES VIEW STATE [READ CURRENT GENERATION] --- TEST: READ MODIFIES VIEW STATE [READ PREVIOUS GENERATION] - -entity L0_dds_reader_test3_arznriu is -end entity; - - -architecture testbench of L0_dds_reader_test3_arznriu is - - -- *CONSTANT DECLARATION* - constant MAX_REMOTE_ENDPOINTS : natural := 3; - - -- *TYPE DECLARATION* - type DDS_STAGE_TYPE is (IDLE, START, DONE, CHECK_SI, CHECK_DATA, WAIT_EOC); - type RTPS_STAGE_TYPE is (IDLE, START, PUSH, DONE); - - -- *SIGNAL DECLARATION* - signal clk : std_logic := '0'; - signal reset : std_logic := '1'; - signal check_time : TIME_TYPE := TIME_ZERO; - signal start_rtps, start_dds, ack_rtps, ack_dds, done_rtps, done_dds : std_logic := '0'; - signal opcode_rtps : HISTORY_CACHE_OPCODE_TYPE := NOP; - signal opcode_dds : DDS_READER_OPCODE_TYPE := NOP; - signal ret_rtps : HISTORY_CACHE_RESPONSE_TYPE := ERROR; - signal ready_in_rtps, valid_in_rtps, last_word_in_rtps : std_logic := '0'; - signal ready_out_dds, valid_out_dds, last_word_out_dds : std_logic := '0'; - signal data_in_rtps, data_out_dds : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); - signal get_data_dds, si_valid_data, si_valid, eoc : std_logic := '0'; - signal return_code_dds : std_logic_vector(RETURN_CODE_WIDTH-1 downto 0) := (others => '0'); - signal status : std_logic_vector(STATUS_KIND_WIDTH-1 downto 0) := (others => '0'); - signal instance_state_dds, si_instance_state : std_logic_vector(INSTANCE_STATE_KIND_WIDTH-1 downto 0) := ANY_INSTANCE_STATE; - signal view_state_dds, si_view_state : std_logic_vector(VIEW_STATE_KIND_WIDTH-1 downto 0) := ANY_VIEW_STATE; - signal sample_state_dds, si_sample_state : std_logic_vector(SAMPLE_STATE_KIND_WIDTH-1 downto 0) := ANY_SAMPLE_STATE; - signal instance_handle_dds, si_instance_handle : INSTANCE_HANDLE_TYPE := HANDLE_NIL; - signal max_samples_dds : std_logic_vector(MAX_SAMPLES_WIDTH-1 downto 0) := (others => '0'); - signal si_source_timestamp : TIME_TYPE := TIME_INVALID; - signal si_publication_handle : INSTANCE_HANDLE_TYPE := HANDLE_NIL; - signal si_disposed_generation_count : std_logic_vector(DISPOSED_GENERATION_COUNT_WIDTH-1 downto 0) := (others => '0'); - signal si_no_writers_generation_count : std_logic_vector(NO_WRITERS_GENERATION_COUNT_WIDTH-1 downto 0) := (others => '0'); - signal si_sample_rank : std_logic_vector(SAMPLE_RANK_WIDTH-1 downto 0) := (others => '0'); - signal si_generation_rank : std_logic_vector(GENERATION_RANK_WIDTH-1 downto 0) := (others => '0'); - signal si_absolute_generation_rank: std_logic_vector(ABSOLUTE_GENERATION_COUNT_WIDTH-1 downto 0) := (others => '0'); - - signal dds_start , dds_done , rtps_start, rtps_done : std_logic := '0'; - signal dds_cnt, dds_cnt2, rtps_cnt : natural := 0; - signal dds_stage : DDS_STAGE_TYPE := IDLE; - signal rtps_stage : RTPS_STAGE_TYPE := IDLE; - shared variable dds : DDS_READER_TEST_TYPE := DEFAULT_DDS_READER_TEST; - shared variable rtps : RTPS_READER_TEST_TYPE := DEFAULT_RTPS_READER_TEST; - shared variable mem : DDS_READER_MEM_TYPE := DEFAULT_DDS_READER_MEM; - signal data_id, ret_id, sstate_id, vstate_id, istate_id, inst_id, ts_id, pub_id, dis_gen_cnt_id, no_w_gen_cnt_id, srank_id, grank_id, agrank_id, eoc_id, valid_id : AlertLogIDType; - - -- *FUNCTION DECLARATION* - function extract_key_hash (payload : TEST_PACKET_TYPE) return INSTANCE_HANDLE_TYPE is - variable ret : INSTANCE_HANDLE_TYPE := HANDLE_NIL; - begin - for i in 0 to 3 loop - ret(i) := not payload.data(i); - end loop; - - return ret; - end function; - - function gen_sn(input : natural) return SEQUENCENUMBER_TYPE is - variable ret : SEQUENCENUMBER_TYPE; - begin - ret(0) := (others => '0'); - ret(1) := unsigned(int(input, WORD_WIDTH)); - return ret; - end function; - -begin - - -- Unit Under Test - uut : entity work.dds_reader(arch) - generic map ( - TIME_BASED_FILTER_QOS => DURATION_ZERO, - DEADLINE_QOS => DURATION_INFINITE, - MAX_SAMPLES => std_logic_vector(to_unsigned(15,CDR_LONG_WIDTH)), - MAX_INSTANCES => std_logic_vector(to_unsigned(4,CDR_LONG_WIDTH)), - MAX_SAMPLES_PER_INSTANCE => std_logic_vector(to_unsigned(15,CDR_LONG_WIDTH)), - HISTORY_QOS => KEEP_ALL_HISTORY_QOS, - RELIABILITY_QOS => RELIABLE_RELIABILITY_QOS, - PRESENTATION_QOS => INSTANCE_PRESENTATION_QOS, - DESTINATION_ORDER_QOS => BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS, - COHERENT_ACCESS => FALSE, - ORDERED_ACCESS => FALSE, - WITH_KEY => FALSE, - PAYLOAD_FRAME_SIZE => 11, - MAX_REMOTE_ENDPOINTS => MAX_REMOTE_ENDPOINTS - ) - port map ( - clk => clk, - reset => reset, - time => check_time, - start_rtps => start_rtps, - opcode_rtps => opcode_rtps, - ack_rtps => ack_rtps, - done_rtps => done_rtps, - ret_rtps => ret_rtps, - data_in_rtps => data_in_rtps, - valid_in_rtps => valid_in_rtps, - ready_in_rtps => ready_in_rtps, - last_word_in_rtps => last_word_in_rtps, - start_dds => start_dds, - ack_dds => ack_dds, - opcode_dds => opcode_dds, - instance_state_dds => instance_state_dds, - view_state_dds => view_state_dds, - sample_state_dds => sample_state_dds, - instance_handle_dds => instance_handle_dds, - max_samples_dds => max_samples_dds, - get_data_dds => get_data_dds, - done_dds => done_dds, - return_code_dds => return_code_dds, - ready_out_dds => ready_out_dds, - valid_out_dds => valid_out_dds, - data_out_dds => data_out_dds, - last_word_out_dds => last_word_out_dds, - sample_info.sample_state => si_sample_state, - sample_info.view_state => si_view_state, - sample_info.instance_state => si_instance_state, - sample_info.source_timestamp => si_source_timestamp, - sample_info.instance_handle => si_instance_handle, - sample_info.publication_handle => si_publication_handle, - sample_info.disposed_generation_count => si_disposed_generation_count, - sample_info.no_writers_generation_count => si_no_writers_generation_count, - sample_info.sample_rank => si_sample_rank, - sample_info.generation_rank => si_generation_rank, - sample_info.absolute_generation_rank => si_absolute_generation_rank, - sample_info.valid_data => si_valid_data, - sample_info_valid => si_valid, - sample_info_ack => '1', - eoc => eoc, - status => status - ); - - stimulus_prc : process - variable RV : RandomPType; - variable cc : CACHE_CHANGE_TYPE := DEFAULT_CACHE_CHANGE; - variable s : SAMPLE_TYPE := DEFAULT_SAMPLE; - variable kh1, kh2, kh3, kh4, kh5 : INSTANCE_HANDLE_TYPE := HANDLE_NIL; - - alias idle_sig is <>; - - impure function gen_payload(key_hash : INSTANCE_HANDLE_TYPE; len : natural) return TEST_PACKET_TYPE is - variable ret : TEST_PACKET_TYPE := EMPTY_TEST_PACKET; - begin - assert (len >= 4) report "Payload length has to be at least 16 Bytes long" severity FAILURE; - - for i in 0 to len-1 loop - if (i < 4) then - -- NOTE: Beginning of payload is negated key to allow deterministic Key Hash generation from the kh_prc - ret.data(ret.length) := not key_hash(i); - else - ret.data(ret.length) := RV.RandSlv(WORD_WIDTH); - end if; - ret.length := ret.length + 1; - end loop; - ret.last(ret.length-1) := '1'; - - return ret; - end function; - - impure function gen_key_hash return KEY_HASH_TYPE is - variable ret : KEY_HASH_TYPE := KEY_HASH_NIL; - begin - for i in 0 to KEY_HASH_TYPE'length-1 loop - ret(i) := RV.RandSlv(WORD_WIDTH); - end loop; - return ret; - end function; - - procedure start_dds is - begin - dds_start <= '1'; - wait until rising_edge(clk); - dds_start <= '0'; - wait until rising_edge(clk); - end procedure; - - procedure start_rtps is - begin - rtps_start <= '1'; - wait until rising_edge(clk); - rtps_start <= '0'; - wait until rising_edge(clk); - end procedure; - - procedure wait_on_dds is - begin - if (dds_done /= '1') then - wait until dds_done = '1'; - end if; - end procedure; - - procedure wait_on_rtps is - begin - if (rtps_done /= '1') then - wait until rtps_done = '1'; - end if; - end procedure; - - procedure wait_on_completion is - begin - if (rtps_done /= '1' or dds_done /= '1') then - wait until rtps_done = '1' and dds_done = '1'; - end if; - end procedure; - - -- NOTE: This procedure waits until the idle_sig is high for at least - -- two consecutive clock cycles. - procedure wait_on_idle is - variable first : boolean := TRUE; - begin - loop - if (idle_sig /= '1') then - wait until idle_sig = '1'; - elsif (not first) then - exit; - end if; - wait until rising_edge(clk); - wait until rising_edge(clk); - first := FALSE; - end loop; - end procedure; - - begin - - SetAlertLogName("L0_dds_reader_test3_arznriu - (KEEP ALL, Reliable, Zero TIME_BASED_FILTER, Keyless, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER, ACCESS SCOPE Instance, Unordered) - DDS Handling"); - SetAlertEnable(FAILURE, TRUE); - SetAlertEnable(ERROR, TRUE); - SetAlertEnable(WARNING, TRUE); - SetLogEnable(DEBUG, TRUE); - SetLogEnable(PASSED, FALSE); - SetLogEnable(INFO, TRUE); - RV.InitSeed(RV'instance_name); - sstate_id <= GetAlertLogID("Sample State", ALERTLOG_BASE_ID); - vstate_id <= GetAlertLogID("View State", ALERTLOG_BASE_ID); - istate_id <= GetAlertLogID("Instance State", ALERTLOG_BASE_ID); - ts_id <= GetAlertLogID("Source Timestamp", ALERTLOG_BASE_ID); - inst_id <= GetAlertLogID("Instance Handle", ALERTLOG_BASE_ID); - pub_id <= GetAlertLogID("Publication Hanlde", ALERTLOG_BASE_ID); - dis_gen_cnt_id <= GetAlertLogID("Disposed Generation Count", ALERTLOG_BASE_ID); - no_w_gen_cnt_id <= GetAlertLogID("No Writers Generation Count", ALERTLOG_BASE_ID); - srank_id <= GetAlertLogID("Sample Rank", ALERTLOG_BASE_ID); - grank_id <= GetAlertLogID("Generation Rank", ALERTLOG_BASE_ID); - agrank_id <= GetAlertLogID("Absolute Generation Rank", ALERTLOG_BASE_ID); - eoc_id <= GetAlertLogID("End Of Collection", ALERTLOG_BASE_ID); - valid_id <= GetAlertLogID("Valid Data", ALERTLOG_BASE_ID); - data_id <= GetAlertLogID("Data Out", ALERTLOG_BASE_ID); - ret_id <= GetAlertLogID("Return Code", ALERTLOG_BASE_ID); - - -- Key Hashes - kh1 := (x"F12C31DA", x"E3FE0F3F", x"01F36685", x"446518CA"); - kh2 := (x"BC070AC4", x"0BAB5811", x"14EA8D61", x"F669189B"); - kh3 := (x"0CEAB0C6", x"FA04B9AD", x"A96EB495", x"4E0EB999"); - kh4 := (x"A7EB605C", x"FF4BEF3A", x"3C5E8724", x"CCA0CA67"); - kh5 := gen_key_hash; - - - Log("Initiating Test", INFO); - Log("Current Time: 0s", INFO); - check_time <= TIME_ZERO; - reset <= '1'; - wait until rising_edge(clk); - wait until rising_edge(clk); - reset <= '0'; - -- MEM: - - -- ISTATE: - - -- VIEW: - - -- WRITER: - - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.payload := gen_payload(KEY_HASH_NIL,10); - cc.src_timestamp := gen_duration(0,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [Writer 0, Aligned Payload] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - rtps.ret_code := OK; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: S0 - -- ISTATE: ALIVE - -- VIEW: NEW - -- WRITER: 0 - - Log("Current Time: 1s", INFO); - check_time <= gen_duration(1,0); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait_on_idle; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := NOT_ALIVE_DISPOSED; - cc.src_timestamp := gen_duration(1,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [DISPOSE, Writer 0, Aligned Payload] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - rtps.ret_code := OK; - s := to_sample(cc,NOT_ALIVE_DISPOSED_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: S0, S1- - -- ISTATE: DISPOSED - -- VIEW: NEW - -- WRITER: 0 - - -- TEST: READ [MAX_SAMPLES < SAMPLES] - - Log("DDS Operation READ [MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE] (Expected ID0)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ; - dds.max_samples := 1; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - start_dds; - wait_on_dds; - -- MEM: S0, S1- - -- ISTATE: DISPOSED - -- VIEW: NOT_NEW - -- WRITER: 0 - - -- TEST: READ [NO COMPATIBLE SAMPLES] - -- TEST: READ MODIFIES VIEW STATE [READ CURRENT GENERATION] - - Log("DDS Operation READ [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, NEW_VIEW_STATE] (No Data)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := NEW_VIEW_STATE; - dds.ret_code := RETCODE_NO_DATA; - start_dds; - wait_on_dds; - -- MEM: S0, S1- - -- ISTATE: DISPOSED - -- VIEW: NOT_NEW - -- WRITER: 0 - - Log("Current Time: 2s", INFO); - check_time <= gen_duration(2,0); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait_on_idle; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.payload := gen_payload(KEY_HASH_NIL,10); - cc.src_timestamp := gen_duration(2,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [Writer 0, Aligned Payload] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - rtps.ret_code := OK; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: S0, S1-, S2 - -- ISTATE: ALIVE - -- VIEW: NEW - -- WRITER: 0 - - -- TEST: READ_NEXT_SAMPLE [WITH UNREAD SAMPLE] - - Log("DDS Operation READ_NEXT_SAMPLE (Expected ID1)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ_NEXT_SAMPLE; - start_dds; - wait_on_dds; - -- MEM: S0, S1-, S2 - -- ISTATE: ALIVE - -- VIEW: NEW - -- WRITER: 0 - - -- TEST: READ MARKS SAMPLES AS READ - -- TEST: READ MODIFIES VIEW STATE [READ PREVIOUS GENERATION] - -- TEST: READ [MAX_SAMPLES > SAMPLES] - - Log("DDS Operation READ [MAX_SAMPLES 20, READ_SAMPLE_STATE, ALIVE_INSTANCE_STATE, NEW_VIEW_STATE] (Expected ID0,ID1)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ; - dds.max_samples := 20; - dds.sstate := READ_SAMPLE_STATE; - dds.istate := ALIVE_INSTANCE_STATE; - dds.vstate := NEW_VIEW_STATE; - start_dds; - wait_on_dds; - -- MEM: S0, S1-, S2 - -- ISTATE: ALIVE - -- VIEW: NEW - -- WRITER: 0 - - -- TEST: TAKE - - Log("DDS Operation TAKE [MAX_SAMPLES 1, READ_SAMPLE_STATE, ALIVE_INSTANCE_STATE, NEW_VIEW_STATE] (Expected ID0)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE; - dds.max_samples := 1; - dds.sstate := READ_SAMPLE_STATE; - dds.istate := ALIVE_INSTANCE_STATE; - dds.vstate := NEW_VIEW_STATE; - start_dds; - wait_on_dds; - -- MEM: S1-, S2 - -- ISTATE: ALIVE - -- VIEW: NEW - -- WRITER: 0 - - -- TEST: TAKE_NEXT_SAMPLE - - Log("DDS Operation TAKE_NEXT_SAMPLE (Expected ID2)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE_NEXT_SAMPLE; - start_dds; - wait_on_dds; - -- MEM: S1- - -- ISTATE: ALIVE - -- VIEW: NOT_NEW - -- WRITER: 0 - - -- TEST: READ_NEXT_SAMPLE [WITHOUT UNREAD SAMPLE] - - Log("DDS Operation READ_NEXT_SAMPLE (No Data)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ_NEXT_SAMPLE; - dds.ret_code := RETCODE_NO_DATA; - start_dds; - wait_on_dds; - -- MEM: S1- - -- ISTATE: ALIVE - -- VIEW: NOT_NEW - -- WRITER: 0 - - Log("DDS Operation TAKE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE] (Expected ID1)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - start_dds; - wait_on_dds; - -- MEM: - - -- ISTATE: ALIVE - -- VIEW: NOT_NEW - -- WRITER: 0 - - -- TEST: TAKE REMOVES SAMPLE - -- TEST: TAKE [NO SAMPLES] - - Log("DDS Operation TAKE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE] (No Data)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.ret_code := RETCODE_NO_DATA; - start_dds; - wait_on_dds; - -- MEM: - - -- ISTATE: ALIVE - -- VIEW: NOT_NEW - -- WRITER: 0 - - -- TEST: READ [NO SAMPLES] - - Log("DDS Operation READ [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE] (No Data)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.ret_code := RETCODE_NO_DATA; - start_dds; - wait_on_dds; - -- MEM: - - -- ISTATE: ALIVE - -- VIEW: NOT_NEW - -- WRITER: 0 - - -- TEST: READ_NEXT_SAMPLE [NO SAMPLE] - - Log("DDS Operation READ_NEXT_SAMPLE (No Data)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ_NEXT_SAMPLE; - dds.ret_code := RETCODE_NO_DATA; - start_dds; - wait_on_dds; - -- MEM: - - -- ISTATE: ALIVE - -- VIEW: NOT_NEW - -- WRITER: 0 - - -- TEST: TAKE_NEXT_SAMPLE [NO SAMPLE] - - Log("DDS Operation TAKE_NEXT_SAMPLE (No Data)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE_NEXT_SAMPLE; - dds.ret_code := RETCODE_NO_DATA; - start_dds; - wait_on_dds; - -- MEM: - - -- ISTATE: ALIVE - -- VIEW: NOT_NEW - -- WRITER: 0 - - -- TEST: READ_INSTANCE - - Log("DDS Operation READ_INSTANCE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Instance 1] (Illegal Operation)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ_INSTANCE; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.inst := kh1; - dds.ret_code := RETCODE_ILLEGAL_OPERATION; - start_dds; - wait_on_dds; - -- MEM: - - -- ISTATE: ALIVE - -- VIEW: NOT_NEW - -- WRITER: 0 - - -- TEST: TAKE_INSTANCE - - Log("DDS Operation TAKE_INSTANCE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Instance 1] (Illegal Operation)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE_INSTANCE; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.inst := kh1; - dds.ret_code := RETCODE_ILLEGAL_OPERATION; - start_dds; - wait_on_dds; - -- MEM: - - -- ISTATE: ALIVE - -- VIEW: NOT_NEW - -- WRITER: 0 - - -- TEST: READ_NEXT_INSTANCE - - Log("DDS Operation READ_NEXT_INSTANCE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Instance 1] (Illegal Operation)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := READ_NEXT_INSTANCE; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.inst := kh1; - dds.ret_code := RETCODE_ILLEGAL_OPERATION; - start_dds; - wait_on_dds; - -- MEM: - - -- ISTATE: ALIVE - -- VIEW: NOT_NEW - -- WRITER: 0 - - -- TEST: TAKE_NEXT_INSTANCE - - Log("DDS Operation TAKE_NEXT_INSTANCE [MAX_SAMPLES 20, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE, Instance 1] (Illegal Operation)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := TAKE_NEXT_INSTANCE; - dds.max_samples := 20; - dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; - dds.vstate := ANY_VIEW_STATE; - dds.inst := kh1; - dds.ret_code := RETCODE_ILLEGAL_OPERATION; - start_dds; - wait_on_dds; - -- MEM: - - -- ISTATE: ALIVE - -- VIEW: NOT_NEW - -- WRITER: 0 - - wait_on_completion; - TranscriptOpen(RESULTS_FILE, APPEND_MODE); - SetTranscriptMirror; - ReportAlerts; - TranscriptClose; - std.env.stop; - wait; - end process; - - clock_prc : process - begin - clk <= '0'; - wait for 25 ns; - clk <= '1'; - wait for 25 ns; - end process; - - alert_prc : process(all) - begin - if rising_edge(clk) then - -- TODO - end if; - end process; - - dds_prc : process(all) - variable col : COLLECTION_TYPE := DEFAULT_COLLECTION; - begin - if rising_edge(clk) then - dds_done <= '0'; - case (dds_stage ) is - when IDLE => - if (dds_start = '1') then - dds_stage <= START; - else - dds_done <= '1'; - end if; - when START => - if (ack_dds = '1') then - dds_stage <= DONE; - dds_cnt <= 0; - end if; - when DONE => - if (done_dds = '1') then - AffirmIfEqual(ret_id, return_code_dds, dds.ret_code); - case (dds.ret_code) is - when RETCODE_OK => - gen_collection(mem, col, dds, INSTANCE_PRESENTATION_QOS, FALSE); - dds_stage <= CHECK_SI; - dds_cnt <= 0; - when others => - dds_stage <= IDLE; - end case; - end if; - when CHECK_SI => - if (si_valid = '1') then - Log("Read Sample ID" & to_string(to_integer(si_source_timestamp(0))), DEBUG); - AffirmIfEqual(sstate_id, si_sample_state, col.s(dds_cnt).sstate); - AffirmIfEqual(vstate_id, si_view_state, col.s(dds_cnt).vstate); - AffirmIfEqual(istate_id, si_instance_state, col.s(dds_cnt).istate); - AffirmIfEqual(ts_id, to_unsigned(si_source_timestamp), to_unsigned(col.s(dds_cnt).ts)); - AffirmIfEqual(inst_id, to_unsigned(si_instance_handle), to_unsigned(col.s(dds_cnt).inst)); - AffirmIfEqual(pub_id, to_unsigned(si_publication_handle), to_unsigned(HANDLE_NIL)); - AffirmIfEqual(dis_gen_cnt_id, si_disposed_generation_count, std_logic_vector(to_unsigned(col.s(dds_cnt).dis_gen_cnt,WORD_WIDTH))); - AffirmIfEqual(no_w_gen_cnt_id, si_no_writers_generation_count, std_logic_vector(to_unsigned(col.s(dds_cnt).no_w_gen_cnt,WORD_WIDTH))); - AffirmIfEqual(srank_id, si_sample_rank, std_logic_vector(to_unsigned(col.s(dds_cnt).srank,WORD_WIDTH))); - AffirmIfEqual(grank_id, si_generation_rank, std_logic_vector(to_unsigned(col.s(dds_cnt).grank,WORD_WIDTH))); - AffirmIfEqual(agrank_id, si_absolute_generation_rank, std_logic_vector(to_unsigned(col.s(dds_cnt).agrank,WORD_WIDTH))); - if (si_valid_data = '1') then - AffirmIf(valid_id, col.s(dds_cnt).data /= EMPTY_TEST_PACKET, "Sample with Data not expected"); - dds_stage <= CHECK_DATA; - dds_cnt2 <= 0; - else - AffirmIf(valid_id, col.s(dds_cnt).data = EMPTY_TEST_PACKET, "Sample with Data expected"); - if (dds_cnt = col.len-1) then - -- DONE - dds_stage <= WAIT_EOC; - else - dds_cnt <= dds_cnt + 1; - end if; - end if; - end if; - AffirmIf(eoc_id, eoc = '0', "EOC pulled high"); - when CHECK_DATA => - if (valid_out_dds = '1') then - AffirmIfEqual(data_id, data_out_dds, col.s(dds_cnt).data.data(dds_cnt2)); - dds_cnt2 <= dds_cnt2 + 1; - if (dds_cnt2 = col.s(dds_cnt).data.length-1) then - AlertIf(data_id, last_word_out_dds /= '1', "Last Word Signal not pulled High", ERROR); - if (dds_cnt = col.len-1) then - -- DONE - dds_stage <= WAIT_EOC; - else - dds_stage <= CHECK_SI; - dds_cnt <= dds_cnt + 1; - end if; - end if; - end if; - when WAIT_EOC => - if (eoc = '1') then - dds_stage <= IDLE; - end if; - end case; - end if; - - -- DEFAULT - start_dds <= '0'; - opcode_dds <= NOP; - instance_state_dds <= ANY_INSTANCE_STATE; - view_state_dds <= ANY_VIEW_STATE; - sample_state_dds <= ANY_SAMPLE_STATE; - instance_handle_dds <= HANDLE_NIL; - max_samples_dds <= (others => '0'); - get_data_dds <= '0'; - ready_out_dds <= '0'; - - - case (dds_stage ) is - when START => - start_dds <= '1'; - opcode_dds <= dds.opcode; - instance_state_dds <= dds.istate; - view_state_dds <= dds.vstate; - sample_state_dds <= dds.sstate; - instance_handle_dds <= dds.inst; - max_samples_dds <= std_logic_vector(to_unsigned(dds.max_samples, WORD_WIDTH)); - when CHECK_SI => - if (si_valid = '1' and si_valid_data = '1') then - get_data_dds <= '1'; - end if; - when CHECK_DATA => - ready_out_dds <= '1'; - when others => - null; - end case; - end process; - - rtps_prc : process(all) - variable stimulus : TEST_PACKET_TYPE := EMPTY_TEST_PACKET; - begin - if rising_edge(clk) then - rtps_done <= '0'; - case (rtps_stage) is - when IDLE => - if (rtps_start = '1') then - rtps_stage <= START; - else - rtps_done <= '1'; - end if; - when START => - if (ack_rtps = '1') then - case (rtps.opcode) is - when ADD_CACHE_CHANGE => - gen_add_cache_change_dds(rtps.cc, rtps.lifespan, rtps.writer_pos, stimulus); - rtps_stage <= PUSH; - when others => - rtps_stage <= DONE; - end case; - end if; - when PUSH => - if (ready_in_rtps = '1') then - rtps_cnt <= rtps_cnt + 1; - if (rtps_cnt = stimulus.length-1) then - rtps_stage <= DONE; - end if; - end if; - when DONE => - if (done_rtps = '1') then - AffirmIfEqual(ret_id, HISTORY_CACHE_RESPONSE_TYPE'pos(ret_rtps), HISTORY_CACHE_RESPONSE_TYPE'pos(rtps.ret_code)); - rtps_stage <= IDLE; - end if; - end case; - end if; - - -- DEFAULT - start_rtps <= '0'; - opcode_rtps <= NOP; - valid_in_rtps <= '0'; - last_word_in_rtps <= '0'; - data_in_rtps <= (others => '0'); - - case (rtps_stage) is - when START => - start_rtps <= '1'; - opcode_rtps <= rtps.opcode; - case (rtps.opcode) is - when REMOVE_WRITER => - data_in_rtps <= std_logic_vector(to_unsigned(rtps.writer_pos,WORD_WIDTH)); - when others => - null; - end case; - when PUSH => - valid_in_rtps <= '1'; - data_in_rtps <= stimulus.data(rtps_cnt); - last_word_in_rtps <= stimulus.last(rtps_cnt); - when others => - null; - end case; - end process; - - watchdog : process - begin - wait for 1 ms; - Alert("Test timeout", FAILURE); - std.env.stop; - end process; - -end architecture; \ No newline at end of file diff --git a/src/Tests/Level_0/L0_dds_reader_test4.vhd b/src/Tests/Level_0/L0_dds_reader_test4.vhd new file mode 100644 index 0000000..5112b5c --- /dev/null +++ b/src/Tests/Level_0/L0_dds_reader_test4.vhd @@ -0,0 +1,957 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library osvvm; -- Utility Library +context osvvm.OsvvmContext; + +use work.rtps_package.all; +use work.user_config.all; +use work.rtps_config_package.all; +use work.rtps_test_package.all; + +-- This testbench tests the Deadline Handling of the DDS Reader, and more specifically the GET_REQUESTED_DEADLINE_MISSED_STATUS DDS Operation. + +entity L0_dds_reader_test4 is +end entity; + + +architecture testbench of L0_dds_reader_test4 is + + -- *CONSTANT DECLARATION* + constant MAX_REMOTE_ENDPOINTS : natural := 3; + constant NUM_READERS : natural := 3; + + impure function gen_test_config return CONFIG_ARRAY_TYPE is + variable ret : CONFIG_ARRAY_TYPE(0 to NUM_READERS-1) := (others => DEFAULT_WRITER_CONFIG); + begin + -- arzkriu + ret(0).TIME_BASED_FILTER_QOS := DURATION_ZERO; + ret(0).DEADLINE_QOS := gen_duration(1 sec); + ret(0).MAX_SAMPLES := std_logic_vector(to_unsigned(10,CDR_LONG_WIDTH)); + ret(0).MAX_INSTANCES := std_logic_vector(to_unsigned(4,CDR_LONG_WIDTH)); + ret(0).MAX_SAMPLES_PER_INSTANCE := std_logic_vector(to_unsigned(10,CDR_LONG_WIDTH)); + ret(0).HISTORY_QOS := KEEP_ALL_HISTORY_QOS; + ret(0).RELIABILITY_QOS := RELIABLE_RELIABILITY_QOS; + ret(0).PRESENTATION_QOS := INSTANCE_PRESENTATION_QOS; + ret(0).DESTINATION_ORDER_QOS := BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS; + ret(0).COHERENT_ACCESS := FALSE; + ret(0).ORDERED_ACCESS := FALSE; + ret(0).WITH_KEY := TRUE; + ret(0).MAX_PAYLOAD_SIZE := 40; + -- arznriu + ret(1).TIME_BASED_FILTER_QOS := DURATION_ZERO; + ret(1).DEADLINE_QOS := gen_duration(1 sec); + ret(1).MAX_SAMPLES := std_logic_vector(to_unsigned(10,CDR_LONG_WIDTH)); + ret(1).MAX_INSTANCES := std_logic_vector(to_unsigned(4,CDR_LONG_WIDTH)); + ret(1).MAX_SAMPLES_PER_INSTANCE := std_logic_vector(to_unsigned(10,CDR_LONG_WIDTH)); + ret(1).HISTORY_QOS := KEEP_ALL_HISTORY_QOS; + ret(1).RELIABILITY_QOS := RELIABLE_RELIABILITY_QOS; + ret(1).PRESENTATION_QOS := INSTANCE_PRESENTATION_QOS; + ret(1).DESTINATION_ORDER_QOS := BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS; + ret(1).COHERENT_ACCESS := FALSE; + ret(1).ORDERED_ACCESS := FALSE; + ret(1).WITH_KEY := FALSE; + ret(1).MAX_PAYLOAD_SIZE := 40; + -- arzkriu + ret(2).TIME_BASED_FILTER_QOS := DURATION_ZERO; + ret(2).DEADLINE_QOS := gen_duration(2 sec); + ret(2).MAX_SAMPLES := std_logic_vector(to_unsigned(10,CDR_LONG_WIDTH)); + ret(2).MAX_INSTANCES := std_logic_vector(to_unsigned(4,CDR_LONG_WIDTH)); + ret(2).MAX_SAMPLES_PER_INSTANCE := std_logic_vector(to_unsigned(10,CDR_LONG_WIDTH)); + ret(2).HISTORY_QOS := KEEP_ALL_HISTORY_QOS; + ret(2).RELIABILITY_QOS := RELIABLE_RELIABILITY_QOS; + ret(2).PRESENTATION_QOS := INSTANCE_PRESENTATION_QOS; + ret(2).DESTINATION_ORDER_QOS := BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS; + ret(2).COHERENT_ACCESS := FALSE; + ret(2).ORDERED_ACCESS := FALSE; + ret(2).WITH_KEY := TRUE; + ret(2).MAX_PAYLOAD_SIZE := 40; + return ret; + end function; + constant TEST_CONFIG : CONFIG_ARRAY_TYPE := gen_test_config; + + -- *TYPE DECLARATION* + type DDS_STAGE_TYPE is (IDLE, START, DONE, CHECK_SI, CHECK_DATA, WAIT_EOC, CHECK_DEADLINE); + type RTPS_STAGE_TYPE is (IDLE, START, PUSH, DONE); + type DDS_READER_MEM_ARRAY_TYPE is array (0 to NUM_READERS-1) of DDS_READER_MEM_TYPE; + + -- *SIGNAL DECLARATION* + signal clk : std_logic := '0'; + signal reset : std_logic := '1'; + signal check_time : TIME_TYPE := TIME_ZERO; + signal start_rtps, start_dds, ack_rtps, ack_dds, done_rtps, done_dds : std_logic_vector(0 to NUM_READERS-1) := (others => '0'); + signal opcode_rtps : HISTORY_CACHE_OPCODE_ARRAY_TYPE(0 to NUM_READERS-1) := (others => NOP); + signal opcode_dds : DDS_READER_OPCODE_ARRAY_TYPE(0 to NUM_READERS-1) := (others => NOP); + signal ret_rtps : HISTORY_CACHE_RESPONSE_ARRAY_TYPE(0 to NUM_READERS-1) := (others => ERROR); + signal ready_in_rtps, valid_in_rtps, last_word_in_rtps : std_logic_vector(0 to NUM_READERS-1) := (others => '0'); + signal ready_out_dds, valid_out_dds, last_word_out_dds : std_logic_vector(0 to NUM_READERS-1) := (others => '0'); + signal data_in_rtps, data_out_dds : WORD_ARRAY_TYPE(0 to NUM_READERS-1) := (others => (others => '0')); + signal get_data_dds, si_valid, eoc : std_logic_vector(0 to NUM_READERS-1) := (others => '0'); + signal return_code_dds : RETURN_CODE_ARRAY_TYPE(0 to NUM_READERS-1) := (others => (others => '0')); + signal status : STATUS_KIND_ARRAY_TYPE(0 to NUM_READERS-1) := (others => (others => '0')); + signal instance_state_dds : INSTANCE_STATE_ARRAY_TYPE(0 to NUM_READERS-1) := (others => ANY_INSTANCE_STATE); + signal view_state_dds : VIEW_STATE_ARRAY_TYPE(0 to NUM_READERS-1) := (others => ANY_VIEW_STATE); + signal sample_state_dds : SAMPLE_STATE_ARRAY_TYPE(0 to NUM_READERS-1) := (others => ANY_SAMPLE_STATE); + signal instance_handle_dds : INSTANCE_HANDLE_ARRAY_TYPE(0 to NUM_READERS-1) := (others => HANDLE_NIL); + signal max_samples_dds : MAX_SAMPLES_ARRAY_TYPE(0 to NUM_READERS-1) := (others => (others => '0')); + signal sample_info : SAMPLE_INFO_ARRAY_TYPE(0 to NUM_READERS-1); + + signal ind : natural := 0; + signal dds_start , dds_done , rtps_start, rtps_done : std_logic := '0'; + signal dds_cnt, dds_cnt2, rtps_cnt : natural := 0; + signal dds_stage : DDS_STAGE_TYPE := IDLE; + signal rtps_stage : RTPS_STAGE_TYPE := IDLE; + shared variable dds : DDS_READER_TEST_TYPE := DEFAULT_DDS_READER_TEST; + shared variable rtps : RTPS_READER_TEST_TYPE := DEFAULT_RTPS_READER_TEST; + shared variable mem : DDS_READER_MEM_ARRAY_TYPE := (others => DEFAULT_DDS_READER_MEM); + signal data_id, ret_id, sstate_id, vstate_id, istate_id, inst_id, ts_id, pub_id, dis_gen_cnt_id, no_w_gen_cnt_id, srank_id, grank_id, agrank_id, eoc_id, valid_id, status_id : AlertLogIDType; + + -- *FUNCTION DECLARATION* + function extract_key_hash (payload : TEST_PACKET_TYPE) return INSTANCE_HANDLE_TYPE is + variable ret : INSTANCE_HANDLE_TYPE := HANDLE_NIL; + begin + for i in 0 to 3 loop + ret(i) := not payload.data(i); + end loop; + + return ret; + end function; + + function gen_sn(input : natural) return SEQUENCENUMBER_TYPE is + variable ret : SEQUENCENUMBER_TYPE; + begin + ret(0) := (others => '0'); + ret(1) := unsigned(int(input, WORD_WIDTH)); + return ret; + end function; + + procedure wait_on_sig(signal sig : std_logic) is + begin + if (sig /= '1') then + wait on sig until sig = '1'; + end if; + end procedure; + +begin + + -- Unit Under Test + uut : entity work.dds_reader(arch) + generic map ( + NUM_READERS => NUM_READERS, + CONFIG_ARRAY => to_QUARTUS_CONFIG_ARRAY_TYPE(TEST_CONFIG), + MAX_REMOTE_ENDPOINTS => MAX_REMOTE_ENDPOINTS + ) + port map ( + clk => clk, + reset => reset, + time => check_time, + start_rtps => start_rtps, + opcode_rtps => opcode_rtps, + ack_rtps => ack_rtps, + done_rtps => done_rtps, + ret_rtps => ret_rtps, + data_in_rtps => data_in_rtps, + valid_in_rtps => valid_in_rtps, + ready_in_rtps => ready_in_rtps, + last_word_in_rtps => last_word_in_rtps, + start_dds => start_dds, + ack_dds => ack_dds, + opcode_dds => opcode_dds, + instance_state_dds => instance_state_dds, + view_state_dds => view_state_dds, + sample_state_dds => sample_state_dds, + instance_handle_dds => instance_handle_dds, + max_samples_dds => max_samples_dds, + get_data_dds => get_data_dds, + done_dds => done_dds, + return_code_dds => return_code_dds, + ready_out_dds => ready_out_dds, + valid_out_dds => valid_out_dds, + data_out_dds => data_out_dds, + last_word_out_dds => last_word_out_dds, + sample_info => sample_info, + sample_info_valid => si_valid, + sample_info_ack => (others => '1'), + eoc => eoc, + status => status + ); + + stimulus_prc : process + variable RV : RandomPType; + variable cc : CACHE_CHANGE_TYPE := DEFAULT_CACHE_CHANGE; + variable s : SAMPLE_TYPE := DEFAULT_SAMPLE; + variable kh1, kh2, kh3, kh4, kh5 : INSTANCE_HANDLE_TYPE := HANDLE_NIL; + + alias idle_sig is <>; + + impure function gen_payload(key_hash : INSTANCE_HANDLE_TYPE; len : natural) return TEST_PACKET_TYPE is + variable ret : TEST_PACKET_TYPE := EMPTY_TEST_PACKET; + begin + assert (len >= 4) report "Payload length has to be at least 16 Bytes long" severity FAILURE; + + for i in 0 to len-1 loop + if (i < 4) then + -- NOTE: Beginning of payload is negated key to allow deterministic Key Hash generation from the kh_prc + ret.data(ret.length) := not key_hash(i); + else + ret.data(ret.length) := RV.RandSlv(WORD_WIDTH); + end if; + ret.length := ret.length + 1; + end loop; + ret.last(ret.length-1) := '1'; + + return ret; + end function; + + impure function gen_key_hash return KEY_HASH_TYPE is + variable ret : KEY_HASH_TYPE := KEY_HASH_NIL; + begin + for i in 0 to KEY_HASH_TYPE'length-1 loop + ret(i) := RV.RandSlv(WORD_WIDTH); + end loop; + return ret; + end function; + + procedure start_dds is + begin + dds_start <= '1'; + wait until rising_edge(clk); + dds_start <= '0'; + wait until rising_edge(clk); + end procedure; + + procedure start_rtps is + begin + rtps_start <= '1'; + wait until rising_edge(clk); + rtps_start <= '0'; + wait until rising_edge(clk); + end procedure; + + procedure wait_on_completion is + begin + if (rtps_done /= '1' or dds_done /= '1') then + wait until rtps_done = '1' and dds_done = '1'; + end if; + end procedure; + + -- NOTE: This procedure waits until the idle_sig is high for at least + -- two consecutive clock cycles. + procedure wait_on_idle is + variable first : boolean := TRUE; + begin + loop + if (idle_sig /= '1') then + wait until idle_sig = '1'; + elsif (not first) then + exit; + end if; + wait until rising_edge(clk); + wait until rising_edge(clk); + first := FALSE; + end loop; + end procedure; + + begin + + SetAlertLogName("L0_dds_reader_test4 - Deadline Handling"); + SetAlertEnable(FAILURE, TRUE); + SetAlertEnable(ERROR, TRUE); + SetAlertEnable(WARNING, TRUE); + SetLogEnable(DEBUG, FALSE); + SetLogEnable(PASSED, FALSE); + SetLogEnable(INFO, TRUE); + RV.InitSeed(RV'instance_name); + sstate_id <= GetAlertLogID("Sample State", ALERTLOG_BASE_ID); + vstate_id <= GetAlertLogID("View State", ALERTLOG_BASE_ID); + istate_id <= GetAlertLogID("Instance State", ALERTLOG_BASE_ID); + ts_id <= GetAlertLogID("Source Timestamp", ALERTLOG_BASE_ID); + inst_id <= GetAlertLogID("Instance Handle", ALERTLOG_BASE_ID); + pub_id <= GetAlertLogID("Publication Hanlde", ALERTLOG_BASE_ID); + dis_gen_cnt_id <= GetAlertLogID("Disposed Generation Count", ALERTLOG_BASE_ID); + no_w_gen_cnt_id <= GetAlertLogID("No Writers Generation Count", ALERTLOG_BASE_ID); + srank_id <= GetAlertLogID("Sample Rank", ALERTLOG_BASE_ID); + grank_id <= GetAlertLogID("Generation Rank", ALERTLOG_BASE_ID); + agrank_id <= GetAlertLogID("Absolute Generation Rank", ALERTLOG_BASE_ID); + eoc_id <= GetAlertLogID("End of Collection", ALERTLOG_BASE_ID); + valid_id <= GetAlertLogID("Valid Data", ALERTLOG_BASE_ID); + data_id <= GetAlertLogID("Data Out", ALERTLOG_BASE_ID); + ret_id <= GetAlertLogID("Return Code", ALERTLOG_BASE_ID); + status_id <= GetAlertLogID("Communication Status", ALERTLOG_BASE_ID); + + -- Key Hashes + kh3 := (x"0CEAB0C6", x"FA04B9AD", x"A96EB495", x"4E0EB999"); + kh4 := (x"A7EB605C", x"FF4BEF3A", x"3C5E8724", x"CCA0CA67"); + kh2 := (x"BC070AC4", x"0BAB5811", x"14EA8D61", x"F669189B"); + kh1 := (x"F12C31DA", x"E3FE0F3F", x"01F36685", x"446518CA"); + + + Log("Initiating Test", INFO); + Log("Current Time: 0s", INFO); + check_time <= TIME_ZERO; + reset <= '1'; + wait until rising_edge(clk); + wait until rising_edge(clk); + reset <= '0'; + wait_on_idle; + + AffirmIf(status_id,(status(0) and REQUESTED_DEADLINE_MISSED_STATUS) /= REQUESTED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(1) and REQUESTED_DEADLINE_MISSED_STATUS) /= REQUESTED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(2) and REQUESTED_DEADLINE_MISSED_STATUS) /= REQUESTED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1"); + + Log("Current Time: 1s", INFO); + check_time <= gen_duration(1 sec); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait_on_idle; + + AffirmIf(status_id,(status(0) and REQUESTED_DEADLINE_MISSED_STATUS) /= REQUESTED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(1) and REQUESTED_DEADLINE_MISSED_STATUS) /= REQUESTED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(2) and REQUESTED_DEADLINE_MISSED_STATUS) /= REQUESTED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1"); + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh1; + cc.payload := gen_payload(kh1,10); + cc.src_timestamp := gen_duration(1 sec); + + Log("R0,R1,R2: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Aligned Payload]", INFO); + Log("R0,R1,R2: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 0; + rtps.ret_code := OK; + s := to_sample(cc,ALIVE_INSTANCE_STATE); + add_sample(s,mem(0), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(1), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(2), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + -- READER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- READER 1 + ind <= 1; + start_rtps; + wait_on_sig(rtps_done); + -- READER 2 + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh2; + cc.payload := gen_payload(kh2,10); + cc.src_timestamp := gen_duration(2 sec); + + Log("R0,R2: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 2, Writer 1, Aligned Payload]", INFO); + Log("R0,R2: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 1; + rtps.ret_code := OK; + s := to_sample(cc,ALIVE_INSTANCE_STATE); + add_sample(s,mem(0), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(2), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + -- READER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- READER 2 + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh4; + cc.payload := gen_payload(kh4,10); + cc.src_timestamp := gen_duration(3 sec); + + Log("R0,R2: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 4, Writer 0, Aligned Payload]", INFO); + Log("R0,R2: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 0; + rtps.ret_code := OK; + s := to_sample(cc,ALIVE_INSTANCE_STATE); + add_sample(s,mem(0), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(2), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + -- READER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- READER 2 + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("Current Time: 2s", INFO); + check_time <= gen_duration(2 sec); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait_on_idle; + + AffirmIf(status_id,(status(0) and REQUESTED_DEADLINE_MISSED_STATUS) /= REQUESTED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(1) and REQUESTED_DEADLINE_MISSED_STATUS) /= REQUESTED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(2) and REQUESTED_DEADLINE_MISSED_STATUS) /= REQUESTED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1"); + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh1; + cc.payload := gen_payload(kh1,10); + cc.src_timestamp := gen_duration(4 sec); + + Log("R0,R2: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Aligned Payload]", INFO); + Log("R0,R2: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 0; + rtps.ret_code := OK; + s := to_sample(cc,ALIVE_INSTANCE_STATE); + add_sample(s,mem(0), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(2), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + -- READER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- READER 2 + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh4; + cc.payload := gen_payload(kh4,10); + cc.src_timestamp := gen_duration(5 sec); + + Log("R0,R1,R2: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 4, Writer 1, Aligned Payload]", INFO); + Log("R0,R1,R2: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 1; + rtps.ret_code := OK; + s := to_sample(cc,ALIVE_INSTANCE_STATE); + add_sample(s,mem(0), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(1), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(2), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + -- READER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- READER 1 + ind <= 1; + start_rtps; + wait_on_sig(rtps_done); + -- READER 2 + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("Current Time: 3s", INFO); + check_time <= gen_duration(3 sec); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait_on_idle; + + AffirmIf(status_id,(status(0) and REQUESTED_DEADLINE_MISSED_STATUS) = REQUESTED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(1) and REQUESTED_DEADLINE_MISSED_STATUS) /= REQUESTED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(2) and REQUESTED_DEADLINE_MISSED_STATUS) /= REQUESTED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1"); + + Log("R0: DDS Operation GET_REQUESTED_DEADLINE_MISSED_STATUS", INFO); + Log("R0: Expected: count 1, change 1, Instance 2", DEBUG); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := GET_REQUESTED_DEADLINE_MISSED_STATUS; + dds.ret_code := RETCODE_OK; + dds.count := 1; + dds.change := 1; + dds.inst := kh2; + -- READER 0 + ind <= 0; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + + AffirmIf(status_id,(status(0) and REQUESTED_DEADLINE_MISSED_STATUS) /= REQUESTED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(1) and REQUESTED_DEADLINE_MISSED_STATUS) /= REQUESTED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(2) and REQUESTED_DEADLINE_MISSED_STATUS) /= REQUESTED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1"); + + Log("R1: DDS Operation GET_REQUESTED_DEADLINE_MISSED_STATUS", INFO); + Log("R1: Expected: count 0, change 0", DEBUG); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := GET_REQUESTED_DEADLINE_MISSED_STATUS; + dds.ret_code := RETCODE_OK; + dds.count := 0; + dds.change := 0; + dds.inst := HANDLE_NIL; + -- READER 1 + ind <= 1; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + + AffirmIf(status_id,(status(0) and REQUESTED_DEADLINE_MISSED_STATUS) /= REQUESTED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(1) and REQUESTED_DEADLINE_MISSED_STATUS) /= REQUESTED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(2) and REQUESTED_DEADLINE_MISSED_STATUS) /= REQUESTED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1"); + + Log("R2: DDS Operation GET_REQUESTED_DEADLINE_MISSED_STATUS", INFO); + Log("R2: Expected: count 0, change 0, HANDLE_NIL", DEBUG); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := GET_REQUESTED_DEADLINE_MISSED_STATUS; + dds.ret_code := RETCODE_OK; + dds.count := 0; + dds.change := 0; + dds.inst := HANDLE_NIL; + -- READER 2 + ind <= 2; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + + AffirmIf(status_id,(status(0) and REQUESTED_DEADLINE_MISSED_STATUS) /= REQUESTED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(1) and REQUESTED_DEADLINE_MISSED_STATUS) /= REQUESTED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(2) and REQUESTED_DEADLINE_MISSED_STATUS) /= REQUESTED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1"); + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh3; + cc.payload := gen_payload(kh3,10); + cc.src_timestamp := gen_duration(6 sec); + + Log("R0,R2: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 3, Writer 2, Aligned Payload]", INFO); + Log("R0,R2: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 2; + rtps.ret_code := OK; + s := to_sample(cc,ALIVE_INSTANCE_STATE); + add_sample(s,mem(0), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(2), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + -- READER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- READER 2 + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("Current Time: 4s", INFO); + check_time <= gen_duration(4 sec); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait_on_idle; + + AffirmIf(status_id,(status(0) and REQUESTED_DEADLINE_MISSED_STATUS) = REQUESTED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(1) and REQUESTED_DEADLINE_MISSED_STATUS) = REQUESTED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(2) and REQUESTED_DEADLINE_MISSED_STATUS) = REQUESTED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0"); + + Log("R0: DDS Operation GET_REQUESTED_DEADLINE_MISSED_STATUS", INFO); + Log("R0: Expected: count 4, change 3, Instance 1", DEBUG); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := GET_REQUESTED_DEADLINE_MISSED_STATUS; + dds.ret_code := RETCODE_OK; + dds.count := 4; + dds.change := 3; + dds.inst := kh1; + -- READER 0 + ind <= 0; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + + AffirmIf(status_id,(status(0) and REQUESTED_DEADLINE_MISSED_STATUS) /= REQUESTED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(1) and REQUESTED_DEADLINE_MISSED_STATUS) = REQUESTED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(2) and REQUESTED_DEADLINE_MISSED_STATUS) = REQUESTED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0"); + + Log("R1: DDS Operation GET_REQUESTED_DEADLINE_MISSED_STATUS", INFO); + Log("R1: Expected: count 1, change 1", DEBUG); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := GET_REQUESTED_DEADLINE_MISSED_STATUS; + dds.ret_code := RETCODE_OK; + dds.count := 1; + dds.change := 1; + dds.inst := HANDLE_NIL; + -- READER 1 + ind <= 1; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + + AffirmIf(status_id,(status(0) and REQUESTED_DEADLINE_MISSED_STATUS) /= REQUESTED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(1) and REQUESTED_DEADLINE_MISSED_STATUS) /= REQUESTED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(2) and REQUESTED_DEADLINE_MISSED_STATUS) = REQUESTED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0"); + + Log("R2: DDS Operation GET_REQUESTED_DEADLINE_MISSED_STATUS", INFO); + Log("R2: Expected: count 1, change 1, Instance 2", DEBUG); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := GET_REQUESTED_DEADLINE_MISSED_STATUS; + dds.ret_code := RETCODE_OK; + dds.count := 1; + dds.change := 1; + dds.inst := kh2; + -- READER 2 + ind <= 2; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + + AffirmIf(status_id,(status(0) and REQUESTED_DEADLINE_MISSED_STATUS) /= REQUESTED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(1) and REQUESTED_DEADLINE_MISSED_STATUS) /= REQUESTED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(2) and REQUESTED_DEADLINE_MISSED_STATUS) /= REQUESTED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1"); + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := FALSE; + cc.kind := ALIVE; + cc.instance := kh4; + cc.payload := gen_payload(kh4,10); + cc.src_timestamp := gen_duration(7 sec); + + Log("R0,R1,R2: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 4, Writer 2, Aligned Payload]", INFO); + Log("R0,R1,R2: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 2; + rtps.ret_code := OK; + s := to_sample(cc,ALIVE_INSTANCE_STATE); + add_sample(s,mem(0), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(1), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(2), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + -- READER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + -- READER 1 + ind <= 1; + start_rtps; + wait_on_sig(rtps_done); + -- READER 2 + ind <= 2; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + + Log("Current Time: 5s", INFO); + check_time <= gen_duration(5 sec); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait_on_idle; + + AffirmIf(status_id,(status(0) and REQUESTED_DEADLINE_MISSED_STATUS) = REQUESTED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(1) and REQUESTED_DEADLINE_MISSED_STATUS) /= REQUESTED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(2) and REQUESTED_DEADLINE_MISSED_STATUS) /= REQUESTED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1"); + + Log("Current Time: 6s", INFO); + check_time <= gen_duration(6 sec); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait_on_idle; + + AffirmIf(status_id,(status(0) and REQUESTED_DEADLINE_MISSED_STATUS) = REQUESTED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(1) and REQUESTED_DEADLINE_MISSED_STATUS) = REQUESTED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(2) and REQUESTED_DEADLINE_MISSED_STATUS) = REQUESTED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0"); + + Log("R0: DDS Operation GET_REQUESTED_DEADLINE_MISSED_STATUS", INFO); + Log("R0: Expected: count 11, change 7, Instance 1", DEBUG); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := GET_REQUESTED_DEADLINE_MISSED_STATUS; + dds.ret_code := RETCODE_OK; + dds.count := 11; + dds.change := 7; + dds.inst := kh1; + -- READER 0 + ind <= 0; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + + AffirmIf(status_id,(status(0) and REQUESTED_DEADLINE_MISSED_STATUS) /= REQUESTED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(1) and REQUESTED_DEADLINE_MISSED_STATUS) = REQUESTED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(2) and REQUESTED_DEADLINE_MISSED_STATUS) = REQUESTED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0"); + + Log("R1: DDS Operation GET_REQUESTED_DEADLINE_MISSED_STATUS", INFO); + Log("R1: Expected: count 2, change 1", DEBUG); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := GET_REQUESTED_DEADLINE_MISSED_STATUS; + dds.ret_code := RETCODE_OK; + dds.count := 2; + dds.change := 1; + dds.inst := HANDLE_NIL; + -- READER 1 + ind <= 1; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + + AffirmIf(status_id,(status(0) and REQUESTED_DEADLINE_MISSED_STATUS) /= REQUESTED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(1) and REQUESTED_DEADLINE_MISSED_STATUS) /= REQUESTED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(2) and REQUESTED_DEADLINE_MISSED_STATUS) = REQUESTED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0"); + + Log("R2: DDS Operation GET_REQUESTED_DEADLINE_MISSED_STATUS", INFO); + Log("R2: Expected: count 3, change 2", DEBUG); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := GET_REQUESTED_DEADLINE_MISSED_STATUS; + dds.ret_code := RETCODE_OK; + dds.count := 4; + dds.change := 3; + dds.inst := kh1; + -- READER 2 + ind <= 2; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + + AffirmIf(status_id,(status(0) and REQUESTED_DEADLINE_MISSED_STATUS) /= REQUESTED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(1) and REQUESTED_DEADLINE_MISSED_STATUS) /= REQUESTED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(2) and REQUESTED_DEADLINE_MISSED_STATUS) /= REQUESTED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1"); + + wait_on_completion; + TranscriptOpen(RESULTS_FILE, APPEND_MODE); + SetTranscriptMirror; + ReportAlerts; + TranscriptClose; + std.env.stop; + wait; + end process; + + clock_prc : process + begin + clk <= '0'; + wait for 25 ns; + clk <= '1'; + wait for 25 ns; + end process; + + dds_prc : process(all) + variable col : COLLECTION_TYPE := DEFAULT_COLLECTION; + begin + if rising_edge(clk) then + dds_done <= '0'; + case (dds_stage ) is + when IDLE => + if (dds_start = '1') then + dds_stage <= START; + else + dds_done <= '1'; + end if; + when START => + if (ack_dds(ind) = '1') then + dds_stage <= DONE; + dds_cnt <= 0; + end if; + when DONE => + if (done_dds(ind) = '1') then + AffirmIfEqual(ret_id, return_code_dds(ind), dds.ret_code); + case (dds.ret_code) is + when RETCODE_OK => + case (dds.opcode) is + when GET_REQUESTED_DEADLINE_MISSED_STATUS => + dds_stage <= CHECK_DEADLINE; + dds_cnt <= 0; + when others => + gen_collection(mem(ind), col, dds, TEST_CONFIG(ind).PRESENTATION_QOS, TEST_CONFIG(ind).ORDERED_ACCESS); + dds_stage <= CHECK_SI; + dds_cnt <= 0; + end case; + when others => + dds_stage <= IDLE; + end case; + end if; + when CHECK_SI => + if (si_valid(ind) = '1') then + AffirmIfEqual(sstate_id, sample_info(ind).sample_state, col.s(dds_cnt).sstate); + AffirmIfEqual(vstate_id, sample_info(ind).view_state, col.s(dds_cnt).vstate); + AffirmIfEqual(istate_id, sample_info(ind).instance_state, col.s(dds_cnt).istate); + AffirmIfEqual(ts_id, to_unsigned(sample_info(ind).source_timestamp), to_unsigned(col.s(dds_cnt).ts)); + AffirmIfEqual(inst_id, to_unsigned(sample_info(ind).instance_handle), to_unsigned(col.s(dds_cnt).inst)); + AffirmIfEqual(pub_id, to_unsigned(sample_info(ind).publication_handle), to_unsigned(HANDLE_NIL)); + AffirmIfEqual(dis_gen_cnt_id, sample_info(ind).disposed_generation_count, std_logic_vector(to_unsigned(col.s(dds_cnt).dis_gen_cnt,WORD_WIDTH))); + AffirmIfEqual(no_w_gen_cnt_id, sample_info(ind).no_writers_generation_count, std_logic_vector(to_unsigned(col.s(dds_cnt).no_w_gen_cnt,WORD_WIDTH))); + AffirmIfEqual(srank_id, sample_info(ind).sample_rank, std_logic_vector(to_unsigned(col.s(dds_cnt).srank,WORD_WIDTH))); + AffirmIfEqual(grank_id, sample_info(ind).generation_rank, std_logic_vector(to_unsigned(col.s(dds_cnt).grank,WORD_WIDTH))); + AffirmIfEqual(agrank_id, sample_info(ind).absolute_generation_rank, std_logic_vector(to_unsigned(col.s(dds_cnt).agrank,WORD_WIDTH))); + if (sample_info(ind).valid_data = '1') then + AffirmIf(valid_id, col.s(dds_cnt).data /= EMPTY_TEST_PACKET, "Sample with Data not expected"); + dds_stage <= CHECK_DATA; + dds_cnt2 <= 0; + else + AffirmIf(valid_id, col.s(dds_cnt).data = EMPTY_TEST_PACKET, "Sample with Data expected"); + if (dds_cnt = col.len-1) then + -- DONE + dds_stage <= WAIT_EOC; + else + dds_cnt <= dds_cnt + 1; + end if; + end if; + end if; + AffirmIf(eoc_id, eoc(ind) = '0', "EOC pulled high"); + when CHECK_DATA => + if (valid_out_dds(ind) = '1') then + AffirmIfEqual(data_id, data_out_dds(ind), col.s(dds_cnt).data.data(dds_cnt2)); + dds_cnt2 <= dds_cnt2 + 1; + if (dds_cnt2 = col.s(dds_cnt).data.length-1) then + AlertIf(data_id, last_word_out_dds(ind) /= '1', "Last Word Signal not pulled High", ERROR); + if (dds_cnt = col.len-1) then + -- DONE + dds_stage <= WAIT_EOC; + else + dds_stage <= CHECK_SI; + dds_cnt <= dds_cnt + 1; + end if; + end if; + end if; + when WAIT_EOC => + if (eoc(ind) = '1') then + dds_stage <= IDLE; + end if; + when CHECK_DEADLINE => + if (valid_out_dds(ind) = '1') then + dds_cnt <= dds_cnt + 1; + case (dds_cnt) is + when 0 => + AffirmIfEqual(data_id, data_out_dds(ind), std_logic_vector(to_unsigned(dds.count,CDR_LONG_WIDTH))); + when 1 => + AffirmIfEqual(data_id, data_out_dds(ind), std_logic_vector(to_unsigned(dds.change,CDR_LONG_WIDTH))); + when 2 => + AffirmIfEqual(data_id, data_out_dds(ind), std_logic_vector(dds.inst(0))); + when 3 => + AffirmIfEqual(data_id, data_out_dds(ind), std_logic_vector(dds.inst(1))); + when 4 => + AffirmIfEqual(data_id, data_out_dds(ind), std_logic_vector(dds.inst(2))); + when 5 => + AffirmIfEqual(data_id, data_out_dds(ind), std_logic_vector(dds.inst(3))); + AlertIf(data_id, last_word_out_dds(ind) /= '1', "Last Word Signal not pulled High", ERROR); + dds_stage <= IDLE; + when others => + null; + end case; + end if; + end case; + end if; + + -- DEFAULT + start_dds <= (others => '0'); + opcode_dds <= (others => NOP); + instance_state_dds <= (others => ANY_INSTANCE_STATE); + view_state_dds <= (others => ANY_VIEW_STATE); + sample_state_dds <= (others => ANY_SAMPLE_STATE); + instance_handle_dds <= (others => HANDLE_NIL); + max_samples_dds <= (others => (others => '0')); + get_data_dds <= (others => '0'); + ready_out_dds <= (others => '0'); + + + case (dds_stage ) is + when START => + start_dds(ind) <= '1'; + opcode_dds(ind) <= dds.opcode; + instance_state_dds(ind) <= dds.istate; + view_state_dds(ind) <= dds.vstate; + sample_state_dds(ind) <= dds.sstate; + instance_handle_dds(ind) <= dds.inst; + max_samples_dds(ind) <= std_logic_vector(to_unsigned(dds.max_samples, WORD_WIDTH)); + when CHECK_SI => + if (si_valid(ind) = '1' and sample_info(ind).valid_data = '1') then + get_data_dds(ind) <= '1'; + end if; + when CHECK_DATA => + ready_out_dds(ind) <= '1'; + when CHECK_DEADLINE => + ready_out_dds(ind) <= '1'; + when others => + null; + end case; + end process; + + rtps_prc : process(all) + variable stimulus : TEST_PACKET_TYPE := EMPTY_TEST_PACKET; + begin + if rising_edge(clk) then + rtps_done <= '0'; + case (rtps_stage) is + when IDLE => + if (rtps_start = '1') then + rtps_stage <= START; + else + rtps_done <= '1'; + end if; + when START => + if (ack_rtps(ind) = '1') then + case (rtps.opcode) is + when ADD_CACHE_CHANGE => + gen_add_cache_change_dds(rtps.cc, rtps.lifespan, rtps.writer_pos, stimulus); + rtps_stage <= PUSH; + when others => + rtps_stage <= DONE; + end case; + end if; + when PUSH => + if (ready_in_rtps(ind) = '1') then + rtps_cnt <= rtps_cnt + 1; + if (rtps_cnt = stimulus.length-1) then + rtps_stage <= DONE; + end if; + end if; + when DONE => + if (done_rtps(ind) = '1') then + AffirmIfEqual(ret_id, HISTORY_CACHE_RESPONSE_TYPE'pos(ret_rtps(ind)), HISTORY_CACHE_RESPONSE_TYPE'pos(rtps.ret_code)); + rtps_stage <= IDLE; + end if; + end case; + end if; + + -- DEFAULT + start_rtps <= (others => '0'); + opcode_rtps <= (others => NOP); + valid_in_rtps <= (others => '0'); + last_word_in_rtps <= (others => '0'); + data_in_rtps <= (others => (others => '0')); + + case (rtps_stage) is + when START => + start_rtps(ind) <= '1'; + opcode_rtps(ind) <= rtps.opcode; + case (rtps.opcode) is + when REMOVE_WRITER => + data_in_rtps(ind) <= std_logic_vector(to_unsigned(rtps.writer_pos,WORD_WIDTH)); + when others => + null; + end case; + when PUSH => + valid_in_rtps(ind) <= '1'; + data_in_rtps(ind) <= stimulus.data(rtps_cnt); + last_word_in_rtps(ind) <= stimulus.last(rtps_cnt); + when others => + null; + end case; + end process; + + watchdog : process + begin + wait for 1 ms; + Alert("Test timeout", FAILURE); + std.env.stop; + end process; + +end architecture; \ No newline at end of file diff --git a/src/Tests/Level_0/L0_dds_reader_test4_arzkriu.vhd b/src/Tests/Level_0/L0_dds_reader_test4_arzkriu.vhd deleted file mode 100644 index 563116f..0000000 --- a/src/Tests/Level_0/L0_dds_reader_test4_arzkriu.vhd +++ /dev/null @@ -1,764 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library osvvm; -- Utility Library -context osvvm.OsvvmContext; - -use work.rtps_package.all; -use work.user_config.all; -use work.rtps_config_package.all; -use work.rtps_test_package.all; - --- This testbench tests the Deadline Handling of the DDS Reader, and more specifically the GET_REQUESTED_DEADLINE_MISSED_STATUS DDS Operation. - -entity L0_dds_reader_test4_arzkriu is -end entity; - - -architecture testbench of L0_dds_reader_test4_arzkriu is - - -- *CONSTANT DECLARATION* - constant MAX_REMOTE_ENDPOINTS : natural := 3; - - -- *TYPE DECLARATION* - type DDS_STAGE_TYPE is (IDLE, START, DONE, CHECK_SI, CHECK_DATA, WAIT_EOC, CHECK_DEADLINE); - type RTPS_STAGE_TYPE is (IDLE, START, PUSH, DONE); - - -- *SIGNAL DECLARATION* - signal clk : std_logic := '0'; - signal reset : std_logic := '1'; - signal check_time : TIME_TYPE := TIME_ZERO; - signal start_rtps, start_dds, ack_rtps, ack_dds, done_rtps, done_dds : std_logic := '0'; - signal opcode_rtps : HISTORY_CACHE_OPCODE_TYPE := NOP; - signal opcode_dds : DDS_READER_OPCODE_TYPE := NOP; - signal ret_rtps : HISTORY_CACHE_RESPONSE_TYPE := ERROR; - signal ready_in_rtps, valid_in_rtps, last_word_in_rtps : std_logic := '0'; - signal ready_out_dds, valid_out_dds, last_word_out_dds : std_logic := '0'; - signal data_in_rtps, data_out_dds : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); - signal get_data_dds, si_valid_data, si_valid, eoc : std_logic := '0'; - signal return_code_dds : std_logic_vector(RETURN_CODE_WIDTH-1 downto 0) := (others => '0'); - signal status : std_logic_vector(STATUS_KIND_WIDTH-1 downto 0) := (others => '0'); - signal instance_state_dds, si_instance_state : std_logic_vector(INSTANCE_STATE_KIND_WIDTH-1 downto 0) := ANY_INSTANCE_STATE; - signal view_state_dds, si_view_state : std_logic_vector(VIEW_STATE_KIND_WIDTH-1 downto 0) := ANY_VIEW_STATE; - signal sample_state_dds, si_sample_state : std_logic_vector(SAMPLE_STATE_KIND_WIDTH-1 downto 0) := ANY_SAMPLE_STATE; - signal instance_handle_dds, si_instance_handle : INSTANCE_HANDLE_TYPE := HANDLE_NIL; - signal max_samples_dds : std_logic_vector(MAX_SAMPLES_WIDTH-1 downto 0) := (others => '0'); - signal si_source_timestamp : TIME_TYPE := TIME_INVALID; - signal si_publication_handle : INSTANCE_HANDLE_TYPE := HANDLE_NIL; - signal si_disposed_generation_count : std_logic_vector(DISPOSED_GENERATION_COUNT_WIDTH-1 downto 0) := (others => '0'); - signal si_no_writers_generation_count : std_logic_vector(NO_WRITERS_GENERATION_COUNT_WIDTH-1 downto 0) := (others => '0'); - signal si_sample_rank : std_logic_vector(SAMPLE_RANK_WIDTH-1 downto 0) := (others => '0'); - signal si_generation_rank : std_logic_vector(GENERATION_RANK_WIDTH-1 downto 0) := (others => '0'); - signal si_absolute_generation_rank: std_logic_vector(ABSOLUTE_GENERATION_COUNT_WIDTH-1 downto 0) := (others => '0'); - - signal dds_start , dds_done , rtps_start, rtps_done : std_logic := '0'; - signal dds_cnt, dds_cnt2, rtps_cnt : natural := 0; - signal dds_stage : DDS_STAGE_TYPE := IDLE; - signal rtps_stage : RTPS_STAGE_TYPE := IDLE; - shared variable dds : DDS_READER_TEST_TYPE := DEFAULT_DDS_READER_TEST; - shared variable rtps : RTPS_READER_TEST_TYPE := DEFAULT_RTPS_READER_TEST; - shared variable mem : DDS_READER_MEM_TYPE := DEFAULT_DDS_READER_MEM; - signal data_id, ret_id, sstate_id, vstate_id, istate_id, inst_id, ts_id, pub_id, dis_gen_cnt_id, no_w_gen_cnt_id, srank_id, grank_id, agrank_id, eoc_id, valid_id, status_id : AlertLogIDType; - - -- *FUNCTION DECLARATION* - function extract_key_hash (payload : TEST_PACKET_TYPE) return INSTANCE_HANDLE_TYPE is - variable ret : INSTANCE_HANDLE_TYPE := HANDLE_NIL; - begin - for i in 0 to 3 loop - ret(i) := not payload.data(i); - end loop; - - return ret; - end function; - - function gen_sn(input : natural) return SEQUENCENUMBER_TYPE is - variable ret : SEQUENCENUMBER_TYPE; - begin - ret(0) := (others => '0'); - ret(1) := unsigned(int(input, WORD_WIDTH)); - return ret; - end function; - -begin - - -- Unit Under Test - uut : entity work.dds_reader(arch) - generic map ( - TIME_BASED_FILTER_QOS => DURATION_ZERO, - DEADLINE_QOS => gen_duration(1,0), - MAX_SAMPLES => std_logic_vector(to_unsigned(10,CDR_LONG_WIDTH)), - MAX_INSTANCES => std_logic_vector(to_unsigned(4,CDR_LONG_WIDTH)), - MAX_SAMPLES_PER_INSTANCE => std_logic_vector(to_unsigned(10,CDR_LONG_WIDTH)), - HISTORY_QOS => KEEP_ALL_HISTORY_QOS, - RELIABILITY_QOS => RELIABLE_RELIABILITY_QOS, - PRESENTATION_QOS => INSTANCE_PRESENTATION_QOS, - DESTINATION_ORDER_QOS => BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS, - COHERENT_ACCESS => FALSE, - ORDERED_ACCESS => FALSE, - WITH_KEY => TRUE, - PAYLOAD_FRAME_SIZE => 11, - MAX_REMOTE_ENDPOINTS => MAX_REMOTE_ENDPOINTS - ) - port map ( - clk => clk, - reset => reset, - time => check_time, - start_rtps => start_rtps, - opcode_rtps => opcode_rtps, - ack_rtps => ack_rtps, - done_rtps => done_rtps, - ret_rtps => ret_rtps, - data_in_rtps => data_in_rtps, - valid_in_rtps => valid_in_rtps, - ready_in_rtps => ready_in_rtps, - last_word_in_rtps => last_word_in_rtps, - start_dds => start_dds, - ack_dds => ack_dds, - opcode_dds => opcode_dds, - instance_state_dds => instance_state_dds, - view_state_dds => view_state_dds, - sample_state_dds => sample_state_dds, - instance_handle_dds => instance_handle_dds, - max_samples_dds => max_samples_dds, - get_data_dds => get_data_dds, - done_dds => done_dds, - return_code_dds => return_code_dds, - ready_out_dds => ready_out_dds, - valid_out_dds => valid_out_dds, - data_out_dds => data_out_dds, - last_word_out_dds => last_word_out_dds, - sample_info.sample_state => si_sample_state, - sample_info.view_state => si_view_state, - sample_info.instance_state => si_instance_state, - sample_info.source_timestamp => si_source_timestamp, - sample_info.instance_handle => si_instance_handle, - sample_info.publication_handle => si_publication_handle, - sample_info.disposed_generation_count => si_disposed_generation_count, - sample_info.no_writers_generation_count => si_no_writers_generation_count, - sample_info.sample_rank => si_sample_rank, - sample_info.generation_rank => si_generation_rank, - sample_info.absolute_generation_rank => si_absolute_generation_rank, - sample_info.valid_data => si_valid_data, - sample_info_valid => si_valid, - sample_info_ack => '1', - eoc => eoc, - status => status - ); - - stimulus_prc : process - variable RV : RandomPType; - variable cc : CACHE_CHANGE_TYPE := DEFAULT_CACHE_CHANGE; - variable s : SAMPLE_TYPE := DEFAULT_SAMPLE; - variable kh1, kh2, kh3, kh4, kh5 : INSTANCE_HANDLE_TYPE := HANDLE_NIL; - - alias idle_sig is <>; - - impure function gen_payload(key_hash : INSTANCE_HANDLE_TYPE; len : natural) return TEST_PACKET_TYPE is - variable ret : TEST_PACKET_TYPE := EMPTY_TEST_PACKET; - begin - assert (len >= 4) report "Payload length has to be at least 16 Bytes long" severity FAILURE; - - for i in 0 to len-1 loop - if (i < 4) then - -- NOTE: Beginning of payload is negated key to allow deterministic Key Hash generation from the kh_prc - ret.data(ret.length) := not key_hash(i); - else - ret.data(ret.length) := RV.RandSlv(WORD_WIDTH); - end if; - ret.length := ret.length + 1; - end loop; - ret.last(ret.length-1) := '1'; - - return ret; - end function; - - impure function gen_key_hash return KEY_HASH_TYPE is - variable ret : KEY_HASH_TYPE := KEY_HASH_NIL; - begin - for i in 0 to KEY_HASH_TYPE'length-1 loop - ret(i) := RV.RandSlv(WORD_WIDTH); - end loop; - return ret; - end function; - - procedure start_dds is - begin - dds_start <= '1'; - wait until rising_edge(clk); - dds_start <= '0'; - wait until rising_edge(clk); - end procedure; - - procedure start_rtps is - begin - rtps_start <= '1'; - wait until rising_edge(clk); - rtps_start <= '0'; - wait until rising_edge(clk); - end procedure; - - procedure wait_on_dds is - begin - if (dds_done /= '1') then - wait until dds_done = '1'; - end if; - end procedure; - - procedure wait_on_rtps is - begin - if (rtps_done /= '1') then - wait until rtps_done = '1'; - end if; - end procedure; - - procedure wait_on_completion is - begin - if (rtps_done /= '1' or dds_done /= '1') then - wait until rtps_done = '1' and dds_done = '1'; - end if; - end procedure; - - -- NOTE: This procedure waits until the idle_sig is high for at least - -- two consecutive clock cycles. - procedure wait_on_idle is - variable first : boolean := TRUE; - begin - loop - if (idle_sig /= '1') then - wait until idle_sig = '1'; - elsif (not first) then - exit; - end if; - wait until rising_edge(clk); - wait until rising_edge(clk); - first := FALSE; - end loop; - end procedure; - - begin - - SetAlertLogName("L0_dds_reader_test4_arzkriu - (KEEP ALL, Reliable, Zero TIME_BASED_FILTER, Keyed, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER, ACCESS SCOPE Instance, Unordered) - Deadline Handling"); - SetAlertEnable(FAILURE, TRUE); - SetAlertEnable(ERROR, TRUE); - SetAlertEnable(WARNING, TRUE); - SetLogEnable(DEBUG, FALSE); - SetLogEnable(PASSED, FALSE); - SetLogEnable(INFO, TRUE); - RV.InitSeed(RV'instance_name); - sstate_id <= GetAlertLogID("Sample State", ALERTLOG_BASE_ID); - vstate_id <= GetAlertLogID("View State", ALERTLOG_BASE_ID); - istate_id <= GetAlertLogID("Instance State", ALERTLOG_BASE_ID); - ts_id <= GetAlertLogID("Source Timestamp", ALERTLOG_BASE_ID); - inst_id <= GetAlertLogID("Instance Handle", ALERTLOG_BASE_ID); - pub_id <= GetAlertLogID("Publication Hanlde", ALERTLOG_BASE_ID); - dis_gen_cnt_id <= GetAlertLogID("Disposed Generation Count", ALERTLOG_BASE_ID); - no_w_gen_cnt_id <= GetAlertLogID("No Writers Generation Count", ALERTLOG_BASE_ID); - srank_id <= GetAlertLogID("Sample Rank", ALERTLOG_BASE_ID); - grank_id <= GetAlertLogID("Generation Rank", ALERTLOG_BASE_ID); - agrank_id <= GetAlertLogID("Absolute Generation Rank", ALERTLOG_BASE_ID); - eoc_id <= GetAlertLogID("End of Collection", ALERTLOG_BASE_ID); - valid_id <= GetAlertLogID("Valid Data", ALERTLOG_BASE_ID); - data_id <= GetAlertLogID("Data Out", ALERTLOG_BASE_ID); - ret_id <= GetAlertLogID("Return Code", ALERTLOG_BASE_ID); - status_id <= GetAlertLogID("Communication Status", ALERTLOG_BASE_ID); - - -- Key Hashes - kh1 := (x"F12C31DA", x"E3FE0F3F", x"01F36685", x"446518CA"); - kh2 := (x"BC070AC4", x"0BAB5811", x"14EA8D61", x"F669189B"); - kh3 := (x"0CEAB0C6", x"FA04B9AD", x"A96EB495", x"4E0EB999"); - kh4 := (x"A7EB605C", x"FF4BEF3A", x"3C5E8724", x"CCA0CA67"); - - - - Log("Initiating Test", INFO); - Log("Current Time: 0s", INFO); - check_time <= TIME_ZERO; - reset <= '1'; - wait until rising_edge(clk); - wait until rising_edge(clk); - reset <= '0'; - wait_on_idle; - -- MEM: 0, 0, 0, 0 - -- ISTATE: - - -- WRITER: - - - AffirmIf(status_id,(status and REQUESTED_DEADLINE_MISSED_STATUS) /= REQUESTED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1"); - - Log("Current Time: 1s", INFO); - check_time <= gen_duration(1,0); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait_on_idle; - - AffirmIf(status_id,(status and REQUESTED_DEADLINE_MISSED_STATUS) /= REQUESTED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh1; - cc.payload := gen_payload(kh1,10); - cc.src_timestamp := gen_duration(1,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Aligned Payload] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - rtps.ret_code := OK; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S1 - -- ISTATE: I1:ALIVE - -- WRITER: W0:I1 - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh2; - cc.payload := gen_payload(kh2,10); - cc.src_timestamp := gen_duration(2,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 2, Writer 1, Aligned Payload] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 1; - rtps.ret_code := OK; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S1, I2S1 - -- ISTATE: I1:ALIVE, I2:ALIVE - -- WRITER: W0:I1, W1:I2 - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh4; - cc.payload := gen_payload(kh4,10); - cc.src_timestamp := gen_duration(3,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 4, Writer 0, Aligned Payload] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - rtps.ret_code := OK; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S1, I2S1, I4S1 - -- ISTATE: I1:ALIVE, I2:ALIVE, I4:ALIVE - -- WRITER: W0:I1,I4, W1:I2 - - Log("Current Time: 2s", INFO); - check_time <= gen_duration(2,0); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait_on_idle; - - AffirmIf(status_id,(status and REQUESTED_DEADLINE_MISSED_STATUS) /= REQUESTED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh1; - cc.payload := gen_payload(kh1,10); - cc.src_timestamp := gen_duration(4,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Aligned Payload] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - rtps.ret_code := OK; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S1, I2S1, I4S1, I1S2 - -- ISTATE: I1:ALIVE, I2:ALIVE, I4:ALIVE - -- WRITER: W0:I1,I4, W1:I2 - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh4; - cc.payload := gen_payload(kh4,10); - cc.src_timestamp := gen_duration(5,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 1, Aligned Payload] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 1; - rtps.ret_code := OK; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S1, I2S1, I4S1, I1S2, I4S2 - -- ISTATE: I1:ALIVE, I2:ALIVE, I4:ALIVE - -- WRITER: W0:I1,I4, W1:I2,I4 - - Log("Current Time: 3s", INFO); - check_time <= gen_duration(3,0); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait_on_idle; - - AffirmIf(status_id,(status and REQUESTED_DEADLINE_MISSED_STATUS) = REQUESTED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0"); - - Log("DDS Operation GET_REQUESTED_DEADLINE_MISSED_STATUS (Expected: count 1, change 1, Instance 2)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := GET_REQUESTED_DEADLINE_MISSED_STATUS; - dds.ret_code := RETCODE_OK; - dds.count := 1; - dds.change := 1; - dds.inst := kh2; - start_dds; - wait_on_dds; - wait_on_idle; - - AffirmIf(status_id,(status and REQUESTED_DEADLINE_MISSED_STATUS) /= REQUESTED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh3; - cc.payload := gen_payload(kh3,10); - cc.src_timestamp := gen_duration(6,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 3, Writer 2, Aligned Payload] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 2; - rtps.ret_code := OK; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S1, I2S1, I4S1, I1S2, I4S2, I3S1 - -- ISTATE: I1:ALIVE, I2:ALIVE, I3:ALIVE, I4:ALIVE - -- WRITER: W0:I1,I4, W1:I2,I4, W2:I3 - - Log("Current Time: 4s", INFO); - check_time <= gen_duration(4,0); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait_on_idle; - - AffirmIf(status_id,(status and REQUESTED_DEADLINE_MISSED_STATUS) = REQUESTED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0"); - - Log("DDS Operation GET_REQUESTED_DEADLINE_MISSED_STATUS (Expected: count 4, change 3, Instance 1)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := GET_REQUESTED_DEADLINE_MISSED_STATUS; - dds.ret_code := RETCODE_OK; - dds.count := 4; - dds.change := 3; - dds.inst := kh1; - start_dds; - wait_on_dds; - wait_on_idle; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh4; - cc.payload := gen_payload(kh4,10); - cc.src_timestamp := gen_duration(7,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 4, Writer 2, Aligned Payload] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 2; - rtps.ret_code := OK; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S1, I2S1, I4S1, I1S2, I4S2, I3S1, I4S3 - -- ISTATE: I1:ALIVE, I2:ALIVE, I3:ALIVE, I4:ALIVE - -- WRITER: W0:I1,I4, W1:I2,I4, W2:I3,I4 - - AffirmIf(status_id,(status and REQUESTED_DEADLINE_MISSED_STATUS) /= REQUESTED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1"); - - Log("Current Time: 5s", INFO); - check_time <= gen_duration(5,0); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait_on_idle; - - AffirmIf(status_id,(status and REQUESTED_DEADLINE_MISSED_STATUS) = REQUESTED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0"); - - Log("Current Time: 6s", INFO); - check_time <= gen_duration(6,0); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait_on_idle; - - AffirmIf(status_id,(status and REQUESTED_DEADLINE_MISSED_STATUS) = REQUESTED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0"); - - Log("DDS Operation GET_REQUESTED_DEADLINE_MISSED_STATUS (Expected: count 11, change 7, Instance 1)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := GET_REQUESTED_DEADLINE_MISSED_STATUS; - dds.ret_code := RETCODE_OK; - dds.count := 11; - dds.change := 7; - dds.inst := kh1; - start_dds; - wait_on_dds; - wait_on_idle; - - AffirmIf(status_id,(status and REQUESTED_DEADLINE_MISSED_STATUS) /= REQUESTED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1"); - - wait_on_completion; - TranscriptOpen(RESULTS_FILE, APPEND_MODE); - SetTranscriptMirror; - ReportAlerts; - TranscriptClose; - std.env.stop; - wait; - end process; - - clock_prc : process - begin - clk <= '0'; - wait for 25 ns; - clk <= '1'; - wait for 25 ns; - end process; - - alert_prc : process(all) - begin - if rising_edge(clk) then - -- TODO - end if; - end process; - - dds_prc : process(all) - variable col : COLLECTION_TYPE := DEFAULT_COLLECTION; - begin - if rising_edge(clk) then - dds_done <= '0'; - case (dds_stage ) is - when IDLE => - if (dds_start = '1') then - dds_stage <= START; - else - dds_done <= '1'; - end if; - when START => - if (ack_dds = '1') then - dds_stage <= DONE; - dds_cnt <= 0; - end if; - when DONE => - if (done_dds = '1') then - AffirmIfEqual(ret_id, return_code_dds, dds.ret_code); - case (dds.ret_code) is - when RETCODE_OK => - case (dds.opcode) is - when GET_REQUESTED_DEADLINE_MISSED_STATUS => - dds_stage <= CHECK_DEADLINE; - dds_cnt <= 0; - when others => - gen_collection(mem, col, dds, INSTANCE_PRESENTATION_QOS, FALSE); - dds_stage <= CHECK_SI; - dds_cnt <= 0; - end case; - when others => - dds_stage <= IDLE; - end case; - end if; - when CHECK_SI => - if (si_valid = '1') then - AffirmIfEqual(sstate_id, si_sample_state, col.s(dds_cnt).sstate); - AffirmIfEqual(vstate_id, si_view_state, col.s(dds_cnt).vstate); - AffirmIfEqual(istate_id, si_instance_state, col.s(dds_cnt).istate); - AffirmIfEqual(ts_id, to_unsigned(si_source_timestamp), to_unsigned(col.s(dds_cnt).ts)); - AffirmIfEqual(inst_id, to_unsigned(si_instance_handle), to_unsigned(col.s(dds_cnt).inst)); - AffirmIfEqual(pub_id, to_unsigned(si_publication_handle), to_unsigned(HANDLE_NIL)); - AffirmIfEqual(dis_gen_cnt_id, si_disposed_generation_count, std_logic_vector(to_unsigned(col.s(dds_cnt).dis_gen_cnt,WORD_WIDTH))); - AffirmIfEqual(no_w_gen_cnt_id, si_no_writers_generation_count, std_logic_vector(to_unsigned(col.s(dds_cnt).no_w_gen_cnt,WORD_WIDTH))); - AffirmIfEqual(srank_id, si_sample_rank, std_logic_vector(to_unsigned(col.s(dds_cnt).srank,WORD_WIDTH))); - AffirmIfEqual(grank_id, si_generation_rank, std_logic_vector(to_unsigned(col.s(dds_cnt).grank,WORD_WIDTH))); - AffirmIfEqual(agrank_id, si_absolute_generation_rank, std_logic_vector(to_unsigned(col.s(dds_cnt).agrank,WORD_WIDTH))); - if (si_valid_data = '1') then - AffirmIf(valid_id, col.s(dds_cnt).data /= EMPTY_TEST_PACKET, "Sample with Data not expected"); - dds_stage <= CHECK_DATA; - dds_cnt2 <= 0; - else - AffirmIf(valid_id, col.s(dds_cnt).data = EMPTY_TEST_PACKET, "Sample with Data expected"); - if (dds_cnt = col.len-1) then - -- DONE - dds_stage <= WAIT_EOC; - else - dds_cnt <= dds_cnt + 1; - end if; - end if; - end if; - AffirmIf(eoc_id, eoc = '0', "EOC pulled high"); - when CHECK_DATA => - if (valid_out_dds = '1') then - AffirmIfEqual(data_id, data_out_dds, col.s(dds_cnt).data.data(dds_cnt2)); - dds_cnt2 <= dds_cnt2 + 1; - if (dds_cnt2 = col.s(dds_cnt).data.length-1) then - AlertIf(data_id, last_word_out_dds /= '1', "Last Word Signal not pulled High", ERROR); - if (dds_cnt = col.len-1) then - -- DONE - dds_stage <= WAIT_EOC; - else - dds_stage <= CHECK_SI; - dds_cnt <= dds_cnt + 1; - end if; - end if; - end if; - when WAIT_EOC => - if (eoc = '1') then - dds_stage <= IDLE; - end if; - when CHECK_DEADLINE => - if (valid_out_dds = '1') then - dds_cnt <= dds_cnt + 1; - case (dds_cnt) is - when 0 => - AffirmIfEqual(data_id, data_out_dds, std_logic_vector(to_unsigned(dds.count,CDR_LONG_WIDTH))); - when 1 => - AffirmIfEqual(data_id, data_out_dds, std_logic_vector(to_unsigned(dds.change,CDR_LONG_WIDTH))); - when 2 => - AffirmIfEqual(data_id, data_out_dds, std_logic_vector(dds.inst(0))); - when 3 => - AffirmIfEqual(data_id, data_out_dds, std_logic_vector(dds.inst(1))); - when 4 => - AffirmIfEqual(data_id, data_out_dds, std_logic_vector(dds.inst(2))); - when 5 => - AffirmIfEqual(data_id, data_out_dds, std_logic_vector(dds.inst(3))); - AlertIf(data_id, last_word_out_dds /= '1', "Last Word Signal not pulled High", ERROR); - dds_stage <= IDLE; - when others => - null; - end case; - end if; - end case; - end if; - - -- DEFAULT - start_dds <= '0'; - opcode_dds <= NOP; - instance_state_dds <= ANY_INSTANCE_STATE; - view_state_dds <= ANY_VIEW_STATE; - sample_state_dds <= ANY_SAMPLE_STATE; - instance_handle_dds <= HANDLE_NIL; - max_samples_dds <= (others => '0'); - get_data_dds <= '0'; - ready_out_dds <= '0'; - - - case (dds_stage ) is - when START => - start_dds <= '1'; - opcode_dds <= dds.opcode; - instance_state_dds <= dds.istate; - view_state_dds <= dds.vstate; - sample_state_dds <= dds.sstate; - instance_handle_dds <= dds.inst; - max_samples_dds <= std_logic_vector(to_unsigned(dds.max_samples, WORD_WIDTH)); - when CHECK_SI => - if (si_valid = '1' and si_valid_data = '1') then - get_data_dds <= '1'; - end if; - when CHECK_DATA => - ready_out_dds <= '1'; - when CHECK_DEADLINE => - ready_out_dds <= '1'; - when others => - null; - end case; - end process; - - rtps_prc : process(all) - variable stimulus : TEST_PACKET_TYPE := EMPTY_TEST_PACKET; - begin - if rising_edge(clk) then - rtps_done <= '0'; - case (rtps_stage) is - when IDLE => - if (rtps_start = '1') then - rtps_stage <= START; - else - rtps_done <= '1'; - end if; - when START => - if (ack_rtps = '1') then - case (rtps.opcode) is - when ADD_CACHE_CHANGE => - gen_add_cache_change_dds(rtps.cc, rtps.lifespan, rtps.writer_pos, stimulus); - rtps_stage <= PUSH; - when others => - rtps_stage <= DONE; - end case; - end if; - when PUSH => - if (ready_in_rtps = '1') then - rtps_cnt <= rtps_cnt + 1; - if (rtps_cnt = stimulus.length-1) then - rtps_stage <= DONE; - end if; - end if; - when DONE => - if (done_rtps = '1') then - AffirmIfEqual(ret_id, HISTORY_CACHE_RESPONSE_TYPE'pos(ret_rtps), HISTORY_CACHE_RESPONSE_TYPE'pos(rtps.ret_code)); - rtps_stage <= IDLE; - end if; - end case; - end if; - - -- DEFAULT - start_rtps <= '0'; - opcode_rtps <= NOP; - valid_in_rtps <= '0'; - last_word_in_rtps <= '0'; - data_in_rtps <= (others => '0'); - - case (rtps_stage) is - when START => - start_rtps <= '1'; - opcode_rtps <= rtps.opcode; - case (rtps.opcode) is - when REMOVE_WRITER => - data_in_rtps <= std_logic_vector(to_unsigned(rtps.writer_pos,WORD_WIDTH)); - when others => - null; - end case; - when PUSH => - valid_in_rtps <= '1'; - data_in_rtps <= stimulus.data(rtps_cnt); - last_word_in_rtps <= stimulus.last(rtps_cnt); - when others => - null; - end case; - end process; - - watchdog : process - begin - wait for 1 ms; - Alert("Test timeout", FAILURE); - std.env.stop; - end process; - -end architecture; \ No newline at end of file diff --git a/src/Tests/Level_0/L0_dds_reader_test4_arznriu.vhd b/src/Tests/Level_0/L0_dds_reader_test4_arznriu.vhd deleted file mode 100644 index 71013c0..0000000 --- a/src/Tests/Level_0/L0_dds_reader_test4_arznriu.vhd +++ /dev/null @@ -1,633 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library osvvm; -- Utility Library -context osvvm.OsvvmContext; - -use work.rtps_package.all; -use work.user_config.all; -use work.rtps_config_package.all; -use work.rtps_test_package.all; - --- This testbench tests the Deadline Handling of the DDS Reader, and more specifically the GET_REQUESTED_DEADLINE_MISSED_STATUS DDS Operation. - -entity L0_dds_reader_test4_arznriu is -end entity; - - -architecture testbench of L0_dds_reader_test4_arznriu is - - -- *CONSTANT DECLARATION* - constant MAX_REMOTE_ENDPOINTS : natural := 3; - - -- *TYPE DECLARATION* - type DDS_STAGE_TYPE is (IDLE, START, DONE, CHECK_SI, CHECK_DATA, WAIT_EOC, CHECK_DEADLINE); - type RTPS_STAGE_TYPE is (IDLE, START, PUSH, DONE); - - -- *SIGNAL DECLARATION* - signal clk : std_logic := '0'; - signal reset : std_logic := '1'; - signal check_time : TIME_TYPE := TIME_ZERO; - signal start_rtps, start_dds, ack_rtps, ack_dds, done_rtps, done_dds : std_logic := '0'; - signal opcode_rtps : HISTORY_CACHE_OPCODE_TYPE := NOP; - signal opcode_dds : DDS_READER_OPCODE_TYPE := NOP; - signal ret_rtps : HISTORY_CACHE_RESPONSE_TYPE := ERROR; - signal ready_in_rtps, valid_in_rtps, last_word_in_rtps : std_logic := '0'; - signal ready_out_dds, valid_out_dds, last_word_out_dds : std_logic := '0'; - signal data_in_rtps, data_out_dds : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); - signal get_data_dds, si_valid_data, si_valid, eoc : std_logic := '0'; - signal return_code_dds : std_logic_vector(RETURN_CODE_WIDTH-1 downto 0) := (others => '0'); - signal status : std_logic_vector(STATUS_KIND_WIDTH-1 downto 0) := (others => '0'); - signal instance_state_dds, si_instance_state : std_logic_vector(INSTANCE_STATE_KIND_WIDTH-1 downto 0) := ANY_INSTANCE_STATE; - signal view_state_dds, si_view_state : std_logic_vector(VIEW_STATE_KIND_WIDTH-1 downto 0) := ANY_VIEW_STATE; - signal sample_state_dds, si_sample_state : std_logic_vector(SAMPLE_STATE_KIND_WIDTH-1 downto 0) := ANY_SAMPLE_STATE; - signal instance_handle_dds, si_instance_handle : INSTANCE_HANDLE_TYPE := HANDLE_NIL; - signal max_samples_dds : std_logic_vector(MAX_SAMPLES_WIDTH-1 downto 0) := (others => '0'); - signal si_source_timestamp : TIME_TYPE := TIME_INVALID; - signal si_publication_handle : INSTANCE_HANDLE_TYPE := HANDLE_NIL; - signal si_disposed_generation_count : std_logic_vector(DISPOSED_GENERATION_COUNT_WIDTH-1 downto 0) := (others => '0'); - signal si_no_writers_generation_count : std_logic_vector(NO_WRITERS_GENERATION_COUNT_WIDTH-1 downto 0) := (others => '0'); - signal si_sample_rank : std_logic_vector(SAMPLE_RANK_WIDTH-1 downto 0) := (others => '0'); - signal si_generation_rank : std_logic_vector(GENERATION_RANK_WIDTH-1 downto 0) := (others => '0'); - signal si_absolute_generation_rank: std_logic_vector(ABSOLUTE_GENERATION_COUNT_WIDTH-1 downto 0) := (others => '0'); - - signal dds_start , dds_done , rtps_start, rtps_done : std_logic := '0'; - signal dds_cnt, dds_cnt2, rtps_cnt : natural := 0; - signal dds_stage : DDS_STAGE_TYPE := IDLE; - signal rtps_stage : RTPS_STAGE_TYPE := IDLE; - shared variable dds : DDS_READER_TEST_TYPE := DEFAULT_DDS_READER_TEST; - shared variable rtps : RTPS_READER_TEST_TYPE := DEFAULT_RTPS_READER_TEST; - shared variable mem : DDS_READER_MEM_TYPE := DEFAULT_DDS_READER_MEM; - signal data_id, ret_id, sstate_id, vstate_id, istate_id, inst_id, ts_id, pub_id, dis_gen_cnt_id, no_w_gen_cnt_id, srank_id, grank_id, agrank_id, eoc_id, valid_id, status_id : AlertLogIDType; - - -- *FUNCTION DECLARATION* - function extract_key_hash (payload : TEST_PACKET_TYPE) return INSTANCE_HANDLE_TYPE is - variable ret : INSTANCE_HANDLE_TYPE := HANDLE_NIL; - begin - for i in 0 to 3 loop - ret(i) := not payload.data(i); - end loop; - - return ret; - end function; - - function gen_sn(input : natural) return SEQUENCENUMBER_TYPE is - variable ret : SEQUENCENUMBER_TYPE; - begin - ret(0) := (others => '0'); - ret(1) := unsigned(int(input, WORD_WIDTH)); - return ret; - end function; - -begin - - -- Unit Under Test - uut : entity work.dds_reader(arch) - generic map ( - TIME_BASED_FILTER_QOS => DURATION_ZERO, - DEADLINE_QOS => gen_duration(1,0), - MAX_SAMPLES => std_logic_vector(to_unsigned(10,CDR_LONG_WIDTH)), - MAX_INSTANCES => std_logic_vector(to_unsigned(4,CDR_LONG_WIDTH)), - MAX_SAMPLES_PER_INSTANCE => std_logic_vector(to_unsigned(10,CDR_LONG_WIDTH)), - HISTORY_QOS => KEEP_ALL_HISTORY_QOS, - RELIABILITY_QOS => RELIABLE_RELIABILITY_QOS, - PRESENTATION_QOS => INSTANCE_PRESENTATION_QOS, - DESTINATION_ORDER_QOS => BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS, - COHERENT_ACCESS => FALSE, - ORDERED_ACCESS => FALSE, - WITH_KEY => FALSE, - PAYLOAD_FRAME_SIZE => 11, - MAX_REMOTE_ENDPOINTS => MAX_REMOTE_ENDPOINTS - ) - port map ( - clk => clk, - reset => reset, - time => check_time, - start_rtps => start_rtps, - opcode_rtps => opcode_rtps, - ack_rtps => ack_rtps, - done_rtps => done_rtps, - ret_rtps => ret_rtps, - data_in_rtps => data_in_rtps, - valid_in_rtps => valid_in_rtps, - ready_in_rtps => ready_in_rtps, - last_word_in_rtps => last_word_in_rtps, - start_dds => start_dds, - ack_dds => ack_dds, - opcode_dds => opcode_dds, - instance_state_dds => instance_state_dds, - view_state_dds => view_state_dds, - sample_state_dds => sample_state_dds, - instance_handle_dds => instance_handle_dds, - max_samples_dds => max_samples_dds, - get_data_dds => get_data_dds, - done_dds => done_dds, - return_code_dds => return_code_dds, - ready_out_dds => ready_out_dds, - valid_out_dds => valid_out_dds, - data_out_dds => data_out_dds, - last_word_out_dds => last_word_out_dds, - sample_info.sample_state => si_sample_state, - sample_info.view_state => si_view_state, - sample_info.instance_state => si_instance_state, - sample_info.source_timestamp => si_source_timestamp, - sample_info.instance_handle => si_instance_handle, - sample_info.publication_handle => si_publication_handle, - sample_info.disposed_generation_count => si_disposed_generation_count, - sample_info.no_writers_generation_count => si_no_writers_generation_count, - sample_info.sample_rank => si_sample_rank, - sample_info.generation_rank => si_generation_rank, - sample_info.absolute_generation_rank => si_absolute_generation_rank, - sample_info.valid_data => si_valid_data, - sample_info_valid => si_valid, - sample_info_ack => '1', - eoc => eoc, - status => status - ); - - stimulus_prc : process - variable RV : RandomPType; - variable cc : CACHE_CHANGE_TYPE := DEFAULT_CACHE_CHANGE; - variable s : SAMPLE_TYPE := DEFAULT_SAMPLE; - variable kh1, kh2, kh3, kh4, kh5 : INSTANCE_HANDLE_TYPE := HANDLE_NIL; - - alias idle_sig is <>; - - impure function gen_payload(key_hash : INSTANCE_HANDLE_TYPE; len : natural) return TEST_PACKET_TYPE is - variable ret : TEST_PACKET_TYPE := EMPTY_TEST_PACKET; - begin - assert (len >= 4) report "Payload length has to be at least 16 Bytes long" severity FAILURE; - - for i in 0 to len-1 loop - if (i < 4) then - -- NOTE: Beginning of payload is negated key to allow deterministic Key Hash generation from the kh_prc - ret.data(ret.length) := not key_hash(i); - else - ret.data(ret.length) := RV.RandSlv(WORD_WIDTH); - end if; - ret.length := ret.length + 1; - end loop; - ret.last(ret.length-1) := '1'; - - return ret; - end function; - - impure function gen_key_hash return KEY_HASH_TYPE is - variable ret : KEY_HASH_TYPE := KEY_HASH_NIL; - begin - for i in 0 to KEY_HASH_TYPE'length-1 loop - ret(i) := RV.RandSlv(WORD_WIDTH); - end loop; - return ret; - end function; - - procedure start_dds is - begin - dds_start <= '1'; - wait until rising_edge(clk); - dds_start <= '0'; - wait until rising_edge(clk); - end procedure; - - procedure start_rtps is - begin - rtps_start <= '1'; - wait until rising_edge(clk); - rtps_start <= '0'; - wait until rising_edge(clk); - end procedure; - - procedure wait_on_dds is - begin - if (dds_done /= '1') then - wait until dds_done = '1'; - end if; - end procedure; - - procedure wait_on_rtps is - begin - if (rtps_done /= '1') then - wait until rtps_done = '1'; - end if; - end procedure; - - procedure wait_on_completion is - begin - if (rtps_done /= '1' or dds_done /= '1') then - wait until rtps_done = '1' and dds_done = '1'; - end if; - end procedure; - - -- NOTE: This procedure waits until the idle_sig is high for at least - -- two consecutive clock cycles. - procedure wait_on_idle is - variable first : boolean := TRUE; - begin - loop - if (idle_sig /= '1') then - wait until idle_sig = '1'; - elsif (not first) then - exit; - end if; - wait until rising_edge(clk); - wait until rising_edge(clk); - first := FALSE; - end loop; - end procedure; - - begin - - SetAlertLogName("L0_dds_reader_test4_arznriu - (KEEP ALL, Reliable, Zero TIME_BASED_FILTER, Keyless, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER, ACCESS SCOPE Instance, Unordered) - Deadline Handling"); - SetAlertEnable(FAILURE, TRUE); - SetAlertEnable(ERROR, TRUE); - SetAlertEnable(WARNING, TRUE); - SetLogEnable(DEBUG, FALSE); - SetLogEnable(PASSED, FALSE); - SetLogEnable(INFO, TRUE); - RV.InitSeed(RV'instance_name); - sstate_id <= GetAlertLogID("Sample State", ALERTLOG_BASE_ID); - vstate_id <= GetAlertLogID("View State", ALERTLOG_BASE_ID); - istate_id <= GetAlertLogID("Instance State", ALERTLOG_BASE_ID); - ts_id <= GetAlertLogID("Source Timestamp", ALERTLOG_BASE_ID); - inst_id <= GetAlertLogID("Instance Handle", ALERTLOG_BASE_ID); - pub_id <= GetAlertLogID("Publication Hanlde", ALERTLOG_BASE_ID); - dis_gen_cnt_id <= GetAlertLogID("Disposed Generation Count", ALERTLOG_BASE_ID); - no_w_gen_cnt_id <= GetAlertLogID("No Writers Generation Count", ALERTLOG_BASE_ID); - srank_id <= GetAlertLogID("Sample Rank", ALERTLOG_BASE_ID); - grank_id <= GetAlertLogID("Generation Rank", ALERTLOG_BASE_ID); - agrank_id <= GetAlertLogID("Absolute Generation Rank", ALERTLOG_BASE_ID); - eoc_id <= GetAlertLogID("End of Collection", ALERTLOG_BASE_ID); - valid_id <= GetAlertLogID("Valid Data", ALERTLOG_BASE_ID); - data_id <= GetAlertLogID("Data Out", ALERTLOG_BASE_ID); - ret_id <= GetAlertLogID("Return Code", ALERTLOG_BASE_ID); - status_id <= GetAlertLogID("Communication Status", ALERTLOG_BASE_ID); - - -- Key Hashes - kh1 := (x"F12C31DA", x"E3FE0F3F", x"01F36685", x"446518CA"); - kh2 := (x"BC070AC4", x"0BAB5811", x"14EA8D61", x"F669189B"); - kh3 := (x"0CEAB0C6", x"FA04B9AD", x"A96EB495", x"4E0EB999"); - kh4 := (x"A7EB605C", x"FF4BEF3A", x"3C5E8724", x"CCA0CA67"); - - - - Log("Initiating Test", INFO); - Log("Current Time: 0s", INFO); - check_time <= TIME_ZERO; - reset <= '1'; - wait until rising_edge(clk); - wait until rising_edge(clk); - reset <= '0'; - wait_on_idle; - -- MEM: - - -- ISTATE: - - -- WRITER: - - - AffirmIf(status_id,(status and REQUESTED_DEADLINE_MISSED_STATUS) /= REQUESTED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1"); - - Log("Current Time: 1s", INFO); - check_time <= gen_duration(1,0); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait_on_idle; - - AffirmIf(status_id,(status and REQUESTED_DEADLINE_MISSED_STATUS) = REQUESTED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0"); - - Log("DDS Operation GET_REQUESTED_DEADLINE_MISSED_STATUS (Expected: count 1, change 1)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := GET_REQUESTED_DEADLINE_MISSED_STATUS; - dds.ret_code := RETCODE_OK; - dds.count := 1; - dds.change := 1; - dds.inst := HANDLE_NIL; - start_dds; - wait_on_dds; - wait_on_idle; - - AffirmIf(status_id,(status and REQUESTED_DEADLINE_MISSED_STATUS) /= REQUESTED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := HANDLE_NIL; - cc.payload := gen_payload(KEY_HASH_NIL,10); - cc.src_timestamp := gen_duration(1,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Writer 0, Aligned Payload] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 0; - rtps.ret_code := OK; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: S1 - -- ISTATE: ALIVE - -- WRITER: W0 - - Log("Current Time: 2s", INFO); - check_time <= gen_duration(2,0); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait_on_idle; - - AffirmIf(status_id,(status and REQUESTED_DEADLINE_MISSED_STATUS) /= REQUESTED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1"); - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := HANDLE_NIL; - cc.payload := gen_payload(KEY_HASH_NIL,10); - cc.src_timestamp := gen_duration(2,0); - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Writer 1, Aligned Payload] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 1; - rtps.ret_code := OK; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); - start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: S1, S2 - -- ISTATE: ALIVE - -- WRITER: W0, W1 - - Log("Current Time: 3s", INFO); - check_time <= gen_duration(3,0); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait_on_idle; - - AffirmIf(status_id,(status and REQUESTED_DEADLINE_MISSED_STATUS) /= REQUESTED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1"); - - Log("Current Time: 4s", INFO); - check_time <= gen_duration(4,0); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait_on_idle; - - AffirmIf(status_id,(status and REQUESTED_DEADLINE_MISSED_STATUS) = REQUESTED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0"); - - Log("Current Time: 5s", INFO); - check_time <= gen_duration(5,0); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait_on_idle; - - AffirmIf(status_id,(status and REQUESTED_DEADLINE_MISSED_STATUS) = REQUESTED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0"); - - Log("DDS Operation GET_REQUESTED_DEADLINE_MISSED_STATUS (Expected: count 3, change 2)", INFO); - dds := DEFAULT_DDS_READER_TEST; - dds.opcode := GET_REQUESTED_DEADLINE_MISSED_STATUS; - dds.ret_code := RETCODE_OK; - dds.count := 3; - dds.change := 2; - dds.inst := HANDLE_NIL; - start_dds; - wait_on_dds; - wait_on_idle; - - AffirmIf(status_id,(status and REQUESTED_DEADLINE_MISSED_STATUS) /= REQUESTED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1"); - - wait_on_completion; - TranscriptOpen(RESULTS_FILE, APPEND_MODE); - SetTranscriptMirror; - ReportAlerts; - TranscriptClose; - std.env.stop; - wait; - end process; - - clock_prc : process - begin - clk <= '0'; - wait for 25 ns; - clk <= '1'; - wait for 25 ns; - end process; - - alert_prc : process(all) - begin - if rising_edge(clk) then - -- TODO - end if; - end process; - - dds_prc : process(all) - variable col : COLLECTION_TYPE := DEFAULT_COLLECTION; - begin - if rising_edge(clk) then - dds_done <= '0'; - case (dds_stage ) is - when IDLE => - if (dds_start = '1') then - dds_stage <= START; - else - dds_done <= '1'; - end if; - when START => - if (ack_dds = '1') then - dds_stage <= DONE; - dds_cnt <= 0; - end if; - when DONE => - if (done_dds = '1') then - AffirmIfEqual(ret_id, return_code_dds, dds.ret_code); - case (dds.ret_code) is - when RETCODE_OK => - case (dds.opcode) is - when GET_REQUESTED_DEADLINE_MISSED_STATUS => - dds_stage <= CHECK_DEADLINE; - dds_cnt <= 0; - when others => - gen_collection(mem, col, dds, INSTANCE_PRESENTATION_QOS, FALSE); - dds_stage <= CHECK_SI; - dds_cnt <= 0; - end case; - when others => - dds_stage <= IDLE; - end case; - end if; - when CHECK_SI => - if (si_valid = '1') then - AffirmIfEqual(sstate_id, si_sample_state, col.s(dds_cnt).sstate); - AffirmIfEqual(vstate_id, si_view_state, col.s(dds_cnt).vstate); - AffirmIfEqual(istate_id, si_instance_state, col.s(dds_cnt).istate); - AffirmIfEqual(ts_id, to_unsigned(si_source_timestamp), to_unsigned(col.s(dds_cnt).ts)); - AffirmIfEqual(inst_id, to_unsigned(si_instance_handle), to_unsigned(col.s(dds_cnt).inst)); - AffirmIfEqual(pub_id, to_unsigned(si_publication_handle), to_unsigned(HANDLE_NIL)); - AffirmIfEqual(dis_gen_cnt_id, si_disposed_generation_count, std_logic_vector(to_unsigned(col.s(dds_cnt).dis_gen_cnt,WORD_WIDTH))); - AffirmIfEqual(no_w_gen_cnt_id, si_no_writers_generation_count, std_logic_vector(to_unsigned(col.s(dds_cnt).no_w_gen_cnt,WORD_WIDTH))); - AffirmIfEqual(srank_id, si_sample_rank, std_logic_vector(to_unsigned(col.s(dds_cnt).srank,WORD_WIDTH))); - AffirmIfEqual(grank_id, si_generation_rank, std_logic_vector(to_unsigned(col.s(dds_cnt).grank,WORD_WIDTH))); - AffirmIfEqual(agrank_id, si_absolute_generation_rank, std_logic_vector(to_unsigned(col.s(dds_cnt).agrank,WORD_WIDTH))); - if (si_valid_data = '1') then - AffirmIf(valid_id, col.s(dds_cnt).data /= EMPTY_TEST_PACKET, "Sample with Data not expected"); - dds_stage <= CHECK_DATA; - dds_cnt2 <= 0; - else - AffirmIf(valid_id, col.s(dds_cnt).data = EMPTY_TEST_PACKET, "Sample with Data expected"); - if (dds_cnt = col.len-1) then - -- DONE - dds_stage <= WAIT_EOC; - else - dds_cnt <= dds_cnt + 1; - end if; - end if; - end if; - AffirmIf(eoc_id, eoc = '0', "EOC pulled high"); - when CHECK_DATA => - if (valid_out_dds = '1') then - AffirmIfEqual(data_id, data_out_dds, col.s(dds_cnt).data.data(dds_cnt2)); - dds_cnt2 <= dds_cnt2 + 1; - if (dds_cnt2 = col.s(dds_cnt).data.length-1) then - AlertIf(data_id, last_word_out_dds /= '1', "Last Word Signal not pulled High", ERROR); - if (dds_cnt = col.len-1) then - -- DONE - dds_stage <= WAIT_EOC; - else - dds_stage <= CHECK_SI; - dds_cnt <= dds_cnt + 1; - end if; - end if; - end if; - when WAIT_EOC => - if (eoc = '1') then - dds_stage <= IDLE; - end if; - when CHECK_DEADLINE => - if (valid_out_dds = '1') then - dds_cnt <= dds_cnt + 1; - case (dds_cnt) is - when 0 => - AffirmIfEqual(data_id, data_out_dds, std_logic_vector(to_unsigned(dds.count,CDR_LONG_WIDTH))); - when 1 => - AffirmIfEqual(data_id, data_out_dds, std_logic_vector(to_unsigned(dds.change,CDR_LONG_WIDTH))); - when 2 => - AffirmIfEqual(data_id, data_out_dds, std_logic_vector(dds.inst(0))); - when 3 => - AffirmIfEqual(data_id, data_out_dds, std_logic_vector(dds.inst(1))); - when 4 => - AffirmIfEqual(data_id, data_out_dds, std_logic_vector(dds.inst(2))); - when 5 => - AffirmIfEqual(data_id, data_out_dds, std_logic_vector(dds.inst(3))); - AlertIf(data_id, last_word_out_dds /= '1', "Last Word Signal not pulled High", ERROR); - dds_stage <= IDLE; - when others => - null; - end case; - end if; - end case; - end if; - - -- DEFAULT - start_dds <= '0'; - opcode_dds <= NOP; - instance_state_dds <= ANY_INSTANCE_STATE; - view_state_dds <= ANY_VIEW_STATE; - sample_state_dds <= ANY_SAMPLE_STATE; - instance_handle_dds <= HANDLE_NIL; - max_samples_dds <= (others => '0'); - get_data_dds <= '0'; - ready_out_dds <= '0'; - - - case (dds_stage ) is - when START => - start_dds <= '1'; - opcode_dds <= dds.opcode; - instance_state_dds <= dds.istate; - view_state_dds <= dds.vstate; - sample_state_dds <= dds.sstate; - instance_handle_dds <= dds.inst; - max_samples_dds <= std_logic_vector(to_unsigned(dds.max_samples, WORD_WIDTH)); - when CHECK_SI => - if (si_valid = '1' and si_valid_data = '1') then - get_data_dds <= '1'; - end if; - when CHECK_DATA => - ready_out_dds <= '1'; - when CHECK_DEADLINE => - ready_out_dds <= '1'; - when others => - null; - end case; - end process; - - rtps_prc : process(all) - variable stimulus : TEST_PACKET_TYPE := EMPTY_TEST_PACKET; - begin - if rising_edge(clk) then - rtps_done <= '0'; - case (rtps_stage) is - when IDLE => - if (rtps_start = '1') then - rtps_stage <= START; - else - rtps_done <= '1'; - end if; - when START => - if (ack_rtps = '1') then - case (rtps.opcode) is - when ADD_CACHE_CHANGE => - gen_add_cache_change_dds(rtps.cc, rtps.lifespan, rtps.writer_pos, stimulus); - rtps_stage <= PUSH; - when others => - rtps_stage <= DONE; - end case; - end if; - when PUSH => - if (ready_in_rtps = '1') then - rtps_cnt <= rtps_cnt + 1; - if (rtps_cnt = stimulus.length-1) then - rtps_stage <= DONE; - end if; - end if; - when DONE => - if (done_rtps = '1') then - AffirmIfEqual(ret_id, HISTORY_CACHE_RESPONSE_TYPE'pos(ret_rtps), HISTORY_CACHE_RESPONSE_TYPE'pos(rtps.ret_code)); - rtps_stage <= IDLE; - end if; - end case; - end if; - - -- DEFAULT - start_rtps <= '0'; - opcode_rtps <= NOP; - valid_in_rtps <= '0'; - last_word_in_rtps <= '0'; - data_in_rtps <= (others => '0'); - - case (rtps_stage) is - when START => - start_rtps <= '1'; - opcode_rtps <= rtps.opcode; - case (rtps.opcode) is - when REMOVE_WRITER => - data_in_rtps <= std_logic_vector(to_unsigned(rtps.writer_pos,WORD_WIDTH)); - when others => - null; - end case; - when PUSH => - valid_in_rtps <= '1'; - data_in_rtps <= stimulus.data(rtps_cnt); - last_word_in_rtps <= stimulus.last(rtps_cnt); - when others => - null; - end case; - end process; - - watchdog : process - begin - wait for 1 ms; - Alert("Test timeout", FAILURE); - std.env.stop; - end process; - -end architecture; \ No newline at end of file diff --git a/src/Tests/Level_0/L0_dds_reader_test5_arzkriu.vhd b/src/Tests/Level_0/L0_dds_reader_test5.vhd similarity index 56% rename from src/Tests/Level_0/L0_dds_reader_test5_arzkriu.vhd rename to src/Tests/Level_0/L0_dds_reader_test5.vhd index 6ba82d9..22f84d3 100644 --- a/src/Tests/Level_0/L0_dds_reader_test5_arzkriu.vhd +++ b/src/Tests/Level_0/L0_dds_reader_test5.vhd @@ -12,53 +12,71 @@ use work.rtps_test_package.all; -- This testbench tests the Sample Reject Status Handling of the DDS Reader, and more specifically the GET_SAMPLE_REJECTED_STATUS DDS Operation. -entity L0_dds_reader_test5_arzkriu is +entity L0_dds_reader_test5 is end entity; -architecture testbench of L0_dds_reader_test5_arzkriu is +architecture testbench of L0_dds_reader_test5 is -- *CONSTANT DECLARATION* constant MAX_REMOTE_ENDPOINTS : natural := 3; + constant NUM_READERS : natural := 1; + + impure function gen_test_config return CONFIG_ARRAY_TYPE is + variable ret : CONFIG_ARRAY_TYPE(0 to NUM_READERS-1) := (others => DEFAULT_WRITER_CONFIG); + begin + -- arzkriu + ret(0).TIME_BASED_FILTER_QOS := DURATION_ZERO; + ret(0).DEADLINE_QOS := DURATION_INFINITE; + ret(0).MAX_SAMPLES := std_logic_vector(to_unsigned(2,CDR_LONG_WIDTH)); + ret(0).MAX_INSTANCES := std_logic_vector(to_unsigned(3,CDR_LONG_WIDTH)); + ret(0).MAX_SAMPLES_PER_INSTANCE := std_logic_vector(to_unsigned(1,CDR_LONG_WIDTH)); + ret(0).HISTORY_QOS := KEEP_ALL_HISTORY_QOS; + ret(0).RELIABILITY_QOS := RELIABLE_RELIABILITY_QOS; + ret(0).PRESENTATION_QOS := INSTANCE_PRESENTATION_QOS; + ret(0).DESTINATION_ORDER_QOS := BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS; + ret(0).COHERENT_ACCESS := FALSE; + ret(0).ORDERED_ACCESS := FALSE; + ret(0).WITH_KEY := TRUE; + ret(0).MAX_PAYLOAD_SIZE := 40; + return ret; + end function; + constant TEST_CONFIG : CONFIG_ARRAY_TYPE := gen_test_config; -- *TYPE DECLARATION* type DDS_STAGE_TYPE is (IDLE, START, DONE, CHECK_SI, CHECK_DATA, WAIT_EOC, CHECK_SAMPLE_REJECT); type RTPS_STAGE_TYPE is (IDLE, START, PUSH, DONE); + type DDS_READER_MEM_ARRAY_TYPE is array (0 to NUM_READERS-1) of DDS_READER_MEM_TYPE; -- *SIGNAL DECLARATION* signal clk : std_logic := '0'; signal reset : std_logic := '1'; signal check_time : TIME_TYPE := TIME_ZERO; - signal start_rtps, start_dds, ack_rtps, ack_dds, done_rtps, done_dds : std_logic := '0'; - signal opcode_rtps : HISTORY_CACHE_OPCODE_TYPE := NOP; - signal opcode_dds : DDS_READER_OPCODE_TYPE := NOP; - signal ret_rtps : HISTORY_CACHE_RESPONSE_TYPE := ERROR; - signal ready_in_rtps, valid_in_rtps, last_word_in_rtps : std_logic := '0'; - signal ready_out_dds, valid_out_dds, last_word_out_dds : std_logic := '0'; - signal data_in_rtps, data_out_dds : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); - signal get_data_dds, si_valid_data, si_valid, eoc : std_logic := '0'; - signal return_code_dds : std_logic_vector(RETURN_CODE_WIDTH-1 downto 0) := (others => '0'); - signal status : std_logic_vector(STATUS_KIND_WIDTH-1 downto 0) := (others => '0'); - signal instance_state_dds, si_instance_state : std_logic_vector(INSTANCE_STATE_KIND_WIDTH-1 downto 0) := ANY_INSTANCE_STATE; - signal view_state_dds, si_view_state : std_logic_vector(VIEW_STATE_KIND_WIDTH-1 downto 0) := ANY_VIEW_STATE; - signal sample_state_dds, si_sample_state : std_logic_vector(SAMPLE_STATE_KIND_WIDTH-1 downto 0) := ANY_SAMPLE_STATE; - signal instance_handle_dds, si_instance_handle : INSTANCE_HANDLE_TYPE := HANDLE_NIL; - signal max_samples_dds : std_logic_vector(MAX_SAMPLES_WIDTH-1 downto 0) := (others => '0'); - signal si_source_timestamp : TIME_TYPE := TIME_INVALID; - signal si_publication_handle : INSTANCE_HANDLE_TYPE := HANDLE_NIL; - signal si_disposed_generation_count : std_logic_vector(DISPOSED_GENERATION_COUNT_WIDTH-1 downto 0) := (others => '0'); - signal si_no_writers_generation_count : std_logic_vector(NO_WRITERS_GENERATION_COUNT_WIDTH-1 downto 0) := (others => '0'); - signal si_sample_rank : std_logic_vector(SAMPLE_RANK_WIDTH-1 downto 0) := (others => '0'); - signal si_generation_rank : std_logic_vector(GENERATION_RANK_WIDTH-1 downto 0) := (others => '0'); - signal si_absolute_generation_rank: std_logic_vector(ABSOLUTE_GENERATION_COUNT_WIDTH-1 downto 0) := (others => '0'); + signal start_rtps, start_dds, ack_rtps, ack_dds, done_rtps, done_dds : std_logic_vector(0 to NUM_READERS-1) := (others => '0'); + signal opcode_rtps : HISTORY_CACHE_OPCODE_ARRAY_TYPE(0 to NUM_READERS-1) := (others => NOP); + signal opcode_dds : DDS_READER_OPCODE_ARRAY_TYPE(0 to NUM_READERS-1) := (others => NOP); + signal ret_rtps : HISTORY_CACHE_RESPONSE_ARRAY_TYPE(0 to NUM_READERS-1) := (others => ERROR); + signal ready_in_rtps, valid_in_rtps, last_word_in_rtps : std_logic_vector(0 to NUM_READERS-1) := (others => '0'); + signal ready_out_dds, valid_out_dds, last_word_out_dds : std_logic_vector(0 to NUM_READERS-1) := (others => '0'); + signal data_in_rtps, data_out_dds : WORD_ARRAY_TYPE(0 to NUM_READERS-1) := (others => (others => '0')); + signal get_data_dds, si_valid, eoc : std_logic_vector(0 to NUM_READERS-1) := (others => '0'); + signal return_code_dds : RETURN_CODE_ARRAY_TYPE(0 to NUM_READERS-1) := (others => (others => '0')); + signal status : STATUS_KIND_ARRAY_TYPE(0 to NUM_READERS-1) := (others => (others => '0')); + signal instance_state_dds : INSTANCE_STATE_ARRAY_TYPE(0 to NUM_READERS-1) := (others => ANY_INSTANCE_STATE); + signal view_state_dds : VIEW_STATE_ARRAY_TYPE(0 to NUM_READERS-1) := (others => ANY_VIEW_STATE); + signal sample_state_dds : SAMPLE_STATE_ARRAY_TYPE(0 to NUM_READERS-1) := (others => ANY_SAMPLE_STATE); + signal instance_handle_dds : INSTANCE_HANDLE_ARRAY_TYPE(0 to NUM_READERS-1) := (others => HANDLE_NIL); + signal max_samples_dds : MAX_SAMPLES_ARRAY_TYPE(0 to NUM_READERS-1) := (others => (others => '0')); + signal sample_info : SAMPLE_INFO_ARRAY_TYPE(0 to NUM_READERS-1); + signal ind : natural := 0; signal dds_start , dds_done , rtps_start, rtps_done : std_logic := '0'; signal dds_cnt, dds_cnt2, rtps_cnt : natural := 0; signal dds_stage : DDS_STAGE_TYPE := IDLE; signal rtps_stage : RTPS_STAGE_TYPE := IDLE; shared variable dds : DDS_READER_TEST_TYPE := DEFAULT_DDS_READER_TEST; shared variable rtps : RTPS_READER_TEST_TYPE := DEFAULT_RTPS_READER_TEST; - shared variable mem : DDS_READER_MEM_TYPE := DEFAULT_DDS_READER_MEM; + shared variable mem : DDS_READER_MEM_ARRAY_TYPE := (others => DEFAULT_DDS_READER_MEM); signal data_id, ret_id, sstate_id, vstate_id, istate_id, inst_id, ts_id, pub_id, dis_gen_cnt_id, no_w_gen_cnt_id, srank_id, grank_id, agrank_id, eoc_id, valid_id, status_id : AlertLogIDType; -- *FUNCTION DECLARATION* @@ -80,70 +98,55 @@ architecture testbench of L0_dds_reader_test5_arzkriu is return ret; end function; + procedure wait_on_sig(signal sig : std_logic) is + begin + if (sig /= '1') then + wait on sig until sig = '1'; + end if; + end procedure; + begin -- Unit Under Test uut : entity work.dds_reader(arch) generic map ( - TIME_BASED_FILTER_QOS => DURATION_ZERO, - DEADLINE_QOS => DURATION_INFINITE, - MAX_SAMPLES => std_logic_vector(to_unsigned(2,CDR_LONG_WIDTH)), - MAX_INSTANCES => std_logic_vector(to_unsigned(3,CDR_LONG_WIDTH)), - MAX_SAMPLES_PER_INSTANCE => std_logic_vector(to_unsigned(1,CDR_LONG_WIDTH)), - HISTORY_QOS => KEEP_ALL_HISTORY_QOS, - RELIABILITY_QOS => RELIABLE_RELIABILITY_QOS, - PRESENTATION_QOS => INSTANCE_PRESENTATION_QOS, - DESTINATION_ORDER_QOS => BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS, - COHERENT_ACCESS => FALSE, - ORDERED_ACCESS => FALSE, - WITH_KEY => TRUE, - PAYLOAD_FRAME_SIZE => 11, - MAX_REMOTE_ENDPOINTS => MAX_REMOTE_ENDPOINTS + NUM_READERS => NUM_READERS, + CONFIG_ARRAY => to_QUARTUS_CONFIG_ARRAY_TYPE(TEST_CONFIG), + MAX_REMOTE_ENDPOINTS => MAX_REMOTE_ENDPOINTS ) port map ( - clk => clk, - reset => reset, - time => check_time, - start_rtps => start_rtps, - opcode_rtps => opcode_rtps, - ack_rtps => ack_rtps, - done_rtps => done_rtps, - ret_rtps => ret_rtps, - data_in_rtps => data_in_rtps, - valid_in_rtps => valid_in_rtps, - ready_in_rtps => ready_in_rtps, - last_word_in_rtps => last_word_in_rtps, - start_dds => start_dds, - ack_dds => ack_dds, - opcode_dds => opcode_dds, - instance_state_dds => instance_state_dds, - view_state_dds => view_state_dds, - sample_state_dds => sample_state_dds, - instance_handle_dds => instance_handle_dds, - max_samples_dds => max_samples_dds, - get_data_dds => get_data_dds, - done_dds => done_dds, - return_code_dds => return_code_dds, - ready_out_dds => ready_out_dds, - valid_out_dds => valid_out_dds, - data_out_dds => data_out_dds, - last_word_out_dds => last_word_out_dds, - sample_info.sample_state => si_sample_state, - sample_info.view_state => si_view_state, - sample_info.instance_state => si_instance_state, - sample_info.source_timestamp => si_source_timestamp, - sample_info.instance_handle => si_instance_handle, - sample_info.publication_handle => si_publication_handle, - sample_info.disposed_generation_count => si_disposed_generation_count, - sample_info.no_writers_generation_count => si_no_writers_generation_count, - sample_info.sample_rank => si_sample_rank, - sample_info.generation_rank => si_generation_rank, - sample_info.absolute_generation_rank => si_absolute_generation_rank, - sample_info.valid_data => si_valid_data, - sample_info_valid => si_valid, - sample_info_ack => '1', - eoc => eoc, - status => status + clk => clk, + reset => reset, + time => check_time, + start_rtps => start_rtps, + opcode_rtps => opcode_rtps, + ack_rtps => ack_rtps, + done_rtps => done_rtps, + ret_rtps => ret_rtps, + data_in_rtps => data_in_rtps, + valid_in_rtps => valid_in_rtps, + ready_in_rtps => ready_in_rtps, + last_word_in_rtps => last_word_in_rtps, + start_dds => start_dds, + ack_dds => ack_dds, + opcode_dds => opcode_dds, + instance_state_dds => instance_state_dds, + view_state_dds => view_state_dds, + sample_state_dds => sample_state_dds, + instance_handle_dds => instance_handle_dds, + max_samples_dds => max_samples_dds, + get_data_dds => get_data_dds, + done_dds => done_dds, + return_code_dds => return_code_dds, + ready_out_dds => ready_out_dds, + valid_out_dds => valid_out_dds, + data_out_dds => data_out_dds, + last_word_out_dds => last_word_out_dds, + sample_info => sample_info, + sample_info_valid => si_valid, + sample_info_ack => (others => '1'), + eoc => eoc, + status => status ); stimulus_prc : process @@ -198,20 +201,6 @@ begin wait until rising_edge(clk); end procedure; - procedure wait_on_dds is - begin - if (dds_done /= '1') then - wait until dds_done = '1'; - end if; - end procedure; - - procedure wait_on_rtps is - begin - if (rtps_done /= '1') then - wait until rtps_done = '1'; - end if; - end procedure; - procedure wait_on_completion is begin if (rtps_done /= '1' or dds_done /= '1') then @@ -238,7 +227,7 @@ begin begin - SetAlertLogName("L0_dds_reader_test5_arzkriu - (KEEP ALL, Reliable, Zero TIME_BASED_FILTER, Keyed, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER, ACCESS SCOPE Instance, Unordered) - Sample Rejected Status Handling"); + SetAlertLogName("L0_dds_reader_test5 - Sample Rejected Status Handling"); SetAlertEnable(FAILURE, TRUE); SetAlertEnable(ERROR, TRUE); SetAlertEnable(WARNING, TRUE); @@ -277,81 +266,94 @@ begin wait until rising_edge(clk); wait until rising_edge(clk); reset <= '0'; + wait_on_idle; -- MEM: - -- ISTATE: - -- WRITER: - - AffirmIf(status_id,(status and SAMPLE_REJECTED_STATUS) /= SAMPLE_REJECTED_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(0) and SAMPLE_REJECTED_STATUS) /= SAMPLE_REJECTED_STATUS, "Expected: 0", "Received: 1"); cc := DEFAULT_CACHE_CHANGE; cc.serialized_key := FALSE; cc.kind := ALIVE; cc.instance := kh1; cc.payload := gen_payload(kh1,30); - cc.src_timestamp := gen_duration(1,0); + cc.src_timestamp := gen_duration(1 sec); - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Aligned Payload (3 Slots)] (ACCEPTED)", INFO); + Log("R0: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Aligned Payload (3 Slots)]", INFO); + Log("R0: ACCEPTED", DEBUG); rtps := DEFAULT_RTPS_READER_TEST; rtps.opcode := ADD_CACHE_CHANGE; rtps.cc := cc; rtps.writer_pos := 0; rtps.ret_code := OK; s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(0), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + -- READER 0 + ind <= 0; start_rtps; - wait_on_rtps; + wait_on_sig(rtps_done); wait_on_idle; -- MEM: I1S1 -- ISTATE: I1:ALIVE -- WRITER: W0:I1 - AffirmIf(status_id,(status and SAMPLE_REJECTED_STATUS) /= SAMPLE_REJECTED_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(0) and SAMPLE_REJECTED_STATUS) /= SAMPLE_REJECTED_STATUS, "Expected: 0", "Received: 1"); cc := DEFAULT_CACHE_CHANGE; cc.serialized_key := FALSE; cc.kind := ALIVE; cc.instance := kh2; cc.payload := gen_payload(kh2,10); - cc.src_timestamp := gen_duration(2,0); + cc.src_timestamp := gen_duration(2 sec); - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 2, Writer 1, Aligned Payload] (REJECTED: Payload memory Full)", INFO); + Log("R0: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 2, Writer 1, Aligned Payload]", INFO); + Log("R0: REJECTED [Payload memory Full]", DEBUG); rtps := DEFAULT_RTPS_READER_TEST; rtps.opcode := ADD_CACHE_CHANGE; rtps.cc := cc; rtps.writer_pos := 1; rtps.ret_code := REJECTED; + -- READER 0 + ind <= 0; start_rtps; - wait_on_rtps; + wait_on_sig(rtps_done); wait_on_idle; -- MEM: I1S1 -- ISTATE: I1:ALIVE -- WRITER: W0:I1 - AffirmIf(status_id,(status and SAMPLE_REJECTED_STATUS) = SAMPLE_REJECTED_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(0) and SAMPLE_REJECTED_STATUS) = SAMPLE_REJECTED_STATUS, "Expected: 1", "Received: 0"); - Log("DDS Operation GET_SAMPLE_REJECTED_STATUS (Expected: Count 1, Change 1, HANDLE_NIL, REJECTED_BY_PAYOAD_MEMORY_LIMIT)", INFO); + Log("R0: DDS Operation GET_SAMPLE_REJECTED_STATUS", INFO); + Log("R0: Expected [Count 1, Change 1, HANDLE_NIL, REJECTED_BY_PAYOAD_MEMORY_LIMIT]", DEBUG); dds := DEFAULT_DDS_READER_TEST; dds.opcode := GET_SAMPLE_REJECTED_STATUS; dds.ret_code := RETCODE_OK; dds.count := 1; dds.change := 1; dds.inst := HANDLE_NIL; - dds.last_reason:= REJECTED_BY_PAYOAD_MEMORY_LIMIT; + dds.last_reason:= REJECTED_BY_PAYLOAD_MEMORY_LIMIT; + -- READER 0 + ind <= 0; start_dds; - wait_on_dds; + wait_on_sig(dds_done); wait_on_idle; - AffirmIf(status_id,(status and SAMPLE_REJECTED_STATUS) /= SAMPLE_REJECTED_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(0) and SAMPLE_REJECTED_STATUS) /= SAMPLE_REJECTED_STATUS, "Expected: 0", "Received: 1"); - Log("DDS Operation TAKE [MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); + Log("R0: DDS Operation TAKE [MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); dds := DEFAULT_DDS_READER_TEST; dds.opcode := TAKE; dds.max_samples := 1; dds.sstate := ANY_SAMPLE_STATE; dds.istate := ANY_INSTANCE_STATE; dds.vstate := ANY_VIEW_STATE; + -- READER 0 + ind <= 0; start_dds; - wait_on_dds; + wait_on_sig(dds_done); + wait_on_idle; -- MEM: - -- ISTATE: I1:ALIVE -- WRITER: W0:I1 @@ -361,54 +363,63 @@ begin cc.kind := ALIVE; cc.instance := kh2; cc.payload := gen_payload(kh2,40); - cc.src_timestamp := gen_duration(3,0); + cc.src_timestamp := gen_duration(3 sec); - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 2, Writer 1, Aligned Payload (4 Slots)] (REJECTED: Payload memory Full)", INFO); + Log("R0: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 2, Writer 1, Aligned Payload (4 Slots)]", INFO); + Log("R0: REJECTED [Payload memory Full]", DEBUG); rtps := DEFAULT_RTPS_READER_TEST; rtps.opcode := ADD_CACHE_CHANGE; rtps.cc := cc; rtps.writer_pos := 1; rtps.ret_code := REJECTED; + -- READER 0 + ind <= 0; start_rtps; - wait_on_rtps; + wait_on_sig(rtps_done); wait_on_idle; -- MEM: - -- ISTATE: I1:ALIVE -- WRITER: W0:I1 - AffirmIf(status_id,(status and SAMPLE_REJECTED_STATUS) = SAMPLE_REJECTED_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(0) and SAMPLE_REJECTED_STATUS) = SAMPLE_REJECTED_STATUS, "Expected: 1", "Received: 0"); - Log("DDS Operation GET_SAMPLE_REJECTED_STATUS (Expected: Count 2, Change 1, Instance 2, REJECTED_BY_PAYOAD_MEMORY_LIMIT)", INFO); + Log("R0: DDS Operation GET_SAMPLE_REJECTED_STATUS", INFO); + Log("R0: Expected [Count 2, Change 1, Instance 2, REJECTED_BY_PAYOAD_MEMORY_LIMIT]", DEBUG); dds := DEFAULT_DDS_READER_TEST; dds.opcode := GET_SAMPLE_REJECTED_STATUS; dds.ret_code := RETCODE_OK; dds.count := 2; dds.change := 1; dds.inst := kh2; - dds.last_reason:= REJECTED_BY_PAYOAD_MEMORY_LIMIT; + dds.last_reason:= REJECTED_BY_PAYLOAD_MEMORY_LIMIT; + -- READER 0 + ind <= 0; start_dds; - wait_on_dds; + wait_on_sig(dds_done); wait_on_idle; - AffirmIf(status_id,(status and SAMPLE_REJECTED_STATUS) /= SAMPLE_REJECTED_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(0) and SAMPLE_REJECTED_STATUS) /= SAMPLE_REJECTED_STATUS, "Expected: 0", "Received: 1"); cc := DEFAULT_CACHE_CHANGE; cc.serialized_key := FALSE; cc.kind := ALIVE; cc.instance := kh1; cc.payload := gen_payload(kh1,10); - cc.src_timestamp := gen_duration(4,0); + cc.src_timestamp := gen_duration(4 sec); - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Aligned Payload] (ACCEPTED)", INFO); + Log("R0: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Aligned Payload]", INFO); + Log("R0: ACCEPTED", DEBUG); rtps := DEFAULT_RTPS_READER_TEST; rtps.opcode := ADD_CACHE_CHANGE; rtps.cc := cc; rtps.writer_pos := 0; rtps.ret_code := OK; s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(0), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + -- READER 0 + ind <= 0; start_rtps; - wait_on_rtps; + wait_on_sig(rtps_done); wait_on_idle; -- MEM: I1S2 -- ISTATE: I1:ALIVE @@ -419,24 +430,28 @@ begin cc.kind := ALIVE; cc.instance := kh1; cc.payload := gen_payload(kh1,10); - cc.src_timestamp := gen_duration(5,0); + cc.src_timestamp := gen_duration(5 sec); - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 1, Aligned Payload] (REJECTED: MAX_SAMPLES_PER_INSTANCE exceeded)", INFO); + Log("R0: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 1, Aligned Payload]", INFO); + Log("R0: REJECTED [MAX_SAMPLES_PER_INSTANCE exceeded]", DEBUG); rtps := DEFAULT_RTPS_READER_TEST; rtps.opcode := ADD_CACHE_CHANGE; rtps.cc := cc; rtps.writer_pos := 1; rtps.ret_code := REJECTED; + -- READER 0 + ind <= 0; start_rtps; - wait_on_rtps; + wait_on_sig(rtps_done); wait_on_idle; -- MEM: I1S2 -- ISTATE: I1:ALIVE -- WRITER: W0:I1 - AffirmIf(status_id,(status and SAMPLE_REJECTED_STATUS) = SAMPLE_REJECTED_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(0) and SAMPLE_REJECTED_STATUS) = SAMPLE_REJECTED_STATUS, "Expected: 1", "Received: 0"); - Log("DDS Operation GET_SAMPLE_REJECTED_STATUS (Expected: Count 3, Change 1, Instance 1, REJECTED_BY_SAMPLES_PER_INSTANCE_LIMIT)", INFO); + Log("R0: DDS Operation GET_SAMPLE_REJECTED_STATUS", INFO); + Log("R0: Expected [Count 3, Change 1, Instance 1, REJECTED_BY_SAMPLES_PER_INSTANCE_LIMIT]", DEBUG); dds := DEFAULT_DDS_READER_TEST; dds.opcode := GET_SAMPLE_REJECTED_STATUS; dds.ret_code := RETCODE_OK; @@ -444,59 +459,68 @@ begin dds.change := 1; dds.inst := kh1; dds.last_reason:= REJECTED_BY_SAMPLES_PER_INSTANCE_LIMIT; + -- READER 0 + ind <= 0; start_dds; - wait_on_dds; + wait_on_sig(dds_done); wait_on_idle; - AffirmIf(status_id,(status and SAMPLE_REJECTED_STATUS) /= SAMPLE_REJECTED_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(0) and SAMPLE_REJECTED_STATUS) /= SAMPLE_REJECTED_STATUS, "Expected: 0", "Received: 1"); cc := DEFAULT_CACHE_CHANGE; cc.serialized_key := FALSE; cc.kind := ALIVE; cc.instance := kh2; cc.payload := gen_payload(kh2,10); - cc.src_timestamp := gen_duration(5,0); + cc.src_timestamp := gen_duration(5 sec); - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 2, Writer 1, Aligned Payload] (ACCEPTED)", INFO); + Log("R0: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 2, Writer 1, Aligned Payload]", INFO); + Log("R0: ACCEPTED", DEBUG); rtps := DEFAULT_RTPS_READER_TEST; rtps.opcode := ADD_CACHE_CHANGE; rtps.cc := cc; rtps.writer_pos := 1; rtps.ret_code := OK; s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(0), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + -- READER 0 + ind <= 0; start_rtps; - wait_on_rtps; + wait_on_sig(rtps_done); wait_on_idle; -- MEM: I1S2, I2S1 -- ISTATE: I1:ALIVE, I2:ALIVE -- WRITER: W0:I1, W1:I2 - AffirmIf(status_id,(status and SAMPLE_REJECTED_STATUS) /= SAMPLE_REJECTED_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(0) and SAMPLE_REJECTED_STATUS) /= SAMPLE_REJECTED_STATUS, "Expected: 0", "Received: 1"); cc := DEFAULT_CACHE_CHANGE; cc.serialized_key := FALSE; cc.kind := ALIVE; cc.instance := kh3; cc.payload := gen_payload(kh3,10); - cc.src_timestamp := gen_duration(6,0); + cc.src_timestamp := gen_duration(6 sec); - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 3, Writer 2, Aligned Payload] (REJECTED: MAX_SAMPLES exceeded)", INFO); + Log("R0: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 3, Writer 2, Aligned Payload]", INFO); + Log("R0: REJECTED [MAX_SAMPLES exceeded]", DEBUG); rtps := DEFAULT_RTPS_READER_TEST; rtps.opcode := ADD_CACHE_CHANGE; rtps.cc := cc; rtps.writer_pos := 2; rtps.ret_code := REJECTED; + -- READER 0 + ind <= 0; start_rtps; - wait_on_rtps; + wait_on_sig(rtps_done); wait_on_idle; -- MEM: I1S2, I2S1 -- ISTATE: I1:ALIVE, I2:ALIVE -- WRITER: W0:I1, W1:I2 - AffirmIf(status_id,(status and SAMPLE_REJECTED_STATUS) = SAMPLE_REJECTED_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(0) and SAMPLE_REJECTED_STATUS) = SAMPLE_REJECTED_STATUS, "Expected: 1", "Received: 0"); - Log("DDS Operation GET_SAMPLE_REJECTED_STATUS (Expected: Count 4, Change 1, Instance 3, REJECTED_BY_SAMPLES_LIMIT)", INFO); + Log("R0: DDS Operation GET_SAMPLE_REJECTED_STATUS", INFO); + Log("R0: Expected [Count 4, Change 1, Instance 3, REJECTED_BY_SAMPLES_LIMIT]", DEBUG); dds := DEFAULT_DDS_READER_TEST; dds.opcode := GET_SAMPLE_REJECTED_STATUS; dds.ret_code := RETCODE_OK; @@ -504,74 +528,86 @@ begin dds.change := 1; dds.inst := kh3; dds.last_reason:= REJECTED_BY_SAMPLES_LIMIT; + -- READER 0 + ind <= 0; start_dds; - wait_on_dds; + wait_on_sig(dds_done); wait_on_idle; - AffirmIf(status_id,(status and SAMPLE_REJECTED_STATUS) /= SAMPLE_REJECTED_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(0) and SAMPLE_REJECTED_STATUS) /= SAMPLE_REJECTED_STATUS, "Expected: 0", "Received: 1"); - Log("DDS Operation TAKE [MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); + Log("R0: DDS Operation TAKE [MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); dds := DEFAULT_DDS_READER_TEST; dds.opcode := TAKE; dds.max_samples := 1; dds.sstate := ANY_SAMPLE_STATE; dds.istate := ANY_INSTANCE_STATE; dds.vstate := ANY_VIEW_STATE; + -- READER 0 + ind <= 0; start_dds; - wait_on_dds; + wait_on_sig(dds_done); + wait_on_idle; -- MEM: I2S1 -- ISTATE: I1:ALIVE, I2:ALIVE -- WRITER: W0:I1, W1:I2 - AffirmIf(status_id,(status and SAMPLE_REJECTED_STATUS) /= SAMPLE_REJECTED_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(0) and SAMPLE_REJECTED_STATUS) /= SAMPLE_REJECTED_STATUS, "Expected: 0", "Received: 1"); cc := DEFAULT_CACHE_CHANGE; cc.serialized_key := FALSE; cc.kind := ALIVE; cc.instance := kh3; cc.payload := gen_payload(kh3,10); - cc.src_timestamp := gen_duration(7,0); + cc.src_timestamp := gen_duration(7 sec); - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 3, Writer 2, Aligned Payload] (ACCEPTED)", INFO); + Log("R0: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 3, Writer 2, Aligned Payload]", INFO); + Log("R0: ACCEPTED", DEBUG); rtps := DEFAULT_RTPS_READER_TEST; rtps.opcode := ADD_CACHE_CHANGE; rtps.cc := cc; rtps.writer_pos := 2; rtps.ret_code := OK; s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(0), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + -- READER 0 + ind <= 0; start_rtps; - wait_on_rtps; + wait_on_sig(rtps_done); wait_on_idle; -- MEM: I2S1, I3S1 -- ISTATE: I1:ALIVE, I2:ALIVE, I3:ALIVE -- WRITER: W0:I1, W1:I2, W2:I3 - AffirmIf(status_id,(status and SAMPLE_REJECTED_STATUS) /= SAMPLE_REJECTED_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(0) and SAMPLE_REJECTED_STATUS) /= SAMPLE_REJECTED_STATUS, "Expected: 0", "Received: 1"); cc := DEFAULT_CACHE_CHANGE; cc.serialized_key := FALSE; cc.kind := ALIVE; cc.instance := kh1; cc.payload := gen_payload(kh1,10); - cc.src_timestamp := gen_duration(8,0); + cc.src_timestamp := gen_duration(8 sec); - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Aligned Payload] (REJECTED: MAX_SAMPLES exceeded)", INFO); + Log("R0: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Aligned Payload]", INFO); + Log("R0: REJECTED [MAX_SAMPLES exceeded]", DEBUG); rtps := DEFAULT_RTPS_READER_TEST; rtps.opcode := ADD_CACHE_CHANGE; rtps.cc := cc; rtps.writer_pos := 2; rtps.ret_code := REJECTED; + -- READER 0 + ind <= 0; start_rtps; - wait_on_rtps; + wait_on_sig(rtps_done); wait_on_idle; -- MEM: I2S1, I3S1 -- ISTATE: I1:ALIVE, I2:ALIVE, I3:ALIVE -- WRITER: W0:I1, W1:I2, W2:I3 - AffirmIf(status_id,(status and SAMPLE_REJECTED_STATUS) = SAMPLE_REJECTED_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(0) and SAMPLE_REJECTED_STATUS) = SAMPLE_REJECTED_STATUS, "Expected: 1", "Received: 0"); - Log("DDS Operation GET_SAMPLE_REJECTED_STATUS (Expected: Count 5, Change 1, Instance 1, REJECTED_BY_SAMPLES_LIMIT)", INFO); + Log("R0: DDS Operation GET_SAMPLE_REJECTED_STATUS", INFO); + Log("R0: Expected [Count 5, Change 1, Instance 1, REJECTED_BY_SAMPLES_LIMIT]", DEBUG); dds := DEFAULT_DDS_READER_TEST; dds.opcode := GET_SAMPLE_REJECTED_STATUS; dds.ret_code := RETCODE_OK; @@ -579,35 +615,41 @@ begin dds.change := 1; dds.inst := kh1; dds.last_reason:= REJECTED_BY_SAMPLES_LIMIT; + -- READER 0 + ind <= 0; start_dds; - wait_on_dds; + wait_on_sig(dds_done); wait_on_idle; - AffirmIf(status_id,(status and SAMPLE_REJECTED_STATUS) /= SAMPLE_REJECTED_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(0) and SAMPLE_REJECTED_STATUS) /= SAMPLE_REJECTED_STATUS, "Expected: 0", "Received: 1"); cc := DEFAULT_CACHE_CHANGE; cc.serialized_key := FALSE; cc.kind := ALIVE; cc.instance := kh4; cc.payload := gen_payload(kh4,10); - cc.src_timestamp := gen_duration(9,0); + cc.src_timestamp := gen_duration(9 sec); - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 4, Writer 0, Aligned Payload] (REJECTED: MAX_INSTANCES exceeded)", INFO); + Log("R0: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 4, Writer 0, Aligned Payload]", INFO); + Log("R0: REJECTED: MAX_INSTANCES exceeded", DEBUG); rtps := DEFAULT_RTPS_READER_TEST; rtps.opcode := ADD_CACHE_CHANGE; rtps.cc := cc; rtps.writer_pos := 0; rtps.ret_code := REJECTED; + -- READER 0 + ind <= 0; start_rtps; - wait_on_rtps; + wait_on_sig(rtps_done); wait_on_idle; -- MEM: I2S1, I3S1 -- ISTATE: I1:ALIVE, I2:ALIVE, I3:ALIVE -- WRITER: W0:I1, W1:I2, W2:I3 - AffirmIf(status_id,(status and SAMPLE_REJECTED_STATUS) = SAMPLE_REJECTED_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(0) and SAMPLE_REJECTED_STATUS) = SAMPLE_REJECTED_STATUS, "Expected: 1", "Received: 0"); - Log("DDS Operation GET_SAMPLE_REJECTED_STATUS (Expected: Count 6, Change 1, Instance 1, REJECTED_BY_INSTANCES_LIMIT)", INFO); + Log("R0: DDS Operation GET_SAMPLE_REJECTED_STATUS", INFO); + Log("R0: Expected [Count 6, Change 1, Instance 1, REJECTED_BY_INSTANCES_LIMIT]", DEBUG); dds := DEFAULT_DDS_READER_TEST; dds.opcode := GET_SAMPLE_REJECTED_STATUS; dds.ret_code := RETCODE_OK; @@ -615,66 +657,78 @@ begin dds.change := 1; dds.inst := kh4; dds.last_reason:= REJECTED_BY_INSTANCES_LIMIT; + -- READER 0 + ind <= 0; start_dds; - wait_on_dds; + wait_on_sig(dds_done); wait_on_idle; - AffirmIf(status_id,(status and SAMPLE_REJECTED_STATUS) /= SAMPLE_REJECTED_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(0) and SAMPLE_REJECTED_STATUS) /= SAMPLE_REJECTED_STATUS, "Expected: 0", "Received: 1"); - Log("DDS Operation TAKE [MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); + Log("R0: DDS Operation TAKE [MAX_SAMPLES 1, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); dds := DEFAULT_DDS_READER_TEST; dds.opcode := TAKE; dds.max_samples := 1; dds.sstate := ANY_SAMPLE_STATE; dds.istate := ANY_INSTANCE_STATE; dds.vstate := ANY_VIEW_STATE; + -- READER 0 + ind <= 0; start_dds; - wait_on_dds; + wait_on_sig(dds_done); + wait_on_idle; -- MEM: I3S1 -- ISTATE: I1:ALIVE, I2:ALIVE, I3:ALIVE -- WRITER: W0:I1, W1:I2, W2:I3 - AffirmIf(status_id,(status and SAMPLE_REJECTED_STATUS) /= SAMPLE_REJECTED_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(0) and SAMPLE_REJECTED_STATUS) /= SAMPLE_REJECTED_STATUS, "Expected: 0", "Received: 1"); cc := DEFAULT_CACHE_CHANGE; cc.serialized_key := FALSE; cc.kind := ALIVE; cc.instance := kh4; cc.payload := gen_payload(kh4,10); - cc.src_timestamp := gen_duration(10,0); + cc.src_timestamp := gen_duration(10 sec); - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 4, Writer 0, Aligned Payload] (REJECTED: MAX_INSTANCES exceeded)", INFO); + Log("R0: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 4, Writer 0, Aligned Payload]", INFO); + Log("R0: REJECTED [MAX_INSTANCES exceeded]", DEBUG); rtps := DEFAULT_RTPS_READER_TEST; rtps.opcode := ADD_CACHE_CHANGE; rtps.cc := cc; rtps.writer_pos := 0; rtps.ret_code := REJECTED; + -- READER 0 + ind <= 0; start_rtps; - wait_on_rtps; + wait_on_sig(rtps_done); wait_on_idle; - AffirmIf(status_id,(status and SAMPLE_REJECTED_STATUS) = SAMPLE_REJECTED_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(0) and SAMPLE_REJECTED_STATUS) = SAMPLE_REJECTED_STATUS, "Expected: 1", "Received: 0"); cc := DEFAULT_CACHE_CHANGE; cc.serialized_key := FALSE; cc.kind := ALIVE; cc.instance := kh5; cc.payload := gen_payload(kh5,10); - cc.src_timestamp := gen_duration(11,0); + cc.src_timestamp := gen_duration(11 sec); - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 5, Writer 1, Aligned Payload] (REJECTED: MAX_INSTANCES exceeded)", INFO); + Log("R0: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 5, Writer 1, Aligned Payload]", INFO); + Log("R0: REJECTED [MAX_INSTANCES exceeded]", DEBUG); rtps := DEFAULT_RTPS_READER_TEST; rtps.opcode := ADD_CACHE_CHANGE; rtps.cc := cc; rtps.writer_pos := 1; rtps.ret_code := REJECTED; + -- READER 0 + ind <= 0; start_rtps; - wait_on_rtps; + wait_on_sig(rtps_done); wait_on_idle; - AffirmIf(status_id,(status and SAMPLE_REJECTED_STATUS) = SAMPLE_REJECTED_STATUS, "Expected: 1", "Received: 0"); + AffirmIf(status_id,(status(0) and SAMPLE_REJECTED_STATUS) = SAMPLE_REJECTED_STATUS, "Expected: 1", "Received: 0"); - Log("DDS Operation GET_SAMPLE_REJECTED_STATUS (Expected: Count 8, Change 2, Instance 5, REJECTED_BY_INSTANCES_LIMIT)", INFO); + Log("R0: DDS Operation GET_SAMPLE_REJECTED_STATUS", INFO); + Log("R0: Expected [Count 8, Change 2, Instance 5, REJECTED_BY_INSTANCES_LIMIT]", DEBUG); dds := DEFAULT_DDS_READER_TEST; dds.opcode := GET_SAMPLE_REJECTED_STATUS; dds.ret_code := RETCODE_OK; @@ -682,11 +736,13 @@ begin dds.change := 2; dds.inst := kh5; dds.last_reason:= REJECTED_BY_INSTANCES_LIMIT; + -- READER 0 + ind <= 0; start_dds; - wait_on_dds; + wait_on_sig(dds_done); wait_on_idle; - AffirmIf(status_id,(status and SAMPLE_REJECTED_STATUS) /= SAMPLE_REJECTED_STATUS, "Expected: 0", "Received: 1"); + AffirmIf(status_id,(status(0) and SAMPLE_REJECTED_STATUS) /= SAMPLE_REJECTED_STATUS, "Expected: 0", "Received: 1"); wait_on_completion; TranscriptOpen(RESULTS_FILE, APPEND_MODE); @@ -705,13 +761,6 @@ begin wait for 25 ns; end process; - alert_prc : process(all) - begin - if rising_edge(clk) then - -- TODO - end if; - end process; - dds_prc : process(all) variable col : COLLECTION_TYPE := DEFAULT_COLLECTION; begin @@ -725,13 +774,13 @@ begin dds_done <= '1'; end if; when START => - if (ack_dds = '1') then + if (ack_dds(ind) = '1') then dds_stage <= DONE; dds_cnt <= 0; end if; when DONE => - if (done_dds = '1') then - AffirmIfEqual(ret_id, return_code_dds, dds.ret_code); + if (done_dds(ind) = '1') then + AffirmIfEqual(ret_id, return_code_dds(ind), dds.ret_code); case (dds.ret_code) is when RETCODE_OK => case (dds.opcode) is @@ -739,7 +788,7 @@ begin dds_stage <= CHECK_SAMPLE_REJECT; dds_cnt <= 0; when others => - gen_collection(mem, col, dds, INSTANCE_PRESENTATION_QOS, FALSE); + gen_collection(mem(ind), col, dds, TEST_CONFIG(ind).PRESENTATION_QOS, TEST_CONFIG(ind).ORDERED_ACCESS); dds_stage <= CHECK_SI; dds_cnt <= 0; end case; @@ -748,19 +797,19 @@ begin end case; end if; when CHECK_SI => - if (si_valid = '1') then - AffirmIfEqual(sstate_id, si_sample_state, col.s(dds_cnt).sstate); - AffirmIfEqual(vstate_id, si_view_state, col.s(dds_cnt).vstate); - AffirmIfEqual(istate_id, si_instance_state, col.s(dds_cnt).istate); - AffirmIfEqual(ts_id, to_unsigned(si_source_timestamp), to_unsigned(col.s(dds_cnt).ts)); - AffirmIfEqual(inst_id, to_unsigned(si_instance_handle), to_unsigned(col.s(dds_cnt).inst)); - AffirmIfEqual(pub_id, to_unsigned(si_publication_handle), to_unsigned(HANDLE_NIL)); - AffirmIfEqual(dis_gen_cnt_id, si_disposed_generation_count, std_logic_vector(to_unsigned(col.s(dds_cnt).dis_gen_cnt,WORD_WIDTH))); - AffirmIfEqual(no_w_gen_cnt_id, si_no_writers_generation_count, std_logic_vector(to_unsigned(col.s(dds_cnt).no_w_gen_cnt,WORD_WIDTH))); - AffirmIfEqual(srank_id, si_sample_rank, std_logic_vector(to_unsigned(col.s(dds_cnt).srank,WORD_WIDTH))); - AffirmIfEqual(grank_id, si_generation_rank, std_logic_vector(to_unsigned(col.s(dds_cnt).grank,WORD_WIDTH))); - AffirmIfEqual(agrank_id, si_absolute_generation_rank, std_logic_vector(to_unsigned(col.s(dds_cnt).agrank,WORD_WIDTH))); - if (si_valid_data = '1') then + if (si_valid(ind) = '1') then + AffirmIfEqual(sstate_id, sample_info(ind).sample_state, col.s(dds_cnt).sstate); + AffirmIfEqual(vstate_id, sample_info(ind).view_state, col.s(dds_cnt).vstate); + AffirmIfEqual(istate_id, sample_info(ind).instance_state, col.s(dds_cnt).istate); + AffirmIfEqual(ts_id, to_unsigned(sample_info(ind).source_timestamp), to_unsigned(col.s(dds_cnt).ts)); + AffirmIfEqual(inst_id, to_unsigned(sample_info(ind).instance_handle), to_unsigned(col.s(dds_cnt).inst)); + AffirmIfEqual(pub_id, to_unsigned(sample_info(ind).publication_handle), to_unsigned(HANDLE_NIL)); + AffirmIfEqual(dis_gen_cnt_id, sample_info(ind).disposed_generation_count, std_logic_vector(to_unsigned(col.s(dds_cnt).dis_gen_cnt,WORD_WIDTH))); + AffirmIfEqual(no_w_gen_cnt_id, sample_info(ind).no_writers_generation_count, std_logic_vector(to_unsigned(col.s(dds_cnt).no_w_gen_cnt,WORD_WIDTH))); + AffirmIfEqual(srank_id, sample_info(ind).sample_rank, std_logic_vector(to_unsigned(col.s(dds_cnt).srank,WORD_WIDTH))); + AffirmIfEqual(grank_id, sample_info(ind).generation_rank, std_logic_vector(to_unsigned(col.s(dds_cnt).grank,WORD_WIDTH))); + AffirmIfEqual(agrank_id, sample_info(ind).absolute_generation_rank, std_logic_vector(to_unsigned(col.s(dds_cnt).agrank,WORD_WIDTH))); + if (sample_info(ind).valid_data = '1') then AffirmIf(valid_id, col.s(dds_cnt).data /= EMPTY_TEST_PACKET, "Sample with Data not expected"); dds_stage <= CHECK_DATA; dds_cnt2 <= 0; @@ -774,13 +823,13 @@ begin end if; end if; end if; - AffirmIf(eoc_id, eoc = '0', "EOC pulled high"); + AffirmIf(eoc_id, eoc(ind) = '0', "EOC pulled high"); when CHECK_DATA => - if (valid_out_dds = '1') then - AffirmIfEqual(data_id, data_out_dds, col.s(dds_cnt).data.data(dds_cnt2)); + if (valid_out_dds(ind) = '1') then + AffirmIfEqual(data_id, data_out_dds(ind), col.s(dds_cnt).data.data(dds_cnt2)); dds_cnt2 <= dds_cnt2 + 1; if (dds_cnt2 = col.s(dds_cnt).data.length-1) then - AlertIf(data_id, last_word_out_dds /= '1', "Last Word Signal not pulled High", ERROR); + AlertIf(data_id, last_word_out_dds(ind) /= '1', "Last Word Signal not pulled High", ERROR); if (dds_cnt = col.len-1) then -- DONE dds_stage <= WAIT_EOC; @@ -791,28 +840,28 @@ begin end if; end if; when WAIT_EOC => - if (eoc = '1') then + if (eoc(ind) = '1') then dds_stage <= IDLE; end if; when CHECK_SAMPLE_REJECT => - if (valid_out_dds = '1') then + if (valid_out_dds(ind) = '1') then dds_cnt <= dds_cnt + 1; case (dds_cnt) is when 0 => - AffirmIfEqual(data_id, data_out_dds, std_logic_vector(to_unsigned(dds.count,CDR_LONG_WIDTH))); + AffirmIfEqual(data_id, data_out_dds(ind), std_logic_vector(to_unsigned(dds.count,CDR_LONG_WIDTH))); when 1 => - AffirmIfEqual(data_id, data_out_dds, std_logic_vector(to_unsigned(dds.change,CDR_LONG_WIDTH))); + AffirmIfEqual(data_id, data_out_dds(ind), std_logic_vector(to_unsigned(dds.change,CDR_LONG_WIDTH))); when 2 => - AffirmIfEqual(data_id, data_out_dds, dds.last_reason); + AffirmIfEqual(data_id, data_out_dds(ind), dds.last_reason); when 3 => - AffirmIfEqual(data_id, data_out_dds, std_logic_vector(dds.inst(0))); + AffirmIfEqual(data_id, data_out_dds(ind), std_logic_vector(dds.inst(0))); when 4 => - AffirmIfEqual(data_id, data_out_dds, std_logic_vector(dds.inst(1))); + AffirmIfEqual(data_id, data_out_dds(ind), std_logic_vector(dds.inst(1))); when 5 => - AffirmIfEqual(data_id, data_out_dds, std_logic_vector(dds.inst(2))); + AffirmIfEqual(data_id, data_out_dds(ind), std_logic_vector(dds.inst(2))); when 6 => - AffirmIfEqual(data_id, data_out_dds, std_logic_vector(dds.inst(3))); - AlertIf(data_id, last_word_out_dds /= '1', "Last Word Signal not pulled High", ERROR); + AffirmIfEqual(data_id, data_out_dds(ind), std_logic_vector(dds.inst(3))); + AlertIf(data_id, last_word_out_dds(ind) /= '1', "Last Word Signal not pulled High", ERROR); dds_stage <= IDLE; when others => null; @@ -822,34 +871,34 @@ begin end if; -- DEFAULT - start_dds <= '0'; - opcode_dds <= NOP; - instance_state_dds <= ANY_INSTANCE_STATE; - view_state_dds <= ANY_VIEW_STATE; - sample_state_dds <= ANY_SAMPLE_STATE; - instance_handle_dds <= HANDLE_NIL; - max_samples_dds <= (others => '0'); - get_data_dds <= '0'; - ready_out_dds <= '0'; + start_dds <= (others => '0'); + opcode_dds <= (others => NOP); + instance_state_dds <= (others => ANY_INSTANCE_STATE); + view_state_dds <= (others => ANY_VIEW_STATE); + sample_state_dds <= (others => ANY_SAMPLE_STATE); + instance_handle_dds <= (others => HANDLE_NIL); + max_samples_dds <= (others => (others => '0')); + get_data_dds <= (others => '0'); + ready_out_dds <= (others => '0'); case (dds_stage ) is when START => - start_dds <= '1'; - opcode_dds <= dds.opcode; - instance_state_dds <= dds.istate; - view_state_dds <= dds.vstate; - sample_state_dds <= dds.sstate; - instance_handle_dds <= dds.inst; - max_samples_dds <= std_logic_vector(to_unsigned(dds.max_samples, WORD_WIDTH)); + start_dds(ind) <= '1'; + opcode_dds(ind) <= dds.opcode; + instance_state_dds(ind) <= dds.istate; + view_state_dds(ind) <= dds.vstate; + sample_state_dds(ind) <= dds.sstate; + instance_handle_dds(ind) <= dds.inst; + max_samples_dds(ind) <= std_logic_vector(to_unsigned(dds.max_samples, WORD_WIDTH)); when CHECK_SI => - if (si_valid = '1' and si_valid_data = '1') then - get_data_dds <= '1'; + if (si_valid(ind) = '1' and sample_info(ind).valid_data = '1') then + get_data_dds(ind) <= '1'; end if; when CHECK_DATA => - ready_out_dds <= '1'; + ready_out_dds(ind) <= '1'; when CHECK_SAMPLE_REJECT => - ready_out_dds <= '1'; + ready_out_dds(ind) <= '1'; when others => null; end case; @@ -868,7 +917,7 @@ begin rtps_done <= '1'; end if; when START => - if (ack_rtps = '1') then + if (ack_rtps(ind) = '1') then case (rtps.opcode) is when ADD_CACHE_CHANGE => gen_add_cache_change_dds(rtps.cc, rtps.lifespan, rtps.writer_pos, stimulus); @@ -878,41 +927,41 @@ begin end case; end if; when PUSH => - if (ready_in_rtps = '1') then + if (ready_in_rtps(ind) = '1') then rtps_cnt <= rtps_cnt + 1; if (rtps_cnt = stimulus.length-1) then rtps_stage <= DONE; end if; end if; when DONE => - if (done_rtps = '1') then - AffirmIfEqual(ret_id, HISTORY_CACHE_RESPONSE_TYPE'pos(ret_rtps), HISTORY_CACHE_RESPONSE_TYPE'pos(rtps.ret_code)); + if (done_rtps(ind) = '1') then + AffirmIfEqual(ret_id, HISTORY_CACHE_RESPONSE_TYPE'pos(ret_rtps(ind)), HISTORY_CACHE_RESPONSE_TYPE'pos(rtps.ret_code)); rtps_stage <= IDLE; end if; end case; end if; -- DEFAULT - start_rtps <= '0'; - opcode_rtps <= NOP; - valid_in_rtps <= '0'; - last_word_in_rtps <= '0'; - data_in_rtps <= (others => '0'); + start_rtps <= (others => '0'); + opcode_rtps <= (others => NOP); + valid_in_rtps <= (others => '0'); + last_word_in_rtps <= (others => '0'); + data_in_rtps <= (others => (others => '0')); case (rtps_stage) is when START => - start_rtps <= '1'; - opcode_rtps <= rtps.opcode; + start_rtps(ind) <= '1'; + opcode_rtps(ind) <= rtps.opcode; case (rtps.opcode) is when REMOVE_WRITER => - data_in_rtps <= std_logic_vector(to_unsigned(rtps.writer_pos,WORD_WIDTH)); + data_in_rtps(ind) <= std_logic_vector(to_unsigned(rtps.writer_pos,WORD_WIDTH)); when others => null; end case; when PUSH => - valid_in_rtps <= '1'; - data_in_rtps <= stimulus.data(rtps_cnt); - last_word_in_rtps <= stimulus.last(rtps_cnt); + valid_in_rtps(ind) <= '1'; + data_in_rtps(ind) <= stimulus.data(rtps_cnt); + last_word_in_rtps(ind) <= stimulus.last(rtps_cnt); when others => null; end case; diff --git a/src/Tests/Level_0/L0_dds_reader_test6_arzkriu.vhd b/src/Tests/Level_0/L0_dds_reader_test6.vhd similarity index 53% rename from src/Tests/Level_0/L0_dds_reader_test6_arzkriu.vhd rename to src/Tests/Level_0/L0_dds_reader_test6.vhd index 279b187..c643a71 100644 --- a/src/Tests/Level_0/L0_dds_reader_test6_arzkriu.vhd +++ b/src/Tests/Level_0/L0_dds_reader_test6.vhd @@ -12,53 +12,71 @@ use work.rtps_test_package.all; -- This testbench tests the Lifespan Handling of the DDS Reader. -entity L0_dds_reader_test6_arzkriu is +entity L0_dds_reader_test6 is end entity; -architecture testbench of L0_dds_reader_test6_arzkriu is +architecture testbench of L0_dds_reader_test6 is -- *CONSTANT DECLARATION* constant MAX_REMOTE_ENDPOINTS : natural := 3; + constant NUM_READERS : natural := 1; + + impure function gen_test_config return CONFIG_ARRAY_TYPE is + variable ret : CONFIG_ARRAY_TYPE(0 to NUM_READERS-1) := (others => DEFAULT_WRITER_CONFIG); + begin + -- arzkriu + ret(0).TIME_BASED_FILTER_QOS := DURATION_ZERO; + ret(0).DEADLINE_QOS := DURATION_INFINITE; + ret(0).MAX_SAMPLES := std_logic_vector(to_unsigned(2,CDR_LONG_WIDTH)); + ret(0).MAX_INSTANCES := std_logic_vector(to_unsigned(3,CDR_LONG_WIDTH)); + ret(0).MAX_SAMPLES_PER_INSTANCE := std_logic_vector(to_unsigned(1,CDR_LONG_WIDTH)); + ret(0).HISTORY_QOS := KEEP_ALL_HISTORY_QOS; + ret(0).RELIABILITY_QOS := RELIABLE_RELIABILITY_QOS; + ret(0).PRESENTATION_QOS := INSTANCE_PRESENTATION_QOS; + ret(0).DESTINATION_ORDER_QOS := BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS; + ret(0).COHERENT_ACCESS := FALSE; + ret(0).ORDERED_ACCESS := FALSE; + ret(0).WITH_KEY := TRUE; + ret(0).MAX_PAYLOAD_SIZE := 40; + return ret; + end function; + constant TEST_CONFIG : CONFIG_ARRAY_TYPE := gen_test_config; -- *TYPE DECLARATION* - type DDS_STAGE_TYPE is (IDLE, START, DONE, CHECK_SI, CHECK_DATA, WAIT_EOC, CHECK_SAMPLE_REJECT); + type DDS_STAGE_TYPE is (IDLE, START, DONE, CHECK_SI, CHECK_DATA, WAIT_EOC); type RTPS_STAGE_TYPE is (IDLE, START, PUSH, DONE); + type DDS_READER_MEM_ARRAY_TYPE is array (0 to NUM_READERS-1) of DDS_READER_MEM_TYPE; -- *SIGNAL DECLARATION* signal clk : std_logic := '0'; signal reset : std_logic := '1'; signal check_time : TIME_TYPE := TIME_ZERO; - signal start_rtps, start_dds, ack_rtps, ack_dds, done_rtps, done_dds : std_logic := '0'; - signal opcode_rtps : HISTORY_CACHE_OPCODE_TYPE := NOP; - signal opcode_dds : DDS_READER_OPCODE_TYPE := NOP; - signal ret_rtps : HISTORY_CACHE_RESPONSE_TYPE := ERROR; - signal ready_in_rtps, valid_in_rtps, last_word_in_rtps : std_logic := '0'; - signal ready_out_dds, valid_out_dds, last_word_out_dds : std_logic := '0'; - signal data_in_rtps, data_out_dds : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); - signal get_data_dds, si_valid_data, si_valid, eoc : std_logic := '0'; - signal return_code_dds : std_logic_vector(RETURN_CODE_WIDTH-1 downto 0) := (others => '0'); - signal status : std_logic_vector(STATUS_KIND_WIDTH-1 downto 0) := (others => '0'); - signal instance_state_dds, si_instance_state : std_logic_vector(INSTANCE_STATE_KIND_WIDTH-1 downto 0) := ANY_INSTANCE_STATE; - signal view_state_dds, si_view_state : std_logic_vector(VIEW_STATE_KIND_WIDTH-1 downto 0) := ANY_VIEW_STATE; - signal sample_state_dds, si_sample_state : std_logic_vector(SAMPLE_STATE_KIND_WIDTH-1 downto 0) := ANY_SAMPLE_STATE; - signal instance_handle_dds, si_instance_handle : INSTANCE_HANDLE_TYPE := HANDLE_NIL; - signal max_samples_dds : std_logic_vector(MAX_SAMPLES_WIDTH-1 downto 0) := (others => '0'); - signal si_source_timestamp : TIME_TYPE := TIME_INVALID; - signal si_publication_handle : INSTANCE_HANDLE_TYPE := HANDLE_NIL; - signal si_disposed_generation_count : std_logic_vector(DISPOSED_GENERATION_COUNT_WIDTH-1 downto 0) := (others => '0'); - signal si_no_writers_generation_count : std_logic_vector(NO_WRITERS_GENERATION_COUNT_WIDTH-1 downto 0) := (others => '0'); - signal si_sample_rank : std_logic_vector(SAMPLE_RANK_WIDTH-1 downto 0) := (others => '0'); - signal si_generation_rank : std_logic_vector(GENERATION_RANK_WIDTH-1 downto 0) := (others => '0'); - signal si_absolute_generation_rank: std_logic_vector(ABSOLUTE_GENERATION_COUNT_WIDTH-1 downto 0) := (others => '0'); + signal start_rtps, start_dds, ack_rtps, ack_dds, done_rtps, done_dds : std_logic_vector(0 to NUM_READERS-1) := (others => '0'); + signal opcode_rtps : HISTORY_CACHE_OPCODE_ARRAY_TYPE(0 to NUM_READERS-1) := (others => NOP); + signal opcode_dds : DDS_READER_OPCODE_ARRAY_TYPE(0 to NUM_READERS-1) := (others => NOP); + signal ret_rtps : HISTORY_CACHE_RESPONSE_ARRAY_TYPE(0 to NUM_READERS-1) := (others => ERROR); + signal ready_in_rtps, valid_in_rtps, last_word_in_rtps : std_logic_vector(0 to NUM_READERS-1) := (others => '0'); + signal ready_out_dds, valid_out_dds, last_word_out_dds : std_logic_vector(0 to NUM_READERS-1) := (others => '0'); + signal data_in_rtps, data_out_dds : WORD_ARRAY_TYPE(0 to NUM_READERS-1) := (others => (others => '0')); + signal get_data_dds, si_valid, eoc : std_logic_vector(0 to NUM_READERS-1) := (others => '0'); + signal return_code_dds : RETURN_CODE_ARRAY_TYPE(0 to NUM_READERS-1) := (others => (others => '0')); + signal status : STATUS_KIND_ARRAY_TYPE(0 to NUM_READERS-1) := (others => (others => '0')); + signal instance_state_dds : INSTANCE_STATE_ARRAY_TYPE(0 to NUM_READERS-1) := (others => ANY_INSTANCE_STATE); + signal view_state_dds : VIEW_STATE_ARRAY_TYPE(0 to NUM_READERS-1) := (others => ANY_VIEW_STATE); + signal sample_state_dds : SAMPLE_STATE_ARRAY_TYPE(0 to NUM_READERS-1) := (others => ANY_SAMPLE_STATE); + signal instance_handle_dds : INSTANCE_HANDLE_ARRAY_TYPE(0 to NUM_READERS-1) := (others => HANDLE_NIL); + signal max_samples_dds : MAX_SAMPLES_ARRAY_TYPE(0 to NUM_READERS-1) := (others => (others => '0')); + signal sample_info : SAMPLE_INFO_ARRAY_TYPE(0 to NUM_READERS-1); + signal ind : natural := 0; signal dds_start , dds_done , rtps_start, rtps_done : std_logic := '0'; signal dds_cnt, dds_cnt2, rtps_cnt : natural := 0; signal dds_stage : DDS_STAGE_TYPE := IDLE; signal rtps_stage : RTPS_STAGE_TYPE := IDLE; shared variable dds : DDS_READER_TEST_TYPE := DEFAULT_DDS_READER_TEST; shared variable rtps : RTPS_READER_TEST_TYPE := DEFAULT_RTPS_READER_TEST; - shared variable mem : DDS_READER_MEM_TYPE := DEFAULT_DDS_READER_MEM; + shared variable mem : DDS_READER_MEM_ARRAY_TYPE := (others => DEFAULT_DDS_READER_MEM); signal data_id, ret_id, sstate_id, vstate_id, istate_id, inst_id, ts_id, pub_id, dis_gen_cnt_id, no_w_gen_cnt_id, srank_id, grank_id, agrank_id, eoc_id, valid_id, status_id : AlertLogIDType; -- *FUNCTION DECLARATION* @@ -80,70 +98,55 @@ architecture testbench of L0_dds_reader_test6_arzkriu is return ret; end function; + procedure wait_on_sig(signal sig : std_logic) is + begin + if (sig /= '1') then + wait on sig until sig = '1'; + end if; + end procedure; + begin -- Unit Under Test uut : entity work.dds_reader(arch) generic map ( - TIME_BASED_FILTER_QOS => DURATION_ZERO, - DEADLINE_QOS => DURATION_INFINITE, - MAX_SAMPLES => std_logic_vector(to_unsigned(2,CDR_LONG_WIDTH)), - MAX_INSTANCES => std_logic_vector(to_unsigned(3,CDR_LONG_WIDTH)), - MAX_SAMPLES_PER_INSTANCE => std_logic_vector(to_unsigned(1,CDR_LONG_WIDTH)), - HISTORY_QOS => KEEP_ALL_HISTORY_QOS, - RELIABILITY_QOS => RELIABLE_RELIABILITY_QOS, - PRESENTATION_QOS => INSTANCE_PRESENTATION_QOS, - DESTINATION_ORDER_QOS => BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS, - COHERENT_ACCESS => FALSE, - ORDERED_ACCESS => FALSE, - WITH_KEY => TRUE, - PAYLOAD_FRAME_SIZE => 11, - MAX_REMOTE_ENDPOINTS => MAX_REMOTE_ENDPOINTS + NUM_READERS => NUM_READERS, + CONFIG_ARRAY => to_QUARTUS_CONFIG_ARRAY_TYPE(TEST_CONFIG), + MAX_REMOTE_ENDPOINTS => MAX_REMOTE_ENDPOINTS ) port map ( - clk => clk, - reset => reset, - time => check_time, - start_rtps => start_rtps, - opcode_rtps => opcode_rtps, - ack_rtps => ack_rtps, - done_rtps => done_rtps, - ret_rtps => ret_rtps, - data_in_rtps => data_in_rtps, - valid_in_rtps => valid_in_rtps, - ready_in_rtps => ready_in_rtps, - last_word_in_rtps => last_word_in_rtps, - start_dds => start_dds, - ack_dds => ack_dds, - opcode_dds => opcode_dds, - instance_state_dds => instance_state_dds, - view_state_dds => view_state_dds, - sample_state_dds => sample_state_dds, - instance_handle_dds => instance_handle_dds, - max_samples_dds => max_samples_dds, - get_data_dds => get_data_dds, - done_dds => done_dds, - return_code_dds => return_code_dds, - ready_out_dds => ready_out_dds, - valid_out_dds => valid_out_dds, - data_out_dds => data_out_dds, - last_word_out_dds => last_word_out_dds, - sample_info.sample_state => si_sample_state, - sample_info.view_state => si_view_state, - sample_info.instance_state => si_instance_state, - sample_info.source_timestamp => si_source_timestamp, - sample_info.instance_handle => si_instance_handle, - sample_info.publication_handle => si_publication_handle, - sample_info.disposed_generation_count => si_disposed_generation_count, - sample_info.no_writers_generation_count => si_no_writers_generation_count, - sample_info.sample_rank => si_sample_rank, - sample_info.generation_rank => si_generation_rank, - sample_info.absolute_generation_rank => si_absolute_generation_rank, - sample_info.valid_data => si_valid_data, - sample_info_valid => si_valid, - sample_info_ack => '1', - eoc => eoc, - status => status + clk => clk, + reset => reset, + time => check_time, + start_rtps => start_rtps, + opcode_rtps => opcode_rtps, + ack_rtps => ack_rtps, + done_rtps => done_rtps, + ret_rtps => ret_rtps, + data_in_rtps => data_in_rtps, + valid_in_rtps => valid_in_rtps, + ready_in_rtps => ready_in_rtps, + last_word_in_rtps => last_word_in_rtps, + start_dds => start_dds, + ack_dds => ack_dds, + opcode_dds => opcode_dds, + instance_state_dds => instance_state_dds, + view_state_dds => view_state_dds, + sample_state_dds => sample_state_dds, + instance_handle_dds => instance_handle_dds, + max_samples_dds => max_samples_dds, + get_data_dds => get_data_dds, + done_dds => done_dds, + return_code_dds => return_code_dds, + ready_out_dds => ready_out_dds, + valid_out_dds => valid_out_dds, + data_out_dds => data_out_dds, + last_word_out_dds => last_word_out_dds, + sample_info => sample_info, + sample_info_valid => si_valid, + sample_info_ack => (others => '1'), + eoc => eoc, + status => status ); stimulus_prc : process @@ -198,20 +201,6 @@ begin wait until rising_edge(clk); end procedure; - procedure wait_on_dds is - begin - if (dds_done /= '1') then - wait until dds_done = '1'; - end if; - end procedure; - - procedure wait_on_rtps is - begin - if (rtps_done /= '1') then - wait until rtps_done = '1'; - end if; - end procedure; - procedure wait_on_completion is begin if (rtps_done /= '1' or dds_done /= '1') then @@ -238,7 +227,7 @@ begin begin - SetAlertLogName("L0_dds_reader_test6_arzkriu - (KEEP ALL, Reliable, Zero TIME_BASED_FILTER, Keyed, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER, ACCESS SCOPE Instance, Unordered) - Sample Rejected Status Handling"); + SetAlertLogName("L0_dds_reader_test6 - Sample Rejected Status Handling"); SetAlertEnable(FAILURE, TRUE); SetAlertEnable(ERROR, TRUE); SetAlertEnable(WARNING, TRUE); @@ -279,6 +268,7 @@ begin wait until rising_edge(clk); wait until rising_edge(clk); reset <= '0'; + wait_on_idle; -- MEM: - -- ISTATE: - -- WRITER: - @@ -288,19 +278,22 @@ begin cc.kind := ALIVE; cc.instance := kh1; cc.payload := gen_payload(kh1,10); - cc.src_timestamp := gen_duration(1,0); + cc.src_timestamp := gen_duration(1 sec); - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Aligned Payload] (ACCEPTED)", INFO); + Log("R0: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Aligned Payload]", INFO); + Log("R0: ACCEPTED", DEBUG); rtps := DEFAULT_RTPS_READER_TEST; rtps.opcode := ADD_CACHE_CHANGE; rtps.cc := cc; rtps.writer_pos := 0; - rtps.lifespan := gen_duration(2,0); + rtps.lifespan := gen_duration(2 sec); rtps.ret_code := OK; s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(0), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + -- READER 0 + ind <= 0; start_rtps; - wait_on_rtps; + wait_on_sig(rtps_done); wait_on_idle; -- MEM: I1S1 -- ISTATE: I1:ALIVE @@ -311,26 +304,29 @@ begin cc.kind := ALIVE; cc.instance := kh2; cc.payload := gen_payload(kh2,10); - cc.src_timestamp := gen_duration(2,0); + cc.src_timestamp := gen_duration(2 sec); - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 2, Writer 1, Aligned Payload] (ACCEPTED)", INFO); + Log("R0: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 2, Writer 1, Aligned Payload]", INFO); + Log("R0: ACCEPTED", DEBUG); rtps := DEFAULT_RTPS_READER_TEST; rtps.opcode := ADD_CACHE_CHANGE; rtps.cc := cc; rtps.writer_pos := 1; - rtps.lifespan := gen_duration(3,0); + rtps.lifespan := gen_duration(3 sec); rtps.ret_code := OK; s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(0), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + -- READER 0 + ind <= 0; start_rtps; - wait_on_rtps; + wait_on_sig(rtps_done); wait_on_idle; -- MEM: I1S1, I2S1 -- ISTATE: I1:ALIVE, I2:ALIVE -- WRITER: W0:I1, W1:I2 Log("Current Time: 1s", INFO); - check_time <= gen_duration(1,0); + check_time <= gen_duration(1 sec); wait until rising_edge(clk); wait until rising_edge(clk); wait_on_idle; @@ -340,24 +336,27 @@ begin cc.kind := ALIVE; cc.instance := kh3; cc.payload := gen_payload(kh3,10); - cc.src_timestamp := gen_duration(3,0); + cc.src_timestamp := gen_duration(3 sec); - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 3, Writer 2, Aligned Payload] (REJECTED: MAX_SAMPLES exceeded)", INFO); + Log("R0: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 3, Writer 2, Aligned Payload]", INFO); + Log("R0: REJECTED [MAX_SAMPLES exceeded]", DEBUG); rtps := DEFAULT_RTPS_READER_TEST; rtps.opcode := ADD_CACHE_CHANGE; rtps.cc := cc; rtps.writer_pos := 2; - rtps.lifespan := gen_duration(1,0); + rtps.lifespan := gen_duration(1 sec); rtps.ret_code := REJECTED; + -- READER 0 + ind <= 0; start_rtps; - wait_on_rtps; + wait_on_sig(rtps_done); wait_on_idle; -- MEM: I1S1, I2S1 -- ISTATE: I1:ALIVE, I2:ALIVE -- WRITER: W0:I1, W1:I2 Log("Current Time: 2s", INFO); - check_time <= gen_duration(2,0); + check_time <= gen_duration(2 sec); wait until rising_edge(clk); wait until rising_edge(clk); wait_on_idle; @@ -367,19 +366,22 @@ begin cc.kind := ALIVE; cc.instance := kh3; cc.payload := gen_payload(kh3,10); - cc.src_timestamp := gen_duration(4,0); + cc.src_timestamp := gen_duration(4 sec); - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 3, Writer 2, Aligned Payload] (ACCEPTED)", INFO); + Log("R0: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 3, Writer 2, Aligned Payload]", INFO); + Log("R0: ACCEPTED", DEBUG); rtps := DEFAULT_RTPS_READER_TEST; rtps.opcode := ADD_CACHE_CHANGE; rtps.cc := cc; rtps.writer_pos := 2; - rtps.lifespan := gen_duration(1,0); + rtps.lifespan := gen_duration(1 sec); rtps.ret_code := OK; s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(0), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + -- READER 0 + ind <= 0; start_rtps; - wait_on_rtps; + wait_on_sig(rtps_done); wait_on_idle; -- MEM: I2S1, I3S1 -- ISTATE: I1:ALIVE, I2:ALIVE, I3:ALIVE @@ -390,24 +392,27 @@ begin cc.kind := ALIVE; cc.instance := kh1; cc.payload := gen_payload(kh1,10); - cc.src_timestamp := gen_duration(5,0); + cc.src_timestamp := gen_duration(5 sec); - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Aligned Payload] (REJECTED: MAX_SAMPLES exceeded)", INFO); + Log("R0: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Aligned Payload]", INFO); + Log("R0: REJECTED [MAX_SAMPLES exceeded]", DEBUG); rtps := DEFAULT_RTPS_READER_TEST; rtps.opcode := ADD_CACHE_CHANGE; rtps.cc := cc; rtps.writer_pos := 0; - rtps.lifespan := gen_duration(1,0); + rtps.lifespan := gen_duration(1 sec); rtps.ret_code := REJECTED; + -- READER 0 + ind <= 0; start_rtps; - wait_on_rtps; + wait_on_sig(rtps_done); wait_on_idle; -- MEM: I2S1, I3S1 -- ISTATE: I1:ALIVE, I2:ALIVE, I3:ALIVE -- WRITER: W0:I1, W1:I2, W2:I3 Log("Current Time: 3s", INFO); - check_time <= gen_duration(3,0); + check_time <= gen_duration(3 sec); wait until rising_edge(clk); wait until rising_edge(clk); wait_on_idle; @@ -417,19 +422,22 @@ begin cc.kind := ALIVE; cc.instance := kh1; cc.payload := gen_payload(kh1,10); - cc.src_timestamp := gen_duration(6,0); + cc.src_timestamp := gen_duration(6 sec); - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Aligned Payload] (ACCEPTED)", INFO); + Log("R0: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Aligned Payload]", INFO); + Log("R0: ACCEPTED", DEBUG); rtps := DEFAULT_RTPS_READER_TEST; rtps.opcode := ADD_CACHE_CHANGE; rtps.cc := cc; rtps.writer_pos := 0; - rtps.lifespan := gen_duration(2,0); + rtps.lifespan := gen_duration(2 sec); rtps.ret_code := OK; s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(0), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + -- READER 0 + ind <= 0; start_rtps; - wait_on_rtps; + wait_on_sig(rtps_done); wait_on_idle; -- MEM: I1S2, 0 -- ISTATE: I1:ALIVE, I2:ALIVE, I3:ALIVE @@ -440,19 +448,22 @@ begin cc.kind := ALIVE; cc.instance := kh3; cc.payload := gen_payload(kh3,10); - cc.src_timestamp := gen_duration(7,0); + cc.src_timestamp := gen_duration(7 sec); - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 3, Writer 2, Aligned Payload] (ACCEPTED)", INFO); + Log("R0: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 3, Writer 2, Aligned Payload]", INFO); + Log("R0: ACCEPTED", DEBUG); rtps := DEFAULT_RTPS_READER_TEST; rtps.opcode := ADD_CACHE_CHANGE; rtps.cc := cc; rtps.writer_pos := 2; - rtps.lifespan := gen_duration(1,0); + rtps.lifespan := gen_duration(1 sec); rtps.ret_code := OK; s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(0), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + -- READER 0 + ind <= 0; start_rtps; - wait_on_rtps; + wait_on_sig(rtps_done); wait_on_idle; -- MEM: I1S2, I3S2 -- ISTATE: I1:ALIVE, I2:ALIVE, I3:ALIVE @@ -475,13 +486,6 @@ begin wait for 25 ns; end process; - alert_prc : process(all) - begin - if rising_edge(clk) then - -- TODO - end if; - end process; - dds_prc : process(all) variable col : COLLECTION_TYPE := DEFAULT_COLLECTION; begin @@ -495,42 +499,36 @@ begin dds_done <= '1'; end if; when START => - if (ack_dds = '1') then + if (ack_dds(ind) = '1') then dds_stage <= DONE; dds_cnt <= 0; end if; when DONE => - if (done_dds = '1') then - AffirmIfEqual(ret_id, return_code_dds, dds.ret_code); + if (done_dds(ind) = '1') then + AffirmIfEqual(ret_id, return_code_dds(ind), dds.ret_code); case (dds.ret_code) is when RETCODE_OK => - case (dds.opcode) is - when GET_SAMPLE_REJECTED_STATUS => - dds_stage <= CHECK_SAMPLE_REJECT; - dds_cnt <= 0; - when others => - gen_collection(mem, col, dds, INSTANCE_PRESENTATION_QOS, FALSE); - dds_stage <= CHECK_SI; - dds_cnt <= 0; - end case; + gen_collection(mem(ind), col, dds, TEST_CONFIG(ind).PRESENTATION_QOS, TEST_CONFIG(ind).ORDERED_ACCESS); + dds_stage <= CHECK_SI; + dds_cnt <= 0; when others => dds_stage <= IDLE; end case; end if; when CHECK_SI => - if (si_valid = '1') then - AffirmIfEqual(sstate_id, si_sample_state, col.s(dds_cnt).sstate); - AffirmIfEqual(vstate_id, si_view_state, col.s(dds_cnt).vstate); - AffirmIfEqual(istate_id, si_instance_state, col.s(dds_cnt).istate); - AffirmIfEqual(ts_id, to_unsigned(si_source_timestamp), to_unsigned(col.s(dds_cnt).ts)); - AffirmIfEqual(inst_id, to_unsigned(si_instance_handle), to_unsigned(col.s(dds_cnt).inst)); - AffirmIfEqual(pub_id, to_unsigned(si_publication_handle), to_unsigned(HANDLE_NIL)); - AffirmIfEqual(dis_gen_cnt_id, si_disposed_generation_count, std_logic_vector(to_unsigned(col.s(dds_cnt).dis_gen_cnt,WORD_WIDTH))); - AffirmIfEqual(no_w_gen_cnt_id, si_no_writers_generation_count, std_logic_vector(to_unsigned(col.s(dds_cnt).no_w_gen_cnt,WORD_WIDTH))); - AffirmIfEqual(srank_id, si_sample_rank, std_logic_vector(to_unsigned(col.s(dds_cnt).srank,WORD_WIDTH))); - AffirmIfEqual(grank_id, si_generation_rank, std_logic_vector(to_unsigned(col.s(dds_cnt).grank,WORD_WIDTH))); - AffirmIfEqual(agrank_id, si_absolute_generation_rank, std_logic_vector(to_unsigned(col.s(dds_cnt).agrank,WORD_WIDTH))); - if (si_valid_data = '1') then + if (si_valid(ind) = '1') then + AffirmIfEqual(sstate_id, sample_info(ind).sample_state, col.s(dds_cnt).sstate); + AffirmIfEqual(vstate_id, sample_info(ind).view_state, col.s(dds_cnt).vstate); + AffirmIfEqual(istate_id, sample_info(ind).instance_state, col.s(dds_cnt).istate); + AffirmIfEqual(ts_id, to_unsigned(sample_info(ind).source_timestamp), to_unsigned(col.s(dds_cnt).ts)); + AffirmIfEqual(inst_id, to_unsigned(sample_info(ind).instance_handle), to_unsigned(col.s(dds_cnt).inst)); + AffirmIfEqual(pub_id, to_unsigned(sample_info(ind).publication_handle), to_unsigned(HANDLE_NIL)); + AffirmIfEqual(dis_gen_cnt_id, sample_info(ind).disposed_generation_count, std_logic_vector(to_unsigned(col.s(dds_cnt).dis_gen_cnt,WORD_WIDTH))); + AffirmIfEqual(no_w_gen_cnt_id, sample_info(ind).no_writers_generation_count, std_logic_vector(to_unsigned(col.s(dds_cnt).no_w_gen_cnt,WORD_WIDTH))); + AffirmIfEqual(srank_id, sample_info(ind).sample_rank, std_logic_vector(to_unsigned(col.s(dds_cnt).srank,WORD_WIDTH))); + AffirmIfEqual(grank_id, sample_info(ind).generation_rank, std_logic_vector(to_unsigned(col.s(dds_cnt).grank,WORD_WIDTH))); + AffirmIfEqual(agrank_id, sample_info(ind).absolute_generation_rank, std_logic_vector(to_unsigned(col.s(dds_cnt).agrank,WORD_WIDTH))); + if (sample_info(ind).valid_data = '1') then AffirmIf(valid_id, col.s(dds_cnt).data /= EMPTY_TEST_PACKET, "Sample with Data not expected"); dds_stage <= CHECK_DATA; dds_cnt2 <= 0; @@ -544,13 +542,13 @@ begin end if; end if; end if; - AffirmIf(eoc_id, eoc = '0', "EOC pulled high"); + AffirmIf(eoc_id, eoc(ind) = '0', "EOC pulled high"); when CHECK_DATA => - if (valid_out_dds = '1') then - AffirmIfEqual(data_id, data_out_dds, col.s(dds_cnt).data.data(dds_cnt2)); + if (valid_out_dds(ind) = '1') then + AffirmIfEqual(data_id, data_out_dds(ind), col.s(dds_cnt).data.data(dds_cnt2)); dds_cnt2 <= dds_cnt2 + 1; if (dds_cnt2 = col.s(dds_cnt).data.length-1) then - AlertIf(data_id, last_word_out_dds /= '1', "Last Word Signal not pulled High", ERROR); + AlertIf(data_id, last_word_out_dds(ind) /= '1', "Last Word Signal not pulled High", ERROR); if (dds_cnt = col.len-1) then -- DONE dds_stage <= WAIT_EOC; @@ -561,65 +559,39 @@ begin end if; end if; when WAIT_EOC => - if (eoc = '1') then + if (eoc(ind) = '1') then dds_stage <= IDLE; end if; - when CHECK_SAMPLE_REJECT => - if (valid_out_dds = '1') then - dds_cnt <= dds_cnt + 1; - case (dds_cnt) is - when 0 => - AffirmIfEqual(data_id, data_out_dds, std_logic_vector(to_unsigned(dds.count,CDR_LONG_WIDTH))); - when 1 => - AffirmIfEqual(data_id, data_out_dds, std_logic_vector(to_unsigned(dds.change,CDR_LONG_WIDTH))); - when 2 => - AffirmIfEqual(data_id, data_out_dds, dds.last_reason); - when 3 => - AffirmIfEqual(data_id, data_out_dds, std_logic_vector(dds.inst(0))); - when 4 => - AffirmIfEqual(data_id, data_out_dds, std_logic_vector(dds.inst(1))); - when 5 => - AffirmIfEqual(data_id, data_out_dds, std_logic_vector(dds.inst(2))); - when 6 => - AffirmIfEqual(data_id, data_out_dds, std_logic_vector(dds.inst(3))); - AlertIf(data_id, last_word_out_dds /= '1', "Last Word Signal not pulled High", ERROR); - dds_stage <= IDLE; - when others => - null; - end case; - end if; end case; end if; -- DEFAULT - start_dds <= '0'; - opcode_dds <= NOP; - instance_state_dds <= ANY_INSTANCE_STATE; - view_state_dds <= ANY_VIEW_STATE; - sample_state_dds <= ANY_SAMPLE_STATE; - instance_handle_dds <= HANDLE_NIL; - max_samples_dds <= (others => '0'); - get_data_dds <= '0'; - ready_out_dds <= '0'; + start_dds <= (others => '0'); + opcode_dds <= (others => NOP); + instance_state_dds <= (others => ANY_INSTANCE_STATE); + view_state_dds <= (others => ANY_VIEW_STATE); + sample_state_dds <= (others => ANY_SAMPLE_STATE); + instance_handle_dds <= (others => HANDLE_NIL); + max_samples_dds <= (others => (others => '0')); + get_data_dds <= (others => '0'); + ready_out_dds <= (others => '0'); case (dds_stage ) is when START => - start_dds <= '1'; - opcode_dds <= dds.opcode; - instance_state_dds <= dds.istate; - view_state_dds <= dds.vstate; - sample_state_dds <= dds.sstate; - instance_handle_dds <= dds.inst; - max_samples_dds <= std_logic_vector(to_unsigned(dds.max_samples, WORD_WIDTH)); + start_dds(ind) <= '1'; + opcode_dds(ind) <= dds.opcode; + instance_state_dds(ind) <= dds.istate; + view_state_dds(ind) <= dds.vstate; + sample_state_dds(ind) <= dds.sstate; + instance_handle_dds(ind) <= dds.inst; + max_samples_dds(ind) <= std_logic_vector(to_unsigned(dds.max_samples, WORD_WIDTH)); when CHECK_SI => - if (si_valid = '1' and si_valid_data = '1') then - get_data_dds <= '1'; + if (si_valid(ind) = '1' and sample_info(ind).valid_data = '1') then + get_data_dds(ind) <= '1'; end if; when CHECK_DATA => - ready_out_dds <= '1'; - when CHECK_SAMPLE_REJECT => - ready_out_dds <= '1'; + ready_out_dds(ind) <= '1'; when others => null; end case; @@ -638,7 +610,7 @@ begin rtps_done <= '1'; end if; when START => - if (ack_rtps = '1') then + if (ack_rtps(ind) = '1') then case (rtps.opcode) is when ADD_CACHE_CHANGE => gen_add_cache_change_dds(rtps.cc, rtps.lifespan, rtps.writer_pos, stimulus); @@ -648,41 +620,41 @@ begin end case; end if; when PUSH => - if (ready_in_rtps = '1') then + if (ready_in_rtps(ind) = '1') then rtps_cnt <= rtps_cnt + 1; if (rtps_cnt = stimulus.length-1) then rtps_stage <= DONE; end if; end if; when DONE => - if (done_rtps = '1') then - AffirmIfEqual(ret_id, HISTORY_CACHE_RESPONSE_TYPE'pos(ret_rtps), HISTORY_CACHE_RESPONSE_TYPE'pos(rtps.ret_code)); + if (done_rtps(ind) = '1') then + AffirmIfEqual(ret_id, HISTORY_CACHE_RESPONSE_TYPE'pos(ret_rtps(ind)), HISTORY_CACHE_RESPONSE_TYPE'pos(rtps.ret_code)); rtps_stage <= IDLE; end if; end case; end if; -- DEFAULT - start_rtps <= '0'; - opcode_rtps <= NOP; - valid_in_rtps <= '0'; - last_word_in_rtps <= '0'; - data_in_rtps <= (others => '0'); + start_rtps <= (others => '0'); + opcode_rtps <= (others => NOP); + valid_in_rtps <= (others => '0'); + last_word_in_rtps <= (others => '0'); + data_in_rtps <= (others => (others => '0')); case (rtps_stage) is when START => - start_rtps <= '1'; - opcode_rtps <= rtps.opcode; + start_rtps(ind) <= '1'; + opcode_rtps(ind) <= rtps.opcode; case (rtps.opcode) is when REMOVE_WRITER => - data_in_rtps <= std_logic_vector(to_unsigned(rtps.writer_pos,WORD_WIDTH)); + data_in_rtps(ind) <= std_logic_vector(to_unsigned(rtps.writer_pos,WORD_WIDTH)); when others => null; end case; when PUSH => - valid_in_rtps <= '1'; - data_in_rtps <= stimulus.data(rtps_cnt); - last_word_in_rtps <= stimulus.last(rtps_cnt); + valid_in_rtps(ind) <= '1'; + data_in_rtps(ind) <= stimulus.data(rtps_cnt); + last_word_in_rtps(ind) <= stimulus.last(rtps_cnt); when others => null; end case; diff --git a/src/Tests/Level_0/L0_dds_reader_test2_arpkriu.vhd b/src/Tests/Level_0/L0_dds_reader_test7.vhd similarity index 50% rename from src/Tests/Level_0/L0_dds_reader_test2_arpkriu.vhd rename to src/Tests/Level_0/L0_dds_reader_test7.vhd index 0ffa520..da555ec 100644 --- a/src/Tests/Level_0/L0_dds_reader_test2_arpkriu.vhd +++ b/src/Tests/Level_0/L0_dds_reader_test7.vhd @@ -10,56 +10,74 @@ use work.user_config.all; use work.rtps_config_package.all; use work.rtps_test_package.all; --- This testbench tests the handling of the TIME_BASED_FILTER QoS of the DDS Reader. +-- This testbench tests the bitmap writer handling (bitmap conversion to/from memory) -entity L0_dds_reader_test2_arpkriu is +entity L0_dds_reader_test7 is end entity; -architecture testbench of L0_dds_reader_test2_arpkriu is +architecture testbench of L0_dds_reader_test7 is -- *CONSTANT DECLARATION* - constant MAX_REMOTE_ENDPOINTS : natural := 3; + constant MAX_REMOTE_ENDPOINTS : natural := 33; + constant NUM_READERS : natural := 1; + + impure function gen_test_config return CONFIG_ARRAY_TYPE is + variable ret : CONFIG_ARRAY_TYPE(0 to NUM_READERS-1) := (others => DEFAULT_WRITER_CONFIG); + begin + -- arzkriu + ret(0).TIME_BASED_FILTER_QOS := DURATION_ZERO; + ret(0).DEADLINE_QOS := DURATION_INFINITE; + ret(0).MAX_SAMPLES := std_logic_vector(to_unsigned(4,CDR_LONG_WIDTH)); + ret(0).MAX_INSTANCES := std_logic_vector(to_unsigned(3,CDR_LONG_WIDTH)); + ret(0).MAX_SAMPLES_PER_INSTANCE := std_logic_vector(to_unsigned(4,CDR_LONG_WIDTH)); + ret(0).HISTORY_QOS := KEEP_ALL_HISTORY_QOS; + ret(0).RELIABILITY_QOS := RELIABLE_RELIABILITY_QOS; + ret(0).PRESENTATION_QOS := INSTANCE_PRESENTATION_QOS; + ret(0).DESTINATION_ORDER_QOS := BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS; + ret(0).COHERENT_ACCESS := FALSE; + ret(0).ORDERED_ACCESS := FALSE; + ret(0).WITH_KEY := TRUE; + ret(0).MAX_PAYLOAD_SIZE := 40; + return ret; + end function; + constant TEST_CONFIG : CONFIG_ARRAY_TYPE := gen_test_config; -- *TYPE DECLARATION* type DDS_STAGE_TYPE is (IDLE, START, DONE, CHECK_SI, CHECK_DATA, WAIT_EOC); type RTPS_STAGE_TYPE is (IDLE, START, PUSH, DONE); + type DDS_READER_MEM_ARRAY_TYPE is array (0 to NUM_READERS-1) of DDS_READER_MEM_TYPE; -- *SIGNAL DECLARATION* signal clk : std_logic := '0'; signal reset : std_logic := '1'; signal check_time : TIME_TYPE := TIME_ZERO; - signal start_rtps, start_dds, ack_rtps, ack_dds, done_rtps, done_dds : std_logic := '0'; - signal opcode_rtps : HISTORY_CACHE_OPCODE_TYPE := NOP; - signal opcode_dds : DDS_READER_OPCODE_TYPE := NOP; - signal ret_rtps : HISTORY_CACHE_RESPONSE_TYPE := ERROR; - signal ready_in_rtps, valid_in_rtps, last_word_in_rtps : std_logic := '0'; - signal ready_out_dds, valid_out_dds, last_word_out_dds : std_logic := '0'; - signal data_in_rtps, data_out_dds : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); - signal get_data_dds, si_valid_data, si_valid, eoc : std_logic := '0'; - signal return_code_dds : std_logic_vector(RETURN_CODE_WIDTH-1 downto 0) := (others => '0'); - signal status : std_logic_vector(STATUS_KIND_WIDTH-1 downto 0) := (others => '0'); - signal instance_state_dds, si_instance_state : std_logic_vector(INSTANCE_STATE_KIND_WIDTH-1 downto 0) := ANY_INSTANCE_STATE; - signal view_state_dds, si_view_state : std_logic_vector(VIEW_STATE_KIND_WIDTH-1 downto 0) := ANY_VIEW_STATE; - signal sample_state_dds, si_sample_state : std_logic_vector(SAMPLE_STATE_KIND_WIDTH-1 downto 0) := ANY_SAMPLE_STATE; - signal instance_handle_dds, si_instance_handle : INSTANCE_HANDLE_TYPE := HANDLE_NIL; - signal max_samples_dds : std_logic_vector(MAX_SAMPLES_WIDTH-1 downto 0) := (others => '0'); - signal si_source_timestamp : TIME_TYPE := TIME_INVALID; - signal si_publication_handle : INSTANCE_HANDLE_TYPE := HANDLE_NIL; - signal si_disposed_generation_count : std_logic_vector(DISPOSED_GENERATION_COUNT_WIDTH-1 downto 0) := (others => '0'); - signal si_no_writers_generation_count : std_logic_vector(NO_WRITERS_GENERATION_COUNT_WIDTH-1 downto 0) := (others => '0'); - signal si_sample_rank : std_logic_vector(SAMPLE_RANK_WIDTH-1 downto 0) := (others => '0'); - signal si_generation_rank : std_logic_vector(GENERATION_RANK_WIDTH-1 downto 0) := (others => '0'); - signal si_absolute_generation_rank: std_logic_vector(ABSOLUTE_GENERATION_COUNT_WIDTH-1 downto 0) := (others => '0'); + signal start_rtps, start_dds, ack_rtps, ack_dds, done_rtps, done_dds : std_logic_vector(0 to NUM_READERS-1) := (others => '0'); + signal opcode_rtps : HISTORY_CACHE_OPCODE_ARRAY_TYPE(0 to NUM_READERS-1) := (others => NOP); + signal opcode_dds : DDS_READER_OPCODE_ARRAY_TYPE(0 to NUM_READERS-1) := (others => NOP); + signal ret_rtps : HISTORY_CACHE_RESPONSE_ARRAY_TYPE(0 to NUM_READERS-1) := (others => ERROR); + signal ready_in_rtps, valid_in_rtps, last_word_in_rtps : std_logic_vector(0 to NUM_READERS-1) := (others => '0'); + signal ready_out_dds, valid_out_dds, last_word_out_dds : std_logic_vector(0 to NUM_READERS-1) := (others => '0'); + signal data_in_rtps, data_out_dds : WORD_ARRAY_TYPE(0 to NUM_READERS-1) := (others => (others => '0')); + signal get_data_dds, si_valid, eoc : std_logic_vector(0 to NUM_READERS-1) := (others => '0'); + signal return_code_dds : RETURN_CODE_ARRAY_TYPE(0 to NUM_READERS-1) := (others => (others => '0')); + signal status : STATUS_KIND_ARRAY_TYPE(0 to NUM_READERS-1) := (others => (others => '0')); + signal instance_state_dds : INSTANCE_STATE_ARRAY_TYPE(0 to NUM_READERS-1) := (others => ANY_INSTANCE_STATE); + signal view_state_dds : VIEW_STATE_ARRAY_TYPE(0 to NUM_READERS-1) := (others => ANY_VIEW_STATE); + signal sample_state_dds : SAMPLE_STATE_ARRAY_TYPE(0 to NUM_READERS-1) := (others => ANY_SAMPLE_STATE); + signal instance_handle_dds : INSTANCE_HANDLE_ARRAY_TYPE(0 to NUM_READERS-1) := (others => HANDLE_NIL); + signal max_samples_dds : MAX_SAMPLES_ARRAY_TYPE(0 to NUM_READERS-1) := (others => (others => '0')); + signal sample_info : SAMPLE_INFO_ARRAY_TYPE(0 to NUM_READERS-1); + signal ind : natural := 0; signal dds_start , dds_done , rtps_start, rtps_done : std_logic := '0'; signal dds_cnt, dds_cnt2, rtps_cnt : natural := 0; signal dds_stage : DDS_STAGE_TYPE := IDLE; signal rtps_stage : RTPS_STAGE_TYPE := IDLE; shared variable dds : DDS_READER_TEST_TYPE := DEFAULT_DDS_READER_TEST; shared variable rtps : RTPS_READER_TEST_TYPE := DEFAULT_RTPS_READER_TEST; - shared variable mem : DDS_READER_MEM_TYPE := DEFAULT_DDS_READER_MEM; - signal data_id, ret_id, sstate_id, vstate_id, istate_id, inst_id, ts_id, pub_id, dis_gen_cnt_id, no_w_gen_cnt_id, srank_id, grank_id, agrank_id, eoc_id, valid_id : AlertLogIDType; + shared variable mem : DDS_READER_MEM_ARRAY_TYPE := (others => DEFAULT_DDS_READER_MEM); + signal data_id, ret_id, sstate_id, vstate_id, istate_id, inst_id, ts_id, pub_id, dis_gen_cnt_id, no_w_gen_cnt_id, srank_id, grank_id, agrank_id, eoc_id, valid_id, status_id : AlertLogIDType; -- *FUNCTION DECLARATION* function extract_key_hash (payload : TEST_PACKET_TYPE) return INSTANCE_HANDLE_TYPE is @@ -80,70 +98,55 @@ architecture testbench of L0_dds_reader_test2_arpkriu is return ret; end function; + procedure wait_on_sig(signal sig : std_logic) is + begin + if (sig /= '1') then + wait on sig until sig = '1'; + end if; + end procedure; + begin -- Unit Under Test uut : entity work.dds_reader(arch) generic map ( - TIME_BASED_FILTER_QOS => gen_duration(2,0), - DEADLINE_QOS => DURATION_INFINITE, - MAX_SAMPLES => std_logic_vector(to_unsigned(4,CDR_LONG_WIDTH)), - MAX_INSTANCES => std_logic_vector(to_unsigned(3,CDR_LONG_WIDTH)), - MAX_SAMPLES_PER_INSTANCE => std_logic_vector(to_unsigned(2,CDR_LONG_WIDTH)), - HISTORY_QOS => KEEP_ALL_HISTORY_QOS, - RELIABILITY_QOS => RELIABLE_RELIABILITY_QOS, - PRESENTATION_QOS => INSTANCE_PRESENTATION_QOS, - DESTINATION_ORDER_QOS => BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS, - COHERENT_ACCESS => FALSE, - ORDERED_ACCESS => FALSE, - WITH_KEY => TRUE, - PAYLOAD_FRAME_SIZE => 11, - MAX_REMOTE_ENDPOINTS => MAX_REMOTE_ENDPOINTS + NUM_READERS => NUM_READERS, + CONFIG_ARRAY => to_QUARTUS_CONFIG_ARRAY_TYPE(TEST_CONFIG), + MAX_REMOTE_ENDPOINTS => MAX_REMOTE_ENDPOINTS ) port map ( - clk => clk, - reset => reset, - time => check_time, - start_rtps => start_rtps, - opcode_rtps => opcode_rtps, - ack_rtps => ack_rtps, - done_rtps => done_rtps, - ret_rtps => ret_rtps, - data_in_rtps => data_in_rtps, - valid_in_rtps => valid_in_rtps, - ready_in_rtps => ready_in_rtps, - last_word_in_rtps => last_word_in_rtps, - start_dds => start_dds, - ack_dds => ack_dds, - opcode_dds => opcode_dds, - instance_state_dds => instance_state_dds, - view_state_dds => view_state_dds, - sample_state_dds => sample_state_dds, - instance_handle_dds => instance_handle_dds, - max_samples_dds => max_samples_dds, - get_data_dds => get_data_dds, - done_dds => done_dds, - return_code_dds => return_code_dds, - ready_out_dds => ready_out_dds, - valid_out_dds => valid_out_dds, - data_out_dds => data_out_dds, - last_word_out_dds => last_word_out_dds, - sample_info.sample_state => si_sample_state, - sample_info.view_state => si_view_state, - sample_info.instance_state => si_instance_state, - sample_info.source_timestamp => si_source_timestamp, - sample_info.instance_handle => si_instance_handle, - sample_info.publication_handle => si_publication_handle, - sample_info.disposed_generation_count => si_disposed_generation_count, - sample_info.no_writers_generation_count => si_no_writers_generation_count, - sample_info.sample_rank => si_sample_rank, - sample_info.generation_rank => si_generation_rank, - sample_info.absolute_generation_rank => si_absolute_generation_rank, - sample_info.valid_data => si_valid_data, - sample_info_valid => si_valid, - sample_info_ack => '1', - eoc => eoc, - status => status + clk => clk, + reset => reset, + time => check_time, + start_rtps => start_rtps, + opcode_rtps => opcode_rtps, + ack_rtps => ack_rtps, + done_rtps => done_rtps, + ret_rtps => ret_rtps, + data_in_rtps => data_in_rtps, + valid_in_rtps => valid_in_rtps, + ready_in_rtps => ready_in_rtps, + last_word_in_rtps => last_word_in_rtps, + start_dds => start_dds, + ack_dds => ack_dds, + opcode_dds => opcode_dds, + instance_state_dds => instance_state_dds, + view_state_dds => view_state_dds, + sample_state_dds => sample_state_dds, + instance_handle_dds => instance_handle_dds, + max_samples_dds => max_samples_dds, + get_data_dds => get_data_dds, + done_dds => done_dds, + return_code_dds => return_code_dds, + ready_out_dds => ready_out_dds, + valid_out_dds => valid_out_dds, + data_out_dds => data_out_dds, + last_word_out_dds => last_word_out_dds, + sample_info => sample_info, + sample_info_valid => si_valid, + sample_info_ack => (others => '1'), + eoc => eoc, + status => status ); stimulus_prc : process @@ -198,20 +201,6 @@ begin wait until rising_edge(clk); end procedure; - procedure wait_on_dds is - begin - if (dds_done /= '1') then - wait until dds_done = '1'; - end if; - end procedure; - - procedure wait_on_rtps is - begin - if (rtps_done /= '1') then - wait until rtps_done = '1'; - end if; - end procedure; - procedure wait_on_completion is begin if (rtps_done /= '1' or dds_done /= '1') then @@ -238,7 +227,7 @@ begin begin - SetAlertLogName("L0_dds_reader_test2_arpkriu - (KEEP ALL, Reliable, Positive TIME_BASED_FILTER, Keyed, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER, ACCESS SCOPE Instance, Unordered) - TIME_BASED_FILTER QoS Handling"); + SetAlertLogName("L0_dds_reader_test7 - Sample Rejected Status Handling"); SetAlertEnable(FAILURE, TRUE); SetAlertEnable(ERROR, TRUE); SetAlertEnable(WARNING, TRUE); @@ -257,17 +246,18 @@ begin srank_id <= GetAlertLogID("Sample Rank", ALERTLOG_BASE_ID); grank_id <= GetAlertLogID("Generation Rank", ALERTLOG_BASE_ID); agrank_id <= GetAlertLogID("Absolute Generation Rank", ALERTLOG_BASE_ID); - eoc_id <= GetAlertLogID("End Of Collection", ALERTLOG_BASE_ID); + eoc_id <= GetAlertLogID("End of Collection", ALERTLOG_BASE_ID); valid_id <= GetAlertLogID("Valid Data", ALERTLOG_BASE_ID); data_id <= GetAlertLogID("Data Out", ALERTLOG_BASE_ID); ret_id <= GetAlertLogID("Return Code", ALERTLOG_BASE_ID); + status_id <= GetAlertLogID("Communication Status", ALERTLOG_BASE_ID); -- Key Hashes kh1 := gen_key_hash; kh2 := gen_key_hash; kh3 := gen_key_hash; kh4 := gen_key_hash; - + kh5 := gen_key_hash; Log("Initiating Test", INFO); @@ -277,7 +267,8 @@ begin wait until rising_edge(clk); wait until rising_edge(clk); reset <= '0'; - -- MEM: 0, 0, 0, 0 + wait_on_idle; + -- MEM: - -- ISTATE: - -- WRITER: - @@ -286,120 +277,132 @@ begin cc.kind := ALIVE; cc.instance := kh1; cc.payload := gen_payload(kh1,10); + cc.src_timestamp := gen_duration(1 sec); - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Aligned Payload] (ACCEPTED)", INFO); + Log("R0: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Aligned Payload] (ACCEPTED)", INFO); + Log("R0: ACCEPTED", DEBUG); rtps := DEFAULT_RTPS_READER_TEST; rtps.opcode := ADD_CACHE_CHANGE; rtps.cc := cc; rtps.writer_pos := 0; rtps.ret_code := OK; s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(0), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + -- READER 0 + ind <= 0; start_rtps; - wait_on_rtps; + wait_on_sig(rtps_done); wait_on_idle; - -- MEM: I1S1, 0, 0, 0 + -- MEM: I1S1 -- ISTATE: I1:ALIVE -- WRITER: W0:I1 - Log("Current Time: 1s", INFO); - check_time <= gen_duration(1,0); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait_on_idle; - cc := DEFAULT_CACHE_CHANGE; cc.serialized_key := FALSE; cc.kind := ALIVE; cc.instance := kh1; cc.payload := gen_payload(kh1,10); + cc.src_timestamp := gen_duration(2 sec); - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Aligned Payload] (IGNORED: Time Based Filter)", INFO); + Log("R0: RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 32, Aligned Payload]", INFO); + Log("R0: ACCEPTED", DEBUG); rtps := DEFAULT_RTPS_READER_TEST; rtps.opcode := ADD_CACHE_CHANGE; rtps.cc := cc; - rtps.writer_pos := 0; - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh2; - cc.payload := gen_payload(kh2,10); - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 2, Writer 1, Aligned Payload] (ACCEPTED)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 1; + rtps.writer_pos := 32; rtps.ret_code := OK; s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + add_sample(s,mem(0), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + -- READER 0 + ind <= 0; start_rtps; - wait_on_rtps; - wait_on_idle; - -- MEM: I1S1, I2S1, 0, 0 - -- ISTATE: I1:ALIVE, I2:ALIVE - -- WRITER: W0:I1, W1:I2 - - Log("Current Time: 2s", INFO); - check_time <= gen_duration(2,0); - wait until rising_edge(clk); - wait until rising_edge(clk); + wait_on_sig(rtps_done); wait_on_idle; + -- MEM: I1S1, I1S2 + -- ISTATE: I1:ALIVE + -- WRITER: W0:I1, W33:I1 cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; - cc.instance := kh2; - cc.payload := gen_payload(kh2,10); - - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 2, Writer 0, Aligned Payload] (IGNORED: Time Based Filter)", INFO); - rtps := DEFAULT_RTPS_READER_TEST; - rtps.opcode := ADD_CACHE_CHANGE; - rtps.cc := cc; - rtps.writer_pos := 1; - rtps.ret_code := OK; - start_rtps; - wait_on_rtps; - wait_on_idle; - - cc := DEFAULT_CACHE_CHANGE; - cc.serialized_key := FALSE; - cc.kind := ALIVE; + cc.serialized_key := TRUE; + cc.kind := NOT_ALIVE_UNREGISTERED; cc.instance := kh1; - cc.payload := gen_payload(kh1,10); + cc.payload := gen_payload(kh1,5); + cc.src_timestamp := gen_duration(3 sec); - Log("RTPS Operation ADD_CACHE_CHANGE [KEY_HASH, Instance 1, Writer 0, Aligned Payload] (ACCEPTED)", INFO); + Log("R0: RTPS Operation ADD_CACHE_CHANGE [UNREGISTER, Instance 1, Writer 0]", INFO); + Log("R0: ACCEPTED", DEBUG); rtps := DEFAULT_RTPS_READER_TEST; rtps.opcode := ADD_CACHE_CHANGE; rtps.cc := cc; rtps.writer_pos := 0; rtps.ret_code := OK; - s := to_sample(cc,ALIVE_INSTANCE_STATE); - add_sample(s,mem, BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + -- READER 0 + ind <= 0; start_rtps; - wait_on_rtps; + wait_on_sig(rtps_done); wait_on_idle; - -- MEM: I1S1, I2S1, I1S2, 0 - -- ISTATE: I1:ALIVE, I2:ALIVE - -- WRITER: W0:I1, W1:I2 + -- MEM: I1S1, I1S2 + -- ISTATE: I1:ALIVE + -- WRITER: W33:I1 - -- VAILDATE STATE - - Log("DDS Operation READ [MAX_SAMPLES 4, ANY_SAMPLE_STATE, ANY_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); + Log("R0: DDS Operation READ [MAX_SAMPLES 4, ANY_SAMPLE_STATE, NOT_ALIVE_NO_WRITERS_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); dds := DEFAULT_DDS_READER_TEST; dds.opcode := READ; dds.max_samples := 4; dds.sstate := ANY_SAMPLE_STATE; - dds.istate := ANY_INSTANCE_STATE; + dds.istate := NOT_ALIVE_NO_WRITERS_INSTANCE_STATE; dds.vstate := ANY_VIEW_STATE; + dds.ret_code := RETCODE_NO_DATA; + -- READER 0 + ind <= 0; start_dds; - wait_on_dds; + wait_on_sig(dds_done); wait_on_idle; + -- MEM: I1S1, I1S2 + -- ISTATE: I1:ALIVE + -- WRITER: W33:I1 + + cc := DEFAULT_CACHE_CHANGE; + cc.serialized_key := TRUE; + cc.kind := NOT_ALIVE_UNREGISTERED; + cc.instance := kh1; + cc.payload := gen_payload(kh1,5); + cc.src_timestamp := gen_duration(3 sec); + + Log("R0: RTPS Operation ADD_CACHE_CHANGE [UNREGISTER, Instance 1, Writer 32]", INFO); + Log("R0: ACCEPTED", DEBUG); + rtps := DEFAULT_RTPS_READER_TEST; + rtps.opcode := ADD_CACHE_CHANGE; + rtps.cc := cc; + rtps.writer_pos := 32; + rtps.ret_code := OK; + s := to_sample(cc,NOT_ALIVE_NO_WRITERS_INSTANCE_STATE); + add_sample(s,mem(0), BY_RECEPTION_TIMESTAMP_DESTINATION_ORDER_QOS); + -- READER 0 + ind <= 0; + start_rtps; + wait_on_sig(rtps_done); + wait_on_idle; + -- MEM: I1S1, I1S2, I1S3- + -- ISTATE: I1:NO_WRITERS + -- WRITER: - + + Log("R0: DDS Operation READ [MAX_SAMPLES 4, ANY_SAMPLE_STATE, NOT_ALIVE_NO_WRITERS_INSTANCE_STATE, ANY_VIEW_STATE]", INFO); + dds := DEFAULT_DDS_READER_TEST; + dds.opcode := READ; + dds.max_samples := 4; + dds.sstate := ANY_SAMPLE_STATE; + dds.istate := NOT_ALIVE_NO_WRITERS_INSTANCE_STATE; + dds.vstate := ANY_VIEW_STATE; + dds.ret_code := RETCODE_OK; + -- READER 0 + ind <= 0; + start_dds; + wait_on_sig(dds_done); + wait_on_idle; + -- MEM: I1S1, I1S2, I1S3- + -- ISTATE: I1:NO_WRITERS + -- WRITER: - wait_on_completion; TranscriptOpen(RESULTS_FILE, APPEND_MODE); @@ -418,13 +421,6 @@ begin wait for 25 ns; end process; - alert_prc : process(all) - begin - if rising_edge(clk) then - -- TODO - end if; - end process; - dds_prc : process(all) variable col : COLLECTION_TYPE := DEFAULT_COLLECTION; begin @@ -438,16 +434,16 @@ begin dds_done <= '1'; end if; when START => - if (ack_dds = '1') then + if (ack_dds(ind) = '1') then dds_stage <= DONE; dds_cnt <= 0; end if; when DONE => - if (done_dds = '1') then - AffirmIfEqual(ret_id, return_code_dds, dds.ret_code); + if (done_dds(ind) = '1') then + AffirmIfEqual(ret_id, return_code_dds(ind), dds.ret_code); case (dds.ret_code) is when RETCODE_OK => - gen_collection(mem, col, dds, INSTANCE_PRESENTATION_QOS, FALSE); + gen_collection(mem(ind), col, dds, TEST_CONFIG(ind).PRESENTATION_QOS, TEST_CONFIG(ind).ORDERED_ACCESS); dds_stage <= CHECK_SI; dds_cnt <= 0; when others => @@ -455,19 +451,19 @@ begin end case; end if; when CHECK_SI => - if (si_valid = '1') then - AffirmIfEqual(sstate_id, si_sample_state, col.s(dds_cnt).sstate); - AffirmIfEqual(vstate_id, si_view_state, col.s(dds_cnt).vstate); - AffirmIfEqual(istate_id, si_instance_state, col.s(dds_cnt).istate); - AffirmIfEqual(ts_id, to_unsigned(si_source_timestamp), to_unsigned(col.s(dds_cnt).ts)); - AffirmIfEqual(inst_id, to_unsigned(si_instance_handle), to_unsigned(col.s(dds_cnt).inst)); - AffirmIfEqual(pub_id, to_unsigned(si_publication_handle), to_unsigned(HANDLE_NIL)); - AffirmIfEqual(dis_gen_cnt_id, si_disposed_generation_count, std_logic_vector(to_unsigned(col.s(dds_cnt).dis_gen_cnt,WORD_WIDTH))); - AffirmIfEqual(no_w_gen_cnt_id, si_no_writers_generation_count, std_logic_vector(to_unsigned(col.s(dds_cnt).no_w_gen_cnt,WORD_WIDTH))); - AffirmIfEqual(srank_id, si_sample_rank, std_logic_vector(to_unsigned(col.s(dds_cnt).srank,WORD_WIDTH))); - AffirmIfEqual(grank_id, si_generation_rank, std_logic_vector(to_unsigned(col.s(dds_cnt).grank,WORD_WIDTH))); - AffirmIfEqual(agrank_id, si_absolute_generation_rank, std_logic_vector(to_unsigned(col.s(dds_cnt).agrank,WORD_WIDTH))); - if (si_valid_data = '1') then + if (si_valid(ind) = '1') then + AffirmIfEqual(sstate_id, sample_info(ind).sample_state, col.s(dds_cnt).sstate); + AffirmIfEqual(vstate_id, sample_info(ind).view_state, col.s(dds_cnt).vstate); + AffirmIfEqual(istate_id, sample_info(ind).instance_state, col.s(dds_cnt).istate); + AffirmIfEqual(ts_id, to_unsigned(sample_info(ind).source_timestamp), to_unsigned(col.s(dds_cnt).ts)); + AffirmIfEqual(inst_id, to_unsigned(sample_info(ind).instance_handle), to_unsigned(col.s(dds_cnt).inst)); + AffirmIfEqual(pub_id, to_unsigned(sample_info(ind).publication_handle), to_unsigned(HANDLE_NIL)); + AffirmIfEqual(dis_gen_cnt_id, sample_info(ind).disposed_generation_count, std_logic_vector(to_unsigned(col.s(dds_cnt).dis_gen_cnt,WORD_WIDTH))); + AffirmIfEqual(no_w_gen_cnt_id, sample_info(ind).no_writers_generation_count, std_logic_vector(to_unsigned(col.s(dds_cnt).no_w_gen_cnt,WORD_WIDTH))); + AffirmIfEqual(srank_id, sample_info(ind).sample_rank, std_logic_vector(to_unsigned(col.s(dds_cnt).srank,WORD_WIDTH))); + AffirmIfEqual(grank_id, sample_info(ind).generation_rank, std_logic_vector(to_unsigned(col.s(dds_cnt).grank,WORD_WIDTH))); + AffirmIfEqual(agrank_id, sample_info(ind).absolute_generation_rank, std_logic_vector(to_unsigned(col.s(dds_cnt).agrank,WORD_WIDTH))); + if (sample_info(ind).valid_data = '1') then AffirmIf(valid_id, col.s(dds_cnt).data /= EMPTY_TEST_PACKET, "Sample with Data not expected"); dds_stage <= CHECK_DATA; dds_cnt2 <= 0; @@ -481,13 +477,13 @@ begin end if; end if; end if; - AffirmIf(eoc_id, eoc = '0', "EOC pulled high"); + AffirmIf(eoc_id, eoc(ind) = '0', "EOC pulled high"); when CHECK_DATA => - if (valid_out_dds = '1') then - AffirmIfEqual(data_id, data_out_dds, col.s(dds_cnt).data.data(dds_cnt2)); + if (valid_out_dds(ind) = '1') then + AffirmIfEqual(data_id, data_out_dds(ind), col.s(dds_cnt).data.data(dds_cnt2)); dds_cnt2 <= dds_cnt2 + 1; if (dds_cnt2 = col.s(dds_cnt).data.length-1) then - AlertIf(data_id, last_word_out_dds /= '1', "Last Word Signal not pulled High", ERROR); + AlertIf(data_id, last_word_out_dds(ind) /= '1', "Last Word Signal not pulled High", ERROR); if (dds_cnt = col.len-1) then -- DONE dds_stage <= WAIT_EOC; @@ -498,39 +494,39 @@ begin end if; end if; when WAIT_EOC => - if (eoc = '1') then + if (eoc(ind) = '1') then dds_stage <= IDLE; end if; end case; end if; -- DEFAULT - start_dds <= '0'; - opcode_dds <= NOP; - instance_state_dds <= ANY_INSTANCE_STATE; - view_state_dds <= ANY_VIEW_STATE; - sample_state_dds <= ANY_SAMPLE_STATE; - instance_handle_dds <= HANDLE_NIL; - max_samples_dds <= (others => '0'); - get_data_dds <= '0'; - ready_out_dds <= '0'; + start_dds <= (others => '0'); + opcode_dds <= (others => NOP); + instance_state_dds <= (others => ANY_INSTANCE_STATE); + view_state_dds <= (others => ANY_VIEW_STATE); + sample_state_dds <= (others => ANY_SAMPLE_STATE); + instance_handle_dds <= (others => HANDLE_NIL); + max_samples_dds <= (others => (others => '0')); + get_data_dds <= (others => '0'); + ready_out_dds <= (others => '0'); case (dds_stage ) is when START => - start_dds <= '1'; - opcode_dds <= dds.opcode; - instance_state_dds <= dds.istate; - view_state_dds <= dds.vstate; - sample_state_dds <= dds.sstate; - instance_handle_dds <= dds.inst; - max_samples_dds <= std_logic_vector(to_unsigned(dds.max_samples, WORD_WIDTH)); + start_dds(ind) <= '1'; + opcode_dds(ind) <= dds.opcode; + instance_state_dds(ind) <= dds.istate; + view_state_dds(ind) <= dds.vstate; + sample_state_dds(ind) <= dds.sstate; + instance_handle_dds(ind) <= dds.inst; + max_samples_dds(ind) <= std_logic_vector(to_unsigned(dds.max_samples, WORD_WIDTH)); when CHECK_SI => - if (si_valid = '1' and si_valid_data = '1') then - get_data_dds <= '1'; + if (si_valid(ind) = '1' and sample_info(ind).valid_data = '1') then + get_data_dds(ind) <= '1'; end if; when CHECK_DATA => - ready_out_dds <= '1'; + ready_out_dds(ind) <= '1'; when others => null; end case; @@ -549,7 +545,7 @@ begin rtps_done <= '1'; end if; when START => - if (ack_rtps = '1') then + if (ack_rtps(ind) = '1') then case (rtps.opcode) is when ADD_CACHE_CHANGE => gen_add_cache_change_dds(rtps.cc, rtps.lifespan, rtps.writer_pos, stimulus); @@ -559,41 +555,41 @@ begin end case; end if; when PUSH => - if (ready_in_rtps = '1') then + if (ready_in_rtps(ind) = '1') then rtps_cnt <= rtps_cnt + 1; if (rtps_cnt = stimulus.length-1) then rtps_stage <= DONE; end if; end if; when DONE => - if (done_rtps = '1') then - AffirmIfEqual(ret_id, HISTORY_CACHE_RESPONSE_TYPE'pos(ret_rtps), HISTORY_CACHE_RESPONSE_TYPE'pos(rtps.ret_code)); + if (done_rtps(ind) = '1') then + AffirmIfEqual(ret_id, HISTORY_CACHE_RESPONSE_TYPE'pos(ret_rtps(ind)), HISTORY_CACHE_RESPONSE_TYPE'pos(rtps.ret_code)); rtps_stage <= IDLE; end if; end case; end if; -- DEFAULT - start_rtps <= '0'; - opcode_rtps <= NOP; - valid_in_rtps <= '0'; - last_word_in_rtps <= '0'; - data_in_rtps <= (others => '0'); + start_rtps <= (others => '0'); + opcode_rtps <= (others => NOP); + valid_in_rtps <= (others => '0'); + last_word_in_rtps <= (others => '0'); + data_in_rtps <= (others => (others => '0')); case (rtps_stage) is when START => - start_rtps <= '1'; - opcode_rtps <= rtps.opcode; + start_rtps(ind) <= '1'; + opcode_rtps(ind) <= rtps.opcode; case (rtps.opcode) is when REMOVE_WRITER => - data_in_rtps <= std_logic_vector(to_unsigned(rtps.writer_pos,WORD_WIDTH)); + data_in_rtps(ind) <= std_logic_vector(to_unsigned(rtps.writer_pos,WORD_WIDTH)); when others => null; end case; when PUSH => - valid_in_rtps <= '1'; - data_in_rtps <= stimulus.data(rtps_cnt); - last_word_in_rtps <= stimulus.last(rtps_cnt); + valid_in_rtps(ind) <= '1'; + data_in_rtps(ind) <= stimulus.data(rtps_cnt); + last_word_in_rtps(ind) <= stimulus.last(rtps_cnt); when others => null; end case; diff --git a/src/Tests/Level_2/L2_Testbench_Lib2.vhd b/src/Tests/Level_2/L2_Testbench_Lib2.vhd index 3900281..77590c6 100644 --- a/src/Tests/Level_2/L2_Testbench_Lib2.vhd +++ b/src/Tests/Level_2/L2_Testbench_Lib2.vhd @@ -417,22 +417,11 @@ begin status => status_dw_wi(0 to NUM_WRITERS-1) ); end generate; - dds_endpoint_gen : for i in 0 to NUM_READERS-1 generate + dds_endpoint_r_if : if (NUM_READERS > 0) generate dds_reader_inst : entity work.dds_reader(arch) generic map ( - TIME_BASED_FILTER_QOS => ENDPOINT_CONFIG(i).TIME_BASED_FILTER_QOS, - DEADLINE_QOS => ENDPOINT_CONFIG(i).DEADLINE_QOS, - MAX_INSTANCES => ENDPOINT_CONFIG(i).MAX_INSTANCES, - MAX_SAMPLES_PER_INSTANCE => ENDPOINT_CONFIG(i).MAX_SAMPLES_PER_INSTANCE, - MAX_SAMPLES => ENDPOINT_CONFIG(i).MAX_SAMPLES, - HISTORY_QOS => ENDPOINT_CONFIG(i).HISTORY_QOS, - RELIABILITY_QOS => ENDPOINT_CONFIG(i).RELIABILITY_QOS, - PRESENTATION_QOS => ENDPOINT_CONFIG(i).PRESENTATION_QOS, - DESTINATION_ORDER_QOS => ENDPOINT_CONFIG(i).DESTINATION_ORDER_QOS, - COHERENT_ACCESS => ENDPOINT_CONFIG(i).COHERENT_ACCESS, - ORDERED_ACCESS => ENDPOINT_CONFIG(i).ORDERED_ACCESS, - WITH_KEY => ENDPOINT_CONFIG(i).WITH_KEY, - PAYLOAD_FRAME_SIZE => ENDPOINT_CONFIG(i).MAX_PAYLOAD_SIZE, + NUM_READERS => NUM_READERS, + CONFIG_ARRAY => to_QUARTUS_CONFIG_ARRAY_TYPE(ENDPOINT_CONFIG(0 to NUM_READERS-1)), MAX_REMOTE_ENDPOINTS => MAX_REMOTE_ENDPOINTS ) port map ( @@ -441,37 +430,37 @@ begin reset => reset, time => time, -- FROM RTPS ENDPOINT - start_rtps => start_rr_dr(i), - opcode_rtps => opcode_rr_dr(i), - ack_rtps => ack_dr_rr(i), - done_rtps => done_dr_rr(i), - ret_rtps => ret_dr_rr(i), - valid_in_rtps => valid_rr_dr(i), - ready_in_rtps => ready_dr_rr(i), - data_in_rtps => data_rr_dr(i), - last_word_in_rtps => last_word_rr_dr(i), + start_rtps => start_rr_dr(0 to NUM_READERS-1), + opcode_rtps => opcode_rr_dr(0 to NUM_READERS-1), + ack_rtps => ack_dr_rr(0 to NUM_READERS-1), + done_rtps => done_dr_rr(0 to NUM_READERS-1), + ret_rtps => ret_dr_rr(0 to NUM_READERS-1), + valid_in_rtps => valid_rr_dr(0 to NUM_READERS-1), + ready_in_rtps => ready_dr_rr(0 to NUM_READERS-1), + data_in_rtps => data_rr_dr(0 to NUM_READERS-1), + last_word_in_rtps => last_word_rr_dr(0 to NUM_READERS-1), -- TO USER ENTITY - start_dds => start_ri_dr(i), - ack_dds => ack_dr_ri(i), - opcode_dds => opcode_ri_dr(i), - instance_state_dds => instance_state_ri_dr(i), - view_state_dds => view_state_ri_dr(i), - sample_state_dds => sample_state_ri_dr(i), - instance_handle_dds => instance_handle_ri_dr(i), - max_samples_dds => max_samples_ri_dr(i), - get_data_dds => get_data_ri_dr(i), - done_dds => done_dr_ri(i), - return_code_dds => return_code_dr_ri(i), - valid_out_dds => valid_dr_ri(i), - ready_out_dds => ready_ri_dr(i), - data_out_dds => data_dr_ri(i), - last_word_out_dds => last_word_dr_ri(i), - sample_info => sample_info_dr_ri(i), - sample_info_valid => sample_info_valid_dr_ri(i), - sample_info_ack => sample_info_ack_ri_dr(i), - eoc => eoc_dr_ri(i), + start_dds => start_ri_dr(0 to NUM_READERS-1), + ack_dds => ack_dr_ri(0 to NUM_READERS-1), + opcode_dds => opcode_ri_dr(0 to NUM_READERS-1), + instance_state_dds => instance_state_ri_dr(0 to NUM_READERS-1), + view_state_dds => view_state_ri_dr(0 to NUM_READERS-1), + sample_state_dds => sample_state_ri_dr(0 to NUM_READERS-1), + instance_handle_dds => instance_handle_ri_dr(0 to NUM_READERS-1), + max_samples_dds => max_samples_ri_dr(0 to NUM_READERS-1), + get_data_dds => get_data_ri_dr(0 to NUM_READERS-1), + done_dds => done_dr_ri(0 to NUM_READERS-1), + return_code_dds => return_code_dr_ri(0 to NUM_READERS-1), + valid_out_dds => valid_dr_ri(0 to NUM_READERS-1), + ready_out_dds => ready_ri_dr(0 to NUM_READERS-1), + data_out_dds => data_dr_ri(0 to NUM_READERS-1), + last_word_out_dds => last_word_dr_ri(0 to NUM_READERS-1), + sample_info => sample_info_dr_ri(0 to NUM_READERS-1), + sample_info_valid => sample_info_valid_dr_ri(0 to NUM_READERS-1), + sample_info_ack => sample_info_ack_ri_dr(0 to NUM_READERS-1), + eoc => eoc_dr_ri(0 to NUM_READERS-1), -- Communication Status - status => status_dr_ri(i) + status => status_dr_ri(0 to NUM_READERS-1) ); end generate; diff --git a/src/Tests/Level_2/L2_Testbench_Lib3.vhd b/src/Tests/Level_2/L2_Testbench_Lib3.vhd index a66ca19..f41d4d8 100644 --- a/src/Tests/Level_2/L2_Testbench_Lib3.vhd +++ b/src/Tests/Level_2/L2_Testbench_Lib3.vhd @@ -424,22 +424,11 @@ begin status => status_dw_wi(0 to NUM_WRITERS-1) ); end generate; - dds_endpoint_gen : for i in 0 to NUM_READERS-1 generate + dds_endpoint_r_if : if (NUM_READERS > 0) generate dds_reader_inst : entity work.dds_reader(arch) generic map ( - TIME_BASED_FILTER_QOS => ENDPOINT_CONFIG(i).TIME_BASED_FILTER_QOS, - DEADLINE_QOS => ENDPOINT_CONFIG(i).DEADLINE_QOS, - MAX_INSTANCES => ENDPOINT_CONFIG(i).MAX_INSTANCES, - MAX_SAMPLES_PER_INSTANCE => ENDPOINT_CONFIG(i).MAX_SAMPLES_PER_INSTANCE, - MAX_SAMPLES => ENDPOINT_CONFIG(i).MAX_SAMPLES, - HISTORY_QOS => ENDPOINT_CONFIG(i).HISTORY_QOS, - RELIABILITY_QOS => ENDPOINT_CONFIG(i).RELIABILITY_QOS, - PRESENTATION_QOS => ENDPOINT_CONFIG(i).PRESENTATION_QOS, - DESTINATION_ORDER_QOS => ENDPOINT_CONFIG(i).DESTINATION_ORDER_QOS, - COHERENT_ACCESS => ENDPOINT_CONFIG(i).COHERENT_ACCESS, - ORDERED_ACCESS => ENDPOINT_CONFIG(i).ORDERED_ACCESS, - WITH_KEY => ENDPOINT_CONFIG(i).WITH_KEY, - PAYLOAD_FRAME_SIZE => ENDPOINT_CONFIG(i).MAX_PAYLOAD_SIZE, + NUM_READERS => NUM_READERS, + CONFIG_ARRAY => to_QUARTUS_CONFIG_ARRAY_TYPE(ENDPOINT_CONFIG(0 to NUM_READERS-1)), MAX_REMOTE_ENDPOINTS => MAX_REMOTE_ENDPOINTS ) port map ( @@ -448,37 +437,37 @@ begin reset => reset, time => time, -- FROM RTPS ENDPOINT - start_rtps => start_rr_dr(i), - opcode_rtps => opcode_rr_dr(i), - ack_rtps => ack_dr_rr(i), - done_rtps => done_dr_rr(i), - ret_rtps => ret_dr_rr(i), - valid_in_rtps => valid_rr_dr(i), - ready_in_rtps => ready_dr_rr(i), - data_in_rtps => data_rr_dr(i), - last_word_in_rtps => last_word_rr_dr(i), + start_rtps => start_rr_dr(0 to NUM_READERS-1), + opcode_rtps => opcode_rr_dr(0 to NUM_READERS-1), + ack_rtps => ack_dr_rr(0 to NUM_READERS-1), + done_rtps => done_dr_rr(0 to NUM_READERS-1), + ret_rtps => ret_dr_rr(0 to NUM_READERS-1), + valid_in_rtps => valid_rr_dr(0 to NUM_READERS-1), + ready_in_rtps => ready_dr_rr(0 to NUM_READERS-1), + data_in_rtps => data_rr_dr(0 to NUM_READERS-1), + last_word_in_rtps => last_word_rr_dr(0 to NUM_READERS-1), -- TO USER ENTITY - start_dds => start_ri_dr(i), - ack_dds => ack_dr_ri(i), - opcode_dds => opcode_ri_dr(i), - instance_state_dds => instance_state_ri_dr(i), - view_state_dds => view_state_ri_dr(i), - sample_state_dds => sample_state_ri_dr(i), - instance_handle_dds => instance_handle_ri_dr(i), - max_samples_dds => max_samples_ri_dr(i), - get_data_dds => get_data_ri_dr(i), - done_dds => done_dr_ri(i), - return_code_dds => return_code_dr_ri(i), - valid_out_dds => valid_dr_ri(i), - ready_out_dds => ready_ri_dr(i), - data_out_dds => data_dr_ri(i), - last_word_out_dds => last_word_dr_ri(i), - sample_info => sample_info_dr_ri(i), - sample_info_valid => sample_info_valid_dr_ri(i), - sample_info_ack => sample_info_ack_ri_dr(i), - eoc => eoc_dr_ri(i), + start_dds => start_ri_dr(0 to NUM_READERS-1), + ack_dds => ack_dr_ri(0 to NUM_READERS-1), + opcode_dds => opcode_ri_dr(0 to NUM_READERS-1), + instance_state_dds => instance_state_ri_dr(0 to NUM_READERS-1), + view_state_dds => view_state_ri_dr(0 to NUM_READERS-1), + sample_state_dds => sample_state_ri_dr(0 to NUM_READERS-1), + instance_handle_dds => instance_handle_ri_dr(0 to NUM_READERS-1), + max_samples_dds => max_samples_ri_dr(0 to NUM_READERS-1), + get_data_dds => get_data_ri_dr(0 to NUM_READERS-1), + done_dds => done_dr_ri(0 to NUM_READERS-1), + return_code_dds => return_code_dr_ri(0 to NUM_READERS-1), + valid_out_dds => valid_dr_ri(0 to NUM_READERS-1), + ready_out_dds => ready_ri_dr(0 to NUM_READERS-1), + data_out_dds => data_dr_ri(0 to NUM_READERS-1), + last_word_out_dds => last_word_dr_ri(0 to NUM_READERS-1), + sample_info => sample_info_dr_ri(0 to NUM_READERS-1), + sample_info_valid => sample_info_valid_dr_ri(0 to NUM_READERS-1), + sample_info_ack => sample_info_ack_ri_dr(0 to NUM_READERS-1), + eoc => eoc_dr_ri(0 to NUM_READERS-1), -- Communication Status - status => status_dr_ri(i) + status => status_dr_ri(0 to NUM_READERS-1) ); end generate; diff --git a/src/Tests/Level_2/L2_testbench_Lib4.vhd b/src/Tests/Level_2/L2_testbench_Lib4.vhd index 1ef7d7b..0711b5e 100644 --- a/src/Tests/Level_2/L2_testbench_Lib4.vhd +++ b/src/Tests/Level_2/L2_testbench_Lib4.vhd @@ -420,22 +420,11 @@ begin status => status_dw_wi(0 to NUM_WRITERS-1) ); end generate; - dds_endpoint_gen : for i in 0 to NUM_READERS-1 generate + dds_endpoint_r_if : if (NUM_READERS > 0) generate dds_reader_inst : entity work.dds_reader(arch) generic map ( - TIME_BASED_FILTER_QOS => ENDPOINT_CONFIG(i).TIME_BASED_FILTER_QOS, - DEADLINE_QOS => ENDPOINT_CONFIG(i).DEADLINE_QOS, - MAX_INSTANCES => ENDPOINT_CONFIG(i).MAX_INSTANCES, - MAX_SAMPLES_PER_INSTANCE => ENDPOINT_CONFIG(i).MAX_SAMPLES_PER_INSTANCE, - MAX_SAMPLES => ENDPOINT_CONFIG(i).MAX_SAMPLES, - HISTORY_QOS => ENDPOINT_CONFIG(i).HISTORY_QOS, - RELIABILITY_QOS => ENDPOINT_CONFIG(i).RELIABILITY_QOS, - PRESENTATION_QOS => ENDPOINT_CONFIG(i).PRESENTATION_QOS, - DESTINATION_ORDER_QOS => ENDPOINT_CONFIG(i).DESTINATION_ORDER_QOS, - COHERENT_ACCESS => ENDPOINT_CONFIG(i).COHERENT_ACCESS, - ORDERED_ACCESS => ENDPOINT_CONFIG(i).ORDERED_ACCESS, - WITH_KEY => ENDPOINT_CONFIG(i).WITH_KEY, - PAYLOAD_FRAME_SIZE => ENDPOINT_CONFIG(i).MAX_PAYLOAD_SIZE, + NUM_READERS => NUM_READERS, + CONFIG_ARRAY => to_QUARTUS_CONFIG_ARRAY_TYPE(ENDPOINT_CONFIG(0 to NUM_READERS-1)), MAX_REMOTE_ENDPOINTS => MAX_REMOTE_ENDPOINTS ) port map ( @@ -444,37 +433,37 @@ begin reset => reset, time => time, -- FROM RTPS ENDPOINT - start_rtps => start_rr_dr(i), - opcode_rtps => opcode_rr_dr(i), - ack_rtps => ack_dr_rr(i), - done_rtps => done_dr_rr(i), - ret_rtps => ret_dr_rr(i), - valid_in_rtps => valid_rr_dr(i), - ready_in_rtps => ready_dr_rr(i), - data_in_rtps => data_rr_dr(i), - last_word_in_rtps => last_word_rr_dr(i), + start_rtps => start_rr_dr(0 to NUM_READERS-1), + opcode_rtps => opcode_rr_dr(0 to NUM_READERS-1), + ack_rtps => ack_dr_rr(0 to NUM_READERS-1), + done_rtps => done_dr_rr(0 to NUM_READERS-1), + ret_rtps => ret_dr_rr(0 to NUM_READERS-1), + valid_in_rtps => valid_rr_dr(0 to NUM_READERS-1), + ready_in_rtps => ready_dr_rr(0 to NUM_READERS-1), + data_in_rtps => data_rr_dr(0 to NUM_READERS-1), + last_word_in_rtps => last_word_rr_dr(0 to NUM_READERS-1), -- TO USER ENTITY - start_dds => start_ri_dr(i), - ack_dds => ack_dr_ri(i), - opcode_dds => opcode_ri_dr(i), - instance_state_dds => instance_state_ri_dr(i), - view_state_dds => view_state_ri_dr(i), - sample_state_dds => sample_state_ri_dr(i), - instance_handle_dds => instance_handle_ri_dr(i), - max_samples_dds => max_samples_ri_dr(i), - get_data_dds => get_data_ri_dr(i), - done_dds => done_dr_ri(i), - return_code_dds => return_code_dr_ri(i), - valid_out_dds => valid_dr_ri(i), - ready_out_dds => ready_ri_dr(i), - data_out_dds => data_dr_ri(i), - last_word_out_dds => last_word_dr_ri(i), - sample_info => sample_info_dr_ri(i), - sample_info_valid => sample_info_valid_dr_ri(i), - sample_info_ack => sample_info_ack_ri_dr(i), - eoc => eoc_dr_ri(i), + start_dds => start_ri_dr(0 to NUM_READERS-1), + ack_dds => ack_dr_ri(0 to NUM_READERS-1), + opcode_dds => opcode_ri_dr(0 to NUM_READERS-1), + instance_state_dds => instance_state_ri_dr(0 to NUM_READERS-1), + view_state_dds => view_state_ri_dr(0 to NUM_READERS-1), + sample_state_dds => sample_state_ri_dr(0 to NUM_READERS-1), + instance_handle_dds => instance_handle_ri_dr(0 to NUM_READERS-1), + max_samples_dds => max_samples_ri_dr(0 to NUM_READERS-1), + get_data_dds => get_data_ri_dr(0 to NUM_READERS-1), + done_dds => done_dr_ri(0 to NUM_READERS-1), + return_code_dds => return_code_dr_ri(0 to NUM_READERS-1), + valid_out_dds => valid_dr_ri(0 to NUM_READERS-1), + ready_out_dds => ready_ri_dr(0 to NUM_READERS-1), + data_out_dds => data_dr_ri(0 to NUM_READERS-1), + last_word_out_dds => last_word_dr_ri(0 to NUM_READERS-1), + sample_info => sample_info_dr_ri(0 to NUM_READERS-1), + sample_info_valid => sample_info_valid_dr_ri(0 to NUM_READERS-1), + sample_info_ack => sample_info_ack_ri_dr(0 to NUM_READERS-1), + eoc => eoc_dr_ri(0 to NUM_READERS-1), -- Communication Status - status => status_dr_ri(i) + status => status_dr_ri(0 to NUM_READERS-1) ); end generate; diff --git a/src/Tests/Level_2/L2_testbench_Lib5.vhd b/src/Tests/Level_2/L2_testbench_Lib5.vhd index 0b526f2..576abea 100644 --- a/src/Tests/Level_2/L2_testbench_Lib5.vhd +++ b/src/Tests/Level_2/L2_testbench_Lib5.vhd @@ -435,22 +435,11 @@ begin status => status_dw_wi(0 to NUM_WRITERS-1) ); end generate; - dds_endpoint_gen : for i in 0 to NUM_READERS-1 generate + dds_endpoint_r_if : if (NUM_READERS > 0) generate dds_reader_inst : entity work.dds_reader(arch) generic map ( - TIME_BASED_FILTER_QOS => ENDPOINT_CONFIG(i).TIME_BASED_FILTER_QOS, - DEADLINE_QOS => ENDPOINT_CONFIG(i).DEADLINE_QOS, - MAX_INSTANCES => ENDPOINT_CONFIG(i).MAX_INSTANCES, - MAX_SAMPLES_PER_INSTANCE => ENDPOINT_CONFIG(i).MAX_SAMPLES_PER_INSTANCE, - MAX_SAMPLES => ENDPOINT_CONFIG(i).MAX_SAMPLES, - HISTORY_QOS => ENDPOINT_CONFIG(i).HISTORY_QOS, - RELIABILITY_QOS => ENDPOINT_CONFIG(i).RELIABILITY_QOS, - PRESENTATION_QOS => ENDPOINT_CONFIG(i).PRESENTATION_QOS, - DESTINATION_ORDER_QOS => ENDPOINT_CONFIG(i).DESTINATION_ORDER_QOS, - COHERENT_ACCESS => ENDPOINT_CONFIG(i).COHERENT_ACCESS, - ORDERED_ACCESS => ENDPOINT_CONFIG(i).ORDERED_ACCESS, - WITH_KEY => ENDPOINT_CONFIG(i).WITH_KEY, - PAYLOAD_FRAME_SIZE => ENDPOINT_CONFIG(i).MAX_PAYLOAD_SIZE, + NUM_READERS => NUM_READERS, + CONFIG_ARRAY => to_QUARTUS_CONFIG_ARRAY_TYPE(ENDPOINT_CONFIG(0 to NUM_READERS-1)), MAX_REMOTE_ENDPOINTS => MAX_REMOTE_ENDPOINTS ) port map ( @@ -459,37 +448,37 @@ begin reset => reset, time => time, -- FROM RTPS ENDPOINT - start_rtps => start_rr_dr(i), - opcode_rtps => opcode_rr_dr(i), - ack_rtps => ack_dr_rr(i), - done_rtps => done_dr_rr(i), - ret_rtps => ret_dr_rr(i), - valid_in_rtps => valid_rr_dr(i), - ready_in_rtps => ready_dr_rr(i), - data_in_rtps => data_rr_dr(i), - last_word_in_rtps => last_word_rr_dr(i), + start_rtps => start_rr_dr(0 to NUM_READERS-1), + opcode_rtps => opcode_rr_dr(0 to NUM_READERS-1), + ack_rtps => ack_dr_rr(0 to NUM_READERS-1), + done_rtps => done_dr_rr(0 to NUM_READERS-1), + ret_rtps => ret_dr_rr(0 to NUM_READERS-1), + valid_in_rtps => valid_rr_dr(0 to NUM_READERS-1), + ready_in_rtps => ready_dr_rr(0 to NUM_READERS-1), + data_in_rtps => data_rr_dr(0 to NUM_READERS-1), + last_word_in_rtps => last_word_rr_dr(0 to NUM_READERS-1), -- TO USER ENTITY - start_dds => start_ri_dr(i), - ack_dds => ack_dr_ri(i), - opcode_dds => opcode_ri_dr(i), - instance_state_dds => instance_state_ri_dr(i), - view_state_dds => view_state_ri_dr(i), - sample_state_dds => sample_state_ri_dr(i), - instance_handle_dds => instance_handle_ri_dr(i), - max_samples_dds => max_samples_ri_dr(i), - get_data_dds => get_data_ri_dr(i), - done_dds => done_dr_ri(i), - return_code_dds => return_code_dr_ri(i), - valid_out_dds => valid_dr_ri(i), - ready_out_dds => ready_ri_dr(i), - data_out_dds => data_dr_ri(i), - last_word_out_dds => last_word_dr_ri(i), - sample_info => sample_info_dr_ri(i), - sample_info_valid => sample_info_valid_dr_ri(i), - sample_info_ack => sample_info_ack_ri_dr(i), - eoc => eoc_dr_ri(i), + start_dds => start_ri_dr(0 to NUM_READERS-1), + ack_dds => ack_dr_ri(0 to NUM_READERS-1), + opcode_dds => opcode_ri_dr(0 to NUM_READERS-1), + instance_state_dds => instance_state_ri_dr(0 to NUM_READERS-1), + view_state_dds => view_state_ri_dr(0 to NUM_READERS-1), + sample_state_dds => sample_state_ri_dr(0 to NUM_READERS-1), + instance_handle_dds => instance_handle_ri_dr(0 to NUM_READERS-1), + max_samples_dds => max_samples_ri_dr(0 to NUM_READERS-1), + get_data_dds => get_data_ri_dr(0 to NUM_READERS-1), + done_dds => done_dr_ri(0 to NUM_READERS-1), + return_code_dds => return_code_dr_ri(0 to NUM_READERS-1), + valid_out_dds => valid_dr_ri(0 to NUM_READERS-1), + ready_out_dds => ready_ri_dr(0 to NUM_READERS-1), + data_out_dds => data_dr_ri(0 to NUM_READERS-1), + last_word_out_dds => last_word_dr_ri(0 to NUM_READERS-1), + sample_info => sample_info_dr_ri(0 to NUM_READERS-1), + sample_info_valid => sample_info_valid_dr_ri(0 to NUM_READERS-1), + sample_info_ack => sample_info_ack_ri_dr(0 to NUM_READERS-1), + eoc => eoc_dr_ri(0 to NUM_READERS-1), -- Communication Status - status => status_dr_ri(i) + status => status_dr_ri(0 to NUM_READERS-1) ); end generate; diff --git a/src/Tests/testbench.pro b/src/Tests/testbench.pro index b440b28..8bdf860 100644 --- a/src/Tests/testbench.pro +++ b/src/Tests/testbench.pro @@ -209,24 +209,13 @@ analyze Level_0/L0_dds_writer_test2.vhd analyze Level_0/L0_dds_writer_test3.vhd analyze Level_0/L0_dds_writer_test4.vhd analyze Level_0/L0_dds_writer_test5.vhd -analyze Level_0/L0_dds_reader_test1_arzkriu.vhd -analyze Level_0/L0_dds_reader_test1_lrzkriu.vhd -analyze Level_0/L0_dds_reader_test1_lbzkriu.vhd -analyze Level_0/L0_dds_reader_test1_abzkriu.vhd -analyze Level_0/L0_dds_reader_test1_arznriu.vhd -analyze Level_0/L0_dds_reader_test1_arzksiu.vhd -analyze Level_0/L0_dds_reader_test2_arpkriu.vhd -analyze Level_0/L0_dds_reader_test3_arzkriu.vhd -analyze Level_0/L0_dds_reader_test3_arzkrio.vhd -analyze Level_0/L0_dds_reader_test3_arzkrtu.vhd -analyze Level_0/L0_dds_reader_test3_arzkrto.vhd -analyze Level_0/L0_dds_reader_test3_arznriu.vhd -analyze Level_0/L0_dds_reader_test3_arzksto.vhd -analyze Level_0/L0_dds_reader_test4_arzkriu.vhd -analyze Level_0/L0_dds_reader_test4_arznriu.vhd -analyze Level_0/L0_dds_reader_test5_arzkriu.vhd -analyze Level_0/L0_dds_reader_test6_arzkriu.vhd -analyze Level_0/L0_dds_reader_test7_arzkriu.vhd +analyze Level_0/L0_dds_reader_test1.vhd +analyze Level_0/L0_dds_reader_test2.vhd +analyze Level_0/L0_dds_reader_test3.vhd +analyze Level_0/L0_dds_reader_test4.vhd +analyze Level_0/L0_dds_reader_test5.vhd +analyze Level_0/L0_dds_reader_test6.vhd +analyze Level_0/L0_dds_reader_test7.vhd analyze Level_1/L1_Type1_interface_test1.vhd analyze Level_1/L1_Type1_interface_test2.vhd analyze Level_1/L1_Type1_key_holder_test1.vhd @@ -266,24 +255,13 @@ simulate L0_dds_writer_test2 simulate L0_dds_writer_test3 simulate L0_dds_writer_test4 simulate L0_dds_writer_test5 -simulate L0_dds_reader_test1_arzkriu -simulate L0_dds_reader_test1_lrzkriu -simulate L0_dds_reader_test1_lbzkriu -simulate L0_dds_reader_test1_abzkriu -simulate L0_dds_reader_test1_arznriu -simulate L0_dds_reader_test1_arzksiu -simulate L0_dds_reader_test2_arpkriu -simulate L0_dds_reader_test3_arzkriu -simulate L0_dds_reader_test3_arzkrio -simulate L0_dds_reader_test3_arzkrtu -simulate L0_dds_reader_test3_arzkrto -simulate L0_dds_reader_test3_arznriu -simulate L0_dds_reader_test3_arzksto -simulate L0_dds_reader_test4_arzkriu -simulate L0_dds_reader_test4_arznriu -simulate L0_dds_reader_test5_arzkriu -simulate L0_dds_reader_test6_arzkriu -simulate L0_dds_reader_test7_arzkriu +simulate L0_dds_reader_test1 +simulate L0_dds_reader_test2 +simulate L0_dds_reader_test3 +simulate L0_dds_reader_test4 +simulate L0_dds_reader_test5 +simulate L0_dds_reader_test6 +simulate L0_dds_reader_test7 simulate L1_Type1_interface_test1 simulate L1_Type1_interface_test2 simulate L1_Type1_key_holder_test1 diff --git a/src/dds_reader.vhd b/src/dds_reader.vhd index 0e76572..ef336f5 100644 --- a/src/dds_reader.vhd +++ b/src/dds_reader.vhd @@ -10,25 +10,23 @@ use work.rtps_package.all; use work.user_config.all; use work.rtps_config_package.all; --- TODO: Check if sample_cnt is always maintained (also with MAX_SAMPLES_PER_INSTANCE = LENGTH_UNLIMITED) - entity dds_reader is generic ( - -- XXX: Quartus Limitation [VHDL error at : generic "" cannot be used in its own interface list (ID: 10556)] - --ID : ID_TYPE := 0; - TIME_BASED_FILTER_QOS : DURATION_TYPE;-- := ENDPOINT_CONFIG(ID).TIME_BASED_FILTER_QOS; - DEADLINE_QOS : DURATION_TYPE;-- := ENDPOINT_CONFIG(ID).DEADLINE_QOS; - MAX_INSTANCES : std_logic_vector(CDR_LONG_WIDTH-1 downto 0);-- := ENDPOINT_CONFIG(ID).MAX_INSTANCES; - MAX_SAMPLES : std_logic_vector(CDR_LONG_WIDTH-1 downto 0);-- := ENDPOINT_CONFIG(ID).MAX_SAMPLES; - MAX_SAMPLES_PER_INSTANCE : std_logic_vector(CDR_LONG_WIDTH-1 downto 0);-- := ENDPOINT_CONFIG(ID).MAX_SAMPLES_PER_INSTANCE; - HISTORY_QOS : std_logic_vector(CDR_ENUMERATION_WIDTH-1 downto 0);-- := ENDPOINT_CONFIG(ID).HISTORY_QOS; - RELIABILITY_QOS : std_logic_vector(CDR_ENUMERATION_WIDTH-1 downto 0);-- := ENDPOINT_CONFIG(ID).RELIABILITY_QOS; - PRESENTATION_QOS : std_logic_vector(CDR_ENUMERATION_WIDTH-1 downto 0);-- := ENDPOINT_CONFIG(ID).PRESENTATION_QOS; - DESTINATION_ORDER_QOS : std_logic_vector(CDR_ENUMERATION_WIDTH-1 downto 0);-- := ENDPOINT_CONFIG(ID).DESTINATION_ORDER_QOS; - COHERENT_ACCESS : boolean;-- := ENDPOINT_CONFIG(ID).COHERENT_ACCESS; - ORDERED_ACCESS : boolean;-- := ENDPOINT_CONFIG(ID).ORDERED_ACCESS; - WITH_KEY : boolean;-- := ENDPOINT_CONFIG(ID).WITH_KEY; - PAYLOAD_FRAME_SIZE : natural; + NUM_READERS : natural; + CONFIG_ARRAY : QUARTUS_CONFIG_ARRAY_TYPE; + -- TIME_BASED_FILTER_QOS + -- DEADLINE_QOS + -- MAX_INSTANCES + -- MAX_SAMPLES + -- MAX_SAMPLES_PER_INSTANCE + -- HISTORY_QOS + -- RELIABILITY_QOS + -- PRESENTATION_QOS + -- DESTINATION_ORDER_QOS + -- COHERENT_ACCESS + -- ORDERED_ACCESS + -- WITH_KEY + -- MAX_PAYLOAD_SIZE MAX_REMOTE_ENDPOINTS : natural := 50 ); port ( @@ -37,42 +35,44 @@ entity dds_reader is reset : in std_logic; time : in TIME_TYPE; -- FROM RTPS ENDPOINT - start_rtps : in std_logic; - opcode_rtps : in HISTORY_CACHE_OPCODE_TYPE; - ack_rtps : out std_logic; - done_rtps : out std_logic; - ret_rtps : out HISTORY_CACHE_RESPONSE_TYPE; - data_in_rtps : in std_logic_vector(WORD_WIDTH-1 downto 0); - valid_in_rtps : in std_logic; - ready_in_rtps : out std_logic; - last_word_in_rtps : in std_logic; + start_rtps : in std_logic_vector(0 to NUM_READERS-1); + opcode_rtps : in HISTORY_CACHE_OPCODE_ARRAY_TYPE(0 to NUM_READERS-1); + ack_rtps : out std_logic_vector(0 to NUM_READERS-1); + done_rtps : out std_logic_vector(0 to NUM_READERS-1); + ret_rtps : out HISTORY_CACHE_RESPONSE_ARRAY_TYPE(0 to NUM_READERS-1); + data_in_rtps : in WORD_ARRAY_TYPE(0 to NUM_READERS-1); + valid_in_rtps : in std_logic_vector(0 to NUM_READERS-1); + ready_in_rtps : out std_logic_vector(0 to NUM_READERS-1); + last_word_in_rtps : in std_logic_vector(0 to NUM_READERS-1); -- TO USER ENTITY - start_dds : in std_logic; - ack_dds : out std_logic; - opcode_dds : in DDS_READER_OPCODE_TYPE; - instance_state_dds : in std_logic_vector(INSTANCE_STATE_KIND_WIDTH-1 downto 0); - view_state_dds : in std_logic_vector(VIEW_STATE_KIND_WIDTH-1 downto 0); - sample_state_dds : in std_logic_vector(SAMPLE_STATE_KIND_WIDTH-1 downto 0); - instance_handle_dds : in INSTANCE_HANDLE_TYPE; - max_samples_dds : in std_logic_vector(MAX_SAMPLES_WIDTH-1 downto 0); - get_data_dds : in std_logic; - done_dds : out std_logic; - return_code_dds : out std_logic_vector(RETURN_CODE_WIDTH-1 downto 0); - valid_out_dds : out std_logic; - ready_out_dds : in std_logic; - data_out_dds : out std_logic_vector(WORD_WIDTH-1 downto 0); - last_word_out_dds : out std_logic; - sample_info : out SAMPLE_INFO_TYPE; - sample_info_valid : out std_logic; - sample_info_ack : in std_logic; - eoc : out std_logic; + start_dds : in std_logic_vector(0 to NUM_READERS-1); + ack_dds : out std_logic_vector(0 to NUM_READERS-1); + opcode_dds : in DDS_READER_OPCODE_ARRAY_TYPE(0 to NUM_READERS-1); + instance_state_dds : in INSTANCE_STATE_ARRAY_TYPE(0 to NUM_READERS-1); + view_state_dds : in VIEW_STATE_ARRAY_TYPE(0 to NUM_READERS-1); + sample_state_dds : in SAMPLE_STATE_ARRAY_TYPE(0 to NUM_READERS-1); + instance_handle_dds : in INSTANCE_HANDLE_ARRAY_TYPE(0 to NUM_READERS-1); + max_samples_dds : in MAX_SAMPLES_ARRAY_TYPE(0 to NUM_READERS-1); + get_data_dds : in std_logic_vector(0 to NUM_READERS-1); + done_dds : out std_logic_vector(0 to NUM_READERS-1); + return_code_dds : out RETURN_CODE_ARRAY_TYPE(0 to NUM_READERS-1); + valid_out_dds : out std_logic_vector(0 to NUM_READERS-1); + ready_out_dds : in std_logic_vector(0 to NUM_READERS-1); + data_out_dds : out WORD_ARRAY_TYPE(0 to NUM_READERS-1); + last_word_out_dds : out std_logic_vector(0 to NUM_READERS-1); + sample_info : out SAMPLE_INFO_ARRAY_TYPE(0 to NUM_READERS-1); + sample_info_valid : out std_logic_vector(0 to NUM_READERS-1); + sample_info_ack : in std_logic_vector(0 to NUM_READERS-1); + eoc : out std_logic_vector(0 to NUM_READERS-1); -- Communication Status - status : out std_logic_vector(STATUS_KIND_WIDTH-1 downto 0) + status : out STATUS_KIND_ARRAY_TYPE(0 to NUM_READERS-1) ); end entity; architecture arch of dds_reader is + constant CONFIG_ARRAY_T : QUARTUS_CONFIG_ARRAY_TYPE(0 to NUM_READERS-1) := CONFIG_ARRAY; + --*****COMPONENT DECLARATION***** component key_holder is port ( @@ -98,6 +98,32 @@ architecture arch of dds_reader is ); end component; + type NATURAL_ARRAY_TYPE is array (0 to NUM_READERS-1) of natural; + function get_max_samples(qos : QUARTUS_CONFIG_ARRAY_TYPE) return natural is + variable ret : natural := 0; + begin + assert (qos'length = NUM_READERS) severity FAILURE; + for i in 0 to NUM_READERS-1 loop + if (unsigned(qos(i).MAX_SAMPLES) > ret) then + ret := to_integer(unsigned(qos(i).MAX_SAMPLES)); + end if; + end loop; + return ret; + end function; + type MAX_SAMPLES_NATURAL_ARRAY_TYPE is array (0 to NUM_READERS-1) of natural range 0 to get_max_samples(CONFIG_ARRAY_T)+1; + function get_max_instances(qos : QUARTUS_CONFIG_ARRAY_TYPE) return natural is + variable ret : natural := 0; + begin + assert (qos'length = NUM_READERS) severity FAILURE; + for i in 0 to NUM_READERS-1 loop + if (unsigned(qos(i).MAX_INSTANCES) > ret) then + ret := to_integer(unsigned(qos(i).MAX_INSTANCES)); + end if; + end loop; + return ret; + end function; + type MAX_INSTANCES_NATURAL_ARRAY_TYPE is array (0 to NUM_READERS-1) of natural range 0 to get_max_instances(CONFIG_ARRAY_T); + --*****CONSTANT DECLARATION***** -- NOTE: Because we need to first determine the Instance before making the ACCEPT/REJECT/DROP decision -- we need to latch the cache change first, calculate the Key Hash if necessary, fetch the associated @@ -105,59 +131,147 @@ architecture arch of dds_reader is -- payload memory that is only used as a latch. -- *SAMPLE MEMORY* -- 4-Byte Word Size of a Sample Info Entry in Memory - function gen_sample_frame_size(WITH_KEY : boolean) return natural is - variable ret : natural := 0; - begin - if (WITH_KEY) then - return 11; - else - return 10; - end if; - end function; - constant SAMPLE_FRAME_SIZE : natural := gen_sample_frame_size(WITH_KEY); + constant SAMPLE_FRAME_SIZE : natural := 11; -- Sample Info Memory Size in 4-Byte Words - constant SAMPLE_MEMORY_SIZE : natural := to_integer(unsigned(MAX_SAMPLES)+1) * SAMPLE_FRAME_SIZE; + function gen_sample_memory_size(qos : QUARTUS_CONFIG_ARRAY_TYPE; size : natural) return NATURAL_ARRAY_TYPE is + variable ret : NATURAL_ARRAY_TYPE; + begin + assert (qos'length = NUM_READERS) severity FAILURE; + + for i in 0 to NUM_READERS-1 loop + ret(i) := to_integer(unsigned(qos(i).MAX_SAMPLES)+1) * size; + end loop; + + return ret; + end function; + constant SAMPLE_MEMORY_SIZE : NATURAL_ARRAY_TYPE := gen_sample_memory_size(CONFIG_ARRAY_T,SAMPLE_FRAME_SIZE); -- Sample Info Memory Address Width - constant SAMPLE_MEMORY_ADDR_WIDTH : natural := log2c(SAMPLE_MEMORY_SIZE); + function get_max_sample_memory_size(sizes : NATURAL_ARRAY_TYPE) return natural is + variable ret : natural := 0; + begin + for i in 0 to NUM_READERS-1 loop + if (sizes(i) > ret) then + ret := sizes(i); + end if; + end loop; + return ret; + end function; + constant SAMPLE_MEMORY_ADDR_WIDTH : natural := log2c(get_max_sample_memory_size(SAMPLE_MEMORY_SIZE)); + type SAMPLE_MEMORY_ADDR_ARRAY_TYPE is array (0 to NUM_READERS-1) of unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0); -- Highest Sample Info Memory Address - constant SAMPLE_MEMORY_MAX_ADDRESS : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) := to_unsigned(SAMPLE_MEMORY_SIZE-1, SAMPLE_MEMORY_ADDR_WIDTH); + constant SAMPLE_MEMORY_MAX_ADDRESS : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) := to_unsigned(get_max_sample_memory_size(SAMPLE_MEMORY_SIZE)-1, SAMPLE_MEMORY_ADDR_WIDTH); -- Highest Sample Info Frame Address - constant MAX_SAMPLE_ADDRESS : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) := SAMPLE_MEMORY_MAX_ADDRESS - SAMPLE_FRAME_SIZE + 1; + function gen_max_sample_address(sizes : NATURAL_ARRAY_TYPE; size : natural) return SAMPLE_MEMORY_ADDR_ARRAY_TYPE is + variable ret : SAMPLE_MEMORY_ADDR_ARRAY_TYPE; + begin + for i in 0 to NUM_READERS-1 loop + ret(i) := to_unsigned(sizes(i) - size, SAMPLE_MEMORY_ADDR_WIDTH); + end loop; + return ret; + end function; + constant MAX_SAMPLE_ADDRESS : SAMPLE_MEMORY_ADDR_ARRAY_TYPE := gen_max_sample_address(SAMPLE_MEMORY_SIZE, SAMPLE_FRAME_SIZE); -- Address pointing to the beginning of the first Sample Data Frame constant FIRST_SAMPLE_ADDRESS : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); -- *PAYLOAD MEMORY* + function gen_payload_frame_size(qos : QUARTUS_CONFIG_ARRAY_TYPE) return NATURAL_ARRAY_TYPE is + variable ret : NATURAL_ARRAY_TYPE; + begin + assert (qos'length = NUM_READERS) severity FAILURE; + + for i in 0 to NUM_READERS-1 loop + ret(i) := round_div(qos(i).MAX_PAYLOAD_SIZE + 4, WORD_WIDTH/BYTE_WIDTH); -- (+ NEXT ADDR Field) + end loop; + + return ret; + end function; + constant PAYLOAD_FRAME_SIZE : NATURAL_ARRAY_TYPE := gen_payload_frame_size(CONFIG_ARRAY_T); -- Payload Memory Size in 4-Byte Words - constant PAYLOAD_MEMORY_SIZE : natural := to_integer(unsigned(MAX_SAMPLES)+1) * PAYLOAD_FRAME_SIZE; + function gen_payload_memory_size(qos : QUARTUS_CONFIG_ARRAY_TYPE; size : NATURAL_ARRAY_TYPE) return NATURAL_ARRAY_TYPE is + variable ret : NATURAL_ARRAY_TYPE; + begin + assert (qos'length = NUM_READERS) severity FAILURE; + + for i in 0 to NUM_READERS-1 loop + ret(i) := to_integer(unsigned(qos(i).MAX_SAMPLES)+1) * size(i); + end loop; + + return ret; + end function; + constant PAYLOAD_MEMORY_SIZE : NATURAL_ARRAY_TYPE := gen_payload_memory_size(CONFIG_ARRAY_T, PAYLOAD_FRAME_SIZE); -- Payload Memory Address Width - constant PAYLOAD_MEMORY_ADDR_WIDTH : natural := log2c(PAYLOAD_MEMORY_SIZE); + function get_max_payload_memory_size(sizes : NATURAL_ARRAY_TYPE) return natural is + variable ret : natural := 0; + begin + for i in 0 to NUM_READERS-1 loop + if (sizes(i) > ret) then + ret := sizes(i); + end if; + end loop; + return ret; + end function; + constant PAYLOAD_MEMORY_ADDR_WIDTH : natural := log2c(get_max_payload_memory_size(PAYLOAD_MEMORY_SIZE)); + type PAYLOAD_MEMORY_ADDR_ARRAY_TYPE is array (0 to NUM_READERS-1) of unsigned(PAYLOAD_MEMORY_ADDR_WIDTH-1 downto 0); -- Highest Payload Memory Address - constant PAYLOAD_MEMORY_MAX_ADDRESS : unsigned(PAYLOAD_MEMORY_ADDR_WIDTH-1 downto 0) := to_unsigned(PAYLOAD_MEMORY_SIZE-1, PAYLOAD_MEMORY_ADDR_WIDTH); + constant PAYLOAD_MEMORY_MAX_ADDRESS : unsigned(PAYLOAD_MEMORY_ADDR_WIDTH-1 downto 0) := to_unsigned(get_max_payload_memory_size(PAYLOAD_MEMORY_SIZE)-1, PAYLOAD_MEMORY_ADDR_WIDTH); -- Highest Payload Frame Address - constant MAX_PAYLOAD_ADDRESS : unsigned(PAYLOAD_MEMORY_ADDR_WIDTH-1 downto 0) := PAYLOAD_MEMORY_MAX_ADDRESS - PAYLOAD_FRAME_SIZE + 1; + function gen_max_payload_address(sizes : NATURAL_ARRAY_TYPE; size : NATURAL_ARRAY_TYPE) return PAYLOAD_MEMORY_ADDR_ARRAY_TYPE is + variable ret : PAYLOAD_MEMORY_ADDR_ARRAY_TYPE; + begin + for i in 0 to NUM_READERS-1 loop + ret(i) := to_unsigned(sizes(i) - size(i), PAYLOAD_MEMORY_ADDR_WIDTH); + end loop; + return ret; + end function; + constant MAX_PAYLOAD_ADDRESS : PAYLOAD_MEMORY_ADDR_ARRAY_TYPE := gen_max_payload_address(PAYLOAD_MEMORY_SIZE, PAYLOAD_FRAME_SIZE); -- Address pointing to the beginning of the first Payload Data Frame constant FIRST_PAYLOAD_ADDRESS : unsigned(PAYLOAD_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); -- *INSTANCE MEMORY* -- 4-Byte Word Size of a Instance Entry in Memory - function gen_inst_frame_size(time_based_filter : DURATION_TYPE) return natural is - variable ret : natural := 0; - begin - if (time_based_filter = DURATION_ZERO) then - return 10 + round_div(MAX_REMOTE_ENDPOINTS, WORD_WIDTH); - else - return 12 + round_div(MAX_REMOTE_ENDPOINTS, WORD_WIDTH); - end if; - end function; - constant INSTANCE_FRAME_SIZE : natural := gen_inst_frame_size(TIME_BASED_FILTER_QOS); + constant INSTANCE_FRAME_SIZE : natural := 12 + round_div(MAX_REMOTE_ENDPOINTS, WORD_WIDTH); -- Instance Memory Size in 4-Byte Words - constant INSTANCE_MEMORY_SIZE : natural := to_integer(unsigned(MAX_INSTANCES)) * INSTANCE_FRAME_SIZE; + function gen_instance_memory_size(qos : QUARTUS_CONFIG_ARRAY_TYPE; size : natural) return NATURAL_ARRAY_TYPE is + variable ret : NATURAL_ARRAY_TYPE; + begin + assert (qos'length = NUM_READERS) severity FAILURE; + + for i in 0 to NUM_READERS-1 loop + if (qos(i).WITH_KEY) then + ret(i) := to_integer(unsigned(qos(i).MAX_INSTANCES)) * size; + else + ret(i) := size; + end if; + end loop; + + return ret; + end function; + constant INSTANCE_MEMORY_SIZE : NATURAL_ARRAY_TYPE := gen_instance_memory_size(CONFIG_ARRAY_T, INSTANCE_FRAME_SIZE); -- Instance Memory Address Width - constant INSTANCE_MEMORY_ADDR_WIDTH : natural := log2c(INSTANCE_MEMORY_SIZE); + function get_max_instance_memory_size(sizes : NATURAL_ARRAY_TYPE) return natural is + variable ret : natural := 0; + begin + for i in 0 to NUM_READERS-1 loop + if (sizes(i) > ret) then + ret := sizes(i); + end if; + end loop; + return ret; + end function; + constant INSTANCE_MEMORY_ADDR_WIDTH : natural := log2c(get_max_instance_memory_size(INSTANCE_MEMORY_SIZE)); + type INSTANCE_MEMORY_ADDR_ARRAY_TYPE is array (0 to NUM_READERS-1) of unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0); -- Highest Instance Memory Address - constant INSTANCE_MEMORY_MAX_ADDRESS: unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0) := to_unsigned(INSTANCE_MEMORY_SIZE-1, INSTANCE_MEMORY_ADDR_WIDTH); + constant INSTANCE_MEMORY_MAX_ADDRESS: unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0) := to_unsigned(get_max_instance_memory_size(INSTANCE_MEMORY_SIZE)-1, INSTANCE_MEMORY_ADDR_WIDTH); -- Highest Instance Frame Address - constant MAX_INSTANCE_ADDRESS : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0) := INSTANCE_MEMORY_MAX_ADDRESS - INSTANCE_FRAME_SIZE + 1; + function gen_max_instance_address(sizes : NATURAL_ARRAY_TYPE; size : natural) return INSTANCE_MEMORY_ADDR_ARRAY_TYPE is + variable ret : INSTANCE_MEMORY_ADDR_ARRAY_TYPE; + begin + for i in 0 to NUM_READERS-1 loop + ret(i) := to_unsigned(sizes(i) - size, INSTANCE_MEMORY_ADDR_WIDTH); + end loop; + return ret; + end function; + constant MAX_INSTANCE_ADDRESS : INSTANCE_MEMORY_ADDR_ARRAY_TYPE := gen_max_instance_address(INSTANCE_MEMORY_SIZE, INSTANCE_FRAME_SIZE); -- Address pointing to the beginning of the first Instance Data Frame constant FIRST_INSTANCE_ADDRESS : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); @@ -168,20 +282,10 @@ architecture arch of dds_reader is constant SMF_LIFESPAN_DEADLINE_OFFSET : natural := 3; constant SMF_PAYLOAD_ADDR_OFFSET : natural := 5; constant SMF_INSTANCE_ADDR_OFFSET : natural := 6; - function gen_smf_disposed_gen_cnt_offset(WITH_KEY : boolean) return natural is - variable ret : natural := 0; - begin - if (WITH_KEY) then - ret := SMF_INSTANCE_ADDR_OFFSET + 1; - else - ret := SMF_INSTANCE_ADDR_OFFSET; - end if; - return ret; - end function; - constant SMF_DISPOSED_GEN_CNT_OFFSET : natural := gen_smf_disposed_gen_cnt_offset(WITH_KEY); - constant SMF_NO_WRITERS_GEN_CNT_OFFSET : natural := SMF_DISPOSED_GEN_CNT_OFFSET + 1; - constant SMF_PREV_ADDR_OFFSET : natural := SMF_NO_WRITERS_GEN_CNT_OFFSET + 1; - constant SMF_NEXT_ADDR_OFFSET : natural := SMF_PREV_ADDR_OFFSET + 1; + constant SMF_DISPOSED_GEN_CNT_OFFSET : natural := 7; + constant SMF_NO_WRITERS_GEN_CNT_OFFSET : natural := 8; + constant SMF_PREV_ADDR_OFFSET : natural := 9; + constant SMF_NEXT_ADDR_OFFSET : natural := 10; -- *PAYLOAD MEMORY FRAME FIELD OFFSETS* -- 4-Byte Word Offsets to Beginning of Respective Fields in the Endpoint Memory Frame @@ -198,17 +302,7 @@ architecture arch of dds_reader is constant IMF_DISPOSED_GEN_CNT_OFFSET : natural := 8; constant IMF_NO_WRITERS_GEN_CNT_OFFSET : natural := 9; constant IMF_IGNORE_DEADLINE_OFFSET : natural := 10; - function gen_imf_writer_bitmap_offset(time_based_filter : DURATION_TYPE) return natural is - variable ret : natural := 0; - begin - if (time_based_filter /= DURATION_ZERO) then - ret := IMF_IGNORE_DEADLINE_OFFSET+2; - else - ret := IMF_IGNORE_DEADLINE_OFFSET; - end if; - return ret; - end function; - constant IMF_WRITER_BITMAP_OFFSET : natural := gen_imf_writer_bitmap_offset(TIME_BASED_FILTER_QOS); + constant IMF_WRITER_BITMAP_OFFSET : natural := 12; -- *INSTANCE MEMORY FRAME FIELD FLAGS* -- Flags mapping to the respective Endpoint Memory Frame Fields @@ -252,6 +346,7 @@ architecture arch of dds_reader is constant WRITER_BITMAP_WIDTH : natural := WRITER_BITMAP_ARRAY_TYPE'length*WORD_WIDTH; -- Record of Instance Data type INSTANCE_DATA_TYPE is record + i : natural; addr : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0); key_hash : KEY_HASH_TYPE; status_info : std_logic_vector(WORD_WIDTH-1 downto 0); @@ -264,6 +359,7 @@ architecture arch of dds_reader is end record; -- Zero initialized Endpoint Data constant ZERO_INSTANCE_DATA : INSTANCE_DATA_TYPE := ( + i => 0, addr => INSTANCE_MEMORY_MAX_ADDRESS, key_hash => KEY_HASH_NIL, status_info => (others => '0'), @@ -283,6 +379,12 @@ architecture arch of dds_reader is signal sample_ready_in, sample_valid_in : std_logic; signal sample_ready_out, sample_valid_out : std_logic; signal sample_abort_read : std_logic; + signal sample_addr_i : SAMPLE_MEMORY_ADDR_ARRAY_TYPE; + signal sample_read_i : std_logic_vector(0 to NUM_READERS-1); + signal sample_read_data_i, sample_write_data_i : WORD_ARRAY_TYPE(0 to NUM_READERS-1); + signal sample_ready_in_i, sample_valid_in_i : std_logic_vector(0 to NUM_READERS-1); + signal sample_ready_out_i, sample_valid_out_i : std_logic_vector(0 to NUM_READERS-1); + signal sample_abort_read_i : std_logic_vector(0 to NUM_READERS-1); -- *PAYLOAD MEMORY CONNECTION SIGNALS* signal payload_addr : unsigned(PAYLOAD_MEMORY_ADDR_WIDTH-1 downto 0); @@ -291,6 +393,12 @@ architecture arch of dds_reader is signal payload_ready_in, payload_valid_in : std_logic; signal payload_ready_out, payload_valid_out : std_logic; signal payload_abort_read : std_logic; + signal payload_addr_i : PAYLOAD_MEMORY_ADDR_ARRAY_TYPE; + signal payload_read_i : std_logic_vector(0 to NUM_READERS-1); + signal payload_read_data_i, payload_write_data_i : WORD_ARRAY_TYPE(0 to NUM_READERS-1); + signal payload_ready_in_i, payload_valid_in_i : std_logic_vector(0 to NUM_READERS-1); + signal payload_ready_out_i, payload_valid_out_i : std_logic_vector(0 to NUM_READERS-1); + signal payload_abort_read_i : std_logic_vector(0 to NUM_READERS-1); -- *INSTANCE MEMORY CONNECTION SIGNALS* signal inst_addr : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0); @@ -299,11 +407,17 @@ architecture arch of dds_reader is signal inst_ready_in, inst_valid_in : std_logic; signal inst_ready_out, inst_valid_out : std_logic; signal inst_abort_read : std_logic; + signal inst_addr_i : INSTANCE_MEMORY_ADDR_ARRAY_TYPE; + signal inst_read_i : std_logic_vector(0 to NUM_READERS-1); + signal inst_read_data_i, inst_write_data_i : WORD_ARRAY_TYPE(0 to NUM_READERS-1); + signal inst_ready_in_i, inst_valid_in_i : std_logic_vector(0 to NUM_READERS-1); + signal inst_ready_out_i, inst_valid_out_i : std_logic_vector(0 to NUM_READERS-1); + signal inst_abort_read_i : std_logic_vector(0 to NUM_READERS-1); -- *KEY HOLDER CONNECTION SIGNALS* - signal start_kh, ack_kh, valid_in_kh, ready_in_kh, last_word_in_kh, valid_out_kh, ready_out_kh, last_word_out_kh, abort_kh : std_logic; - signal opcode_kh : KEY_HOLDER_OPCODE_TYPE; - signal data_in_kh, data_out_kh : std_logic_vector(WORD_WIDTH-1 downto 0); + signal start_kh, ack_kh, valid_in_kh, ready_in_kh, last_word_in_kh, valid_out_kh, ready_out_kh, last_word_out_kh, abort_kh : std_logic_vector(0 to NUM_READERS-1); + signal opcode_kh : KEY_HOLDER_OPCODE_ARRAY_TYPE(0 to NUM_READERS-1); + signal data_in_kh, data_out_kh : WORD_ARRAY_TYPE(0 to NUM_READERS-1); -- *MAIN PROCESS* -- FSM state @@ -311,21 +425,21 @@ architecture arch of dds_reader is -- General Purpose Counter signal cnt, cnt_next : natural range 0 to 18; -- Counter used to read/write Payload Fames - signal cnt2, cnt2_next : natural range 0 to PAYLOAD_FRAME_SIZE; + signal cnt2, cnt2_next : natural range 0 to get_max_payload_memory_size(PAYLOAD_FRAME_SIZE); -- Counter used to read/write Payload Fames - signal cnt3, cnt3_next : natural range 0 to PAYLOAD_FRAME_SIZE; + signal cnt3, cnt3_next : natural range 0 to get_max_payload_memory_size(PAYLOAD_FRAME_SIZE); -- Head of Empty Sample List - signal empty_sample_list_head, empty_sample_list_head_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0); + signal empty_sample_list_head, empty_sample_list_head_next : SAMPLE_MEMORY_ADDR_ARRAY_TYPE; -- Tail of Empty Sample List - signal empty_sample_list_tail, empty_sample_list_tail_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0); + signal empty_sample_list_tail, empty_sample_list_tail_next : SAMPLE_MEMORY_ADDR_ARRAY_TYPE; -- Head of Empty Payload List - signal empty_payload_list_head, empty_payload_list_head_next : unsigned(PAYLOAD_MEMORY_ADDR_WIDTH-1 downto 0); + signal empty_payload_list_head, empty_payload_list_head_next : PAYLOAD_MEMORY_ADDR_ARRAY_TYPE; -- Oldest Sample (Head of Occupied Sample List) - signal oldest_sample, oldest_sample_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0); + signal oldest_sample, oldest_sample_next : SAMPLE_MEMORY_ADDR_ARRAY_TYPE; -- Newest Sample (Tail of Occupied Sample List) - signal newest_sample, newest_sample_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0); + signal newest_sample, newest_sample_next : SAMPLE_MEMORY_ADDR_ARRAY_TYPE; -- Highest Timestamp of all READ Samples - signal last_read_ts, last_read_ts_next : TIME_TYPE; + signal last_read_ts, last_read_ts_next : TIME_ARRAY_TYPE(0 to NUM_READERS-1); -- Denotes if the oldest Sample should be removed signal remove_oldest_sample, remove_oldest_sample_next : std_logic; -- Denotes if the oldest sample of the Instance with 'key_hash' should be removed @@ -404,9 +518,7 @@ architecture arch of dds_reader is -- Denotes if the READ/TAKE operation does not apply to a specific Instance signal dynamic_next_instance, dynamic_next_instance_next : std_logic; -- Signal containing the number of currently stale Instances - signal stale_inst_cnt, stale_inst_cnt_next : natural range 0 to to_integer(unsigned(MAX_INSTANCES))-1; - -- Test signal used for testbench synchronisation - signal idle_sig : std_logic; + signal stale_inst_cnt, stale_inst_cnt_next : MAX_INSTANCES_NATURAL_ARRAY_TYPE; -- Signal denoting if the PRE_CALCULATE stage was run for the current instance signal pre_calculated, pre_calculated_next : std_logic; -- Disposed Generation Count Latch @@ -421,20 +533,28 @@ architecture arch of dds_reader is signal trigger_sample_gen, trigger_sample_gen_next : std_logic; -- Waits for Sample Removal (MAX_SAMPLES Limit lift) to trigger Sample Generation signal wait_for_sample_removal, wait_for_sample_removal_next : std_logic; + -- Signal used to index the readers + signal ind, ind_next : natural range 0 to NUM_READERS-1; + -- Test signals used in testbenches + signal idle_sig : std_logic; + signal empty_inst_head_sig : NATURAL_ARRAY_TYPE; + signal empty_sample_head_sig : NATURAL_ARRAY_TYPE; + signal empty_payload_head_sig : NATURAL_ARRAY_TYPE; -- *COMMUNICATION STATUS* - signal status_sig, status_sig_next : std_logic_vector(STATUS_KIND_WIDTH-1 downto 0); + signal status_sig, status_sig_next : STATUS_KIND_ARRAY_TYPE(0 to NUM_READERS-1); -- SAMPLE REJECT STATUS - signal sample_rej_cnt, sample_rej_cnt_next : unsigned(SAMPLE_REJECTED_STATUS_COUNT_WIDTH-1 downto 0); - signal sample_rej_cnt_change, sample_rej_cnt_change_next : unsigned(SAMPLE_REJECTED_STATUS_COUNT_WIDTH-1 downto 0); - signal sample_rej_last_reason, sample_rej_last_reason_next : std_logic_vector(CDR_ENUMERATION_WIDTH-1 downto 0); - signal sample_rej_last_inst, sample_rej_last_inst_next : INSTANCE_HANDLE_TYPE; + signal sample_rej_cnt, sample_rej_cnt_next : SAMPLE_REJECTED_STATUS_COUNT_ARRAY_TYPE(0 to NUM_READERS-1); + signal sample_rej_cnt_change, sample_rej_cnt_change_next : SAMPLE_REJECTED_STATUS_COUNT_ARRAY_TYPE(0 to NUM_READERS-1); + signal sample_rej_last_reason, sample_rej_last_reason_next : CDR_ENUMERATION_ARRAY_TYPE(0 to NUM_READERS-1); + signal sample_rej_last_inst, sample_rej_last_inst_next : INSTANCE_HANDLE_ARRAY_TYPE(0 to NUM_READERS-1); -- REQUESTED DEADLINE MISSED STATUS -- Time of next Deadline Miss Check - signal deadline_time, deadline_time_next : TIME_TYPE; - signal deadline_miss_cnt, deadline_miss_cnt_next : unsigned(REQUESTED_DEADLINE_MISSED_STATUS_COUNT_WIDTH-1 downto 0); - signal deadline_miss_cnt_change, deadline_miss_cnt_change_next : unsigned(REQUESTED_DEADLINE_MISSED_STATUS_COUNT_WIDTH-1 downto 0); - signal deadline_miss_last_inst, deadline_miss_last_inst_next : INSTANCE_HANDLE_TYPE; + signal deadline_check_time , deadline_check_time_next : TIME_TYPE; + signal deadline_time, deadline_time_next : TIME_ARRAY_TYPE(0 to NUM_READERS-1); + signal deadline_miss_cnt, deadline_miss_cnt_next : REQUESTED_DEADLINE_MISSED_STATUS_COUNT_ARRAY_TYPE(0 to NUM_READERS-1); + signal deadline_miss_cnt_change, deadline_miss_cnt_change_next : REQUESTED_DEADLINE_MISSED_STATUS_COUNT_ARRAY_TYPE(0 to NUM_READERS-1); + signal deadline_miss_last_inst, deadline_miss_last_inst_next : INSTANCE_HANDLE_ARRAY_TYPE(0 to NUM_READERS-1); -- *SAMPLE INFO* signal sample_info_sig, sample_info_sig_next : SAMPLE_INFO_TYPE; @@ -461,15 +581,13 @@ architecture arch of dds_reader is -- General Purpose Instance Memory Address Latch signal inst_addr_latch, inst_addr_latch_next : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0); -- Head of Empty Instance List - signal inst_empty_head, inst_empty_head_next : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0); + signal inst_empty_head, inst_empty_head_next : INSTANCE_MEMORY_ADDR_ARRAY_TYPE; -- Head of Occupied Instance List - signal inst_occupied_head, inst_occupied_head_next : unsigned(INSTANCE_MEMORY_ADDR_WIDTH-1 downto 0); + signal inst_occupied_head, inst_occupied_head_next : INSTANCE_MEMORY_ADDR_ARRAY_TYPE; -- Latch for Instance Data from main process signal inst_latch_data, inst_latch_data_next : INSTANCE_DATA_TYPE; - -- NOTE: The next signal is driven by the inst_ctrl_prc. In case WITH_KEY is FALSE, no inst_ctrl_prc is generated and the inst_data is - -- set by the main process directly by drivng the next2 signal. The sync_prc is responsible for latching the corrct next signal. -- Latch for Instance Data from memory - signal inst_data, inst_data_next, inst_data_next2 : INSTANCE_DATA_TYPE; + signal inst_data, inst_data_next : INSTANCE_DATA_TYPE; -- General Purpose Counter signal inst_cnt, inst_cnt_next : natural range 0 to 21; -- Counter used to read/write the Writer Bitmap @@ -552,106 +670,177 @@ begin --*****COMPONENT INSTANTIATION***** - key_holder_inst : key_holder - port map ( - -- SYSTEM - clk => clk, - reset => reset, - -- CONTROL - start => start_kh, - opcode => opcode_kh, - ack => ack_kh, - decode_error => open, - abort => abort_kh, - -- INPUT - ready_in => ready_out_kh, - valid_in => valid_out_kh, - data_in => data_out_kh, - last_word_in => last_word_out_kh, - -- OUTPUT - ready_out => ready_in_kh, - valid_out => valid_in_kh, - data_out => data_in_kh, - last_word_out => last_word_in_kh - ); + key_holder_gen : for i in 0 to NUM_READERS-1 generate + key_holder_inst : key_holder + port map ( + -- SYSTEM + clk => clk, + reset => reset, + -- CONTROL + start => start_kh(i), + opcode => opcode_kh(i), + ack => ack_kh(i), + decode_error => open, + abort => abort_kh(i), + -- INPUT + ready_in => ready_out_kh(i), + valid_in => valid_out_kh(i), + data_in => data_out_kh(i), + last_word_in => last_word_out_kh(i), + -- OUTPUT + ready_out => ready_in_kh(i), + valid_out => valid_in_kh(i), + data_out => data_in_kh(i), + last_word_out => last_word_in_kh(i) + ); + end generate; - sample_mem_ctrl_inst : entity work.mem_ctrl(arch) - generic map ( - ADDR_WIDTH => SAMPLE_MEMORY_ADDR_WIDTH, - DATA_WIDTH => WORD_WIDTH, - MEMORY_DEPTH => SAMPLE_MEMORY_SIZE, - MAX_BURST_LENGTH => SAMPLE_FRAME_SIZE - ) - port map ( - clk => clk, - reset => reset or sample_abort_read, - addr => std_logic_vector(sample_addr), - read => sample_read, - ready_in => sample_ready_in, - valid_in => sample_valid_in, - data_in => sample_write_data, - ready_out => sample_ready_out, - valid_out => sample_valid_out, - data_out => sample_read_data - ); + sample_mem_ctrl_gen : for i in 0 to NUM_READERS-1 generate + sample_mem_ctrl_inst : entity work.mem_ctrl(arch) + generic map ( + ADDR_WIDTH => SAMPLE_MEMORY_ADDR_WIDTH, + DATA_WIDTH => WORD_WIDTH, + MEMORY_DEPTH => SAMPLE_MEMORY_SIZE(i), + MAX_BURST_LENGTH => SAMPLE_FRAME_SIZE + ) + port map ( + clk => clk, + reset => reset or sample_abort_read_i(i), + addr => std_logic_vector(sample_addr_i(i)), + read => sample_read_i(i), + ready_in => sample_ready_in_i(i), + valid_in => sample_valid_in_i(i), + data_in => sample_write_data_i(i), + ready_out => sample_ready_out_i(i), + valid_out => sample_valid_out_i(i), + data_out => sample_read_data_i(i) + ); + end generate; - payload_mem_ctrl_inst : entity work.mem_ctrl(arch) - generic map ( - ADDR_WIDTH => PAYLOAD_MEMORY_ADDR_WIDTH, - DATA_WIDTH => WORD_WIDTH, - MEMORY_DEPTH => PAYLOAD_MEMORY_SIZE, - MAX_BURST_LENGTH => PAYLOAD_FRAME_SIZE - ) - port map ( - clk => clk, - reset => reset or payload_abort_read, - addr => std_logic_vector(payload_addr), - read => payload_read, - ready_in => payload_ready_in, - valid_in => payload_valid_in, - data_in => payload_write_data, - ready_out => payload_ready_out, - valid_out => payload_valid_out, - data_out => payload_read_data - ); + payload_mem_ctrl_gen : for i in 0 to NUM_READERS-1 generate + payload_mem_ctrl_inst : entity work.mem_ctrl(arch) + generic map ( + ADDR_WIDTH => PAYLOAD_MEMORY_ADDR_WIDTH, + DATA_WIDTH => WORD_WIDTH, + MEMORY_DEPTH => PAYLOAD_MEMORY_SIZE(i), + MAX_BURST_LENGTH => PAYLOAD_FRAME_SIZE(i) + ) + port map ( + clk => clk, + reset => reset or payload_abort_read_i(i), + addr => std_logic_vector(payload_addr_i(i)), + read => payload_read_i(i), + ready_in => payload_ready_in_i(i), + valid_in => payload_valid_in_i(i), + data_in => payload_write_data_i(i), + ready_out => payload_ready_out_i(i), + valid_out => payload_valid_out_i(i), + data_out => payload_read_data_i(i) + ); + end generate; - gen_instance_mem_ctrl_inst : if WITH_KEY generate + instance_mem_ctrl_gen : for i in 0 to NUM_READERS-1 generate instance_mem_ctrl_inst : entity work.mem_ctrl(arch) generic map ( ADDR_WIDTH => INSTANCE_MEMORY_ADDR_WIDTH, DATA_WIDTH => WORD_WIDTH, - MEMORY_DEPTH => INSTANCE_MEMORY_SIZE, + MEMORY_DEPTH => INSTANCE_MEMORY_SIZE(i), MAX_BURST_LENGTH => INSTANCE_FRAME_SIZE ) port map ( clk => clk, - reset => reset or inst_abort_read, - addr => std_logic_vector(inst_addr), - read => inst_read, - ready_in => inst_ready_in, - valid_in => inst_valid_in, - data_in => inst_write_data, - ready_out => inst_ready_out, - valid_out => inst_valid_out, - data_out => inst_read_data + reset => reset or inst_abort_read_i(i), + addr => std_logic_vector(inst_addr_i(i)), + read => inst_read_i(i), + ready_in => inst_ready_in_i(i), + valid_in => inst_valid_in_i(i), + data_in => inst_write_data_i(i), + ready_out => inst_ready_out_i(i), + valid_out => inst_valid_out_i(i), + data_out => inst_read_data_i(i) ); end generate; - sample_info.sample_state <= si_sample_state_sig; - sample_info.view_state <= si_view_state_sig; - sample_info.instance_state <= si_instance_state_sig; - sample_info.source_timestamp <= si_source_timestamp_sig; - sample_info.instance_handle <= si_instance_handle_sig; - sample_info.publication_handle <= si_publication_handle_sig; - sample_info.disposed_generation_count <= si_disposed_generation_count_sig; - sample_info.no_writers_generation_count <= si_no_writers_generation_count_sig; - sample_info.sample_rank <= std_logic_vector(si_sample_rank_sig); - sample_info.generation_rank <= std_logic_vector(si_generation_rank_sig); - sample_info.absolute_generation_rank <= std_logic_vector(si_absolute_generation_rank_sig); - sample_info.valid_data <= si_valid_data_sig; - sample_info_valid <= si_valid_sig; - eoc <= eoc_sig; - status <= status_sig; + inst_memory_mux : process (all) + begin + inst_abort_read_i <= (others => '0'); + inst_addr_i <= (others => (others => '0')); + inst_read_i <= (others => '0'); + inst_valid_in_i <= (others => '0'); + inst_write_data_i <= (others => (others => '0')); + inst_ready_out_i <= (others => '0'); + + inst_abort_read_i(inst_latch_data.i) <= inst_abort_read; + inst_addr_i(inst_latch_data.i) <= inst_addr; + inst_read_i(inst_latch_data.i) <= inst_read; + inst_valid_in_i(inst_latch_data.i) <= inst_valid_in; + inst_write_data_i(inst_latch_data.i) <= inst_write_data; + inst_ready_out_i(inst_latch_data.i) <= inst_ready_out; + + inst_ready_in <= inst_ready_in_i(inst_latch_data.i); + inst_valid_out <= inst_valid_out_i(inst_latch_data.i); + inst_read_data <= inst_read_data_i(inst_latch_data.i); + end process; + + sample_memory_mux : process (all) + begin + sample_abort_read_i <= (others => '0'); + sample_addr_i <= (others => (others => '0')); + sample_read_i <= (others => '0'); + sample_valid_in_i <= (others => '0'); + sample_write_data_i <= (others => (others => '0')); + sample_ready_out_i <= (others => '0'); + + sample_abort_read_i(ind) <= sample_abort_read; + sample_addr_i(ind) <= sample_addr; + sample_read_i(ind) <= sample_read; + sample_valid_in_i(ind) <= sample_valid_in; + sample_write_data_i(ind) <= sample_write_data; + sample_ready_out_i(ind) <= sample_ready_out; + + sample_ready_in <= sample_ready_in_i(ind); + sample_valid_out <= sample_valid_out_i(ind); + sample_read_data <= sample_read_data_i(ind); + end process; + + payload_memory_mux : process (all) + begin + payload_abort_read_i <= (others => '0'); + payload_addr_i <= (others => (others => '0')); + payload_read_i <= (others => '0'); + payload_valid_in_i <= (others => '0'); + payload_write_data_i <= (others => (others => '0')); + payload_ready_out_i <= (others => '0'); + + payload_abort_read_i(ind) <= payload_abort_read; + payload_addr_i(ind) <= payload_addr; + payload_read_i(ind) <= payload_read; + payload_valid_in_i(ind) <= payload_valid_in; + payload_write_data_i(ind) <= payload_write_data; + payload_ready_out_i(ind) <= payload_ready_out; + + payload_ready_in <= payload_ready_in_i(ind); + payload_valid_out <= payload_valid_out_i(ind); + payload_read_data <= payload_read_data_i(ind); + end process; + + sample_info_gen : for i in 0 to NUM_READERS-1 generate + sample_info(i).sample_state <= si_sample_state_sig; + sample_info(i).view_state <= si_view_state_sig; + sample_info(i).instance_state <= si_instance_state_sig; + sample_info(i).source_timestamp <= si_source_timestamp_sig; + sample_info(i).instance_handle <= si_instance_handle_sig; + sample_info(i).publication_handle <= si_publication_handle_sig; + sample_info(i).disposed_generation_count <= si_disposed_generation_count_sig; + sample_info(i).no_writers_generation_count <= si_no_writers_generation_count_sig; + sample_info(i).sample_rank <= std_logic_vector(si_sample_rank_sig); + sample_info(i).generation_rank <= std_logic_vector(si_generation_rank_sig); + sample_info(i).absolute_generation_rank <= std_logic_vector(si_absolute_generation_rank_sig); + sample_info(i).valid_data <= si_valid_data_sig; + end generate; + sample_info_valid <= (others => si_valid_sig); + eoc <= (others => eoc_sig); + status <= status_sig; -- *Main State Machine* -- STATE DESCRIPTION @@ -686,7 +875,7 @@ begin -- FIND_NEXT_INSTANCE Find next Instance that passes requested masks -- CHECK_INSTANCE Check if selected Instance passes requested masks -- CHECK_LIFESPAN Check and remove samples with expired Lifespans - -- PROCESS_PENDING_SAMPLE_GENERATION Iterate through the Instances and Generate Samples where required + -- PROCESS_PENDING_SAMPLE_GENERATION Iterate through the Instances and Generate Samples where required (A Sample is generated for NOT_ALIVE_NO_WRITERS transitions) -- GET_SAMPLE_REJECTED_STATUS Return Sample Rejected Status -- GET_REQUESTED_DEADLINE_MISSED_STATUS Return Requested Deadline Missed Status -- CHECK_DEADLINE Check and Mark Instances with missed Deadlines @@ -752,6 +941,7 @@ begin sample_rej_cnt_change_next <= sample_rej_cnt_change; sample_rej_last_reason_next <= sample_rej_last_reason; sample_rej_last_inst_next <= sample_rej_last_inst; + deadline_check_time_next <= deadline_check_time; deadline_time_next <= deadline_time; deadline_miss_cnt_next <= deadline_miss_cnt; deadline_miss_cnt_change_next <= deadline_miss_cnt_change; @@ -764,7 +954,6 @@ begin cnt3_next <= cnt3; lifespan_next <= lifespan; stale_inst_cnt_next <= stale_inst_cnt; - inst_data_next2 <= inst_data; oldest_sample_next <= oldest_sample; rtps_return_code_latch_next <= rtps_return_code_latch; dds_return_code_latch_next <= dds_return_code_latch; @@ -775,15 +964,16 @@ begin new_inst_next <= new_inst; trigger_sample_gen_next <= trigger_sample_gen; wait_for_sample_removal_next <= wait_for_sample_removal; + ind_next <= ind; -- DEFAULT Unregistered inst_opcode <= NOP; - opcode_kh <= NOP; - ret_rtps <= ERROR; - return_code_dds <= RETCODE_UNSUPPORTED; - ack_dds <= '0'; - done_dds <= '0'; - ack_rtps <= '0'; - done_rtps <= '0'; + opcode_kh <= (others => NOP); + ret_rtps <= (others => ERROR); + return_code_dds <= (others => RETCODE_UNSUPPORTED); + ack_dds <= (others => '0'); + done_dds <= (others => '0'); + ack_rtps <= (others => '0'); + done_rtps <= (others => '0'); inst_op_start <= '0'; sample_read <= '0'; sample_ready_out <= '0'; @@ -793,17 +983,17 @@ begin payload_ready_out <= '0'; payload_valid_in <= '0'; payload_abort_read <= '0'; - ready_in_rtps <= '0'; - start_kh <= '0'; - abort_kh <= '0'; - ready_in_kh <= '0'; - valid_out_kh <= '0'; - last_word_out_kh <= '0'; - valid_out_dds <= '0'; - last_word_out_dds <= '0'; + ready_in_rtps <= (others => '0'); + start_kh <= (others => '0'); + abort_kh <= (others => '0'); + ready_in_kh <= (others => '0'); + valid_out_kh <= (others => '0'); + last_word_out_kh <= (others => '0'); + valid_out_dds <= (others => '0'); + last_word_out_dds <= (others => '0'); idle_sig <= '0'; - data_out_dds <= (others => '0'); - data_out_kh <= (others => '0'); + data_out_dds <= (others => (others => '0')); + data_out_kh <= (others => (others => '0')); sample_addr <= (others => '0'); sample_write_data <= (others => '0'); payload_addr <= (others => '0'); @@ -825,370 +1015,300 @@ begin -- DEADLINE QoS - if (DEADLINE_QOS /= DURATION_INFINITE and deadline_time <= time) then - -- Reset Timeout - deadline_time_next <= deadline_time + DEADLINE_QOS; + if (deadline_check_time <= time) then + -- Reset + deadline_check_time_next <= TIME_INFINITE; - -- Synthesis Guard - if (WITH_KEY) then - stage_next <= CHECK_DEADLINE; - cnt_next <= 0; - else - if (inst_data.status_info(ISI_LIVELINESS_FLAG) = '1') then - -- Reset Liveliness Flag - inst_data_next2.status_info(ISI_LIVELINESS_FLAG) <= '0'; - else - -- Update Requested Deadline Missed Status - status_sig_next <= status_sig or REQUESTED_DEADLINE_MISSED_STATUS; - deadline_miss_cnt_next <= deadline_miss_cnt + 1; - deadline_miss_cnt_change_next <= deadline_miss_cnt_change + 1; - end if; - end if; + ind_next <= 0; + stage_next <= CHECK_DEADLINE; + cnt_next <= 1; -- CHECK DEADLINE -- LIFESPAN QoS elsif (lifespan_time <= time) then -- Reset Timeout lifespan_time_next <= TIME_INFINITE; + is_lifespan_check_next <= '1'; + ind_next <= 0; - -- Samples Available - if (oldest_sample /= SAMPLE_MEMORY_MAX_ADDRESS) then - cur_sample_next <= oldest_sample; - stage_next <= CHECK_LIFESPAN; - cnt_next <= 0; - end if; + stage_next <= CHECK_LIFESPAN; + cnt_next <= 1; -- CHECK LIFESPAN -- Sample Generation elsif (trigger_sample_gen = '1') then - - -- Synthesis Guard - if (WITH_KEY) then - stage_next <= PROCESS_PENDING_SAMPLE_GENERATION; - cnt_next <= 0; - else - -- RESOURCE_LIMITS_QOS (MAX_SAMPLES) - if (empty_sample_list_head = empty_sample_list_tail) then - if (HISTORY_QOS = KEEP_ALL_HISTORY_QOS and RELIABILITY_QOS = RELIABLE_RELIABILITY_QOS) then - wait_for_sample_removal_next <= '1'; - -- Reset - trigger_sample_gen_next <= '0'; - -- DONE - stage_next <= IDLE; - else - -- Reset - trigger_sample_gen_next <= '0'; - - -- Update Instance - inst_data_next2.status_info(ISI_GENERATE_SAMPLE_FLAG) <= '0'; - inst_data_next2.sample_cnt <= inst_data.sample_cnt + 1; - - -- Accept Change (Remove Oldest Sample) - remove_oldest_sample_next <= '1'; - - cur_sample_next <= empty_sample_list_head; - cur_inst_next <= inst_data.addr; - stage_next <= GENERATE_SAMPLE; - cnt_next <= 0; - end if; - else - -- Reset - trigger_sample_gen_next <= '0'; - - -- Update Instance - inst_data_next2.status_info(ISI_GENERATE_SAMPLE_FLAG) <= '0'; - inst_data_next2.sample_cnt <= inst_data.sample_cnt + 1; - - cur_sample_next <= empty_sample_list_head; - cur_inst_next <= inst_data.addr; - stage_next <= GENERATE_SAMPLE; - cnt_next <= 0; - end if; - end if; + stage_next <= PROCESS_PENDING_SAMPLE_GENERATION; + cnt_next <= 0; -- RTPS Operation - elsif (start_rtps = '1') then - case (opcode_rtps) is - when ADD_CACHE_CHANGE => - -- NOTE: We have to explicitly check the Payload Memory, as it may be "unaligned" with our Sample Memory - -- (Sample Memory has available Slot, but Payload Memory not) - -- Payload Memory Full - if (empty_payload_list_head = PAYLOAD_MEMORY_MAX_ADDRESS) then - if (HISTORY_QOS = KEEP_ALL_HISTORY_QOS and RELIABILITY_QOS = RELIABLE_RELIABILITY_QOS) then - ack_rtps <= '1'; - -- Reject Change - stage_next <= SKIP_AND_RETURN; - cnt_next <= 0; - rtps_return_code_latch_next <= REJECTED; - - -- Update Sample Reject Status - status_sig_next <= status_sig or SAMPLE_REJECTED_STATUS; - sample_rej_cnt_next <= sample_rej_cnt + 1; - sample_rej_cnt_change_next <= sample_rej_cnt_change + 1; - sample_rej_last_reason_next <= REJECTED_BY_PAYOAD_MEMORY_LIMIT; - sample_rej_last_inst_next <= HANDLE_NIL; - else - assert (oldest_sample /= SAMPLE_MEMORY_MAX_ADDRESS) severity FAILURE; - -- Do not ACK Operation - ack_dds <= '0'; - - remove_oldest_sample_next <= '1'; - if (WITH_KEY) then - stage_next <= GET_OLDEST_SAMPLE_INSTANCE; - cnt_next <= 0; + elsif (start_rtps /= (start_rtps'range => '0')) then + if (start_rtps(ind) /= '1') then + if (ind = NUM_READERS-1) then + ind_next <= 0; + else + ind_next <= ind + 1; + end if; + else + case (opcode_rtps(ind)) is + when ADD_CACHE_CHANGE => + -- NOTE: We have to explicitly check the Payload Memory, as it may be "unaligned" with our Sample Memory + -- (Sample Memory has available Slot, but Payload Memory not) + -- Payload Memory Full + if (empty_payload_list_head(ind) = PAYLOAD_MEMORY_MAX_ADDRESS) then + if (CONFIG_ARRAY_T(ind).HISTORY_QOS = KEEP_ALL_HISTORY_QOS and CONFIG_ARRAY_T(ind).RELIABILITY_QOS = RELIABLE_RELIABILITY_QOS) then + ack_rtps(ind) <= '1'; + + -- Reject Change + stage_next <= SKIP_AND_RETURN; + cnt_next <= 0; + rtps_return_code_latch_next <= REJECTED; + + -- Update Sample Reject Status + status_sig_next(ind) <= status_sig(ind) or SAMPLE_REJECTED_STATUS; + sample_rej_cnt_next(ind) <= std_logic_vector(unsigned(sample_rej_cnt(ind)) + 1); + sample_rej_cnt_change_next(ind) <= std_logic_vector(unsigned(sample_rej_cnt_change(ind)) + 1); + sample_rej_last_reason_next(ind) <= REJECTED_BY_PAYLOAD_MEMORY_LIMIT; + sample_rej_last_inst_next(ind) <= HANDLE_NIL; else - cur_sample_next <= oldest_sample; - stage_next <= REMOVE_SAMPLE; - cnt_next <= 0; + assert (oldest_sample(ind) /= SAMPLE_MEMORY_MAX_ADDRESS) severity FAILURE; + -- Do not ACK Operation + ack_dds(ind) <= '0'; + + remove_oldest_sample_next <= '1'; + stage_next <= GET_OLDEST_SAMPLE_INSTANCE; + cnt_next <= 0; end if; + else + ack_rtps(ind) <= '1'; + stage_next <= ADD_SAMPLE_INFO; + cur_sample_next <= empty_sample_list_head(ind); + cnt_next <= 0; end if; - else - ack_rtps <= '1'; - stage_next <= ADD_SAMPLE_INFO; - cur_sample_next <= empty_sample_list_head; - cnt_next <= 0; - end if; - when REMOVE_WRITER => - ack_rtps <= '1'; - - -- Synthesis Guard - if (WITH_KEY) then + when REMOVE_WRITER => + ack_rtps(ind) <= '1'; + -- Latch Writer Pos - writer_id_next <= to_integer(unsigned(data_in_rtps)); + writer_id_next <= to_integer(unsigned(data_in_rtps(ind))); stage_next <= REMOVE_WRITER; - cnt_next <= 2; - else - -- Convert Writer Bitmap to SLV - tmp_bitmap := from_writer_bitmap_array(inst_data.writer_bitmap); - - -- Remove Writer - tmp_bitmap(to_integer(unsigned(data_in_rtps))) := '0'; - - -- Convert Back - inst_data_next2.writer_bitmap <= to_writer_bitmap_array(tmp_bitmap); - - -- NOT_ALIVE_NO_WRITERS Transition - if (tmp_bitmap = (tmp_bitmap'reverse_range => '0') and inst_data.status_info(ISI_NOT_ALIVE_DISPOSED_FLAG) = '0') then - trigger_sample_gen_next <= '1'; - inst_data_next2.status_info(ISI_GENERATE_SAMPLE_FLAG) <= '1'; - inst_data_next2.status_info(ISI_NOT_ALIVE_NO_WRITERS_FLAG) <= '1'; - end if; - - stage_next <= RETURN_RTPS; - rtps_return_code_latch_next <= OK; - end if; - when others => - null; - end case; + cnt_next <= 2; -- GET FIRST INSTANCE + when others => + null; + end case; + end if; -- Unmark Instances - elsif (WITH_KEY and unmark_instances_flag = '1') then + elsif (unmark_instances_flag = '1') then -- Memory Operation Guard if (inst_op_done = '1') then inst_op_start <= '1'; inst_opcode <= UNMARK_INSTANCES; + inst_r.i <= ind; unmark_instances_flag_next <= '0'; end if; -- DDS Operation - elsif (start_dds = '1') then - -- Latch Input Signals - sample_state_next <= sample_state_dds; - view_state_next <= view_state_dds; - instance_state_next <= instance_state_dds; - max_samples_latch_next <= unsigned(max_samples_dds); - - -- Reset - sel_sample_next <= SAMPLE_MEMORY_MAX_ADDRESS; - sample_p1_next <= SAMPLE_MEMORY_MAX_ADDRESS; - sample_p2_next <= SAMPLE_MEMORY_MAX_ADDRESS; - pre_calculated_next <= '0'; - if (WITH_KEY) then - single_instance_next <= '0'; + elsif (start_dds /= (start_dds'range => '0')) then + if (start_dds(ind) /= '1') then + if (ind = NUM_READERS-1) then + ind_next <= 0; + else + ind_next <= ind + 1; + end if; else - single_instance_next <= '1'; - end if; - dynamic_next_instance_next <= '0'; - collection_cnt_next <= (others => '0'); - collection_cnt_max_next <= (others => '0'); - si_sample_state_sig_next <= (others => '0'); - si_view_state_sig_next <= (others => '0'); - si_instance_state_sig_next <= (others => '0'); - si_source_timestamp_sig_next <= TIME_ZERO; - si_instance_handle_sig_next <= HANDLE_NIL; - si_publication_handle_sig_next <= HANDLE_NIL; - si_sample_rank_sig_next <= (others => '0'); - si_generation_rank_sig_next <= (others => '0'); - si_valid_data_sig_next <= '0'; - si_valid_sig_next <= '0'; - eoc_sig_next <= '0'; - si_absolute_generation_rank_sig_next <= (others => '0'); - si_disposed_generation_count_sig_next <= (others => '0'); - si_no_writers_generation_count_sig_next <= (others => '0'); - - case (opcode_dds) is - when READ => - ack_dds <= '1'; - -- No Samples Available - if (oldest_sample = SAMPLE_MEMORY_MAX_ADDRESS) then - stage_next <= RETURN_DDS; - dds_return_code_latch_next <= RETCODE_NO_DATA; - else - cur_sample_next <= oldest_sample; - cur_inst_next <= INSTANCE_MEMORY_MAX_ADDRESS; - stage_next <= GET_NEXT_SAMPLE; - cnt_next <= 0; - if (unsigned(max_samples_dds) = 1) then - single_instance_next <= '1'; - end if; - end if; - when TAKE => - ack_dds <= '1'; - -- No Samples Available - if (oldest_sample = SAMPLE_MEMORY_MAX_ADDRESS) then - stage_next <= RETURN_DDS; - dds_return_code_latch_next <= RETCODE_NO_DATA; - else - is_take_next <= '1'; - cur_sample_next <= oldest_sample; - cur_inst_next <= INSTANCE_MEMORY_MAX_ADDRESS; - stage_next <= GET_NEXT_SAMPLE; - cnt_next <= 0; - if (unsigned(max_samples_dds) = 1) then - single_instance_next <= '1'; - end if; - end if; - when READ_NEXT_SAMPLE => - ack_dds <= '1'; - -- No Samples Available - if (oldest_sample = SAMPLE_MEMORY_MAX_ADDRESS) then - stage_next <= RETURN_DDS; - dds_return_code_latch_next <= RETCODE_NO_DATA; - else - single_instance_next <= '1'; - cur_sample_next <= oldest_sample; - cur_inst_next <= INSTANCE_MEMORY_MAX_ADDRESS; - sample_state_next <= NOT_READ_SAMPLE_STATE; - view_state_next <= ANY_VIEW_STATE; - instance_state_next <= ANY_INSTANCE_STATE; - max_samples_latch_next <= to_unsigned(1, max_samples_latch'length); - stage_next <= GET_NEXT_SAMPLE; - cnt_next <= 0; - end if; - when TAKE_NEXT_SAMPLE => - ack_dds <= '1'; - -- No Samples Available - if (oldest_sample = SAMPLE_MEMORY_MAX_ADDRESS) then - stage_next <= RETURN_DDS; - dds_return_code_latch_next <= RETCODE_NO_DATA; - else - is_take_next <= '1'; - single_instance_next <= '1'; - cur_sample_next <= oldest_sample; - cur_inst_next <= INSTANCE_MEMORY_MAX_ADDRESS; - sample_state_next <= NOT_READ_SAMPLE_STATE; - view_state_next <= ANY_VIEW_STATE; - instance_state_next <= ANY_INSTANCE_STATE; - max_samples_latch_next <= to_unsigned(1, max_samples_latch'length); - stage_next <= GET_NEXT_SAMPLE; - cnt_next <= 0; - end if; - when READ_INSTANCE => - ack_dds <= '1'; - -- Synthesis Guard - if (WITH_KEY) then + -- Latch Input Signals + sample_state_next <= sample_state_dds(ind); + view_state_next <= view_state_dds(ind); + instance_state_next <= instance_state_dds(ind); + max_samples_latch_next <= unsigned(max_samples_dds(ind)); + + -- Reset + sel_sample_next <= SAMPLE_MEMORY_MAX_ADDRESS; + sample_p1_next <= SAMPLE_MEMORY_MAX_ADDRESS; + sample_p2_next <= SAMPLE_MEMORY_MAX_ADDRESS; + pre_calculated_next <= '0'; + single_instance_next <= '0'; + dynamic_next_instance_next <= '0'; + collection_cnt_next <= (others => '0'); + collection_cnt_max_next <= (others => '0'); + si_sample_state_sig_next <= (others => '0'); + si_view_state_sig_next <= (others => '0'); + si_instance_state_sig_next <= (others => '0'); + si_source_timestamp_sig_next <= TIME_ZERO; + si_instance_handle_sig_next <= HANDLE_NIL; + si_publication_handle_sig_next <= HANDLE_NIL; + si_sample_rank_sig_next <= (others => '0'); + si_generation_rank_sig_next <= (others => '0'); + si_valid_data_sig_next <= '0'; + si_valid_sig_next <= '0'; + eoc_sig_next <= '0'; + si_absolute_generation_rank_sig_next <= (others => '0'); + si_disposed_generation_count_sig_next <= (others => '0'); + si_no_writers_generation_count_sig_next <= (others => '0'); + + case (opcode_dds(ind)) is + when READ => + ack_dds(ind) <= '1'; -- No Samples Available - if (oldest_sample = SAMPLE_MEMORY_MAX_ADDRESS) then + if (oldest_sample(ind) = SAMPLE_MEMORY_MAX_ADDRESS) then + stage_next <= RETURN_DDS; + dds_return_code_latch_next <= RETCODE_NO_DATA; + else + cur_sample_next <= oldest_sample(ind); + cur_inst_next <= INSTANCE_MEMORY_MAX_ADDRESS; + stage_next <= GET_NEXT_SAMPLE; + cnt_next <= 0; + if (unsigned(max_samples_dds(ind)) = 1) then + single_instance_next <= '1'; + end if; + end if; + when TAKE => + ack_dds(ind) <= '1'; + -- No Samples Available + if (oldest_sample(ind) = SAMPLE_MEMORY_MAX_ADDRESS) then + stage_next <= RETURN_DDS; + dds_return_code_latch_next <= RETCODE_NO_DATA; + else + is_take_next <= '1'; + cur_sample_next <= oldest_sample(ind); + cur_inst_next <= INSTANCE_MEMORY_MAX_ADDRESS; + stage_next <= GET_NEXT_SAMPLE; + cnt_next <= 0; + if (unsigned(max_samples_dds(ind)) = 1) then + single_instance_next <= '1'; + end if; + end if; + when READ_NEXT_SAMPLE => + ack_dds(ind) <= '1'; + -- No Samples Available + if (oldest_sample(ind) = SAMPLE_MEMORY_MAX_ADDRESS) then stage_next <= RETURN_DDS; dds_return_code_latch_next <= RETCODE_NO_DATA; else single_instance_next <= '1'; - cur_sample_next <= oldest_sample; - key_hash_next <= instance_handle_dds; - stage_next <= CHECK_INSTANCE; + cur_sample_next <= oldest_sample(ind); + cur_inst_next <= INSTANCE_MEMORY_MAX_ADDRESS; + sample_state_next <= NOT_READ_SAMPLE_STATE; + view_state_next <= ANY_VIEW_STATE; + instance_state_next <= ANY_INSTANCE_STATE; + max_samples_latch_next <= to_unsigned(1, max_samples_latch'length); + stage_next <= GET_NEXT_SAMPLE; cnt_next <= 0; end if; - else - stage_next <= RETURN_DDS; - dds_return_code_latch_next <= RETCODE_ILLEGAL_OPERATION; - end if; - when TAKE_INSTANCE => - ack_dds <= '1'; - -- Synthesis Guard - if (WITH_KEY) then + when TAKE_NEXT_SAMPLE => + ack_dds(ind) <= '1'; -- No Samples Available - if (oldest_sample = SAMPLE_MEMORY_MAX_ADDRESS) then + if (oldest_sample(ind) = SAMPLE_MEMORY_MAX_ADDRESS) then stage_next <= RETURN_DDS; dds_return_code_latch_next <= RETCODE_NO_DATA; else is_take_next <= '1'; single_instance_next <= '1'; - cur_sample_next <= oldest_sample; - key_hash_next <= instance_handle_dds; - stage_next <= CHECK_INSTANCE; + cur_sample_next <= oldest_sample(ind); + cur_inst_next <= INSTANCE_MEMORY_MAX_ADDRESS; + sample_state_next <= NOT_READ_SAMPLE_STATE; + view_state_next <= ANY_VIEW_STATE; + instance_state_next <= ANY_INSTANCE_STATE; + max_samples_latch_next <= to_unsigned(1, max_samples_latch'length); + stage_next <= GET_NEXT_SAMPLE; cnt_next <= 0; end if; - else - stage_next <= RETURN_DDS; - dds_return_code_latch_next <= RETCODE_ILLEGAL_OPERATION; - end if; - when READ_NEXT_INSTANCE => - ack_dds <= '1'; - -- Synthesis Guard - if (WITH_KEY) then - -- No Samples Available - if (oldest_sample = SAMPLE_MEMORY_MAX_ADDRESS) then - stage_next <= RETURN_DDS; - dds_return_code_latch_next <= RETCODE_NO_DATA; + when READ_INSTANCE => + ack_dds(ind) <= '1'; + -- Synthesis Guard + if (CONFIG_ARRAY_T(ind).WITH_KEY) then + -- No Samples Available + if (oldest_sample(ind) = SAMPLE_MEMORY_MAX_ADDRESS) then + stage_next <= RETURN_DDS; + dds_return_code_latch_next <= RETCODE_NO_DATA; + else + single_instance_next <= '1'; + cur_sample_next <= oldest_sample(ind); + key_hash_next <= instance_handle_dds(ind); + stage_next <= CHECK_INSTANCE; + cnt_next <= 0; + end if; else - single_instance_next <= '1'; - dynamic_next_instance_next <= '1'; - cur_sample_next <= oldest_sample; - key_hash_next <= instance_handle_dds; - stage_next <= FIND_NEXT_INSTANCE; - cnt_next <= 0; -- GET FIRST INSTANCE - end if; - else - stage_next <= RETURN_DDS; - dds_return_code_latch_next <= RETCODE_ILLEGAL_OPERATION; - end if; - when TAKE_NEXT_INSTANCE => - ack_dds <= '1'; - -- Synthesis Guard - if (WITH_KEY) then - -- No Samples Available - if (oldest_sample = SAMPLE_MEMORY_MAX_ADDRESS) then stage_next <= RETURN_DDS; - dds_return_code_latch_next <= RETCODE_NO_DATA; - else - is_take_next <= '1'; - single_instance_next <= '1'; - dynamic_next_instance_next <= '1'; - cur_sample_next <= oldest_sample; - key_hash_next <= instance_handle_dds; - stage_next <= FIND_NEXT_INSTANCE; - cnt_next <= 0; -- GET FIRST INSTANCE + dds_return_code_latch_next <= RETCODE_ILLEGAL_OPERATION; end if; - else + when TAKE_INSTANCE => + ack_dds(ind) <= '1'; + -- Synthesis Guard + if (CONFIG_ARRAY_T(ind).WITH_KEY) then + -- No Samples Available + if (oldest_sample(ind) = SAMPLE_MEMORY_MAX_ADDRESS) then + stage_next <= RETURN_DDS; + dds_return_code_latch_next <= RETCODE_NO_DATA; + else + is_take_next <= '1'; + single_instance_next <= '1'; + cur_sample_next <= oldest_sample(ind); + key_hash_next <= instance_handle_dds(ind); + stage_next <= CHECK_INSTANCE; + cnt_next <= 0; + end if; + else + stage_next <= RETURN_DDS; + dds_return_code_latch_next <= RETCODE_ILLEGAL_OPERATION; + end if; + when READ_NEXT_INSTANCE => + ack_dds(ind) <= '1'; + -- Synthesis Guard + if (CONFIG_ARRAY_T(ind).WITH_KEY) then + -- No Samples Available + if (oldest_sample(ind) = SAMPLE_MEMORY_MAX_ADDRESS) then + stage_next <= RETURN_DDS; + dds_return_code_latch_next <= RETCODE_NO_DATA; + else + single_instance_next <= '1'; + dynamic_next_instance_next <= '1'; + cur_sample_next <= oldest_sample(ind); + key_hash_next <= instance_handle_dds(ind); + stage_next <= FIND_NEXT_INSTANCE; + cnt_next <= 0; -- GET FIRST INSTANCE + end if; + else + stage_next <= RETURN_DDS; + dds_return_code_latch_next <= RETCODE_ILLEGAL_OPERATION; + end if; + when TAKE_NEXT_INSTANCE => + ack_dds(ind) <= '1'; + -- Synthesis Guard + if (CONFIG_ARRAY_T(ind).WITH_KEY) then + -- No Samples Available + if (oldest_sample(ind) = SAMPLE_MEMORY_MAX_ADDRESS) then + stage_next <= RETURN_DDS; + dds_return_code_latch_next <= RETCODE_NO_DATA; + else + is_take_next <= '1'; + single_instance_next <= '1'; + dynamic_next_instance_next <= '1'; + cur_sample_next <= oldest_sample(ind); + key_hash_next <= instance_handle_dds(ind); + stage_next <= FIND_NEXT_INSTANCE; + cnt_next <= 0; -- GET FIRST INSTANCE + end if; + else + stage_next <= RETURN_DDS; + dds_return_code_latch_next <= RETCODE_ILLEGAL_OPERATION; + end if; + when GET_SAMPLE_REJECTED_STATUS => + ack_dds(ind) <= '1'; + stage_next <= GET_SAMPLE_REJECTED_STATUS; + cnt_next <= 0; + when GET_REQUESTED_DEADLINE_MISSED_STATUS => + ack_dds(ind) <= '1'; + stage_next <= GET_REQUESTED_DEADLINE_MISSED_STATUS; + cnt_next <= 0; + when others => + ack_dds(ind) <= '1'; stage_next <= RETURN_DDS; - dds_return_code_latch_next <= RETCODE_ILLEGAL_OPERATION; - end if; - when GET_SAMPLE_REJECTED_STATUS => - ack_dds <= '1'; - stage_next <= GET_SAMPLE_REJECTED_STATUS; - cnt_next <= 0; - when GET_REQUESTED_DEADLINE_MISSED_STATUS => - ack_dds <= '1'; - stage_next <= GET_REQUESTED_DEADLINE_MISSED_STATUS; - cnt_next <= 0; - when others => - ack_dds <= '1'; - stage_next <= RETURN_DDS; - dds_return_code_latch_next <= RETCODE_UNSUPPORTED; - end case; + dds_return_code_latch_next <= RETCODE_UNSUPPORTED; + end case; + end if; end if; when RETURN_DDS => - done_dds <= '1'; - return_code_dds <= dds_return_code_latch; + done_dds(ind) <= '1'; + return_code_dds(ind) <= dds_return_code_latch; -- DONE stage_next <= IDLE; when RETURN_RTPS => - done_rtps <= '1'; - ret_rtps <= rtps_return_code_latch; + done_rtps(ind) <= '1'; + ret_rtps(ind) <= rtps_return_code_latch; -- DONE stage_next <= IDLE; @@ -1199,63 +1319,66 @@ begin -- SET Status Info when 0 => -- Input Guard - if (valid_in_rtps = '1') then + if (valid_in_rtps(ind) = '1') then -- NOTE: The PAYLOAD_FLAG and KEY_HASH_FLAG are set by the RTPS Reader -- NOTE: The ALIGNED_FLAG is set by default. if actual Payload is not aligned, need to reset. sample_valid_in <= '1'; sample_addr <= cur_sample + SMF_STATUS_INFO_OFFSET; - sample_write_data <= data_in_rtps; + sample_write_data <= data_in_rtps(ind); sample_write_data(SSI_KEY_HASH_FLAG) <= '0'; -- Key Hash Flag is not stored sample_write_data(SSI_READ_FLAG) <= '0'; - sample_write_data(SSI_ALIGNED_FLAG) <= data_in_rtps(SSI_DATA_FLAG); + sample_write_data(SSI_ALIGNED_FLAG) <= data_in_rtps(ind)(SSI_DATA_FLAG); -- Latch Status Info - sample_status_info_next <= data_in_rtps; + sample_status_info_next <= data_in_rtps(ind); sample_status_info_next(SSI_READ_FLAG) <= '0'; - sample_status_info_next(SSI_ALIGNED_FLAG) <= data_in_rtps(SSI_DATA_FLAG); + sample_status_info_next(SSI_ALIGNED_FLAG) <= data_in_rtps(ind)(SSI_DATA_FLAG); + if (not CONFIG_ARRAY_T(ind).WITH_KEY) then + sample_status_info_next(SSI_KEY_HASH_FLAG) <= '1'; + end if; -- Memory Flow Control Guard if (sample_ready_in = '1') then - ready_in_rtps <= '1'; - cnt_next <= cnt + 1; + ready_in_rtps(ind) <= '1'; + cnt_next <= cnt + 1; end if; end if; -- SET Timestamp 1/2 when 1 => -- Input Guard - if (valid_in_rtps = '1') then + if (valid_in_rtps(ind) = '1') then sample_valid_in <= '1'; sample_addr <= cur_sample + SMF_TIMESTAMP_OFFSET; - sample_write_data <= data_in_rtps; + sample_write_data <= data_in_rtps(ind); -- Latch Timestamp - ts_latch_next(0) <= unsigned(data_in_rtps); + ts_latch_next(0) <= unsigned(data_in_rtps(ind)); -- Memory Flow Control Guard if (sample_ready_in = '1') then - ready_in_rtps <= '1'; - cnt_next <= cnt + 1; + ready_in_rtps(ind) <= '1'; + cnt_next <= cnt + 1; end if; end if; -- SET Timestamp 2/2 when 2 => -- Input Guard - if (valid_in_rtps = '1') then + if (valid_in_rtps(ind) = '1') then sample_valid_in <= '1'; sample_addr <= cur_sample + SMF_TIMESTAMP_OFFSET + 1; - sample_write_data <= data_in_rtps; + sample_write_data <= data_in_rtps(ind); -- Latch Timestamp - ts_latch_next(1) <= unsigned(data_in_rtps); + ts_latch_next(1) <= unsigned(data_in_rtps(ind)); -- Memory Flow Control Guard if (sample_ready_in = '1') then - ready_in_rtps <= '1'; - cnt_next <= cnt + 1; + ready_in_rtps(ind) <= '1'; + cnt_next <= cnt + 1; -- Synthesis Guard - if (DESTINATION_ORDER_QOS = BY_SOURCE_TIMESTAMP_DESTINATION_ORDER_QOS) then + if (CONFIG_ARRAY_T(ind).DESTINATION_ORDER_QOS = BY_SOURCE_TIMESTAMP_DESTINATION_ORDER_QOS) then -- Check Timestamp - tmp_dw := (0 => ts_latch(0), 1 => unsigned(data_in_rtps)); + tmp_dw := (0 => ts_latch(0), 1 => unsigned(data_in_rtps(ind))); -- NOTE: Equal timestamps are still acceptable, as they are inserted after the -- last read sample. -- Timestamp is smaller than highest last read (Or is Invalid) - if (tmp_dw = TIME_INVALID or (tmp_dw /= TIME_INVALID and tmp_dw < last_read_ts)) then + if (tmp_dw = TIME_INVALID or (tmp_dw /= TIME_INVALID and tmp_dw < last_read_ts(ind))) then -- Drop Sample rtps_return_code_latch_next <= OK; stage_next <= SKIP_AND_RETURN; @@ -1267,33 +1390,37 @@ begin -- SET Lifespan Deadline 1/2 when 3 => -- Input Guard - if (valid_in_rtps = '1') then + if (valid_in_rtps(ind) = '1') then sample_valid_in <= '1'; sample_addr <= cur_sample + SMF_LIFESPAN_DEADLINE_OFFSET; - sample_write_data <= data_in_rtps; + sample_write_data <= data_in_rtps(ind); -- Latch Lifespan - lifespan_next(0) <= unsigned(data_in_rtps); + lifespan_next(0) <= unsigned(data_in_rtps(ind)); -- Memory Flow Control Guard if (sample_ready_in = '1') then - ready_in_rtps <= '1'; - cnt_next <= cnt + 1; + ready_in_rtps(ind) <= '1'; + cnt_next <= cnt + 1; end if; end if; -- SET Lifespan Deadline 2/2 when 4 => -- Input Guard - if (valid_in_rtps = '1') then + if (valid_in_rtps(ind) = '1') then sample_valid_in <= '1'; sample_addr <= cur_sample + SMF_LIFESPAN_DEADLINE_OFFSET + 1; - sample_write_data <= data_in_rtps; + sample_write_data <= data_in_rtps(ind); -- Latch Lifespan - lifespan_next(1) <= unsigned(data_in_rtps); + lifespan_next(1) <= unsigned(data_in_rtps(ind)); -- Memory Flow Control Guard if (sample_ready_in = '1') then - ready_in_rtps <= '1'; + ready_in_rtps(ind) <= '1'; + -- NON-Keyed have default Key hash + if (not CONFIG_ARRAY_T(ind).WITH_KEY) then + key_hash_next <= HANDLE_NIL; + cnt_next <= 9; -- WRITER ENDPOINT POSITION -- Skip Key Hash, if not available - if (has_key_hash = '0') then - cnt_next <= 9; + elsif (has_key_hash = '0') then + cnt_next <= 9; -- WRITER ENDPOINT POSITION else cnt_next <= cnt + 1; end if; @@ -1302,58 +1429,58 @@ begin -- Key Hash 1/4 when 5 => -- Input Guard - if (valid_in_rtps = '1') then - ready_in_rtps <= '1'; + if (valid_in_rtps(ind) = '1') then + ready_in_rtps(ind) <= '1'; -- Latch Input, but do not pass to Memory - key_hash_next(0) <= data_in_rtps; + key_hash_next(0) <= data_in_rtps(ind); cnt_next <= cnt + 1; end if; -- Key Hash 2/4 when 6 => -- Input Guard - if (valid_in_rtps = '1') then - ready_in_rtps <= '1'; + if (valid_in_rtps(ind) = '1') then + ready_in_rtps(ind) <= '1'; -- Latch Input, but do not pass to Memory - key_hash_next(1) <= data_in_rtps; + key_hash_next(1) <= data_in_rtps(ind); cnt_next <= cnt + 1; end if; -- Key Hash 3/4 when 7 => -- Input Guard - if (valid_in_rtps = '1') then - ready_in_rtps <= '1'; + if (valid_in_rtps(ind) = '1') then + ready_in_rtps(ind) <= '1'; -- Latch Input, but do not pass to Memory - key_hash_next(2) <= data_in_rtps; + key_hash_next(2) <= data_in_rtps(ind); cnt_next <= cnt + 1; end if; -- Key Hash 4/4 when 8 => -- Input Guard - if (valid_in_rtps = '1') then - ready_in_rtps <= '1'; + if (valid_in_rtps(ind) = '1') then + ready_in_rtps(ind) <= '1'; -- Latch Input, but do not pass to Memory - key_hash_next(3) <= data_in_rtps; + key_hash_next(3) <= data_in_rtps(ind); cnt_next <= cnt + 1; end if; -- Writer Endpoint Position when 9 => -- Input Guard - if (valid_in_rtps = '1') then - ready_in_rtps <= '1'; + if (valid_in_rtps(ind) = '1') then + ready_in_rtps(ind) <= '1'; -- Latch Input, but do not pass to Memory - writer_id_next <= cap_range(to_integer(unsigned(data_in_rtps)), MAX_REMOTE_ENDPOINTS-1); + writer_id_next <= cap_range(to_integer(unsigned(data_in_rtps(ind))), MAX_REMOTE_ENDPOINTS-1); cnt_next <= cnt + 1; end if; -- SET Payload Address when 10 => - assert (empty_payload_list_head /= PAYLOAD_MEMORY_MAX_ADDRESS) severity FAILURE; + assert (empty_payload_list_head(ind) /= PAYLOAD_MEMORY_MAX_ADDRESS) severity FAILURE; sample_valid_in <= '1'; sample_addr <= cur_sample + SMF_PAYLOAD_ADDR_OFFSET; if (has_data = '1') then -- Store Payload Address - sample_write_data <= std_logic_vector(resize(empty_payload_list_head, WORD_WIDTH)); + sample_write_data <= std_logic_vector(resize(empty_payload_list_head(ind), WORD_WIDTH)); - cur_payload_next <= empty_payload_list_head; + cur_payload_next <= empty_payload_list_head(ind); else -- Mark Sample with no Payload sample_write_data <= std_logic_vector(resize(PAYLOAD_MEMORY_MAX_ADDRESS, WORD_WIDTH)); @@ -1361,44 +1488,39 @@ begin -- Memory Flow Control Guard if (sample_ready_in = '1') then - -- If Key Hash is available, start the Instance Search first - if (WITH_KEY and has_key_hash = '1') then - stage_next <= INITIATE_INSTANCE_SEARCH; -- Key Hash Needs to be Calculated - elsif (WITH_KEY and has_key_hash = '0') then + if (has_key_hash = '0') then cnt_next <= cnt + 1; elsif (has_data = '1') then - assert (not WITH_KEY) severity FAILURE; stage_next <= ADD_PAYLOAD; cnt_next <= 0; cnt2_next <= 1; - else -- has_data = '0' - assert (not WITH_KEY) severity FAILURE; - stage_next <= FILTER_STAGE; + else + assert (has_data = '0' and has_key_hash = '1') severity FAILURE; + stage_next <= INITIATE_INSTANCE_SEARCH; end if; end if; -- Initiate KH Operation when 11 => - -- Synthesis Guard - if (WITH_KEY) then - start_kh <= '1'; + assert (CONFIG_ARRAY_T(ind).WITH_KEY) severity FAILURE; + + start_kh(ind) <= '1'; + -- Payload is Serialized Key + if (has_data = '0') then + opcode_kh(ind) <= PUSH_SERIALIZED_KEY; + else + opcode_kh(ind) <= PUSH_DATA; + end if; + + if (ack_kh(ind) = '1') then -- Payload is Serialized Key if (has_data = '0') then - opcode_kh <= PUSH_SERIALIZED_KEY; + stage_next <= ADD_PAYLOAD; + cnt_next <= 1; else - opcode_kh <= PUSH_DATA; - end if; - - if (ack_kh = '1') then - -- Payload is Serialized Key - if (has_data = '0') then - stage_next <= ADD_PAYLOAD; - cnt_next <= 1; - else - stage_next <= ADD_PAYLOAD; - cnt_next <= 0; - cnt2_next <= 1; - end if; + stage_next <= ADD_PAYLOAD; + cnt_next <= 0; + cnt2_next <= 1; end if; end if; when others => @@ -1410,7 +1532,7 @@ begin -- NOTE: This state is responsible for reading the payload and writing it through to the local payload memory -- and key hash generator (KHG). This state is taken on following cases: -- has_data has_key_hash - -- 1 1 The payload is written to memory [Entered from INITIATE_INSTANCE_SEARCH] + -- 1 1 The payload is written to memory -- 1 0 The payload is written to memory and the KHG at the same time (KHG controls the flow) -- 0 0 There is no payload to write, but the input contains the key for the KHG @@ -1418,29 +1540,29 @@ begin -- Push to memory when 0 => -- Input Guard - if (valid_in_rtps = '1') then + if (valid_in_rtps(ind) = '1') then payload_valid_in <= '1'; payload_addr <= cur_payload + cnt2; - payload_write_data <= data_in_rtps; + payload_write_data <= data_in_rtps(ind); -- Memory Control Flow Guard if (payload_ready_in = '1') then -- Key Hash needs to be calculated - if (WITH_KEY and has_key_hash = '0') then + if (CONFIG_ARRAY_T(ind).WITH_KEY and has_key_hash = '0') then cnt_next <= cnt + 1; else - ready_in_rtps <= '1'; + ready_in_rtps(ind) <= '1'; -- End of Payload - if (last_word_in_rtps = '1') then + if (last_word_in_rtps(ind) = '1') then -- End of Payload Slot - if (cnt2 = PAYLOAD_FRAME_SIZE-1) then - stage_next <= FILTER_STAGE; + if (cnt2 = PAYLOAD_FRAME_SIZE(ind)-1) then + stage_next <= INITIATE_INSTANCE_SEARCH; else stage_next <= ALIGN_PAYLOAD; cnt_next <= 0; end if; else -- End of Payload Slot - if (cnt2 = PAYLOAD_FRAME_SIZE-1) then + if (cnt2 = PAYLOAD_FRAME_SIZE(ind)-1) then stage_next <= NEXT_PAYLOAD_SLOT; cnt_next <= 0; else @@ -1453,54 +1575,53 @@ begin end if; -- Push to KHG when 1 => - -- Synthesis Guard - if (WITH_KEY) then - -- Input Guard - if (valid_in_rtps = '1') then - valid_out_kh <= '1'; - data_out_kh <= data_in_rtps; + assert (CONFIG_ARRAY_T(ind).WITH_KEY) severity FAILURE; + + -- Input Guard + if (valid_in_rtps(ind) = '1') then + valid_out_kh(ind) <= '1'; + data_out_kh(ind) <= data_in_rtps(ind); + + -- Output Guard + if (ready_out_kh(ind) = '1') then + ready_in_rtps(ind) <= '1'; - -- Output Guard - if (ready_out_kh = '1') then - ready_in_rtps <= '1'; - - if (has_data = '1') then - -- End of Payload - if (last_word_in_rtps = '1') then - last_word_out_kh <= '1'; - -- End of Payload Slot - if (cnt2 = PAYLOAD_FRAME_SIZE-1) then - -- Fetch the Key Hash - stage_next <= GET_KEY_HASH; - cnt_next <= 0; - cnt2_next <= 0; - else - stage_next <= ALIGN_PAYLOAD; - cnt_next <= 0; - end if; - else - -- End of Payload Slot - if (cnt2 = PAYLOAD_FRAME_SIZE-1) then - stage_next <= NEXT_PAYLOAD_SLOT; - cnt_next <= 0; - else - -- Next Word - cnt_next <= 0; - cnt2_next <= cnt2 + 1; - end if; - end if; - else - -- End of Payload - if (last_word_in_rtps = '1') then - last_word_out_kh <= '1'; + if (has_data = '1') then + -- End of Payload + if (last_word_in_rtps(ind) = '1') then + last_word_out_kh(ind) <= '1'; + -- End of Payload Slot + if (cnt2 = PAYLOAD_FRAME_SIZE(ind)-1) then -- Fetch the Key Hash stage_next <= GET_KEY_HASH; cnt_next <= 0; cnt2_next <= 0; else - -- Next Word - cnt_next <= 1; -- Same Sub-state + stage_next <= ALIGN_PAYLOAD; + cnt_next <= 0; end if; + else + -- End of Payload Slot + if (cnt2 = PAYLOAD_FRAME_SIZE(ind)-1) then + stage_next <= NEXT_PAYLOAD_SLOT; + cnt_next <= 0; + else + -- Next Word + cnt_next <= 0; -- PUSH TO MEMORY + cnt2_next <= cnt2 + 1; + end if; + end if; + else + -- End of Payload + if (last_word_in_rtps(ind) = '1') then + last_word_out_kh(ind) <= '1'; + -- Fetch the Key Hash + stage_next <= GET_KEY_HASH; + cnt_next <= 0; + cnt2_next <= 0; + else + -- Next Word + cnt_next <= 1; -- Same Sub-state end if; end if; end if; @@ -1535,13 +1656,13 @@ begin stage_next <= SKIP_AND_RETURN; cnt_next <= 0; -- Abort Key Hash Generation - abort_kh <= '1'; + abort_kh(ind) <= '1'; -- Update Sample Reject Status - status_sig_next <= status_sig or SAMPLE_REJECTED_STATUS; - sample_rej_cnt_next <= sample_rej_cnt + 1; - sample_rej_cnt_change_next <= sample_rej_cnt_change + 1; - sample_rej_last_reason_next <= REJECTED_BY_PAYOAD_MEMORY_LIMIT; - sample_rej_last_inst_next <= key_hash; + status_sig_next(ind) <= status_sig(ind) or SAMPLE_REJECTED_STATUS; + sample_rej_cnt_next(ind) <= std_logic_vector(unsigned(sample_rej_cnt(ind)) + 1); + sample_rej_cnt_change_next(ind) <= std_logic_vector(unsigned(sample_rej_cnt_change(ind)) + 1); + sample_rej_last_reason_next(ind) <= REJECTED_BY_PAYLOAD_MEMORY_LIMIT; + sample_rej_last_inst_next(ind) <= key_hash; else -- Latch next Payload Slot and Continue cur_payload_next <= resize(unsigned(payload_read_data),PAYLOAD_MEMORY_ADDR_WIDTH); @@ -1569,82 +1690,73 @@ begin -- Store Payload End Offset when 1 => payload_valid_in <= '1'; - payload_addr <= cur_payload + PAYLOAD_FRAME_SIZE-1; + payload_addr <= cur_payload + PAYLOAD_FRAME_SIZE(ind)-1; payload_write_data <= std_logic_vector(to_unsigned(cnt2, WORD_WIDTH)); -- Memory Control Flow Guard if (payload_ready_in = '1') then - if (WITH_KEY and has_key_hash = '0') then + if (has_key_hash = '0') then stage_next <= GET_KEY_HASH; cnt_next <= 0; cnt2_next <= 0; else - stage_next <= FILTER_STAGE; + stage_next <= INITIATE_INSTANCE_SEARCH; end if; end if; when others => null; end case; when GET_KEY_HASH => - -- Synthesis Guard - if (WITH_KEY) then - case (cnt) is - -- Initiate READ Operation - when 0 => - start_kh <= '1'; - opcode_kh <= READ_KEY_HASH; - - if (ack_kh = '1') then - cnt_next <= cnt + 1; - end if; - -- READ Key Hash - when 1 => - ready_in_kh <= '1'; - - if (valid_in_kh = '1') then - cnt2_next <= cnt2 + 1; - - -- Latch Key Hash - key_hash_next(cnt2) <= data_in_kh; - - -- Exit Condition - if (last_word_in_kh = '1') then - -- DONE - stage_next <= INITIATE_INSTANCE_SEARCH; - end if; - end if; - when others => - null; - end case; - end if; - when INITIATE_INSTANCE_SEARCH => - -- Synthesis Guard - if (WITH_KEY) then - -- Memory Operation Guard - if (inst_op_done = '1') then - inst_op_start <= '1'; - inst_opcode <= SEARCH_INSTANCE; - inst_r.key_hash <= key_hash; - inst_r.field_flags <= IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_DISPOSED_CNT_FLAG or IMF_NO_WRITERS_CNT_FLAG or IMF_IGNORE_DEADLINE_FLAG or IMF_WRITER_BITMAP_FLAG; + assert (CONFIG_ARRAY_T(ind).WITH_KEY) severity FAILURE; + + case (cnt) is + -- Initiate READ Operation + when 0 => + start_kh(ind) <= '1'; + opcode_kh(ind) <= READ_KEY_HASH; - -- Payload not yet stored - if (has_data = '1' and WITH_KEY and has_key_hash = '1') then - stage_next <= ADD_PAYLOAD; - cnt_next <= 0; - cnt2_next <= 1; - else - stage_next <= FILTER_STAGE; + if (ack_kh(ind) = '1') then + cnt_next <= cnt + 1; end if; - end if; + -- READ Key Hash + when 1 => + ready_in_kh(ind) <= '1'; + + if (valid_in_kh(ind) = '1') then + cnt2_next <= cnt2 + 1; + + -- Latch Key Hash + key_hash_next(cnt2) <= data_in_kh(ind); + + -- Exit Condition + if (last_word_in_kh(ind) = '1') then + -- DONE + stage_next <= INITIATE_INSTANCE_SEARCH; + end if; + end if; + when others => + null; + end case; + when INITIATE_INSTANCE_SEARCH => + -- Memory Operation Guard + if (inst_op_done = '1') then + inst_op_start <= '1'; + inst_opcode <= SEARCH_INSTANCE; + inst_r.i <= ind; + inst_r.key_hash <= key_hash; + inst_r.field_flags <= IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_DISPOSED_CNT_FLAG or IMF_NO_WRITERS_CNT_FLAG or IMF_IGNORE_DEADLINE_FLAG or IMF_WRITER_BITMAP_FLAG; + + + stage_next <= FILTER_STAGE; end if; when FILTER_STAGE => -- Precondition: cur_sample set, inst_data set (IMF_STATUS_FLAG, IMF_IGNORE_DEADLINE_FLAG, IMF_SAMPLE_CNT_FLAG, IMF_DISPOSED_CNT_FLAG, IMF_NO_WRITERS_CNT_FLAG) -- Wait for Instance Search to finish - if (not WITH_KEY or inst_op_done = '1') then + if (inst_op_done = '1') then -- Instance Found - if (not WITH_KEY or inst_data.addr /= INSTANCE_MEMORY_MAX_ADDRESS) then - assert (not WITH_KEY or stable(clk,check_mask(inst_data.field_flags, IMF_STATUS_FLAG or IMF_IGNORE_DEADLINE_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_DISPOSED_CNT_FLAG or IMF_NO_WRITERS_CNT_FLAG))) severity FAILURE; + if (inst_data.addr /= INSTANCE_MEMORY_MAX_ADDRESS) then + assert (stable(clk, inst_data.i = ind and check_mask(inst_data.field_flags, IMF_STATUS_FLAG or IMF_IGNORE_DEADLINE_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_DISPOSED_CNT_FLAG or IMF_NO_WRITERS_CNT_FLAG))) severity FAILURE; -- Latch Instance Pointer cur_inst_next <= inst_data.addr; @@ -1653,14 +1765,14 @@ begin no_w_gen_cnt_latch_next <= inst_data.no_writers_gen_cnt; -- TIME_BASED_FILTER QOS - if (TIME_BASED_FILTER_QOS /= DURATION_ZERO and time < inst_data.ignore_deadline) then + if (CONFIG_ARRAY_T(ind).TIME_BASED_FILTER_QOS /= DURATION_ZERO and time < inst_data.ignore_deadline) then -- Drop Change - done_rtps <= '1'; - ret_rtps <= OK; - stage_next <= IDLE; + done_rtps(ind) <= '1'; + ret_rtps(ind) <= OK; + stage_next <= IDLE; -- Pending Sample Generation - -- NOTE: If there is a Pending Sample Generation and we reach this stage, the limiting factor is still here and the Sample will be rejected. - -- In order to have a valid sample rejected status it makes sense to let the sample be rejected "naturally". + -- NOTE: If there is a Pending Sample Generation and we reach this stage, the limiting factor still exists and the Sample will be rejected. + -- In order to have a valid sample rejected status it makes sense to let the sample be rejected "naturally", instead of defining a REJECTED_BY_PENDING_SAMPLE_GENERATION --elsif (inst_data.status_info(ISI_GENERATE_SAMPLE_FLAG) = '1') then -- -- Reject Change -- done_rtps <= '1'; @@ -1673,56 +1785,56 @@ begin -- sample_rej_last_reason_next <= REJECTED_BY_PENDING_SAMPLE_GENERATION; -- sample_rej_last_inst_next <= key_hash; -- RESOURCE_LIMITS_QOS (MAX_SAMPLES_PER_INSTANCE) - elsif (WITH_KEY and MAX_SAMPLES_PER_INSTANCE /= LENGTH_UNLIMITED and inst_data.sample_cnt = unsigned(MAX_SAMPLES_PER_INSTANCE)) then - if (HISTORY_QOS = KEEP_ALL_HISTORY_QOS and RELIABILITY_QOS = RELIABLE_RELIABILITY_QOS) then + elsif (CONFIG_ARRAY_T(ind).MAX_SAMPLES_PER_INSTANCE /= LENGTH_UNLIMITED and inst_data.sample_cnt = unsigned(CONFIG_ARRAY_T(ind).MAX_SAMPLES_PER_INSTANCE)) then + if (CONFIG_ARRAY_T(ind).HISTORY_QOS = KEEP_ALL_HISTORY_QOS and CONFIG_ARRAY_T(ind).RELIABILITY_QOS = RELIABLE_RELIABILITY_QOS) then -- Reject Change - done_rtps <= '1'; - ret_rtps <= REJECTED; - stage_next <= IDLE; + done_rtps(ind) <= '1'; + ret_rtps(ind) <= REJECTED; + stage_next <= IDLE; -- Update Sample Reject Status - status_sig_next <= status_sig or SAMPLE_REJECTED_STATUS; - sample_rej_cnt_next <= sample_rej_cnt + 1; - sample_rej_cnt_change_next <= sample_rej_cnt_change + 1; - sample_rej_last_reason_next <= REJECTED_BY_SAMPLES_PER_INSTANCE_LIMIT; - sample_rej_last_inst_next <= key_hash; + status_sig_next(ind) <= status_sig(ind) or SAMPLE_REJECTED_STATUS; + sample_rej_cnt_next(ind) <= std_logic_vector(unsigned(sample_rej_cnt(ind)) + 1); + sample_rej_cnt_change_next(ind) <= std_logic_vector(unsigned(sample_rej_cnt_change(ind)) + 1); + sample_rej_last_reason_next(ind) <= REJECTED_BY_SAMPLES_PER_INSTANCE_LIMIT; + sample_rej_last_inst_next(ind) <= key_hash; else -- Accept Change (Remove Oldest Instance Sample) remove_oldest_inst_sample_next <= '1'; - done_rtps <= '1'; - ret_rtps <= OK; - if (DESTINATION_ORDER_QOS = BY_SOURCE_TIMESTAMP_DESTINATION_ORDER_QOS and newest_sample /= SAMPLE_MEMORY_MAX_ADDRESS) then + done_rtps(ind) <= '1'; + ret_rtps(ind) <= OK; + if (CONFIG_ARRAY_T(ind).DESTINATION_ORDER_QOS = BY_SOURCE_TIMESTAMP_DESTINATION_ORDER_QOS and newest_sample(ind) /= SAMPLE_MEMORY_MAX_ADDRESS) then stage_next <= FIND_POS; next_sample_next <= SAMPLE_MEMORY_MAX_ADDRESS; - prev_sample_next <= newest_sample; - cur_sample_next <= newest_sample; + prev_sample_next <= newest_sample(ind); + cur_sample_next <= newest_sample(ind); cnt_next <= 0; else stage_next <= UPDATE_INSTANCE; end if; end if; -- RESOURCE_LIMITS_QOS (MAX_SAMPLES) - elsif (empty_sample_list_head = empty_sample_list_tail) then - if (HISTORY_QOS = KEEP_ALL_HISTORY_QOS and RELIABILITY_QOS = RELIABLE_RELIABILITY_QOS) then + elsif (empty_sample_list_head(ind) = empty_sample_list_tail(ind)) then + if (CONFIG_ARRAY_T(ind).HISTORY_QOS = KEEP_ALL_HISTORY_QOS and CONFIG_ARRAY_T(ind).RELIABILITY_QOS = RELIABLE_RELIABILITY_QOS) then -- Reject Change - done_rtps <= '1'; - ret_rtps <= REJECTED; - stage_next <= IDLE; + done_rtps(ind) <= '1'; + ret_rtps(ind) <= REJECTED; + stage_next <= IDLE; -- Update Sample Reject Status - status_sig_next <= status_sig or SAMPLE_REJECTED_STATUS; - sample_rej_cnt_next <= sample_rej_cnt + 1; - sample_rej_cnt_change_next <= sample_rej_cnt_change + 1; - sample_rej_last_reason_next <= REJECTED_BY_SAMPLES_LIMIT; - sample_rej_last_inst_next <= key_hash; + status_sig_next(ind) <= status_sig(ind) or SAMPLE_REJECTED_STATUS; + sample_rej_cnt_next(ind) <= std_logic_vector(unsigned(sample_rej_cnt(ind)) + 1); + sample_rej_cnt_change_next(ind) <= std_logic_vector(unsigned(sample_rej_cnt_change(ind)) + 1); + sample_rej_last_reason_next(ind) <= REJECTED_BY_SAMPLES_LIMIT; + sample_rej_last_inst_next(ind) <= key_hash; else -- Accept Change (Remove Oldest Sample) remove_oldest_sample_next <= '1'; - done_rtps <= '1'; - ret_rtps <= OK; - if (DESTINATION_ORDER_QOS = BY_SOURCE_TIMESTAMP_DESTINATION_ORDER_QOS and newest_sample /= SAMPLE_MEMORY_MAX_ADDRESS) then + done_rtps(ind) <= '1'; + ret_rtps(ind) <= OK; + if (CONFIG_ARRAY_T(ind).DESTINATION_ORDER_QOS = BY_SOURCE_TIMESTAMP_DESTINATION_ORDER_QOS and newest_sample(ind) /= SAMPLE_MEMORY_MAX_ADDRESS) then stage_next <= FIND_POS; next_sample_next <= SAMPLE_MEMORY_MAX_ADDRESS; - prev_sample_next <= newest_sample; - cur_sample_next <= newest_sample; + prev_sample_next <= newest_sample(ind); + cur_sample_next <= newest_sample(ind); cnt_next <= 0; else stage_next <= UPDATE_INSTANCE; @@ -1730,81 +1842,85 @@ begin end if; else -- Accept Change - done_rtps <= '1'; - ret_rtps <= OK; - if (DESTINATION_ORDER_QOS = BY_SOURCE_TIMESTAMP_DESTINATION_ORDER_QOS and newest_sample /= SAMPLE_MEMORY_MAX_ADDRESS) then + done_rtps(ind) <= '1'; + ret_rtps(ind) <= OK; + if (CONFIG_ARRAY_T(ind).DESTINATION_ORDER_QOS = BY_SOURCE_TIMESTAMP_DESTINATION_ORDER_QOS and newest_sample(ind) /= SAMPLE_MEMORY_MAX_ADDRESS) then stage_next <= FIND_POS; next_sample_next <= SAMPLE_MEMORY_MAX_ADDRESS; - prev_sample_next <= newest_sample; - cur_sample_next <= newest_sample; + prev_sample_next <= newest_sample(ind); + cur_sample_next <= newest_sample(ind); cnt_next <= 0; else stage_next <= UPDATE_INSTANCE; end if; end if; - else -- (only WITH_KEY) + else new_inst_next <= '1'; -- Latch Instance Pointer - cur_inst_next <= inst_empty_head; + cur_inst_next <= inst_empty_head(ind); -- Ignore UNREGISTER/FILTERED Samples on Unknown Instances if (sample_status_info(SSI_UNREGISTERED_FLAG) = '1' or sample_status_info(SSI_FILTERED_FLAG) = '1') then -- Drop Change - done_rtps <= '1'; - ret_rtps <= OK; + done_rtps(ind) <= '1'; + ret_rtps(ind) <= OK; -- DONE stage_next <= IDLE; -- RESOURCE_LIMITS_QOS (MAX_INSTANCES) (Instance Memory Full) - elsif (inst_empty_head = INSTANCE_MEMORY_MAX_ADDRESS) then + elsif (inst_empty_head(ind) = INSTANCE_MEMORY_MAX_ADDRESS) then + assert (stable(clk,CONFIG_ARRAY_T(ind).WITH_KEY)) severity FAILURE; + -- No Stale Instances available - if (stale_inst_cnt = 0) then + if (stale_inst_cnt(ind) = 0) then -- Reject Change - done_rtps <= '1'; - ret_rtps <= REJECTED; + done_rtps(ind) <= '1'; + ret_rtps(ind) <= REJECTED; -- DONE stage_next <= IDLE; -- Update Sample Reject Status - status_sig_next <= status_sig or SAMPLE_REJECTED_STATUS; - sample_rej_cnt_next <= sample_rej_cnt + 1; - sample_rej_cnt_change_next <= sample_rej_cnt_change + 1; - sample_rej_last_reason_next <= REJECTED_BY_INSTANCES_LIMIT; - sample_rej_last_inst_next <= key_hash; + status_sig_next(ind) <= status_sig(ind) or SAMPLE_REJECTED_STATUS; + sample_rej_cnt_next(ind) <= std_logic_vector(unsigned(sample_rej_cnt(ind)) + 1); + sample_rej_cnt_change_next(ind) <= std_logic_vector(unsigned(sample_rej_cnt_change(ind)) + 1); + sample_rej_last_reason_next(ind) <= REJECTED_BY_INSTANCES_LIMIT; + sample_rej_last_inst_next(ind) <= key_hash; else -- RESOURCE_LIMITS_QOS (MAX_SAMPLES) - if (empty_sample_list_head = empty_sample_list_tail) then - if (HISTORY_QOS = KEEP_ALL_HISTORY_QOS and RELIABILITY_QOS = RELIABLE_RELIABILITY_QOS) then + if (empty_sample_list_head(ind) = empty_sample_list_tail(ind)) then + if (CONFIG_ARRAY_T(ind).HISTORY_QOS = KEEP_ALL_HISTORY_QOS and CONFIG_ARRAY_T(ind).RELIABILITY_QOS = RELIABLE_RELIABILITY_QOS) then -- Reject Change - done_rtps <= '1'; - ret_rtps <= REJECTED; + done_rtps(ind) <= '1'; + ret_rtps(ind) <= REJECTED; stage_next <= IDLE; -- Update Sample Reject Status - status_sig_next <= status_sig or SAMPLE_REJECTED_STATUS; - sample_rej_cnt_next <= sample_rej_cnt + 1; - sample_rej_cnt_change_next <= sample_rej_cnt_change + 1; - sample_rej_last_reason_next <= REJECTED_BY_SAMPLES_LIMIT; - sample_rej_last_inst_next <= key_hash; + status_sig_next(ind) <= status_sig(ind) or SAMPLE_REJECTED_STATUS; + sample_rej_cnt_next(ind) <= std_logic_vector(unsigned(sample_rej_cnt(ind)) + 1); + sample_rej_cnt_change_next(ind) <= std_logic_vector(unsigned(sample_rej_cnt_change(ind)) + 1); + sample_rej_last_reason_next(ind) <= REJECTED_BY_SAMPLES_LIMIT; + sample_rej_last_inst_next(ind) <= key_hash; else -- Accept Change (Remove Oldest Sample) remove_oldest_sample_next <= '1'; - done_rtps <= '1'; - ret_rtps <= OK; + done_rtps(ind) <= '1'; + ret_rtps(ind) <= OK; -- Remove Stale Instance and Insert Instance inst_op_start <= '1'; inst_opcode <= GET_INSTANCE; - inst_r.addr <= inst_occupied_head; + inst_r.i <= ind; + inst_r.addr <= inst_occupied_head(ind); inst_r.field_flags <= IMF_SAMPLE_CNT_FLAG or IMF_WRITER_BITMAP_FLAG; stage_next <= REMOVE_STALE_INSTANCE; cnt_next <= 0; end if; else - done_rtps <= '1'; - ret_rtps <= OK; + done_rtps(ind) <= '1'; + ret_rtps(ind) <= OK; -- Remove Stale Instance and Insert Instance inst_op_start <= '1'; inst_opcode <= GET_INSTANCE; - inst_r.addr <= inst_occupied_head; + inst_r.addr <= inst_occupied_head(ind); + inst_r.i <= ind; inst_r.field_flags <= IMF_SAMPLE_CNT_FLAG or IMF_WRITER_BITMAP_FLAG; stage_next <= REMOVE_STALE_INSTANCE; cnt_next <= 0; @@ -1812,32 +1928,33 @@ begin end if; else -- RESOURCE_LIMITS_QOS (MAX_SAMPLES) - if (empty_sample_list_head = empty_sample_list_tail) then - if (HISTORY_QOS = KEEP_ALL_HISTORY_QOS and RELIABILITY_QOS = RELIABLE_RELIABILITY_QOS) then + if (empty_sample_list_head(ind) = empty_sample_list_tail(ind)) then + if (CONFIG_ARRAY_T(ind).HISTORY_QOS = KEEP_ALL_HISTORY_QOS and CONFIG_ARRAY_T(ind).RELIABILITY_QOS = RELIABLE_RELIABILITY_QOS) then -- Reject Change - done_rtps <= '1'; - ret_rtps <= REJECTED; + done_rtps(ind) <= '1'; + ret_rtps(ind) <= REJECTED; stage_next <= IDLE; -- Update Sample Reject Status - status_sig_next <= status_sig or SAMPLE_REJECTED_STATUS; - sample_rej_cnt_next <= sample_rej_cnt + 1; - sample_rej_cnt_change_next <= sample_rej_cnt_change + 1; - sample_rej_last_reason_next <= REJECTED_BY_SAMPLES_LIMIT; - sample_rej_last_inst_next <= key_hash; + status_sig_next(ind) <= status_sig(ind) or SAMPLE_REJECTED_STATUS; + sample_rej_cnt_next(ind) <= std_logic_vector(unsigned(sample_rej_cnt(ind)) + 1); + sample_rej_cnt_change_next(ind) <= std_logic_vector(unsigned(sample_rej_cnt_change(ind)) + 1); + sample_rej_last_reason_next(ind) <= REJECTED_BY_SAMPLES_LIMIT; + sample_rej_last_inst_next(ind) <= key_hash; else -- Accept Change (Remove Oldest Sample) remove_oldest_sample_next <= '1'; - done_rtps <= '1'; - ret_rtps <= OK; + done_rtps(ind) <= '1'; + ret_rtps(ind) <= OK; -- Insert New Instance - inst_op_start <= '1'; - inst_opcode <= INSERT_INSTANCE; - inst_r.key_hash <= key_hash; - inst_r.status_info <= (ISI_LIVELINESS_FLAG => '1', ISI_NOT_ALIVE_DISPOSED_FLAG => sample_status_info(SSI_DISPOSED_FLAG), others => '0'); - inst_r.sample_cnt <= to_unsigned(1, WORD_WIDTH); - if (TIME_BASED_FILTER_QOS /= DURATION_ZERO) then - inst_r.ignore_deadline <= time + TIME_BASED_FILTER_QOS; + inst_op_start <= '1'; + inst_opcode <= INSERT_INSTANCE; + inst_r.i <= ind; + inst_r.key_hash <= key_hash; + inst_r.status_info <= (ISI_LIVELINESS_FLAG => '1', ISI_NOT_ALIVE_DISPOSED_FLAG => sample_status_info(SSI_DISPOSED_FLAG), others => '0'); + inst_r.sample_cnt <= to_unsigned(1, WORD_WIDTH); + if (CONFIG_ARRAY_T(ind).TIME_BASED_FILTER_QOS /= DURATION_ZERO) then + inst_r.ignore_deadline <= time + CONFIG_ARRAY_T(ind).TIME_BASED_FILTER_QOS; else inst_r.ignore_deadline <= TIME_INVALID; end if; @@ -1845,11 +1962,11 @@ begin tmp_bitmap(writer_id) := '1'; inst_r.writer_bitmap <= to_writer_bitmap_array(tmp_bitmap); - if (DESTINATION_ORDER_QOS = BY_SOURCE_TIMESTAMP_DESTINATION_ORDER_QOS and newest_sample /= SAMPLE_MEMORY_MAX_ADDRESS) then + if (CONFIG_ARRAY_T(ind).DESTINATION_ORDER_QOS = BY_SOURCE_TIMESTAMP_DESTINATION_ORDER_QOS and newest_sample(ind) /= SAMPLE_MEMORY_MAX_ADDRESS) then stage_next <= FIND_POS; next_sample_next <= SAMPLE_MEMORY_MAX_ADDRESS; - prev_sample_next <= newest_sample; - cur_sample_next <= newest_sample; + prev_sample_next <= newest_sample(ind); + cur_sample_next <= newest_sample(ind); cnt_next <= 0; else if (has_data = '1') then @@ -1863,17 +1980,18 @@ begin end if; else -- Accept Change - done_rtps <= '1'; - ret_rtps <= OK; + done_rtps(ind) <= '1'; + ret_rtps(ind) <= OK; -- Insert New Instance - inst_op_start <= '1'; - inst_opcode <= INSERT_INSTANCE; - inst_r.key_hash <= key_hash; - inst_r.status_info <= (ISI_LIVELINESS_FLAG => '1', ISI_NOT_ALIVE_DISPOSED_FLAG => sample_status_info(SSI_DISPOSED_FLAG), others => '0'); - inst_r.sample_cnt <= to_unsigned(1, WORD_WIDTH); - if (TIME_BASED_FILTER_QOS /= DURATION_ZERO) then - inst_r.ignore_deadline <= time + TIME_BASED_FILTER_QOS; + inst_op_start <= '1'; + inst_opcode <= INSERT_INSTANCE; + inst_r.i <= ind; + inst_r.key_hash <= key_hash; + inst_r.status_info <= (ISI_LIVELINESS_FLAG => '1', ISI_NOT_ALIVE_DISPOSED_FLAG => sample_status_info(SSI_DISPOSED_FLAG), others => '0'); + inst_r.sample_cnt <= to_unsigned(1, WORD_WIDTH); + if (CONFIG_ARRAY_T(ind).TIME_BASED_FILTER_QOS /= DURATION_ZERO) then + inst_r.ignore_deadline <= time + CONFIG_ARRAY_T(ind).TIME_BASED_FILTER_QOS; else inst_r.ignore_deadline <= TIME_INVALID; end if; @@ -1881,11 +1999,11 @@ begin tmp_bitmap(writer_id) := '1'; inst_r.writer_bitmap <= to_writer_bitmap_array(tmp_bitmap); - if (DESTINATION_ORDER_QOS = BY_SOURCE_TIMESTAMP_DESTINATION_ORDER_QOS and newest_sample /= SAMPLE_MEMORY_MAX_ADDRESS) then + if (CONFIG_ARRAY_T(ind).DESTINATION_ORDER_QOS = BY_SOURCE_TIMESTAMP_DESTINATION_ORDER_QOS and newest_sample(ind) /= SAMPLE_MEMORY_MAX_ADDRESS) then stage_next <= FIND_POS; next_sample_next <= SAMPLE_MEMORY_MAX_ADDRESS; - prev_sample_next <= newest_sample; - cur_sample_next <= newest_sample; + prev_sample_next <= newest_sample(ind); + cur_sample_next <= newest_sample(ind); cnt_next <= 0; else if (has_data = '1') then @@ -1901,80 +2019,123 @@ begin end if; end if; when FIND_POS => - -- Synthesis Guard - if (DESTINATION_ORDER_QOS = BY_SOURCE_TIMESTAMP_DESTINATION_ORDER_QOS) then - -- Precondition: cur_sample set - - case (cnt) is - -- GET Timestamp 1/2 - when 0 => - sample_valid_in <= '1'; - sample_addr <= cur_sample + SMF_TIMESTAMP_OFFSET; - sample_read <= '1'; + -- Precondition: cur_sample set + assert (CONFIG_ARRAY_T(ind).DESTINATION_ORDER_QOS = BY_SOURCE_TIMESTAMP_DESTINATION_ORDER_QOS) severity FAILURE; + + case (cnt) is + -- GET Timestamp 1/2 + when 0 => + sample_valid_in <= '1'; + sample_addr <= cur_sample + SMF_TIMESTAMP_OFFSET; + sample_read <= '1'; + + -- Memory Flow Control Guard + if (sample_ready_in = '1') then + cnt_next <= cnt + 1; + end if; + -- GET Timestamp 2/2 + when 1 => + sample_valid_in <= '1'; + sample_addr <= cur_sample + SMF_TIMESTAMP_OFFSET + 1; + sample_read <= '1'; + + -- Memory Flow Control Guard + if (sample_ready_in = '1') then + cnt_next <= cnt + 1; + end if; + -- GET Previous Sample + when 2 => + sample_valid_in <= '1'; + sample_addr <= cur_sample + SMF_PREV_ADDR_OFFSET; + sample_read <= '1'; + + -- Memory Flow Control Guard + if (sample_ready_in = '1') then + cnt_next <= cnt + 1; + end if; + -- GET Instance Pointer + when 3 => + sample_valid_in <= '1'; + sample_addr <= cur_sample + SMF_INSTANCE_ADDR_OFFSET; + sample_read <= '1'; + + -- Memory Flow Control Guard + if (sample_ready_in = '1') then + cnt_next <= cnt + 1; + end if; + -- READ Timestamp 1/2 + when 4 => + sample_ready_out <= '1'; + + -- Memory Flow Control Guard + if (sample_valid_out = '1') then + long_latch_next <= sample_read_data; + cnt_next <= cnt + 1; + end if; + -- READ Timestamp 2/2 + when 5 => + sample_ready_out <= '1'; + + -- Memory Flow Control Guard + if (sample_valid_out = '1') then + tmp_dw := (0 => unsigned(long_latch), 1 => unsigned(sample_read_data)); - -- Memory Flow Control Guard - if (sample_ready_in = '1') then - cnt_next <= cnt + 1; - end if; - -- GET Timestamp 2/2 - when 1 => - sample_valid_in <= '1'; - sample_addr <= cur_sample + SMF_TIMESTAMP_OFFSET + 1; - sample_read <= '1'; - - -- Memory Flow Control Guard - if (sample_ready_in = '1') then - cnt_next <= cnt + 1; - end if; - -- GET Previous Sample - when 2 => - sample_valid_in <= '1'; - sample_addr <= cur_sample + SMF_PREV_ADDR_OFFSET; - sample_read <= '1'; - - -- Memory Flow Control Guard - if (sample_ready_in = '1') then - if (WITH_KEY) then - cnt_next <= cnt + 1; + -- Found position (After current slot) + if (ts_latch >= tmp_dw) then + sample_abort_read <= '1'; + prev_sample_next <= cur_sample; + cur_sample_next <= empty_sample_list_head(ind); + if (new_inst = '1') then + if (has_data = '1') then + stage_next <= FINALIZE_PAYLOAD; + cnt_next <= 0; + else + stage_next <= PRE_SAMPLE_FINALIZE; + cnt_next <= 0; + end if; else - cnt_next <= cnt + 2; -- Skip next Stage + stage_next <= UPDATE_INSTANCE; end if; + else + cnt_next <= cnt + 1; end if; - -- GET Instance Pointer - when 3 => - -- Synthesis Guard - if (WITH_KEY) then - sample_valid_in <= '1'; - sample_addr <= cur_sample + SMF_INSTANCE_ADDR_OFFSET; - sample_read <= '1'; - - -- Memory Flow Control Guard - if (sample_ready_in = '1') then + end if; + -- READ Previous Sample Pointer + when 6 => + sample_ready_out <= '1'; + + -- Memory Flow Control Guard + if (sample_valid_out = '1') then + prev_sample_next <= resize(unsigned(sample_read_data),SAMPLE_MEMORY_ADDR_WIDTH); + cnt_next <= cnt + 1; + end if; + -- READ Instance Poiner + when 7 => + sample_ready_out <= '1'; + + -- Memory Flow Control Guard + if (sample_valid_out = '1') then + -- Sample has Same Instance + if (resize(unsigned(sample_read_data),INSTANCE_MEMORY_ADDR_WIDTH) = cur_inst) then + -- Newer Sample of same Instance found + newer_inst_sample_next <= '1'; + -- NOT_ALIVE Sample + if (sample_status_info(SSI_DISPOSED_FLAG) = '1' or sample_status_info(SSI_UNREGISTERED_FLAG) = '1') then + -- NOTE: We drop Dispose and Unregister Samples if a newer Sample of the same Instance exists, because else + -- the Instance State and Generation Counters would have to be recalculated (by crawling through all the Instance Samples) + -- Drop Sample + stage_next <= IDLE; + else cnt_next <= cnt + 1; end if; - end if; - -- READ Timestamp 1/2 - when 4 => - sample_ready_out <= '1'; - - -- Memory Flow Control Guard - if (sample_valid_out = '1') then - long_latch_next <= sample_read_data; - cnt_next <= cnt + 1; - end if; - -- READ Timestamp 2/2 - when 5 => - sample_ready_out <= '1'; - - -- Memory Flow Control Guard - if (sample_valid_out = '1') then - tmp_dw := (0 => unsigned(long_latch), 1 => unsigned(sample_read_data)); - - -- Found position (After current slot) - if (ts_latch >= tmp_dw) then - sample_abort_read <= '1'; - prev_sample_next <= cur_sample; - cur_sample_next <= empty_sample_list_head; + else + -- No previous Slot (Oldest Sample) + if (prev_sample = PAYLOAD_MEMORY_MAX_ADDRESS) then + assert (cur_sample = oldest_sample(ind)) severity FAILURE; + + -- NOTE: Sample is added to HEAD of List + next_sample_next <= cur_sample; + cur_sample_next <= empty_sample_list_head(ind); if (new_inst = '1') then if (has_data = '1') then stage_next <= FINALIZE_PAYLOAD; @@ -1987,120 +2148,61 @@ begin stage_next <= UPDATE_INSTANCE; end if; else - cnt_next <= cnt + 1; + -- Continue Search + cur_sample_next <= prev_sample; + next_sample_next <= cur_sample; + cnt_next <= 0; end if; end if; - -- READ Previous Sample Pointer - when 6 => - sample_ready_out <= '1'; + end if; + -- GET Disposed Generation Count + when 8 => + sample_valid_in <= '1'; + sample_addr <= cur_sample + SMF_DISPOSED_GEN_CNT_OFFSET; + sample_read <= '1'; + + -- Memory Flow Control Guard + if (sample_ready_in = '1') then + cnt_next <= cnt + 1; + end if; + -- GET No Writers Generation Count + when 9 => + sample_valid_in <= '1'; + sample_addr <= cur_sample + SMF_NO_WRITERS_GEN_CNT_OFFSET; + sample_read <= '1'; + + -- Memory Flow Control Guard + if (sample_ready_in = '1') then + cnt_next <= cnt + 1; + end if; + -- READ Disposed Generation Count + when 10 => + sample_ready_out <= '1'; + + -- Memory Flow Control Guard + if (sample_valid_out = '1') then + -- Latch Generation Counter + dis_gen_cnt_latch_next <= unsigned(sample_read_data); - -- Memory Flow Control Guard - if (sample_valid_out = '1') then - prev_sample_next <= resize(unsigned(sample_read_data),SAMPLE_MEMORY_ADDR_WIDTH); - if (WITH_KEY) then - cnt_next <= cnt + 1; - else - cnt_next <= cnt + 2; -- Skip next stage - end if; - end if; - -- READ Instance Poiner - when 7 => - -- Synthesis Guard - if (WITH_KEY) then - sample_ready_out <= '1'; - - -- Memory Flow Control Guard - if (sample_valid_out = '1') then - -- Sample has Same Instance - if (resize(unsigned(sample_read_data),INSTANCE_MEMORY_ADDR_WIDTH) = cur_inst) then - -- Newer Sample of same Instance found - newer_inst_sample_next <= '1'; - -- NOT_ALIVE Sample - if (sample_status_info(SSI_DISPOSED_FLAG) = '1' or sample_status_info(SSI_UNREGISTERED_FLAG) = '1') then - -- NOTE: We drop Dispose and Unregister Samples if a newer Sample of the same Instance exists, because else - -- the Instance State and Generation Counters would have to be recalculated (by crawling through all the Instance Samples) - -- Drop Sample - stage_next <= IDLE; - else - cnt_next <= cnt + 1; - end if; - else - -- No previous Slot (Oldest Sample) - if (prev_sample = PAYLOAD_MEMORY_MAX_ADDRESS) then - assert (cur_sample = oldest_sample) severity FAILURE; - - -- NOTE: Sample is added to HEAD of List - next_sample_next <= cur_sample; - cur_sample_next <= empty_sample_list_head; - if (new_inst = '1') then - if (has_data = '1') then - stage_next <= FINALIZE_PAYLOAD; - cnt_next <= 0; - else - stage_next <= PRE_SAMPLE_FINALIZE; - cnt_next <= 0; - end if; - else - stage_next <= UPDATE_INSTANCE; - end if; - else - -- Continue Search - cur_sample_next <= prev_sample; - next_sample_next <= cur_sample; - cnt_next <= 0; - end if; - end if; - end if; - end if; - -- GET Disposed Generation Count - when 8 => - sample_valid_in <= '1'; - sample_addr <= cur_sample + SMF_DISPOSED_GEN_CNT_OFFSET; - sample_read <= '1'; + cnt_next <= cnt + 1; + end if; + -- READ No Writers Generation Count + when 11 => + sample_ready_out <= '1'; + + -- Memory Flow Control Guard + if (sample_valid_out = '1') then + -- Latch Generation Counter + no_w_gen_cnt_latch_next <= unsigned(sample_read_data); - -- Memory Flow Control Guard - if (sample_ready_in = '1') then - cnt_next <= cnt + 1; - end if; - -- GET No Writers Generation Count - when 9 => - sample_valid_in <= '1'; - sample_addr <= cur_sample + SMF_NO_WRITERS_GEN_CNT_OFFSET; - sample_read <= '1'; - - -- Memory Flow Control Guard - if (sample_ready_in = '1') then - cnt_next <= cnt + 1; - end if; - -- READ Disposed Generation Count - when 10 => - sample_ready_out <= '1'; - - -- Memory Flow Control Guard - if (sample_valid_out = '1') then - -- Latch Generation Counter - dis_gen_cnt_latch_next <= unsigned(sample_read_data); - - cnt_next <= cnt + 1; - end if; - -- READ No Writers Generation Count - when 11 => - sample_ready_out <= '1'; - - -- Memory Flow Control Guard - if (sample_valid_out = '1') then - -- Latch Generation Counter - no_w_gen_cnt_latch_next <= unsigned(sample_read_data); - - -- Continue Search - cur_sample_next <= prev_sample; - next_sample_next <= cur_sample; - cnt_next <= 0; - end if; - when others => - null; - end case; - end if; + -- Continue Search + cur_sample_next <= prev_sample; + next_sample_next <= cur_sample; + cnt_next <= 0; + end if; + when others => + null; + end case; when UPDATE_INSTANCE => -- Precondition inst_data set (IMF_STATUS_FLAG, IMF_WRITER_BITMAP_FLAG, IMF_DISPOSED_CNT_FLAG, IMF_NO_WRITERS_CNT_FLAG, IMF_SAMPLE_CNT_FLAG, IMF_IGNORE_DEADLINE_FLAG) @@ -2108,18 +2210,14 @@ begin tmp_bool := TRUE; -- Memory Operation Guard - if (not WITH_KEY or inst_op_done = '1') then - assert (not WITH_KEY or inst_data.addr /= INSTANCE_MEMORY_MAX_ADDRESS) severity FAILURE; - assert (not WITH_KEY or stable(clk, check_mask(inst_data.field_flags, IMF_STATUS_FLAG or IMF_WRITER_BITMAP_FLAG or IMF_DISPOSED_CNT_FLAG or IMF_NO_WRITERS_CNT_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_IGNORE_DEADLINE_FLAG))) severity FAILURE; + if (inst_op_done = '1') then + assert (inst_data.addr /= INSTANCE_MEMORY_MAX_ADDRESS) severity FAILURE; + assert (stable(clk, inst_data.i = ind and check_mask(inst_data.field_flags, IMF_STATUS_FLAG or IMF_WRITER_BITMAP_FLAG or IMF_DISPOSED_CNT_FLAG or IMF_NO_WRITERS_CNT_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_IGNORE_DEADLINE_FLAG))) severity FAILURE; -- DEFAULT STATUS INFO (LIVELINESS) - if (WITH_KEY) then - tmp_update := IMF_STATUS_FLAG; - inst_r.status_info <= inst_data.status_info; - inst_r.status_info(ISI_LIVELINESS_FLAG) <= '1'; - else - inst_data_next2.status_info(ISI_LIVELINESS_FLAG) <= '1'; - end if; + tmp_update := IMF_STATUS_FLAG; + inst_r.status_info <= inst_data.status_info; + inst_r.status_info(ISI_LIVELINESS_FLAG) <= '1'; -- *WRITER BITMAP* -- Convert Writer Bitmap to SLV @@ -2131,13 +2229,8 @@ begin -- Insert Writer tmp_bitmap(writer_id) := '1'; -- Convert Back - -- Synthesis Guard - if (WITH_KEY) then - inst_r.writer_bitmap <= to_writer_bitmap_array(tmp_bitmap); - tmp_update := tmp_update or IMF_WRITER_BITMAP_FLAG; - else - inst_data_next2.writer_bitmap <= to_writer_bitmap_array(tmp_bitmap); - end if; + inst_r.writer_bitmap <= to_writer_bitmap_array(tmp_bitmap); + tmp_update := tmp_update or IMF_WRITER_BITMAP_FLAG; end if; else -- Write if Writer New for Instance @@ -2145,13 +2238,8 @@ begin -- Insert Writer tmp_bitmap(writer_id) := '0'; -- Convert Back - -- Synthesis Guard - if (WITH_KEY) then - inst_r.writer_bitmap <= to_writer_bitmap_array(tmp_bitmap); - tmp_update := tmp_update or IMF_WRITER_BITMAP_FLAG; - else - inst_data_next2.writer_bitmap <= to_writer_bitmap_array(tmp_bitmap); - end if; + inst_r.writer_bitmap <= to_writer_bitmap_array(tmp_bitmap); + tmp_update := tmp_update or IMF_WRITER_BITMAP_FLAG; end if; end if; @@ -2160,26 +2248,14 @@ begin if (newer_inst_sample = '0') then -- NOT_ALIVE_DISPOSED -> ALIVE Transition if (sample_status_info(SSI_DISPOSED_FLAG) = '0' and sample_status_info(SSI_UNREGISTERED_FLAG) = '0' and inst_data.status_info(ISI_NOT_ALIVE_DISPOSED_FLAG) = '1') then - -- Synthesis Guard - if (WITH_KEY) then - tmp_update := tmp_update or IMF_DISPOSED_CNT_FLAG; - inst_r.disposed_gen_cnt <= inst_data.disposed_gen_cnt + 1; - inst_r.status_info(ISI_VIEW_FLAG) <= '0'; - else - inst_data_next2.disposed_gen_cnt <= inst_data.disposed_gen_cnt + 1; - inst_data_next2.status_info(ISI_VIEW_FLAG) <= '0'; - end if; + tmp_update := tmp_update or IMF_DISPOSED_CNT_FLAG; + inst_r.disposed_gen_cnt <= inst_data.disposed_gen_cnt + 1; + inst_r.status_info(ISI_VIEW_FLAG) <= '0'; -- NOT_ALIVE_NO_WRITERS -> ALIVE Transition OR NOT_ALIVE_NO_WRITERS -> NOT_ALIVE_DISPOSED Transition elsif (sample_status_info(SSI_UNREGISTERED_FLAG) = '0' and inst_data.status_info(ISI_NOT_ALIVE_NO_WRITERS_FLAG) = '1') then - -- Synthesis Guard - if (WITH_KEY) then - tmp_update := tmp_update or IMF_NO_WRITERS_CNT_FLAG; - inst_r.no_writers_gen_cnt <= inst_data.no_writers_gen_cnt + 1; - inst_r.status_info(ISI_VIEW_FLAG) <= '0'; - else - inst_data_next2.no_writers_gen_cnt <= inst_data.no_writers_gen_cnt + 1; - inst_data_next2.status_info(ISI_VIEW_FLAG) <= '0'; - end if; + tmp_update := tmp_update or IMF_NO_WRITERS_CNT_FLAG; + inst_r.no_writers_gen_cnt <= inst_data.no_writers_gen_cnt + 1; + inst_r.status_info(ISI_VIEW_FLAG) <= '0'; end if; end if; @@ -2191,14 +2267,8 @@ begin tmp_bool := FALSE; -- Only Update Instance State if Sample if newest elsif (newer_inst_sample = '0') then - -- Synthesis Guard - if (WITH_KEY) then - inst_r.status_info(ISI_NOT_ALIVE_DISPOSED_FLAG) <= '1'; - inst_r.status_info(ISI_NOT_ALIVE_NO_WRITERS_FLAG) <= '0'; - else - inst_data_next2.status_info(ISI_NOT_ALIVE_DISPOSED_FLAG) <= '1'; - inst_data_next2.status_info(ISI_NOT_ALIVE_NO_WRITERS_FLAG) <= '0'; - end if; + inst_r.status_info(ISI_NOT_ALIVE_DISPOSED_FLAG) <= '1'; + inst_r.status_info(ISI_NOT_ALIVE_NO_WRITERS_FLAG) <= '0'; end if; -- * -> NOT_ALIVE_NO_WRITERS Transition elsif (sample_status_info(SSI_UNREGISTERED_FLAG) = '1' and tmp_bitmap = (tmp_bitmap'reverse_range => '0')) then @@ -2207,14 +2277,8 @@ begin tmp_bool := FALSE; -- Only Update Instance State if Sample if newest elsif (newer_inst_sample = '0') then - -- Synthesis Guard - if (WITH_KEY) then - inst_r.status_info(ISI_NOT_ALIVE_DISPOSED_FLAG) <= '0'; - inst_r.status_info(ISI_NOT_ALIVE_NO_WRITERS_FLAG) <= '1'; - else - inst_data_next2.status_info(ISI_NOT_ALIVE_DISPOSED_FLAG) <= '0'; - inst_data_next2.status_info(ISI_NOT_ALIVE_NO_WRITERS_FLAG) <= '1'; - end if; + inst_r.status_info(ISI_NOT_ALIVE_DISPOSED_FLAG) <= '0'; + inst_r.status_info(ISI_NOT_ALIVE_NO_WRITERS_FLAG) <= '1'; end if; -- * -> ALIVE Transition elsif (sample_status_info(SSI_UNREGISTERED_FLAG) = '0' and sample_status_info(SSI_DISPOSED_FLAG) = '0') then @@ -2228,14 +2292,8 @@ begin end if; -- Only Update Instance State if Sample if newest elsif (newer_inst_sample = '0') then - -- Synthesis Guard - if (WITH_KEY) then - inst_r.status_info(ISI_NOT_ALIVE_DISPOSED_FLAG) <= '0'; - inst_r.status_info(ISI_NOT_ALIVE_NO_WRITERS_FLAG) <= '0'; - else - inst_data_next2.status_info(ISI_NOT_ALIVE_DISPOSED_FLAG) <= '0'; - inst_data_next2.status_info(ISI_NOT_ALIVE_NO_WRITERS_FLAG) <= '0'; - end if; + inst_r.status_info(ISI_NOT_ALIVE_DISPOSED_FLAG) <= '0'; + inst_r.status_info(ISI_NOT_ALIVE_NO_WRITERS_FLAG) <= '0'; end if; else tmp_bool := FALSE; @@ -2243,66 +2301,48 @@ begin -- *INSTANCE SAMPLE COUNT* if (tmp_bool) then - -- Synthesis Guard - if (WITH_KEY) then - tmp_update := tmp_update or IMF_SAMPLE_CNT_FLAG; - inst_r.sample_cnt <= inst_data.sample_cnt + 1; - else - inst_data_next2.sample_cnt <= inst_data.sample_cnt + 1; - end if; + tmp_update := tmp_update or IMF_SAMPLE_CNT_FLAG; + inst_r.sample_cnt <= inst_data.sample_cnt + 1; end if; -- *IGNORE DEADLINE* - if (TIME_BASED_FILTER_QOS /= DURATION_ZERO) then - -- Synthesis Guard - if (WITH_KEY) then - tmp_update := tmp_update or IMF_IGNORE_DEADLINE_FLAG; - inst_r.ignore_deadline <= time + TIME_BASED_FILTER_QOS; - else - inst_data_next2.ignore_deadline <= time + TIME_BASED_FILTER_QOS; - end if; + if (CONFIG_ARRAY_T(ind).TIME_BASED_FILTER_QOS /= DURATION_ZERO) then + tmp_update := tmp_update or IMF_IGNORE_DEADLINE_FLAG; + inst_r.ignore_deadline <= time + CONFIG_ARRAY_T(ind).TIME_BASED_FILTER_QOS; end if; -- *STALE INSTANCE COUNT* if (tmp_bool) then - -- Synthesis Guard - if (WITH_KEY) then - -- Instance was Stale - if (inst_data.sample_cnt = 0 and inst_data.writer_bitmap = ZERO_WRITER_BITMAP_ARRAY) then - assert (stale_inst_cnt /= 0) severity FAILURE; - -- NOTE: The UPDATE_INSTANCE state is only taken if a new Sample is added to an existing Instance. - -- Since Instances with Samples are not stale, we have to unmark the Instance. - stale_inst_cnt_next <= stale_inst_cnt - 1; - end if; + -- Instance was Stale + if (inst_data.sample_cnt = 0 and inst_data.writer_bitmap = ZERO_WRITER_BITMAP_ARRAY) then + assert (stale_inst_cnt(ind) /= 0) severity FAILURE; + -- NOTE: The UPDATE_INSTANCE state is only taken if a new Sample is added to an existing Instance. + -- Since Instances with Samples are not stale, we have to unmark the Instance. + stale_inst_cnt_next(ind) <= stale_inst_cnt(ind) - 1; end if; else - -- Synthesis Guard - if (WITH_KEY) then - -- Stale Instance Transition - if (inst_data.sample_cnt = 0 and inst_data.writer_bitmap /= ZERO_WRITER_BITMAP_ARRAY and tmp_bitmap = (tmp_bitmap'reverse_range => '0')) then - stale_inst_cnt_next <= stale_inst_cnt + 1; - end if; + -- Stale Instance Transition + if (inst_data.sample_cnt = 0 and inst_data.writer_bitmap /= ZERO_WRITER_BITMAP_ARRAY and tmp_bitmap = (tmp_bitmap'reverse_range => '0')) then + stale_inst_cnt_next(ind) <= stale_inst_cnt(ind) + 1; end if; end if; - -- Synthesis Guard - if (WITH_KEY) then - -- UPDATE Instance - inst_op_start <= '1'; - inst_opcode <= UPDATE_INSTANCE; - inst_r.addr <= inst_data.addr; - inst_r.field_flags <= tmp_update; - end if; + -- UPDATE Instance + inst_op_start <= '1'; + inst_opcode <= UPDATE_INSTANCE; + inst_r.i <= ind; + inst_r.addr <= inst_data.addr; + inst_r.field_flags <= tmp_update; if (not tmp_bool) then -- DONE (Drop Sample) stage_next <= IDLE; elsif (has_data = '1') then - stage_next <= FINALIZE_PAYLOAD; - cnt_next <= 0; + stage_next <= FINALIZE_PAYLOAD; + cnt_next <= 0; else - stage_next <= PRE_SAMPLE_FINALIZE; - cnt_next <= 0; + stage_next <= PRE_SAMPLE_FINALIZE; + cnt_next <= 0; end if; end if; when FINALIZE_PAYLOAD => @@ -2337,7 +2377,7 @@ begin -- Memory Control Flow Guard if (payload_valid_out = '1') then -- Fix New Empty List Head - empty_payload_list_head_next <= resize(unsigned(payload_read_data),PAYLOAD_MEMORY_ADDR_WIDTH); + empty_payload_list_head_next(ind) <= resize(unsigned(payload_read_data),PAYLOAD_MEMORY_ADDR_WIDTH); stage_next <= PRE_SAMPLE_FINALIZE; cnt_next <= 0; @@ -2349,9 +2389,9 @@ begin -- Precondition: cur_sample set, inst_data set (IMF_DISPOSED_CNT_FLAG, IMF_NO_WRITERS_CNT_FLAG) -- Wait for instance Update to Complete - if (not WITH_KEY or inst_op_done = '1') then - assert (not WITH_KEY or inst_data.addr /= INSTANCE_MEMORY_MAX_ADDRESS) severity FAILURE; - assert (not WITH_KEY or stable(clk, check_mask(inst_data.field_flags, IMF_DISPOSED_CNT_FLAG or IMF_NO_WRITERS_CNT_FLAG))) severity FAILURE; + if (inst_op_done = '1') then + assert (inst_data.addr /= INSTANCE_MEMORY_MAX_ADDRESS) severity FAILURE; + assert (stable(clk, inst_data.i = ind and check_mask(inst_data.field_flags, IMF_DISPOSED_CNT_FLAG or IMF_NO_WRITERS_CNT_FLAG))) severity FAILURE; case (cnt) is -- SET Disposed Generation Counter @@ -2383,12 +2423,12 @@ begin -- Memory Flow Control Guard if (sample_ready_in = '1') then -- First Sample - if (newest_sample = SAMPLE_MEMORY_MAX_ADDRESS) then + if (newest_sample(ind) = SAMPLE_MEMORY_MAX_ADDRESS) then stage_next <= FINALIZE_SAMPLE; next_sample_next <= SAMPLE_MEMORY_MAX_ADDRESS; prev_sample_next <= SAMPLE_MEMORY_MAX_ADDRESS; cnt_next <= 0; - elsif (DESTINATION_ORDER_QOS = BY_SOURCE_TIMESTAMP_DESTINATION_ORDER_QOS) then + elsif (CONFIG_ARRAY_T(ind).DESTINATION_ORDER_QOS = BY_SOURCE_TIMESTAMP_DESTINATION_ORDER_QOS) then stage_next <= FIX_POINTERS; if (prev_sample = SAMPLE_MEMORY_MAX_ADDRESS) then cnt_next <= 1; -- Skip to Previous Pointer Fix @@ -2398,7 +2438,7 @@ begin else stage_next <= FIX_POINTERS; next_sample_next <= SAMPLE_MEMORY_MAX_ADDRESS; - prev_sample_next <= newest_sample; + prev_sample_next <= newest_sample(ind); cnt_next <= 0; end if; end if; @@ -2415,16 +2455,16 @@ begin -- Fix Next Pointer sample_valid_in <= '1'; sample_addr <= prev_sample + SMF_NEXT_ADDR_OFFSET; - sample_write_data <= std_logic_vector(resize(empty_sample_list_head,WORD_WIDTH)); + sample_write_data <= std_logic_vector(resize(empty_sample_list_head(ind),WORD_WIDTH)); -- Memory Flow Control Guard if (sample_ready_in = '1') then -- No next Slot (Newest Sample) if (next_sample = SAMPLE_MEMORY_MAX_ADDRESS) then - assert (prev_sample = newest_sample) report "Next Sample is MAX_ADDRESS, but sample is not NEWEST (TAIL)" severity FAILURE; + assert (prev_sample = newest_sample(ind)) report "Next Sample is MAX_ADDRESS, but sample is not NEWEST (TAIL)" severity FAILURE; stage_next <= FINALIZE_SAMPLE; - cur_sample_next <= empty_sample_list_head; + cur_sample_next <= empty_sample_list_head(ind); cnt_next <= 0; else cnt_next <= 1; @@ -2435,12 +2475,12 @@ begin -- Fix Previous Pointer sample_valid_in <= '1'; sample_addr <= next_sample + SMF_PREV_ADDR_OFFSET; - sample_write_data <= std_logic_vector(resize(empty_sample_list_head,WORD_WIDTH)); + sample_write_data <= std_logic_vector(resize(empty_sample_list_head(ind),WORD_WIDTH)); -- Memory Flow Control Guard if (sample_ready_in = '1') then stage_next <= FINALIZE_SAMPLE; - cur_sample_next <= empty_sample_list_head; + cur_sample_next <= empty_sample_list_head(ind); cnt_next <= 0; end if; when others => @@ -2457,26 +2497,18 @@ begin sample_read <= '1'; -- Memory Flow Control Guard if (sample_ready_in = '1') then - -- Synthesis Guard - if (WITH_KEY) then - cnt_next <= cnt + 1; - else - cnt_next <= cnt + 2; - end if; + cnt_next <= cnt + 1; end if; -- SET Instance Pointer when 1 => - -- Synthesis Guard - if (WITH_KEY) then - -- Write Instance Pointer - sample_valid_in <= '1'; - sample_addr <= cur_sample + SMF_INSTANCE_ADDR_OFFSET; - sample_write_data <= std_logic_vector(resize(cur_inst,WORD_WIDTH)); - - -- Memory Flow Control Guard - if (sample_ready_in = '1') then - cnt_next <= cnt + 1; - end if; + -- Write Instance Pointer + sample_valid_in <= '1'; + sample_addr <= cur_sample + SMF_INSTANCE_ADDR_OFFSET; + sample_write_data <= std_logic_vector(resize(cur_inst,WORD_WIDTH)); + + -- Memory Flow Control Guard + if (sample_ready_in = '1') then + cnt_next <= cnt + 1; end if; -- SET Previous Pointer when 2 => @@ -2509,44 +2541,37 @@ begin if (sample_valid_out = '1') then -- Fix new Empty List Head - empty_sample_list_head_next <= resize(unsigned(sample_read_data),SAMPLE_MEMORY_ADDR_WIDTH); + empty_sample_list_head_next(ind) <= resize(unsigned(sample_read_data),SAMPLE_MEMORY_ADDR_WIDTH); -- If newest Sample is now previous, select current sample as new newest - if (newest_sample = prev_sample) then - newest_sample_next <= cur_sample; + if (newest_sample(ind) = prev_sample) then + newest_sample_next(ind) <= cur_sample; end if; -- If current Sample as no predecessor, it is the oldest if (prev_sample = SAMPLE_MEMORY_MAX_ADDRESS) then - oldest_sample_next <= cur_sample; + oldest_sample_next(ind) <= cur_sample; end if; -- Signal Data Available - status_sig_next <= status_sig or DATA_AVAILABLE_STATUS; + status_sig_next(ind) <= status_sig(ind) or DATA_AVAILABLE_STATUS; -- Update Lifespan Check Time if (lifespan /= TIME_INVALID and lifespan < lifespan_time) then lifespan_time_next <= lifespan; end if; - if (WITH_KEY and remove_oldest_inst_sample = '1') then - assert (oldest_sample /= SAMPLE_MEMORY_MAX_ADDRESS) severity FAILURE; + if (remove_oldest_inst_sample = '1') then + assert (oldest_sample(ind) /= SAMPLE_MEMORY_MAX_ADDRESS) severity FAILURE; - cur_sample_next <= oldest_sample; + cur_sample_next <= oldest_sample(ind); stage_next <= FIND_OLDEST_INST_SAMPLE; cnt_next <= 0; elsif (remove_oldest_sample = '1') then - assert (oldest_sample /= SAMPLE_MEMORY_MAX_ADDRESS) severity FAILURE; + assert (oldest_sample(ind) /= SAMPLE_MEMORY_MAX_ADDRESS) severity FAILURE; - -- Synthesis Guard - if (WITH_KEY) then - stage_next <= GET_OLDEST_SAMPLE_INSTANCE; - cnt_next <= 0; - else - cur_sample_next <= oldest_sample; - stage_next <= REMOVE_SAMPLE; - cnt_next <= 0; - end if; + stage_next <= GET_OLDEST_SAMPLE_INSTANCE; + cnt_next <= 0; else -- DONE stage_next <= IDLE; @@ -2559,9 +2584,9 @@ begin -- Precondition: cur_sample set, cur_inst set, inst_data set (IMF_DISPOSED_CNT_FLAG, IMF_NO_WRITERS_CNT_FLAG) -- Wait for Instane Data - if (not WITH_KEY or inst_op_done = '1') then - assert (not WITH_KEY or inst_data.addr /= INSTANCE_MEMORY_MAX_ADDRESS) severity FAILURE; - assert (not WITH_KEY or stable(clk, check_mask(inst_data.field_flags, IMF_DISPOSED_CNT_FLAG or IMF_NO_WRITERS_CNT_FLAG))) severity FAILURE; + if (inst_op_done = '1') then + assert (inst_data.addr /= INSTANCE_MEMORY_MAX_ADDRESS) severity FAILURE; + assert (stable(clk, inst_data.i = ind and check_mask(inst_data.field_flags, IMF_DISPOSED_CNT_FLAG or IMF_NO_WRITERS_CNT_FLAG))) severity FAILURE; case (cnt) is -- GET Next Sample (Empty List) @@ -2632,24 +2657,17 @@ begin -- Memory Flow Control Guard if (sample_ready_in = '1') then - if (WITH_KEY) then - cnt_next <= cnt + 1; - else - cnt_next <= cnt + 2; -- Skip next Stage - end if; + cnt_next <= cnt + 1; end if; -- SET Instance Pointer when 7 => - -- Synthesis Guard - if (WITH_KEY) then - sample_valid_in <= '1'; - sample_addr <= cur_sample + SMF_INSTANCE_ADDR_OFFSET; - sample_write_data <= std_logic_vector(resize(cur_inst,WORD_WIDTH)); - - -- Memory Flow Control Guard - if (sample_ready_in = '1') then - cnt_next <= cnt + 1; - end if; + sample_valid_in <= '1'; + sample_addr <= cur_sample + SMF_INSTANCE_ADDR_OFFSET; + sample_write_data <= std_logic_vector(resize(cur_inst,WORD_WIDTH)); + + -- Memory Flow Control Guard + if (sample_ready_in = '1') then + cnt_next <= cnt + 1; end if; -- SET Disposed Generation Count when 8 => @@ -2675,7 +2693,7 @@ begin when 10 => sample_valid_in <= '1'; sample_addr <= cur_sample + SMF_PREV_ADDR_OFFSET; - sample_write_data <= std_logic_vector(resize(newest_sample,WORD_WIDTH)); + sample_write_data <= std_logic_vector(resize(newest_sample(ind),WORD_WIDTH)); -- Memory Flow Control Guard if (sample_ready_in = '1') then @@ -2689,14 +2707,14 @@ begin -- Memory Flow Control Guard if (sample_ready_in = '1') then - assert (newest_sample /= SAMPLE_MEMORY_MAX_ADDRESS) severity FAILURE; + assert (newest_sample(ind) /= SAMPLE_MEMORY_MAX_ADDRESS) severity FAILURE; cnt_next <= cnt + 1; end if; -- SET Next Sample Pointer (Previous Sample) when 12 => sample_valid_in <= '1'; - sample_addr <= newest_sample + SMF_NEXT_ADDR_OFFSET; - sample_write_data <= std_logic_vector(resize(empty_sample_list_head,WORD_WIDTH)); + sample_addr <= newest_sample(ind) + SMF_NEXT_ADDR_OFFSET; + sample_write_data <= std_logic_vector(resize(empty_sample_list_head(ind),WORD_WIDTH)); -- Memory Flow Control Guard if (sample_ready_in = '1') then @@ -2709,30 +2727,23 @@ begin -- Memory Flow Control Guard if (sample_valid_out = '1') then -- Update Sample List Pointer - newest_sample_next <= cur_sample; - empty_sample_list_head_next <= resize(unsigned(sample_read_data), SAMPLE_MEMORY_ADDR_WIDTH); + newest_sample_next(ind) <= cur_sample; + empty_sample_list_head_next(ind) <= resize(unsigned(sample_read_data), SAMPLE_MEMORY_ADDR_WIDTH); -- Signal Data Available - status_sig_next <= status_sig or DATA_AVAILABLE_STATUS; + status_sig_next(ind) <= status_sig(ind) or DATA_AVAILABLE_STATUS; - if (WITH_KEY and remove_oldest_inst_sample = '1') then - assert (oldest_sample /= SAMPLE_MEMORY_MAX_ADDRESS) severity FAILURE; + if (remove_oldest_inst_sample = '1') then + assert (oldest_sample(ind) /= SAMPLE_MEMORY_MAX_ADDRESS) severity FAILURE; - cur_sample_next <= oldest_sample; + cur_sample_next <= oldest_sample(ind); stage_next <= FIND_OLDEST_INST_SAMPLE; cnt_next <= 0; elsif (remove_oldest_sample = '1') then - assert (oldest_sample /= SAMPLE_MEMORY_MAX_ADDRESS) severity FAILURE; + assert (oldest_sample(ind) /= SAMPLE_MEMORY_MAX_ADDRESS) severity FAILURE; - -- Synthesis Guard - if (WITH_KEY) then - stage_next <= GET_OLDEST_SAMPLE_INSTANCE; - cnt_next <= 0; - else - cur_sample_next <= oldest_sample; - stage_next <= REMOVE_SAMPLE; - cnt_next <= 0; - end if; + stage_next <= GET_OLDEST_SAMPLE_INSTANCE; + cnt_next <= 0; elsif (trigger_sample_gen = '1') then -- Continue stage_next <= PROCESS_PENDING_SAMPLE_GENERATION; @@ -2747,104 +2758,99 @@ begin end case; end if; when GET_OLDEST_SAMPLE_INSTANCE => - -- Synthesis Guard - if (WITH_KEY) then - case (cnt) is - -- GET Instance Pointer (Oldest Sample) - when 0 => - sample_valid_in <= '1'; - sample_addr <= oldest_sample + SMF_INSTANCE_ADDR_OFFSET; - sample_read <= '1'; + case (cnt) is + -- GET Instance Pointer (Oldest Sample) + when 0 => + sample_valid_in <= '1'; + sample_addr <= oldest_sample(ind) + SMF_INSTANCE_ADDR_OFFSET; + sample_read <= '1'; + + -- Memory Flow Control Guard + if (sample_ready_in = '1') then + cnt_next <= cnt + 1; + end if; + -- READ Instance Pointer (Oldest Sample) + when 1 => + -- Memory Operation Guard + if (inst_op_done = '1') then + sample_ready_out <= '1'; -- Memory Flow Control Guard - if (sample_ready_in = '1') then - cnt_next <= cnt + 1; + if (sample_valid_out = '1') then + cur_inst_next <= resize(unsigned(sample_read_data),INSTANCE_MEMORY_ADDR_WIDTH); + cur_sample_next <= oldest_sample(ind); + stage_next <= REMOVE_SAMPLE; + cnt_next <= 0; end if; - -- READ Instance Pointer (Oldest Sample) - when 1 => - -- Memory Operation Guard - if (inst_op_done = '1') then - sample_ready_out <= '1'; - - -- Memory Flow Control Guard - if (sample_valid_out = '1') then - cur_inst_next <= resize(unsigned(sample_read_data),INSTANCE_MEMORY_ADDR_WIDTH); - cur_sample_next <= oldest_sample; - stage_next <= REMOVE_SAMPLE; - cnt_next <= 0; - end if; - end if; - when others => - null; - end case; - end if; + end if; + when others => + null; + end case; when FIND_OLDEST_INST_SAMPLE => -- Precondition: cur_sample set - -- Synthesis Guard - if (WITH_KEY) then - case (cnt) is - -- GET Instance Pointer - when 0 => - sample_valid_in <= '1'; - sample_addr <= cur_sample + SMF_INSTANCE_ADDR_OFFSET; - sample_read <= '1'; - - -- Memory Flow Control Guard - if (sample_ready_in = '1') then - cnt_next <= cnt + 1; - end if; - -- GET Next Sample - when 1 => - sample_valid_in <= '1'; - sample_addr <= cur_sample + SMF_NEXT_ADDR_OFFSET; - sample_read <= '1'; - - -- Memory Flow Control Guard - if (sample_ready_in = '1') then - cnt_next <= cnt + 1; - end if; - -- READ Instance Pointer - when 2 => - sample_ready_out <= '1'; - - -- Memory Flow Control Guard - if (sample_valid_out = '1') then - -- Oldest Instance Sample Found - if (resize(unsigned(sample_read_data),INSTANCE_MEMORY_ADDR_WIDTH) = cur_inst) then - sample_abort_read <= '1'; - stage_next <= REMOVE_SAMPLE; - cnt_next <= 0; - else - cnt_next <= cnt + 1; - end if; - end if; - -- READ Next Sample - when 3 => - sample_ready_out <= '1'; - - -- Memory Flow Control Guard - if (sample_valid_out = '1') then - cur_sample_next <= resize(unsigned(sample_read_data),SAMPLE_MEMORY_ADDR_WIDTH); + case (cnt) is + -- GET Instance Pointer + when 0 => + sample_valid_in <= '1'; + sample_addr <= cur_sample + SMF_INSTANCE_ADDR_OFFSET; + sample_read <= '1'; + + -- Memory Flow Control Guard + if (sample_ready_in = '1') then + cnt_next <= cnt + 1; + end if; + -- GET Next Sample + when 1 => + sample_valid_in <= '1'; + sample_addr <= cur_sample + SMF_NEXT_ADDR_OFFSET; + sample_read <= '1'; + + -- Memory Flow Control Guard + if (sample_ready_in = '1') then + cnt_next <= cnt + 1; + end if; + -- READ Instance Pointer + when 2 => + sample_ready_out <= '1'; + + -- Memory Flow Control Guard + if (sample_valid_out = '1') then + -- Oldest Instance Sample Found + if (resize(unsigned(sample_read_data),INSTANCE_MEMORY_ADDR_WIDTH) = cur_inst) then + sample_abort_read <= '1'; + stage_next <= REMOVE_SAMPLE; cnt_next <= 0; + else + cnt_next <= cnt + 1; end if; - when others => - null; - end case; - end if; + end if; + -- READ Next Sample + when 3 => + sample_ready_out <= '1'; + + -- Memory Flow Control Guard + if (sample_valid_out = '1') then + cur_sample_next <= resize(unsigned(sample_read_data),SAMPLE_MEMORY_ADDR_WIDTH); + cnt_next <= 0; + end if; + when others => + null; + end case; when REMOVE_SAMPLE => -- Precondition: cur_sample set, cur_inst set case (cnt) is -- GET Instance Data when 0 => - if (not WITH_KEY or (cur_inst = inst_data.addr and check_mask(inst_data.field_flags, IMF_SAMPLE_CNT_FLAG or IMF_WRITER_BITMAP_FLAG))) then + if (cur_inst = inst_data.addr and inst_data.i = ind and check_mask(inst_data.field_flags, IMF_SAMPLE_CNT_FLAG or IMF_WRITER_BITMAP_FLAG)) then cnt_next <= cnt + 1; else -- Memory Operation Guard if (inst_op_done = '1') then inst_op_start <= '1'; inst_opcode <= GET_INSTANCE; + inst_r.i <= ind; inst_r.addr <= cur_inst; inst_r.field_flags <= IMF_SAMPLE_CNT_FLAG or IMF_WRITER_BITMAP_FLAG or IMF_STATUS_FLAG; cnt_next <= cnt + 1; @@ -2896,9 +2902,9 @@ begin next_sample_next <= resize(unsigned(sample_read_data),SAMPLE_MEMORY_ADDR_WIDTH); -- Sample Memory Full - if (empty_sample_list_head = SAMPLE_MEMORY_MAX_ADDRESS) then - empty_sample_list_head_next <= cur_sample; - empty_sample_list_tail_next <= cur_sample; + if (empty_sample_list_head(ind) = SAMPLE_MEMORY_MAX_ADDRESS) then + empty_sample_list_head_next(ind) <= cur_sample; + empty_sample_list_tail_next(ind) <= cur_sample; cnt_next <= cnt + 2; --Skip Next Step else cnt_next <= cnt + 1; @@ -2908,7 +2914,7 @@ begin when 6 => -- Add Current Sample after Empty List Tail sample_valid_in <= '1'; - sample_addr <= empty_sample_list_tail + SMF_NEXT_ADDR_OFFSET; + sample_addr <= empty_sample_list_tail(ind) + SMF_NEXT_ADDR_OFFSET; sample_write_data <= std_logic_vector(resize(cur_sample,WORD_WIDTH)); -- Memory Flow Control Guard @@ -2925,23 +2931,23 @@ begin -- Memory Flow Control Guard if (sample_ready_in = '1') then -- Fix Empty List Pointers - empty_sample_list_tail_next <= cur_sample; + empty_sample_list_tail_next(ind) <= cur_sample; -- Current Sample is Newest (Occupied List Tail) if (next_sample = SAMPLE_MEMORY_MAX_ADDRESS) then - assert (cur_sample = newest_sample) report "Next Sample is MAX_ADDR, but cur_sample /= newest_sample" severity FAILURE; + assert (cur_sample = newest_sample(ind)) report "Next Sample is MAX_ADDR, but cur_sample /= newest_sample" severity FAILURE; -- Fix Newest Pointer - newest_sample_next <= prev_sample; + newest_sample_next(ind) <= prev_sample; -- Current Sample is Oldest (List Head) if (prev_sample = SAMPLE_MEMORY_MAX_ADDRESS) then - assert (cur_sample = oldest_sample) report "Previous Sample is MAX_ADDR, but cur_sample /= oldest_sample" severity FAILURE; - assert (newest_sample = oldest_sample) report "Previous and Next Sample is MAX_ADDR, but cur_sample /= newest_sample /= oldest_sample" severity FAILURE; + assert (cur_sample = oldest_sample(ind)) report "Previous Sample is MAX_ADDR, but cur_sample /= oldest_sample" severity FAILURE; + assert (newest_sample(ind) = oldest_sample(ind)) report "Previous and Next Sample is MAX_ADDR, but cur_sample /= newest_sample /= oldest_sample" severity FAILURE; -- NOTE: Sample Memory Empty (newest_sample also set to MAX_ADDR) -- Fix Oldest Pointer - oldest_sample_next <= SAMPLE_MEMORY_MAX_ADDRESS; + oldest_sample_next(ind) <= SAMPLE_MEMORY_MAX_ADDRESS; cnt_next <= cnt + 3; -- Skip next 2 steps else @@ -2962,10 +2968,10 @@ begin if (sample_ready_in = '1') then -- Current Sample is oldest sample (List Head) if (prev_sample = SAMPLE_MEMORY_MAX_ADDRESS) then - assert (cur_sample = oldest_sample) report "Previous Sample is MAX_ADDR, but cur_sample /= oldest_sample" severity FAILURE; + assert (cur_sample = oldest_sample(ind)) report "Previous Sample is MAX_ADDR, but cur_sample /= oldest_sample" severity FAILURE; -- Fix Oldest Pointer - oldest_sample_next <= next_sample; + oldest_sample_next(ind) <= next_sample; cnt_next <= cnt + 2; -- Skip next step else @@ -2994,9 +3000,9 @@ begin if (resize(unsigned(sample_read_data),PAYLOAD_MEMORY_ADDR_WIDTH) = PAYLOAD_MEMORY_MAX_ADDRESS) then stage_next <= POST_SAMPLE_REMOVE; -- Payload Memory Full - elsif (empty_payload_list_head = PAYLOAD_MEMORY_MAX_ADDRESS) then + elsif (empty_payload_list_head(ind) = PAYLOAD_MEMORY_MAX_ADDRESS) then -- Fix Empty List Head - empty_payload_list_head_next <= resize(unsigned(sample_read_data),PAYLOAD_MEMORY_ADDR_WIDTH); + empty_payload_list_head_next(ind) <= resize(unsigned(sample_read_data),PAYLOAD_MEMORY_ADDR_WIDTH); stage_next <= POST_SAMPLE_REMOVE; else @@ -3033,10 +3039,10 @@ begin when 13 => payload_valid_in <= '1'; payload_addr <= cur_payload + PMF_NEXT_ADDR_OFFSET; - payload_write_data <= std_logic_vector(resize(empty_payload_list_head,WORD_WIDTH)); + payload_write_data <= std_logic_vector(resize(empty_payload_list_head(ind),WORD_WIDTH)); -- Fix Empty List Head - empty_payload_list_head_next <= first_payload; + empty_payload_list_head_next(ind) <= first_payload; -- Memory Flow Control Guard if (payload_ready_in = '1') then @@ -3049,26 +3055,22 @@ begin -- Precondition: inst_data set (IMF_SAMPLE_CNT_FLAG, IMF_WRITER_BITMAP_FLAG, IMF_STATUS_FLAG) -- Memory Operation Guard - if (not WITH_KEY or inst_op_done = '1') then - assert (not WITH_KEY or inst_data.addr /= INSTANCE_MEMORY_MAX_ADDRESS) severity FAILURE; - assert (not WITH_KEY or stable(clk, check_mask(inst_data.field_flags, IMF_SAMPLE_CNT_FLAG or IMF_WRITER_BITMAP_FLAG or IMF_STATUS_FLAG))) severity FAILURE; + if (inst_op_done = '1') then + assert (inst_data.addr /= INSTANCE_MEMORY_MAX_ADDRESS) severity FAILURE; + assert (stable(clk, inst_data.i = ind and check_mask(inst_data.field_flags, IMF_SAMPLE_CNT_FLAG or IMF_WRITER_BITMAP_FLAG or IMF_STATUS_FLAG))) severity FAILURE; - -- Synthesis Guard - if (WITH_KEY) then - -- Stale Instance Update - if (inst_data.sample_cnt = 1 and inst_data.writer_bitmap = ZERO_WRITER_BITMAP_ARRAY) then - stale_inst_cnt_next <= stale_inst_cnt + 1; - end if; - - inst_op_start <= '1'; - inst_opcode <= UPDATE_INSTANCE; - inst_r.addr <= inst_data.addr; - inst_r.field_flags <= IMF_SAMPLE_CNT_FLAG; - inst_r.sample_cnt <= inst_data.sample_cnt - 1; - else - inst_data_next2.sample_cnt <= inst_data.sample_cnt - 1; + -- Stale Instance Update + if (inst_data.sample_cnt = 1 and inst_data.writer_bitmap = ZERO_WRITER_BITMAP_ARRAY) then + stale_inst_cnt_next(ind) <= stale_inst_cnt(ind) + 1; end if; + inst_op_start <= '1'; + inst_opcode <= UPDATE_INSTANCE; + inst_r.i <= ind; + inst_r.addr <= inst_data.addr; + inst_r.field_flags <= IMF_SAMPLE_CNT_FLAG; + inst_r.sample_cnt <= inst_data.sample_cnt - 1; + if (wait_for_sample_removal = '1' or inst_data.status_info(ISI_GENERATE_SAMPLE_FLAG) = '1') then trigger_sample_gen_next <= '1'; -- Reset @@ -3108,7 +3110,7 @@ begin -- Continue Search cur_sample_next <= next_sample; stage_next <= CHECK_LIFESPAN; - cnt_next <= 0; + cnt_next <= 2; -- GET NEXT SAMPLE end if; elsif (trigger_sample_gen = '1') then -- Continue @@ -3123,15 +3125,15 @@ begin case (cnt) is -- SKIP READ when 0 => - ready_in_rtps <= '1'; + ready_in_rtps(ind) <= '1'; -- Wait until last word from input - if (last_word_in_rtps = '1') then + if (last_word_in_rtps(ind) = '1') then cnt_next <= cnt + 1; end if; -- Return Code when 1 => - done_rtps <= '1'; - ret_rtps <= rtps_return_code_latch; + done_rtps(ind) <= '1'; + ret_rtps(ind) <= rtps_return_code_latch; -- DONE stage_next <= IDLE; @@ -3141,151 +3143,154 @@ begin when REMOVE_WRITER => -- Precondition: inst_data set (IMF_WRITER_BITMAP_FLAG, IMF_STATUS_FLAG, IMF_SAMPLE_CNT_FLAG) - -- Synthesis Guard - if (WITH_KEY) then - -- Memory Operation Guard - if (inst_op_done = '1') then - case (cnt) is - when 0 => - -- No More Instances - if (inst_data.addr = INSTANCE_MEMORY_MAX_ADDRESS) then - -- DONE - done_rtps <= '1'; - ret_rtps <= OK; - stage_next <= IDLE; + -- Memory Operation Guard + if (inst_op_done = '1') then + case (cnt) is + -- UPDATE INSTANCE + when 0 => + -- No More Instances + if (inst_data.addr = INSTANCE_MEMORY_MAX_ADDRESS) then + -- DONE + done_rtps(ind) <= '1'; + ret_rtps(ind) <= OK; + stage_next <= IDLE; + else + assert stable(clk, inst_data.i = ind and check_mask(inst_data.field_flags, IMF_WRITER_BITMAP_FLAG or IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG)) severity FAILURE; + + -- Convert Writer Bitmap to SLV + tmp_bitmap := from_writer_bitmap_array(inst_data.writer_bitmap); + + -- Remove Writer + tmp_bitmap(writer_id) := '0'; + + -- NOTE: writer_bitmap is not latched, since the memory process is latching it at the + -- same clock cycle. + -- Convert Back + inst_r.writer_bitmap <= to_writer_bitmap_array(tmp_bitmap); + + -- NOT_ALIVE_NO_WRITERS Transition + if (tmp_bitmap = (tmp_bitmap'reverse_range => '0') and inst_data.status_info(ISI_NOT_ALIVE_DISPOSED_FLAG) = '0') then + trigger_sample_gen_next <= '1'; + inst_r.status_info <= inst_data.status_info; + inst_r.status_info(ISI_NOT_ALIVE_NO_WRITERS_FLAG) <= '1'; + inst_r.status_info(ISI_GENERATE_SAMPLE_FLAG) <= '1'; + inst_op_start <= '1'; + inst_opcode <= UPDATE_INSTANCE; + inst_r.i <= ind; + inst_r.addr <= inst_data.addr; + inst_r.field_flags <= IMF_STATUS_FLAG or IMF_WRITER_BITMAP_FLAG; else - assert stable(clk, check_mask(inst_data.field_flags, IMF_WRITER_BITMAP_FLAG or IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG)) severity FAILURE; - - -- Convert Writer Bitmap to SLV - tmp_bitmap := from_writer_bitmap_array(inst_data.writer_bitmap); - - -- Remove Writer - tmp_bitmap(writer_id) := '0'; - - -- NOTE: writer_bitmap is not latched, since the memory process is latching it at the - -- same clock cycle. - -- Convert Back - inst_r.writer_bitmap <= to_writer_bitmap_array(tmp_bitmap); - - -- NOT_ALIVE_NO_WRITERS Transition - if (tmp_bitmap = (tmp_bitmap'reverse_range => '0') and inst_data.status_info(ISI_NOT_ALIVE_DISPOSED_FLAG) = '0') then - trigger_sample_gen_next <= '1'; - inst_r.status_info <= inst_data.status_info; - inst_r.status_info(ISI_NOT_ALIVE_NO_WRITERS_FLAG) <= '1'; - inst_r.status_info(ISI_GENERATE_SAMPLE_FLAG) <= '1'; - inst_op_start <= '1'; - inst_opcode <= UPDATE_INSTANCE; - inst_r.addr <= inst_data.addr; - inst_r.field_flags <= IMF_STATUS_FLAG or IMF_WRITER_BITMAP_FLAG; - else - inst_op_start <= '1'; - inst_opcode <= UPDATE_INSTANCE; - inst_r.addr <= inst_data.addr; - inst_r.field_flags <= IMF_WRITER_BITMAP_FLAG; - end if; - - -- Update Stale Instance Count - if (tmp_bitmap = (tmp_bitmap'reverse_range => '0') and inst_data.sample_cnt = 0) then - stale_inst_cnt_next <= stale_inst_cnt + 1; - end if; - - -- Continue - cnt_next <= 1; + inst_op_start <= '1'; + inst_opcode <= UPDATE_INSTANCE; + inst_r.i <= ind; + inst_r.addr <= inst_data.addr; + inst_r.field_flags <= IMF_WRITER_BITMAP_FLAG; end if; - when 1 => - inst_op_start <= '1'; - inst_opcode <= GET_NEXT_INSTANCE; - inst_r.addr <= inst_data.addr; - inst_r.field_flags <= IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_WRITER_BITMAP_FLAG; - stage_next <= REMOVE_WRITER; - cnt_next <= 0; - when 2 => - inst_op_start <= '1'; - inst_opcode <= GET_INSTANCE; - inst_r.addr <= inst_occupied_head; - inst_r.field_flags <= IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_WRITER_BITMAP_FLAG; - stage_next <= REMOVE_WRITER; - cnt_next <= 0; - when others => - null; - end case; - end if; + + -- Update Stale Instance Count + if (tmp_bitmap = (tmp_bitmap'reverse_range => '0') and inst_data.sample_cnt = 0) then + stale_inst_cnt_next(ind) <= stale_inst_cnt(ind) + 1; + end if; + + -- Continue + cnt_next <= 1; + end if; + -- GET NEXT INSTANCE + when 1 => + inst_op_start <= '1'; + inst_opcode <= GET_NEXT_INSTANCE; + inst_r.i <= ind; + inst_r.addr <= inst_data.addr; + inst_r.field_flags <= IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_WRITER_BITMAP_FLAG; + cnt_next <= 0; -- UPDATE INSTANCE + -- GET FIRST INSTANCE + when 2 => + inst_op_start <= '1'; + inst_opcode <= GET_INSTANCE; + inst_r.i <= ind; + inst_r.addr <= inst_occupied_head(ind); + inst_r.field_flags <= IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_WRITER_BITMAP_FLAG; + cnt_next <= 0; -- UPDATE INSTANCE + when others => + null; + end case; end if; when REMOVE_STALE_INSTANCE => -- Precondition: inst_data set (IMF_SAMPLE_CNT_FLAG, IMF_WRITER_BITMAP_FLAG) + assert (CONFIG_ARRAY_T(ind).WITH_KEY) severity FAILURE; - -- Synthesis Guard - if (WITH_KEY) then - -- Wait for Instance Data - if (inst_op_done = '1') then - case (cnt) is - -- Find and Remove First Stale Instance - when 0 => - -- Iterated through all Instances - if (inst_data.addr = INSTANCE_MEMORY_MAX_ADDRESS) then - -- NOTE: We should enter this state only if there is at least one stale Instance to be removed, so we should never enter this branch. - assert stable(clk, FALSE) severity FAILURE; - stage_next <= IDLE; - else - assert stable(clk, check_mask(inst_data.field_flags, IMF_SAMPLE_CNT_FLAG or IMF_WRITER_BITMAP_FLAG)) severity FAILURE; + -- Wait for Instance Data + if (inst_op_done = '1') then + case (cnt) is + -- Find and Remove First Stale Instance + when 0 => + -- Iterated through all Instances + if (inst_data.addr = INSTANCE_MEMORY_MAX_ADDRESS) then + -- NOTE: We should enter this state only if there is at least one stale Instance to be removed, so we should never enter this branch. + assert stable(clk, FALSE) severity FAILURE; + stage_next <= IDLE; + else + assert stable(clk, inst_data.i = ind and check_mask(inst_data.field_flags, IMF_SAMPLE_CNT_FLAG or IMF_WRITER_BITMAP_FLAG)) severity FAILURE; + + -- Found Stale Instance (No Samples and No Active Writers) + if (inst_data.sample_cnt = 0 and inst_data.writer_bitmap = ZERO_WRITER_BITMAP_ARRAY) then + -- Remove Stale Instance + inst_op_start <= '1'; + inst_opcode <= REMOVE_INSTANCE; + inst_r.i <= ind; + inst_r.addr <= inst_data.addr; + -- Update Stale Instance Count + stale_inst_cnt_next(ind) <= stale_inst_cnt(ind) - 1; + + cnt_next <= cnt + 1; - -- Found Stale Instance (No Samples and No Active Writers) - if (inst_data.sample_cnt = 0 and inst_data.writer_bitmap = ZERO_WRITER_BITMAP_ARRAY) then - -- Remove Stale Instance - inst_op_start <= '1'; - inst_opcode <= REMOVE_INSTANCE; - inst_r.addr <= inst_data.addr; - -- Update Stale Instance Count - stale_inst_cnt_next <= stale_inst_cnt - 1; - - cnt_next <= cnt + 1; - - else - -- Continue Search - inst_op_start <= '1'; - inst_opcode <= GET_NEXT_INSTANCE; - inst_r.addr <= inst_data.addr; - inst_r.field_flags <= IMF_SAMPLE_CNT_FLAG or IMF_WRITER_BITMAP_FLAG; - end if; - end if; - -- Insert New Instance - when 1 => - inst_op_start <= '1'; - inst_opcode <= INSERT_INSTANCE; - inst_r.key_hash <= key_hash; - inst_r.status_info <= (ISI_LIVELINESS_FLAG => '1', ISI_NOT_ALIVE_DISPOSED_FLAG => sample_status_info(SSI_DISPOSED_FLAG), others => '0'); - inst_r.sample_cnt <= to_unsigned(1, WORD_WIDTH); - if (TIME_BASED_FILTER_QOS /= DURATION_ZERO) then - inst_r.ignore_deadline <= time + TIME_BASED_FILTER_QOS; else - inst_r.ignore_deadline <= TIME_INVALID; + -- Continue Search + inst_op_start <= '1'; + inst_opcode <= GET_NEXT_INSTANCE; + inst_r.i <= ind; + inst_r.addr <= inst_data.addr; + inst_r.field_flags <= IMF_SAMPLE_CNT_FLAG or IMF_WRITER_BITMAP_FLAG; end if; - tmp_bitmap := (others => '0'); - tmp_bitmap(writer_id) := '1'; - inst_r.writer_bitmap <= to_writer_bitmap_array(tmp_bitmap); - - -- Latch Instance Pointer - cur_inst_next <= inst_empty_head; - - if (DESTINATION_ORDER_QOS = BY_SOURCE_TIMESTAMP_DESTINATION_ORDER_QOS and newest_sample /= SAMPLE_MEMORY_MAX_ADDRESS) then - stage_next <= FIND_POS; - next_sample_next <= SAMPLE_MEMORY_MAX_ADDRESS; - prev_sample_next <= newest_sample; - cur_sample_next <= newest_sample; - cnt_next <= 0; + end if; + -- Insert New Instance + when 1 => + inst_op_start <= '1'; + inst_opcode <= INSERT_INSTANCE; + inst_r.i <= ind; + inst_r.key_hash <= key_hash; + inst_r.status_info <= (ISI_LIVELINESS_FLAG => '1', ISI_NOT_ALIVE_DISPOSED_FLAG => sample_status_info(SSI_DISPOSED_FLAG), others => '0'); + inst_r.sample_cnt <= to_unsigned(1, WORD_WIDTH); + if (CONFIG_ARRAY_T(ind).TIME_BASED_FILTER_QOS /= DURATION_ZERO) then + inst_r.ignore_deadline <= time + CONFIG_ARRAY_T(ind).TIME_BASED_FILTER_QOS; + else + inst_r.ignore_deadline <= TIME_INVALID; + end if; + tmp_bitmap := (others => '0'); + tmp_bitmap(writer_id) := '1'; + inst_r.writer_bitmap <= to_writer_bitmap_array(tmp_bitmap); + + -- Latch Instance Pointer + cur_inst_next <= inst_empty_head(ind); + + if (CONFIG_ARRAY_T(ind).DESTINATION_ORDER_QOS = BY_SOURCE_TIMESTAMP_DESTINATION_ORDER_QOS and newest_sample(ind) /= SAMPLE_MEMORY_MAX_ADDRESS) then + stage_next <= FIND_POS; + next_sample_next <= SAMPLE_MEMORY_MAX_ADDRESS; + prev_sample_next <= newest_sample(ind); + cur_sample_next <= newest_sample(ind); + cnt_next <= 0; + else + if (has_data = '1') then + stage_next <= FINALIZE_PAYLOAD; + cnt_next <= 0; else - if (has_data = '1') then - stage_next <= FINALIZE_PAYLOAD; - cnt_next <= 0; - else - stage_next <= PRE_SAMPLE_FINALIZE; - cnt_next <= 0; - end if; + stage_next <= PRE_SAMPLE_FINALIZE; + cnt_next <= 0; end if; - when others => - null; - end case; - end if; + end if; + when others => + null; + end case; end if; when GET_NEXT_SAMPLE => -- Precondition: cur_sample set, cur_inst set, si_sample_rank_sig set @@ -3309,25 +3314,17 @@ begin -- Memory Control Flow Guard if (sample_ready_in = '1') then - -- Synthesis Guard - if (WITH_KEY) then - cnt_next <= cnt + 1; - else - cnt_next <= cnt + 2; -- Skip Next Step - end if; + cnt_next <= cnt + 1; end if; -- GET Instance Pointer when 2 => - -- Synthesis Guard - if (WITH_KEY) then - sample_valid_in <= '1'; - sample_addr <= cur_sample + SMF_INSTANCE_ADDR_OFFSET; - sample_read <= '1'; - - -- Memory Control Flow Guard - if (sample_ready_in = '1') then - cnt_next <= cnt + 1; - end if; + sample_valid_in <= '1'; + sample_addr <= cur_sample + SMF_INSTANCE_ADDR_OFFSET; + sample_read <= '1'; + + -- Memory Control Flow Guard + if (sample_ready_in = '1') then + cnt_next <= cnt + 1; end if; -- READ Next Sample when 3 => @@ -3374,101 +3371,80 @@ begin -- Sample Passes Checks if (tmp_bool) then - if (WITH_KEY) then - cnt_next <= cnt + 1; - else - -- First Instance Sample - -- NOTE: If sample rank is bigger than zero, we have already accepted the instance. - if (si_sample_rank_sig = 0) then - cnt_next <= cnt + 3; --Skip to Check Instance State - else - -- Select Sample - collection_cnt_next <= collection_cnt + 1; - sel_sample_next <= cur_sample; - -- Latch Next Sample (For resume purposes) - sample_p1_next <= next_sample; - si_sample_rank_sig_next <= si_sample_rank_sig - 1; - cnt_next <= cnt + 4; --Skip all Instance Related States - end if; - end if; + cnt_next <= cnt + 1; else -- Sample not in collection, Skip Sample - cnt_next <= 18; + cnt_next <= 18; -- EXIT STATE sample_abort_read <= '1'; end if; end if; -- READ Instance Pointer when 5 => - -- Synthesis Guard - if (WITH_KEY) then - sample_ready_out <= '1'; - - -- Memory Control Flow Guard - if (sample_valid_out = '1') then - -- Instance pre-selected - if (cur_inst /= INSTANCE_MEMORY_MAX_ADDRESS) then - -- Sample has different Instance - if (cur_inst /= resize(unsigned(sample_read_data),INSTANCE_MEMORY_ADDR_WIDTH)) then - -- Consecutive Instance Sample Order - if (not ORDERED_ACCESS or PRESENTATION_QOS = INSTANCE_PRESENTATION_QOS or single_instance = '1') then - -- Skip Sample - cnt_next <= 18; - sample_abort_read <= '1'; - -- Latch first skipped Sample - if (sample_p2 = SAMPLE_MEMORY_MAX_ADDRESS) then - sample_p2_next <= cur_sample; - end if; - else - -- Get Instance Data - next_inst_next <= resize(unsigned(sample_read_data),INSTANCE_MEMORY_ADDR_WIDTH); - cnt_next <= cnt + 1; + sample_ready_out <= '1'; + + -- Memory Control Flow Guard + if (sample_valid_out = '1') then + -- Instance pre-selected + if (cur_inst /= INSTANCE_MEMORY_MAX_ADDRESS) then + -- Sample has different Instance + if (cur_inst /= resize(unsigned(sample_read_data),INSTANCE_MEMORY_ADDR_WIDTH)) then + -- Consecutive Instance Sample Order + if (not CONFIG_ARRAY_T(ind).ORDERED_ACCESS or CONFIG_ARRAY_T(ind).PRESENTATION_QOS = INSTANCE_PRESENTATION_QOS or single_instance = '1') then + -- Skip Sample + cnt_next <= 18; -- EXIT STATE + sample_abort_read <= '1'; + -- Latch first skipped Sample + if (sample_p2 = SAMPLE_MEMORY_MAX_ADDRESS) then + sample_p2_next <= cur_sample; end if; else - -- Select Sample - collection_cnt_next <= collection_cnt + 1; - sel_sample_next <= cur_sample; - -- Latch Next Sample (For resume purposes) - sample_p1_next <= next_sample; - - -- First Instance Sample - -- NOTE: This state only enters with a sample rank of 0 and cur_inst set, when the - -- first sample of the instance has not yet been selected - if (si_sample_rank_sig = 0) then - -- Reset - collection_cnt_max_next <= collection_cnt + 1; - else - si_sample_rank_sig_next <= si_sample_rank_sig - 1; - end if; - - -- Skip Instance Operation - cnt_next <= cnt + 3; + -- Get Instance Data + next_inst_next <= resize(unsigned(sample_read_data),INSTANCE_MEMORY_ADDR_WIDTH); + cnt_next <= cnt + 1; end if; else - -- Get Instance Data - next_inst_next <= resize(unsigned(sample_read_data),INSTANCE_MEMORY_ADDR_WIDTH); - cnt_next <= cnt + 1; + -- Select Sample + collection_cnt_next <= collection_cnt + 1; + sel_sample_next <= cur_sample; + -- Latch Next Sample (For resume purposes) + sample_p1_next <= next_sample; + + -- First Instance Sample + -- NOTE: This state only enters with a sample rank of 0 and cur_inst set, when the + -- first sample of the instance has not yet been selected + if (si_sample_rank_sig = 0) then + -- Reset + collection_cnt_max_next <= collection_cnt + 1; + else + si_sample_rank_sig_next <= si_sample_rank_sig - 1; + end if; + + -- Skip Instance Operation + cnt_next <= cnt + 3; -- GET TIMESTAMP 1/2 end if; + else + -- Get Instance Data + next_inst_next <= resize(unsigned(sample_read_data),INSTANCE_MEMORY_ADDR_WIDTH); + cnt_next <= cnt + 1; end if; end if; -- Get Instance Data when 6 => - -- Synthesis Guard - if (WITH_KEY) then - -- Memory Operation Guard - if (inst_op_done = '1') then - inst_op_start <= '1'; - inst_opcode <= GET_INSTANCE; - inst_r.addr <= next_inst; - inst_r.field_flags <= IMF_STATUS_FLAG; - cnt_next <= cnt + 1; - end if; + -- Memory Operation Guard + if (inst_op_done = '1') then + inst_op_start <= '1'; + inst_opcode <= GET_INSTANCE; + inst_r.i <= ind; + inst_r.addr <= next_inst; + inst_r.field_flags <= IMF_STATUS_FLAG; + cnt_next <= cnt + 1; end if; -- Check Instance Data when 7 => -- Wait for Instance Data - if (not WITH_KEY or inst_op_done = '1') then - assert (not WITH_KEY or stable(clk, check_mask(inst_data.field_flags, IMF_STATUS_FLAG))) severity FAILURE; - assert (not WITH_KEY or next_inst = inst_data.addr) severity FAILURE; + if (inst_op_done = '1') then + assert (stable(clk, inst_data.i = ind and check_mask(inst_data.field_flags, IMF_STATUS_FLAG))) severity FAILURE; + assert (next_inst = inst_data.addr) severity FAILURE; -- DEFAULT tmp_bool := TRUE; @@ -3533,15 +3509,15 @@ begin -- Reset pre_calculated_next <= '0'; else - if (WITH_KEY) then + if (CONFIG_ARRAY_T(ind).WITH_KEY) then -- Skip Sample - cnt_next <= 18; + cnt_next <= 18; -- EXIT STATE sample_abort_read <= '1'; else -- Instance does not pass Checks - done_dds <= '1'; - return_code_dds <= RETCODE_NO_DATA; - stage_next <= IDLE; + done_dds(ind) <= '1'; + return_code_dds(ind) <= RETCODE_NO_DATA; + stage_next <= IDLE; end if; end if; end if; @@ -3685,8 +3661,8 @@ begin -- First Sample Selected if (collection_cnt = 1) then - done_dds <= '1'; - return_code_dds <= RETCODE_OK; + done_dds(ind) <= '1'; + return_code_dds(ind) <= RETCODE_OK; end if; else -- End of Samples @@ -3694,22 +3670,22 @@ begin -- Collection Empty if (collection_cnt = 0) then -- READ_NEXT_INSTANCE/TAKE_NEXT_INSTANCE Operation - if (WITH_KEY and dynamic_next_instance = '1') then + if (CONFIG_ARRAY_T(ind).WITH_KEY and dynamic_next_instance = '1') then -- NOTE: We selected a compatible instance, but the instance has no compatible samples. -- Find next compatible instance. stage_next <= FIND_NEXT_INSTANCE; cnt_next <= 1; -- GET NEXT INSTANCE else - done_dds <= '1'; - return_code_dds <= RETCODE_NO_DATA; - stage_next <= IDLE; + done_dds(ind) <= '1'; + return_code_dds(ind) <= RETCODE_NO_DATA; + stage_next <= IDLE; end if; else -- Mark End of Collection eoc_sig_next <= '1'; stage_next <= IDLE; -- Consecutive Instance Sample Order of multiple Instances - if ((not ORDERED_ACCESS or PRESENTATION_QOS = INSTANCE_PRESENTATION_QOS) and single_instance = '0') then + if ((not CONFIG_ARRAY_T(ind).ORDERED_ACCESS or CONFIG_ARRAY_T(ind).PRESENTATION_QOS = INSTANCE_PRESENTATION_QOS) and single_instance = '0') then -- Unmark Instances unmark_instances_flag_next <= '1'; end if; @@ -3717,7 +3693,7 @@ begin else -- Continue Searching cur_sample_next <= next_sample; - cnt_next <= 0; + cnt_next <= 0; -- GET NEXT SAMPLE end if; end if; when others => @@ -3745,25 +3721,17 @@ begin -- Memory Control Flow Guard if (sample_ready_in = '1') then - -- Synthesis Guard - if (WITH_KEY) then - cnt_next <= cnt + 1; - else - cnt_next <= cnt + 2; --Skip Next Step - end if; + cnt_next <= cnt + 1; end if; -- GET Instance Pointer when 2 => - -- Synthesis Guard - if (WITH_KEY) then - sample_valid_in <= '1'; - sample_addr <= cur_sample + SMF_INSTANCE_ADDR_OFFSET; - sample_read <= '1'; - - -- Memory Control Flow Guard - if (sample_ready_in = '1') then - cnt_next <= cnt + 1; - end if; + sample_valid_in <= '1'; + sample_addr <= cur_sample + SMF_INSTANCE_ADDR_OFFSET; + sample_read <= '1'; + + -- Memory Control Flow Guard + if (sample_ready_in = '1') then + cnt_next <= cnt + 1; end if; -- GET Disposed Generation Count when 3 => @@ -3821,47 +3789,38 @@ begin -- Sample Passes Checks if (tmp_bool) then - -- Synthesis Guard - if (WITH_KEY) then - cnt_next <= cnt + 1; - else - -- Count Sample (No need to check Instance) - collection_cnt_max_next <= collection_cnt_max + 1; - si_sample_rank_sig_next <= si_sample_rank_sig + 1; - cnt_next <= cnt + 2; --Skip Next Step - end if; + cnt_next <= cnt + 1; else -- Skip Sample - cnt_next <= 12; + cnt_next <= 12; -- EXIT STATE sample_abort_read <= '1'; end if; end if; -- READ Instance Pointer when 7 => - -- Synthesis Guard - if (WITH_KEY) then - sample_ready_out <= '1'; - - -- Memory Control Flow Guard - if (sample_valid_out = '1') then - -- Same Instance - if (resize(unsigned(sample_read_data),INSTANCE_MEMORY_ADDR_WIDTH) = cur_inst) then - -- Count Sample (No need to check Instance) - collection_cnt_max_next <= collection_cnt_max + 1; - si_sample_rank_sig_next <= si_sample_rank_sig + 1; - - cnt_next <= cnt + 1; + sample_ready_out <= '1'; + + -- Memory Control Flow Guard + if (sample_valid_out = '1') then + -- Same Instance + if (resize(unsigned(sample_read_data),INSTANCE_MEMORY_ADDR_WIDTH) = cur_inst) then + -- Count Sample (No need to check Instance) + collection_cnt_max_next <= collection_cnt_max + 1; + si_sample_rank_sig_next <= si_sample_rank_sig + 1; + + cnt_next <= cnt + 1; + else + assert stable(clk, CONFIG_ARRAY_T(ind).WITH_KEY) severity FAILURE; + + -- Consecutive Instance Sample Order + if (not CONFIG_ARRAY_T(ind).ORDERED_ACCESS or CONFIG_ARRAY_T(ind).PRESENTATION_QOS = INSTANCE_PRESENTATION_QOS or single_instance = '1') then + -- Skip Sample + cnt_next <= 12; -- EXIT STATE + sample_abort_read <= '1'; else - -- Consecutive Instance Sample Order - if (not ORDERED_ACCESS or PRESENTATION_QOS = INSTANCE_PRESENTATION_QOS or single_instance = '1') then - -- Skip Sample - cnt_next <= 12; - sample_abort_read <= '1'; - else - -- Check New Instance - cnt_next <= cnt + 3; - sample_abort_read <= '1'; - end if; + -- Check New Instance + cnt_next <= cnt + 3; -- GET INSTANCE DATA + sample_abort_read <= '1'; end if; end if; end if; @@ -3884,86 +3843,85 @@ begin -- Calculate highest collection generation rank collection_generation_rank_next <= collection_generation_rank + unsigned(sample_read_data); -- Skip Instance Check - cnt_next <= cnt + 3; + cnt_next <= cnt + 3; -- EXIT STATE end if; -- Get Instance Data when 10 => - -- Synthesis Guard - if (WITH_KEY) then - -- Memory Operation Guard - if (inst_op_done = '1') then - inst_op_start <= '1'; - inst_opcode <= GET_INSTANCE; - inst_r.addr <= next_inst; - inst_r.field_flags <= IMF_STATUS_FLAG; - cnt_next <= cnt + 1; - end if; + assert (CONFIG_ARRAY_T(ind).WITH_KEY) severity FAILURE; + + -- Memory Operation Guard + if (inst_op_done = '1') then + inst_op_start <= '1'; + inst_opcode <= GET_INSTANCE; + inst_r.i <= ind; + inst_r.addr <= next_inst; + inst_r.field_flags <= IMF_STATUS_FLAG; + cnt_next <= cnt + 1; end if; -- Check Instance Data when 11 => - -- Synthesis Guard - if (WITH_KEY) then - -- Wait for Instance Data - if (inst_op_done = '1') then - assert stable(clk, check_mask(inst_data.field_flags, IMF_STATUS_FLAG)) severity FAILURE; - assert (next_inst = inst_data.addr) severity FAILURE; - - -- DEFAULT - tmp_bool := TRUE; - - -- Check Instance State - case (instance_state) is - when ALIVE_INSTANCE_STATE => - if (inst_data.status_info(ISI_NOT_ALIVE_DISPOSED_FLAG) = '1' or inst_data.status_info(ISI_NOT_ALIVE_NO_WRITERS_FLAG) = '1') then - tmp_bool := FALSE; - end if; - when NOT_ALIVE_DISPOSED_INSTANCE_STATE => - if (inst_data.status_info(ISI_NOT_ALIVE_DISPOSED_FLAG) = '0') then - tmp_bool := FALSE; - end if; - when NOT_ALIVE_NO_WRITERS_INSTANCE_STATE => - if (inst_data.status_info(ISI_NOT_ALIVE_NO_WRITERS_FLAG) = '0') then - tmp_bool := FALSE; - end if; - when NOT_ALIVE_INSTANCE_STATE => - if (inst_data.status_info(ISI_NOT_ALIVE_DISPOSED_FLAG) = '0' and inst_data.status_info(ISI_NOT_ALIVE_NO_WRITERS_FLAG) = '0') then - tmp_bool := FALSE; - end if; - when ANY_INSTANCE_STATE => - null; - when others => + assert (CONFIG_ARRAY_T(ind).WITH_KEY) severity FAILURE; + + -- Wait for Instance Data + if (inst_op_done = '1') then + assert stable(clk, inst_data.i = ind and check_mask(inst_data.field_flags, IMF_STATUS_FLAG)) severity FAILURE; + assert (next_inst = inst_data.addr) severity FAILURE; + + -- DEFAULT + tmp_bool := TRUE; + + -- Check Instance State + case (instance_state) is + when ALIVE_INSTANCE_STATE => + if (inst_data.status_info(ISI_NOT_ALIVE_DISPOSED_FLAG) = '1' or inst_data.status_info(ISI_NOT_ALIVE_NO_WRITERS_FLAG) = '1') then tmp_bool := FALSE; - end case; - - -- Check View State - case (view_state) is - when NEW_VIEW_STATE => - if (inst_data.status_info(ISI_VIEW_FLAG) = '1') then - tmp_bool := FALSE; - end if; - when NOT_NEW_VIEW_STATE => - if (inst_data.status_info(ISI_VIEW_FLAG) = '0') then - tmp_bool := FALSE; - end if; - when ANY_VIEW_STATE => - null; - when others => + end if; + when NOT_ALIVE_DISPOSED_INSTANCE_STATE => + if (inst_data.status_info(ISI_NOT_ALIVE_DISPOSED_FLAG) = '0') then tmp_bool := FALSE; - end case; - - -- Check Instance Mark - if (inst_data.status_info(ISI_MARK_FLAG) = '1') then - -- Skip Marked Instance + end if; + when NOT_ALIVE_NO_WRITERS_INSTANCE_STATE => + if (inst_data.status_info(ISI_NOT_ALIVE_NO_WRITERS_FLAG) = '0') then + tmp_bool := FALSE; + end if; + when NOT_ALIVE_INSTANCE_STATE => + if (inst_data.status_info(ISI_NOT_ALIVE_DISPOSED_FLAG) = '0' and inst_data.status_info(ISI_NOT_ALIVE_NO_WRITERS_FLAG) = '0') then + tmp_bool := FALSE; + end if; + when ANY_INSTANCE_STATE => + null; + when others => tmp_bool := FALSE; - end if; - - -- Instance passes Checks - if (tmp_bool) then - -- Count Sample - collection_cnt_max_next <= collection_cnt_max + 1; - end if; - cnt_next <= cnt + 1; + end case; + + -- Check View State + case (view_state) is + when NEW_VIEW_STATE => + if (inst_data.status_info(ISI_VIEW_FLAG) = '1') then + tmp_bool := FALSE; + end if; + when NOT_NEW_VIEW_STATE => + if (inst_data.status_info(ISI_VIEW_FLAG) = '0') then + tmp_bool := FALSE; + end if; + when ANY_VIEW_STATE => + null; + when others => + tmp_bool := FALSE; + end case; + + -- Check Instance Mark + if (inst_data.status_info(ISI_MARK_FLAG) = '1') then + -- Skip Marked Instance + tmp_bool := FALSE; end if; + + -- Instance passes Checks + if (tmp_bool) then + -- Count Sample + collection_cnt_max_next <= collection_cnt_max + 1; + end if; + cnt_next <= cnt + 1; end if; -- Exit State when 12 => @@ -3975,7 +3933,7 @@ begin else -- Continue with next Sample cur_sample_next <= next_sample; - cnt_next <= 0; + cnt_next <= 0; -- GET NEXT SAMPLE end if; when others => null; @@ -3987,9 +3945,9 @@ begin -- Finalize Sample Info Data when 0 => -- Wait for Instance Data - if (not WITH_KEY or inst_op_done = '1') then + if (inst_op_done = '1') then -- Instance Data valid - if (not WITH_KEY or (inst_data.addr = cur_inst and check_mask(inst_data.field_flags,IMF_STATUS_FLAG or IMF_KEY_HASH_FLAG or IMF_DISPOSED_CNT_FLAG or IMF_NO_WRITERS_CNT_FLAG))) then + if (inst_data.addr = cur_inst and inst_data.i = ind and check_mask(inst_data.field_flags,IMF_STATUS_FLAG or IMF_KEY_HASH_FLAG or IMF_DISPOSED_CNT_FLAG or IMF_NO_WRITERS_CNT_FLAG)) then -- Sample Info View State if (inst_data.status_info(ISI_VIEW_FLAG) = '0') then @@ -4030,6 +3988,7 @@ begin -- Get Instance Data inst_op_start <= '1'; inst_opcode <= GET_INSTANCE; + inst_r.i <= ind; inst_r.addr <= cur_inst; inst_r.field_flags <= IMF_KEY_HASH_FLAG or IMF_STATUS_FLAG or IMF_DISPOSED_CNT_FLAG or IMF_NO_WRITERS_CNT_FLAG; end if; @@ -4037,20 +3996,20 @@ begin -- Present Data when 1 => -- Synthesis Guard - if (DESTINATION_ORDER_QOS = BY_SOURCE_TIMESTAMP_DESTINATION_ORDER_QOS) then + if (CONFIG_ARRAY_T(ind).DESTINATION_ORDER_QOS = BY_SOURCE_TIMESTAMP_DESTINATION_ORDER_QOS) then -- Update Last Read Timestamp - if (si_source_timestamp_sig > last_read_ts) then - last_read_ts_next <= si_source_timestamp_sig; + if (si_source_timestamp_sig > last_read_ts(ind)) then + last_read_ts_next(ind) <= si_source_timestamp_sig; end if; end if; -- Reset Data Available Status - status_sig_next <= status_sig and (not DATA_AVAILABLE_STATUS); + status_sig_next(ind) <= status_sig(ind) and (not DATA_AVAILABLE_STATUS); -- Wait on User - if (sample_info_ack = '1') then + if (sample_info_ack(ind) = '1') then -- Sample Data Request - if (get_data_dds = '1') then + if (get_data_dds(ind) = '1') then stage_next <= GET_PAYLOAD; cnt_next <= 0; else @@ -4062,40 +4021,31 @@ begin -- Post-Present Data when 2 => -- Memory Operation Guard - if (not WITH_KEY or inst_op_done = '1') then - assert (not WITH_KEY or inst_data.addr /= INSTANCE_MEMORY_MAX_ADDRESS) severity FAILURE; - assert (not WITH_KEY or stable(clk, check_mask(inst_data.field_flags, IMF_STATUS_FLAG))) severity FAILURE; + if (inst_op_done = '1') then + assert (inst_data.addr /= INSTANCE_MEMORY_MAX_ADDRESS) severity FAILURE; + assert (stable(clk, inst_data.i = ind and check_mask(inst_data.field_flags, IMF_STATUS_FLAG))) severity FAILURE; -- NOTE: If we have a presentation of consecutive same instance samples of multiple instances, we have to -- mark the instances we have already handled, in order to prevent the GET_NEXT_SAMPLE state to -- re-process them. -- Last Sample of Instance in Collection if (si_sample_rank_sig = 0) then - -- Synthesis Guard - if (WITH_KEY) then - - inst_op_start <= '1'; - inst_opcode <= UPDATE_INSTANCE; - inst_r.addr <= inst_data.addr; - inst_r.field_flags <= IMF_STATUS_FLAG; - inst_r.status_info <= inst_data.status_info; - - -- Consecutive Instance Sample Order of multiple Instances - if ((not ORDERED_ACCESS or PRESENTATION_QOS = INSTANCE_PRESENTATION_QOS) and single_instance = '0') then - -- Mark Instance - inst_r.status_info(ISI_MARK_FLAG) <= '1'; - end if; - - -- Instance is NOT_VIEWED and sample is from last generation of Instance - if (inst_data.status_info(ISI_VIEW_FLAG) = '0' and si_absolute_generation_rank_sig = 0) then - -- Mark Instance as VIEWED - inst_r.status_info(ISI_VIEW_FLAG) <= '1'; - end if; - else - -- Instance is NOT_VIEWED and sample is from last generation of Instance - if (inst_data.status_info(ISI_VIEW_FLAG) = '0' and si_absolute_generation_rank_sig = 0) then - -- Mark Instance as VIEWED - inst_data_next2.status_info(ISI_VIEW_FLAG) <= '1'; - end if; + inst_op_start <= '1'; + inst_opcode <= UPDATE_INSTANCE; + inst_r.i <= ind; + inst_r.addr <= inst_data.addr; + inst_r.field_flags <= IMF_STATUS_FLAG; + inst_r.status_info <= inst_data.status_info; + + -- Consecutive Instance Sample Order of multiple Instances + if ((not CONFIG_ARRAY_T(ind).ORDERED_ACCESS or CONFIG_ARRAY_T(ind).PRESENTATION_QOS = INSTANCE_PRESENTATION_QOS) and single_instance = '0') then + -- Mark Instance + inst_r.status_info(ISI_MARK_FLAG) <= '1'; + end if; + + -- Instance is NOT_VIEWED and sample is from last generation of Instance + if (inst_data.status_info(ISI_VIEW_FLAG) = '0' and si_absolute_generation_rank_sig = 0) then + -- Mark Instance as VIEWED + inst_r.status_info(ISI_VIEW_FLAG) <= '1'; end if; end if; @@ -4104,7 +4054,7 @@ begin -- Mark End of Collection eoc_sig_next <= '1'; -- Consecutive Instance Sample Order of multiple Instances - if ((not ORDERED_ACCESS or PRESENTATION_QOS = INSTANCE_PRESENTATION_QOS) and single_instance = '0') then + if ((not CONFIG_ARRAY_T(ind).ORDERED_ACCESS or CONFIG_ARRAY_T(ind).PRESENTATION_QOS = INSTANCE_PRESENTATION_QOS) and single_instance = '0') then -- Unmark Instances unmark_instances_flag_next <= '1'; end if; @@ -4191,13 +4141,13 @@ begin cnt_next <= cnt + 1; else cnt_next <= cnt + 3; - long_latch_next <= std_logic_vector(to_unsigned(PAYLOAD_FRAME_SIZE-1,CDR_LONG_WIDTH)); + long_latch_next <= std_logic_vector(to_unsigned(PAYLOAD_FRAME_SIZE(ind)-1,CDR_LONG_WIDTH)); end if; end if; -- GET Payload Offset when 2 => payload_valid_in <= '1'; - payload_addr <= cur_payload + PAYLOAD_FRAME_SIZE-1; + payload_addr <= cur_payload + PAYLOAD_FRAME_SIZE(ind)-1; payload_read <= '1'; -- Memory Flow Control Guard @@ -4246,16 +4196,16 @@ begin if (cnt3 /= 0) then -- Memory Flow Control Guard if (payload_valid_out = '1') then - valid_out_dds <= '1'; - data_out_dds <= payload_read_data; + valid_out_dds(ind) <= '1'; + data_out_dds(ind) <= payload_read_data; -- End of Payload if (cnt3 = 1 and cnt = 5) then - last_word_out_dds <= '1'; + last_word_out_dds(ind) <= '1'; end if; -- DDS Read - if (ready_out_dds = '1') then + if (ready_out_dds(ind) = '1') then payload_ready_out <= '1'; -- NOTE: We are using the tmp_bool variable to signal if there is an increment -- on the same clock cycle. @@ -4277,91 +4227,171 @@ begin end if; end if; when FIND_NEXT_INSTANCE => - -- Synthesis Guard - if (WITH_KEY) then - -- Wait for Instance Data - if (inst_op_done = '1') then - case (cnt) is - -- GET FIRST INSTANCE - when 0 => - -- NOTE: The Generation Counters are not used directly in this state, but will be needed by the FINALIZE_SAMPLE_INFO state. - inst_op_start <= '1'; - inst_opcode <= GET_INSTANCE; - inst_r.addr <= inst_occupied_head; - inst_r.field_flags <= IMF_STATUS_FLAG or IMF_KEY_HASH_FLAG; - cnt_next <= 2; - -- GET NEXT INSTANCE - when 1 => - -- NOTE: The Generation Counters are not used directly in this state, but will be needed by the FINALIZE_SAMPLE_INFO state. - inst_op_start <= '1'; - inst_opcode <= GET_NEXT_INSTANCE; - inst_r.addr <= inst_data.addr; - inst_r.field_flags <= IMF_STATUS_FLAG or IMF_KEY_HASH_FLAG; - cnt_next <= 2; - -- EXIT CONDITION - when 2 => - -- No More Instances - if (inst_data.addr = INSTANCE_MEMORY_MAX_ADDRESS) then - -- DONE - done_dds <= '1'; - return_code_dds <= RETCODE_NO_DATA; - stage_next <= IDLE; - else - -- Check Instance - cnt_next <= cnt + 1; - end if; - -- KEY HASH 1/4 - when 3 => - assert (inst_data.addr /= INSTANCE_MEMORY_MAX_ADDRESS) severity FAILURE; - assert stable(clk, check_mask(inst_data.field_flags, IMF_KEY_HASH_FLAG)) severity FAILURE; - - if (unsigned(inst_data.key_hash(0)) > unsigned(key_hash(0))) then - cnt_next <= 7; -- INSTANCE STATUS CHECK - elsif (unsigned(inst_data.key_hash(0)) = unsigned(key_hash(0))) then - -- Continue Check - cnt_next <= cnt + 1; - else -- LESS THAN - cnt_next <= 1; -- GET NEXT INSTANCE - end if; - -- KEY HASH 2/4 - when 4 => - assert (inst_data.addr /= INSTANCE_MEMORY_MAX_ADDRESS) severity FAILURE; - assert stable(clk, check_mask(inst_data.field_flags, IMF_KEY_HASH_FLAG)) severity FAILURE; - - if (unsigned(inst_data.key_hash(1)) > unsigned(key_hash(1))) then - cnt_next <= 7; -- INSTANCE STATUS CHECK - elsif (unsigned(inst_data.key_hash(1)) = unsigned(key_hash(1))) then - -- Continue Check - cnt_next <= cnt + 1; - else -- LESS THAN - cnt_next <= 1; -- GET NEXT INSTANCE - end if; - -- KEY HASH 3/4 - when 5 => - assert (inst_data.addr /= INSTANCE_MEMORY_MAX_ADDRESS) severity FAILURE; - assert stable(clk, check_mask(inst_data.field_flags, IMF_KEY_HASH_FLAG)) severity FAILURE; - - if (unsigned(inst_data.key_hash(2)) > unsigned(key_hash(2))) then - cnt_next <= 7; -- INSTANCE STATUS CHECK - elsif (unsigned(inst_data.key_hash(2)) = unsigned(key_hash(2))) then - -- Continue Check - cnt_next <= cnt + 1; - else -- LESS THAN - cnt_next <= 1; -- GET NEXT INSTANCE - end if; - -- KEY HASH 4/4 - when 6 => - assert stable(clk, check_mask(inst_data.field_flags, IMF_KEY_HASH_FLAG)) severity FAILURE; - - if (unsigned(inst_data.key_hash(3)) > unsigned(key_hash(3))) then - cnt_next <= 7; -- INSTANCE STATUS CHECK - else -- LESS THAN EQUAL - cnt_next <= 1; -- GET NEXT INSTANCE - end if; - -- INSTANCE STATUS CHECK - when 7 => - assert (inst_data.addr /= INSTANCE_MEMORY_MAX_ADDRESS) severity FAILURE; - assert stable(clk, check_mask(inst_data.field_flags, IMF_STATUS_FLAG)) severity FAILURE; + assert (CONFIG_ARRAY_T(ind).WITH_KEY) severity FAILURE; + + -- Wait for Instance Data + if (inst_op_done = '1') then + case (cnt) is + -- GET FIRST INSTANCE + when 0 => + -- NOTE: The Generation Counters are not used directly in this state, but will be needed by the FINALIZE_SAMPLE_INFO state. + inst_op_start <= '1'; + inst_opcode <= GET_INSTANCE; + inst_r.i <= ind; + inst_r.addr <= inst_occupied_head(ind); + inst_r.field_flags <= IMF_STATUS_FLAG or IMF_KEY_HASH_FLAG; + cnt_next <= 2; -- EXIT CONDITION + -- GET NEXT INSTANCE + when 1 => + -- NOTE: The Generation Counters are not used directly in this state, but will be needed by the FINALIZE_SAMPLE_INFO state. + inst_op_start <= '1'; + inst_opcode <= GET_NEXT_INSTANCE; + inst_r.i <= ind; + inst_r.addr <= inst_data.addr; + inst_r.field_flags <= IMF_STATUS_FLAG or IMF_KEY_HASH_FLAG; + cnt_next <= 2; -- EXIT CONDITION + -- EXIT CONDITION + when 2 => + -- No More Instances + if (inst_data.addr = INSTANCE_MEMORY_MAX_ADDRESS) then + -- DONE + done_dds(ind) <= '1'; + return_code_dds(ind) <= RETCODE_NO_DATA; + stage_next <= IDLE; + else + -- Check Instance + cnt_next <= cnt + 1; + end if; + -- KEY HASH 1/4 + when 3 => + assert (inst_data.addr /= INSTANCE_MEMORY_MAX_ADDRESS) severity FAILURE; + assert stable(clk, inst_data.i = ind and check_mask(inst_data.field_flags, IMF_KEY_HASH_FLAG)) severity FAILURE; + + if (unsigned(inst_data.key_hash(0)) > unsigned(key_hash(0))) then + cnt_next <= 7; -- INSTANCE STATUS CHECK + elsif (unsigned(inst_data.key_hash(0)) = unsigned(key_hash(0))) then + -- Continue Check + cnt_next <= cnt + 1; + else -- LESS THAN + cnt_next <= 1; -- GET NEXT INSTANCE + end if; + -- KEY HASH 2/4 + when 4 => + assert (inst_data.addr /= INSTANCE_MEMORY_MAX_ADDRESS) severity FAILURE; + assert stable(clk, inst_data.i = ind and check_mask(inst_data.field_flags, IMF_KEY_HASH_FLAG)) severity FAILURE; + + if (unsigned(inst_data.key_hash(1)) > unsigned(key_hash(1))) then + cnt_next <= 7; -- INSTANCE STATUS CHECK + elsif (unsigned(inst_data.key_hash(1)) = unsigned(key_hash(1))) then + -- Continue Check + cnt_next <= cnt + 1; + else -- LESS THAN + cnt_next <= 1; -- GET NEXT INSTANCE + end if; + -- KEY HASH 3/4 + when 5 => + assert (inst_data.addr /= INSTANCE_MEMORY_MAX_ADDRESS) severity FAILURE; + assert stable(clk, inst_data.i = ind and check_mask(inst_data.field_flags, IMF_KEY_HASH_FLAG)) severity FAILURE; + + if (unsigned(inst_data.key_hash(2)) > unsigned(key_hash(2))) then + cnt_next <= 7; -- INSTANCE STATUS CHECK + elsif (unsigned(inst_data.key_hash(2)) = unsigned(key_hash(2))) then + -- Continue Check + cnt_next <= cnt + 1; + else -- LESS THAN + cnt_next <= 1; -- GET NEXT INSTANCE + end if; + -- KEY HASH 4/4 + when 6 => + assert stable(clk, inst_data.i = ind and check_mask(inst_data.field_flags, IMF_KEY_HASH_FLAG)) severity FAILURE; + + if (unsigned(inst_data.key_hash(3)) > unsigned(key_hash(3))) then + cnt_next <= 7; -- INSTANCE STATUS CHECK + else -- LESS THAN EQUAL + cnt_next <= 1; -- GET NEXT INSTANCE + end if; + -- INSTANCE STATUS CHECK + when 7 => + assert (inst_data.addr /= INSTANCE_MEMORY_MAX_ADDRESS) severity FAILURE; + assert stable(clk, inst_data.i = ind and check_mask(inst_data.field_flags, IMF_STATUS_FLAG)) severity FAILURE; + + -- DEFAULT + tmp_bool := TRUE; + + -- Check Instance State + case (instance_state) is + when ALIVE_INSTANCE_STATE => + if (inst_data.status_info(ISI_NOT_ALIVE_DISPOSED_FLAG) = '1' or inst_data.status_info(ISI_NOT_ALIVE_NO_WRITERS_FLAG) = '1') then + tmp_bool := FALSE; + end if; + when NOT_ALIVE_DISPOSED_INSTANCE_STATE => + if (inst_data.status_info(ISI_NOT_ALIVE_DISPOSED_FLAG) = '0') then + tmp_bool := FALSE; + end if; + when NOT_ALIVE_NO_WRITERS_INSTANCE_STATE => + if (inst_data.status_info(ISI_NOT_ALIVE_NO_WRITERS_FLAG) = '0') then + tmp_bool := FALSE; + end if; + when NOT_ALIVE_INSTANCE_STATE => + if (inst_data.status_info(ISI_NOT_ALIVE_DISPOSED_FLAG) = '0' and inst_data.status_info(ISI_NOT_ALIVE_NO_WRITERS_FLAG) = '0') then + tmp_bool := FALSE; + end if; + when ANY_INSTANCE_STATE => + null; + when others => + tmp_bool := FALSE; + end case; + + -- Check View State + case (view_state) is + when NEW_VIEW_STATE => + if (inst_data.status_info(ISI_VIEW_FLAG) = '1') then + tmp_bool := FALSE; + end if; + when NOT_NEW_VIEW_STATE => + if (inst_data.status_info(ISI_VIEW_FLAG) = '0') then + tmp_bool := FALSE; + end if; + when ANY_VIEW_STATE => + null; + when others => + tmp_bool := FALSE; + end case; + + -- Instance Passes Checks + if (tmp_bool) then + cur_inst_next <= inst_data.addr; + stage_next <= GET_NEXT_SAMPLE; + cnt_next <= 0; + -- Reset + sel_sample_next <= SAMPLE_MEMORY_MAX_ADDRESS; + sample_p1_next <= SAMPLE_MEMORY_MAX_ADDRESS; + sample_p2_next <= SAMPLE_MEMORY_MAX_ADDRESS; + else + cnt_next <= 1; -- GET NEXT INSTANCE + end if; + when others => + null; + end case; + end if; + when CHECK_INSTANCE => + assert (CONFIG_ARRAY_T(ind).WITH_KEY) severity FAILURE; + + -- Wait for Instance Data + if (inst_op_done = '1') then + case (cnt) is + when 0 => + -- NOTE: The Generation Counters are not used directly in this state, but will be needed by the FINALIZE_SAMPLE_INFO state. + inst_op_start <= '1'; + inst_opcode <= SEARCH_INSTANCE; + inst_r.i <= ind; + inst_r.key_hash <= key_hash; + inst_r.field_flags <= IMF_STATUS_FLAG; + cnt_next <= cnt + 1; + when 1 => + -- Instance Found + if (inst_data.addr /= INSTANCE_MEMORY_MAX_ADDRESS) then + assert stable(clk, inst_data.i = ind and check_mask(inst_data.field_flags, IMF_STATUS_FLAG)) severity FAILURE; -- DEFAULT tmp_bool := TRUE; @@ -4408,112 +4438,56 @@ begin -- Instance Passes Checks if (tmp_bool) then + -- Get Instance Samples cur_inst_next <= inst_data.addr; stage_next <= GET_NEXT_SAMPLE; - cnt_next <= 0; - -- Reset - sel_sample_next <= SAMPLE_MEMORY_MAX_ADDRESS; - sample_p1_next <= SAMPLE_MEMORY_MAX_ADDRESS; - sample_p2_next <= SAMPLE_MEMORY_MAX_ADDRESS; + cnt_next <= 0; else - cnt_next <= 1; -- GET NEXT INSTANCE - end if; - when others => - null; - end case; - end if; - end if; - when CHECK_INSTANCE => - -- Synthesis Guard - if (WITH_KEY) then - -- Wait for Instance Data - if (inst_op_done = '1') then - case (cnt) is - when 0 => - -- NOTE: The Generation Counters are not used directly in this state, but will be needed by the FINALIZE_SAMPLE_INFO state. - inst_op_start <= '1'; - inst_opcode <= SEARCH_INSTANCE; - inst_r.key_hash <= key_hash; - inst_r.field_flags <= IMF_STATUS_FLAG; - cnt_next <= cnt + 1; - when 1 => - -- Instance Found - if (inst_data.addr /= INSTANCE_MEMORY_MAX_ADDRESS) then - assert stable(clk, check_mask(inst_data.field_flags, IMF_STATUS_FLAG)) severity FAILURE; - - -- DEFAULT - tmp_bool := TRUE; - - -- Check Instance State - case (instance_state) is - when ALIVE_INSTANCE_STATE => - if (inst_data.status_info(ISI_NOT_ALIVE_DISPOSED_FLAG) = '1' or inst_data.status_info(ISI_NOT_ALIVE_NO_WRITERS_FLAG) = '1') then - tmp_bool := FALSE; - end if; - when NOT_ALIVE_DISPOSED_INSTANCE_STATE => - if (inst_data.status_info(ISI_NOT_ALIVE_DISPOSED_FLAG) = '0') then - tmp_bool := FALSE; - end if; - when NOT_ALIVE_NO_WRITERS_INSTANCE_STATE => - if (inst_data.status_info(ISI_NOT_ALIVE_NO_WRITERS_FLAG) = '0') then - tmp_bool := FALSE; - end if; - when NOT_ALIVE_INSTANCE_STATE => - if (inst_data.status_info(ISI_NOT_ALIVE_DISPOSED_FLAG) = '0' and inst_data.status_info(ISI_NOT_ALIVE_NO_WRITERS_FLAG) = '0') then - tmp_bool := FALSE; - end if; - when ANY_INSTANCE_STATE => - null; - when others => - tmp_bool := FALSE; - end case; - - -- Check View State - case (view_state) is - when NEW_VIEW_STATE => - if (inst_data.status_info(ISI_VIEW_FLAG) = '1') then - tmp_bool := FALSE; - end if; - when NOT_NEW_VIEW_STATE => - if (inst_data.status_info(ISI_VIEW_FLAG) = '0') then - tmp_bool := FALSE; - end if; - when ANY_VIEW_STATE => - null; - when others => - tmp_bool := FALSE; - end case; - - -- Instance Passes Checks - if (tmp_bool) then - -- Get Instance Samples - cur_inst_next <= inst_data.addr; - stage_next <= GET_NEXT_SAMPLE; - cnt_next <= 0; - else - -- DONE - done_dds <= '1'; - return_code_dds <= RETCODE_NO_DATA; - stage_next <= IDLE; - end if; - else - -- Given Instance does not exist -- DONE - done_dds <= '1'; - return_code_dds <= RETCODE_BAD_PARAMETER; - stage_next <= IDLE; + done_dds(ind) <= '1'; + return_code_dds(ind) <= RETCODE_NO_DATA; + stage_next <= IDLE; end if; - when others => - null; - end case; - end if; + else + -- Given Instance does not exist + -- DONE + done_dds(ind) <= '1'; + return_code_dds(ind) <= RETCODE_BAD_PARAMETER; + stage_next <= IDLE; + end if; + when others => + null; + end case; end if; when CHECK_LIFESPAN => -- Precondition: cur_sample set, case (cnt) is - -- GET Next Sample + -- GET NEXT WRITER when 0 => + if (ind = NUM_READERS-1) then + -- Reset + is_lifespan_check_next <= '0'; + + -- DONE + stage_next <= IDLE; + else + -- Next Writer + ind_next <= ind + 1; + cnt_next <= cnt + 1; + end if; + -- CHECK LIFESPAN + when 1 => + -- Samples Available + if (oldest_sample(ind) /= SAMPLE_MEMORY_MAX_ADDRESS) then + cur_sample_next <= oldest_sample(ind); + cnt_next <= cnt + 1; + else + -- Continue + cnt_next <= 0; -- GET NEXT WRITER + end if; + -- GET NEXT Sample + when 2 => sample_valid_in <= '1'; sample_addr <= cur_sample + SMF_NEXT_ADDR_OFFSET; sample_read <= '1'; @@ -4523,7 +4497,7 @@ begin cnt_next <= cnt + 1; end if; -- GET Lifespan 1/2 - when 1 => + when 3 => sample_valid_in <= '1'; sample_addr <= cur_sample + SMF_LIFESPAN_DEADLINE_OFFSET; sample_read <= '1'; @@ -4533,34 +4507,27 @@ begin cnt_next <= cnt + 1; end if; -- GET Lifespan 2/2 - when 2 => + when 4 => sample_valid_in <= '1'; sample_addr <= cur_sample + SMF_LIFESPAN_DEADLINE_OFFSET + 1; sample_read <= '1'; -- Memory Control Flow Guard if (sample_ready_in = '1') then - if (WITH_KEY) then - cnt_next <= cnt + 1; - else - cnt_next <= cnt + 2; --Skip Next Step - end if; + cnt_next <= cnt + 1; end if; -- GET Instance Pointer - when 3 => - -- Synthesis Guard - if (WITH_KEY) then - sample_valid_in <= '1'; - sample_addr <= cur_sample + SMF_INSTANCE_ADDR_OFFSET; - sample_read <= '1'; - - -- Memory Control Flow Guard - if (sample_ready_in = '1') then - cnt_next <= cnt + 1; - end if; + when 5 => + sample_valid_in <= '1'; + sample_addr <= cur_sample + SMF_INSTANCE_ADDR_OFFSET; + sample_read <= '1'; + + -- Memory Control Flow Guard + if (sample_ready_in = '1') then + cnt_next <= cnt + 1; end if; -- READ Next Sample - when 4 => + when 6 => sample_ready_out <= '1'; -- Memory Control Flow Guard @@ -4569,7 +4536,7 @@ begin cnt_next <= cnt + 1; end if; -- READ Lifespan 1/2 - when 5 => + when 7 => sample_ready_out <= '1'; -- Memory Control Flow Guard @@ -4578,7 +4545,7 @@ begin cnt_next <= cnt + 1; end if; -- READ Lifespan 2/2 - when 6 => + when 8 => sample_ready_out <= '1'; -- Memory Control Flow Guard @@ -4587,13 +4554,7 @@ begin -- Sample Lifespan Expired if (tmp_dw /= TIME_INVALID and time >= tmp_dw) then - if (WITH_KEY) then - cnt_next <= cnt + 1; - else - -- Remove Sample - stage_next <= REMOVE_SAMPLE; - cnt_next <= 0; - end if; + cnt_next <= cnt + 1; else sample_abort_read <= '1'; @@ -4604,225 +4565,222 @@ begin -- Reached End of Samples if (next_sample = SAMPLE_MEMORY_MAX_ADDRESS) then - -- DONE - stage_next <= IDLE; + -- Continue + cnt_next <= 0; -- GET NEXT WRITER else -- Continue Search cur_sample_next <= next_sample; - cnt_next <= 0; + cnt_next <= 2; -- GET NEXT SAMPLE end if; end if; end if; -- READ Instance Pointer - when 7 => - -- Synthesis Guard - if (WITH_KEY) then - -- Memory Operation Guard - if (inst_op_done = '1') then - sample_ready_out <= '1'; + when 9 => + -- Memory Operation Guard + if (inst_op_done = '1') then + sample_ready_out <= '1'; + + -- Memory Control Flow Guard + if (sample_valid_out = '1') then + -- Fetch Instance Data + inst_op_start <= '1'; + inst_opcode <= GET_INSTANCE; + inst_r.i <= ind; + inst_r.addr <= resize(unsigned(sample_read_data),INSTANCE_MEMORY_ADDR_WIDTH); + inst_r.field_flags <= IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_WRITER_BITMAP_FLAG; - -- Memory Control Flow Guard - if (sample_valid_out = '1') then - -- Fetch Instance Data - inst_op_start <= '1'; - inst_opcode <= GET_INSTANCE; - inst_r.addr <= resize(unsigned(sample_read_data),INSTANCE_MEMORY_ADDR_WIDTH); - inst_r.field_flags <= IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_WRITER_BITMAP_FLAG; - - -- Remove Sample - stage_next <= REMOVE_SAMPLE; - cnt_next <= 0; - end if; + -- Remove Sample + stage_next <= REMOVE_SAMPLE; + cnt_next <= 0; end if; end if; when others => null; end case; when PROCESS_PENDING_SAMPLE_GENERATION => - -- Synthesis Guard - if (WITH_KEY) then - -- Wait for Instance Data - if (inst_op_done = '1') then - case (cnt) is - when 0 => - inst_op_start <= '1'; - inst_opcode <= GET_INSTANCE; - inst_r.addr <= inst_occupied_head; - inst_r.field_flags <= IMF_STATUS_FLAG; - cnt_next <= cnt + 2; - when 1 => - -- Continue - inst_op_start <= '1'; - inst_opcode <= GET_NEXT_INSTANCE; - inst_r.addr <= inst_data.addr; - inst_r.field_flags <= IMF_STATUS_FLAG; - cnt_next <= cnt + 1; - when 2 => - -- Instance Found - if (inst_data.addr /= INSTANCE_MEMORY_MAX_ADDRESS) then - assert stable(clk, check_mask(inst_data.field_flags, IMF_STATUS_FLAG)) severity FAILURE; - - -- Sample needs to be Generated - if (inst_data.status_info(ISI_GENERATE_SAMPLE_FLAG) = '1') then - -- GET Required Instance Data - inst_op_start <= '1'; - inst_opcode <= GET_INSTANCE; - inst_r.addr <= inst_data.addr; - inst_r.field_flags <= IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_DISPOSED_CNT_FLAG or IMF_NO_WRITERS_CNT_FLAG; - cnt_next <= cnt + 1; - else - -- Continue - inst_op_start <= '1'; - inst_opcode <= GET_NEXT_INSTANCE; - inst_r.addr <= inst_data.addr; - inst_r.field_flags <= IMF_STATUS_FLAG; - end if; - else - -- Reset - trigger_sample_gen_next <= '0'; - -- DONE - stage_next <= IDLE; - end if; - when 3 => - assert (inst_data.addr /= INSTANCE_MEMORY_MAX_ADDRESS) severity FAILURE; - assert stable(clk, check_mask(inst_data.field_flags, IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG)) severity FAILURE; + -- Wait for Instance Data + if (inst_op_done = '1') then + case (cnt) is + -- GET FIRST INSTANCE + when 0 => + inst_op_start <= '1'; + inst_opcode <= GET_INSTANCE; + inst_r.i <= ind; + inst_r.addr <= inst_occupied_head(ind); + inst_r.field_flags <= IMF_STATUS_FLAG; + cnt_next <= cnt + 2; + -- GET NEXT INSTANCE + when 1 => + -- Continue + inst_op_start <= '1'; + inst_opcode <= GET_NEXT_INSTANCE; + inst_r.i <= ind; + inst_r.addr <= inst_data.addr; + inst_r.field_flags <= IMF_STATUS_FLAG; + cnt_next <= cnt + 1; + -- CHECK INSTANCE + when 2 => + -- Instance Found + if (inst_data.addr /= INSTANCE_MEMORY_MAX_ADDRESS) then + assert stable(clk, inst_data.i = ind and check_mask(inst_data.field_flags, IMF_STATUS_FLAG)) severity FAILURE; - -- RESOURCE_LIMITS_QOS (MAX_SAMPLES_PER_INSTANCE) - if (WITH_KEY and MAX_SAMPLES_PER_INSTANCE /= LENGTH_UNLIMITED and inst_data.sample_cnt = unsigned(MAX_SAMPLES_PER_INSTANCE)) then - if (HISTORY_QOS = KEEP_ALL_HISTORY_QOS and RELIABILITY_QOS = RELIABLE_RELIABILITY_QOS) then - -- Continue - inst_op_start <= '1'; - inst_opcode <= GET_NEXT_INSTANCE; - inst_r.addr <= inst_data.addr; - inst_r.field_flags <= IMF_STATUS_FLAG; - cnt_next <= 2; - else - -- Accept Change (Remove Oldest Instance Sample) - remove_oldest_inst_sample_next <= '1'; - - -- Update Instance - inst_op_start <= '1'; - inst_opcode <= UPDATE_INSTANCE; - inst_r.addr <= inst_data.addr; - inst_r.field_flags <= IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG; - inst_r.sample_cnt <= inst_data.sample_cnt + 1; - inst_r.status_info <= inst_data.status_info; - inst_r.status_info(ISI_GENERATE_SAMPLE_FLAG) <= '0'; - - - cur_sample_next <= empty_sample_list_head; - cur_inst_next <= inst_data.addr; - stage_next <= GENERATE_SAMPLE; - cnt_next <= 0; - end if; - -- RESOURCE_LIMITS_QOS (MAX_SAMPLES) - elsif (empty_sample_list_head = empty_sample_list_tail) then - if (HISTORY_QOS = KEEP_ALL_HISTORY_QOS and RELIABILITY_QOS = RELIABLE_RELIABILITY_QOS) then - wait_for_sample_removal_next <= '1'; - -- Reset - trigger_sample_gen_next <= '0'; - -- DONE - stage_next <= IDLE; - else - -- Accept Change (Remove Oldest Sample) - remove_oldest_sample_next <= '1'; - - -- Update Instance - inst_op_start <= '1'; - inst_opcode <= UPDATE_INSTANCE; - inst_r.addr <= inst_data.addr; - inst_r.field_flags <= IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG; - inst_r.sample_cnt <= inst_data.sample_cnt + 1; - inst_r.status_info <= inst_data.status_info; - inst_r.status_info(ISI_GENERATE_SAMPLE_FLAG) <= '0'; - - cur_sample_next <= empty_sample_list_head; - cur_inst_next <= inst_data.addr; - stage_next <= GENERATE_SAMPLE; - cnt_next <= 0; - end if; + -- Sample needs to be Generated + if (inst_data.status_info(ISI_GENERATE_SAMPLE_FLAG) = '1') then + -- GET Required Instance Data + inst_op_start <= '1'; + inst_opcode <= GET_INSTANCE; + inst_r.i <= ind; + inst_r.addr <= inst_data.addr; + inst_r.field_flags <= IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG or IMF_DISPOSED_CNT_FLAG or IMF_NO_WRITERS_CNT_FLAG; + cnt_next <= cnt + 1; else + -- Continue + cnt_next <= 1; -- GET NEXT INSTANCE + end if; + else + -- Reset + trigger_sample_gen_next <= '0'; + -- DONE + stage_next <= IDLE; + end if; + -- CHECK QOS + when 3 => + assert (inst_data.addr /= INSTANCE_MEMORY_MAX_ADDRESS) severity FAILURE; + assert stable(clk, inst_data.i = ind and check_mask(inst_data.field_flags, IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG)) severity FAILURE; + + -- RESOURCE_LIMITS_QOS (MAX_SAMPLES_PER_INSTANCE) + if (CONFIG_ARRAY_T(ind).MAX_SAMPLES_PER_INSTANCE /= LENGTH_UNLIMITED and inst_data.sample_cnt = unsigned(CONFIG_ARRAY_T(ind).MAX_SAMPLES_PER_INSTANCE)) then + if (CONFIG_ARRAY_T(ind).HISTORY_QOS = KEEP_ALL_HISTORY_QOS and CONFIG_ARRAY_T(ind).RELIABILITY_QOS = RELIABLE_RELIABILITY_QOS) then + wait_for_sample_removal_next <= '1'; + -- Continue + cnt_next <= 1; -- GET NEXT INSTANCE + else + -- Accept Change (Remove Oldest Instance Sample) + remove_oldest_inst_sample_next <= '1'; + -- Update Instance inst_op_start <= '1'; inst_opcode <= UPDATE_INSTANCE; + inst_r.i <= ind; inst_r.addr <= inst_data.addr; inst_r.field_flags <= IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG; inst_r.sample_cnt <= inst_data.sample_cnt + 1; inst_r.status_info <= inst_data.status_info; inst_r.status_info(ISI_GENERATE_SAMPLE_FLAG) <= '0'; - cur_sample_next <= empty_sample_list_head; + + cur_sample_next <= empty_sample_list_head(ind); cur_inst_next <= inst_data.addr; stage_next <= GENERATE_SAMPLE; cnt_next <= 0; end if; - when others => - null; - end case; - end if; + -- RESOURCE_LIMITS_QOS (MAX_SAMPLES) + elsif (empty_sample_list_head(ind) = empty_sample_list_tail(ind)) then + if (CONFIG_ARRAY_T(ind).HISTORY_QOS = KEEP_ALL_HISTORY_QOS and CONFIG_ARRAY_T(ind).RELIABILITY_QOS = RELIABLE_RELIABILITY_QOS) then + wait_for_sample_removal_next <= '1'; + -- Continue + cnt_next <= 1; -- GET NEXT INSTANCE + else + -- Accept Change (Remove Oldest Sample) + remove_oldest_sample_next <= '1'; + + -- Update Instance + inst_op_start <= '1'; + inst_opcode <= UPDATE_INSTANCE; + inst_r.i <= ind; + inst_r.addr <= inst_data.addr; + inst_r.field_flags <= IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG; + inst_r.sample_cnt <= inst_data.sample_cnt + 1; + inst_r.status_info <= inst_data.status_info; + inst_r.status_info(ISI_GENERATE_SAMPLE_FLAG) <= '0'; + + cur_sample_next <= empty_sample_list_head(ind); + cur_inst_next <= inst_data.addr; + stage_next <= GENERATE_SAMPLE; + cnt_next <= 0; + end if; + else + -- Update Instance + inst_op_start <= '1'; + inst_opcode <= UPDATE_INSTANCE; + inst_r.i <= ind; + inst_r.addr <= inst_data.addr; + inst_r.field_flags <= IMF_STATUS_FLAG or IMF_SAMPLE_CNT_FLAG; + inst_r.sample_cnt <= inst_data.sample_cnt + 1; + inst_r.status_info <= inst_data.status_info; + inst_r.status_info(ISI_GENERATE_SAMPLE_FLAG) <= '0'; + + cur_sample_next <= empty_sample_list_head(ind); + cur_inst_next <= inst_data.addr; + stage_next <= GENERATE_SAMPLE; + cnt_next <= 0; + end if; + when others => + null; + end case; end if; when GET_SAMPLE_REJECTED_STATUS => case (cnt) is -- Return Code when 0 => - done_dds <= '1'; - return_code_dds <= RETCODE_OK; - cnt_next <= cnt + 1; + done_dds(ind) <= '1'; + return_code_dds(ind) <= RETCODE_OK; + cnt_next <= cnt + 1; -- Total Count when 1 => - data_out_dds <= std_logic_vector(sample_rej_cnt); - valid_out_dds <= '1'; - if (ready_out_dds = '1') then + data_out_dds(ind) <= std_logic_vector(sample_rej_cnt(ind)); + valid_out_dds(ind) <= '1'; + if (ready_out_dds(ind) = '1') then cnt_next <= cnt + 1; end if; -- Total Count Change when 2 => - data_out_dds <= std_logic_vector(sample_rej_cnt_change); - valid_out_dds <= '1'; - if (ready_out_dds = '1') then + data_out_dds(ind) <= std_logic_vector(sample_rej_cnt_change(ind)); + valid_out_dds(ind) <= '1'; + if (ready_out_dds(ind) = '1') then -- Reset - sample_rej_cnt_change_next <= (others => '0'); + sample_rej_cnt_change_next(ind) <= (others => '0'); cnt_next <= cnt + 1; end if; -- Last Reason when 3 => - data_out_dds <= sample_rej_last_reason; - valid_out_dds <= '1'; - if (ready_out_dds = '1') then + data_out_dds(ind) <= sample_rej_last_reason(ind); + valid_out_dds(ind) <= '1'; + if (ready_out_dds(ind) = '1') then -- Reset - sample_rej_last_reason_next <= NOT_REJECTED; + sample_rej_last_reason_next(ind) <= NOT_REJECTED; cnt_next <= cnt + 1; end if; -- Last Instance Handle 1/4 when 4 => - data_out_dds <= sample_rej_last_inst(0); - valid_out_dds <= '1'; - if (ready_out_dds = '1') then + data_out_dds(ind) <= sample_rej_last_inst(ind)(0); + valid_out_dds(ind) <= '1'; + if (ready_out_dds(ind) = '1') then cnt_next <= cnt + 1; end if; -- Last Instance Handle 2/4 when 5 => - data_out_dds <= sample_rej_last_inst(1); - valid_out_dds <= '1'; - if (ready_out_dds = '1') then + data_out_dds(ind) <= sample_rej_last_inst(ind)(1); + valid_out_dds(ind) <= '1'; + if (ready_out_dds(ind) = '1') then cnt_next <= cnt + 1; end if; -- Last Instance Handle 3/4 when 6 => - data_out_dds <= sample_rej_last_inst(2); - valid_out_dds <= '1'; - if (ready_out_dds = '1') then + data_out_dds(ind) <= sample_rej_last_inst(ind)(2); + valid_out_dds(ind) <= '1'; + if (ready_out_dds(ind) = '1') then cnt_next <= cnt + 1; end if; -- Last Instance Handle 4/4 when 7 => - data_out_dds <= sample_rej_last_inst(3); - valid_out_dds <= '1'; - last_word_out_dds <= '1'; - if (ready_out_dds = '1') then + data_out_dds(ind) <= sample_rej_last_inst(ind)(3); + valid_out_dds(ind) <= '1'; + last_word_out_dds(ind) <= '1'; + if (ready_out_dds(ind) = '1') then -- Reset - sample_rej_last_inst_next <= HANDLE_NIL; - status_sig_next <= status_sig and (not SAMPLE_REJECTED_STATUS); + sample_rej_last_inst_next(ind) <= HANDLE_NIL; + status_sig_next(ind) <= status_sig(ind) and (not SAMPLE_REJECTED_STATUS); -- DONE stage_next <= IDLE; @@ -4834,55 +4792,55 @@ begin case (cnt) is -- Return Code when 0 => - done_dds <= '1'; - return_code_dds <= RETCODE_OK; - cnt_next <= cnt + 1; + done_dds(ind) <= '1'; + return_code_dds(ind) <= RETCODE_OK; + cnt_next <= cnt + 1; -- Total Count when 1 => - data_out_dds <= std_logic_vector(deadline_miss_cnt); - valid_out_dds <= '1'; - if (ready_out_dds = '1') then + data_out_dds(ind) <= std_logic_vector(deadline_miss_cnt(ind)); + valid_out_dds(ind) <= '1'; + if (ready_out_dds(ind) = '1') then cnt_next <= cnt + 1; end if; -- Total Count Change when 2 => - data_out_dds <= std_logic_vector(deadline_miss_cnt_change); - valid_out_dds <= '1'; - if (ready_out_dds = '1') then + data_out_dds(ind) <= std_logic_vector(deadline_miss_cnt_change(ind)); + valid_out_dds(ind) <= '1'; + if (ready_out_dds(ind) = '1') then -- Reset - deadline_miss_cnt_change_next <= (others => '0'); + deadline_miss_cnt_change_next(ind) <= (others => '0'); cnt_next <= cnt + 1; end if; -- Last Instance Handle 1/4 when 3 => - data_out_dds <= deadline_miss_last_inst(0); - valid_out_dds <= '1'; - if (ready_out_dds = '1') then + data_out_dds(ind) <= deadline_miss_last_inst(ind)(0); + valid_out_dds(ind) <= '1'; + if (ready_out_dds(ind) = '1') then cnt_next <= cnt + 1; end if; -- Last Instance Handle 2/4 when 4 => - data_out_dds <= deadline_miss_last_inst(1); - valid_out_dds <= '1'; - if (ready_out_dds = '1') then + data_out_dds(ind) <= deadline_miss_last_inst(ind)(1); + valid_out_dds(ind) <= '1'; + if (ready_out_dds(ind) = '1') then cnt_next <= cnt + 1; end if; -- Last Instance Handle 3/4 when 5 => - data_out_dds <= deadline_miss_last_inst(2); - valid_out_dds <= '1'; - if (ready_out_dds = '1') then + data_out_dds(ind) <= deadline_miss_last_inst(ind)(2); + valid_out_dds(ind) <= '1'; + if (ready_out_dds(ind) = '1') then cnt_next <= cnt + 1; end if; -- Last Instance Handle 4/4 when 6 => - data_out_dds <= deadline_miss_last_inst(3); - valid_out_dds <= '1'; - last_word_out_dds <= '1'; - if (ready_out_dds = '1') then + data_out_dds(ind) <= deadline_miss_last_inst(ind)(3); + valid_out_dds(ind) <= '1'; + last_word_out_dds(ind) <= '1'; + if (ready_out_dds(ind) = '1') then -- Reset - deadline_miss_last_inst_next <= HANDLE_NIL; - status_sig_next <= status_sig and (not REQUESTED_DEADLINE_MISSED_STATUS); + deadline_miss_last_inst_next(ind) <= HANDLE_NIL; + status_sig_next(ind) <= status_sig(ind) and (not REQUESTED_DEADLINE_MISSED_STATUS); -- DONE stage_next <= IDLE; @@ -4891,67 +4849,94 @@ begin null; end case; when CHECK_DEADLINE => - -- Synthesis Guard - if (WITH_KEY) then - -- Memory Operation Guard - if (inst_op_done = '1') then - case (cnt) is - -- Get First Instance - when 0 => - inst_op_start <= '1'; - inst_opcode <= GET_INSTANCE; - inst_r.addr <= inst_occupied_head; - inst_r.field_flags <= IMF_KEY_HASH_FLAG or IMF_STATUS_FLAG; - cnt_next <= 2; - -- Get Next Instance - when 1 => - inst_op_start <= '1'; - inst_opcode <= GET_NEXT_INSTANCE; - inst_r.addr <= inst_data.addr; - inst_r.field_flags <= IMF_KEY_HASH_FLAG or IMF_STATUS_FLAG; - cnt_next <= 2; - -- Check Instance - when 2 => - -- Reached End of Instances - if (inst_data.addr = INSTANCE_MEMORY_MAX_ADDRESS) then - -- DONE - stage_next <= IDLE; - else - assert stable(clk, check_mask(inst_data.field_flags, IMF_STATUS_FLAG or IMF_KEY_HASH_FLAG)) severity FAILURE; - - -- Instance received Sample - if (inst_data.status_info(ISI_LIVELINESS_FLAG) = '1') then - -- Reset Liveliness Flag - inst_op_start <= '1'; - inst_opcode <= UPDATE_INSTANCE; - inst_r.addr <= inst_data.addr; - inst_r.field_flags <= IMF_STATUS_FLAG; - inst_r.status_info <= inst_data.status_info; - inst_r.status_info(ISI_LIVELINESS_FLAG) <= '0'; - cnt_next <= 1; - else - -- Update Requested Deadline Missed Status - status_sig_next <= status_sig or REQUESTED_DEADLINE_MISSED_STATUS; - deadline_miss_cnt_next <= deadline_miss_cnt + 1; - deadline_miss_cnt_change_next <= deadline_miss_cnt_change + 1; - deadline_miss_last_inst_next <= inst_data.key_hash; - cnt_next <= 1; - end if; + -- Memory Operation Guard + if (inst_op_done = '1') then + case (cnt) is + -- GET NEXT WRITER + when 0 => + if (ind = NUM_READERS-1) then + -- DONE + stage_next <= IDLE; + else + -- Next Writer + ind_next <= ind + 1; + cnt_next <= cnt + 1; + end if; + -- CHECK DEADLINE + when 1 => + -- Deadline Check Trigger + if (CONFIG_ARRAY_T(ind).DEADLINE_QOS /= DURATION_INFINITE and deadline_time(ind) <= time) then + tmp_dw := deadline_time(ind) + CONFIG_ARRAY_T(ind).DEADLINE_QOS; + deadline_time_next(ind) <= tmp_dw; + + -- XXX: Possible Worst Case Path (64-bit addition and comparison in same clock) + -- Update Check Time + if (tmp_dw < deadline_check_time) then + deadline_check_time_next <= tmp_dw; end if; - when others => - null; - end case; - end if; + + cnt_next <= cnt + 1; + else + if (CONFIG_ARRAY_T(ind).DEADLINE_QOS /= DURATION_INFINITE and deadline_time(ind) <= deadline_check_time) then + deadline_check_time_next <= deadline_time(ind); + end if; + + -- Continue + cnt_next <= 0; -- GET NEXT WRITER + end if; + -- GET FIRST Instance + when 2 => + inst_op_start <= '1'; + inst_opcode <= GET_INSTANCE; + inst_r.i <= ind; + inst_r.addr <= inst_occupied_head(ind); + inst_r.field_flags <= IMF_KEY_HASH_FLAG or IMF_STATUS_FLAG; + cnt_next <= 4; -- CHECK INSTANCE + -- GET NEXT Instance + when 3 => + inst_op_start <= '1'; + inst_opcode <= GET_NEXT_INSTANCE; + inst_r.i <= ind; + inst_r.addr <= inst_data.addr; + inst_r.field_flags <= IMF_KEY_HASH_FLAG or IMF_STATUS_FLAG; + cnt_next <= 4; -- CHECK INSTANCE + -- CHECK Instance + when 4 => + -- Reached End of Instances + if (inst_data.addr = INSTANCE_MEMORY_MAX_ADDRESS) then + -- Continue + cnt_next <= 0; -- GET NEXT WRITER + else + assert stable(clk, inst_data.i = ind and check_mask(inst_data.field_flags, IMF_STATUS_FLAG or IMF_KEY_HASH_FLAG)) severity FAILURE; + + -- Instance received Sample + if (inst_data.status_info(ISI_LIVELINESS_FLAG) = '1') then + -- Reset Liveliness Flag + inst_op_start <= '1'; + inst_opcode <= UPDATE_INSTANCE; + inst_r.i <= ind; + inst_r.addr <= inst_data.addr; + inst_r.field_flags <= IMF_STATUS_FLAG; + inst_r.status_info <= inst_data.status_info; + inst_r.status_info(ISI_LIVELINESS_FLAG) <= '0'; + cnt_next <= 3; -- GET NEXT INSTANCE + else + -- Update Requested Deadline Missed Status + status_sig_next(ind) <= status_sig(ind) or REQUESTED_DEADLINE_MISSED_STATUS; + deadline_miss_cnt_next(ind) <= std_logic_vector(unsigned(deadline_miss_cnt(ind)) + 1); + deadline_miss_cnt_change_next(ind) <= std_logic_vector(unsigned(deadline_miss_cnt_change(ind)) + 1); + deadline_miss_last_inst_next(ind) <= inst_data.key_hash; + cnt_next <= 3; -- GET NEXT INSTANCE + end if; + end if; + when others => + null; + end case; end if; when RESET_SAMPLE_MEMORY => case (cnt) is - -- Initialize + -- SET Previous Pointer when 0 => - prev_sample_next <= SAMPLE_MEMORY_MAX_ADDRESS; - cur_sample_next <= (others => '0'); - cnt_next <= cnt + 1; - -- Set Previous Pointer - when 1 => sample_valid_in <= '1'; sample_addr <= cur_sample + SMF_PREV_ADDR_OFFSET; sample_write_data <= std_logic_vector(resize(prev_sample,WORD_WIDTH)); @@ -4960,11 +4945,11 @@ begin if (sample_ready_in = '1') then cnt_next <= cnt + 1; end if; - -- Set Next Pointer - when 2 => + -- SET Next Pointer + when 1 => sample_valid_in <= '1'; sample_addr <= cur_sample + SMF_NEXT_ADDR_OFFSET; - if (cur_sample = MAX_SAMPLE_ADDRESS) then + if (cur_sample = MAX_SAMPLE_ADDRESS(ind)) then sample_write_data <= std_logic_vector(resize(SAMPLE_MEMORY_MAX_ADDRESS,WORD_WIDTH)); else sample_write_data <= std_logic_vector(resize(cur_sample + SAMPLE_FRAME_SIZE,WORD_WIDTH)); @@ -4972,488 +4957,337 @@ begin -- Memory Flow Control Guard if (sample_ready_in = '1') then - if (cur_sample = MAX_SAMPLE_ADDRESS) then + if (cur_sample = MAX_SAMPLE_ADDRESS(ind)) then + empty_sample_list_head_next(ind) <= FIRST_SAMPLE_ADDRESS; + empty_sample_list_tail_next(ind) <= MAX_SAMPLE_ADDRESS(ind); -- DONE - stage_next <= RESET_PAYLOAD_MEMORY; - cnt_next <= 0; - empty_sample_list_head_next <= FIRST_SAMPLE_ADDRESS; - empty_sample_list_tail_next <= MAX_SAMPLE_ADDRESS; + cur_payload_next <= FIRST_PAYLOAD_ADDRESS; + stage_next <= RESET_PAYLOAD_MEMORY; else -- Continue cur_sample_next <= cur_sample + SAMPLE_FRAME_SIZE; prev_sample_next <= cur_sample; - cnt_next <= 1; + cnt_next <= 0; -- SET Previous Pointer end if; end if; when others => null; end case; when RESET_PAYLOAD_MEMORY => - case (cnt) is - -- Initialize - when 0 => - cur_payload_next <= (others => '0'); - cnt_next <= cnt + 1; - -- Set Next Pointer - when 1 => - payload_valid_in <= '1'; - payload_addr <= cur_payload + PMF_NEXT_ADDR_OFFSET; - if (cur_payload = MAX_PAYLOAD_ADDRESS) then - payload_write_data <= std_logic_vector(resize(PAYLOAD_MEMORY_MAX_ADDRESS,WORD_WIDTH)); - else - payload_write_data <= std_logic_vector(resize(cur_payload + PAYLOAD_FRAME_SIZE,WORD_WIDTH)); - end if; + -- SET Next Pointer + payload_valid_in <= '1'; + payload_addr <= cur_payload + PMF_NEXT_ADDR_OFFSET; + if (cur_payload = MAX_PAYLOAD_ADDRESS(ind)) then + payload_write_data <= std_logic_vector(resize(PAYLOAD_MEMORY_MAX_ADDRESS,WORD_WIDTH)); + else + payload_write_data <= std_logic_vector(resize(cur_payload + PAYLOAD_FRAME_SIZE(ind),WORD_WIDTH)); + end if; + + -- Memory Flow Control Guard + if (payload_ready_in = '1') then + if (cur_payload = MAX_PAYLOAD_ADDRESS(ind)) then + empty_payload_list_head_next(ind) <= FIRST_PAYLOAD_ADDRESS; - -- Memory Flow Control Guard - if (payload_ready_in = '1') then - if (cur_payload = MAX_PAYLOAD_ADDRESS) then - -- DONE - stage_next <= IDLE; - empty_payload_list_head_next <= FIRST_PAYLOAD_ADDRESS; - else - cur_payload_next <= cur_payload + PAYLOAD_FRAME_SIZE; - end if; + if (ind = NUM_READERS-1) then + -- DONE + stage_next <= IDLE; + else + -- Continue (Next Writer) + ind_next <= ind + 1; + prev_sample_next <= SAMPLE_MEMORY_MAX_ADDRESS; + cur_sample_next <= FIRST_SAMPLE_ADDRESS; + stage_next <= RESET_SAMPLE_MEMORY; + cnt_next <= 0; end if; - when others => - null; - end case; + else + cur_payload_next <= cur_payload + PAYLOAD_FRAME_SIZE(ind); + end if; + end if; end case; end process; - gen_inst_ctrl_prc : if WITH_KEY generate + empty_head_sig_prc : process(all) + begin + for i in 0 to NUM_READERS-1 loop + empty_inst_head_sig(i) <= to_integer(inst_empty_head(i)); + empty_sample_head_sig(i) <= to_integer(empty_sample_list_head(i)); + empty_payload_head_sig(i) <= to_integer(empty_payload_list_head(i)); + end loop; + end process; - -- *Instance Memory Process* - -- STATE DESCRIPTION - -- IDLE Idle State. Done Signal is pulled high and Memory FSM accepts new memory operations - -- SEARCH_INSTANCE See Memory OPCODE Description - -- GET_NEXT_INSTANCE See Memory OPCODE Description - -- GET_INSTANCE_DATA Latch specified Instance Data for use by main process - -- FIND_POS Find List position of Instance to be added - -- INSERT_INSTANCE See Memory OPCODE Description - -- UPDATE_INSTANCE See Memory OPCODE Description - -- REMOVE_INSTANCE See Memory OPCODE Description - -- UNMARK_INTANCES See Memory OPCODE Description - -- RESET_MEMORY Reset Endpoint Memory to Empty State - inst_ctrl_prc : process(all) - begin - -- DEFAULT Registered - inst_stage_next <= inst_stage; - inst_addr_base_next <= inst_addr_base; - inst_empty_head_next <= inst_empty_head; - inst_occupied_head_next <= inst_occupied_head; - inst_latch_data_next <= inst_latch_data; - inst_addr_latch_next <= inst_addr_latch; - inst_cnt_next <= inst_cnt; - inst_cnt2_next <= inst_cnt2; - inst_data_next <= inst_data; - inst_long_latch_next <= inst_long_latch; - -- DEFAULT Unregistered - inst_abort_read <= '0'; - inst_ready_out <= '0'; - inst_valid_in <= '0'; - inst_read <= '0'; - inst_op_done <= '0'; - inst_addr <= (others => '0'); - inst_write_data <= (others => '0'); - - - case (inst_stage) is - when IDLE => - inst_op_done <= '1'; + -- *Instance Memory Process* + -- STATE DESCRIPTION + -- IDLE Idle State. Done Signal is pulled high and Memory FSM accepts new memory operations + -- SEARCH_INSTANCE See Memory OPCODE Description + -- GET_NEXT_INSTANCE See Memory OPCODE Description + -- GET_INSTANCE_DATA Latch specified Instance Data for use by main process + -- FIND_POS Find List position of Instance to be added + -- INSERT_INSTANCE See Memory OPCODE Description + -- UPDATE_INSTANCE See Memory OPCODE Description + -- REMOVE_INSTANCE See Memory OPCODE Description + -- UNMARK_INTANCES See Memory OPCODE Description + -- RESET_MEMORY Reset Endpoint Memory to Empty State + inst_ctrl_prc : process(all) + begin + -- DEFAULT Registered + inst_stage_next <= inst_stage; + inst_addr_base_next <= inst_addr_base; + inst_empty_head_next <= inst_empty_head; + inst_occupied_head_next <= inst_occupied_head; + inst_latch_data_next <= inst_latch_data; + inst_addr_latch_next <= inst_addr_latch; + inst_cnt_next <= inst_cnt; + inst_cnt2_next <= inst_cnt2; + inst_data_next <= inst_data; + inst_long_latch_next <= inst_long_latch; + -- DEFAULT Unregistered + inst_abort_read <= '0'; + inst_ready_out <= '0'; + inst_valid_in <= '0'; + inst_read <= '0'; + inst_op_done <= '0'; + inst_addr <= (others => '0'); + inst_write_data <= (others => '0'); + + + case (inst_stage) is + when IDLE => + inst_op_done <= '1'; + + if (inst_op_start = '1') then + inst_latch_data_next <= inst_r; - if (inst_op_start = '1') then - inst_latch_data_next <= inst_r; + case(inst_opcode) is + when SEARCH_INSTANCE => + -- Reset Data + inst_data_next <= ZERO_INSTANCE_DATA; + inst_data_next.i <= inst_r.i; + + -- No Instances available + if (inst_occupied_head(inst_r.i) /= INSTANCE_MEMORY_MAX_ADDRESS) then + inst_addr_base_next <= inst_occupied_head(inst_r.i); + inst_stage_next <= SEARCH_INSTANCE; + inst_cnt_next <= 0; + end if; + when INSERT_INSTANCE => + assert (inst_empty_head(inst_r.i) /= INSTANCE_MEMORY_MAX_ADDRESS) severity FAILURE; + + inst_data_next <= ZERO_INSTANCE_DATA; + inst_data_next.i <= inst_r.i; + + -- First Instance + if (inst_occupied_head(inst_r.i) = INSTANCE_MEMORY_MAX_ADDRESS) then + + inst_data_next.addr <= inst_empty_head(inst_r.i); + + inst_addr_base_next <= INSTANCE_MEMORY_MAX_ADDRESS; + inst_addr_latch_next <= INSTANCE_MEMORY_MAX_ADDRESS; + inst_stage_next <= INSERT_INSTANCE; + inst_cnt_next <= 0; + else + inst_data_next.addr <= inst_empty_head(inst_r.i); + inst_addr_base_next <= inst_occupied_head(inst_r.i); + inst_stage_next <= FIND_POS; + inst_cnt_next <= 0; + end if; + when UPDATE_INSTANCE => + if (inst_r.addr = INSTANCE_MEMORY_MAX_ADDRESS) then + inst_data_next <= ZERO_INSTANCE_DATA; + inst_data_next.i <= inst_r.i; + else + if (inst_r.i /= inst_data.i or inst_r.addr /= inst_data.addr) then + inst_data_next <= ZERO_INSTANCE_DATA; + inst_data_next.i <= inst_r.i; + end if; + + inst_data_next.addr <= inst_r.addr; + inst_addr_base_next <= inst_r.addr; + inst_stage_next <= UPDATE_INSTANCE; + if check_mask(inst_r.field_flags,IMF_STATUS_FLAG) then + inst_cnt_next <= 0; + elsif check_mask(inst_r.field_flags,IMF_SAMPLE_CNT_FLAG) then + inst_cnt_next <= 1; + elsif check_mask(inst_r.field_flags,IMF_DISPOSED_CNT_FLAG) then + inst_cnt_next <= 2; + elsif check_mask(inst_r.field_flags,IMF_NO_WRITERS_CNT_FLAG) then + inst_cnt_next <= 3; + elsif check_mask(inst_r.field_flags,IMF_IGNORE_DEADLINE_FLAG) then + inst_cnt_next <= 4; + elsif check_mask(inst_r.field_flags,IMF_WRITER_BITMAP_FLAG) then + inst_cnt_next <= 6; + inst_cnt2_next <= 0; + else + -- DONE + inst_stage_next <= IDLE; + end if; + end if; + when REMOVE_INSTANCE => + inst_data_next <= ZERO_INSTANCE_DATA; + inst_data_next.i <= inst_r.i; + + if (inst_r.addr /= INSTANCE_MEMORY_MAX_ADDRESS) then + inst_addr_base_next <= inst_r.addr; + inst_stage_next <= REMOVE_INSTANCE; + inst_cnt_next <= 0; + end if; + when GET_NEXT_INSTANCE => + inst_data_next <= ZERO_INSTANCE_DATA; + inst_data_next.i <= inst_r.i; + + -- No Instances available + if (inst_r.addr /= INSTANCE_MEMORY_MAX_ADDRESS) then + inst_addr_base_next <= inst_r.addr; + inst_stage_next <= GET_NEXT_INSTANCE; + inst_cnt_next <= 0; + end if; + when GET_INSTANCE => + if (inst_r.addr = INSTANCE_MEMORY_MAX_ADDRESS) then + inst_data_next <= ZERO_INSTANCE_DATA; + inst_data_next.i <= inst_r.i; + else + if (inst_r.i /= inst_data.i or inst_r.addr /= inst_data.addr) then + inst_data_next <= ZERO_INSTANCE_DATA; + inst_data_next.i <= inst_r.i; + end if; + + inst_data_next.addr <= inst_r.addr; + inst_addr_base_next <= inst_r.addr; + inst_stage_next <= GET_INSTANCE_DATA; + if check_mask(inst_r.field_flags,IMF_KEY_HASH_FLAG) then + inst_cnt_next <= 0; + elsif check_mask(inst_r.field_flags,IMF_STATUS_FLAG) then + inst_cnt_next <= 4; + elsif check_mask(inst_r.field_flags,IMF_SAMPLE_CNT_FLAG) then + inst_cnt_next <= 5; + elsif check_mask(inst_r.field_flags,IMF_DISPOSED_CNT_FLAG) then + inst_cnt_next <= 6; + elsif check_mask(inst_r.field_flags,IMF_NO_WRITERS_CNT_FLAG) then + inst_cnt_next <= 7; + elsif check_mask(inst_r.field_flags,IMF_IGNORE_DEADLINE_FLAG) then + inst_cnt_next <= 8; + elsif check_mask(inst_r.field_flags,IMF_WRITER_BITMAP_FLAG) then + inst_cnt_next <= 10; + inst_cnt2_next <= 0; + else + -- DONE + inst_stage_next <= IDLE; + end if; + end if; + when UNMARK_INSTANCES => + -- Empty Memory Guard + if (inst_occupied_head(inst_r.i) /= INSTANCE_MEMORY_MAX_ADDRESS) then + inst_data_next <= ZERO_INSTANCE_DATA; + inst_data_next.i <= inst_r.i; + + inst_addr_base_next <= inst_occupied_head(inst_r.i); + inst_stage_next <= UNMARK_INSTANCES; + inst_cnt_next <= 0; + end if; + when others => + null; + end case; + end if; + when SEARCH_INSTANCE => + + case (inst_cnt) is + -- GET Key Hash 1/4 + when 0 => + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_KEY_HASH_OFFSET; + inst_read <= '1'; - case(inst_opcode) is - when SEARCH_INSTANCE => - -- Reset Data - inst_data_next <= ZERO_INSTANCE_DATA; - if (TIME_BASED_FILTER_QOS = DURATION_ZERO) then - inst_data_next.field_flags <= IMF_IGNORE_DEADLINE_FLAG; - end if; - - -- No Instances available - if (inst_occupied_head /= INSTANCE_MEMORY_MAX_ADDRESS) then - inst_addr_base_next <= inst_occupied_head; - inst_stage_next <= SEARCH_INSTANCE; - inst_cnt_next <= 0; - end if; - when INSERT_INSTANCE => - assert (inst_empty_head /= INSTANCE_MEMORY_MAX_ADDRESS) severity FAILURE; - - inst_data_next <= ZERO_INSTANCE_DATA; - if (TIME_BASED_FILTER_QOS = DURATION_ZERO) then - inst_data_next.field_flags <= IMF_IGNORE_DEADLINE_FLAG; - end if; - - -- First Instance - if (inst_occupied_head = INSTANCE_MEMORY_MAX_ADDRESS) then - - inst_data_next.addr <= inst_empty_head; - - inst_addr_base_next <= INSTANCE_MEMORY_MAX_ADDRESS; - inst_addr_latch_next <= INSTANCE_MEMORY_MAX_ADDRESS; - inst_stage_next <= INSERT_INSTANCE; - inst_cnt_next <= 0; - else - inst_data_next.addr <= inst_empty_head; - inst_addr_base_next <= inst_occupied_head; - inst_stage_next <= FIND_POS; - inst_cnt_next <= 0; - end if; - when UPDATE_INSTANCE => - if (inst_r.addr = INSTANCE_MEMORY_MAX_ADDRESS) then - inst_data_next <= ZERO_INSTANCE_DATA; - if (TIME_BASED_FILTER_QOS = DURATION_ZERO) then - inst_data_next.field_flags <= IMF_IGNORE_DEADLINE_FLAG; - end if; - else - if (inst_r.addr /= inst_data.addr) then - inst_data_next <= ZERO_INSTANCE_DATA; - if (TIME_BASED_FILTER_QOS = DURATION_ZERO) then - inst_data_next.field_flags <= IMF_IGNORE_DEADLINE_FLAG; - end if; - end if; - - inst_data_next.addr <= inst_r.addr; - inst_addr_base_next <= inst_r.addr; - inst_stage_next <= UPDATE_INSTANCE; - if check_mask(inst_r.field_flags,IMF_STATUS_FLAG) then - inst_cnt_next <= 0; - elsif check_mask(inst_r.field_flags,IMF_SAMPLE_CNT_FLAG) then - inst_cnt_next <= 1; - elsif check_mask(inst_r.field_flags,IMF_DISPOSED_CNT_FLAG) then - inst_cnt_next <= 2; - elsif check_mask(inst_r.field_flags,IMF_NO_WRITERS_CNT_FLAG) then - inst_cnt_next <= 3; - elsif (TIME_BASED_FILTER_QOS /= DURATION_ZERO and check_mask(inst_r.field_flags,IMF_IGNORE_DEADLINE_FLAG)) then - inst_cnt_next <= 4; - elsif check_mask(inst_r.field_flags,IMF_WRITER_BITMAP_FLAG) then - inst_cnt_next <= 6; - inst_cnt2_next <= 0; - else - -- DONE - inst_stage_next <= IDLE; - end if; - end if; - when REMOVE_INSTANCE => - inst_data_next <= ZERO_INSTANCE_DATA; - if (TIME_BASED_FILTER_QOS = DURATION_ZERO) then - inst_data_next.field_flags <= IMF_IGNORE_DEADLINE_FLAG; - end if; - - if (inst_r.addr /= INSTANCE_MEMORY_MAX_ADDRESS) then - inst_addr_base_next <= inst_r.addr; - inst_stage_next <= REMOVE_INSTANCE; - inst_cnt_next <= 0; - end if; - when GET_NEXT_INSTANCE => - inst_data_next <= ZERO_INSTANCE_DATA; - if (TIME_BASED_FILTER_QOS = DURATION_ZERO) then - inst_data_next.field_flags <= IMF_IGNORE_DEADLINE_FLAG; - end if; - - -- No Instances available - if (inst_r.addr /= INSTANCE_MEMORY_MAX_ADDRESS) then - inst_addr_base_next <= inst_r.addr; - inst_stage_next <= GET_NEXT_INSTANCE; - inst_cnt_next <= 0; - end if; - when GET_INSTANCE => - if (inst_r.addr = INSTANCE_MEMORY_MAX_ADDRESS) then - inst_data_next <= ZERO_INSTANCE_DATA; - if (TIME_BASED_FILTER_QOS = DURATION_ZERO) then - inst_data_next.field_flags <= IMF_IGNORE_DEADLINE_FLAG; - end if; - else - if (inst_r.addr /= inst_data.addr) then - inst_data_next <= ZERO_INSTANCE_DATA; - if (TIME_BASED_FILTER_QOS = DURATION_ZERO) then - inst_data_next.field_flags <= IMF_IGNORE_DEADLINE_FLAG; - end if; - end if; - - inst_data_next.addr <= inst_r.addr; - inst_addr_base_next <= inst_r.addr; - inst_stage_next <= GET_INSTANCE_DATA; - if check_mask(inst_r.field_flags,IMF_KEY_HASH_FLAG) then - inst_cnt_next <= 0; - elsif check_mask(inst_r.field_flags,IMF_STATUS_FLAG) then - inst_cnt_next <= 4; - elsif check_mask(inst_r.field_flags,IMF_SAMPLE_CNT_FLAG) then - inst_cnt_next <= 5; - elsif check_mask(inst_r.field_flags,IMF_DISPOSED_CNT_FLAG) then - inst_cnt_next <= 6; - elsif check_mask(inst_r.field_flags,IMF_NO_WRITERS_CNT_FLAG) then - inst_cnt_next <= 7; - elsif (TIME_BASED_FILTER_QOS /= DURATION_ZERO and check_mask(inst_r.field_flags,IMF_IGNORE_DEADLINE_FLAG)) then - inst_cnt_next <= 8; - elsif check_mask(inst_r.field_flags,IMF_WRITER_BITMAP_FLAG) then - inst_cnt_next <= 10; - inst_cnt2_next <= 0; - else - -- DONE - inst_stage_next <= IDLE; - end if; - end if; - when UNMARK_INSTANCES => - -- Empty Memory Guard - if (inst_occupied_head /= INSTANCE_MEMORY_MAX_ADDRESS) then - inst_data_next <= ZERO_INSTANCE_DATA; - if (TIME_BASED_FILTER_QOS = DURATION_ZERO) then - inst_data_next.field_flags <= IMF_IGNORE_DEADLINE_FLAG; - end if; - - inst_addr_base_next <= inst_occupied_head; - inst_stage_next <= UNMARK_INSTANCES; - inst_cnt_next <= 0; - end if; - when others => - null; - end case; - end if; - when SEARCH_INSTANCE => - - case (inst_cnt) is - -- GET Key Hash 1/4 - when 0 => - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_KEY_HASH_OFFSET; - inst_read <= '1'; - - -- Memory Flow Control Guard - if (inst_ready_in = '1') then + -- Memory Flow Control Guard + if (inst_ready_in = '1') then + inst_cnt_next <= inst_cnt + 1; + end if; + -- GET Key Hash 2/4 + when 1 => + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_KEY_HASH_OFFSET + 1; + inst_read <= '1'; + + -- Memory Flow Control Guard + if (inst_ready_in = '1') then + inst_cnt_next <= inst_cnt + 1; + end if; + -- GET Key Hash 3/4 + when 2 => + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_KEY_HASH_OFFSET + 2; + inst_read <= '1'; + + -- Memory Flow Control Guard + if (inst_ready_in = '1') then + inst_cnt_next <= inst_cnt + 1; + end if; + -- GET Key Hash 4/4 + when 3 => + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_KEY_HASH_OFFSET + 3; + inst_read <= '1'; + + -- Memory Flow Control Guard + if (inst_ready_in = '1') then + inst_cnt_next <= inst_cnt + 1; + end if; + -- READ Key Hash 1/4 + when 4 => + inst_ready_out <= '1'; + + -- Memory Flow Control Guard + if (inst_valid_out = '1') then + -- No Match + if (inst_read_data /= inst_latch_data.key_hash(0)) then + inst_abort_read <= '1'; + inst_cnt_next <= 8; -- GET NEXT INSTANCE + else inst_cnt_next <= inst_cnt + 1; end if; - -- GET Key Hash 2/4 - when 1 => - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_KEY_HASH_OFFSET + 1; - inst_read <= '1'; - - -- Memory Flow Control Guard - if (inst_ready_in = '1') then + end if; + -- READ Key Hash 2/4 + when 5 => + inst_ready_out <= '1'; + + -- Memory Flow Control Guard + if (inst_valid_out = '1') then + -- No Match + if (inst_read_data /= inst_latch_data.key_hash(1)) then + inst_abort_read <= '1'; + inst_cnt_next <= 8; -- GET NEXT INSTANCE + else inst_cnt_next <= inst_cnt + 1; end if; - -- GET Key Hash 3/4 - when 2 => - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_KEY_HASH_OFFSET + 2; - inst_read <= '1'; - - -- Memory Flow Control Guard - if (inst_ready_in = '1') then + end if; + -- READ Key Hash 3/4 + when 6 => + inst_ready_out <= '1'; + + -- Memory Flow Control Guard + if (inst_valid_out = '1') then + -- No Match + if (inst_read_data /= inst_latch_data.key_hash(2)) then + inst_abort_read <= '1'; + inst_cnt_next <= 8; -- GET NEXT INSTANCE + else inst_cnt_next <= inst_cnt + 1; end if; - -- GET Key Hash 4/4 - when 3 => - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_KEY_HASH_OFFSET + 3; - inst_read <= '1'; - - -- Memory Flow Control Guard - if (inst_ready_in = '1') then - inst_cnt_next <= inst_cnt + 1; - end if; - -- READ Key Hash 1/4 - when 4 => - inst_ready_out <= '1'; - - -- Memory Flow Control Guard - if (inst_valid_out = '1') then - -- No Match - if (inst_read_data /= inst_latch_data.key_hash(0)) then - inst_abort_read <= '1'; - inst_cnt_next <= 8; -- GET NEXT INSTANCE - else - inst_cnt_next <= inst_cnt + 1; - end if; - end if; - -- READ Key Hash 2/4 - when 5 => - inst_ready_out <= '1'; - - -- Memory Flow Control Guard - if (inst_valid_out = '1') then - -- No Match - if (inst_read_data /= inst_latch_data.key_hash(1)) then - inst_abort_read <= '1'; - inst_cnt_next <= 8; -- GET NEXT INSTANCE - else - inst_cnt_next <= inst_cnt + 1; - end if; - end if; - -- READ Key Hash 3/4 - when 6 => - inst_ready_out <= '1'; - - -- Memory Flow Control Guard - if (inst_valid_out = '1') then - -- No Match - if (inst_read_data /= inst_latch_data.key_hash(2)) then - inst_abort_read <= '1'; - inst_cnt_next <= 8; -- GET NEXT INSTANCE - else - inst_cnt_next <= inst_cnt + 1; - end if; - end if; - -- READ Key Hash 4/4 - when 7 => - inst_ready_out <= '1'; - - -- Memory Flow Control Guard - if (inst_valid_out = '1') then - -- No Match - if (inst_read_data /= inst_latch_data.key_hash(3)) then - inst_cnt_next <= 8; -- GET NEXT INSTANCE - else - inst_data_next.addr <= inst_addr_base; - -- Get Instance Data - inst_stage_next <= GET_INSTANCE_DATA; - if check_mask(inst_latch_data.field_flags,IMF_KEY_HASH_FLAG) then - inst_cnt_next <= 0; - elsif check_mask(inst_latch_data.field_flags,IMF_STATUS_FLAG) then - inst_cnt_next <= 4; - elsif check_mask(inst_latch_data.field_flags,IMF_SAMPLE_CNT_FLAG) then - inst_cnt_next <= 5; - elsif check_mask(inst_latch_data.field_flags,IMF_DISPOSED_CNT_FLAG) then - inst_cnt_next <= 6; - elsif check_mask(inst_latch_data.field_flags,IMF_NO_WRITERS_CNT_FLAG) then - inst_cnt_next <= 7; - elsif (TIME_BASED_FILTER_QOS /= DURATION_ZERO and check_mask(inst_latch_data.field_flags,IMF_IGNORE_DEADLINE_FLAG)) then - inst_cnt_next <= 8; - elsif check_mask(inst_latch_data.field_flags,IMF_WRITER_BITMAP_FLAG) then - inst_cnt_next <= 10; - inst_cnt2_next <= 0; - else - -- DONE - inst_stage_next <= IDLE; - end if; - end if; - end if; - -- GET Next Instance - when 8 => - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_NEXT_ADDR_OFFSET; - inst_read <= '1'; - - -- Memory Flow Control Guard - if (inst_ready_in = '1') then - inst_cnt_next <= inst_cnt + 1; - end if; - -- READ Next Instance - when 9 => - inst_ready_out <= '1'; - - -- Memory Flow Control Guard - if (inst_valid_out = '1') then - -- No more Endpoints - if (resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH) = INSTANCE_MEMORY_MAX_ADDRESS) then - inst_data_next.addr <= INSTANCE_MEMORY_MAX_ADDRESS; --No match - -- DONE - inst_stage_next <= IDLE; - else - -- Continue - inst_addr_base_next <= resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH); - inst_cnt_next <= 0; - end if; - end if; - when others => - null; - end case; - when GET_NEXT_INSTANCE => - case (inst_cnt) is - -- GET next Instance - when 0 => - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_NEXT_ADDR_OFFSET; - inst_read <= '1'; - - -- Memory Flow Control Guard - if (inst_ready_in = '1') then - inst_cnt_next <= inst_cnt + 1; - end if; - -- READ Next Instance - when 1 => - inst_ready_out <= '1'; - - -- Memory Flow Control Guard - if (inst_valid_out = '1') then - if (resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH) = INSTANCE_MEMORY_MAX_ADDRESS) then - inst_data_next.addr <= INSTANCE_MEMORY_MAX_ADDRESS; - -- DONE - inst_stage_next <= IDLE; - else - inst_data_next.addr <= resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH); - - -- Get Instance Data - inst_addr_base_next <= resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH); - inst_stage_next <= GET_INSTANCE_DATA; - if check_mask(inst_latch_data.field_flags,IMF_KEY_HASH_FLAG) then - inst_cnt_next <= 0; - elsif check_mask(inst_latch_data.field_flags,IMF_STATUS_FLAG) then - inst_cnt_next <= 4; - elsif check_mask(inst_latch_data.field_flags,IMF_SAMPLE_CNT_FLAG) then - inst_cnt_next <= 5; - elsif check_mask(inst_latch_data.field_flags,IMF_DISPOSED_CNT_FLAG) then - inst_cnt_next <= 6; - elsif check_mask(inst_latch_data.field_flags,IMF_NO_WRITERS_CNT_FLAG) then - inst_cnt_next <= 7; - elsif (TIME_BASED_FILTER_QOS /= DURATION_ZERO and check_mask(inst_latch_data.field_flags,IMF_IGNORE_DEADLINE_FLAG)) then - inst_cnt_next <= 8; - elsif check_mask(inst_latch_data.field_flags,IMF_WRITER_BITMAP_FLAG) then - inst_cnt_next <= 10; - inst_cnt2_next <= 0; - else - -- DONE - inst_stage_next <= IDLE; - end if; - end if; - end if; - when others => - null; - end case; - when GET_INSTANCE_DATA => - case (inst_cnt) is - -- GET Key Hash 1/4 - when 0 => - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_KEY_HASH_OFFSET; - inst_read <= '1'; - - -- Memory Flow Control Guard - if (inst_ready_in = '1') then - inst_cnt_next <= inst_cnt + 1; - end if; - -- GET Key Hash 2/4 - when 1 => - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_KEY_HASH_OFFSET + 1; - inst_read <= '1'; - - -- Memory Flow Control Guard - if (inst_ready_in = '1') then - inst_cnt_next <= inst_cnt + 1; - end if; - -- GET Key Hash 3/4 - when 2 => - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_KEY_HASH_OFFSET + 2; - inst_read <= '1'; - - -- Memory Flow Control Guard - if (inst_ready_in = '1') then - inst_cnt_next <= inst_cnt + 1; - end if; - -- GET Key Hash 4/4 - when 3 => - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_KEY_HASH_OFFSET + 3; - inst_read <= '1'; - - -- Memory Flow Control Guard - if (inst_ready_in = '1') then - if check_mask(inst_latch_data.field_flags,IMF_STATUS_FLAG) then + end if; + -- READ Key Hash 4/4 + when 7 => + inst_ready_out <= '1'; + + -- Memory Flow Control Guard + if (inst_valid_out = '1') then + -- No Match + if (inst_read_data /= inst_latch_data.key_hash(3)) then + inst_cnt_next <= 8; -- GET NEXT INSTANCE + else + inst_data_next.addr <= inst_addr_base; + -- Get Instance Data + inst_stage_next <= GET_INSTANCE_DATA; + if check_mask(inst_latch_data.field_flags,IMF_KEY_HASH_FLAG) then + inst_cnt_next <= 0; + elsif check_mask(inst_latch_data.field_flags,IMF_STATUS_FLAG) then inst_cnt_next <= 4; elsif check_mask(inst_latch_data.field_flags,IMF_SAMPLE_CNT_FLAG) then inst_cnt_next <= 5; @@ -5461,234 +5295,289 @@ begin inst_cnt_next <= 6; elsif check_mask(inst_latch_data.field_flags,IMF_NO_WRITERS_CNT_FLAG) then inst_cnt_next <= 7; - elsif (TIME_BASED_FILTER_QOS /= DURATION_ZERO and check_mask(inst_latch_data.field_flags,IMF_IGNORE_DEADLINE_FLAG)) then + elsif check_mask(inst_latch_data.field_flags,IMF_IGNORE_DEADLINE_FLAG) then inst_cnt_next <= 8; elsif check_mask(inst_latch_data.field_flags,IMF_WRITER_BITMAP_FLAG) then inst_cnt_next <= 10; inst_cnt2_next <= 0; else - inst_cnt_next <= 11; + -- DONE + inst_stage_next <= IDLE; end if; end if; - -- GET Status Info - when 4 => - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_STATUS_INFO_OFFSET; - inst_read <= '1'; - - -- Memory Flow Control Guard - if (inst_ready_in = '1') then - if check_mask(inst_latch_data.field_flags,IMF_SAMPLE_CNT_FLAG) then + end if; + -- GET Next Instance + when 8 => + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_NEXT_ADDR_OFFSET; + inst_read <= '1'; + + -- Memory Flow Control Guard + if (inst_ready_in = '1') then + inst_cnt_next <= inst_cnt + 1; + end if; + -- READ Next Instance + when 9 => + inst_ready_out <= '1'; + + -- Memory Flow Control Guard + if (inst_valid_out = '1') then + -- No more Endpoints + if (resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH) = INSTANCE_MEMORY_MAX_ADDRESS) then + inst_data_next.addr <= INSTANCE_MEMORY_MAX_ADDRESS; --No match + -- DONE + inst_stage_next <= IDLE; + else + -- Continue + inst_addr_base_next <= resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH); + inst_cnt_next <= 0; + end if; + end if; + when others => + null; + end case; + when GET_NEXT_INSTANCE => + case (inst_cnt) is + -- GET next Instance + when 0 => + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_NEXT_ADDR_OFFSET; + inst_read <= '1'; + + -- Memory Flow Control Guard + if (inst_ready_in = '1') then + inst_cnt_next <= inst_cnt + 1; + end if; + -- READ Next Instance + when 1 => + inst_ready_out <= '1'; + + -- Memory Flow Control Guard + if (inst_valid_out = '1') then + if (resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH) = INSTANCE_MEMORY_MAX_ADDRESS) then + inst_data_next.addr <= INSTANCE_MEMORY_MAX_ADDRESS; + -- DONE + inst_stage_next <= IDLE; + else + inst_data_next.addr <= resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH); + + -- Get Instance Data + inst_addr_base_next <= resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH); + inst_stage_next <= GET_INSTANCE_DATA; + if check_mask(inst_latch_data.field_flags,IMF_KEY_HASH_FLAG) then + inst_cnt_next <= 0; + elsif check_mask(inst_latch_data.field_flags,IMF_STATUS_FLAG) then + inst_cnt_next <= 4; + elsif check_mask(inst_latch_data.field_flags,IMF_SAMPLE_CNT_FLAG) then inst_cnt_next <= 5; elsif check_mask(inst_latch_data.field_flags,IMF_DISPOSED_CNT_FLAG) then inst_cnt_next <= 6; elsif check_mask(inst_latch_data.field_flags,IMF_NO_WRITERS_CNT_FLAG) then inst_cnt_next <= 7; - elsif (TIME_BASED_FILTER_QOS /= DURATION_ZERO and check_mask(inst_latch_data.field_flags,IMF_IGNORE_DEADLINE_FLAG)) then + elsif check_mask(inst_latch_data.field_flags,IMF_IGNORE_DEADLINE_FLAG) then inst_cnt_next <= 8; elsif check_mask(inst_latch_data.field_flags,IMF_WRITER_BITMAP_FLAG) then inst_cnt_next <= 10; inst_cnt2_next <= 0; else - if check_mask(inst_latch_data.field_flags,IMF_KEY_HASH_FLAG) then - inst_cnt_next <= 11; - else - inst_cnt_next <= 15; - end if; + -- DONE + inst_stage_next <= IDLE; end if; end if; - -- GET Sample Count - when 5 => - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_SAMPLE_CNT_OFFSET; - inst_read <= '1'; - - -- Memory Flow Control Guard - if (inst_ready_in = '1') then - if check_mask(inst_latch_data.field_flags,IMF_DISPOSED_CNT_FLAG) then - inst_cnt_next <= 6; - elsif check_mask(inst_latch_data.field_flags,IMF_NO_WRITERS_CNT_FLAG) then - inst_cnt_next <= 7; - elsif (TIME_BASED_FILTER_QOS /= DURATION_ZERO and check_mask(inst_latch_data.field_flags,IMF_IGNORE_DEADLINE_FLAG)) then - inst_cnt_next <= 8; - elsif check_mask(inst_latch_data.field_flags,IMF_WRITER_BITMAP_FLAG) then - inst_cnt_next <= 10; - inst_cnt2_next <= 0; + end if; + when others => + null; + end case; + when GET_INSTANCE_DATA => + case (inst_cnt) is + -- GET Key Hash 1/4 + when 0 => + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_KEY_HASH_OFFSET; + inst_read <= '1'; + + -- Memory Flow Control Guard + if (inst_ready_in = '1') then + inst_cnt_next <= inst_cnt + 1; + end if; + -- GET Key Hash 2/4 + when 1 => + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_KEY_HASH_OFFSET + 1; + inst_read <= '1'; + + -- Memory Flow Control Guard + if (inst_ready_in = '1') then + inst_cnt_next <= inst_cnt + 1; + end if; + -- GET Key Hash 3/4 + when 2 => + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_KEY_HASH_OFFSET + 2; + inst_read <= '1'; + + -- Memory Flow Control Guard + if (inst_ready_in = '1') then + inst_cnt_next <= inst_cnt + 1; + end if; + -- GET Key Hash 4/4 + when 3 => + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_KEY_HASH_OFFSET + 3; + inst_read <= '1'; + + -- Memory Flow Control Guard + if (inst_ready_in = '1') then + if check_mask(inst_latch_data.field_flags,IMF_STATUS_FLAG) then + inst_cnt_next <= 4; + elsif check_mask(inst_latch_data.field_flags,IMF_SAMPLE_CNT_FLAG) then + inst_cnt_next <= 5; + elsif check_mask(inst_latch_data.field_flags,IMF_DISPOSED_CNT_FLAG) then + inst_cnt_next <= 6; + elsif check_mask(inst_latch_data.field_flags,IMF_NO_WRITERS_CNT_FLAG) then + inst_cnt_next <= 7; + elsif check_mask(inst_latch_data.field_flags,IMF_IGNORE_DEADLINE_FLAG) then + inst_cnt_next <= 8; + elsif check_mask(inst_latch_data.field_flags,IMF_WRITER_BITMAP_FLAG) then + inst_cnt_next <= 10; + inst_cnt2_next <= 0; + else + inst_cnt_next <= 11; + end if; + end if; + -- GET Status Info + when 4 => + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_STATUS_INFO_OFFSET; + inst_read <= '1'; + + -- Memory Flow Control Guard + if (inst_ready_in = '1') then + if check_mask(inst_latch_data.field_flags,IMF_SAMPLE_CNT_FLAG) then + inst_cnt_next <= 5; + elsif check_mask(inst_latch_data.field_flags,IMF_DISPOSED_CNT_FLAG) then + inst_cnt_next <= 6; + elsif check_mask(inst_latch_data.field_flags,IMF_NO_WRITERS_CNT_FLAG) then + inst_cnt_next <= 7; + elsif check_mask(inst_latch_data.field_flags,IMF_IGNORE_DEADLINE_FLAG) then + inst_cnt_next <= 8; + elsif check_mask(inst_latch_data.field_flags,IMF_WRITER_BITMAP_FLAG) then + inst_cnt_next <= 10; + inst_cnt2_next <= 0; + else + if check_mask(inst_latch_data.field_flags,IMF_KEY_HASH_FLAG) then + inst_cnt_next <= 11; else - if check_mask(inst_latch_data.field_flags,IMF_KEY_HASH_FLAG) then - inst_cnt_next <= 11; - elsif check_mask(inst_latch_data.field_flags,IMF_STATUS_FLAG) then - inst_cnt_next <= 15; - else - inst_cnt_next <= 16; - end if; + inst_cnt_next <= 15; end if; end if; - -- GET Disposed Generation Count - when 6 => - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_DISPOSED_GEN_CNT_OFFSET; - inst_read <= '1'; - - -- Memory Flow Control Guard - if (inst_ready_in = '1') then - if check_mask(inst_latch_data.field_flags,IMF_NO_WRITERS_CNT_FLAG) then - inst_cnt_next <= 7; - elsif (TIME_BASED_FILTER_QOS /= DURATION_ZERO and check_mask(inst_latch_data.field_flags,IMF_IGNORE_DEADLINE_FLAG)) then - inst_cnt_next <= 8; - elsif check_mask(inst_latch_data.field_flags,IMF_WRITER_BITMAP_FLAG) then - inst_cnt_next <= 10; - inst_cnt2_next <= 0; + end if; + -- GET Sample Count + when 5 => + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_SAMPLE_CNT_OFFSET; + inst_read <= '1'; + + -- Memory Flow Control Guard + if (inst_ready_in = '1') then + if check_mask(inst_latch_data.field_flags,IMF_DISPOSED_CNT_FLAG) then + inst_cnt_next <= 6; + elsif check_mask(inst_latch_data.field_flags,IMF_NO_WRITERS_CNT_FLAG) then + inst_cnt_next <= 7; + elsif check_mask(inst_latch_data.field_flags,IMF_IGNORE_DEADLINE_FLAG) then + inst_cnt_next <= 8; + elsif check_mask(inst_latch_data.field_flags,IMF_WRITER_BITMAP_FLAG) then + inst_cnt_next <= 10; + inst_cnt2_next <= 0; + else + if check_mask(inst_latch_data.field_flags,IMF_KEY_HASH_FLAG) then + inst_cnt_next <= 11; + elsif check_mask(inst_latch_data.field_flags,IMF_STATUS_FLAG) then + inst_cnt_next <= 15; else - if check_mask(inst_latch_data.field_flags,IMF_KEY_HASH_FLAG) then - inst_cnt_next <= 11; - elsif check_mask(inst_latch_data.field_flags,IMF_STATUS_FLAG) then - inst_cnt_next <= 15; - elsif check_mask(inst_latch_data.field_flags,IMF_SAMPLE_CNT_FLAG) then - inst_cnt_next <= 16; - else - inst_cnt_next <= 17; - end if; + inst_cnt_next <= 16; end if; end if; - -- GET No Writers Generation Count - when 7 => - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_NO_WRITERS_GEN_CNT_OFFSET; - inst_read <= '1'; - - -- Memory Flow Control Guard - if (inst_ready_in = '1') then - if (TIME_BASED_FILTER_QOS /= DURATION_ZERO and check_mask(inst_latch_data.field_flags,IMF_IGNORE_DEADLINE_FLAG)) then - inst_cnt_next <= 8; - elsif check_mask(inst_latch_data.field_flags,IMF_WRITER_BITMAP_FLAG) then - inst_cnt_next <= 10; - inst_cnt2_next <= 0; + end if; + -- GET Disposed Generation Count + when 6 => + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_DISPOSED_GEN_CNT_OFFSET; + inst_read <= '1'; + + -- Memory Flow Control Guard + if (inst_ready_in = '1') then + if check_mask(inst_latch_data.field_flags,IMF_NO_WRITERS_CNT_FLAG) then + inst_cnt_next <= 7; + elsif check_mask(inst_latch_data.field_flags,IMF_IGNORE_DEADLINE_FLAG) then + inst_cnt_next <= 8; + elsif check_mask(inst_latch_data.field_flags,IMF_WRITER_BITMAP_FLAG) then + inst_cnt_next <= 10; + inst_cnt2_next <= 0; + else + if check_mask(inst_latch_data.field_flags,IMF_KEY_HASH_FLAG) then + inst_cnt_next <= 11; + elsif check_mask(inst_latch_data.field_flags,IMF_STATUS_FLAG) then + inst_cnt_next <= 15; + elsif check_mask(inst_latch_data.field_flags,IMF_SAMPLE_CNT_FLAG) then + inst_cnt_next <= 16; else - if check_mask(inst_latch_data.field_flags,IMF_KEY_HASH_FLAG) then - inst_cnt_next <= 11; - elsif check_mask(inst_latch_data.field_flags,IMF_STATUS_FLAG) then - inst_cnt_next <= 15; - elsif check_mask(inst_latch_data.field_flags,IMF_SAMPLE_CNT_FLAG) then - inst_cnt_next <= 16; - elsif check_mask(inst_latch_data.field_flags,IMF_DISPOSED_CNT_FLAG) then - inst_cnt_next <= 17; - else - inst_cnt_next <= 18; - end if; + inst_cnt_next <= 17; end if; end if; - -- GET Ignore Deadline 1/2 - when 8 => - -- Synthesis Guard - if (TIME_BASED_FILTER_QOS /= DURATION_ZERO) then - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_IGNORE_DEADLINE_OFFSET; - inst_read <= '1'; - - -- Memory Flow Control Guard - if (inst_ready_in = '1') then - inst_cnt_next <= inst_cnt + 1; - end if; - end if; - -- GET Ignore Deadline 2/2 - when 9 => - -- Synthesis Guard - if (TIME_BASED_FILTER_QOS /= DURATION_ZERO) then - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_IGNORE_DEADLINE_OFFSET + 1; - inst_read <= '1'; - - -- Memory Flow Control Guard - if (inst_ready_in = '1') then - if check_mask(inst_latch_data.field_flags,IMF_WRITER_BITMAP_FLAG) then - inst_cnt_next <= 10; - inst_cnt2_next <= 0; - else - if check_mask(inst_latch_data.field_flags,IMF_KEY_HASH_FLAG) then - inst_cnt_next <= 11; - elsif check_mask(inst_latch_data.field_flags,IMF_STATUS_FLAG) then - inst_cnt_next <= 15; - elsif check_mask(inst_latch_data.field_flags,IMF_SAMPLE_CNT_FLAG) then - inst_cnt_next <= 16; - elsif check_mask(inst_latch_data.field_flags,IMF_DISPOSED_CNT_FLAG) then - inst_cnt_next <= 17; - elsif check_mask(inst_latch_data.field_flags,IMF_NO_WRITERS_CNT_FLAG) then - inst_cnt_next <= 18; - else - inst_cnt_next <= 19; - end if; - end if; - end if; - end if; - -- GET Writer Bitmap - when 10 => - -- XXX: Possible Worst case Path (2 Additions in same clock) - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_WRITER_BITMAP_OFFSET + inst_cnt2; - inst_read <= '1'; - - -- Memory Flow Control Guard - if (inst_ready_in = '1') then - -- Exit Condition - if (inst_cnt2 = WRITER_BITMAP_ARRAY_TYPE'length-1) then - if check_mask(inst_latch_data.field_flags,IMF_KEY_HASH_FLAG) then - inst_cnt_next <= 11; - elsif check_mask(inst_latch_data.field_flags,IMF_STATUS_FLAG) then - inst_cnt_next <= 15; - elsif check_mask(inst_latch_data.field_flags,IMF_SAMPLE_CNT_FLAG) then - inst_cnt_next <= 16; - elsif check_mask(inst_latch_data.field_flags,IMF_DISPOSED_CNT_FLAG) then - inst_cnt_next <= 17; - elsif check_mask(inst_latch_data.field_flags,IMF_NO_WRITERS_CNT_FLAG) then - inst_cnt_next <= 18; - elsif (TIME_BASED_FILTER_QOS /= DURATION_ZERO and check_mask(inst_latch_data.field_flags,IMF_IGNORE_DEADLINE_FLAG)) then - inst_cnt_next <= 19; - else - inst_cnt_next <= 21; - inst_cnt2_next <= 0; - end if; + end if; + -- GET No Writers Generation Count + when 7 => + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_NO_WRITERS_GEN_CNT_OFFSET; + inst_read <= '1'; + + -- Memory Flow Control Guard + if (inst_ready_in = '1') then + if check_mask(inst_latch_data.field_flags,IMF_IGNORE_DEADLINE_FLAG) then + inst_cnt_next <= 8; + elsif check_mask(inst_latch_data.field_flags,IMF_WRITER_BITMAP_FLAG) then + inst_cnt_next <= 10; + inst_cnt2_next <= 0; + else + if check_mask(inst_latch_data.field_flags,IMF_KEY_HASH_FLAG) then + inst_cnt_next <= 11; + elsif check_mask(inst_latch_data.field_flags,IMF_STATUS_FLAG) then + inst_cnt_next <= 15; + elsif check_mask(inst_latch_data.field_flags,IMF_SAMPLE_CNT_FLAG) then + inst_cnt_next <= 16; + elsif check_mask(inst_latch_data.field_flags,IMF_DISPOSED_CNT_FLAG) then + inst_cnt_next <= 17; else - inst_cnt2_next <= inst_cnt2 + 1; + inst_cnt_next <= 18; end if; end if; - -- READ Key Hash 1/4 - when 11 => - inst_ready_out <= '1'; - - -- Memory Flow Control Guard - if (inst_valid_out = '1') then - inst_data_next.key_hash(0) <= inst_read_data; - inst_cnt_next <= inst_cnt + 1; - end if; - -- READ Key Hash 2/4 - when 12 => - inst_ready_out <= '1'; - - -- Memory Flow Control Guard - if (inst_valid_out = '1') then - inst_data_next.key_hash(1) <= inst_read_data; - inst_cnt_next <= inst_cnt + 1; - end if; - -- READ Key Hash 3/4 - when 13 => - inst_ready_out <= '1'; - - -- Memory Flow Control Guard - if (inst_valid_out = '1') then - inst_data_next.key_hash(2) <= inst_read_data; - inst_cnt_next <= inst_cnt + 1; - end if; - -- READ Key Hash 4/4 - when 14 => - inst_ready_out <= '1'; - - -- Memory Flow Control Guard - if (inst_valid_out = '1') then - inst_data_next.key_hash(3) <= inst_read_data; - inst_data_next.field_flags <= inst_data.field_flags or IMF_KEY_HASH_FLAG; - - if check_mask(inst_latch_data.field_flags,IMF_STATUS_FLAG) then + end if; + -- GET Ignore Deadline 1/2 + when 8 => + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_IGNORE_DEADLINE_OFFSET; + inst_read <= '1'; + + -- Memory Flow Control Guard + if (inst_ready_in = '1') then + inst_cnt_next <= inst_cnt + 1; + end if; + -- GET Ignore Deadline 2/2 + when 9 => + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_IGNORE_DEADLINE_OFFSET + 1; + inst_read <= '1'; + + -- Memory Flow Control Guard + if (inst_ready_in = '1') then + if check_mask(inst_latch_data.field_flags,IMF_WRITER_BITMAP_FLAG) then + inst_cnt_next <= 10; + inst_cnt2_next <= 0; + else + if check_mask(inst_latch_data.field_flags,IMF_KEY_HASH_FLAG) then + inst_cnt_next <= 11; + elsif check_mask(inst_latch_data.field_flags,IMF_STATUS_FLAG) then inst_cnt_next <= 15; elsif check_mask(inst_latch_data.field_flags,IMF_SAMPLE_CNT_FLAG) then inst_cnt_next <= 16; @@ -5696,855 +5585,901 @@ begin inst_cnt_next <= 17; elsif check_mask(inst_latch_data.field_flags,IMF_NO_WRITERS_CNT_FLAG) then inst_cnt_next <= 18; - elsif (TIME_BASED_FILTER_QOS /= DURATION_ZERO and check_mask(inst_latch_data.field_flags,IMF_IGNORE_DEADLINE_FLAG)) then - inst_cnt_next <= 19; - elsif check_mask(inst_latch_data.field_flags,IMF_WRITER_BITMAP_FLAG) then - inst_cnt_next <= 21; - inst_cnt2_next <= 0; else - -- DONE - inst_stage_next <= IDLE; + inst_cnt_next <= 19; end if; end if; - -- READ Status Info - when 15 => - inst_ready_out <= '1'; - - -- Memory Flow Control Guard - if (inst_valid_out = '1') then - inst_data_next.status_info <= inst_read_data; - inst_data_next.field_flags <= inst_data.field_flags or IMF_STATUS_FLAG; - - if check_mask(inst_latch_data.field_flags,IMF_SAMPLE_CNT_FLAG) then + end if; + -- GET Writer Bitmap + when 10 => + -- XXX: Possible Worst case Path (2 Additions in same clock) + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_WRITER_BITMAP_OFFSET + inst_cnt2; + inst_read <= '1'; + + -- Memory Flow Control Guard + if (inst_ready_in = '1') then + -- Exit Condition + if (inst_cnt2 = WRITER_BITMAP_ARRAY_TYPE'length-1) then + if check_mask(inst_latch_data.field_flags,IMF_KEY_HASH_FLAG) then + inst_cnt_next <= 11; + elsif check_mask(inst_latch_data.field_flags,IMF_STATUS_FLAG) then + inst_cnt_next <= 15; + elsif check_mask(inst_latch_data.field_flags,IMF_SAMPLE_CNT_FLAG) then inst_cnt_next <= 16; elsif check_mask(inst_latch_data.field_flags,IMF_DISPOSED_CNT_FLAG) then inst_cnt_next <= 17; elsif check_mask(inst_latch_data.field_flags,IMF_NO_WRITERS_CNT_FLAG) then inst_cnt_next <= 18; - elsif (TIME_BASED_FILTER_QOS /= DURATION_ZERO and check_mask(inst_latch_data.field_flags,IMF_IGNORE_DEADLINE_FLAG)) then + elsif check_mask(inst_latch_data.field_flags,IMF_IGNORE_DEADLINE_FLAG) then inst_cnt_next <= 19; - elsif check_mask(inst_latch_data.field_flags,IMF_WRITER_BITMAP_FLAG) then + else inst_cnt_next <= 21; inst_cnt2_next <= 0; - else - -- DONE - inst_stage_next <= IDLE; end if; + else + inst_cnt2_next <= inst_cnt2 + 1; end if; - -- READ Sample Count - when 16 => - inst_ready_out <= '1'; - - -- Memory Flow Control Guard - if (inst_valid_out = '1') then - inst_data_next.sample_cnt <= unsigned(inst_read_data); - inst_data_next.field_flags <= inst_data.field_flags or IMF_SAMPLE_CNT_FLAG; - - if check_mask(inst_latch_data.field_flags,IMF_DISPOSED_CNT_FLAG) then - inst_cnt_next <= 17; - elsif check_mask(inst_latch_data.field_flags,IMF_NO_WRITERS_CNT_FLAG) then - inst_cnt_next <= 18; - elsif (TIME_BASED_FILTER_QOS /= DURATION_ZERO and check_mask(inst_latch_data.field_flags,IMF_IGNORE_DEADLINE_FLAG)) then - inst_cnt_next <= 19; - elsif check_mask(inst_latch_data.field_flags,IMF_WRITER_BITMAP_FLAG) then - inst_cnt_next <= 21; - inst_cnt2_next <= 0; - else - -- DONE - inst_stage_next <= IDLE; - end if; - end if; - -- READ Disposed Generation Count - when 17 => - inst_ready_out <= '1'; - - -- Memory Flow Control Guard - if (inst_valid_out = '1') then - inst_data_next.disposed_gen_cnt <= unsigned(inst_read_data); - inst_data_next.field_flags <= inst_data.field_flags or IMF_DISPOSED_CNT_FLAG; - - if check_mask(inst_latch_data.field_flags,IMF_NO_WRITERS_CNT_FLAG) then - inst_cnt_next <= 18; - elsif (TIME_BASED_FILTER_QOS /= DURATION_ZERO and check_mask(inst_latch_data.field_flags,IMF_IGNORE_DEADLINE_FLAG)) then - inst_cnt_next <= 19; - elsif check_mask(inst_latch_data.field_flags,IMF_WRITER_BITMAP_FLAG) then - inst_cnt_next <= 21; - inst_cnt2_next <= 0; - else - -- DONE - inst_stage_next <= IDLE; - end if; - end if; - -- READ No Writers Generation Count - when 18 => - inst_ready_out <= '1'; - - -- Memory Flow Control Guard - if (inst_valid_out = '1') then - inst_data_next.no_writers_gen_cnt <= unsigned(inst_read_data); - inst_data_next.field_flags <= inst_data.field_flags or IMF_NO_WRITERS_CNT_FLAG; - - if (TIME_BASED_FILTER_QOS /= DURATION_ZERO and check_mask(inst_latch_data.field_flags,IMF_IGNORE_DEADLINE_FLAG)) then - inst_cnt_next <= 19; - elsif check_mask(inst_latch_data.field_flags,IMF_WRITER_BITMAP_FLAG) then - inst_cnt_next <= 21; - inst_cnt2_next <= 0; - else - -- DONE - inst_stage_next <= IDLE; - end if; - end if; - -- READ Ignore Deadline 1/2 - when 19 => - inst_ready_out <= '1'; - - -- Memory Flow Control Guard - if (inst_valid_out = '1') then - inst_data_next.ignore_deadline(0) <= unsigned(inst_read_data); - - inst_cnt_next <= inst_cnt + 1; - end if; - -- READ Ignore Deadline 2/2 - when 20 => - inst_ready_out <= '1'; - - -- Memory Flow Control Guard - if (inst_valid_out = '1') then - inst_data_next.ignore_deadline(1) <= unsigned(inst_read_data); - inst_data_next.field_flags <= inst_data.field_flags or IMF_IGNORE_DEADLINE_FLAG; - - if check_mask(inst_latch_data.field_flags,IMF_WRITER_BITMAP_FLAG) then - inst_cnt_next <= 21; - inst_cnt2_next <= 0; - else - -- DONE - inst_stage_next <= IDLE; - end if; - end if; - -- READ Writer Bitamp - when 21 => - inst_ready_out <= '1'; - - -- Memory Flow Control Guard - if (inst_valid_out = '1') then - inst_data_next.writer_bitmap(inst_cnt2) <= inst_read_data; - -- Exit Condition - if (inst_cnt2 = WRITER_BITMAP_ARRAY_TYPE'length-1) then - inst_data_next.field_flags <= inst_data.field_flags or IMF_WRITER_BITMAP_FLAG; - -- DONE - inst_stage_next <= IDLE; - else - inst_cnt2_next <= inst_cnt2 + 1; - end if; - end if; - end case; - when FIND_POS => - -- NOTE: Instances are inserted in KEY_HASH numerical order. - - case (inst_cnt) is - -- GET Key Hash 1/4 - when 0 => - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_KEY_HASH_OFFSET; - inst_read <= '1'; - - -- Memory Flow Control Guard - if (inst_ready_in = '1') then - inst_cnt_next <= inst_cnt + 1; - end if; - -- GET Key Hash 2/4 - when 1 => - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_KEY_HASH_OFFSET + 1; - inst_read <= '1'; - - -- Memory Flow Control Guard - if (inst_ready_in = '1') then - inst_cnt_next <= inst_cnt + 1; - end if; - -- GET Key Hash 3/4 - when 2 => - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_KEY_HASH_OFFSET + 2; - inst_read <= '1'; - - -- Memory Flow Control Guard - if (inst_ready_in = '1') then - inst_cnt_next <= inst_cnt + 1; - end if; - -- GET Key Hash 4/4 - when 3 => - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_KEY_HASH_OFFSET + 3; - inst_read <= '1'; - - -- Memory Flow Control Guard - if (inst_ready_in = '1') then - inst_cnt_next <= inst_cnt + 1; - end if; - -- READ Key Hash 1/4 - when 4 => - inst_ready_out <= '1'; - - -- Memory Flow Control Guard - if (inst_valid_out = '1') then - -- Found Position (Before Current Instance) - if (inst_latch_data.key_hash(0) < inst_read_data) then - inst_abort_read <= '1'; - inst_addr_latch_next <= inst_addr_base; - inst_stage_next <= INSERT_INSTANCE; - inst_cnt_next <= 0; - -- BIGGER-THAN - elsif (inst_latch_data.key_hash(0) /= inst_read_data) then - inst_abort_read <= '1'; - -- Continue - inst_cnt_next <= 8; -- GET NEXT INSTANCE - else - inst_cnt_next <= inst_cnt + 1; - end if; - end if; - -- READ Key Hash 2/4 - when 5 => - inst_ready_out <= '1'; - - -- Memory Flow Control Guard - if (inst_valid_out = '1') then - -- Found Position (Before Current Instance) - if (inst_latch_data.key_hash(1) < inst_read_data) then - inst_abort_read <= '1'; - inst_addr_latch_next <= inst_addr_base; - inst_stage_next <= INSERT_INSTANCE; - inst_cnt_next <= 0; - -- BIGGER-THAN - elsif (inst_latch_data.key_hash(1) /= inst_read_data) then - inst_abort_read <= '1'; - -- Continue - inst_cnt_next <= 8; -- GET NEXT INSTANCE - else - inst_cnt_next <= inst_cnt + 1; - end if; - end if; - -- READ Key Hash 3/4 - when 6 => - inst_ready_out <= '1'; - - -- Memory Flow Control Guard - if (inst_valid_out = '1') then - -- Found Position (Before Current Instance) - if (inst_latch_data.key_hash(2) < inst_read_data) then - inst_abort_read <= '1'; - inst_addr_latch_next <= inst_addr_base; - inst_stage_next <= INSERT_INSTANCE; - inst_cnt_next <= 0; - -- BIGGER-THAN - elsif (inst_latch_data.key_hash(2) /= inst_read_data) then - inst_abort_read <= '1'; - -- Continue - inst_cnt_next <= 8; -- GET NEXT INSTANCE - else - inst_cnt_next <= inst_cnt + 1; - end if; - end if; - -- Key Hash 4/4 - when 7 => - inst_ready_out <= '1'; - - -- Memory Flow Control Guard - if (inst_valid_out = '1') then - -- Found Position (Before Current Instance) - if (inst_latch_data.key_hash(3) < inst_read_data) then - inst_abort_read <= '1'; - inst_addr_latch_next <= inst_addr_base; - inst_stage_next <= INSERT_INSTANCE; - inst_cnt_next <= 0; - else - assert (inst_latch_data.key_hash(3) /= inst_read_data) report "Duplicate Instance Detected" severity FAILURE; - - -- Continue - inst_cnt_next <= inst_cnt + 1; - end if; - end if; - -- GET Next Instance - when 8 => - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_NEXT_ADDR_OFFSET; - inst_read <= '1'; - - -- Memory Flow Control Guard - if (inst_ready_in = '1') then - inst_cnt_next <= inst_cnt + 1; - end if; - -- READ Next Instance - when 9 => - inst_ready_out <= '1'; - - -- Memory Flow Control Guard - if (inst_valid_out = '1') then - -- No more Endpoints - if (resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH) = INSTANCE_MEMORY_MAX_ADDRESS) then - inst_addr_latch_next <= INSTANCE_MEMORY_MAX_ADDRESS; - inst_stage_next <= INSERT_INSTANCE; - inst_cnt_next <= 0; - else - -- Continue - inst_addr_base_next <= resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH); - inst_cnt_next <= 0; - end if; - end if; - when others => - null; - end case; - when INSERT_INSTANCE => - case (inst_cnt) is - -- GET NEXT ADDR - when 0 => - inst_valid_in <= '1'; - inst_addr <= inst_empty_head + IMF_NEXT_ADDR_OFFSET; - inst_read <= '1'; - - -- Memory Flow Control Guard - if (inst_ready_in = '1') then - inst_cnt_next <= inst_cnt + 1; - end if; - -- SET NEXT ADDR - when 1 => - inst_valid_in <= '1'; - inst_addr <= inst_empty_head + IMF_NEXT_ADDR_OFFSET; - inst_write_data <= std_logic_vector(resize(inst_addr_latch,WORD_WIDTH)); - - -- Memory Flow Control Guard - if (inst_ready_in = '1') then - inst_cnt_next <= inst_cnt + 1; - end if; - -- READ NEXT ADDR - when 2 => - inst_ready_out <= '1'; - - -- Memory Flow Control Guard - if (inst_valid_out = '1') then - -- Fix Empty List Head - inst_empty_head_next <= resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH); - inst_addr_base_next <= inst_empty_head; - - -- No Next Instance (Occupied Tail) - if (inst_addr_latch = INSTANCE_MEMORY_MAX_ADDRESS) then - inst_cnt_next <= inst_cnt + 4; -- SET PREV ADDR - -- NOTE: inst_addr_base contains the current occupied tail - inst_addr_latch_next <= inst_addr_base; - else - inst_cnt_next <= inst_cnt + 1; - end if; - end if; - -- GET PREV ADDR (Next Instance) - when 3 => - inst_valid_in <= '1'; - inst_addr <= inst_addr_latch + IMF_PREV_ADDR_OFFSET; - inst_read <= '1'; - - -- Memory Flow Control Guard - if (inst_ready_in = '1') then - inst_cnt_next <= inst_cnt + 1; - end if; - -- SET PREV ADDR (Next Instance) - when 4 => - inst_valid_in <= '1'; - inst_addr <= inst_addr_latch + IMF_PREV_ADDR_OFFSET; - inst_write_data <= std_logic_vector(resize(inst_addr_base,WORD_WIDTH)); - - -- Memory Flow Control Guard - if (inst_ready_in = '1') then - inst_cnt_next <= inst_cnt + 1; - end if; - -- READ PREV ADDR - when 5 => - inst_ready_out <= '1'; - - -- Memory Flow Control Guard - if (inst_valid_out = '1') then - inst_addr_latch_next <= resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH); - - inst_cnt_next <= inst_cnt + 1; - end if; - -- SET PREV ADDR - when 6 => - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_PREV_ADDR_OFFSET; - inst_write_data <= std_logic_vector(resize(inst_addr_latch,WORD_WIDTH)); - - -- Memory Flow Control Guard - if (inst_ready_in = '1') then - -- No Previous Instance (Occupied Head) - if (inst_addr_latch = INSTANCE_MEMORY_MAX_ADDRESS) then - inst_cnt_next <= inst_cnt + 2; -- SET Key Hash 1/4 - inst_occupied_head_next <= inst_addr_base; - else - inst_cnt_next <= inst_cnt + 1; - end if; - end if; - -- SET NEXT ADDR (Previous Instance) - when 7 => - inst_valid_in <= '1'; - inst_addr <= inst_addr_latch + IMF_NEXT_ADDR_OFFSET; - inst_write_data <= std_logic_vector(resize(inst_addr_base,WORD_WIDTH)); - - -- Memory Flow Control Guard - if (inst_ready_in = '1') then - inst_cnt_next <= inst_cnt + 1; - end if; - -- SET Key Hash 1/4 - when 8 => - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_KEY_HASH_OFFSET; - inst_write_data <= inst_latch_data.key_hash(0); - inst_data_next.key_hash(0) <= inst_latch_data.key_hash(0); - - -- Memory Flow Control Guard - if (inst_ready_in = '1') then - inst_cnt_next <= inst_cnt + 1; - end if; - -- SET Key Hash 2/4 - when 9 => - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_KEY_HASH_OFFSET + 1; - inst_write_data <= inst_latch_data.key_hash(1); - inst_data_next.key_hash(1) <= inst_latch_data.key_hash(1); - - -- Memory Flow Control Guard - if (inst_ready_in = '1') then - inst_cnt_next <= inst_cnt + 1; - end if; - -- SET Key Hash 3/4 - when 10 => - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_KEY_HASH_OFFSET + 2; - inst_write_data <= inst_latch_data.key_hash(2); - inst_data_next.key_hash(2) <= inst_latch_data.key_hash(2); - - -- Memory Flow Control Guard - if (inst_ready_in = '1') then - inst_cnt_next <= inst_cnt + 1; - end if; - -- SET Key Hash 4/4 - when 11 => - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_KEY_HASH_OFFSET + 3; - inst_write_data <= inst_latch_data.key_hash(3); - inst_data_next.key_hash(3) <= inst_latch_data.key_hash(3); + end if; + -- READ Key Hash 1/4 + when 11 => + inst_ready_out <= '1'; + + -- Memory Flow Control Guard + if (inst_valid_out = '1') then + inst_data_next.key_hash(0) <= inst_read_data; + inst_cnt_next <= inst_cnt + 1; + end if; + -- READ Key Hash 2/4 + when 12 => + inst_ready_out <= '1'; + + -- Memory Flow Control Guard + if (inst_valid_out = '1') then + inst_data_next.key_hash(1) <= inst_read_data; + inst_cnt_next <= inst_cnt + 1; + end if; + -- READ Key Hash 3/4 + when 13 => + inst_ready_out <= '1'; + + -- Memory Flow Control Guard + if (inst_valid_out = '1') then + inst_data_next.key_hash(2) <= inst_read_data; + inst_cnt_next <= inst_cnt + 1; + end if; + -- READ Key Hash 4/4 + when 14 => + inst_ready_out <= '1'; + + -- Memory Flow Control Guard + if (inst_valid_out = '1') then + inst_data_next.key_hash(3) <= inst_read_data; inst_data_next.field_flags <= inst_data.field_flags or IMF_KEY_HASH_FLAG; - -- Memory Flow Control Guard - if (inst_ready_in = '1') then - inst_cnt_next <= inst_cnt + 1; + if check_mask(inst_latch_data.field_flags,IMF_STATUS_FLAG) then + inst_cnt_next <= 15; + elsif check_mask(inst_latch_data.field_flags,IMF_SAMPLE_CNT_FLAG) then + inst_cnt_next <= 16; + elsif check_mask(inst_latch_data.field_flags,IMF_DISPOSED_CNT_FLAG) then + inst_cnt_next <= 17; + elsif check_mask(inst_latch_data.field_flags,IMF_NO_WRITERS_CNT_FLAG) then + inst_cnt_next <= 18; + elsif check_mask(inst_latch_data.field_flags,IMF_IGNORE_DEADLINE_FLAG) then + inst_cnt_next <= 19; + elsif check_mask(inst_latch_data.field_flags,IMF_WRITER_BITMAP_FLAG) then + inst_cnt_next <= 21; + inst_cnt2_next <= 0; + else + -- DONE + inst_stage_next <= IDLE; end if; - -- SET Status Info - when 12 => - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_STATUS_INFO_OFFSET; - inst_write_data <= inst_latch_data.status_info; - inst_data_next.status_info <= inst_latch_data.status_info; + end if; + -- READ Status Info + when 15 => + inst_ready_out <= '1'; + + -- Memory Flow Control Guard + if (inst_valid_out = '1') then + inst_data_next.status_info <= inst_read_data; inst_data_next.field_flags <= inst_data.field_flags or IMF_STATUS_FLAG; - -- Memory Flow Control Guard - if (inst_ready_in = '1') then - inst_cnt_next <= inst_cnt + 1; + if check_mask(inst_latch_data.field_flags,IMF_SAMPLE_CNT_FLAG) then + inst_cnt_next <= 16; + elsif check_mask(inst_latch_data.field_flags,IMF_DISPOSED_CNT_FLAG) then + inst_cnt_next <= 17; + elsif check_mask(inst_latch_data.field_flags,IMF_NO_WRITERS_CNT_FLAG) then + inst_cnt_next <= 18; + elsif check_mask(inst_latch_data.field_flags,IMF_IGNORE_DEADLINE_FLAG) then + inst_cnt_next <= 19; + elsif check_mask(inst_latch_data.field_flags,IMF_WRITER_BITMAP_FLAG) then + inst_cnt_next <= 21; + inst_cnt2_next <= 0; + else + -- DONE + inst_stage_next <= IDLE; end if; - -- SET Sample Count - when 13 => - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_SAMPLE_CNT_OFFSET; - inst_write_data <= std_logic_vector(inst_latch_data.sample_cnt); - inst_data_next.sample_cnt <= inst_latch_data.sample_cnt; + end if; + -- READ Sample Count + when 16 => + inst_ready_out <= '1'; + + -- Memory Flow Control Guard + if (inst_valid_out = '1') then + inst_data_next.sample_cnt <= unsigned(inst_read_data); inst_data_next.field_flags <= inst_data.field_flags or IMF_SAMPLE_CNT_FLAG; - -- Memory Flow Control Guard - if (inst_ready_in = '1') then + if check_mask(inst_latch_data.field_flags,IMF_DISPOSED_CNT_FLAG) then + inst_cnt_next <= 17; + elsif check_mask(inst_latch_data.field_flags,IMF_NO_WRITERS_CNT_FLAG) then + inst_cnt_next <= 18; + elsif check_mask(inst_latch_data.field_flags,IMF_IGNORE_DEADLINE_FLAG) then + inst_cnt_next <= 19; + elsif check_mask(inst_latch_data.field_flags,IMF_WRITER_BITMAP_FLAG) then + inst_cnt_next <= 21; + inst_cnt2_next <= 0; + else + -- DONE + inst_stage_next <= IDLE; + end if; + end if; + -- READ Disposed Generation Count + when 17 => + inst_ready_out <= '1'; + + -- Memory Flow Control Guard + if (inst_valid_out = '1') then + inst_data_next.disposed_gen_cnt <= unsigned(inst_read_data); + inst_data_next.field_flags <= inst_data.field_flags or IMF_DISPOSED_CNT_FLAG; + + if check_mask(inst_latch_data.field_flags,IMF_NO_WRITERS_CNT_FLAG) then + inst_cnt_next <= 18; + elsif check_mask(inst_latch_data.field_flags,IMF_IGNORE_DEADLINE_FLAG) then + inst_cnt_next <= 19; + elsif check_mask(inst_latch_data.field_flags,IMF_WRITER_BITMAP_FLAG) then + inst_cnt_next <= 21; + inst_cnt2_next <= 0; + else + -- DONE + inst_stage_next <= IDLE; + end if; + end if; + -- READ No Writers Generation Count + when 18 => + inst_ready_out <= '1'; + + -- Memory Flow Control Guard + if (inst_valid_out = '1') then + inst_data_next.no_writers_gen_cnt <= unsigned(inst_read_data); + inst_data_next.field_flags <= inst_data.field_flags or IMF_NO_WRITERS_CNT_FLAG; + + if check_mask(inst_latch_data.field_flags,IMF_IGNORE_DEADLINE_FLAG) then + inst_cnt_next <= 19; + elsif check_mask(inst_latch_data.field_flags,IMF_WRITER_BITMAP_FLAG) then + inst_cnt_next <= 21; + inst_cnt2_next <= 0; + else + -- DONE + inst_stage_next <= IDLE; + end if; + end if; + -- READ Ignore Deadline 1/2 + when 19 => + inst_ready_out <= '1'; + + -- Memory Flow Control Guard + if (inst_valid_out = '1') then + inst_data_next.ignore_deadline(0) <= unsigned(inst_read_data); + + inst_cnt_next <= inst_cnt + 1; + end if; + -- READ Ignore Deadline 2/2 + when 20 => + inst_ready_out <= '1'; + + -- Memory Flow Control Guard + if (inst_valid_out = '1') then + inst_data_next.ignore_deadline(1) <= unsigned(inst_read_data); + inst_data_next.field_flags <= inst_data.field_flags or IMF_IGNORE_DEADLINE_FLAG; + + if check_mask(inst_latch_data.field_flags,IMF_WRITER_BITMAP_FLAG) then + inst_cnt_next <= 21; + inst_cnt2_next <= 0; + else + -- DONE + inst_stage_next <= IDLE; + end if; + end if; + -- READ Writer Bitamp + when 21 => + inst_ready_out <= '1'; + + -- Memory Flow Control Guard + if (inst_valid_out = '1') then + inst_data_next.writer_bitmap(inst_cnt2) <= inst_read_data; + -- Exit Condition + if (inst_cnt2 = WRITER_BITMAP_ARRAY_TYPE'length-1) then + inst_data_next.field_flags <= inst_data.field_flags or IMF_WRITER_BITMAP_FLAG; + -- DONE + inst_stage_next <= IDLE; + else + inst_cnt2_next <= inst_cnt2 + 1; + end if; + end if; + end case; + when FIND_POS => + -- NOTE: Instances are inserted in KEY_HASH numerical order. + + case (inst_cnt) is + -- GET Key Hash 1/4 + when 0 => + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_KEY_HASH_OFFSET; + inst_read <= '1'; + + -- Memory Flow Control Guard + if (inst_ready_in = '1') then + inst_cnt_next <= inst_cnt + 1; + end if; + -- GET Key Hash 2/4 + when 1 => + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_KEY_HASH_OFFSET + 1; + inst_read <= '1'; + + -- Memory Flow Control Guard + if (inst_ready_in = '1') then + inst_cnt_next <= inst_cnt + 1; + end if; + -- GET Key Hash 3/4 + when 2 => + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_KEY_HASH_OFFSET + 2; + inst_read <= '1'; + + -- Memory Flow Control Guard + if (inst_ready_in = '1') then + inst_cnt_next <= inst_cnt + 1; + end if; + -- GET Key Hash 4/4 + when 3 => + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_KEY_HASH_OFFSET + 3; + inst_read <= '1'; + + -- Memory Flow Control Guard + if (inst_ready_in = '1') then + inst_cnt_next <= inst_cnt + 1; + end if; + -- READ Key Hash 1/4 + when 4 => + inst_ready_out <= '1'; + + -- Memory Flow Control Guard + if (inst_valid_out = '1') then + -- Found Position (Before Current Instance) + if (inst_latch_data.key_hash(0) < inst_read_data) then + inst_abort_read <= '1'; + inst_addr_latch_next <= inst_addr_base; + inst_stage_next <= INSERT_INSTANCE; + inst_cnt_next <= 0; + -- BIGGER-THAN + elsif (inst_latch_data.key_hash(0) /= inst_read_data) then + inst_abort_read <= '1'; + -- Continue + inst_cnt_next <= 8; -- GET NEXT INSTANCE + else inst_cnt_next <= inst_cnt + 1; end if; - -- SET Disposed Generation Count - when 14 => - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_DISPOSED_GEN_CNT_OFFSET; - inst_write_data <= (others => '0'); - inst_data_next.disposed_gen_cnt <= (others => '0'); - inst_data_next.field_flags <= inst_data.field_flags or IMF_DISPOSED_CNT_FLAG; - - -- Memory Flow Control Guard - if (inst_ready_in = '1') then + end if; + -- READ Key Hash 2/4 + when 5 => + inst_ready_out <= '1'; + + -- Memory Flow Control Guard + if (inst_valid_out = '1') then + -- Found Position (Before Current Instance) + if (inst_latch_data.key_hash(1) < inst_read_data) then + inst_abort_read <= '1'; + inst_addr_latch_next <= inst_addr_base; + inst_stage_next <= INSERT_INSTANCE; + inst_cnt_next <= 0; + -- BIGGER-THAN + elsif (inst_latch_data.key_hash(1) /= inst_read_data) then + inst_abort_read <= '1'; + -- Continue + inst_cnt_next <= 8; -- GET NEXT INSTANCE + else inst_cnt_next <= inst_cnt + 1; end if; - -- SET No Writers Generation Count - when 15 => - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_NO_WRITERS_GEN_CNT_OFFSET; - inst_write_data <= (others => '0'); - inst_data_next.no_writers_gen_cnt <= (others => '0'); - inst_data_next.field_flags <= inst_data.field_flags or IMF_NO_WRITERS_CNT_FLAG; - - -- Memory Flow Control Guard - if (inst_ready_in = '1') then - if (TIME_BASED_FILTER_QOS /= DURATION_ZERO) then - inst_cnt_next <= inst_cnt + 1; - else - inst_cnt_next <= inst_cnt + 3; - inst_cnt2_next <= 0; - end if; + end if; + -- READ Key Hash 3/4 + when 6 => + inst_ready_out <= '1'; + + -- Memory Flow Control Guard + if (inst_valid_out = '1') then + -- Found Position (Before Current Instance) + if (inst_latch_data.key_hash(2) < inst_read_data) then + inst_abort_read <= '1'; + inst_addr_latch_next <= inst_addr_base; + inst_stage_next <= INSERT_INSTANCE; + inst_cnt_next <= 0; + -- BIGGER-THAN + elsif (inst_latch_data.key_hash(2) /= inst_read_data) then + inst_abort_read <= '1'; + -- Continue + inst_cnt_next <= 8; -- GET NEXT INSTANCE + else + inst_cnt_next <= inst_cnt + 1; end if; - -- SET Ignore Deadline 1/2 - when 16 => - -- Synthesis Guard - if (TIME_BASED_FILTER_QOS /= DURATION_ZERO) then - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_IGNORE_DEADLINE_OFFSET; - inst_write_data <= std_logic_vector(inst_latch_data.ignore_deadline(0)); - inst_data_next.ignore_deadline(0) <= inst_latch_data.ignore_deadline(0); + end if; + -- Key Hash 4/4 + when 7 => + inst_ready_out <= '1'; + + -- Memory Flow Control Guard + if (inst_valid_out = '1') then + -- Found Position (Before Current Instance) + if (inst_latch_data.key_hash(3) < inst_read_data) then + inst_abort_read <= '1'; + inst_addr_latch_next <= inst_addr_base; + inst_stage_next <= INSERT_INSTANCE; + inst_cnt_next <= 0; + else + assert (inst_latch_data.key_hash(3) /= inst_read_data) report "Duplicate Instance Detected" severity FAILURE; - -- Memory Flow Control Guard - if (inst_ready_in = '1') then - inst_cnt_next <= inst_cnt + 1; - end if; + -- Continue + inst_cnt_next <= inst_cnt + 1; end if; - -- SET Ignore Deadline 2/2 - when 17 => - -- Synthesis Guard - if (TIME_BASED_FILTER_QOS /= DURATION_ZERO) then - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_IGNORE_DEADLINE_OFFSET + 1; - inst_write_data <= std_logic_vector(inst_latch_data.ignore_deadline(1)); - inst_data_next.ignore_deadline(1) <= inst_latch_data.ignore_deadline(1); - inst_data_next.field_flags <= inst_data.field_flags or IMF_IGNORE_DEADLINE_FLAG; - - -- Memory Flow Control Guard - if (inst_ready_in = '1') then - inst_cnt_next <= inst_cnt + 1; - inst_cnt2_next <= 0; - end if; + end if; + -- GET Next Instance + when 8 => + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_NEXT_ADDR_OFFSET; + inst_read <= '1'; + + -- Memory Flow Control Guard + if (inst_ready_in = '1') then + inst_cnt_next <= inst_cnt + 1; + end if; + -- READ Next Instance + when 9 => + inst_ready_out <= '1'; + + -- Memory Flow Control Guard + if (inst_valid_out = '1') then + -- No more Endpoints + if (resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH) = INSTANCE_MEMORY_MAX_ADDRESS) then + inst_addr_latch_next <= INSTANCE_MEMORY_MAX_ADDRESS; + inst_stage_next <= INSERT_INSTANCE; + inst_cnt_next <= 0; + else + -- Continue + inst_addr_base_next <= resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH); + inst_cnt_next <= 0; end if; - -- SET Writer Bitmap - when 18 => - -- XXX: Possible Worst case Path (2 Additions in same clock) - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_WRITER_BITMAP_OFFSET + inst_cnt2; - inst_write_data <= inst_latch_data.writer_bitmap(inst_cnt2); - inst_data_next.writer_bitmap <= inst_latch_data.writer_bitmap; + end if; + when others => + null; + end case; + when INSERT_INSTANCE => + case (inst_cnt) is + -- GET NEXT ADDR + when 0 => + inst_valid_in <= '1'; + inst_addr <= inst_empty_head(inst_latch_data.i) + IMF_NEXT_ADDR_OFFSET; + inst_read <= '1'; + + -- Memory Flow Control Guard + if (inst_ready_in = '1') then + inst_cnt_next <= inst_cnt + 1; + end if; + -- SET NEXT ADDR + when 1 => + inst_valid_in <= '1'; + inst_addr <= inst_empty_head(inst_latch_data.i) + IMF_NEXT_ADDR_OFFSET; + inst_write_data <= std_logic_vector(resize(inst_addr_latch,WORD_WIDTH)); + + -- Memory Flow Control Guard + if (inst_ready_in = '1') then + inst_cnt_next <= inst_cnt + 1; + end if; + -- READ NEXT ADDR + when 2 => + inst_ready_out <= '1'; + + -- Memory Flow Control Guard + if (inst_valid_out = '1') then + -- Fix Empty List Head + inst_empty_head_next(inst_latch_data.i) <= resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH); + inst_addr_base_next <= inst_empty_head(inst_latch_data.i); - -- Memory Flow Control Guard - if (inst_ready_in = '1') then - -- Exit Condition - if (inst_cnt2 = WRITER_BITMAP_ARRAY_TYPE'length-1) then - inst_data_next.field_flags <= inst_data.field_flags or IMF_WRITER_BITMAP_FLAG; - -- DONE - inst_stage_next <= IDLE; - else - inst_cnt2_next <= inst_cnt2 + 1; - end if; + -- No Next Instance (Occupied Tail) + if (inst_addr_latch = INSTANCE_MEMORY_MAX_ADDRESS) then + inst_cnt_next <= inst_cnt + 4; -- SET PREV ADDR + -- NOTE: inst_addr_base contains the current occupied tail + inst_addr_latch_next <= inst_addr_base; + else + inst_cnt_next <= inst_cnt + 1; end if; - when others => - null; - end case; - when UPDATE_INSTANCE => - case (inst_cnt) is - -- Status Info - when 0 => - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_STATUS_INFO_OFFSET; - inst_write_data <= inst_latch_data.status_info; - inst_data_next.status_info <= inst_latch_data.status_info; - inst_data_next.field_flags <= inst_data.field_flags or IMF_STATUS_FLAG; - -- Memory Flow Control Guard - if (inst_ready_in = '1') then - if check_mask(inst_latch_data.field_flags,IMF_SAMPLE_CNT_FLAG) then - inst_cnt_next <= 1; - elsif check_mask(inst_latch_data.field_flags,IMF_DISPOSED_CNT_FLAG) then - inst_cnt_next <= 2; - elsif check_mask(inst_latch_data.field_flags,IMF_NO_WRITERS_CNT_FLAG) then - inst_cnt_next <= 3; - elsif (TIME_BASED_FILTER_QOS /= DURATION_ZERO and check_mask(inst_latch_data.field_flags,IMF_IGNORE_DEADLINE_FLAG)) then - inst_cnt_next <= 4; - elsif check_mask(inst_latch_data.field_flags,IMF_WRITER_BITMAP_FLAG) then - inst_cnt_next <= 6; - inst_cnt2_next <= 0; - else - -- DONE - inst_stage_next <= IDLE; - end if; - end if; - -- Sample Count - when 1 => - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_SAMPLE_CNT_OFFSET; - inst_write_data <= std_logic_vector(inst_latch_data.sample_cnt); - inst_data_next.sample_cnt <= inst_latch_data.sample_cnt; - inst_data_next.field_flags <= inst_data.field_flags or IMF_SAMPLE_CNT_FLAG; - -- Memory Flow Control Guard - if (inst_ready_in = '1') then - if check_mask(inst_latch_data.field_flags,IMF_DISPOSED_CNT_FLAG) then - inst_cnt_next <= 2; - elsif check_mask(inst_latch_data.field_flags,IMF_NO_WRITERS_CNT_FLAG) then - inst_cnt_next <= 3; - elsif (TIME_BASED_FILTER_QOS /= DURATION_ZERO and check_mask(inst_latch_data.field_flags,IMF_IGNORE_DEADLINE_FLAG)) then - inst_cnt_next <= 4; - elsif check_mask(inst_latch_data.field_flags,IMF_WRITER_BITMAP_FLAG) then - inst_cnt_next <= 6; - inst_cnt2_next <= 0; - else - -- DONE - inst_stage_next <= IDLE; - end if; - end if; - -- Disposed Generation Count - when 2 => - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_DISPOSED_GEN_CNT_OFFSET; - inst_write_data <= std_logic_vector(inst_latch_data.disposed_gen_cnt); - inst_data_next.disposed_gen_cnt <= inst_latch_data.disposed_gen_cnt; - inst_data_next.field_flags <= inst_data.field_flags or IMF_DISPOSED_CNT_FLAG; - -- Memory Flow Control Guard - if (inst_ready_in = '1') then - if check_mask(inst_latch_data.field_flags,IMF_NO_WRITERS_CNT_FLAG) then - inst_cnt_next <= 3; - elsif (TIME_BASED_FILTER_QOS /= DURATION_ZERO and check_mask(inst_latch_data.field_flags,IMF_IGNORE_DEADLINE_FLAG)) then - inst_cnt_next <= 4; - elsif check_mask(inst_latch_data.field_flags,IMF_WRITER_BITMAP_FLAG) then - inst_cnt_next <= 6; - inst_cnt2_next <= 0; - else - -- DONE - inst_stage_next <= IDLE; - end if; - end if; - -- No Writers Generation Count - when 3 => - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_NO_WRITERS_GEN_CNT_OFFSET; - inst_write_data <= std_logic_vector(inst_latch_data.no_writers_gen_cnt); - inst_data_next.no_writers_gen_cnt <= inst_latch_data.no_writers_gen_cnt; - inst_data_next.field_flags <= inst_data.field_flags or IMF_NO_WRITERS_CNT_FLAG; - -- Memory Flow Control Guard - if (inst_ready_in = '1') then - if (TIME_BASED_FILTER_QOS /= DURATION_ZERO and check_mask(inst_latch_data.field_flags,IMF_IGNORE_DEADLINE_FLAG)) then - inst_cnt_next <= 4; - elsif check_mask(inst_latch_data.field_flags,IMF_WRITER_BITMAP_FLAG) then - inst_cnt_next <= 6; - inst_cnt2_next <= 0; - else - -- DONE - inst_stage_next <= IDLE; - end if; - end if; - -- Ignore Deadline 1/2 - when 4 => - if (TIME_BASED_FILTER_QOS /= DURATION_ZERO) then - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_IGNORE_DEADLINE_OFFSET; - inst_write_data <= std_logic_vector(inst_latch_data.ignore_deadline(0)); - inst_data_next.ignore_deadline(0) <= inst_latch_data.ignore_deadline(0); - -- Memory Flow Control Guard - if (inst_ready_in = '1') then - inst_cnt_next <= inst_cnt + 1; - end if; - end if; - -- Ignore Deadline 2/2 - when 5 => - if (TIME_BASED_FILTER_QOS /= DURATION_ZERO) then - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_IGNORE_DEADLINE_OFFSET + 1; - inst_write_data <= std_logic_vector(inst_latch_data.ignore_deadline(1)); - inst_data_next.ignore_deadline(1) <= inst_latch_data.ignore_deadline(1); - inst_data_next.field_flags <= inst_data.field_flags or IMF_IGNORE_DEADLINE_FLAG; - -- Memory Flow Control Guard - if (inst_ready_in = '1') then - if check_mask(inst_latch_data.field_flags,IMF_WRITER_BITMAP_FLAG) then - inst_cnt_next <= 6; - inst_cnt2_next <= 0; - else - -- DONE - inst_stage_next <= IDLE; - end if; - end if; - end if; - -- Writer Bitmap - when 6 => - -- XXX: Possible Worst case Path (2 Additions in same clock) - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_WRITER_BITMAP_OFFSET + inst_cnt2; - inst_write_data <= inst_latch_data.writer_bitmap(inst_cnt2); - inst_data_next.writer_bitmap <= inst_latch_data.writer_bitmap; - -- Memory Flow Control Guard - if (inst_ready_in = '1') then - -- Exit Condition - if (inst_cnt2 = WRITER_BITMAP_ARRAY_TYPE'length-1) then - inst_data_next.field_flags <= inst_data.field_flags or IMF_WRITER_BITMAP_FLAG; - -- DONE - inst_stage_next <= IDLE; - else - inst_cnt2_next <= inst_cnt2 + 1; - end if; - end if; - when others => - null; - end case; - when REMOVE_INSTANCE => - case (inst_cnt) is - -- GET Next Addr - when 0 => - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_NEXT_ADDR_OFFSET; - inst_read <= '1'; - -- Memory Flow Control Guard - if (inst_ready_in = '1') then - inst_cnt_next <= inst_cnt + 1; - end if; - -- GET Prev Addr - when 1 => - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_PREV_ADDR_OFFSET; - inst_read <= '1'; - -- Memory Flow Control Guard - if (inst_ready_in = '1') then - inst_cnt_next <= inst_cnt + 1; - end if; - -- SET Next Addr - when 2 => - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_NEXT_ADDR_OFFSET; - inst_write_data <= std_logic_vector(resize(inst_empty_head,WORD_WIDTH)); + end if; + -- GET PREV ADDR (Next Instance) + when 3 => + inst_valid_in <= '1'; + inst_addr <= inst_addr_latch + IMF_PREV_ADDR_OFFSET; + inst_read <= '1'; + + -- Memory Flow Control Guard + if (inst_ready_in = '1') then + inst_cnt_next <= inst_cnt + 1; + end if; + -- SET PREV ADDR (Next Instance) + when 4 => + inst_valid_in <= '1'; + inst_addr <= inst_addr_latch + IMF_PREV_ADDR_OFFSET; + inst_write_data <= std_logic_vector(resize(inst_addr_base,WORD_WIDTH)); + + -- Memory Flow Control Guard + if (inst_ready_in = '1') then + inst_cnt_next <= inst_cnt + 1; + end if; + -- READ PREV ADDR + when 5 => + inst_ready_out <= '1'; + + -- Memory Flow Control Guard + if (inst_valid_out = '1') then + inst_addr_latch_next <= resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH); - if (inst_ready_in = '1') then - -- Set New Empty Head - inst_empty_head_next <= inst_addr_base; - - inst_cnt_next <= inst_cnt + 1; + inst_cnt_next <= inst_cnt + 1; + end if; + -- SET PREV ADDR + when 6 => + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_PREV_ADDR_OFFSET; + inst_write_data <= std_logic_vector(resize(inst_addr_latch,WORD_WIDTH)); + + -- Memory Flow Control Guard + if (inst_ready_in = '1') then + -- No Previous Instance (Occupied Head) + if (inst_addr_latch = INSTANCE_MEMORY_MAX_ADDRESS) then + inst_cnt_next <= inst_cnt + 2; -- SET Key Hash 1/4 + inst_occupied_head_next(inst_latch_data.i) <= inst_addr_base; + else + inst_cnt_next <= inst_cnt + 1; end if; - -- READ Next Addr - when 3 => - inst_ready_out <= '1'; - -- Memory Flow Control Guard - if (inst_valid_out = '1') then - inst_addr_latch_next <= resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH); - inst_cnt_next <= inst_cnt + 1; + end if; + -- SET NEXT ADDR (Previous Instance) + when 7 => + inst_valid_in <= '1'; + inst_addr <= inst_addr_latch + IMF_NEXT_ADDR_OFFSET; + inst_write_data <= std_logic_vector(resize(inst_addr_base,WORD_WIDTH)); + + -- Memory Flow Control Guard + if (inst_ready_in = '1') then + inst_cnt_next <= inst_cnt + 1; + end if; + -- SET Key Hash 1/4 + when 8 => + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_KEY_HASH_OFFSET; + inst_write_data <= inst_latch_data.key_hash(0); + inst_data_next.key_hash(0) <= inst_latch_data.key_hash(0); + + -- Memory Flow Control Guard + if (inst_ready_in = '1') then + inst_cnt_next <= inst_cnt + 1; + end if; + -- SET Key Hash 2/4 + when 9 => + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_KEY_HASH_OFFSET + 1; + inst_write_data <= inst_latch_data.key_hash(1); + inst_data_next.key_hash(1) <= inst_latch_data.key_hash(1); + + -- Memory Flow Control Guard + if (inst_ready_in = '1') then + inst_cnt_next <= inst_cnt + 1; + end if; + -- SET Key Hash 3/4 + when 10 => + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_KEY_HASH_OFFSET + 2; + inst_write_data <= inst_latch_data.key_hash(2); + inst_data_next.key_hash(2) <= inst_latch_data.key_hash(2); + + -- Memory Flow Control Guard + if (inst_ready_in = '1') then + inst_cnt_next <= inst_cnt + 1; + end if; + -- SET Key Hash 4/4 + when 11 => + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_KEY_HASH_OFFSET + 3; + inst_write_data <= inst_latch_data.key_hash(3); + inst_data_next.key_hash(3) <= inst_latch_data.key_hash(3); + inst_data_next.field_flags <= inst_data.field_flags or IMF_KEY_HASH_FLAG; + + -- Memory Flow Control Guard + if (inst_ready_in = '1') then + inst_cnt_next <= inst_cnt + 1; + end if; + -- SET Status Info + when 12 => + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_STATUS_INFO_OFFSET; + inst_write_data <= inst_latch_data.status_info; + inst_data_next.status_info <= inst_latch_data.status_info; + inst_data_next.field_flags <= inst_data.field_flags or IMF_STATUS_FLAG; + + -- Memory Flow Control Guard + if (inst_ready_in = '1') then + inst_cnt_next <= inst_cnt + 1; + end if; + -- SET Sample Count + when 13 => + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_SAMPLE_CNT_OFFSET; + inst_write_data <= std_logic_vector(inst_latch_data.sample_cnt); + inst_data_next.sample_cnt <= inst_latch_data.sample_cnt; + inst_data_next.field_flags <= inst_data.field_flags or IMF_SAMPLE_CNT_FLAG; + + -- Memory Flow Control Guard + if (inst_ready_in = '1') then + inst_cnt_next <= inst_cnt + 1; + end if; + -- SET Disposed Generation Count + when 14 => + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_DISPOSED_GEN_CNT_OFFSET; + inst_write_data <= (others => '0'); + inst_data_next.disposed_gen_cnt <= (others => '0'); + inst_data_next.field_flags <= inst_data.field_flags or IMF_DISPOSED_CNT_FLAG; + + -- Memory Flow Control Guard + if (inst_ready_in = '1') then + inst_cnt_next <= inst_cnt + 1; + end if; + -- SET No Writers Generation Count + when 15 => + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_NO_WRITERS_GEN_CNT_OFFSET; + inst_write_data <= (others => '0'); + inst_data_next.no_writers_gen_cnt <= (others => '0'); + inst_data_next.field_flags <= inst_data.field_flags or IMF_NO_WRITERS_CNT_FLAG; + + -- Memory Flow Control Guard + if (inst_ready_in = '1') then + inst_cnt_next <= inst_cnt + 1; + end if; + -- SET Ignore Deadline 1/2 + when 16 => + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_IGNORE_DEADLINE_OFFSET; + inst_write_data <= std_logic_vector(inst_latch_data.ignore_deadline(0)); + inst_data_next.ignore_deadline(0) <= inst_latch_data.ignore_deadline(0); + + -- Memory Flow Control Guard + if (inst_ready_in = '1') then + inst_cnt_next <= inst_cnt + 1; + end if; + -- SET Ignore Deadline 2/2 + when 17 => + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_IGNORE_DEADLINE_OFFSET + 1; + inst_write_data <= std_logic_vector(inst_latch_data.ignore_deadline(1)); + inst_data_next.ignore_deadline(1) <= inst_latch_data.ignore_deadline(1); + inst_data_next.field_flags <= inst_data.field_flags or IMF_IGNORE_DEADLINE_FLAG; + + -- Memory Flow Control Guard + if (inst_ready_in = '1') then + inst_cnt_next <= inst_cnt + 1; + inst_cnt2_next <= 0; + end if; + -- SET Writer Bitmap + when 18 => + -- XXX: Possible Worst case Path (2 Additions in same clock) + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_WRITER_BITMAP_OFFSET + inst_cnt2; + inst_write_data <= inst_latch_data.writer_bitmap(inst_cnt2); + inst_data_next.writer_bitmap <= inst_latch_data.writer_bitmap; + + -- Memory Flow Control Guard + if (inst_ready_in = '1') then + -- Exit Condition + if (inst_cnt2 = WRITER_BITMAP_ARRAY_TYPE'length-1) then + inst_data_next.field_flags <= inst_data.field_flags or IMF_WRITER_BITMAP_FLAG; + -- DONE + inst_stage_next <= IDLE; + else + inst_cnt2_next <= inst_cnt2 + 1; end if; - -- READ Prev Addr - when 4 => - inst_ready_out <= '1'; - -- Memory Flow Control Guard - if (inst_valid_out = '1') then - if (inst_addr_latch = INSTANCE_MEMORY_MAX_ADDRESS) then - if (resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH) = INSTANCE_MEMORY_MAX_ADDRESS) then - -- RESET Occupied List Head - inst_occupied_head_next <= INSTANCE_MEMORY_MAX_ADDRESS; - - inst_data_next.addr <= INSTANCE_MEMORY_MAX_ADDRESS; - -- DONE - inst_stage_next <= IDLE; - else - inst_addr_base_next <= resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH); - inst_cnt_next <= inst_cnt + 2; -- Skip Next Step - end if; - else - inst_addr_base_next <= inst_addr_latch; - inst_addr_latch_next <= resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH); - inst_cnt_next <= inst_cnt + 1; - end if; + end if; + when others => + null; + end case; + when UPDATE_INSTANCE => + case (inst_cnt) is + -- Status Info + when 0 => + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_STATUS_INFO_OFFSET; + inst_write_data <= inst_latch_data.status_info; + inst_data_next.status_info <= inst_latch_data.status_info; + inst_data_next.field_flags <= inst_data.field_flags or IMF_STATUS_FLAG; + -- Memory Flow Control Guard + if (inst_ready_in = '1') then + if check_mask(inst_latch_data.field_flags,IMF_SAMPLE_CNT_FLAG) then + inst_cnt_next <= 1; + elsif check_mask(inst_latch_data.field_flags,IMF_DISPOSED_CNT_FLAG) then + inst_cnt_next <= 2; + elsif check_mask(inst_latch_data.field_flags,IMF_NO_WRITERS_CNT_FLAG) then + inst_cnt_next <= 3; + elsif check_mask(inst_latch_data.field_flags,IMF_IGNORE_DEADLINE_FLAG) then + inst_cnt_next <= 4; + elsif check_mask(inst_latch_data.field_flags,IMF_WRITER_BITMAP_FLAG) then + inst_cnt_next <= 6; + inst_cnt2_next <= 0; + else + -- DONE + inst_stage_next <= IDLE; end if; - -- SET Prev Addr (Next Slot) - when 5 => - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_PREV_ADDR_OFFSET; - inst_write_data <= std_logic_vector(resize(inst_addr_latch,WORD_WIDTH)); + end if; + -- Sample Count + when 1 => + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_SAMPLE_CNT_OFFSET; + inst_write_data <= std_logic_vector(inst_latch_data.sample_cnt); + inst_data_next.sample_cnt <= inst_latch_data.sample_cnt; + inst_data_next.field_flags <= inst_data.field_flags or IMF_SAMPLE_CNT_FLAG; + -- Memory Flow Control Guard + if (inst_ready_in = '1') then + if check_mask(inst_latch_data.field_flags,IMF_DISPOSED_CNT_FLAG) then + inst_cnt_next <= 2; + elsif check_mask(inst_latch_data.field_flags,IMF_NO_WRITERS_CNT_FLAG) then + inst_cnt_next <= 3; + elsif check_mask(inst_latch_data.field_flags,IMF_IGNORE_DEADLINE_FLAG) then + inst_cnt_next <= 4; + elsif check_mask(inst_latch_data.field_flags,IMF_WRITER_BITMAP_FLAG) then + inst_cnt_next <= 6; + inst_cnt2_next <= 0; + else + -- DONE + inst_stage_next <= IDLE; + end if; + end if; + -- Disposed Generation Count + when 2 => + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_DISPOSED_GEN_CNT_OFFSET; + inst_write_data <= std_logic_vector(inst_latch_data.disposed_gen_cnt); + inst_data_next.disposed_gen_cnt <= inst_latch_data.disposed_gen_cnt; + inst_data_next.field_flags <= inst_data.field_flags or IMF_DISPOSED_CNT_FLAG; + -- Memory Flow Control Guard + if (inst_ready_in = '1') then + if check_mask(inst_latch_data.field_flags,IMF_NO_WRITERS_CNT_FLAG) then + inst_cnt_next <= 3; + elsif check_mask(inst_latch_data.field_flags,IMF_IGNORE_DEADLINE_FLAG) then + inst_cnt_next <= 4; + elsif check_mask(inst_latch_data.field_flags,IMF_WRITER_BITMAP_FLAG) then + inst_cnt_next <= 6; + inst_cnt2_next <= 0; + else + -- DONE + inst_stage_next <= IDLE; + end if; + end if; + -- No Writers Generation Count + when 3 => + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_NO_WRITERS_GEN_CNT_OFFSET; + inst_write_data <= std_logic_vector(inst_latch_data.no_writers_gen_cnt); + inst_data_next.no_writers_gen_cnt <= inst_latch_data.no_writers_gen_cnt; + inst_data_next.field_flags <= inst_data.field_flags or IMF_NO_WRITERS_CNT_FLAG; + -- Memory Flow Control Guard + if (inst_ready_in = '1') then + if check_mask(inst_latch_data.field_flags,IMF_IGNORE_DEADLINE_FLAG) then + inst_cnt_next <= 4; + elsif check_mask(inst_latch_data.field_flags,IMF_WRITER_BITMAP_FLAG) then + inst_cnt_next <= 6; + inst_cnt2_next <= 0; + else + -- DONE + inst_stage_next <= IDLE; + end if; + end if; + -- Ignore Deadline 1/2 + when 4 => + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_IGNORE_DEADLINE_OFFSET; + inst_write_data <= std_logic_vector(inst_latch_data.ignore_deadline(0)); + inst_data_next.ignore_deadline(0) <= inst_latch_data.ignore_deadline(0); + -- Memory Flow Control Guard + if (inst_ready_in = '1') then + inst_cnt_next <= inst_cnt + 1; + end if; + -- Ignore Deadline 2/2 + when 5 => + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_IGNORE_DEADLINE_OFFSET + 1; + inst_write_data <= std_logic_vector(inst_latch_data.ignore_deadline(1)); + inst_data_next.ignore_deadline(1) <= inst_latch_data.ignore_deadline(1); + inst_data_next.field_flags <= inst_data.field_flags or IMF_IGNORE_DEADLINE_FLAG; + -- Memory Flow Control Guard + if (inst_ready_in = '1') then + if check_mask(inst_latch_data.field_flags,IMF_WRITER_BITMAP_FLAG) then + inst_cnt_next <= 6; + inst_cnt2_next <= 0; + else + -- DONE + inst_stage_next <= IDLE; + end if; + end if; + -- Writer Bitmap + when 6 => + -- XXX: Possible Worst case Path (2 Additions in same clock) + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_WRITER_BITMAP_OFFSET + inst_cnt2; + inst_write_data <= inst_latch_data.writer_bitmap(inst_cnt2); + inst_data_next.writer_bitmap <= inst_latch_data.writer_bitmap; + -- Memory Flow Control Guard + if (inst_ready_in = '1') then + -- Exit Condition + if (inst_cnt2 = WRITER_BITMAP_ARRAY_TYPE'length-1) then + inst_data_next.field_flags <= inst_data.field_flags or IMF_WRITER_BITMAP_FLAG; + -- DONE + inst_stage_next <= IDLE; + else + inst_cnt2_next <= inst_cnt2 + 1; + end if; + end if; + when others => + null; + end case; + when REMOVE_INSTANCE => + case (inst_cnt) is + -- GET Next Addr + when 0 => + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_NEXT_ADDR_OFFSET; + inst_read <= '1'; + -- Memory Flow Control Guard + if (inst_ready_in = '1') then + inst_cnt_next <= inst_cnt + 1; + end if; + -- GET Prev Addr + when 1 => + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_PREV_ADDR_OFFSET; + inst_read <= '1'; + -- Memory Flow Control Guard + if (inst_ready_in = '1') then + inst_cnt_next <= inst_cnt + 1; + end if; + -- SET Next Addr + when 2 => + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_NEXT_ADDR_OFFSET; + inst_write_data <= std_logic_vector(resize(inst_empty_head(inst_latch_data.i),WORD_WIDTH)); + + if (inst_ready_in = '1') then + -- Set New Empty Head + inst_empty_head_next(inst_latch_data.i) <= inst_addr_base; - if (inst_ready_in = '1') then - if (inst_addr_latch = INSTANCE_MEMORY_MAX_ADDRESS) then - -- Set New Occupied List Head - inst_occupied_head_next <= inst_addr_base; + inst_cnt_next <= inst_cnt + 1; + end if; + -- READ Next Addr + when 3 => + inst_ready_out <= '1'; + -- Memory Flow Control Guard + if (inst_valid_out = '1') then + inst_addr_latch_next <= resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH); + inst_cnt_next <= inst_cnt + 1; + end if; + -- READ Prev Addr + when 4 => + inst_ready_out <= '1'; + -- Memory Flow Control Guard + if (inst_valid_out = '1') then + if (inst_addr_latch = INSTANCE_MEMORY_MAX_ADDRESS) then + if (resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH) = INSTANCE_MEMORY_MAX_ADDRESS) then + -- RESET Occupied List Head + inst_occupied_head_next(inst_latch_data.i) <= INSTANCE_MEMORY_MAX_ADDRESS; - inst_data_next.addr <= inst_addr_base; + inst_data_next.addr <= INSTANCE_MEMORY_MAX_ADDRESS; -- DONE inst_stage_next <= IDLE; else - inst_addr_base_next <= inst_addr_latch; - inst_addr_latch_next <= inst_addr_base; - inst_cnt_next <= inst_cnt + 1; + inst_addr_base_next <= resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH); + inst_cnt_next <= inst_cnt + 2; -- Skip Next Step end if; + else + inst_addr_base_next <= inst_addr_latch; + inst_addr_latch_next <= resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH); + inst_cnt_next <= inst_cnt + 1; end if; - -- SET Next Addr (Previous Slot) - when 6 => - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_NEXT_ADDR_OFFSET; - inst_write_data <= std_logic_vector(resize(inst_addr_latch,WORD_WIDTH)); - - if (inst_ready_in = '1') then - inst_data_next.addr <= inst_addr_latch; + end if; + -- SET Prev Addr (Next Slot) + when 5 => + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_PREV_ADDR_OFFSET; + inst_write_data <= std_logic_vector(resize(inst_addr_latch,WORD_WIDTH)); + + if (inst_ready_in = '1') then + if (inst_addr_latch = INSTANCE_MEMORY_MAX_ADDRESS) then + -- Set New Occupied List Head + inst_occupied_head_next(inst_latch_data.i) <= inst_addr_base; + + inst_data_next.addr <= inst_addr_base; -- DONE inst_stage_next <= IDLE; + else + inst_addr_base_next <= inst_addr_latch; + inst_addr_latch_next <= inst_addr_base; + inst_cnt_next <= inst_cnt + 1; end if; - when others => - null; - end case; - when UNMARK_INSTANCES => - -- Precondition: inst_addr_base set - - case (inst_cnt) is - -- GET Next Instance - when 0 => - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_NEXT_ADDR_OFFSET; - inst_read <= '1'; - - -- Memory Flow Control Guard - if (inst_ready_in = '1') then + end if; + -- SET Next Addr (Previous Slot) + when 6 => + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_NEXT_ADDR_OFFSET; + inst_write_data <= std_logic_vector(resize(inst_addr_latch,WORD_WIDTH)); + + if (inst_ready_in = '1') then + inst_data_next.addr <= inst_addr_latch; + -- DONE + inst_stage_next <= IDLE; + end if; + when others => + null; + end case; + when UNMARK_INSTANCES => + -- Precondition: inst_addr_base set + + case (inst_cnt) is + -- GET Next Instance + when 0 => + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_NEXT_ADDR_OFFSET; + inst_read <= '1'; + + -- Memory Flow Control Guard + if (inst_ready_in = '1') then + inst_cnt_next <= inst_cnt + 1; + end if; + -- GET Status Info + when 1 => + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_STATUS_INFO_OFFSET; + inst_read <= '1'; + + -- Memory Flow Control Guard + if (inst_ready_in = '1') then + inst_cnt_next <= inst_cnt + 1; + end if; + -- READ Next Instance + when 2 => + inst_ready_out <= '1'; + + -- Memory Flow Control Guard + if (inst_valid_out = '1') then + inst_addr_latch_next <= resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH); + inst_cnt_next <= inst_cnt + 1; + end if; + -- READ Status Info + when 3 => + inst_ready_out <= '1'; + + -- Memory Flow Control Guard + if (inst_valid_out = '1') then + -- MARK Flag Set + if (inst_read_data(ISI_MARK_FLAG) = '1') then + -- Latch Status Info (With MARK removed) + inst_long_latch_next <= inst_read_data; + inst_long_latch_next(ISI_MARK_FLAG) <= '0'; inst_cnt_next <= inst_cnt + 1; - end if; - -- GET Status Info - when 1 => - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_STATUS_INFO_OFFSET; - inst_read <= '1'; - - -- Memory Flow Control Guard - if (inst_ready_in = '1') then - inst_cnt_next <= inst_cnt + 1; - end if; - -- READ Next Instance - when 2 => - inst_ready_out <= '1'; - - -- Memory Flow Control Guard - if (inst_valid_out = '1') then - inst_addr_latch_next <= resize(unsigned(inst_read_data),INSTANCE_MEMORY_ADDR_WIDTH); - inst_cnt_next <= inst_cnt + 1; - end if; - -- READ Status Info - when 3 => - inst_ready_out <= '1'; - - -- Memory Flow Control Guard - if (inst_valid_out = '1') then - -- MARK Flag Set - if (inst_read_data(ISI_MARK_FLAG) = '1') then - -- Latch Status Info (With MARK removed) - inst_long_latch_next <= inst_read_data; - inst_long_latch_next(ISI_MARK_FLAG) <= '0'; - inst_cnt_next <= inst_cnt + 1; - else - -- End of Instances - if (inst_addr_latch = INSTANCE_MEMORY_MAX_ADDRESS) then - -- DONE - inst_stage_next <= IDLE; - else - -- Continue - inst_addr_base_next <= inst_addr_latch; - inst_cnt_next <= 0; - end if; - end if; - end if; - -- SET Status Info - when 4 => - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_STATUS_INFO_OFFSET; - inst_write_data <= inst_long_latch; - - -- Memory Flow Control Guard - if (inst_ready_in = '1') then + else -- End of Instances if (inst_addr_latch = INSTANCE_MEMORY_MAX_ADDRESS) then -- DONE @@ -6555,52 +6490,78 @@ begin inst_cnt_next <= 0; end if; end if; - when others => - null; - end case; - when RESET_MEMORY => - case (inst_cnt) is - -- SET Next Pointer - when 0 => - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_NEXT_ADDR_OFFSET; - if (inst_addr_base = MAX_INSTANCE_ADDRESS) then - inst_write_data <= std_logic_vector(resize(INSTANCE_MEMORY_MAX_ADDRESS,WORD_WIDTH)); + end if; + -- Status Info + when 4 => + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_STATUS_INFO_OFFSET; + inst_write_data <= inst_long_latch; + + -- Memory Flow Control Guard + if (inst_ready_in = '1') then + -- End of Instances + if (inst_addr_latch = INSTANCE_MEMORY_MAX_ADDRESS) then + -- DONE + inst_stage_next <= IDLE; else - inst_write_data <= std_logic_vector(resize(inst_addr_base + INSTANCE_FRAME_SIZE,WORD_WIDTH)); + -- Continue + inst_addr_base_next <= inst_addr_latch; + inst_cnt_next <= 0; end if; - - -- Memory Flow Control Guard - if (inst_ready_in = '1') then - inst_cnt_next <= inst_cnt + 1; - end if; - -- SET Previous Pointer - when 1 => - inst_valid_in <= '1'; - inst_addr <= inst_addr_base + IMF_PREV_ADDR_OFFSET; - inst_write_data <= std_logic_vector(resize(inst_addr_latch,WORD_WIDTH)); - - -- Memory Flow Control Guard - if (inst_ready_in = '1') then - if (inst_addr_base = MAX_INSTANCE_ADDRESS) then - -- Initialize Empty and Occupied Heads - inst_empty_head_next <= FIRST_INSTANCE_ADDRESS; - inst_occupied_head_next <= INSTANCE_MEMORY_MAX_ADDRESS; - + end if; + when others => + null; + end case; + when RESET_MEMORY => + case (inst_cnt) is + -- SET Next Pointer + when 0 => + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_NEXT_ADDR_OFFSET; + if (inst_addr_base = MAX_INSTANCE_ADDRESS(inst_latch_data.i)) then + inst_write_data <= std_logic_vector(resize(INSTANCE_MEMORY_MAX_ADDRESS,WORD_WIDTH)); + else + inst_write_data <= std_logic_vector(resize(inst_addr_base + INSTANCE_FRAME_SIZE,WORD_WIDTH)); + end if; + + -- Memory Flow Control Guard + if (inst_ready_in = '1') then + inst_cnt_next <= inst_cnt + 1; + end if; + -- SET Previous Pointer + when 1 => + inst_valid_in <= '1'; + inst_addr <= inst_addr_base + IMF_PREV_ADDR_OFFSET; + inst_write_data <= std_logic_vector(resize(inst_addr_latch,WORD_WIDTH)); + + -- Memory Flow Control Guard + if (inst_ready_in = '1') then + if (inst_addr_base = MAX_INSTANCE_ADDRESS(inst_latch_data.i)) then + -- Initialize Empty and Occupied Heads + inst_empty_head_next(inst_latch_data.i) <= FIRST_INSTANCE_ADDRESS; + inst_occupied_head_next(inst_latch_data.i) <= INSTANCE_MEMORY_MAX_ADDRESS; + + if (inst_latch_data.i = NUM_READERS-1) then -- DONE inst_stage_next <= IDLE; else - inst_addr_latch_next <= inst_addr_base; - inst_addr_base_next <= inst_addr_base + INSTANCE_FRAME_SIZE; - inst_cnt_next <= 0; + -- NEXT MEMORY + inst_latch_data_next.i <= inst_latch_data.i + 1; + inst_addr_base_next <= FIRST_INSTANCE_ADDRESS; + inst_addr_latch_next <= INSTANCE_MEMORY_MAX_ADDRESS; + inst_cnt_next <= 0; end if; + else + inst_addr_latch_next <= inst_addr_base; + inst_addr_base_next <= inst_addr_base + INSTANCE_FRAME_SIZE; + inst_cnt_next <= 0; end if; - when others => - null; - end case; - end case; - end process; - end generate; + end if; + when others => + null; + end case; + end case; + end process; sync_prc : process(clk) begin @@ -6608,26 +6569,29 @@ begin if (reset = '1') then stage <= RESET_SAMPLE_MEMORY; inst_stage <= RESET_MEMORY; - newest_sample <= SAMPLE_MEMORY_MAX_ADDRESS; - oldest_sample <= SAMPLE_MEMORY_MAX_ADDRESS; - empty_sample_list_head <= SAMPLE_MEMORY_MAX_ADDRESS; - empty_sample_list_tail <= SAMPLE_MEMORY_MAX_ADDRESS; - empty_payload_list_head <= PAYLOAD_MEMORY_MAX_ADDRESS; + newest_sample <= (others => SAMPLE_MEMORY_MAX_ADDRESS); + oldest_sample <= (others => SAMPLE_MEMORY_MAX_ADDRESS); + empty_sample_list_head <= (others => SAMPLE_MEMORY_MAX_ADDRESS); + empty_sample_list_tail <= (others => SAMPLE_MEMORY_MAX_ADDRESS); + empty_payload_list_head <= (others => PAYLOAD_MEMORY_MAX_ADDRESS); inst_addr_base <= FIRST_INSTANCE_ADDRESS; inst_addr_latch <= INSTANCE_MEMORY_MAX_ADDRESS; - inst_occupied_head <= INSTANCE_MEMORY_MAX_ADDRESS; - inst_empty_head <= INSTANCE_MEMORY_MAX_ADDRESS; + inst_occupied_head <= (others => INSTANCE_MEMORY_MAX_ADDRESS); + inst_empty_head <= (others => INSTANCE_MEMORY_MAX_ADDRESS); key_hash <= KEY_HASH_NIL; si_instance_handle_sig <= HANDLE_NIL; si_publication_handle_sig <= HANDLE_NIL; instance_handle <= HANDLE_NIL; - sample_rej_last_inst <= HANDLE_NIL; + sample_rej_last_inst <= (others => HANDLE_NIL); ts_latch <= TIME_INVALID; lifespan_time <= TIME_INFINITE; lifespan <= TIME_INVALID; si_source_timestamp_sig <= TIME_INVALID; - last_read_ts <= TIME_ZERO; - deadline_time <= time + DEADLINE_QOS; + last_read_ts <= (others => TIME_ZERO); + for i in 0 to NUM_READERS-1 loop + deadline_time(i) <= time + CONFIG_ARRAY_T(i).DEADLINE_QOS; + end loop; + deadline_check_time <= TIME_ZERO; si_sample_state_sig <= ANY_SAMPLE_STATE; sample_state <= ANY_SAMPLE_STATE; si_view_state_sig <= ANY_VIEW_STATE; @@ -6635,20 +6599,18 @@ begin si_instance_state_sig <= ANY_INSTANCE_STATE; instance_state <= ANY_INSTANCE_STATE; inst_data <= ZERO_INSTANCE_DATA; - if (not WITH_KEY) then - inst_data.field_flags <= (others => '1'); - end if; inst_latch_data <= ZERO_INSTANCE_DATA; - sample_rej_last_reason <= NOT_REJECTED; + sample_rej_last_reason <= (others => NOT_REJECTED); rtps_return_code_latch <= ERROR; dds_return_code_latch <= RETCODE_ERROR; + ind <= 0; writer_id <= 0; cnt <= 0; cnt2 <= 0; cnt3 <= 0; inst_cnt <= 0; inst_cnt2 <= 0; - stale_inst_cnt <= 0; + stale_inst_cnt <= (others => 0); is_lifespan_check <= '0'; remove_oldest_sample <= '0'; remove_oldest_inst_sample <= '0'; @@ -6666,9 +6628,9 @@ begin wait_for_sample_removal <= '0'; dis_gen_cnt_latch <= (others => '0'); no_w_gen_cnt_latch <= (others => '0'); - sample_addr_latch_1 <= (others => '0'); + sample_addr_latch_1 <= SAMPLE_MEMORY_MAX_ADDRESS; sample_addr_latch_2 <= (others => '0'); - sample_addr_latch_3 <= (others => '0'); + sample_addr_latch_3 <= FIRST_SAMPLE_ADDRESS; sample_addr_latch_4 <= (others => '0'); sample_addr_latch_5 <= (others => '0'); payload_addr_latch_1 <= (others => '0'); @@ -6687,12 +6649,12 @@ begin collection_cnt_max <= (others => '0'); collection_generation_rank <= (others => '0'); cur_generation_rank <= (others => '0'); - sample_rej_cnt <= (others => '0'); - sample_rej_cnt_change <= (others => '0'); - deadline_miss_cnt <= (others => '0'); - deadline_miss_cnt_change <= (others => '0'); - deadline_miss_last_inst <= HANDLE_NIL; - status_sig <= (others => '0'); + sample_rej_cnt <= (others => (others => '0')); + sample_rej_cnt_change <= (others => (others => '0')); + deadline_miss_cnt <= (others => (others => '0')); + deadline_miss_cnt_change <= (others => (others => '0')); + deadline_miss_last_inst <= (others => HANDLE_NIL); + status_sig <= (others => (others => '0')); inst_long_latch <= (others => '0'); else stage <= stage_next; @@ -6717,21 +6679,19 @@ begin si_source_timestamp_sig <= si_source_timestamp_sig_next; last_read_ts <= last_read_ts_next; deadline_time <= deadline_time_next; + deadline_check_time <= deadline_check_time_next; si_sample_state_sig <= si_sample_state_sig_next; sample_state <= sample_state_next; si_view_state_sig <= si_view_state_sig_next; view_state <= view_state_next; si_instance_state_sig <= si_instance_state_sig_next; instance_state <= instance_state_next; - if (WITH_KEY) then - inst_data <= inst_data_next; - else - inst_data <= inst_data_next2; - end if; + inst_data <= inst_data_next; inst_latch_data <= inst_latch_data_next; sample_rej_last_reason <= sample_rej_last_reason_next; rtps_return_code_latch <= rtps_return_code_latch_next; dds_return_code_latch <= dds_return_code_latch_next; + ind <= ind_next; writer_id <= writer_id_next; cnt <= cnt_next; cnt2 <= cnt2_next; diff --git a/src/ros2/Tests/Level_2/L2_Testbench_ROS_Lib2.vhd b/src/ros2/Tests/Level_2/L2_Testbench_ROS_Lib2.vhd index 8e75b53..5be127c 100644 --- a/src/ros2/Tests/Level_2/L2_Testbench_ROS_Lib2.vhd +++ b/src/ros2/Tests/Level_2/L2_Testbench_ROS_Lib2.vhd @@ -410,22 +410,11 @@ begin status => status_dw_wi(0 to NUM_WRITERS-2) ); end generate; - dds_endpoint_gen : for i in 0 to NUM_READERS-1 generate + dds_endpoint_r_if : if (NUM_READERS > 0) generate dds_reader_inst : entity work.dds_reader(arch) generic map ( - TIME_BASED_FILTER_QOS => ENDPOINT_CONFIG(i).TIME_BASED_FILTER_QOS, - DEADLINE_QOS => ENDPOINT_CONFIG(i).DEADLINE_QOS, - MAX_INSTANCES => ENDPOINT_CONFIG(i).MAX_INSTANCES, - MAX_SAMPLES_PER_INSTANCE => ENDPOINT_CONFIG(i).MAX_SAMPLES_PER_INSTANCE, - MAX_SAMPLES => ENDPOINT_CONFIG(i).MAX_SAMPLES, - HISTORY_QOS => ENDPOINT_CONFIG(i).HISTORY_QOS, - RELIABILITY_QOS => ENDPOINT_CONFIG(i).RELIABILITY_QOS, - PRESENTATION_QOS => ENDPOINT_CONFIG(i).PRESENTATION_QOS, - DESTINATION_ORDER_QOS => ENDPOINT_CONFIG(i).DESTINATION_ORDER_QOS, - COHERENT_ACCESS => ENDPOINT_CONFIG(i).COHERENT_ACCESS, - ORDERED_ACCESS => ENDPOINT_CONFIG(i).ORDERED_ACCESS, - WITH_KEY => ENDPOINT_CONFIG(i).WITH_KEY, - PAYLOAD_FRAME_SIZE => ENDPOINT_CONFIG(i).MAX_PAYLOAD_SIZE, + NUM_READERS => NUM_READERS, + CONFIG_ARRAY => to_QUARTUS_CONFIG_ARRAY_TYPE(ENDPOINT_CONFIG(0 to NUM_READERS-1)), MAX_REMOTE_ENDPOINTS => MAX_REMOTE_ENDPOINTS ) port map ( @@ -434,37 +423,37 @@ begin reset => reset, time => time, -- FROM RTPS ENDPOINT - start_rtps => start_rr_dr(i), - opcode_rtps => opcode_rr_dr(i), - ack_rtps => ack_dr_rr(i), - done_rtps => done_dr_rr(i), - ret_rtps => ret_dr_rr(i), - valid_in_rtps => valid_rr_dr(i), - ready_in_rtps => ready_dr_rr(i), - data_in_rtps => data_rr_dr(i), - last_word_in_rtps => last_word_rr_dr(i), + start_rtps => start_rr_dr(0 to NUM_READERS-1), + opcode_rtps => opcode_rr_dr(0 to NUM_READERS-1), + ack_rtps => ack_dr_rr(0 to NUM_READERS-1), + done_rtps => done_dr_rr(0 to NUM_READERS-1), + ret_rtps => ret_dr_rr(0 to NUM_READERS-1), + valid_in_rtps => valid_rr_dr(0 to NUM_READERS-1), + ready_in_rtps => ready_dr_rr(0 to NUM_READERS-1), + data_in_rtps => data_rr_dr(0 to NUM_READERS-1), + last_word_in_rtps => last_word_rr_dr(0 to NUM_READERS-1), -- TO USER ENTITY - start_dds => start_ri_dr(i), - ack_dds => ack_dr_ri(i), - opcode_dds => opcode_ri_dr(i), - instance_state_dds => instance_state_ri_dr(i), - view_state_dds => view_state_ri_dr(i), - sample_state_dds => sample_state_ri_dr(i), - instance_handle_dds => instance_handle_ri_dr(i), - max_samples_dds => max_samples_ri_dr(i), - get_data_dds => get_data_ri_dr(i), - done_dds => done_dr_ri(i), - return_code_dds => return_code_dr_ri(i), - valid_out_dds => valid_dr_ri(i), - ready_out_dds => ready_ri_dr(i), - data_out_dds => data_dr_ri(i), - last_word_out_dds => last_word_dr_ri(i), - sample_info => sample_info_dr_ri(i), - sample_info_valid => sample_info_valid_dr_ri(i), - sample_info_ack => sample_info_ack_ri_dr(i), - eoc => eoc_dr_ri(i), + start_dds => start_ri_dr(0 to NUM_READERS-1), + ack_dds => ack_dr_ri(0 to NUM_READERS-1), + opcode_dds => opcode_ri_dr(0 to NUM_READERS-1), + instance_state_dds => instance_state_ri_dr(0 to NUM_READERS-1), + view_state_dds => view_state_ri_dr(0 to NUM_READERS-1), + sample_state_dds => sample_state_ri_dr(0 to NUM_READERS-1), + instance_handle_dds => instance_handle_ri_dr(0 to NUM_READERS-1), + max_samples_dds => max_samples_ri_dr(0 to NUM_READERS-1), + get_data_dds => get_data_ri_dr(0 to NUM_READERS-1), + done_dds => done_dr_ri(0 to NUM_READERS-1), + return_code_dds => return_code_dr_ri(0 to NUM_READERS-1), + valid_out_dds => valid_dr_ri(0 to NUM_READERS-1), + ready_out_dds => ready_ri_dr(0 to NUM_READERS-1), + data_out_dds => data_dr_ri(0 to NUM_READERS-1), + last_word_out_dds => last_word_dr_ri(0 to NUM_READERS-1), + sample_info => sample_info_dr_ri(0 to NUM_READERS-1), + sample_info_valid => sample_info_valid_dr_ri(0 to NUM_READERS-1), + sample_info_ack => sample_info_ack_ri_dr(0 to NUM_READERS-1), + eoc => eoc_dr_ri(0 to NUM_READERS-1), -- Communication Status - status => status_dr_ri(i) + status => status_dr_ri(0 to NUM_READERS-1) ); end generate; diff --git a/src/ros2/Tests/Level_2/L2_Testbench_ROS_Lib3.vhd b/src/ros2/Tests/Level_2/L2_Testbench_ROS_Lib3.vhd index 9401c67..003f533 100644 --- a/src/ros2/Tests/Level_2/L2_Testbench_ROS_Lib3.vhd +++ b/src/ros2/Tests/Level_2/L2_Testbench_ROS_Lib3.vhd @@ -418,22 +418,11 @@ begin status => status_dw_wi(0 to NUM_WRITERS-2) ); end generate; - dds_endpoint_gen : for i in 0 to NUM_READERS-1 generate + dds_endpoint_r_if : if (NUM_READERS > 0) generate dds_reader_inst : entity work.dds_reader(arch) generic map ( - TIME_BASED_FILTER_QOS => ENDPOINT_CONFIG(i).TIME_BASED_FILTER_QOS, - DEADLINE_QOS => ENDPOINT_CONFIG(i).DEADLINE_QOS, - MAX_INSTANCES => ENDPOINT_CONFIG(i).MAX_INSTANCES, - MAX_SAMPLES_PER_INSTANCE => ENDPOINT_CONFIG(i).MAX_SAMPLES_PER_INSTANCE, - MAX_SAMPLES => ENDPOINT_CONFIG(i).MAX_SAMPLES, - HISTORY_QOS => ENDPOINT_CONFIG(i).HISTORY_QOS, - RELIABILITY_QOS => ENDPOINT_CONFIG(i).RELIABILITY_QOS, - PRESENTATION_QOS => ENDPOINT_CONFIG(i).PRESENTATION_QOS, - DESTINATION_ORDER_QOS => ENDPOINT_CONFIG(i).DESTINATION_ORDER_QOS, - COHERENT_ACCESS => ENDPOINT_CONFIG(i).COHERENT_ACCESS, - ORDERED_ACCESS => ENDPOINT_CONFIG(i).ORDERED_ACCESS, - WITH_KEY => ENDPOINT_CONFIG(i).WITH_KEY, - PAYLOAD_FRAME_SIZE => ENDPOINT_CONFIG(i).MAX_PAYLOAD_SIZE, + NUM_READERS => NUM_READERS, + CONFIG_ARRAY => to_QUARTUS_CONFIG_ARRAY_TYPE(ENDPOINT_CONFIG(0 to NUM_READERS-1)), MAX_REMOTE_ENDPOINTS => MAX_REMOTE_ENDPOINTS ) port map ( @@ -442,37 +431,37 @@ begin reset => reset, time => time, -- FROM RTPS ENDPOINT - start_rtps => start_rr_dr(i), - opcode_rtps => opcode_rr_dr(i), - ack_rtps => ack_dr_rr(i), - done_rtps => done_dr_rr(i), - ret_rtps => ret_dr_rr(i), - valid_in_rtps => valid_rr_dr(i), - ready_in_rtps => ready_dr_rr(i), - data_in_rtps => data_rr_dr(i), - last_word_in_rtps => last_word_rr_dr(i), + start_rtps => start_rr_dr(0 to NUM_READERS-1), + opcode_rtps => opcode_rr_dr(0 to NUM_READERS-1), + ack_rtps => ack_dr_rr(0 to NUM_READERS-1), + done_rtps => done_dr_rr(0 to NUM_READERS-1), + ret_rtps => ret_dr_rr(0 to NUM_READERS-1), + valid_in_rtps => valid_rr_dr(0 to NUM_READERS-1), + ready_in_rtps => ready_dr_rr(0 to NUM_READERS-1), + data_in_rtps => data_rr_dr(0 to NUM_READERS-1), + last_word_in_rtps => last_word_rr_dr(0 to NUM_READERS-1), -- TO USER ENTITY - start_dds => start_ri_dr(i), - ack_dds => ack_dr_ri(i), - opcode_dds => opcode_ri_dr(i), - instance_state_dds => instance_state_ri_dr(i), - view_state_dds => view_state_ri_dr(i), - sample_state_dds => sample_state_ri_dr(i), - instance_handle_dds => instance_handle_ri_dr(i), - max_samples_dds => max_samples_ri_dr(i), - get_data_dds => get_data_ri_dr(i), - done_dds => done_dr_ri(i), - return_code_dds => return_code_dr_ri(i), - valid_out_dds => valid_dr_ri(i), - ready_out_dds => ready_ri_dr(i), - data_out_dds => data_dr_ri(i), - last_word_out_dds => last_word_dr_ri(i), - sample_info => sample_info_dr_ri(i), - sample_info_valid => sample_info_valid_dr_ri(i), - sample_info_ack => sample_info_ack_ri_dr(i), - eoc => eoc_dr_ri(i), + start_dds => start_ri_dr(0 to NUM_READERS-1), + ack_dds => ack_dr_ri(0 to NUM_READERS-1), + opcode_dds => opcode_ri_dr(0 to NUM_READERS-1), + instance_state_dds => instance_state_ri_dr(0 to NUM_READERS-1), + view_state_dds => view_state_ri_dr(0 to NUM_READERS-1), + sample_state_dds => sample_state_ri_dr(0 to NUM_READERS-1), + instance_handle_dds => instance_handle_ri_dr(0 to NUM_READERS-1), + max_samples_dds => max_samples_ri_dr(0 to NUM_READERS-1), + get_data_dds => get_data_ri_dr(0 to NUM_READERS-1), + done_dds => done_dr_ri(0 to NUM_READERS-1), + return_code_dds => return_code_dr_ri(0 to NUM_READERS-1), + valid_out_dds => valid_dr_ri(0 to NUM_READERS-1), + ready_out_dds => ready_ri_dr(0 to NUM_READERS-1), + data_out_dds => data_dr_ri(0 to NUM_READERS-1), + last_word_out_dds => last_word_dr_ri(0 to NUM_READERS-1), + sample_info => sample_info_dr_ri(0 to NUM_READERS-1), + sample_info_valid => sample_info_valid_dr_ri(0 to NUM_READERS-1), + sample_info_ack => sample_info_ack_ri_dr(0 to NUM_READERS-1), + eoc => eoc_dr_ri(0 to NUM_READERS-1), -- Communication Status - status => status_dr_ri(i) + status => status_dr_ri(0 to NUM_READERS-1) ); end generate; diff --git a/src/ros2/Tests/Level_2/L2_Testbench_ROS_Lib4.vhd b/src/ros2/Tests/Level_2/L2_Testbench_ROS_Lib4.vhd index 5012da4..0ef32c6 100644 --- a/src/ros2/Tests/Level_2/L2_Testbench_ROS_Lib4.vhd +++ b/src/ros2/Tests/Level_2/L2_Testbench_ROS_Lib4.vhd @@ -421,22 +421,11 @@ begin status => status_dw_wi(0 to NUM_WRITERS-2) ); end generate; - dds_endpoint_gen : for i in 0 to NUM_READERS-1 generate + dds_endpoint_r_if : if (NUM_READERS > 0) generate dds_reader_inst : entity work.dds_reader(arch) generic map ( - TIME_BASED_FILTER_QOS => ENDPOINT_CONFIG(i).TIME_BASED_FILTER_QOS, - DEADLINE_QOS => ENDPOINT_CONFIG(i).DEADLINE_QOS, - MAX_INSTANCES => ENDPOINT_CONFIG(i).MAX_INSTANCES, - MAX_SAMPLES_PER_INSTANCE => ENDPOINT_CONFIG(i).MAX_SAMPLES_PER_INSTANCE, - MAX_SAMPLES => ENDPOINT_CONFIG(i).MAX_SAMPLES, - HISTORY_QOS => ENDPOINT_CONFIG(i).HISTORY_QOS, - RELIABILITY_QOS => ENDPOINT_CONFIG(i).RELIABILITY_QOS, - PRESENTATION_QOS => ENDPOINT_CONFIG(i).PRESENTATION_QOS, - DESTINATION_ORDER_QOS => ENDPOINT_CONFIG(i).DESTINATION_ORDER_QOS, - COHERENT_ACCESS => ENDPOINT_CONFIG(i).COHERENT_ACCESS, - ORDERED_ACCESS => ENDPOINT_CONFIG(i).ORDERED_ACCESS, - WITH_KEY => ENDPOINT_CONFIG(i).WITH_KEY, - PAYLOAD_FRAME_SIZE => ENDPOINT_CONFIG(i).MAX_PAYLOAD_SIZE, + NUM_READERS => NUM_READERS, + CONFIG_ARRAY => to_QUARTUS_CONFIG_ARRAY_TYPE(ENDPOINT_CONFIG(0 to NUM_READERS-1)), MAX_REMOTE_ENDPOINTS => MAX_REMOTE_ENDPOINTS ) port map ( @@ -445,37 +434,37 @@ begin reset => reset, time => time, -- FROM RTPS ENDPOINT - start_rtps => start_rr_dr(i), - opcode_rtps => opcode_rr_dr(i), - ack_rtps => ack_dr_rr(i), - done_rtps => done_dr_rr(i), - ret_rtps => ret_dr_rr(i), - valid_in_rtps => valid_rr_dr(i), - ready_in_rtps => ready_dr_rr(i), - data_in_rtps => data_rr_dr(i), - last_word_in_rtps => last_word_rr_dr(i), + start_rtps => start_rr_dr(0 to NUM_READERS-1), + opcode_rtps => opcode_rr_dr(0 to NUM_READERS-1), + ack_rtps => ack_dr_rr(0 to NUM_READERS-1), + done_rtps => done_dr_rr(0 to NUM_READERS-1), + ret_rtps => ret_dr_rr(0 to NUM_READERS-1), + valid_in_rtps => valid_rr_dr(0 to NUM_READERS-1), + ready_in_rtps => ready_dr_rr(0 to NUM_READERS-1), + data_in_rtps => data_rr_dr(0 to NUM_READERS-1), + last_word_in_rtps => last_word_rr_dr(0 to NUM_READERS-1), -- TO USER ENTITY - start_dds => start_ri_dr(i), - ack_dds => ack_dr_ri(i), - opcode_dds => opcode_ri_dr(i), - instance_state_dds => instance_state_ri_dr(i), - view_state_dds => view_state_ri_dr(i), - sample_state_dds => sample_state_ri_dr(i), - instance_handle_dds => instance_handle_ri_dr(i), - max_samples_dds => max_samples_ri_dr(i), - get_data_dds => get_data_ri_dr(i), - done_dds => done_dr_ri(i), - return_code_dds => return_code_dr_ri(i), - valid_out_dds => valid_dr_ri(i), - ready_out_dds => ready_ri_dr(i), - data_out_dds => data_dr_ri(i), - last_word_out_dds => last_word_dr_ri(i), - sample_info => sample_info_dr_ri(i), - sample_info_valid => sample_info_valid_dr_ri(i), - sample_info_ack => sample_info_ack_ri_dr(i), - eoc => eoc_dr_ri(i), + start_dds => start_ri_dr(0 to NUM_READERS-1), + ack_dds => ack_dr_ri(0 to NUM_READERS-1), + opcode_dds => opcode_ri_dr(0 to NUM_READERS-1), + instance_state_dds => instance_state_ri_dr(0 to NUM_READERS-1), + view_state_dds => view_state_ri_dr(0 to NUM_READERS-1), + sample_state_dds => sample_state_ri_dr(0 to NUM_READERS-1), + instance_handle_dds => instance_handle_ri_dr(0 to NUM_READERS-1), + max_samples_dds => max_samples_ri_dr(0 to NUM_READERS-1), + get_data_dds => get_data_ri_dr(0 to NUM_READERS-1), + done_dds => done_dr_ri(0 to NUM_READERS-1), + return_code_dds => return_code_dr_ri(0 to NUM_READERS-1), + valid_out_dds => valid_dr_ri(0 to NUM_READERS-1), + ready_out_dds => ready_ri_dr(0 to NUM_READERS-1), + data_out_dds => data_dr_ri(0 to NUM_READERS-1), + last_word_out_dds => last_word_dr_ri(0 to NUM_READERS-1), + sample_info => sample_info_dr_ri(0 to NUM_READERS-1), + sample_info_valid => sample_info_valid_dr_ri(0 to NUM_READERS-1), + sample_info_ack => sample_info_ack_ri_dr(0 to NUM_READERS-1), + eoc => eoc_dr_ri(0 to NUM_READERS-1), -- Communication Status - status => status_dr_ri(i) + status => status_dr_ri(0 to NUM_READERS-1) ); end generate; diff --git a/src/ros2/Tests/Level_2/L2_Testbench_ROS_Lib5.vhd b/src/ros2/Tests/Level_2/L2_Testbench_ROS_Lib5.vhd index 07450bb..7f49f86 100644 --- a/src/ros2/Tests/Level_2/L2_Testbench_ROS_Lib5.vhd +++ b/src/ros2/Tests/Level_2/L2_Testbench_ROS_Lib5.vhd @@ -451,22 +451,11 @@ begin status => status_dw_wi(0 to NUM_WRITERS-2) ); end generate; - dds_endpoint_gen : for i in 0 to NUM_READERS-1 generate + dds_endpoint_r_if : if (NUM_READERS > 0) generate dds_reader_inst : entity work.dds_reader(arch) generic map ( - TIME_BASED_FILTER_QOS => ENDPOINT_CONFIG(i).TIME_BASED_FILTER_QOS, - DEADLINE_QOS => ENDPOINT_CONFIG(i).DEADLINE_QOS, - MAX_INSTANCES => ENDPOINT_CONFIG(i).MAX_INSTANCES, - MAX_SAMPLES_PER_INSTANCE => ENDPOINT_CONFIG(i).MAX_SAMPLES_PER_INSTANCE, - MAX_SAMPLES => ENDPOINT_CONFIG(i).MAX_SAMPLES, - HISTORY_QOS => ENDPOINT_CONFIG(i).HISTORY_QOS, - RELIABILITY_QOS => ENDPOINT_CONFIG(i).RELIABILITY_QOS, - PRESENTATION_QOS => ENDPOINT_CONFIG(i).PRESENTATION_QOS, - DESTINATION_ORDER_QOS => ENDPOINT_CONFIG(i).DESTINATION_ORDER_QOS, - COHERENT_ACCESS => ENDPOINT_CONFIG(i).COHERENT_ACCESS, - ORDERED_ACCESS => ENDPOINT_CONFIG(i).ORDERED_ACCESS, - WITH_KEY => ENDPOINT_CONFIG(i).WITH_KEY, - PAYLOAD_FRAME_SIZE => ENDPOINT_CONFIG(i).MAX_PAYLOAD_SIZE, + NUM_READERS => NUM_READERS, + CONFIG_ARRAY => to_QUARTUS_CONFIG_ARRAY_TYPE(ENDPOINT_CONFIG(0 to NUM_READERS-1)), MAX_REMOTE_ENDPOINTS => MAX_REMOTE_ENDPOINTS ) port map ( @@ -475,37 +464,37 @@ begin reset => reset, time => time, -- FROM RTPS ENDPOINT - start_rtps => start_rr_dr(i), - opcode_rtps => opcode_rr_dr(i), - ack_rtps => ack_dr_rr(i), - done_rtps => done_dr_rr(i), - ret_rtps => ret_dr_rr(i), - valid_in_rtps => valid_rr_dr(i), - ready_in_rtps => ready_dr_rr(i), - data_in_rtps => data_rr_dr(i), - last_word_in_rtps => last_word_rr_dr(i), + start_rtps => start_rr_dr(0 to NUM_READERS-1), + opcode_rtps => opcode_rr_dr(0 to NUM_READERS-1), + ack_rtps => ack_dr_rr(0 to NUM_READERS-1), + done_rtps => done_dr_rr(0 to NUM_READERS-1), + ret_rtps => ret_dr_rr(0 to NUM_READERS-1), + valid_in_rtps => valid_rr_dr(0 to NUM_READERS-1), + ready_in_rtps => ready_dr_rr(0 to NUM_READERS-1), + data_in_rtps => data_rr_dr(0 to NUM_READERS-1), + last_word_in_rtps => last_word_rr_dr(0 to NUM_READERS-1), -- TO USER ENTITY - start_dds => start_ri_dr(i), - ack_dds => ack_dr_ri(i), - opcode_dds => opcode_ri_dr(i), - instance_state_dds => instance_state_ri_dr(i), - view_state_dds => view_state_ri_dr(i), - sample_state_dds => sample_state_ri_dr(i), - instance_handle_dds => instance_handle_ri_dr(i), - max_samples_dds => max_samples_ri_dr(i), - get_data_dds => get_data_ri_dr(i), - done_dds => done_dr_ri(i), - return_code_dds => return_code_dr_ri(i), - valid_out_dds => valid_dr_ri(i), - ready_out_dds => ready_ri_dr(i), - data_out_dds => data_dr_ri(i), - last_word_out_dds => last_word_dr_ri(i), - sample_info => sample_info_dr_ri(i), - sample_info_valid => sample_info_valid_dr_ri(i), - sample_info_ack => sample_info_ack_ri_dr(i), - eoc => eoc_dr_ri(i), + start_dds => start_ri_dr(0 to NUM_READERS-1), + ack_dds => ack_dr_ri(0 to NUM_READERS-1), + opcode_dds => opcode_ri_dr(0 to NUM_READERS-1), + instance_state_dds => instance_state_ri_dr(0 to NUM_READERS-1), + view_state_dds => view_state_ri_dr(0 to NUM_READERS-1), + sample_state_dds => sample_state_ri_dr(0 to NUM_READERS-1), + instance_handle_dds => instance_handle_ri_dr(0 to NUM_READERS-1), + max_samples_dds => max_samples_ri_dr(0 to NUM_READERS-1), + get_data_dds => get_data_ri_dr(0 to NUM_READERS-1), + done_dds => done_dr_ri(0 to NUM_READERS-1), + return_code_dds => return_code_dr_ri(0 to NUM_READERS-1), + valid_out_dds => valid_dr_ri(0 to NUM_READERS-1), + ready_out_dds => ready_ri_dr(0 to NUM_READERS-1), + data_out_dds => data_dr_ri(0 to NUM_READERS-1), + last_word_out_dds => last_word_dr_ri(0 to NUM_READERS-1), + sample_info => sample_info_dr_ri(0 to NUM_READERS-1), + sample_info_valid => sample_info_valid_dr_ri(0 to NUM_READERS-1), + sample_info_ack => sample_info_ack_ri_dr(0 to NUM_READERS-1), + eoc => eoc_dr_ri(0 to NUM_READERS-1), -- Communication Status - status => status_dr_ri(i) + status => status_dr_ri(0 to NUM_READERS-1) ); end generate; diff --git a/src/rtps_package.vhd b/src/rtps_package.vhd index cf1f0ed..b31f3f2 100644 --- a/src/rtps_package.vhd +++ b/src/rtps_package.vhd @@ -28,6 +28,7 @@ package rtps_package is constant CDR_LONG_WIDTH : natural := 32; constant CDR_FLOAT_WIDTH : natural := 32; constant CDR_ENUMERATION_WIDTH : natural := 32; + type CDR_ENUMERATION_ARRAY_TYPE is array (natural range <>) of std_logic_vector(CDR_ENUMERATION_WIDTH-1 downto 0); constant CDR_LONG_LONG_WIDTH : natural := 64; constant CDR_DOUBLE_WIDTH : natural := 64; constant CDR_LONG_DOUBLE_WIDTH : natural := 128; @@ -76,8 +77,11 @@ package rtps_package is constant ABSOLUTE_GENERATION_COUNT_WIDTH : natural := CDR_LONG_WIDTH; constant INCONSISTENT_TOPIC_STATUS_COUNT_WIDTH : natural := CDR_LONG_WIDTH; + type INCONSISTENT_TOPIC_STATUS_COUNT_ARRAY_TYPE is array (natural range <>) of std_logic_vector(INCONSISTENT_TOPIC_STATUS_COUNT_WIDTH-1 downto 0); constant SAMPLE_LOST_STATUS_COUNT_WIDTH : natural := CDR_LONG_WIDTH; + type SAMPLE_LOST_STATUS_COUNT_ARRAY_TYPE is array (natural range <>) of std_logic_vector(SAMPLE_LOST_STATUS_COUNT_WIDTH-1 downto 0); constant SAMPLE_REJECTED_STATUS_COUNT_WIDTH : natural := CDR_LONG_WIDTH; + type SAMPLE_REJECTED_STATUS_COUNT_ARRAY_TYPE is array (natural range <>) of std_logic_vector(SAMPLE_REJECTED_STATUS_COUNT_WIDTH-1 downto 0); constant LIVELINESS_LOST_STATUS_COUNT_WIDTH : natural := CDR_LONG_WIDTH; type LIVELINESS_LOST_STATUS_COUNT_ARRAY_TYPE is array (natural range <>) of std_logic_vector(LIVELINESS_LOST_STATUS_COUNT_WIDTH-1 downto 0); constant LIVELINESS_CHANGED_STATUS_COUNT_WIDTH : natural := CDR_LONG_WIDTH; @@ -86,9 +90,13 @@ package rtps_package is constant REQUESTED_DEADLINE_MISSED_STATUS_COUNT_WIDTH : natural := CDR_LONG_WIDTH; type REQUESTED_DEADLINE_MISSED_STATUS_COUNT_ARRAY_TYPE is array (natural range <>) of std_logic_vector(REQUESTED_DEADLINE_MISSED_STATUS_COUNT_WIDTH-1 downto 0); constant OFFERED_INCOMPATIBLE_QOS_STATUS_COUNT_WIDTH : natural := CDR_LONG_WIDTH; + type OFFERED_INCOMPATIBLE_QOS_STATUS_COUNT_ARRAY_TYPE is array (natural range <>) of std_logic_vector(OFFERED_INCOMPATIBLE_QOS_STATUS_COUNT_WIDTH-1 downto 0); constant REQUESTED_INCOMPATIBLE_QOS_STATUS_COUNT_WIDTH : natural := CDR_LONG_WIDTH; + type REQUESTED_INCOMPATIBLE_QOS_STATUS_COUNT_ARRAY_TYPE is array (natural range <>) of std_logic_vector(REQUESTED_INCOMPATIBLE_QOS_STATUS_COUNT_WIDTH-1 downto 0); constant PUBLICATION_MATCHED_STATUS_COUNT_WIDTH : natural := CDR_LONG_WIDTH; + type PUBLICATION_MATCHED_STATUS_COUNT_ARRAY_TYPE is array (natural range <>) of std_logic_vector(PUBLICATION_MATCHED_STATUS_COUNT_WIDTH-1 downto 0); constant SUBSCRIPTION_MATCHED_STATUS_COUNT_WIDTH : natural := CDR_LONG_WIDTH; + type SUBSCRIPTION_MATCHED_STATUS_COUNT_ARRAY_TYPE is array (natural range <>) of std_logic_vector(SUBSCRIPTION_MATCHED_STATUS_COUNT_WIDTH-1 downto 0); @@ -197,7 +205,7 @@ package rtps_package is constant REJECTED_BY_SAMPLES_LIMIT : std_logic_vector(CDR_ENUMERATION_WIDTH-1 downto 0) := std_logic_vector(to_unsigned(2,CDR_ENUMERATION_WIDTH)); constant REJECTED_BY_SAMPLES_PER_INSTANCE_LIMIT : std_logic_vector(CDR_ENUMERATION_WIDTH-1 downto 0) := std_logic_vector(to_unsigned(3,CDR_ENUMERATION_WIDTH)); -- Extension - constant REJECTED_BY_PAYOAD_MEMORY_LIMIT : std_logic_vector(CDR_ENUMERATION_WIDTH-1 downto 0) := std_logic_vector(to_unsigned(255,CDR_ENUMERATION_WIDTH)); + constant REJECTED_BY_PAYLOAD_MEMORY_LIMIT : std_logic_vector(CDR_ENUMERATION_WIDTH-1 downto 0) := std_logic_vector(to_unsigned(255,CDR_ENUMERATION_WIDTH)); constant REJECTED_BY_PENDING_SAMPLE_GENERATION : std_logic_vector(CDR_ENUMERATION_WIDTH-1 downto 0) := std_logic_vector(to_unsigned(256,CDR_ENUMERATION_WIDTH)); -- *QOS POLICY ID* (DDS) diff --git a/syn/DE10-Nano/top.qsf b/syn/DE10-Nano/top.qsf index 21af300..0f54f58 100644 --- a/syn/DE10-Nano/top.qsf +++ b/syn/DE10-Nano/top.qsf @@ -39,7 +39,7 @@ set_global_assignment -name FAMILY "Cyclone V" set_global_assignment -name DEVICE 5CSEBA6U23I7 -set_global_assignment -name TOP_LEVEL_ENTITY dds_writer_syn +set_global_assignment -name TOP_LEVEL_ENTITY test_top set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.0 set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:33:09 NOVEMBER 02, 2020" set_global_assignment -name LAST_QUARTUS_VERSION "21.1.0 Lite Edition" diff --git a/syn/dds_reader_syn.vhd b/syn/dds_reader_syn.vhd index e2be539..33be506 100644 --- a/syn/dds_reader_syn.vhd +++ b/syn/dds_reader_syn.vhd @@ -18,38 +18,37 @@ entity dds_reader_syn is reset : in std_logic; time : in TIME_TYPE; -- FROM RTPS ENDPOINT - start_rtps : in std_logic; - opcode_rtps : in HISTORY_CACHE_OPCODE_TYPE; - ack_rtps : out std_logic; - done_rtps : out std_logic; - ret_rtps : out HISTORY_CACHE_RESPONSE_TYPE; - data_in_rtps : in std_logic_vector(WORD_WIDTH-1 downto 0); - valid_in_rtps : in std_logic; - ready_in_rtps : out std_logic; - last_word_in_rtps : in std_logic; + start_rtps : in std_logic_vector(0 to 0); + opcode_rtps : in HISTORY_CACHE_OPCODE_ARRAY_TYPE(0 to 0); + ack_rtps : out std_logic_vector(0 to 0); + done_rtps : out std_logic_vector(0 to 0); + ret_rtps : out HISTORY_CACHE_RESPONSE_ARRAY_TYPE(0 to 0); + data_in_rtps : in WORD_ARRAY_TYPE(0 to 0); + valid_in_rtps : in std_logic_vector(0 to 0); + ready_in_rtps : out std_logic_vector(0 to 0); + last_word_in_rtps : in std_logic_vector(0 to 0); -- TO USER ENTITY - start_dds : in std_logic; - ack_dds : out std_logic; - opcode_dds : in DDS_READER_OPCODE_TYPE; - instance_state_dds : in std_logic_vector(INSTANCE_STATE_KIND_WIDTH-1 downto 0); - view_state_dds : in std_logic_vector(VIEW_STATE_KIND_WIDTH-1 downto 0); - sample_state_dds : in std_logic_vector(SAMPLE_STATE_KIND_WIDTH-1 downto 0); - instance_handle_dds : in INSTANCE_HANDLE_TYPE; - max_samples_dds : in std_logic_vector(MAX_SAMPLES_WIDTH-1 downto 0); - get_data_dds : in std_logic; - done_dds : out std_logic; - return_code_dds : out std_logic_vector(RETURN_CODE_WIDTH-1 downto 0); - ready_out_dds : in std_logic; - valid_out_dds : out std_logic; - data_out_dds : out std_logic_vector(WORD_WIDTH-1 downto 0); - last_word_out_dds : out std_logic; - -- Sample Info - sample_info : out SAMPLE_INFO_TYPE; - sample_info_valid : out std_logic; - sample_info_ack : in std_logic; - eoc : out std_logic; + start_dds : in std_logic_vector(0 to 0); + ack_dds : out std_logic_vector(0 to 0); + opcode_dds : in DDS_READER_OPCODE_ARRAY_TYPE(0 to 0); + instance_state_dds : in INSTANCE_STATE_ARRAY_TYPE(0 to 0); + view_state_dds : in VIEW_STATE_ARRAY_TYPE(0 to 0); + sample_state_dds : in SAMPLE_STATE_ARRAY_TYPE(0 to 0); + instance_handle_dds : in INSTANCE_HANDLE_ARRAY_TYPE(0 to 0); + max_samples_dds : in MAX_SAMPLES_ARRAY_TYPE(0 to 0); + get_data_dds : in std_logic_vector(0 to 0); + done_dds : out std_logic_vector(0 to 0); + return_code_dds : out RETURN_CODE_ARRAY_TYPE(0 to 0); + valid_out_dds : out std_logic_vector(0 to 0); + ready_out_dds : in std_logic_vector(0 to 0); + data_out_dds : out WORD_ARRAY_TYPE(0 to 0); + last_word_out_dds : out std_logic_vector(0 to 0); + sample_info : out SAMPLE_INFO_ARRAY_TYPE(0 to 0); + sample_info_valid : out std_logic_vector(0 to 0); + sample_info_ack : in std_logic_vector(0 to 0); + eoc : out std_logic_vector(0 to 0); -- Communication Status - status : out std_logic_vector(STATUS_KIND_WIDTH-1 downto 0) + status : out STATUS_KIND_ARRAY_TYPE(0 to 0) ); end entity; @@ -59,19 +58,9 @@ begin if_gen : if (NUM_READERS > 0) generate syn_inst : entity work.dds_reader(arch) generic map ( - TIME_BASED_FILTER_QOS => ENDPOINT_CONFIG(0).TIME_BASED_FILTER_QOS, - DEADLINE_QOS => ENDPOINT_CONFIG(0).DEADLINE_QOS, - MAX_INSTANCES => ENDPOINT_CONFIG(0).MAX_INSTANCES, - MAX_SAMPLES_PER_INSTANCE => ENDPOINT_CONFIG(0).MAX_SAMPLES_PER_INSTANCE, - MAX_SAMPLES => ENDPOINT_CONFIG(0).MAX_SAMPLES, - HISTORY_QOS => ENDPOINT_CONFIG(0).HISTORY_QOS, - RELIABILITY_QOS => ENDPOINT_CONFIG(0).RELIABILITY_QOS, - PRESENTATION_QOS => ENDPOINT_CONFIG(0).PRESENTATION_QOS, - DESTINATION_ORDER_QOS => ENDPOINT_CONFIG(0).DESTINATION_ORDER_QOS, - COHERENT_ACCESS => ENDPOINT_CONFIG(0).COHERENT_ACCESS, - ORDERED_ACCESS => ENDPOINT_CONFIG(0).ORDERED_ACCESS, - WITH_KEY => ENDPOINT_CONFIG(0).WITH_KEY, - PAYLOAD_FRAME_SIZE => MAX_TYPE1_SIZE + NUM_READERS => 1, + CONFIG_ARRAY => to_QUARTUS_CONFIG_ARRAY_TYPE(ENDPOINT_CONFIG(0 to 0)), + MAX_REMOTE_ENDPOINTS => 50 ) port map ( clk => clk,