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Redo Memory Interface of RTPS Endpoint

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The Memory Control Process is made more generic (with less specialised
code), to allow the main process more control. I.e. all Memory Frame
Fields are individually addressable (during GET and UPDATE).
The RAM instance is hidden behind a Memory Controller with Flow Control
Signals, allowing easy future integration to different Memory Interfaces
(e.g. AXI Lite).
This commit is contained in:
Greek 2021-01-29 11:50:22 +01:00
parent 63b8858af9
commit d54bf55b46
5 changed files with 1406 additions and 698 deletions
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49
src/REF.txt
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@ -303,6 +303,9 @@ ENDPOINT LIVELINESS UPDATE
LOCAL ENDPOINT BUFFER
=====================
READER
------
31............24..............16..............8...............0
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+-------------------------------------------------------------+
@ -315,21 +318,55 @@ LOCAL ENDPOINT BUFFER
03| |
+-------------------------------------------------------------+
04| IPv4_ADDRESS | [Reliable Only]
+-----------------------------+-----------------------------+-+
05| UDP_PORT | UNUSED |Q| [Reliable Only]
+-----------------------------+-----------------------------+-+
+-----------------------------+-------------------------------+
05| UDP_PORT | UNUSED | [Reliable Only]
+-----------------------------+-------------------------------+
06| |
+ NEXT_SEQ_NR +
07| |
+-------------------------------------------------------------+
08| |
+ LEASE_DEADLINE +
09| |
+-------------------------------------------------------------+
10| |
+ RES_TIME + [Reliable Only]
11| |
+-------------------------------------------------------------+
WRITER
------
31............24..............16..............8...............0
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+-------------------------------------------------------------+
00| ENTITYID |
+-------------------------------------------------------------+
01| |
+ +
02| GUIDPREFIX |
+ +
03| |
+-------------------------------------------------------------+
04| IPv4_ADDRESS | [Reliable Only]
+-----------------------------+---------------------------+-+-+
05| UDP_PORT | UNUSED |P|Q| [Reliable Only]
+-----------------------------+---------------------------+-+-+
06| |
+ LEASE_DEADLINE +
07| |
+-------------------------------------------------------------+
08| |
+ RES_TIME + [Reliable Only]
08| |
+ GAP_LOW_SEQ_NR + [Reliable Only]
09| |
+-------------------------------------------------------------+
10| |
+ NEXT_SEQ_NR +
+ GAP_HIGH_SEQ_NR + [Reliable Only]
11| |
+-------------------------------------------------------------+
12| |
+ RES_TIME + [Reliable Only]
13| |
+-------------------------------------------------------------+
HISTORY CACHE

98
src/mem_ctrl.vhd Normal file
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@ -0,0 +1,98 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mem_ctrl is
generic (
ADDR_WIDTH : natural;
DATA_WIDTH : natural;
MEMORY_DEPTH : natural;
MAX_BURST_LENGTH : natural
);
port (
clk : in std_logic;
reset : in std_logic;
addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
read : in std_logic;
ready_in : out std_logic;
valid_in : in std_logic;
data_in : in std_logic_vector(DATA_WIDTH-1 downto 0);
ready_out : in std_logic;
valid_out : out std_logic;
data_out : out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end entity;
architecture arch of mem_ctrl is
-- *CONSTANT DECLARATION*
constant READ_LATENCY : natural := 1;
-- *TYPE DECLARATION*
-- *SIGNAL DECLARATION*
signal mem_read_data : std_logic_vector(DATA_WIDTH-1 downto 0);
signal delay_line : std_logic_vector(READ_LATENCY downto 0) := (others => '0');
signal fifo_empty : std_logic := '0';
signal fifo_cnt : natural 0 to MAX_BURST_LENGTH := 0;
signal delay_cnt : natural 0 to READ_LATENCY := 0;
begin
--*****COMPONENT INSTANTIATION*****
ram_inst : entity work.single_port_ram(arch)
generic map (
ADDR_WIDTH => ADDR_WIDTH,
DATA_WIDTH => DATA_WIDTH,
MEMORY_DEPTH => MEMORY_DEPTH
)
port map (
clk => clk,
addr => addr,
wen => not read,
ren => read,
wr_data => data_in,
rd_data => mem_read_data
);
delay_line_prc : process(clk)
begin
if rising_edge(clk) then
if (reset = '1') then
delay_line <= (others => '0');
delay_cnt <= 0;
else
-- Shift Right
delay_line(READ_LATENCY-1 downto 0) <= delay_line(READ_LATENCY downto 1);
delay_line(READ_LATENCY) <= read;
if (read = '1' and delay_line(1) = '0') then
delay_cnt <= delay_cnt + 1;
elsif (read = '0' and delay_line(1) = '1') then
delay_cnt <= delay_cnt - 1;
end if;
end if;
end if;
end process;
burst_fifo_inst : entity work.FWFT_FIFO(arch)
generic map (
FIFO_DEPTH => MAX_BURST_LENGTH,
DATA_WIDTH => DATA_WIDTH
)
port map (
clk => clk,
reset => reset,
data_in => mem_read_data,
write => delay_line(0),
read => ready_out,
data_out => data_out,
empty => fifo_empty,
full => open,
free => fifo_cnt,
);
ready_in <= '0' when (fifo_cnt + delay_cnt = MAX_BURST_LENGTH) else '1';
valid_out <= not fifo_empty;
end architecture;

12
src/rtps_config_package.vhd
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@ -136,6 +136,8 @@ package rtps_config_package is
function check_qos_compatibility(src_is_reader : std_logic; direction : std_logic; remote : unsigned(WORD_WIDTH-1 downto 0); local : unsigned(WORD_WIDTH-1 downto 0)) return boolean;
function check_qos_compatibility(src_is_reader : std_logic; direction : std_logic; remote : DOUBLE_WORD_ARRAY; local : DOUBLE_WORD_ARRAY) return boolean;
function check_mask(flags : std_logic_vector, mask : std_logic_vector) return boolean;
end package;
package body rtps_config_package is
@ -1087,4 +1089,14 @@ package body rtps_config_package is
return ret;
end function;
function check_mask(flags : std_logic_vector, mask : std_logic_vector) return boolean is
begin
assert (flags'length = mask'length) report "Flag and mask Signal have unequal length" severity FAILURE;
if ((flags and mask) = mask) then
return TRUE;
else
return FALSE;
end if;
end function;
end package body;

1944
src/rtps_endpoint.vhd
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File diff suppressed because it is too large Load Diff

1
src/rtps_package.vhd
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@ -115,6 +115,7 @@ package rtps_package is
constant PROTOCOLVERSION_2_4 : std_logic_vector(PROTOCOLVERSION_WIDTH-1 downto 0) := x"0204";
constant VENDORID_UNKNOWN : std_logic_vector(VENDORID_WIDTH-1 downto 0) := (others => '0');
constant GUIDPREFIX_UNKNOWN : GUIDPREFIX_TYPE := (others => (others => '0'));
constant GUID_UNKNOWN : GUID_TYPE := (others => (others => '0'));
constant UDP_PORT_INVALID : std_logic_vector(UDP_PORT_WIDTH-1 downto 0) := (others => '0');
constant IPv4_ADDRESS_INVALID : std_logic_vector(IPv4_ADDRESS_WIDTH-1 downto 0) := (others => '0');
constant LENGTH_UNLIMITED : std_logic_vector(CDR_LONG_WIDTH-1 downto 0) := std_logic_vector(to_signed(-1,CDR_LONG_WIDTH));