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* rtps_builtin_endpoint compiles

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* Single port RAM implementation for Altera
* Added Altera doc
This commit is contained in:
Greek 2020-10-26 23:43:54 +01:00
parent 63c8c8dccc
commit d61b9dc80a
7 changed files with 292 additions and 199 deletions
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3
VHDL-2008.txt
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@ -3,3 +3,6 @@ Quartus 18.1 Unsupported
* Unconstrained arrays in records (Supported in Pro)
* Vectors in aggregate statements
e.g. V := ("0000", others => '1');
* Unary logical operators
* Referencing generics in generic lists
*

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doc/Altera/qts_qii51007.pdf Normal file
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doc/Altera/ug_ram.pdf Normal file
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328
src/rtps_builtin_endpoint.vhd
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60
src/rtps_package.vhd
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@ -129,8 +129,11 @@ package rtps_package is
constant DURATION_DELTA : DOUBLE_WORD_ARRAY := (to_unsigned(0,32),to_unsigned(429496730,32)); --100 ms
constant DEFAULT_PARTICIPANT_LEASE_DURATION : DOUBLE_WORD_ARRAY := (to_unsigned(100,32),to_unsigned(0,32));
constant DEFAULT_PARTICIPANT_LEASE_DURATION : DOUBLE_WORD_ARRAY := (to_unsigned(100,32),to_unsigned(0,32)); -- 100s
constant PARTICIPANT_ANNOUNCEMENT_PERIOD : DOUBLE_WORD_ARRAY := (to_unsigned(30,32),to_unsigned(0,32)); -- 30s
constant PARTICIPANT_LEASE_DURATION : DOUBLE_WORD_ARRAY := DEFAULT_PARTICIPANT_LEASE_DURATION;
constant MIN_ENDPOINT_LEASE_DURATION : DOUBLE_WORD_ARRAY; -- Deferred to package Body
-- NOTE: The buffer will not only store participants, but also endpoint data
-- Used to determine the size of the builtin endpoint buffer
@ -193,7 +196,7 @@ package rtps_package is
constant PID_HISTORY : std_logic_vector(PARAMETER_ID_WIDTH-1 downto 0) := x"0040";
constant PID_RESOURCE_LIMITS : std_logic_vector(PARAMETER_ID_WIDTH-1 downto 0) := x"0041";
constant PID_OWNERSHIP : std_logic_vector(PARAMETER_ID_WIDTH-1 downto 0) := x"001f";
constant PID_OWNERSHIP_STRENGTH : std_logic_vector(PARAMETER_ID_WIDTH-1 downto 0) := x"001e";
constant PID_OWNERSHIP_STRENGTH : std_logic_vector(PARAMETER_ID_WIDTH-1 downto 0) := x"0006";
constant PID_PRESENTATION : std_logic_vector(PARAMETER_ID_WIDTH-1 downto 0) := x"0021";
constant PID_PARTITION : std_logic_vector(PARAMETER_ID_WIDTH-1 downto 0) := x"0029";
constant PID_TIME_BASED_FILTER : std_logic_vector(PARAMETER_ID_WIDTH-1 downto 0) := x"0004";
@ -357,7 +360,7 @@ package rtps_package is
constant OPCODE_LIVELINESS_UPDATE : std_logic_vector(ENDPOINT_MATCH_OPCODE_WIDTH-1 downto 0) := x"55000002";
type USER_ENDPOINT_OUTPUT is array (0 to MAX_ENDPOINTS-1) of std_logic_vector(31 downto 0);
type ENDPOINT_BITMASK_ARRAY_TYPE is array (0 to ENDPOINT_BITMASK_SIZE-1) of std_logic_vector(31 downto 0);
type ENDPOINT_BITMASK_ARRAY_TYPE is array (0 to ENDPOINT_BITMASK_SIZE-1) of std_logic_vector(0 to 31);
type WORD_ARRAY_TYPE is array (natural range <>) of std_logic_vector(31 downto 0);
type OUTPUT_DATA_TYPE is record
@ -397,6 +400,8 @@ package rtps_package is
function "-" (L,R: DOUBLE_WORD_ARRAY) return DOUBLE_WORD_ARRAY;
function "-" (L: DOUBLE_WORD_ARRAY; R: natural) return DOUBLE_WORD_ARRAY;
function "-" (L: natural; R: DOUBLE_WORD_ARRAY) return DOUBLE_WORD_ARRAY;
function min(L, R : DOUBLE_WORD_ARRAY) return DOUBLE_WORD_ARRAY;
function max(L, R : DOUBLE_WORD_ARRAY) return DOUBLE_WORD_ARRAY;
end package;
@ -454,14 +459,37 @@ package body rtps_package is
constant GUIDPREFIX : GUIDPREFIX_TYPE := gen_guidprefix;
function find_min_lease_duration return DOUBLE_WORD_ARRAY is
variable ret : DOUBLE_WORD_ARRAY := (others => (others => '0'));
begin
ret := DURATION_INFINITE;
-- Sanity Check
if (NUM_WRITERS = 0) then
return ret;
end if;
-- Iterate through writers
for i in NUM_READERS to MAX_ENDPOINTS-1 loop
-- Do not consider "MANUAL_BY_TOPIC" Liveliness
if (ENDPOINT_LIVELINESS(i) /= MANUAL_BY_TOPIC_LIVELINESS_QOS) then
-- Find Minimum Lease Duration
if (ENDPOINT_LEASE_DURATION(i) < ret) then
ret := ENDPOINT_LEASE_DURATION(i);
end if;
end if;
end loop;
return ret;
end function;
constant MIN_ENDPOINT_LEASE_DURATION : DOUBLE_WORD_ARRAY := find_min_lease_duration;
-- TODO: Use unconstraint string as input
function convert_string (str : string(1 to 256)) return STRING_SLV_WORD_TYPE is
variable ret : STRING_SLV_WORD_TYPE := (others => (others => '0'));
begin
ret := (others => (others => '0'));
for i in 0 to ret'length-1 loop
ret(i) := std_logic_vector(to_unsigned(character'POS(str(1)), 8)) & std_logic_vector(to_unsigned(character'POS(str(2)), 8)) & std_logic_vector(to_unsigned(character'POS(str(3)), 8)) & std_logic_vector(to_unsigned(character'POS(str(4)), 8));
--ret(i) := std_logic_vector(to_unsigned(character'POS(str((i*4)+1)), 8)) & std_logic_vector(to_unsigned(character'POS(str((i*4)+2)), 8)) & std_logic_vector(to_unsigned(character'POS(str((i*4)+3)), 8)) & std_logic_vector(to_unsigned(character'POS(str((i*4)+4)), 8));
ret(i) := std_logic_vector(to_unsigned(character'POS(str((i*4)+1)), 8)) & std_logic_vector(to_unsigned(character'POS(str((i*4)+2)), 8)) & std_logic_vector(to_unsigned(character'POS(str((i*4)+3)), 8)) & std_logic_vector(to_unsigned(character'POS(str((i*4)+4)), 8));
end loop;
return ret;
end function;
@ -1105,4 +1133,26 @@ package body rtps_package is
return convert_to_double_word(L - convert_from_double_word(R));
end function;
function min(L, R : DOUBLE_WORD_ARRAY) return DOUBLE_WORD_ARRAY is
variable ret : DOUBLE_WORD_ARRAY;
begin
if L < R then
ret := L;
else
ret := R;
end if;
return ret;
end function;
function max(L, R : DOUBLE_WORD_ARRAY) return DOUBLE_WORD_ARRAY is
variable ret : DOUBLE_WORD_ARRAY;
begin
if L > R then
ret := L;
else
ret := R;
end if;
return ret;
end function;
end package body;

64
src/single_port_ram.vhd
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@ -2,15 +2,14 @@ library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
Library xpm;
use xpm.vcomponents.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
entity single_port_ram is
generic (
ADDR_WIDTH : integer := 8;
DATA_WIDTH : integer := 12;
MEMORY_SIZE : integer := DATA_WIDTH*(2**ADDR_WIDTH)
ADDR_WIDTH : natural := 8;
DATA_WIDTH : natural := 12;
MEMORY_DEPTH : natural := 256
);
port (
clk : in std_logic;
@ -26,41 +25,30 @@ architecture arch of single_port_ram is
begin
xpm_memory_spram_inst : xpm_memory_spram
altsyncram_component : altsyncram
generic map (
ADDR_WIDTH_A => ADDR_WIDTH,
AUTO_SLEEP_TIME => 0,
BYTE_WRITE_WIDTH_A => DATA_WIDTH,
ECC_MODE => "no_ecc",
MEMORY_INIT_FILE => "none",
MEMORY_INIT_PARAM => "0",
MEMORY_OPTIMIZATION => "true",
MEMORY_PRIMITIVE => "auto",
MEMORY_SIZE => MEMORY_SIZE,
MESSAGE_CONTROL => 0,
READ_DATA_WIDTH_A => DATA_WIDTH,
READ_LATENCY_A => 1,
READ_RESET_VALUE_A => "0",
RST_MODE_A => "SYNC",
USE_MEM_INIT => 1,
WAKEUP_TIME => "disable_sleep",
WRITE_DATA_WIDTH_A => DATA_WIDTH,
WRITE_MODE_A => "read_first"
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
intended_device_family => "Cyclone V",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => MEMORY_DEPTH,
operation_mode => "SINGLE_PORT",
outdata_aclr_a => "NONE",
outdata_reg_a => "UNREGISTERED",
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "DONT_CARE",
widthad_a => ADDR_WIDTH,
width_a => DATA_WIDTH,
width_byteena_a => 1
)
port map (
dbiterra => open,
douta => rd_data,
sbiterra => open,
addra => addr,
clka => clk,
dina => wr_data,
ena => (ren or wen),
injectdbiterra => '0',
injectsbiterra => '0',
regcea => '1',
rsta => '0',
sleep => '0',
wea => (others => wen) --1-bit Vector
address_a => addr,
clock0 => clk,
data_a => wr_data,
rden_a => ren,
wren_a => wen,
q_a => rd_data
);
end architecture;

4
syn/DE10-Nano/top.qsf
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@ -38,7 +38,7 @@
set_global_assignment -name FAMILY "Cyclone V"
set_global_assignment -name DEVICE 5CSEBA6U23I7
set_global_assignment -name TOP_LEVEL_ENTITY test
set_global_assignment -name TOP_LEVEL_ENTITY rtps_builtin_endpoint
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:05:11 MAY 29, 2020"
set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Lite Edition"
@ -51,6 +51,8 @@ set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name VHDL_FILE ../../src/single_port_ram.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/rtps_builtin_endpoint.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/rtps_package.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/test_package.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/test.vhd -hdl_version VHDL_2008