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Add Level 1 Test 2 of TYPE2 wrapper and key_holder

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The writer_wrapper was modified to allow changing the used endian via
generic. This allows to test Little Endian handling in simulations.
The Test2 are basically Test1 with Little Endian
This commit is contained in:
Greek 2021-11-07 16:21:20 +01:00
parent 27aa801e74
commit d907a85c07
7 changed files with 967 additions and 27 deletions
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6
src/Tests/Level_1/L1_Type2_key_holder_test1.vhd
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@ -11,6 +11,10 @@ use work.rtps_config_package.all;
use work.rtps_test_package.all; use work.rtps_test_package.all;
use work.Type2_package.all; use work.Type2_package.all;
-- This testbench tests the KEY_HOLDER commands of TYPE2.
-- It uses the writer_wrapper to send a valid TYPE2 payload, then reads the serialized key and the key hash. The returned serialized key is compared to a "handcrafted" reference, and the key hash is latched for later comparison.
-- Then the reference serialized key is pushed (resetting the internaly generated key hash), and the serialized key and key hash are re-read and compared (The key hash is compared to the previosuly compared).
-- The TYPE2 payload is sent in Big Endian.
entity L1_Type2_key_holder_test1 is entity L1_Type2_key_holder_test1 is
end entity; end entity;
@ -181,7 +185,7 @@ begin
begin begin
SetAlertLogName("Type2_key_holder - Level 1"); SetAlertLogName("Type2_key_holder - Level 1 - (Big Endian) - Generic");
SetAlertEnable(FAILURE, TRUE); SetAlertEnable(FAILURE, TRUE);
SetAlertEnable(ERROR, TRUE); SetAlertEnable(ERROR, TRUE);
SetAlertEnable(WARNING, TRUE); SetAlertEnable(WARNING, TRUE);

437
src/Tests/Level_1/L1_Type2_key_holder_test2.vhd Normal file
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@ -0,0 +1,437 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library osvvm; -- Utility Library
context osvvm.OsvvmContext;
use work.rtps_package.all;
use work.user_config.all;
use work.rtps_config_package.all;
use work.rtps_test_package.all;
use work.Type2_package.all;
-- This testbench tests the KEY_HOLDER commands of TYPE2.
-- It uses the writer_wrapper to send a valid TYPE2 payload, then reads the serialized key and the key hash. The returned serialized key is compared to a "handcrafted" reference, and the key hash is latched for later comparison.
-- Then the reference serialized key is pushed (resetting the internaly generated key hash), and the serialized key and key hash are re-read and compared (The key hash is compared to the previosuly compared).
-- The TYPE2 payload is sent in Little Endian.
entity L1_Type2_key_holder_test2 is
end entity;
architecture testbench of L1_Type2_key_holder_test2 is
signal clk, reset : std_logic := '0';
signal ready_sk, ready_w, ready_kh_in, ready_kh_out, valid_sk, valid_w, valid_kh_in, valid_kh_out, last_word_sk, last_word_w, last_word_kh_in, last_word_kh_out : std_logic := '0';
signal data_sk, data_w, data_kh_in, data_kh_out : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
signal start_w, ack_w, start_kh, ack_kh, decode_error, encode_done : std_logic := '0';
signal opcode_kh : KEY_HOLDER_OPCODE_TYPE := NOP;
shared variable SB_out : osvvm.ScoreBoardPkg_slv.ScoreBoardPType;
shared variable serialized_key : TEST_PACKET_TYPE := EMPTY_TEST_PACKET;
signal key_hash, key_hash_latch : KEY_HASH_TYPE := HANDLE_NIL;
signal id_in : std_logic_vector(CDR_LONG_WIDTH-1 downto 0) := (others => '0');
signal TestSequence_len_in, TestSequence_addr_in: std_logic_vector(TESTSEQUENCE_ADDR_WIDTH-1 downto 0) := (others => '0');
signal TestSequence_ready_in, TestSequence_wen_in : std_logic := '0';
signal TestSequence_TestArray_addr_in : std_logic_vector(TESTSEQUENCE_TESTARRAY_ADDR_WIDTH-1 downto 0) := (others => '0');
signal TestSequence_TestArray_ready_in, TestSequence_TestArray_wen_in : std_logic := '0';
signal TestSequence_TestArray_w_in : std_logic_vector(CDR_OCTET_WIDTH-1 downto 0) := (others => '0');
signal TestSequence_TestChar_w_in : std_logic_vector(CDR_CHAR_WIDTH-1 downto 0) := (others => '0');
signal TestSequence_TestWChar_w_in : std_logic_vector(CDR_WCHAR_WIDTH-1 downto 0) := (others => '0');
signal TestSequence_TestLongLong_w_in : std_logic_vector(CDR_LONG_LONG_WIDTH-1 downto 0) := (others => '0');
signal TestSequence_TestLongDouble_w_in : std_logic_vector(CDR_LONG_DOUBLE_WIDTH-1 downto 0) := (others => '0');
signal TestSequence_TestLongDouble_valid_w_in : std_logic := '0';
signal TestMap_len_in, TestMap_addr_in : std_logic_vector(TESTMAP_ADDR_WIDTH-1 downto 0) := (others => '0');
signal TestMap_ready_in, TestMap_wen_in : std_logic := '0';
signal TestMap_key_w_in : std_logic_vector(CDR_OCTET_WIDTH-1 downto 0) := (others => '0');
signal TestMap_value_w_in : std_logic_vector(CDR_SHORT_WIDTH-1 downto 0) := (others => '0');
signal TestEnum_in : std_logic_vector(TESTENUM_WIDTH-1 downto 0) := (others => '0');
signal TestUnion_valid_in : std_logic := '0';
signal TestUnion_d_in : std_logic_vector(CDR_CHAR_WIDTH-1 downto 0) := (others => '0');
signal TestUnion_LongU_in : std_logic_vector(CDR_LONG_WIDTH-1 downto 0) := (others => '0');
signal TestUnion_OctetU_in : std_logic_vector(CDR_OCTET_WIDTH-1 downto 0) := (others => '0');
signal TestBitmask_in : std_logic_vector(TESTBITMASK_WIDTH-1 downto 0) := (others => '0');
signal TestString_len_in, TestString_addr_in : std_logic_vector(TESTSTRING_ADDR_WIDTH-1 downto 0) := (others => '0');
signal TestString_ready_in, TestString_wen_in : std_logic := '0';
signal TestString_w_in : std_logic_vector(CDR_CHAR_WIDTH-1 downto 0) := (others => '0');
begin
Type2_writer_wrapper_inst : entity work.Type2_writer_wrapper(arch)
generic map (
LITTLE_ENDIAN => '1'
)
port map (
clk => clk,
reset => reset,
start_dds => open,
ack_dds => '1',
opcode_dds => open,
instance_handle_dds => open,
source_ts_dds => open,
max_wait_dds => open,
done_dds => '1',
return_code_dds => RETCODE_OK,
ready_out_dds => ready_w,
valid_out_dds => valid_w,
data_out_dds => data_w,
last_word_out_dds => last_word_w,
ready_in_dds => open,
valid_in_dds => '0',
data_in_dds => (others => '0'),
last_word_in_dds => '0',
status_dds => (others => '0'),
start_user => start_w,
ack_user => ack_w,
opcode_user => WRITE,
instance_handle_user => HANDLE_NIL,
source_ts_user => TIME_ZERO,
max_wait_user => TIME_INFINITE,
done_user => open,
return_code_user => open,
ready_out_user => '1',
valid_out_user => open,
data_out_user => open,
last_word_out_user => open,
status_user => open,
encode_done => encode_done,
id => id_in,
TestSequence_len => TestSequence_len_in,
TestSequence_addr => TestSequence_addr_in,
TestSequence_ready => TestSequence_ready_in,
TestSequence_ren => '0',
TestSequence_wen => TestSequence_wen_in,
TestSequence_valid => open,
TestSequence_ack => '0',
TestSequence_TestArray_addr => TestSequence_TestArray_addr_in,
TestSequence_TestArray_ready => TestSequence_TestArray_ready_in,
TestSequence_TestArray_ren => '0',
TestSequence_TestArray_wen => TestSequence_TestArray_wen_in,
TestSequence_TestArray_valid => open,
TestSequence_TestArray_ack => '0',
TestSequence_TestArray_r => open,
TestSequence_TestArray_w => TestSequence_TestArray_w_in,
TestSequence_TestChar_r => open,
TestSequence_TestChar_w => TestSequence_TestChar_w_in,
TestSequence_TestWChar_r => open,
TestSequence_TestWChar_w => TestSequence_TestWChar_w_in,
TestSequence_TestLongLong_r => open,
TestSequence_TestLongLong_w => TestSequence_TestLongLong_w_in,
TestSequence_TestLongDouble_r => open,
TestSequence_TestLongDouble_w => TestSequence_TestLongDouble_w_in,
TestSequence_TestLongDouble_valid_r => open,
TestSequence_TestLongDouble_valid_w => TestSequence_TestLongDouble_valid_w_in,
TestMap_len => TestMap_len_in,
TestMap_addr => TestMap_addr_in,
TestMap_ready => TestMap_ready_in,
TestMap_ren => '0',
TestMap_wen => TestMap_wen_in,
TestMap_valid => open,
TestMap_ack => '0',
TestMap_key_r => open,
TestMap_key_w => TestMap_key_w_in,
TestMap_value_r => open,
TestMap_value_w => TestMap_value_w_in,
TestEnum => TestEnum_in,
TestUnion_valid => TestUnion_valid_in,
TestUnion_d => TestUnion_d_in,
TestUnion_LongU => TestUnion_LongU_in,
TestUnion_OctetU => TestUnion_OctetU_in,
TestBitmask => TestBitmask_in,
TestString_len => TestString_len_in,
TestString_addr => TestString_addr_in,
TestString_ready => TestString_ready_in,
TestString_ren => '0',
TestString_wen => TestString_wen_in,
TestString_valid => open,
TestString_ack => '0',
TestString_r => open,
TestString_w => TestString_w_in
);
uut : entity work.key_holder(TYPE2)
port map (
clk => clk,
reset => reset,
start => start_kh,
opcode => opcode_kh,
ack => ack_kh,
decode_error => decode_error,
data_in => data_kh_in,
valid_in => valid_kh_in,
ready_in => ready_kh_in,
last_word_in => last_word_kh_in,
data_out => data_kh_out,
valid_out => valid_kh_out,
ready_out => ready_kh_out,
last_word_out => last_word_kh_out
);
stimulus_prc : process
variable RV : RandomPType;
variable align_offset : unsigned(MAX_ALIGN_OFFSET_WIDTH-1 downto 0) := (others => '0');
variable SK, KH : AlertLogIDType;
procedure wait_on_sig(signal sig : std_logic) is
begin
if (sig /= '1') then
wait on sig until sig = '1';
end if;
end procedure;
procedure push_sk is
begin
for i in 0 to serialized_key.length-1 loop
SB_out.Push(serialized_key.data(i));
end loop;
end procedure;
begin
SetAlertLogName("Type2_key_holder - Level 1 - (Little Endian) - Generic");
SetAlertEnable(FAILURE, TRUE);
SetAlertEnable(ERROR, TRUE);
SetAlertEnable(WARNING, TRUE);
SetLogEnable(DEBUG, FALSE);
SetLogEnable(PASSED, FALSE);
SetLogEnable(INFO, TRUE);
RV.InitSeed(RV'instance_name);
SK := GetAlertLogID("SerializedKey", ALERTLOG_BASE_ID);
KH := GetAlertLogID("KeyHash", ALERTLOG_BASE_ID);
Log("Setting Data in Writer Side", INFO);
start_w <= '0';
wait until rising_edge(clk);
-- Static
id_in <= RV.RandSlv(id_in'length);
TestEnum_in <= RV.RandSlv(TestEnum_in'length);
TestUnion_valid_in <= '1';
TestUnion_d_in <= (others => '0');
TestUnion_LongU_in <= RV.RandSlv(TestUnion_LongU_in'length);
TestUnion_OctetU_in <= RV.RandSlv(TestUnion_OctetU_in'length);
TestBitmask_in <= RV.RandSlv(TestBitmask_in'length);
wait for 0 ns;
gen_CDR(id_in, ALIGN_4, align_offset, serialized_key);
TestSequence_len_in <= int(2,TestSequence_len_in'length);
gen_CDR(int(2,CDR_LONG_WIDTH), ALIGN_4, align_offset, serialized_key);
-- Memory
for i in 0 to 1 loop
TestSequence_addr_in <= int(i,TestSequence_addr_in'length);
TestSequence_TestChar_w_in <= RV.RandSlv(TestSequence_TestChar_w_in'length);
TestSequence_TestWChar_w_in <= RV.RandSlv(TestSequence_TestWChar_w_in'length);
TestSequence_TestLongLong_w_in <= RV.RandSlv(TestSequence_TestLongLong_w_in'length);
TestSequence_TestLongDouble_w_in <= RV.RandSlv(TestSequence_TestLongDouble_w_in'length);
TestSequence_TestLongDouble_valid_w_in <= RV.RandSlv(1)(1);
for j in 0 to 4 loop
TestSequence_TestArray_addr_in <= int(j,TestSequence_TestArray_addr_in'length);
TestSequence_TestArray_w_in <= RV.RandSlv(TestSequence_TestArray_w_in'length);
wait_on_sig(TestSequence_TestArray_ready_in);
TestSequence_TestArray_wen_in <= '1';
wait until rising_edge(clk);
TestSequence_TestArray_wen_in <= '0';
gen_CDR(TestSequence_TestArray_w_in, ALIGN_1, align_offset, serialized_key);
end loop;
wait_on_sig(TestSequence_ready_in);
TestSequence_wen_in <= '1';
wait until rising_edge(clk);
TestSequence_wen_in <= '0';
end loop;
for i in 0 to 0 loop
TestMap_len_in <= int(1,TestMap_len_in'length);
TestMap_addr_in <= int(i,TestMap_addr_in'length);
TestMap_key_w_in <= RV.RandSlv(TestMap_key_w_in'length);
TestMap_value_w_in <= RV.RandSlv(TestMap_value_w_in'length);
wait_on_sig(TestMap_ready_in);
TestMap_wen_in <= '1';
wait until rising_edge(clk);
TestMap_wen_in <= '0';
end loop;
for i in 0 to 9 loop
TestString_len_in <= int(10,TestString_len_in'length);
TestString_addr_in <= int(i,TestString_addr_in'length);
TestString_w_in <= RV.RandSlv(TestString_w_in'length);
wait_on_sig(TestString_ready_in);
TestString_wen_in <= '1';
wait until rising_edge(clk);
TestString_wen_in <= '0';
end loop;
-- Finalize Serialized Key
if (align_offset(1 downto 0) /= "00") then
serialized_key.length := serialized_key.length + 1;
end if;
push_sk;
Log("Push DATA", INFO);
opcode_kh <= PUSH_DATA;
start_w <= '1';
wait_on_sig(ack_w);
wait until rising_edge(clk);
start_w <= '0';
start_kh <= '1';
wait_on_sig(ack_kh);
wait until rising_edge(clk);
start_kh <= '0';
wait_on_sig(last_word_kh_in);
wait_on_sig(ready_kh_in);
wait until rising_edge(clk);
Log("Read and Compare Serialized Key", INFO);
opcode_kh <= READ_SERIALIZED_KEY;
start_kh <= '1';
wait_on_sig(ack_kh);
wait until rising_edge(clk);
start_kh <= '0';
wait_on_sig(last_word_kh_out);
wait_on_sig(ready_kh_out);
wait until rising_edge(clk);
Log("Read Key Hash", INFO);
opcode_kh <= READ_KEY_HASH;
start_kh <= '1';
wait_on_sig(ack_kh);
wait until rising_edge(clk);
start_kh <= '0';
wait_on_sig(last_word_kh_out);
wait_on_sig(ready_kh_out);
wait until rising_edge(clk);
Log("Push Serialized Key", INFO);
opcode_kh <= PUSH_SERIALIZED_KEY;
start_kh <= '1';
wait_on_sig(ack_kh);
wait until rising_edge(clk);
start_kh <= '0';
wait_on_sig(last_word_sk);
wait_on_sig(ready_sk);
wait until rising_edge(clk);
push_sk;
Log("Read and Compare Serialized Key", INFO);
opcode_kh <= READ_SERIALIZED_KEY;
start_kh <= '1';
wait_on_sig(ack_kh);
wait until rising_edge(clk);
start_kh <= '0';
wait_on_sig(last_word_kh_out);
wait_on_sig(ready_kh_out);
wait until rising_edge(clk);
-- Latch previous read Key Hash
key_hash_latch <= key_hash;
Log("Read and Compare Key Hash", INFO);
opcode_kh <= READ_KEY_HASH;
start_kh <= '1';
wait_on_sig(ack_kh);
wait until rising_edge(clk);
start_kh <= '0';
wait_on_sig(last_word_kh_out);
wait_on_sig(ready_kh_out);
wait until rising_edge(clk);
AffirmIfEqual(KH, to_unsigned(key_hash), to_unsigned(key_hash_latch));
TranscriptOpen(RESULTS_FILE, APPEND_MODE);
SetTranscriptMirror;
ReportAlerts;
TranscriptClose;
std.env.stop;
wait;
end process;
clock_prc : process
begin
clk <= '0';
wait for TEST_CLOCK_PERIOD/2;
clk <= '1';
wait for TEST_CLOCK_PERIOD/2;
end process;
alert_prc : process(all)
begin
if rising_edge(clk) then
Alertif(decode_error = '1', "The Reader signals a DECODE Error", ERROR);
end if;
end process;
switch_prc : process(all)
begin
case (opcode_kh) is
when PUSH_SERIALIZED_KEY =>
ready_sk <= ready_kh_in;
valid_kh_in <= valid_sk;
data_kh_in <= data_sk;
last_word_kh_in <= last_word_sk;
ready_w <= '0';
when others =>
ready_w <= ready_kh_in;
valid_kh_in <= valid_w;
data_kh_in <= data_w;
last_word_kh_in <= last_word_w;
ready_sk <= '0';
end case;
end process;
sk_prc : process(all)
variable cnt : natural := 0;
begin
if rising_edge(clk) then
valid_sk <= '1';
data_sk <= serialized_key.data(cnt);
if (cnt = serialized_key.length-1) then
last_word_sk <= '1';
end if;
if (ready_sk = '1') then
if (cnt = serialized_key.length-1) then
cnt := 0;
else
cnt := cnt + 1;
end if;
end if;
end if;
end process;
output_check_prc : process(all)
variable cnt : natural range 0 to 3 := 0;
begin
if rising_edge(clk) then
case (opcode_kh) is
when READ_KEY_HASH =>
ready_kh_out <= '1';
if (valid_kh_out = '1') then
key_hash(cnt) <= data_kh_out;
if (cnt = 3) then
cnt := 0;
Alertif(last_word_kh_out = '0', "last_word_in is 0");
else
cnt := cnt + 1;
end if;
end if;
when READ_SERIALIZED_KEY =>
ready_kh_out <= '1';
if (valid_kh_out = '1') then
SB_out.Check(data_kh_out);
if (SB_out.empty) then
Alertif(last_word_kh_out = '0', "last_word_in is 0");
end if;
end if;
when others =>
ready_kh_out <= '0';
end case;
end if;
end process;
watchdog : process
begin
wait for 1 ms;
Alert("Test timeout", FAILURE);
std.env.stop;
end process;
end architecture;

5
src/Tests/Level_1/L1_Type2_wrapper_test1.vhd
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@ -11,6 +11,9 @@ use work.rtps_config_package.all;
use work.rtps_test_package.all; use work.rtps_test_package.all;
use work.Type2_package.all; use work.Type2_package.all;
-- This testbench tests the Payload encoding/decoding of the TYPE2_wrapper entities.
-- It does so by interconnecting the writer and reader wrapper, setting some inputs to the writer and checking if the reader returns the same data.
-- This testbench tests only the Big Endian encoding/decoding.
entity L1_Type2_wrapper_test1 is entity L1_Type2_wrapper_test1 is
end entity; end entity;
@ -254,7 +257,7 @@ begin
end procedure; end procedure;
begin begin
SetAlertLogName("Type2_wrapper - Level 1"); SetAlertLogName("Type2_wrapper - Level 1 - (Big Endian) - Encoding/Decoding");
SetAlertEnable(FAILURE, TRUE); SetAlertEnable(FAILURE, TRUE);
SetAlertEnable(ERROR, TRUE); SetAlertEnable(ERROR, TRUE);
SetAlertEnable(WARNING, TRUE); SetAlertEnable(WARNING, TRUE);

483
src/Tests/Level_1/L1_Type2_wrapper_test2.vhd Normal file
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@ -0,0 +1,483 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library osvvm; -- Utility Library
context osvvm.OsvvmContext;
use work.rtps_package.all;
use work.user_config.all;
use work.rtps_config_package.all;
use work.rtps_test_package.all;
use work.Type2_package.all;
-- This testbench tests the Payload encoding/decoding of the TYPE2_wrapper entities.
-- It does so by interconnecting the writer and reader wrapper, setting some inputs to the writer and checking if the reader returns the same data.
-- This testbench tests only the Little Endian encoding/decoding.
entity L1_Type2_wrapper_test2 is
end entity;
architecture testbench of L1_Type2_wrapper_test2 is
signal clk, reset : std_logic := '0';
signal ready, valid, last_word : std_logic := '0';
signal data : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
signal start_w, get_data_r, decode_error, valid_r, encode_done : std_logic := '0';
signal id_in, id_out : std_logic_vector(CDR_LONG_WIDTH-1 downto 0) := (others => '0');
signal TestSequence_len_in, TestSequence_len_out, TestSequence_addr_in, TestSequence_addr_out : std_logic_vector(TESTSEQUENCE_ADDR_WIDTH-1 downto 0) := (others => '0');
signal TestSequence_ready_in, TestSequence_ready_out, TestSequence_ren_in, TestSequence_ren_out, TestSequence_wen_in, TestSequence_valid_in, TestSequence_valid_out, TestSequence_ack_in, TestSequence_ack_out : std_logic := '0';
signal TestSequence_TestArray_addr_in, TestSequence_TestArray_addr_out : std_logic_vector(TESTSEQUENCE_TESTARRAY_ADDR_WIDTH-1 downto 0) := (others => '0');
signal TestSequence_TestArray_ready_in, TestSequence_TestArray_ready_out, TestSequence_TestArray_ren_in, TestSequence_TestArray_ren_out, TestSequence_TestArray_wen_in, TestSequence_TestArray_valid_in, TestSequence_TestArray_valid_out, TestSequence_TestArray_ack_in, TestSequence_TestArray_ack_out : std_logic := '0';
signal TestSequence_TestArray_r_in, TestSequence_TestArray_w_in, TestSequence_TestArray_out : std_logic_vector(CDR_OCTET_WIDTH-1 downto 0) := (others => '0');
signal TestSequence_TestChar_r_in, TestSequence_TestChar_w_in, TestSequence_TestChar_out : std_logic_vector(CDR_CHAR_WIDTH-1 downto 0) := (others => '0');
signal TestSequence_TestWChar_r_in, TestSequence_TestWChar_w_in, TestSequence_TestWChar_out : std_logic_vector(CDR_WCHAR_WIDTH-1 downto 0) := (others => '0');
signal TestSequence_TestLongLong_r_in, TestSequence_TestLongLong_w_in, TestSequence_TestLongLong_out : std_logic_vector(CDR_LONG_LONG_WIDTH-1 downto 0) := (others => '0');
signal TestSequence_TestLongDouble_r_in, TestSequence_TestLongDouble_w_in, TestSequence_TestLongDouble_out : std_logic_vector(CDR_LONG_DOUBLE_WIDTH-1 downto 0) := (others => '0');
signal TestSequence_TestLongDouble_valid_r_in, TestSequence_TestLongDouble_valid_w_in, TestSequence_TestLongDouble_valid_out : std_logic := '0';
signal TestMap_len_in, TestMap_len_out, TestMap_addr_in, TestMap_addr_out : std_logic_vector(TESTMAP_ADDR_WIDTH-1 downto 0) := (others => '0');
signal TestMap_ready_in, TestMap_ready_out, TestMap_ren_in, TestMap_ren_out, TestMap_wen_in, TestMap_valid_in, TestMap_valid_out, TestMap_ack_in, TestMap_ack_out : std_logic := '0';
signal TestMap_key_r_in, TestMap_key_w_in, TestMap_key_out : std_logic_vector(CDR_OCTET_WIDTH-1 downto 0) := (others => '0');
signal TestMap_value_r_in, TestMap_value_w_in, TestMap_value_out : std_logic_vector(CDR_SHORT_WIDTH-1 downto 0) := (others => '0');
signal TestEnum_in, TestEnum_out : std_logic_vector(TESTENUM_WIDTH-1 downto 0) := (others => '0');
signal TestUnion_valid_in, TestUnion_valid_out : std_logic := '0';
signal TestUnion_d_in, TestUnion_d_out : std_logic_vector(CDR_CHAR_WIDTH-1 downto 0) := (others => '0');
signal TestUnion_LongU_in, TestUnion_LongU_out : std_logic_vector(CDR_LONG_WIDTH-1 downto 0) := (others => '0');
signal TestUnion_OctetU_in, TestUnion_OctetU_out : std_logic_vector(CDR_OCTET_WIDTH-1 downto 0) := (others => '0');
signal TestBitmask_in, TestBitmask_out : std_logic_vector(TESTBITMASK_WIDTH-1 downto 0) := (others => '0');
signal TestString_len_in, TestString_len_out, TestString_addr_in, TestString_addr_out : std_logic_vector(TESTSTRING_ADDR_WIDTH-1 downto 0) := (others => '0');
signal TestString_ready_in, TestString_ready_out, TestString_ren_in, TestString_ren_out, TestString_wen_in, TestString_valid_in, TestString_valid_out, TestString_ack_in, TestString_ack_out : std_logic := '0';
signal TestString_r_in, TestString_w_in, TestString_out : std_logic_vector(CDR_CHAR_WIDTH-1 downto 0) := (others => '0');
begin
uut_w : entity work.Type2_writer_wrapper(arch)
generic map (
LITTLE_ENDIAN => '1'
)
port map (
clk => clk,
reset => reset,
start_dds => open,
ack_dds => '1',
opcode_dds => open,
instance_handle_dds => open,
source_ts_dds => open,
max_wait_dds => open,
done_dds => '1',
return_code_dds => RETCODE_OK,
ready_out_dds => ready,
valid_out_dds => valid,
data_out_dds => data,
last_word_out_dds => last_word,
ready_in_dds => open,
valid_in_dds => '0',
data_in_dds => (others => '0'),
last_word_in_dds => '0',
status_dds => (others => '0'),
start_user => start_w,
ack_user => open,
opcode_user => WRITE,
instance_handle_user => HANDLE_NIL,
source_ts_user => TIME_ZERO,
max_wait_user => TIME_INFINITE,
done_user => open,
return_code_user => open,
ready_out_user => '1',
valid_out_user => open,
data_out_user => open,
last_word_out_user => open,
status_user => open,
encode_done => encode_done,
id => id_in,
TestSequence_len => TestSequence_len_in,
TestSequence_addr => TestSequence_addr_in,
TestSequence_ready => TestSequence_ready_in,
TestSequence_ren => TestSequence_ren_in,
TestSequence_wen => TestSequence_wen_in,
TestSequence_valid => TestSequence_valid_in,
TestSequence_ack => TestSequence_ack_in,
TestSequence_TestArray_addr => TestSequence_TestArray_addr_in,
TestSequence_TestArray_ready => TestSequence_TestArray_ready_in,
TestSequence_TestArray_ren => TestSequence_TestArray_ren_in,
TestSequence_TestArray_wen => TestSequence_TestArray_wen_in,
TestSequence_TestArray_valid => TestSequence_TestArray_valid_in,
TestSequence_TestArray_ack => TestSequence_TestArray_ack_in,
TestSequence_TestArray_r => TestSequence_TestArray_r_in,
TestSequence_TestArray_w => TestSequence_TestArray_w_in,
TestSequence_TestChar_r => TestSequence_TestChar_r_in,
TestSequence_TestChar_w => TestSequence_TestChar_w_in,
TestSequence_TestWChar_r => TestSequence_TestWChar_r_in,
TestSequence_TestWChar_w => TestSequence_TestWChar_w_in,
TestSequence_TestLongLong_r => TestSequence_TestLongLong_r_in,
TestSequence_TestLongLong_w => TestSequence_TestLongLong_w_in,
TestSequence_TestLongDouble_r => TestSequence_TestLongDouble_r_in,
TestSequence_TestLongDouble_w => TestSequence_TestLongDouble_w_in,
TestSequence_TestLongDouble_valid_r => TestSequence_TestLongDouble_valid_r_in,
TestSequence_TestLongDouble_valid_w => TestSequence_TestLongDouble_valid_w_in,
TestMap_len => TestMap_len_in,
TestMap_addr => TestMap_addr_in,
TestMap_ready => TestMap_ready_in,
TestMap_ren => TestMap_ren_in,
TestMap_wen => TestMap_wen_in,
TestMap_valid => TestMap_valid_in,
TestMap_ack => TestMap_ack_in,
TestMap_key_r => TestMap_key_r_in,
TestMap_key_w => TestMap_key_w_in,
TestMap_value_r => TestMap_value_r_in,
TestMap_value_w => TestMap_value_w_in,
TestEnum => TestEnum_in,
TestUnion_valid => TestUnion_valid_in,
TestUnion_d => TestUnion_d_in,
TestUnion_LongU => TestUnion_LongU_in,
TestUnion_OctetU => TestUnion_OctetU_in,
TestBitmask => TestBitmask_in,
TestString_len => TestString_len_in,
TestString_addr => TestString_addr_in,
TestString_ready => TestString_ready_in,
TestString_ren => TestString_ren_in,
TestString_wen => TestString_wen_in,
TestString_valid => TestString_valid_in,
TestString_ack => TestString_ack_in,
TestString_r => TestString_r_in,
TestString_w => TestString_w_in
);
uut_r : entity work.Type2_reader_wrapper(arch)
port map (
clk => clk,
reset => reset,
start_dds => open,
ack_dds => '1',
opcode_dds => open,
instance_state_dds => open,
view_state_dds => open,
sample_state_dds => open,
instance_handle_dds => open,
max_samples_dds => open,
get_data_dds => open,
done_dds => '1',
return_code_dds => RETCODE_OK,
ready_in_dds => ready,
valid_in_dds => valid,
data_in_dds => data,
last_word_in_dds => last_word,
si_sample_state_dds => (others => '0'),
si_view_state_dds => (others => '0'),
si_instance_state_dds => (others => '0'),
si_source_timestamp_dds => TIME_ZERO,
si_instance_handle_dds => HANDLE_NIL,
si_publication_handle_dds => GUID_UNKNOWN,
si_disposed_generation_count_dds => (others => '0'),
si_no_writers_generation_count_dds => (others => '0'),
si_sample_rank_dds => (others => '0'),
si_generation_rank_dds => (others => '0'),
si_absolute_generation_rank_dds => (others => '0'),
si_valid_data_dds => '1',
si_valid_dds => '1',
si_ack_dds => open,
eoc_dds => '1',
status_dds => (others => '0'),
start_user => '0',
ack_user => open,
opcode_user => NOP,
instance_state_user => (others => '0'),
view_state_user => (others => '0'),
sample_state_user => (others => '0'),
instance_handle_user => HANDLE_NIL,
max_samples_user => (others => '0'),
get_data_user => get_data_r,
done_user => open,
return_code_user => open,
si_sample_state_user => open,
si_view_state_user => open,
si_instance_state_user => open,
si_source_timestamp_user => open,
si_instance_handle_user => open,
si_publication_handle_user => open,
si_disposed_generation_count_user => open,
si_no_writers_generation_count_user => open,
si_sample_rank_user => open,
si_generation_rank_user => open,
si_absolute_generation_rank_user => open,
si_valid_data_user => open,
si_valid_user => open,
si_ack_user => '1',
eoc_user => open,
status_user => open,
decode_error => decode_error,
id => id_out,
TestSequence_len => TestSequence_len_out,
TestSequence_addr => TestSequence_addr_out,
TestSequence_ready => TestSequence_ready_out,
TestSequence_ren => TestSequence_ren_out,
TestSequence_valid => TestSequence_valid_out,
TestSequence_ack => TestSequence_ack_out,
TestSequence_TestArray_addr => TestSequence_TestArray_addr_out,
TestSequence_TestArray_ready => TestSequence_TestArray_ready_out,
TestSequence_TestArray_ren => TestSequence_TestArray_ren_out,
TestSequence_TestArray_valid => TestSequence_TestArray_valid_out,
TestSequence_TestArray_ack => TestSequence_TestArray_ack_out,
TestSequence_TestArray => TestSequence_TestArray_out,
TestSequence_TestChar => TestSequence_TestChar_out,
TestSequence_TestWChar => TestSequence_TestWChar_out,
TestSequence_TestLongLong => TestSequence_TestLongLong_out,
TestSequence_TestLongDouble => TestSequence_TestLongDouble_out,
TestSequence_TestLongDouble_valid => TestSequence_TestLongDouble_valid_out,
TestMap_len => TestMap_len_out,
TestMap_addr => TestMap_addr_out,
TestMap_ready => TestMap_ready_out,
TestMap_ren => TestMap_ren_out,
TestMap_valid => TestMap_valid_out,
TestMap_ack => TestMap_ack_out,
TestMap_key => TestMap_key_out,
TestMap_value => TestMap_value_out,
TestEnum => TestEnum_out,
TestUnion_valid => TestUnion_valid_out,
TestUnion_d => TestUnion_d_out,
TestUnion_LongU => TestUnion_LongU_out,
TestUnion_OctetU => TestUnion_OctetU_out,
TestBitmask => TestBitmask_out,
TestString_len => TestString_len_out,
TestString_addr => TestString_addr_out,
TestString_ready => TestString_ready_out,
TestString_ren => TestString_ren_out,
TestString_valid => TestString_valid_out,
TestString_ack => TestString_ack_out,
TestString => TestString_out,
valid => valid_r
);
stimulus_prc : process
variable RV : RandomPType;
variable ID, TS_TA, TS_TC, TS_TWC, TS_TLL, TS_TLD, TM, TE, TU, TB, TS : AlertLogIDType;
procedure wait_on_sig(signal sig : std_logic) is
begin
if (sig /= '1') then
wait on sig until sig = '1';
end if;
end procedure;
begin
SetAlertLogName("Type2_wrapper - Level 1 - (Little Endian) - Encoding/Decoding");
SetAlertEnable(FAILURE, TRUE);
SetAlertEnable(ERROR, TRUE);
SetAlertEnable(WARNING, TRUE);
SetLogEnable(DEBUG, FALSE);
SetLogEnable(PASSED, FALSE);
SetLogEnable(INFO, TRUE);
RV.InitSeed(RV'instance_name);
ID := GetAlertLogID("ID", ALERTLOG_BASE_ID);
TS_TA := GetAlertLogID("TestSequence_TestArray", ALERTLOG_BASE_ID);
TS_TC := GetAlertLogID("TestSequence_TestChar", ALERTLOG_BASE_ID);
TS_TWC := GetAlertLogID("TestSequence_TestWChar", ALERTLOG_BASE_ID);
TS_TLL := GetAlertLogID("TestSequence_TestLongLong", ALERTLOG_BASE_ID);
TS_TLD := GetAlertLogID("TestSequence_TestLongDouble", ALERTLOG_BASE_ID);
TM := GetAlertLogID("TestMap", ALERTLOG_BASE_ID);
TE := GetAlertLogID("TestEnum", ALERTLOG_BASE_ID);
TU := GetAlertLogID("TestUnion", ALERTLOG_BASE_ID);
TB := GetAlertLogID("TestBitmask", ALERTLOG_BASE_ID);
TS := GetAlertLogID("TestString", ALERTLOG_BASE_ID);
Log("Setting Data in Writer Side", INFO);
start_w <= '0';
get_data_r <= '0';
-- Static
id_in <= RV.RandSlv(id_in'length);
TestEnum_in <= RV.RandSlv(TestEnum_in'length);
TestUnion_valid_in <= '1';
TestUnion_d_in <= (others => '0');
TestUnion_LongU_in <= RV.RandSlv(TestUnion_LongU_in'length);
TestUnion_OctetU_in <= RV.RandSlv(TestUnion_OctetU_in'length);
TestBitmask_in <= RV.RandSlv(TestBitmask_in'length);
-- Memory
for i in 0 to 1 loop
TestSequence_len_in <= int(2,TestSequence_len_in'length);
TestSequence_addr_in <= int(i,TestSequence_addr_in'length);
TestSequence_TestChar_w_in <= RV.RandSlv(TestSequence_TestChar_w_in'length);
TestSequence_TestWChar_w_in <= RV.RandSlv(TestSequence_TestWChar_w_in'length);
TestSequence_TestLongLong_w_in <= RV.RandSlv(TestSequence_TestLongLong_w_in'length);
TestSequence_TestLongDouble_w_in <= RV.RandSlv(TestSequence_TestLongDouble_w_in'length);
TestSequence_TestLongDouble_valid_w_in <= RV.RandSlv(1)(1);
for j in 0 to 4 loop
TestSequence_TestArray_addr_in <= int(j,TestSequence_TestArray_addr_in'length);
TestSequence_TestArray_w_in <= RV.RandSlv(TestSequence_TestArray_w_in'length);
wait_on_sig(TestSequence_TestArray_ready_in);
TestSequence_TestArray_wen_in <= '1';
wait for TEST_CLOCK_PERIOD;
TestSequence_TestArray_wen_in <= '0';
end loop;
wait_on_sig(TestSequence_ready_in);
TestSequence_wen_in <= '1';
wait for TEST_CLOCK_PERIOD;
TestSequence_wen_in <= '0';
end loop;
for i in 0 to 0 loop
TestMap_len_in <= int(1,TestMap_len_in'length);
TestMap_addr_in <= int(i,TestMap_addr_in'length);
TestMap_key_w_in <= RV.RandSlv(TestMap_key_w_in'length);
TestMap_value_w_in <= RV.RandSlv(TestMap_value_w_in'length);
wait_on_sig(TestMap_ready_in);
TestMap_wen_in <= '1';
wait for TEST_CLOCK_PERIOD;
TestMap_wen_in <= '0';
end loop;
for i in 0 to 9 loop
TestString_len_in <= int(10,TestString_len_in'length);
TestString_addr_in <= int(i,TestString_addr_in'length);
TestString_w_in <= RV.RandSlv(TestString_w_in'length);
wait_on_sig(TestString_ready_in);
TestString_wen_in <= '1';
wait for TEST_CLOCK_PERIOD;
TestString_wen_in <= '0';
end loop;
Log("Initiate Writer->Reader Transfer", INFO);
start_w <= '1';
get_data_r <= '1';
wait for TEST_CLOCK_PERIOD;
start_w <= '0';
get_data_r <= '0';
Log("Wait until Transfer done", INFO);
wait_on_sig(encode_done);
wait_on_sig(valid_r);
Log("Compare Writer and Reader Side", INFO);
AffirmIfEqual(ID, id_out, id_in);
AffirmIfEqual(TE, TestEnum_out,TestEnum_in);
AffirmIfEqual(TU, TestUnion_valid_out, TestUnion_valid_in);
if (TestUnion_valid_in = '1') then
AffirmIfEqual(TU, TestUnion_d_out, TestUnion_d_in);
--AffirmIfEqual(TU, TestUnion_LongU_out, TestUnion_LongU_in);
AffirmIfEqual(TU, TestUnion_OctetU_out, TestUnion_OctetU_in);
end if;
AffirmIfEqual(TB, TestBitmask_out, TestBitmask_in);
AffirmIfEqual(TestSequence_len_out,TestSequence_len_in);
for i in 0 to to_integer(unsigned(TestSequence_len_in)) loop
TestSequence_addr_out <= int(i,TestSequence_addr_out'length);
TestSequence_addr_in <= int(i,TestSequence_addr_in'length);
wait_on_sig(TestSequence_ready_out);
wait_on_sig(TestSequence_ready_in);
TestSequence_ren_out <= '1';
TestSequence_ren_in <= '1';
wait for TEST_CLOCK_PERIOD;
TestSequence_ren_out <= '0';
TestSequence_ren_in <= '0';
wait_on_sig(TestSequence_valid_out);
wait_on_sig(TestSequence_valid_in);
AffirmIfEqual(TS_TC, TestSequence_TestChar_out, TestSequence_TestChar_r_in);
AffirmIfEqual(TS_TWC, TestSequence_TestWChar_out, TestSequence_TestWChar_r_in);
AffirmIfEqual(TS_TLL, TestSequence_TestLongLong_out, TestSequence_TestLongLong_r_in);
AffirmIfEqual(TS_TLD, TestSequence_TestLongDouble_valid_out, TestSequence_TestLongDouble_valid_r_in);
if (TestSequence_TestLongDouble_valid_r_in = '1') then
AffirmIfEqual(TS_TLD, TestSequence_TestLongDouble_out, TestSequence_TestLongDouble_r_in);
end if;
for j in 0 to 4 loop
TestSequence_TestArray_addr_out <= int(j,TestSequence_TestArray_addr_out'length);
TestSequence_TestArray_addr_in <= int(j,TestSequence_TestArray_addr_in'length);
wait_on_sig(TestSequence_TestArray_ready_out);
wait_on_sig(TestSequence_TestArray_ready_in);
TestSequence_TestArray_ren_out <= '1';
TestSequence_TestArray_ren_in <= '1';
wait for TEST_CLOCK_PERIOD;
TestSequence_TestArray_ren_out <= '0';
TestSequence_TestArray_ren_in <= '0';
wait_on_sig(TestSequence_TestArray_valid_out);
wait_on_sig(TestSequence_TestArray_valid_in);
AffirmIfEqual(TS_TA, TestSequence_TestArray_out, TestSequence_TestArray_r_in);
TestSequence_TestArray_ack_out <= '1';
TestSequence_TestArray_ack_in <= '1';
wait for TEST_CLOCK_PERIOD;
TestSequence_TestArray_ack_out <= '0';
TestSequence_TestArray_ack_in <= '0';
end loop;
TestSequence_ack_out <= '1';
TestSequence_ack_in <= '1';
wait for TEST_CLOCK_PERIOD;
TestSequence_ack_out <= '0';
TestSequence_ack_in <= '0';
end loop;
AffirmIfEqual(TestMap_len_out, TestMap_len_in);
for i in 0 to to_integer(unsigned(TestMap_len_in)) loop
TestMap_addr_out <= int(i,TestMap_addr_out'length);
TestMap_addr_in <= int(i,TestMap_addr_in'length);
wait_on_sig(TestMap_ready_out);
wait_on_sig(TestMap_ready_in);
TestMap_ren_out <= '1';
TestMap_ren_in <= '1';
wait for TEST_CLOCK_PERIOD;
TestMap_ren_out <= '0';
TestMap_ren_in <= '0';
wait_on_sig(TestMap_valid_out);
wait_on_sig(TestMap_valid_in);
AffirmIfEqual(TM, TestMap_key_out, TestMap_key_r_in);
AffirmIfEqual(TM, TestMap_value_out, TestMap_value_r_in);
TestMap_ack_out <= '1';
TestMap_ack_in <= '1';
wait for TEST_CLOCK_PERIOD;
TestMap_ack_out <= '0';
TestMap_ack_in <= '0';
end loop;
AffirmIfEqual(TestString_len_out, TestString_len_in);
for i in 0 to to_integer(unsigned(TestString_len_in)) loop
TestString_addr_out <= int(i,TestString_addr_out'length);
TestString_addr_in <= int(i,TestString_addr_in'length);
wait_on_sig(TestString_ready_out);
wait_on_sig(TestString_ready_in);
TestString_ren_out <= '1';
TestString_ren_in <= '1';
wait for TEST_CLOCK_PERIOD;
TestString_ren_out <= '0';
TestString_ren_in <= '0';
wait_on_sig(TestString_valid_out);
wait_on_sig(TestString_valid_in);
AffirmIfEqual(TS, TestString_out, TestString_r_in);
TestString_ack_out <= '1';
TestString_ack_in <= '1';
wait for TEST_CLOCK_PERIOD;
TestString_ack_out <= '0';
TestString_ack_in <= '0';
end loop;
TranscriptOpen(RESULTS_FILE, APPEND_MODE);
SetTranscriptMirror;
ReportAlerts;
TranscriptClose;
std.env.stop;
wait;
end process;
clock_prc : process
begin
clk <= '0';
wait for TEST_CLOCK_PERIOD/2;
clk <= '1';
wait for TEST_CLOCK_PERIOD/2;
end process;
alert_prc : process(all)
begin
if rising_edge(clk) then
alertif(decode_error = '1', "The Reader signals a DECODE Error", ERROR);
end if;
end process;
watchdog : process
begin
wait for 1 ms;
Alert("Test timeout", FAILURE);
std.env.stop;
end process;
end architecture;

49
src/Tests/Type2_writer_wrapper.vhd
View File

@ -7,6 +7,9 @@ use work.rtps_config_package.all;
use work.Type2_package.all; use work.Type2_package.all;
entity Type2_writer_wrapper is entity Type2_writer_wrapper is
generic (
LITTLE_ENDIAN : std_logic := '0'
);
port ( port (
-- SYSTEM -- SYSTEM
clk : in std_logic; clk : in std_logic;
@ -473,7 +476,11 @@ begin
TestString_mem_ready_out <= TestString_ack; TestString_mem_ready_out <= TestString_ack;
end if; end if;
when WRITE_PAYLOAD_HEADER => when WRITE_PAYLOAD_HEADER =>
if (LITTLE_ENDIAN = '0') then
data_out_latch_next <= CDR_BE & x"0000"; data_out_latch_next <= CDR_BE & x"0000";
else
data_out_latch_next <= CDR_LE & x"0000";
end if;
stage_next <= PUSH; stage_next <= PUSH;
when PUSH => when PUSH =>
-- Mark Last Word -- Mark Last Word
@ -522,7 +529,7 @@ begin
target_align_next <= ALIGN_4; target_align_next <= ALIGN_4;
stage_next <= ALIGN_STREAM; stage_next <= ALIGN_STREAM;
else else
data_out_latch_next <= id; data_out_latch_next <= endian_swap(LITTLE_ENDIAN,id);
align_offset_next <= align_offset + 4; align_offset_next <= align_offset + 4;
stage_next <= PUSH; stage_next <= PUSH;
-- Next Member -- Next Member
@ -534,7 +541,7 @@ begin
target_align_next <= ALIGN_4; target_align_next <= ALIGN_4;
stage_next <= ALIGN_STREAM; stage_next <= ALIGN_STREAM;
else else
data_out_latch_next <= std_logic_vector(resize(unsigned(TestSequence_len),WORD_WIDTH)); data_out_latch_next <= endian_swap(LITTLE_ENDIAN, std_logic_vector(resize(unsigned(TestSequence_len),WORD_WIDTH)));
align_offset_next <= align_offset + 4; align_offset_next <= align_offset + 4;
stage_next <= PUSH; stage_next <= PUSH;
@ -571,7 +578,7 @@ begin
TestSequence_TestArray_mem_ready_out(TestSequence_cnt) <= '1'; TestSequence_TestArray_mem_ready_out(TestSequence_cnt) <= '1';
-- Memory Operation Guard -- Memory Operation Guard
if (TestSequence_TestArray_mem_valid_out(TestSequence_cnt) = '1') then if (TestSequence_TestArray_mem_valid_out(TestSequence_cnt) = '1') then
data_out_latch_next <= write_sub_vector(data_out_latch, TestSequence_TestArray_mem_data_out(TestSequence_cnt), to_integer(align_offset(1 downto 0)), TRUE); data_out_latch_next <= write_sub_vector(data_out_latch, endian_swap(LITTLE_ENDIAN, TestSequence_TestArray_mem_data_out(TestSequence_cnt)), to_integer(align_offset(1 downto 0)), TRUE);
align_offset_next <= align_offset + 1; align_offset_next <= align_offset + 1;
cnt_next <= 0; cnt_next <= 0;
@ -613,7 +620,7 @@ begin
TestSequence_TestChar_mem_ready_out <= '1'; TestSequence_TestChar_mem_ready_out <= '1';
-- Memory Operation Guard -- Memory Operation Guard
if (TestSequence_TestChar_mem_valid_out = '1') then if (TestSequence_TestChar_mem_valid_out = '1') then
data_out_latch_next <= write_sub_vector(data_out_latch, TestSequence_TestChar_mem_data_out, to_integer(align_offset(1 downto 0)), TRUE); data_out_latch_next <= write_sub_vector(data_out_latch, endian_swap(LITTLE_ENDIAN, TestSequence_TestChar_mem_data_out), to_integer(align_offset(1 downto 0)), TRUE);
align_offset_next <= align_offset + 1; align_offset_next <= align_offset + 1;
encode_stage_next <= WRITE_TESTSEQUENCE_TESTWCHAR; encode_stage_next <= WRITE_TESTSEQUENCE_TESTWCHAR;
@ -649,7 +656,7 @@ begin
TestSequence_TestWChar_mem_ready_out <= '1'; TestSequence_TestWChar_mem_ready_out <= '1';
-- Memory Operation Guard -- Memory Operation Guard
if (TestSequence_TestWChar_mem_valid_out = '1') then if (TestSequence_TestWChar_mem_valid_out = '1') then
data_out_latch_next <= write_sub_vector(data_out_latch, TestSequence_TestWChar_mem_data_out, to_integer(align_offset(1 downto 1)), TRUE); data_out_latch_next <= write_sub_vector(data_out_latch, endian_swap(LITTLE_ENDIAN, TestSequence_TestWChar_mem_data_out), to_integer(align_offset(1 downto 1)), TRUE);
align_offset_next <= align_offset + 2; align_offset_next <= align_offset + 2;
encode_stage_next <= WRITE_TESTSEQUENCE_TESTLONGLONG; encode_stage_next <= WRITE_TESTSEQUENCE_TESTLONGLONG;
@ -684,7 +691,7 @@ begin
when 1 => when 1 =>
-- Memory Operation Guard -- Memory Operation Guard
if (TestSequence_TestLongLong_mem_valid_out = '1') then if (TestSequence_TestLongLong_mem_valid_out = '1') then
data_out_latch_next <= get_sub_vector(TestSequence_TestLongLong_mem_data_out, 0, WORD_WIDTH, TRUE); data_out_latch_next <= get_sub_vector(endian_swap(LITTLE_ENDIAN, TestSequence_TestLongLong_mem_data_out), 0, WORD_WIDTH, TRUE);
stage_next <= PUSH; stage_next <= PUSH;
cnt_next <= cnt + 1; cnt_next <= cnt + 1;
end if; end if;
@ -693,7 +700,7 @@ begin
TestSequence_TestLongLong_mem_ready_out <= '1'; TestSequence_TestLongLong_mem_ready_out <= '1';
-- Memory Operation Guard -- Memory Operation Guard
if (TestSequence_TestLongLong_mem_valid_out = '1') then if (TestSequence_TestLongLong_mem_valid_out = '1') then
data_out_latch_next <= get_sub_vector(TestSequence_TestLongLong_mem_data_out, 1, WORD_WIDTH, TRUE); data_out_latch_next <= get_sub_vector(endian_swap(LITTLE_ENDIAN, TestSequence_TestLongLong_mem_data_out), 1, WORD_WIDTH, TRUE);
stage_next <= PUSH; stage_next <= PUSH;
align_offset_next <= align_offset + 8; align_offset_next <= align_offset + 8;
encode_stage_next <= WRITE_TESTSEQUENCE_TESTLONGDOUBLE; encode_stage_next <= WRITE_TESTSEQUENCE_TESTLONGDOUBLE;
@ -744,7 +751,7 @@ begin
when 2 => when 2 =>
-- Memory Operation Guard -- Memory Operation Guard
if (TestSequence_TestLongDouble_mem_valid_out = '1') then if (TestSequence_TestLongDouble_mem_valid_out = '1') then
data_out_latch_next <= get_sub_vector(TestSequence_TestLongDouble_mem_data_out(CDR_LONG_DOUBLE_WIDTH-1 downto 0), 0, WORD_WIDTH, TRUE); data_out_latch_next <= get_sub_vector(endian_swap(LITTLE_ENDIAN, TestSequence_TestLongDouble_mem_data_out(CDR_LONG_DOUBLE_WIDTH-1 downto 0)), 0, WORD_WIDTH, TRUE);
stage_next <= PUSH; stage_next <= PUSH;
cnt_next <= cnt + 1; cnt_next <= cnt + 1;
end if; end if;
@ -752,7 +759,7 @@ begin
when 3 => when 3 =>
-- Memory Operation Guard -- Memory Operation Guard
if (TestSequence_TestLongDouble_mem_valid_out = '1') then if (TestSequence_TestLongDouble_mem_valid_out = '1') then
data_out_latch_next <= get_sub_vector(TestSequence_TestLongDouble_mem_data_out(CDR_LONG_DOUBLE_WIDTH-1 downto 0), 1, WORD_WIDTH, TRUE); data_out_latch_next <= get_sub_vector(endian_swap(LITTLE_ENDIAN, TestSequence_TestLongDouble_mem_data_out(CDR_LONG_DOUBLE_WIDTH-1 downto 0)), 1, WORD_WIDTH, TRUE);
stage_next <= PUSH; stage_next <= PUSH;
cnt_next <= cnt + 1; cnt_next <= cnt + 1;
end if; end if;
@ -760,7 +767,7 @@ begin
when 4 => when 4 =>
-- Memory Operation Guard -- Memory Operation Guard
if (TestSequence_TestLongDouble_mem_valid_out = '1') then if (TestSequence_TestLongDouble_mem_valid_out = '1') then
data_out_latch_next <= get_sub_vector(TestSequence_TestLongDouble_mem_data_out(CDR_LONG_DOUBLE_WIDTH-1 downto 0), 2, WORD_WIDTH, TRUE); data_out_latch_next <= get_sub_vector(endian_swap(LITTLE_ENDIAN, TestSequence_TestLongDouble_mem_data_out(CDR_LONG_DOUBLE_WIDTH-1 downto 0)), 2, WORD_WIDTH, TRUE);
stage_next <= PUSH; stage_next <= PUSH;
cnt_next <= cnt + 1; cnt_next <= cnt + 1;
end if; end if;
@ -769,7 +776,7 @@ begin
TestSequence_TestLongDouble_mem_ready_out <= '1'; TestSequence_TestLongDouble_mem_ready_out <= '1';
-- Memory Operation Guard -- Memory Operation Guard
if (TestSequence_TestLongDouble_mem_valid_out = '1') then if (TestSequence_TestLongDouble_mem_valid_out = '1') then
data_out_latch_next <= get_sub_vector(TestSequence_TestLongDouble_mem_data_out(CDR_LONG_DOUBLE_WIDTH-1 downto 0), 3, WORD_WIDTH, TRUE); data_out_latch_next <= get_sub_vector(endian_swap(LITTLE_ENDIAN, TestSequence_TestLongDouble_mem_data_out(CDR_LONG_DOUBLE_WIDTH-1 downto 0)), 3, WORD_WIDTH, TRUE);
stage_next <= PUSH; stage_next <= PUSH;
align_offset_next <= align_offset + 16; align_offset_next <= align_offset + 16;
encode_stage_next <= TESTSEQUENCE_MEMBER_END; encode_stage_next <= TESTSEQUENCE_MEMBER_END;
@ -796,7 +803,7 @@ begin
target_align_next <= ALIGN_4; target_align_next <= ALIGN_4;
stage_next <= ALIGN_STREAM; stage_next <= ALIGN_STREAM;
else else
data_out_latch_next <= std_logic_vector(resize(unsigned(TestMap_len),WORD_WIDTH)); data_out_latch_next <= endian_swap(LITTLE_ENDIAN, std_logic_vector(resize(unsigned(TestMap_len),WORD_WIDTH)));
align_offset_next <= align_offset + 4; align_offset_next <= align_offset + 4;
stage_next <= PUSH; stage_next <= PUSH;
@ -830,7 +837,7 @@ begin
when 1 => when 1 =>
-- Memory Operation Guard -- Memory Operation Guard
if (TestMap_mem_valid_out = '1') then if (TestMap_mem_valid_out = '1') then
data_out_latch_next <= write_sub_vector(data_out_latch, TestMap_mem_data_out(CDR_OCTET_WIDTH+CDR_SHORT_WIDTH-1 downto CDR_SHORT_WIDTH), to_integer(align_offset(1 downto 0)), TRUE); data_out_latch_next <= write_sub_vector(data_out_latch, endian_swap(LITTLE_ENDIAN, TestMap_mem_data_out(CDR_OCTET_WIDTH+CDR_SHORT_WIDTH-1 downto CDR_SHORT_WIDTH)), to_integer(align_offset(1 downto 0)), TRUE);
align_offset_next <= align_offset + 1; align_offset_next <= align_offset + 1;
encode_stage_next <= WRITE_TESTMAP_VALUE; encode_stage_next <= WRITE_TESTMAP_VALUE;
@ -853,7 +860,7 @@ begin
TestMap_mem_ready_out <= '1'; TestMap_mem_ready_out <= '1';
-- Memory Operation Guard -- Memory Operation Guard
if (TestMap_mem_valid_out = '1') then if (TestMap_mem_valid_out = '1') then
data_out_latch_next <= write_sub_vector(data_out_latch, TestMap_mem_data_out(CDR_SHORT_WIDTH-1 downto 0), to_integer(align_offset(1 downto 1)), TRUE); data_out_latch_next <= write_sub_vector(data_out_latch, endian_swap(LITTLE_ENDIAN, TestMap_mem_data_out(CDR_SHORT_WIDTH-1 downto 0)), to_integer(align_offset(1 downto 1)), TRUE);
align_offset_next <= align_offset + 2; align_offset_next <= align_offset + 2;
encode_stage_next <= TESTMAP_MEMBER_END; encode_stage_next <= TESTMAP_MEMBER_END;
@ -881,7 +888,7 @@ begin
target_align_next <= ALIGN_1; target_align_next <= ALIGN_1;
stage_next <= ALIGN_STREAM; stage_next <= ALIGN_STREAM;
else else
data_out_latch_next <= write_sub_vector(data_out_latch, std_logic_vector(resize(unsigned(TestEnum),TESTENUM_CDR_WIDTH)), to_integer(align_offset(1 downto 0)), TRUE); data_out_latch_next <= write_sub_vector(data_out_latch, endian_swap(LITTLE_ENDIAN, std_logic_vector(resize(unsigned(TestEnum),TESTENUM_CDR_WIDTH))), to_integer(align_offset(1 downto 0)), TRUE);
align_offset_next <= align_offset + 1; align_offset_next <= align_offset + 1;
-- Next Member -- Next Member
@ -925,7 +932,7 @@ begin
stage_next <= PUSH; stage_next <= PUSH;
-- WRITE Discriminator -- WRITE Discriminator
when 1 => when 1 =>
data_out_latch_next <= write_sub_vector(data_out_latch, TestUnion_d, to_integer(align_offset(1 downto 0)), TRUE); data_out_latch_next <= write_sub_vector(data_out_latch, endian_swap(LITTLE_ENDIAN, TestUnion_d), to_integer(align_offset(1 downto 0)), TRUE);
align_offset_next <= align_offset + 1; align_offset_next <= align_offset + 1;
case (TestUnion_d) is case (TestUnion_d) is
@ -949,7 +956,7 @@ begin
target_align_next <= ALIGN_4; target_align_next <= ALIGN_4;
stage_next <= ALIGN_STREAM; stage_next <= ALIGN_STREAM;
else else
data_out_latch_next <= TestUnion_LongU; data_out_latch_next <= endian_swap(LITTLE_ENDIAN, TestUnion_LongU);
align_offset_next <= align_offset + 4; align_offset_next <= align_offset + 4;
-- Next Member -- Next Member
@ -962,7 +969,7 @@ begin
target_align_next <= ALIGN_1; target_align_next <= ALIGN_1;
stage_next <= ALIGN_STREAM; stage_next <= ALIGN_STREAM;
else else
data_out_latch_next <= write_sub_vector(data_out_latch, TestUnion_OctetU, to_integer(align_offset(1 downto 0)), TRUE); data_out_latch_next <= write_sub_vector(data_out_latch, endian_swap(LITTLE_ENDIAN, TestUnion_OctetU), to_integer(align_offset(1 downto 0)), TRUE);
align_offset_next <= align_offset + 1; align_offset_next <= align_offset + 1;
-- Next Member -- Next Member
@ -979,7 +986,7 @@ begin
target_align_next <= ALIGN_2; target_align_next <= ALIGN_2;
stage_next <= ALIGN_STREAM; stage_next <= ALIGN_STREAM;
else else
data_out_latch_next <= write_sub_vector(data_out_latch, std_logic_vector(resize(unsigned(TestBitmask),TESTBITMASK_CDR_WIDTH)), to_integer(align_offset(1 downto 1)), TRUE); data_out_latch_next <= write_sub_vector(data_out_latch, endian_swap(LITTLE_ENDIAN, std_logic_vector(resize(unsigned(TestBitmask),TESTBITMASK_CDR_WIDTH))), to_integer(align_offset(1 downto 1)), TRUE);
align_offset_next <= align_offset + 2; align_offset_next <= align_offset + 2;
-- Next Member -- Next Member
@ -996,7 +1003,7 @@ begin
target_align_next <= ALIGN_4; target_align_next <= ALIGN_4;
stage_next <= ALIGN_STREAM; stage_next <= ALIGN_STREAM;
else else
data_out_latch_next <= std_logic_vector(resize(unsigned(TestString_len),WORD_WIDTH)); data_out_latch_next <= endian_swap(LITTLE_ENDIAN, std_logic_vector(resize(unsigned(TestString_len),WORD_WIDTH)));
align_offset_next <= align_offset + 4; align_offset_next <= align_offset + 4;
stage_next <= PUSH; stage_next <= PUSH;
@ -1032,7 +1039,7 @@ begin
TestString_mem_ready_out <= '1'; TestString_mem_ready_out <= '1';
-- Memory Operation Guard -- Memory Operation Guard
if (TestString_mem_valid_out = '1') then if (TestString_mem_valid_out = '1') then
data_out_latch_next <= write_sub_vector(data_out_latch, TestString_mem_data_out, to_integer(align_offset(1 downto 0)), TRUE); data_out_latch_next <= write_sub_vector(data_out_latch, endian_swap(LITTLE_ENDIAN, TestString_mem_data_out), to_integer(align_offset(1 downto 0)), TRUE);
align_offset_next <= align_offset + 1; align_offset_next <= align_offset + 1;
cnt_next <= 0; cnt_next <= 0;

4
src/Tests/testbench.pro
View File

@ -89,7 +89,9 @@ analyze Type2_writer_wrapper.vhd
analyze Type2_key_holder.vhd analyze Type2_key_holder.vhd
analyze test_md5.vhd analyze test_md5.vhd
analyze Level_1/L1_Type2_wrapper_test1.vhd analyze Level_1/L1_Type2_wrapper_test1.vhd
analyze Level_1/L1_Type2_wrapper_test2.vhd
analyze Level_1/L1_Type2_key_holder_test1.vhd analyze Level_1/L1_Type2_key_holder_test1.vhd
analyze Level_1/L1_Type2_key_holder_test2.vhd
simulate L0_rtps_handler_test1 simulate L0_rtps_handler_test1
simulate L0_rtps_handler_test2 simulate L0_rtps_handler_test2
@ -153,4 +155,6 @@ simulate L0_dds_reader_test5_arzkriu
simulate L0_dds_reader_test6_arzkriu simulate L0_dds_reader_test6_arzkriu
simulate L0_dds_reader_test7_arzkriu simulate L0_dds_reader_test7_arzkriu
simulate L1_Type2_wrapper_test1 simulate L1_Type2_wrapper_test1
simulate L1_Type2_wrapper_test2
simulate L1_Type2_key_holder_test1 simulate L1_Type2_key_holder_test1
simulate L1_Type2_key_holder_test2

6
src/rtps_config_package.vhd
View File

@ -1168,15 +1168,17 @@ package body rtps_config_package is
-- Returns the 'data' argument either as is, or with reversed Byte order, depending on the -- Returns the 'data' argument either as is, or with reversed Byte order, depending on the
-- 'swap' argument. -- 'swap' argument.
function endian_swap(swap : std_logic; data : std_logic_vector) return std_logic_vector is function endian_swap(swap : std_logic; data : std_logic_vector) return std_logic_vector is
variable ret : std_logic_vector(data'range); variable ret, ref : std_logic_vector(data'length-1 downto 0);
begin begin
-- Assert that Data Signal is Byte aligned -- Assert that Data Signal is Byte aligned
assert (data'length mod 8 = 0) severity failure; assert (data'length mod 8 = 0) severity failure;
-- NOTE: The input signal is explicitly copied over to make sure the slice is (length-1 downto 0)
ref := data;
-- Little Endian -- Little Endian
if (swap = '1') then if (swap = '1') then
-- Reverse byte Order -- Reverse byte Order
for i in 0 to (data'length/8)-1 loop for i in 0 to (data'length/8)-1 loop
ret(i*8+8-1 downto i*8) := data(((data'length/8)-1-i)*8+8-1 downto ((data'length/8)-1-i)*8); ret(i*8+8-1 downto i*8) := ref(((data'length/8)-1-i)*8+8-1 downto ((data'length/8)-1-i)*8);
end loop; end loop;
-- Big Endian -- Big Endian
else else