Update and resynthesize all examples in GHRD Project

syn/DE10_NANO_SoC_GHRD/test_fpga_hw.tcl.dds_loopback.BAK

@@ -0,0 +1,157 @@
+# TCL File Generated by Component Editor 21.1
+# Sat Jul 29 22:19:17 GMT+02:00 2023
+# DO NOT MODIFY
+
+
+# 
+# test_fpga "test_fpga" v1.0
+#  2023.07.29.22:19:17
+# Test PL-PS Communication
+# 
+
+# 
+# request TCL package from ACDS 16.1
+# 
+package require -exact qsys 16.1
+
+
+# 
+# module test_fpga
+# 
+set_module_property DESCRIPTION "Test PL-PS Communication"
+set_module_property NAME test_fpga
+set_module_property VERSION 1.0
+set_module_property INTERNAL false
+set_module_property OPAQUE_ADDRESS_MAP true
+set_module_property AUTHOR ""
+set_module_property DISPLAY_NAME test_fpga
+set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
+set_module_property EDITABLE true
+set_module_property REPORT_TO_TALKBACK false
+set_module_property ALLOW_GREYBOX_GENERATION false
+set_module_property REPORT_HIERARCHY false
+
+
+# 
+# file sets
+# 
+add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
+set_fileset_property QUARTUS_SYNTH TOP_LEVEL test_top
+set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
+set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
+add_fileset_file test_top.vhd VHDL PATH ../test_top.vhd TOP_LEVEL_FILE
+add_fileset_file syn_config.vhd VHDL PATH ../syn_config.vhd
+add_fileset_file Avalon_MM_wrapper.vhd VHDL PATH ../../src/Avalon_MM_wrapper.vhd
+add_fileset_file FWFT_FIFO.vhd VHDL PATH ../../src/FWFT_FIFO.vhd
+add_fileset_file FWFT_FIFO_Altera.vhd VHDL PATH ../../src/FWFT_FIFO_Altera.vhd
+add_fileset_file FWFT_FIFO_cfg.vhd VHDL PATH ../../src/FWFT_FIFO_cfg.vhd
+add_fileset_file dds_reader.vhd VHDL PATH ../../src/dds_reader.vhd
+add_fileset_file dds_writer.vhd VHDL PATH ../../src/dds_writer.vhd
+add_fileset_file dp_mem_ctrl.vhd VHDL PATH ../../src/dp_mem_ctrl.vhd
+add_fileset_file dual_port_ram.vhd VHDL PATH ../../src/dual_port_ram.vhd
+add_fileset_file dual_port_ram_Altera.vhd VHDL PATH ../../src/dual_port_ram_Altera.vhd
+add_fileset_file dual_port_ram_cfg.vhd VHDL PATH ../../src/dual_port_ram_cfg.vhd
+add_fileset_file math_pkg.vhd VHDL PATH ../../src/math_pkg.vhd
+add_fileset_file mem_ctrl.vhd VHDL PATH ../../src/mem_ctrl.vhd
+add_fileset_file mult.vhd VHDL PATH ../../src/mult.vhd
+add_fileset_file mult_Altera.vhd VHDL PATH ../../src/mult_Altera.vhd
+add_fileset_file mult_cfg.vhd VHDL PATH ../../src/mult_cfg.vhd
+add_fileset_file rtps_config_package.vhd VHDL PATH ../../src/rtps_config_package.vhd
+add_fileset_file rtps_discovery_module.vhd VHDL PATH ../../src/rtps_discovery_module.vhd
+add_fileset_file rtps_handler.vhd VHDL PATH ../../src/rtps_handler.vhd
+add_fileset_file rtps_out.vhd VHDL PATH ../../src/rtps_out.vhd
+add_fileset_file rtps_package.vhd VHDL PATH ../../src/rtps_package.vhd
+add_fileset_file rtps_reader.vhd VHDL PATH ../../src/rtps_reader.vhd
+add_fileset_file rtps_writer.vhd VHDL PATH ../../src/rtps_writer.vhd
+add_fileset_file single_port_ram.vhd VHDL PATH ../../src/single_port_ram.vhd
+add_fileset_file single_port_ram_Altera.vhd VHDL PATH ../../src/single_port_ram_Altera.vhd
+add_fileset_file single_port_ram_cfg.vhd VHDL PATH ../../src/single_port_ram_cfg.vhd
+add_fileset_file vector_FIFO.vhd VHDL PATH ../../src/vector_FIFO.vhd
+add_fileset_file Type1_cfg.vhd VHDL PATH ../../src/Tests/Type1_cfg.vhd
+add_fileset_file Type1_key_holder.vhd VHDL PATH ../../src/Tests/Type1_key_holder.vhd
+add_fileset_file Type1_package.vhd VHDL PATH ../../src/Tests/Type1_package.vhd
+add_fileset_file Type1_reader_interface.vhd VHDL PATH ../../src/Tests/Type1_reader_interface.vhd
+add_fileset_file Type1_writer_interface.vhd VHDL PATH ../../src/Tests/Type1_writer_interface.vhd
+add_fileset_file test_loopback.vhd VHDL PATH ../../src/Tests/test_loopback.vhd
+add_fileset_file L2_Testbench_Lib4.vhd VHDL PATH ../../src/Tests/Level_2/L2_Testbench_Lib4.vhd
+add_fileset_file key_holder.vhd VHDL PATH ../../src/key_holder.vhd
+add_fileset_file key_hash_generator.vhd VHDL PATH ../../src/key_hash_generator.vhd
+add_fileset_file verbatim_key_hash_generator.vhd VHDL PATH ../../src/verbatim_key_hash_generator.vhd
+
+
+# 
+# parameters
+# 
+
+
+# 
+# display items
+# 
+
+
+# 
+# connection point clock
+# 
+add_interface clock clock end
+set_interface_property clock clockRate 0
+set_interface_property clock ENABLED true
+set_interface_property clock EXPORT_OF ""
+set_interface_property clock PORT_NAME_MAP ""
+set_interface_property clock CMSIS_SVD_VARIABLES ""
+set_interface_property clock SVD_ADDRESS_GROUP ""
+
+add_interface_port clock clk clk Input 1
+
+
+# 
+# connection point reset
+# 
+add_interface reset reset end
+set_interface_property reset associatedClock clock
+set_interface_property reset synchronousEdges DEASSERT
+set_interface_property reset ENABLED true
+set_interface_property reset EXPORT_OF ""
+set_interface_property reset PORT_NAME_MAP ""
+set_interface_property reset CMSIS_SVD_VARIABLES ""
+set_interface_property reset SVD_ADDRESS_GROUP ""
+
+add_interface_port reset reset reset Input 1
+
+
+# 
+# connection point avalon_slave_0
+# 
+add_interface avalon_slave_0 avalon end
+set_interface_property avalon_slave_0 addressUnits WORDS
+set_interface_property avalon_slave_0 associatedClock clock
+set_interface_property avalon_slave_0 associatedReset reset
+set_interface_property avalon_slave_0 bitsPerSymbol 8
+set_interface_property avalon_slave_0 burstOnBurstBoundariesOnly false
+set_interface_property avalon_slave_0 burstcountUnits WORDS
+set_interface_property avalon_slave_0 explicitAddressSpan 0
+set_interface_property avalon_slave_0 holdTime 0
+set_interface_property avalon_slave_0 linewrapBursts false
+set_interface_property avalon_slave_0 maximumPendingReadTransactions 0
+set_interface_property avalon_slave_0 maximumPendingWriteTransactions 0
+set_interface_property avalon_slave_0 readLatency 0
+set_interface_property avalon_slave_0 readWaitTime 1
+set_interface_property avalon_slave_0 setupTime 0
+set_interface_property avalon_slave_0 timingUnits Cycles
+set_interface_property avalon_slave_0 writeWaitTime 0
+set_interface_property avalon_slave_0 ENABLED true
+set_interface_property avalon_slave_0 EXPORT_OF ""
+set_interface_property avalon_slave_0 PORT_NAME_MAP ""
+set_interface_property avalon_slave_0 CMSIS_SVD_VARIABLES ""
+set_interface_property avalon_slave_0 SVD_ADDRESS_GROUP ""
+
+add_interface_port avalon_slave_0 address address Input 2
+add_interface_port avalon_slave_0 read read Input 1
+add_interface_port avalon_slave_0 write write Input 1
+add_interface_port avalon_slave_0 readdata readdata Output 32
+add_interface_port avalon_slave_0 writedata writedata Input 32
+add_interface_port avalon_slave_0 waitrequest waitrequest Output 1
+set_interface_assignment avalon_slave_0 embeddedsw.configuration.isFlash 0
+set_interface_assignment avalon_slave_0 embeddedsw.configuration.isMemoryDevice 0
+set_interface_assignment avalon_slave_0 embeddedsw.configuration.isNonVolatileStorage 0
+set_interface_assignment avalon_slave_0 embeddedsw.configuration.isPrintableDevice 0
+

syn/DE10_NANO_SoC_GHRD/test_fpga_hw.tcl.loopback.BAK

@@ -0,0 +1,129 @@
+# TCL File Generated by Component Editor 21.1
+# Thu Jul 27 13:57:40 GMT+02:00 2023
+# DO NOT MODIFY
+
+
+# 
+# test_fpga "test_fpga" v1.0
+#  2023.07.27.13:57:40
+# Test PL-PS Communication
+# 
+
+# 
+# request TCL package from ACDS 16.1
+# 
+package require -exact qsys 16.1
+
+
+# 
+# module test_fpga
+# 
+set_module_property DESCRIPTION "Test PL-PS Communication"
+set_module_property NAME test_fpga
+set_module_property VERSION 1.0
+set_module_property INTERNAL false
+set_module_property OPAQUE_ADDRESS_MAP true
+set_module_property AUTHOR ""
+set_module_property DISPLAY_NAME test_fpga
+set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
+set_module_property EDITABLE true
+set_module_property REPORT_TO_TALKBACK false
+set_module_property ALLOW_GREYBOX_GENERATION false
+set_module_property REPORT_HIERARCHY false
+
+
+# 
+# file sets
+# 
+add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
+set_fileset_property QUARTUS_SYNTH TOP_LEVEL test_top
+set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
+set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
+add_fileset_file test_top.vhd VHDL PATH ../test_top.vhd TOP_LEVEL_FILE
+add_fileset_file FWFT_FIFO.vhd VHDL PATH ../../src/FWFT_FIFO.vhd
+add_fileset_file FWFT_FIFO_Altera.vhd VHDL PATH ../../src/FWFT_FIFO_Altera.vhd
+add_fileset_file FWFT_FIFO_cfg.vhd VHDL PATH ../../src/FWFT_FIFO_cfg.vhd
+add_fileset_file Avalon_MM_wrapper.vhd VHDL PATH ../../src/Avalon_MM_wrapper.vhd
+add_fileset_file loopback.vhd VHDL PATH ../loopback.vhd
+add_fileset_file math_pkg.vhd VHDL PATH ../../src/math_pkg.vhd
+add_fileset_file rtps_config_package.vhd VHDL PATH ../../src/rtps_config_package.vhd
+add_fileset_file rtps_package.vhd VHDL PATH ../../src/rtps_package.vhd
+add_fileset_file TEMPLATE_user_config.vhd VHDL PATH ../../src/TEMPLATE_user_config.vhd
+
+
+# 
+# parameters
+# 
+
+
+# 
+# display items
+# 
+
+
+# 
+# connection point clock
+# 
+add_interface clock clock end
+set_interface_property clock clockRate 0
+set_interface_property clock ENABLED true
+set_interface_property clock EXPORT_OF ""
+set_interface_property clock PORT_NAME_MAP ""
+set_interface_property clock CMSIS_SVD_VARIABLES ""
+set_interface_property clock SVD_ADDRESS_GROUP ""
+
+add_interface_port clock clk clk Input 1
+
+
+# 
+# connection point reset
+# 
+add_interface reset reset end
+set_interface_property reset associatedClock clock
+set_interface_property reset synchronousEdges DEASSERT
+set_interface_property reset ENABLED true
+set_interface_property reset EXPORT_OF ""
+set_interface_property reset PORT_NAME_MAP ""
+set_interface_property reset CMSIS_SVD_VARIABLES ""
+set_interface_property reset SVD_ADDRESS_GROUP ""
+
+add_interface_port reset reset reset Input 1
+
+
+# 
+# connection point avalon_slave_0
+# 
+add_interface avalon_slave_0 avalon end
+set_interface_property avalon_slave_0 addressUnits WORDS
+set_interface_property avalon_slave_0 associatedClock clock
+set_interface_property avalon_slave_0 associatedReset reset
+set_interface_property avalon_slave_0 bitsPerSymbol 8
+set_interface_property avalon_slave_0 burstOnBurstBoundariesOnly false
+set_interface_property avalon_slave_0 burstcountUnits WORDS
+set_interface_property avalon_slave_0 explicitAddressSpan 0
+set_interface_property avalon_slave_0 holdTime 0
+set_interface_property avalon_slave_0 linewrapBursts false
+set_interface_property avalon_slave_0 maximumPendingReadTransactions 0
+set_interface_property avalon_slave_0 maximumPendingWriteTransactions 0
+set_interface_property avalon_slave_0 readLatency 0
+set_interface_property avalon_slave_0 readWaitTime 1
+set_interface_property avalon_slave_0 setupTime 0
+set_interface_property avalon_slave_0 timingUnits Cycles
+set_interface_property avalon_slave_0 writeWaitTime 0
+set_interface_property avalon_slave_0 ENABLED true
+set_interface_property avalon_slave_0 EXPORT_OF ""
+set_interface_property avalon_slave_0 PORT_NAME_MAP ""
+set_interface_property avalon_slave_0 CMSIS_SVD_VARIABLES ""
+set_interface_property avalon_slave_0 SVD_ADDRESS_GROUP ""
+
+add_interface_port avalon_slave_0 address address Input 2
+add_interface_port avalon_slave_0 read read Input 1
+add_interface_port avalon_slave_0 write write Input 1
+add_interface_port avalon_slave_0 readdata readdata Output 32
+add_interface_port avalon_slave_0 writedata writedata Input 32
+add_interface_port avalon_slave_0 waitrequest waitrequest Output 1
+set_interface_assignment avalon_slave_0 embeddedsw.configuration.isFlash 0
+set_interface_assignment avalon_slave_0 embeddedsw.configuration.isMemoryDevice 0
+set_interface_assignment avalon_slave_0 embeddedsw.configuration.isNonVolatileStorage 0
+set_interface_assignment avalon_slave_0 embeddedsw.configuration.isPrintableDevice 0
+

syn/DE10_NANO_SoC_GHRD/test_fpga_hw.tcl.ros_action.BAK

@@ -1,11 +1,11 @@
 # TCL File Generated by Component Editor 21.1
-# Thu Apr 14 15:21:46 GMT+02:00 2022
+# Sat Jul 29 18:35:32 GMT+02:00 2023
 # DO NOT MODIFY
 
 
 # 
 # test_fpga "test_fpga" v1.0
-#  2022.04.14.15:21:46
+#  2023.07.29.18:35:32
 # Test PL-PS Communication
 # 
 
@@ -39,43 +39,37 @@ add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
 set_fileset_property QUARTUS_SYNTH TOP_LEVEL test_top
 set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
 set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
-add_fileset_file test_top.vhd VHDL PATH ../../syn/test_top.vhd TOP_LEVEL_FILE
+add_fileset_file test_top.vhd VHDL PATH ../test_top.vhd TOP_LEVEL_FILE
 add_fileset_file Avalon_MM_wrapper.vhd VHDL PATH ../../src/Avalon_MM_wrapper.vhd
-add_fileset_file L2_testbench_Lib4.vhd VHDL PATH ../../src/Tests/Level_2/L2_Testbench_Lib4.vhd
 add_fileset_file FWFT_FIFO.vhd VHDL PATH ../../src/FWFT_FIFO.vhd
 add_fileset_file FWFT_FIFO_Altera.vhd VHDL PATH ../../src/FWFT_FIFO_Altera.vhd
 add_fileset_file FWFT_FIFO_cfg.vhd VHDL PATH ../../src/FWFT_FIFO_cfg.vhd
 add_fileset_file dds_reader.vhd VHDL PATH ../../src/dds_reader.vhd
 add_fileset_file dds_writer.vhd VHDL PATH ../../src/dds_writer.vhd
-add_fileset_file key_hash_generator.vhd VHDL PATH ../../src/key_hash_generator.vhd
-add_fileset_file key_holder.vhd VHDL PATH ../../src/key_holder.vhd
-add_fileset_file mem_ctrl.vhd VHDL PATH ../../src/mem_ctrl.vhd
-add_fileset_file rtps_discovery_module.vhd VHDL PATH ../../src/rtps_discovery_module.vhd
-add_fileset_file rtps_config_package.vhd VHDL PATH ../../src/rtps_config_package.vhd
-add_fileset_file math_pkg.vhd VHDL PATH ../../src/math_pkg.vhd
-add_fileset_file rtps_package.vhd VHDL PATH ../../src/rtps_package.vhd
-add_fileset_file Type1_cfg.vhd VHDL PATH ../../src/Tests/Type1_cfg.vhd
-add_fileset_file Type1_key_holder.vhd VHDL PATH ../../src/Tests/Type1_key_holder.vhd
-add_fileset_file Type1_package.vhd VHDL PATH ../../src/Tests/Type1_package.vhd
-add_fileset_file Type1_reader_interface.vhd VHDL PATH ../../src/Tests/Type1_reader_interface.vhd
-add_fileset_file Type1_writer_interface.vhd VHDL PATH ../../src/Tests/Type1_writer_interface.vhd
-add_fileset_file rtps_handler.vhd VHDL PATH ../../src/rtps_handler.vhd
-add_fileset_file rtps_reader.vhd VHDL PATH ../../src/rtps_reader.vhd
-add_fileset_file rtps_writer.vhd VHDL PATH ../../src/rtps_writer.vhd
-add_fileset_file rtps_out.vhd VHDL PATH ../../src/rtps_out.vhd
-add_fileset_file test_loopback.vhd VHDL PATH ../../src/Tests/test_loopback.vhd
-add_fileset_file single_port_ram.vhd VHDL PATH ../../src/single_port_ram.vhd
-add_fileset_file single_port_ram_Altera.vhd VHDL PATH ../../src/single_port_ram_Altera.vhd
-add_fileset_file single_port_ram_cfg.vhd VHDL PATH ../../src/single_port_ram_cfg.vhd
 add_fileset_file dp_mem_ctrl.vhd VHDL PATH ../../src/dp_mem_ctrl.vhd
 add_fileset_file dual_port_ram.vhd VHDL PATH ../../src/dual_port_ram.vhd
 add_fileset_file dual_port_ram_Altera.vhd VHDL PATH ../../src/dual_port_ram_Altera.vhd
 add_fileset_file dual_port_ram_cfg.vhd VHDL PATH ../../src/dual_port_ram_cfg.vhd
+add_fileset_file mult.vhd VHDL PATH ../../src/mult.vhd
+add_fileset_file mult_Altera.vhd VHDL PATH ../../src/mult_Altera.vhd
+add_fileset_file mult_cfg.vhd VHDL PATH ../../src/mult_cfg.vhd
+add_fileset_file rtps_config_package.vhd VHDL PATH ../../src/rtps_config_package.vhd
+add_fileset_file rtps_discovery_module.vhd VHDL PATH ../../src/rtps_discovery_module.vhd
+add_fileset_file rtps_handler.vhd VHDL PATH ../../src/rtps_handler.vhd
+add_fileset_file rtps_out.vhd VHDL PATH ../../src/rtps_out.vhd
+add_fileset_file rtps_package.vhd VHDL PATH ../../src/rtps_package.vhd
+add_fileset_file rtps_reader.vhd VHDL PATH ../../src/rtps_reader.vhd
+add_fileset_file rtps_writer.vhd VHDL PATH ../../src/rtps_writer.vhd
+add_fileset_file single_port_ram.vhd VHDL PATH ../../src/single_port_ram.vhd
+add_fileset_file single_port_ram_Altera.vhd VHDL PATH ../../src/single_port_ram_Altera.vhd
+add_fileset_file single_port_ram_cfg.vhd VHDL PATH ../../src/single_port_ram_cfg.vhd
+add_fileset_file vector_FIFO.vhd VHDL PATH ../../src/vector_FIFO.vhd
 add_fileset_file dds_user_config.vhd VHDL PATH ../../src/ros2/dds_user_config.vhd
+add_fileset_file ros_action_server.vhd VHDL PATH ../../src/ros2/ros_action_server.vhd
 add_fileset_file ros_config_package.vhd VHDL PATH ../../src/ros2/ros_config_package.vhd
 add_fileset_file ros_package.vhd VHDL PATH ../../src/ros2/ros_package.vhd
 add_fileset_file ros_static_discovery_writer.vhd VHDL PATH ../../src/ros2/ros_static_discovery_writer.vhd
-add_fileset_file AddTwoInts_package.vhd VHDL PATH ../../src/ros2/example_interfaces/AddTwoInts_package.vhd
+add_fileset_file ros_time_converter.vhd VHDL PATH ../../src/ros2/ros_time_converter.vhd
 add_fileset_file CancelGoal_package.vhd VHDL PATH ../../src/ros2/rcl_interfaces/action_msgs/CancelGoal_package.vhd
 add_fileset_file CancelGoal_ros_srv_client.vhd VHDL PATH ../../src/ros2/rcl_interfaces/action_msgs/CancelGoal_ros_srv_client.vhd
 add_fileset_file CancelGoal_ros_srv_server.vhd VHDL PATH ../../src/ros2/rcl_interfaces/action_msgs/CancelGoal_ros_srv_server.vhd
@@ -84,8 +78,6 @@ add_fileset_file GoalStatusArray_package.vhd VHDL PATH ../../src/ros2/rcl_interf
 add_fileset_file GoalStatusArray_ros_pub.vhd VHDL PATH ../../src/ros2/rcl_interfaces/action_msgs/GoalStatusArray_ros_pub.vhd
 add_fileset_file GoalStatusArray_ros_sub.vhd VHDL PATH ../../src/ros2/rcl_interfaces/action_msgs/GoalStatusArray_ros_sub.vhd
 add_fileset_file GoalStatus_package.vhd VHDL PATH ../../src/ros2/rcl_interfaces/action_msgs/GoalStatus_package.vhd
-add_fileset_file vector_FIFO.vhd VHDL PATH ../../src/vector_FIFO.vhd
-add_fileset_file L2_Testbench_ROS_Lib4.vhd VHDL PATH ../../src/ros2/Tests/Level_2/L2_Testbench_ROS_Lib4.vhd
 add_fileset_file Fibonacci_package.vhd VHDL PATH ../../src/ros2/example_interfaces/Fibonacci_package.vhd
 add_fileset_file Fibonacci_ros_action_client.vhd VHDL PATH ../../src/ros2/example_interfaces/Fibonacci_ros_action_client.vhd
 add_fileset_file Fibonacci_ros_action_feedback_pub.vhd VHDL PATH ../../src/ros2/example_interfaces/Fibonacci_ros_action_feedback_pub.vhd
@@ -95,14 +87,11 @@ add_fileset_file Fibonacci_ros_action_goal_srv_server.vhd VHDL PATH ../../src/ro
 add_fileset_file Fibonacci_ros_action_result_srv_client.vhd VHDL PATH ../../src/ros2/example_interfaces/Fibonacci_ros_action_result_srv_client.vhd
 add_fileset_file Fibonacci_ros_action_result_srv_server.vhd VHDL PATH ../../src/ros2/example_interfaces/Fibonacci_ros_action_result_srv_server.vhd
 add_fileset_file Fibonacci_ros_action_server.vhd VHDL PATH ../../src/ros2/example_interfaces/Fibonacci_ros_action_server.vhd
-add_fileset_file ros_time_converter.vhd VHDL PATH ../../src/ros2/ros_time_converter.vhd
 add_fileset_file Fibonacci.vhd VHDL PATH ../../src/ros2/Tests/Fibonacci.vhd
-add_fileset_file ros_action_server.vhd VHDL PATH ../../src/ros2/ros_action_server.vhd
+add_fileset_file L2_Testbench_ROS_Lib4.vhd VHDL PATH ../../src/ros2/Tests/Level_2/L2_Testbench_ROS_Lib4.vhd
-add_fileset_file mult.vhd VHDL PATH ../../src/mult.vhd
+add_fileset_file syn_ros_action_config.vhd VHDL PATH ../syn_ros_action_config.vhd
-add_fileset_file mult_Altera.vhd VHDL PATH ../../src/mult_Altera.vhd
+add_fileset_file math_pkg.vhd VHDL PATH ../../src/math_pkg.vhd
-add_fileset_file mult_cfg.vhd VHDL PATH ../../src/mult_cfg.vhd
+add_fileset_file mem_ctrl.vhd VHDL PATH ../../src/mem_ctrl.vhd
-add_fileset_file syn_ros_action_config.vhd VHDL PATH ../../syn/syn_ros_action_config.vhd
-add_fileset_file verbatim_key_hash_generator.vhd VHDL PATH ../../src/verbatim_key_hash_generator.vhd
 
 
 # 

syn/DE10_NANO_SoC_GHRD/test_fpga_hw.tcl.ros_service.BAK

@@ -0,0 +1,161 @@
+# TCL File Generated by Component Editor 21.1
+# Sat Jul 29 20:10:53 GMT+02:00 2023
+# DO NOT MODIFY
+
+
+# 
+# test_fpga "test_fpga" v1.0
+#  2023.07.29.20:10:53
+# Test PL-PS Communication
+# 
+
+# 
+# request TCL package from ACDS 16.1
+# 
+package require -exact qsys 16.1
+
+
+# 
+# module test_fpga
+# 
+set_module_property DESCRIPTION "Test PL-PS Communication"
+set_module_property NAME test_fpga
+set_module_property VERSION 1.0
+set_module_property INTERNAL false
+set_module_property OPAQUE_ADDRESS_MAP true
+set_module_property AUTHOR ""
+set_module_property DISPLAY_NAME test_fpga
+set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
+set_module_property EDITABLE true
+set_module_property REPORT_TO_TALKBACK false
+set_module_property ALLOW_GREYBOX_GENERATION false
+set_module_property REPORT_HIERARCHY false
+
+
+# 
+# file sets
+# 
+add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
+set_fileset_property QUARTUS_SYNTH TOP_LEVEL test_top
+set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
+set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
+add_fileset_file test_top.vhd VHDL PATH ../test_top.vhd TOP_LEVEL_FILE
+add_fileset_file syn_ros_service_config.vhd VHDL PATH ../syn_ros_service_config.vhd
+add_fileset_file Avalon_MM_wrapper.vhd VHDL PATH ../../src/Avalon_MM_wrapper.vhd
+add_fileset_file FWFT_FIFO.vhd VHDL PATH ../../src/FWFT_FIFO.vhd
+add_fileset_file FWFT_FIFO_Altera.vhd VHDL PATH ../../src/FWFT_FIFO_Altera.vhd
+add_fileset_file FWFT_FIFO_cfg.vhd VHDL PATH ../../src/FWFT_FIFO_cfg.vhd
+add_fileset_file dds_reader.vhd VHDL PATH ../../src/dds_reader.vhd
+add_fileset_file dds_writer.vhd VHDL PATH ../../src/dds_writer.vhd
+add_fileset_file dp_mem_ctrl.vhd VHDL PATH ../../src/dp_mem_ctrl.vhd
+add_fileset_file dual_port_ram.vhd VHDL PATH ../../src/dual_port_ram.vhd
+add_fileset_file dual_port_ram_Altera.vhd VHDL PATH ../../src/dual_port_ram_Altera.vhd
+add_fileset_file dual_port_ram_cfg.vhd VHDL PATH ../../src/dual_port_ram_cfg.vhd
+add_fileset_file math_pkg.vhd VHDL PATH ../../src/math_pkg.vhd
+add_fileset_file mem_ctrl.vhd VHDL PATH ../../src/mem_ctrl.vhd
+add_fileset_file mult.vhd VHDL PATH ../../src/mult.vhd
+add_fileset_file mult_Altera.vhd VHDL PATH ../../src/mult_Altera.vhd
+add_fileset_file mult_cfg.vhd VHDL PATH ../../src/mult_cfg.vhd
+add_fileset_file rtps_config_package.vhd VHDL PATH ../../src/rtps_config_package.vhd
+add_fileset_file rtps_discovery_module.vhd VHDL PATH ../../src/rtps_discovery_module.vhd
+add_fileset_file rtps_handler.vhd VHDL PATH ../../src/rtps_handler.vhd
+add_fileset_file rtps_out.vhd VHDL PATH ../../src/rtps_out.vhd
+add_fileset_file rtps_package.vhd VHDL PATH ../../src/rtps_package.vhd
+add_fileset_file rtps_reader.vhd VHDL PATH ../../src/rtps_reader.vhd
+add_fileset_file rtps_writer.vhd VHDL PATH ../../src/rtps_writer.vhd
+add_fileset_file single_port_ram.vhd VHDL PATH ../../src/single_port_ram.vhd
+add_fileset_file single_port_ram_Altera.vhd VHDL PATH ../../src/single_port_ram_Altera.vhd
+add_fileset_file single_port_ram_cfg.vhd VHDL PATH ../../src/single_port_ram_cfg.vhd
+add_fileset_file vector_FIFO.vhd VHDL PATH ../../src/vector_FIFO.vhd
+add_fileset_file dds_user_config.vhd VHDL PATH ../../src/ros2/dds_user_config.vhd
+add_fileset_file ros_config_package.vhd VHDL PATH ../../src/ros2/ros_config_package.vhd
+add_fileset_file ros_package.vhd VHDL PATH ../../src/ros2/ros_package.vhd
+add_fileset_file ros_static_discovery_writer.vhd VHDL PATH ../../src/ros2/ros_static_discovery_writer.vhd
+add_fileset_file ros_time_converter.vhd VHDL PATH ../../src/ros2/ros_time_converter.vhd
+add_fileset_file AddTwoInts_package.vhd VHDL PATH ../../src/ros2/example_interfaces/AddTwoInts_package.vhd
+add_fileset_file AddTwoInts_ros_srv_client.vhd VHDL PATH ../../src/ros2/example_interfaces/AddTwoInts_ros_srv_client.vhd
+add_fileset_file AddTwoInts_ros_srv_server.vhd VHDL PATH ../../src/ros2/example_interfaces/AddTwoInts_ros_srv_server.vhd
+add_fileset_file L2_Testbench_ROS_Lib2.vhd VHDL PATH ../../src/ros2/Tests/Level_2/L2_Testbench_ROS_Lib2.vhd
+add_fileset_file AddTwoInts.vhd VHDL PATH ../../src/ros2/Tests/AddTwoInts.vhd
+add_fileset_file CancelGoal_package.vhd VHDL PATH ../../src/ros2/rcl_interfaces/action_msgs/CancelGoal_package.vhd
+add_fileset_file GoalStatusArray_package.vhd VHDL PATH ../../src/ros2/rcl_interfaces/action_msgs/GoalStatusArray_package.vhd
+add_fileset_file GoalStatus_package.vhd VHDL PATH ../../src/ros2/rcl_interfaces/action_msgs/GoalStatus_package.vhd
+add_fileset_file GoalInfo_package.vhd VHDL PATH ../../src/ros2/rcl_interfaces/action_msgs/GoalInfo_package.vhd
+
+
+# 
+# parameters
+# 
+
+
+# 
+# display items
+# 
+
+
+# 
+# connection point clock
+# 
+add_interface clock clock end
+set_interface_property clock clockRate 0
+set_interface_property clock ENABLED true
+set_interface_property clock EXPORT_OF ""
+set_interface_property clock PORT_NAME_MAP ""
+set_interface_property clock CMSIS_SVD_VARIABLES ""
+set_interface_property clock SVD_ADDRESS_GROUP ""
+
+add_interface_port clock clk clk Input 1
+
+
+# 
+# connection point reset
+# 
+add_interface reset reset end
+set_interface_property reset associatedClock clock
+set_interface_property reset synchronousEdges DEASSERT
+set_interface_property reset ENABLED true
+set_interface_property reset EXPORT_OF ""
+set_interface_property reset PORT_NAME_MAP ""
+set_interface_property reset CMSIS_SVD_VARIABLES ""
+set_interface_property reset SVD_ADDRESS_GROUP ""
+
+add_interface_port reset reset reset Input 1
+
+
+# 
+# connection point avalon_slave_0
+# 
+add_interface avalon_slave_0 avalon end
+set_interface_property avalon_slave_0 addressUnits WORDS
+set_interface_property avalon_slave_0 associatedClock clock
+set_interface_property avalon_slave_0 associatedReset reset
+set_interface_property avalon_slave_0 bitsPerSymbol 8
+set_interface_property avalon_slave_0 burstOnBurstBoundariesOnly false
+set_interface_property avalon_slave_0 burstcountUnits WORDS
+set_interface_property avalon_slave_0 explicitAddressSpan 0
+set_interface_property avalon_slave_0 holdTime 0
+set_interface_property avalon_slave_0 linewrapBursts false
+set_interface_property avalon_slave_0 maximumPendingReadTransactions 0
+set_interface_property avalon_slave_0 maximumPendingWriteTransactions 0
+set_interface_property avalon_slave_0 readLatency 0
+set_interface_property avalon_slave_0 readWaitTime 1
+set_interface_property avalon_slave_0 setupTime 0
+set_interface_property avalon_slave_0 timingUnits Cycles
+set_interface_property avalon_slave_0 writeWaitTime 0
+set_interface_property avalon_slave_0 ENABLED true
+set_interface_property avalon_slave_0 EXPORT_OF ""
+set_interface_property avalon_slave_0 PORT_NAME_MAP ""
+set_interface_property avalon_slave_0 CMSIS_SVD_VARIABLES ""
+set_interface_property avalon_slave_0 SVD_ADDRESS_GROUP ""
+
+add_interface_port avalon_slave_0 address address Input 2
+add_interface_port avalon_slave_0 read read Input 1
+add_interface_port avalon_slave_0 write write Input 1
+add_interface_port avalon_slave_0 readdata readdata Output 32
+add_interface_port avalon_slave_0 writedata writedata Input 32
+add_interface_port avalon_slave_0 waitrequest waitrequest Output 1
+set_interface_assignment avalon_slave_0 embeddedsw.configuration.isFlash 0
+set_interface_assignment avalon_slave_0 embeddedsw.configuration.isMemoryDevice 0
+set_interface_assignment avalon_slave_0 embeddedsw.configuration.isNonVolatileStorage 0
+set_interface_assignment avalon_slave_0 embeddedsw.configuration.isPrintableDevice 0
+

syn/DE10_NANO_SoC_GHRD/test_fpga_hw.tcl.test_fpga.BAK

@@ -0,0 +1,129 @@
+# TCL File Generated by Component Editor 21.1
+# Sat Jul 29 22:44:38 GMT+02:00 2023
+# DO NOT MODIFY
+
+
+# 
+# test_fpga "test_fpga" v1.0
+#  2023.07.29.22:44:38
+# Test PL-PS Communication
+# 
+
+# 
+# request TCL package from ACDS 16.1
+# 
+package require -exact qsys 16.1
+
+
+# 
+# module test_fpga
+# 
+set_module_property DESCRIPTION "Test PL-PS Communication"
+set_module_property NAME test_fpga
+set_module_property VERSION 1.0
+set_module_property INTERNAL false
+set_module_property OPAQUE_ADDRESS_MAP true
+set_module_property AUTHOR ""
+set_module_property DISPLAY_NAME test_fpga
+set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
+set_module_property EDITABLE true
+set_module_property REPORT_TO_TALKBACK false
+set_module_property ALLOW_GREYBOX_GENERATION false
+set_module_property REPORT_HIERARCHY false
+
+
+# 
+# file sets
+# 
+add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
+set_fileset_property QUARTUS_SYNTH TOP_LEVEL test_top
+set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
+set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
+add_fileset_file test_top.vhd VHDL PATH ../test_top.vhd TOP_LEVEL_FILE
+add_fileset_file test_fpga.vhd VHDL PATH ../test_fpga.vhd
+add_fileset_file rtps_package.vhd VHDL PATH ../../src/rtps_package.vhd
+add_fileset_file Avalon_MM_wrapper.vhd VHDL PATH ../../src/Avalon_MM_wrapper.vhd
+add_fileset_file rtps_config_package.vhd VHDL PATH ../../src/rtps_config_package.vhd
+add_fileset_file TEMPLATE_user_config.vhd VHDL PATH ../../src/TEMPLATE_user_config.vhd
+add_fileset_file math_pkg.vhd VHDL PATH ../../src/math_pkg.vhd
+add_fileset_file FWFT_FIFO.vhd VHDL PATH ../../src/FWFT_FIFO.vhd
+add_fileset_file FWFT_FIFO_Altera.vhd VHDL PATH ../../src/FWFT_FIFO_Altera.vhd
+add_fileset_file FWFT_FIFO_cfg.vhd VHDL PATH ../../src/FWFT_FIFO_cfg.vhd
+
+
+# 
+# parameters
+# 
+
+
+# 
+# display items
+# 
+
+
+# 
+# connection point clock
+# 
+add_interface clock clock end
+set_interface_property clock clockRate 0
+set_interface_property clock ENABLED true
+set_interface_property clock EXPORT_OF ""
+set_interface_property clock PORT_NAME_MAP ""
+set_interface_property clock CMSIS_SVD_VARIABLES ""
+set_interface_property clock SVD_ADDRESS_GROUP ""
+
+add_interface_port clock clk clk Input 1
+
+
+# 
+# connection point reset
+# 
+add_interface reset reset end
+set_interface_property reset associatedClock clock
+set_interface_property reset synchronousEdges DEASSERT
+set_interface_property reset ENABLED true
+set_interface_property reset EXPORT_OF ""
+set_interface_property reset PORT_NAME_MAP ""
+set_interface_property reset CMSIS_SVD_VARIABLES ""
+set_interface_property reset SVD_ADDRESS_GROUP ""
+
+add_interface_port reset reset reset Input 1
+
+
+# 
+# connection point avalon_slave_0
+# 
+add_interface avalon_slave_0 avalon end
+set_interface_property avalon_slave_0 addressUnits WORDS
+set_interface_property avalon_slave_0 associatedClock clock
+set_interface_property avalon_slave_0 associatedReset reset
+set_interface_property avalon_slave_0 bitsPerSymbol 8
+set_interface_property avalon_slave_0 burstOnBurstBoundariesOnly false
+set_interface_property avalon_slave_0 burstcountUnits WORDS
+set_interface_property avalon_slave_0 explicitAddressSpan 0
+set_interface_property avalon_slave_0 holdTime 0
+set_interface_property avalon_slave_0 linewrapBursts false
+set_interface_property avalon_slave_0 maximumPendingReadTransactions 0
+set_interface_property avalon_slave_0 maximumPendingWriteTransactions 0
+set_interface_property avalon_slave_0 readLatency 0
+set_interface_property avalon_slave_0 readWaitTime 1
+set_interface_property avalon_slave_0 setupTime 0
+set_interface_property avalon_slave_0 timingUnits Cycles
+set_interface_property avalon_slave_0 writeWaitTime 0
+set_interface_property avalon_slave_0 ENABLED true
+set_interface_property avalon_slave_0 EXPORT_OF ""
+set_interface_property avalon_slave_0 PORT_NAME_MAP ""
+set_interface_property avalon_slave_0 CMSIS_SVD_VARIABLES ""
+set_interface_property avalon_slave_0 SVD_ADDRESS_GROUP ""
+
+add_interface_port avalon_slave_0 address address Input 2
+add_interface_port avalon_slave_0 read read Input 1
+add_interface_port avalon_slave_0 write write Input 1
+add_interface_port avalon_slave_0 readdata readdata Output 32
+add_interface_port avalon_slave_0 writedata writedata Input 32
+add_interface_port avalon_slave_0 waitrequest waitrequest Output 1
+set_interface_assignment avalon_slave_0 embeddedsw.configuration.isFlash 0
+set_interface_assignment avalon_slave_0 embeddedsw.configuration.isMemoryDevice 0
+set_interface_assignment avalon_slave_0 embeddedsw.configuration.isNonVolatileStorage 0
+set_interface_assignment avalon_slave_0 embeddedsw.configuration.isPrintableDevice 0
+

syn/test_fpga.vhd

@@ -29,7 +29,6 @@ architecture arch of test_fpga is
     type STAGE_TYPE is (SRC_ADDR_IN,DEST_ADDR_IN,UDP_PORTS_IN,PACKET_LEN_IN,SRC_ADDR_OUT,DEST_ADDR_OUT,UDP_PORTS_OUT,PACKET_LEN_OUT,WRITE_MAGIC_WORD,WRITE_PACKET);
     
     --*****CONSTANT DECLARATION*****
-    constant RES_IPv4_ADDRESS   : std_logic_vector(IPv4_ADDRESS_WIDTH-1 downto 0) := x"C0A8000A"; --192.168.0.10
     constant MAGIC_WORD         : std_logic_vector(WORD_WIDTH-1 downto 0) := x"DEADBEEF";
     
     --*****SIGNAL DECLARATION*****

syn/test_top.vhd

@@ -84,6 +84,21 @@ begin
             free        => output_util
         );
     
+    --test_fpga_inst : entity work.test_fpga(arch)
+    --    port map (
+    --        -- SYSTEM
+    --        clk         => clk,
+    --        reset       => reset,
+    --        -- INPUT
+    --        empty       => empty_fi_test,
+    --        read        => read_test_fi,
+    --        data_in     => data_fi_test,
+    --        -- OUTPUT
+    --        full        => full_fo_test,
+    --        write       => write_test_fo,
+    --        data_out    => data_test_fo
+    --    );
+    
     --dds_loopback_inst : entity work.L2_Testbench_Lib4(arch)
     --    port map (
     --        -- SYSTEM
@@ -115,7 +130,7 @@ begin
     --        write       => write_test_fo,
     --        data_out    => data_test_fo
     --    );
-        
+    
     --ros_action_inst : entity work.L2_Testbench_ROS_Lib4(arch)
     --    port map (
     --        -- SYSTEM
@@ -150,7 +165,7 @@ begin
     --        write       => write_test_fo,
     --        data_out    => data_test_fo
     --    );
-        
+    
     loopback_inst : entity work.loopback(arch)
         port map (
             -- SYSTEM
@@ -165,7 +180,7 @@ begin
             wr          => write_test_fo,
             data_out    => data_test_fo
         );
-        
+    
     time_prc : process(clk)
     begin
         if rising_edge(clk) then