diff --git a/sim/rtps_builtin_endpoint_test5.do b/sim/rtps_builtin_endpoint_test5.do new file mode 100644 index 0000000..0ccb299 --- /dev/null +++ b/sim/rtps_builtin_endpoint_test5.do @@ -0,0 +1,68 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate -divider SYSTEM +add wave -noupdate /rtps_builtin_endpoint_test5/uut/clk +add wave -noupdate /rtps_builtin_endpoint_test5/uut/reset +add wave -noupdate -divider INPUT +add wave -noupdate /rtps_builtin_endpoint_test5/uut/empty +add wave -noupdate /rtps_builtin_endpoint_test5/uut/rd +add wave -noupdate -radix hexadecimal /rtps_builtin_endpoint_test5/uut/data_in +add wave -noupdate /rtps_builtin_endpoint_test5/uut/last_word_in +add wave -noupdate /rtps_builtin_endpoint_test5/uut/last_word_in_latch +add wave -noupdate -divider OUTPUT +add wave -noupdate -radix hexadecimal /rtps_builtin_endpoint_test5/uut/data_out +add wave -noupdate /rtps_builtin_endpoint_test5/uut/endpoint_wr +add wave -noupdate /rtps_builtin_endpoint_test5/uut/last_word_out +add wave -noupdate -divider TESTBENCH +add wave -noupdate /rtps_builtin_endpoint_test5/start +add wave -noupdate /rtps_builtin_endpoint_test5/stim_stage +add wave -noupdate /rtps_builtin_endpoint_test5/stimulus.length +add wave -noupdate /rtps_builtin_endpoint_test5/cnt_stim +add wave -noupdate /rtps_builtin_endpoint_test5/packet_sent +add wave -noupdate -divider {MAIN FSM} +add wave -noupdate /rtps_builtin_endpoint_test5/uut/stage +add wave -noupdate /rtps_builtin_endpoint_test5/uut/stage_next +add wave -noupdate /rtps_builtin_endpoint_test5/uut/cnt +add wave -noupdate /rtps_builtin_endpoint_test5/uut/endpoint_mask +add wave -noupdate /rtps_builtin_endpoint_test5/uut/participant_match +add wave -noupdate -divider {MEM FSM} +add wave -noupdate -group MEM_FSM /rtps_builtin_endpoint_test5/uut/mem_opcode +add wave -noupdate -group MEM_FSM /rtps_builtin_endpoint_test5/uut/mem_op_start +add wave -noupdate -group MEM_FSM /rtps_builtin_endpoint_test5/uut/mem_op_done +add wave -noupdate -group MEM_FSM /rtps_builtin_endpoint_test5/uut/mem_stage +add wave -noupdate -group MEM_FSM /rtps_builtin_endpoint_test5/uut/mem_stage_next +add wave -noupdate -group MEM_FSM /rtps_builtin_endpoint_test5/uut/mem_cnt +add wave -noupdate -group MEM_FSM -radix unsigned /rtps_builtin_endpoint_test5/uut/mem_addr_base +add wave -noupdate -group MEM_FSM -radix unsigned /rtps_builtin_endpoint_test5/uut/addr_res +add wave -noupdate -divider GUARD +add wave -noupdate -radix unsigned /rtps_builtin_endpoint_test5/uut/read_cnt +add wave -noupdate -radix unsigned /rtps_builtin_endpoint_test5/uut/parameter_end +add wave -noupdate /rtps_builtin_endpoint_test5/uut/parse_prc/rd_guard +add wave -noupdate -divider MEMORY +add wave -noupdate -group MEMORY -radix unsigned /rtps_builtin_endpoint_test5/uut/ram_inst/addr +add wave -noupdate -group MEMORY /rtps_builtin_endpoint_test5/uut/ram_inst/wen +add wave -noupdate -group MEMORY /rtps_builtin_endpoint_test5/uut/ram_inst/ren +add wave -noupdate -group MEMORY -radix hexadecimal /rtps_builtin_endpoint_test5/uut/ram_inst/wr_data +add wave -noupdate -group MEMORY -radix hexadecimal /rtps_builtin_endpoint_test5/uut/ram_inst/rd_data +add wave -noupdate -divider MISC +add wave -noupdate /rtps_builtin_endpoint_test5/uut/update_participant_flags +add wave -noupdate -radix unsigned /rtps_builtin_endpoint_test5/uut/mem_seq_nr +add wave -noupdate -radix unsigned /rtps_builtin_endpoint_test5/uut/seq_nr +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {Begin {847825000 ps} 1} {Error {851525000 ps} 1} {Cursor {33675000 ps} 0} +quietly wave cursor active 1 +configure wave -namecolwidth 149 +configure wave -valuecolwidth 144 +configure wave -justifyvalue left +configure wave -signalnamewidth 1 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ns +update +WaveRestoreZoom {848883724 ps} {850032066 ps} diff --git a/src/Tests/Level_0/rtps_builtin_endpoint_test1.vhd b/src/Tests/Level_0/rtps_builtin_endpoint_test1.vhd index 610efe5..6e5d6f4 100644 --- a/src/Tests/Level_0/rtps_builtin_endpoint_test1.vhd +++ b/src/Tests/Level_0/rtps_builtin_endpoint_test1.vhd @@ -553,29 +553,28 @@ begin begin data_in <= stimulus.data(cnt_stim); last_word_in <= stimulus.last(cnt_stim); - case (stim_stage) is - when IDLE => - packet_sent <= '1'; - when BUSY => - packet_sent <= '0'; - end case; if rising_edge(clk) then if (reset = '1') then cnt_stim <= 0; stim_stage <= IDLE; + packet_sent <= '1'; else case (stim_stage) is when IDLE => - if (start = '1') then + if (start = '1' and stimulus.length /= 0) then stim_stage <= BUSY; cnt_stim <= 0; + packet_sent <= '0'; end if; when BUSY => - if (cnt_stim = stimulus.length) then - stim_stage <= IDLE; - elsif (rd_sig = '1') then - cnt_stim <= cnt_stim + 1; + if (rd_sig = '1') then + if (cnt_stim = stimulus.length-1) then + stim_stage <= IDLE; + packet_sent <= '1'; + else + cnt_stim <= cnt_stim + 1; + end if; end if; end case; end if; @@ -607,9 +606,7 @@ begin -- NOTE: The first read after the packet is sent signifies that the State Machine has begun processing the next packet. -- The memory operation that could still be in progress is the last one concerning the last sent packet. wait until packet_sent = '1'; - if (rd_sig /= '1') then - wait until rd_sig = '1'; - end if; + wait until rising_edge(rd_sig); if (mem_op_done /= '1') then wait until mem_op_done = '1'; end if; diff --git a/src/Tests/Level_0/rtps_builtin_endpoint_test2.vhd b/src/Tests/Level_0/rtps_builtin_endpoint_test2.vhd index 05fc4a2..363800f 100644 --- a/src/Tests/Level_0/rtps_builtin_endpoint_test2.vhd +++ b/src/Tests/Level_0/rtps_builtin_endpoint_test2.vhd @@ -884,29 +884,28 @@ begin begin data_in <= stimulus.data(cnt_stim); last_word_in <= stimulus.last(cnt_stim); - case (stim_stage) is - when IDLE => - packet_sent <= '1'; - when BUSY => - packet_sent <= '0'; - end case; if rising_edge(clk) then if (reset = '1') then cnt_stim <= 0; stim_stage <= IDLE; + packet_sent <= '1'; else case (stim_stage) is when IDLE => - if (start = '1') then + if (start = '1' and stimulus.length /= 0) then stim_stage <= BUSY; cnt_stim <= 0; + packet_sent <= '0'; end if; when BUSY => - if (cnt_stim = stimulus.length) then - stim_stage <= IDLE; - elsif (rd_sig = '1') then - cnt_stim <= cnt_stim + 1; + if (rd_sig = '1') then + if (cnt_stim = stimulus.length-1) then + stim_stage <= IDLE; + packet_sent <= '1'; + else + cnt_stim <= cnt_stim + 1; + end if; end if; end case; end if; diff --git a/src/Tests/Level_0/rtps_builtin_endpoint_test3.vhd b/src/Tests/Level_0/rtps_builtin_endpoint_test3.vhd index 2aefb1c..f1dc684 100644 --- a/src/Tests/Level_0/rtps_builtin_endpoint_test3.vhd +++ b/src/Tests/Level_0/rtps_builtin_endpoint_test3.vhd @@ -1149,29 +1149,28 @@ begin begin data_in <= stimulus.data(cnt_stim); last_word_in <= stimulus.last(cnt_stim); - case (stim_stage) is - when IDLE => - packet_sent <= '1'; - when BUSY => - packet_sent <= '0'; - end case; if rising_edge(clk) then if (reset = '1') then cnt_stim <= 0; stim_stage <= IDLE; + packet_sent <= '1'; else case (stim_stage) is when IDLE => - if (start = '1') then + if (start = '1' and stimulus.length /= 0) then stim_stage <= BUSY; cnt_stim <= 0; + packet_sent <= '0'; end if; when BUSY => - if (cnt_stim = stimulus.length) then - stim_stage <= IDLE; - elsif (rd_sig = '1') then - cnt_stim <= cnt_stim + 1; + if (rd_sig = '1') then + if (cnt_stim = stimulus.length-1) then + stim_stage <= IDLE; + packet_sent <= '1'; + else + cnt_stim <= cnt_stim + 1; + end if; end if; end case; end if; @@ -1203,9 +1202,7 @@ begin -- NOTE: The first read after the packet is sent signifies that the State Machine has begun processing the next packet. -- The memory operation that could still be in progress is the last one concerning the last sent packet. wait on packet_sent until (packet_sent = '1' and mem_check = '1'); - if (rd_sig /= '1') then - wait until rd_sig = '1'; - end if; + wait until rising_edge(rd_sig); if (mem_op_done /= '1') then wait until mem_op_done = '1'; end if; diff --git a/src/Tests/Level_0/rtps_builtin_endpoint_test4.vhd b/src/Tests/Level_0/rtps_builtin_endpoint_test4.vhd index 1214613..049472f 100644 --- a/src/Tests/Level_0/rtps_builtin_endpoint_test4.vhd +++ b/src/Tests/Level_0/rtps_builtin_endpoint_test4.vhd @@ -336,29 +336,28 @@ begin begin data_in <= stimulus.data(cnt_stim); last_word_in <= stimulus.last(cnt_stim); - case (stim_stage) is - when IDLE => - packet_sent <= '1'; - when BUSY => - packet_sent <= '0'; - end case; if rising_edge(clk) then if (reset = '1') then cnt_stim <= 0; stim_stage <= IDLE; + packet_sent <= '1'; else case (stim_stage) is when IDLE => - if (start = '1') then + if (start = '1' and stimulus.length /= 0) then stim_stage <= BUSY; cnt_stim <= 0; + packet_sent <= '0'; end if; when BUSY => - if (cnt_stim = stimulus.length) then - stim_stage <= IDLE; - elsif (rd_sig = '1') then - cnt_stim <= cnt_stim + 1; + if (rd_sig = '1') then + if (cnt_stim = stimulus.length-1) then + stim_stage <= IDLE; + packet_sent <= '1'; + else + cnt_stim <= cnt_stim + 1; + end if; end if; end case; end if; @@ -390,9 +389,7 @@ begin -- NOTE: The first read after the packet is sent signifies that the State Machine has begun processing the next packet. -- The memory operation that could still be in progress is the last one concerning the last sent packet. wait on packet_sent until (packet_sent = '1' and mem_check = '1'); - if (rd_sig /= '1') then - wait until rd_sig = '1'; - end if; + wait until rising_edge(rd_sig); if (mem_op_done /= '1') then wait until mem_op_done = '1'; end if; diff --git a/src/Tests/Level_0/rtps_builtin_endpoint_test5.vhd b/src/Tests/Level_0/rtps_builtin_endpoint_test5.vhd index 612a2bc..01b6a42 100644 --- a/src/Tests/Level_0/rtps_builtin_endpoint_test5.vhd +++ b/src/Tests/Level_0/rtps_builtin_endpoint_test5.vhd @@ -461,29 +461,28 @@ begin begin data_in <= stimulus.data(cnt_stim); last_word_in <= stimulus.last(cnt_stim); - case (stim_stage) is - when IDLE => - packet_sent <= '1'; - when BUSY => - packet_sent <= '0'; - end case; if rising_edge(clk) then if (reset = '1') then cnt_stim <= 0; stim_stage <= IDLE; + packet_sent <= '1'; else case (stim_stage) is when IDLE => - if (start = '1') then + if (start = '1' and stimulus.length /= 0) then stim_stage <= BUSY; cnt_stim <= 0; + packet_sent <= '0'; end if; when BUSY => - if (cnt_stim = stimulus.length) then - stim_stage <= IDLE; - elsif (rd_sig = '1') then - cnt_stim <= cnt_stim + 1; + if (rd_sig = '1') then + if (cnt_stim = stimulus.length-1) then + stim_stage <= IDLE; + packet_sent <= '1'; + else + cnt_stim <= cnt_stim + 1; + end if; end if; end case; end if; @@ -515,9 +514,7 @@ begin -- NOTE: The first read after the packet is sent signifies that the State Machine has begun processing the next packet. -- The memory operation that could still be in progress is the last one concerning the last sent packet. wait on packet_sent until (packet_sent = '1' and mem_check = '1'); - if (rd_sig /= '1') then - wait until rd_sig = '1'; - end if; + wait until rising_edge(rd_sig); if (mem_op_done /= '1') then wait until mem_op_done = '1'; end if; diff --git a/src/Tests/Level_0/rtps_handler_test1.vhd b/src/Tests/Level_0/rtps_handler_test1.vhd index 8c9fa2f..b637d67 100644 --- a/src/Tests/Level_0/rtps_handler_test1.vhd +++ b/src/Tests/Level_0/rtps_handler_test1.vhd @@ -1349,37 +1349,34 @@ begin input_prc : process(all) begin data_in <= stimulus.data(cnt_stim); - case (stim_stage) is - when IDLE => - packet_sent <= '1'; - when BUSY => - packet_sent <= '0'; - end case; if rising_edge(clk) then if (reset = '1') then cnt_stim <= 0; stim_stage <= IDLE; + packet_sent <= '1'; else case (stim_stage) is when IDLE => - if (start = '1') then + if (start = '1' and stimulus.length /= 0) then stim_stage <= BUSY; cnt_stim <= 0; + packet_sent <= '0'; end if; when BUSY => - if (cnt_stim = stimulus.length) then - stim_stage <= IDLE; - elsif (rd_sig = '1') then - cnt_stim <= cnt_stim + 1; + if (rd_sig = '1') then + if (cnt_stim = stimulus.length-1) then + stim_stage <= IDLE; + packet_sent <= '1'; + else + cnt_stim <= cnt_stim + 1; + end if; end if; end case; end if; end if; end process; - - output_prc : process(all) begin case (ref_stage) is diff --git a/src/Tests/Level_0/rtps_handler_test2.vhd b/src/Tests/Level_0/rtps_handler_test2.vhd index 07c34ba..c75e2f2 100644 --- a/src/Tests/Level_0/rtps_handler_test2.vhd +++ b/src/Tests/Level_0/rtps_handler_test2.vhd @@ -258,29 +258,28 @@ begin input_prc : process(all) begin data_in <= stimulus.data(cnt_stim); - case (stim_stage) is - when IDLE => - packet_sent <= '1'; - when BUSY => - packet_sent <= '0'; - end case; if rising_edge(clk) then if (reset = '1') then cnt_stim <= 0; stim_stage <= IDLE; + packet_sent <= '1'; else case (stim_stage) is when IDLE => - if (start = '1') then + if (start = '1' and stimulus.length /= 0) then stim_stage <= BUSY; cnt_stim <= 0; + packet_sent <= '0'; end if; when BUSY => - if (cnt_stim = stimulus.length) then - stim_stage <= IDLE; - elsif (rd_sig = '1') then - cnt_stim <= cnt_stim + 1; + if (rd_sig = '1') then + if (cnt_stim = stimulus.length-1) then + stim_stage <= IDLE; + packet_sent <= '1'; + else + cnt_stim <= cnt_stim + 1; + end if; end if; end case; end if; diff --git a/src/Tests/testbench.pro b/src/Tests/testbench.pro index 41876f4..408b48f 100644 --- a/src/Tests/testbench.pro +++ b/src/Tests/testbench.pro @@ -25,9 +25,9 @@ analyze Level_0/rtps_out_test1.vhd #simulate rtps_handler_test1 #simulate rtps_handler_test2 -#simulate rtps_builtin_endpoint_test1 +simulate rtps_builtin_endpoint_test1 #simulate rtps_builtin_endpoint_test2 #simulate rtps_builtin_endpoint_test3 #simulate rtps_builtin_endpoint_test4 #simulate rtps_builtin_endpoint_test5 -simulate rtps_out_test1 \ No newline at end of file +#simulate rtps_out_test1 \ No newline at end of file diff --git a/src/rtps_handler.vhd b/src/rtps_handler.vhd index 93913d9..01592cd 100644 --- a/src/rtps_handler.vhd +++ b/src/rtps_handler.vhd @@ -872,17 +872,18 @@ begin -- Keep Sub-State cnt_next <= cnt; - -- Exit Condition - else - -- Prevent Input Latching - rd_guard := '0'; - -- DONE - stage_next <= MATCH_DST_ENDPOINT; end if; when others => null; end case; end if; + -- Exit Condition (Not influenced by Empty Signal) + if (cnt = 7 and cnt2 >= bitmap_cnt) then + -- Prevent Input Latching + rd_guard := '0'; + -- DONE + stage_next <= MATCH_DST_ENDPOINT; + end if; when PARSE_DATA => -- Input FIFO Guard if (empty = '0') then