Add Level 2 ROS Action Test (Fibonacci)
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parent
90a8aaad19
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145
sim/L2_Fibonacci_test1.do
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145
sim/L2_Fibonacci_test1.do
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onerror {resume}
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radix define ROS_RETCODE {
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"10#0#" "ROS_RET_OK",
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"10#1#" "ROS_RET_ERROR",
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"10#2#" "ROS_RET_TIMEOUT",
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"10#3#" "ROS_RET_UNSUPPORTED",
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"10#10#" "ROS_RET_BAD_ALLOC",
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"10#11#" "ROS_RET_INVALID_ARGUMENT",
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"10#12#" "ROS_RET_INCORRECT_RMW_IMPLEMENTATION",
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"10#100#" "ROS_RET_ALREADY_INIT",
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"10#101#" "ROS_RET_NOT_INIT",
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"10#102#" "ROS_RET_MISMATCHED_RMW",
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"10#103#" "ROS_RET_TOPIC_NAME_INVALID",
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"10#104#" "ROS_RET_SERVICE_NAME_INVALID",
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"10#105#" "ROS_RET_UNKNOWN_SUBSTITUTION",
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"10#106#" "ROS_RET_ALREADY_SHUTDOWN",
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"10#200#" "ROS_RET_NODE_INVALID",
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"10#201#" "ROS_RET_NODE_INVALID_NAME",
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"10#202#" "ROS_RET_NODE_INVALID_NAMESPACE",
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"10#203#" "ROS_RET_NODE_NAME_NON_EXISTENT",
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"10#400#" "ROS_RET_SUBSCRIPTION_INVALID",
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"10#401#" "ROS_RET_SUBSCRIPTION_TAKE_FAILED",
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"10#500#" "ROS_RET_CLIENT_INVALID",
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"10#501#" "ROS_RET_CLIENT_TAKE_FAILED",
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"10#600#" "ROS_RET_SERVICE_INVALID",
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"10#601#" "ROS_RET_SERVICE_TAKE_FAILED",
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"10#800#" "ROS_RET_TIMER_INVALID",
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"10#801#" "ROS_RET_TIMER_CANCELED",
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"10#900#" "ROS_RET_WAIT_SET_INVALID",
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"10#901#" "ROS_RET_WAIT_SET_EMPTY",
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"10#902#" "ROS_RET_WAIT_SET_FULL",
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"10#1001#" "ROS_RET_INVALID_REMAP_RULE",
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"10#1002#" "ROS_RET_WRONG_LEXEME",
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"10#1003#" "ROS_RET_INVALID_ROS_ARGS",
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"10#1010#" "ROS_RET_INVALID_PARAM_RULE",
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"10#1020#" "ROS_RET_INVALID_LOG_LEVEL_RULE",
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"10#2001#" "ROS_RET_EVENT_TAKE_FAILED",
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"10#2000#" "ROS_RET_ACTION_NAME_INVALID",
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"10#2100#" "ROS_RET_ACTION_GOAL_ACCEPTED",
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"10#2101#" "ROS_RET_ACTION_GOAL_REJECTED",
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"10#2102#" "ROS_RET_ACTION_CLIENT_INVALID",
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"10#2103#" "ROS_RET_ACTION_CLIENT_TAKE_FAILED",
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"10#2200#" "ROS_RET_ACTION_SERVER_INVALID",
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"10#2201#" "ROS_RET_ACTION_SERVER_TAKE_FAILED",
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"10#2300#" "ROS_RET_ACTION_GOAL_HANDLE_INVALID",
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"10#2301#" "ROS_RET_ACTION_GOAL_EVENT_INVALID",
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"10#3000#" "ROS_RET_LIFECYCLE_STATE_REGISTERED",
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"10#3001#" "ROS_RET_LIFECYCLE_STATE_NOT_REGISTERED",
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-default unsigned
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}
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radix define GOAL_STATUS {
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"10#0#" "STATUS_UNKNOWN",
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"10#1#" "STATUS_ACCEPTED",
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"10#2#" "STATUS_EXECUTING",
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"10#3#" "STATUS_CANCELING",
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"10#4#" "STATUS_SUCCEEDED",
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"10#5#" "STATUS_CANCELED",
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"10#6#" "STATUS_ABORTED",
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-default unsigned
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}
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quietly WaveActivateNextPane {} 0
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add wave -noupdate -divider SYSTEM
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add wave -noupdate /l2_fibonacci_ros_action_test1/clk
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add wave -noupdate /l2_fibonacci_ros_action_test1/reset
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add wave -noupdate -radix unsigned /l2_fibonacci_ros_action_test1/time
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add wave -noupdate -radix unsigned /l2_fibonacci_ros_action_test1/server_inst/ros_time
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add wave -noupdate -divider CLIENT
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add wave -noupdate -group CLIENT /l2_fibonacci_ros_action_test1/client_inst/Fibonacci_ros_action_client_inst/start
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add wave -noupdate -group CLIENT /l2_fibonacci_ros_action_test1/client_inst/Fibonacci_ros_action_client_inst/opcode
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add wave -noupdate -group CLIENT /l2_fibonacci_ros_action_test1/client_inst/Fibonacci_ros_action_client_inst/ack
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add wave -noupdate -group CLIENT -radix hexadecimal /l2_fibonacci_ros_action_test1/client_inst/Fibonacci_ros_action_client_inst/sequence_id
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add wave -noupdate -group CLIENT -radix hexadecimal /l2_fibonacci_ros_action_test1/client_inst/Fibonacci_ros_action_client_inst/service_info
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add wave -noupdate -group CLIENT /l2_fibonacci_ros_action_test1/client_inst/Fibonacci_ros_action_client_inst/data_available_g
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add wave -noupdate -group CLIENT /l2_fibonacci_ros_action_test1/client_inst/Fibonacci_ros_action_client_inst/data_available_r
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add wave -noupdate -group CLIENT /l2_fibonacci_ros_action_test1/client_inst/Fibonacci_ros_action_client_inst/data_available_c
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add wave -noupdate -group CLIENT /l2_fibonacci_ros_action_test1/client_inst/Fibonacci_ros_action_client_inst/data_available_f
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add wave -noupdate -group CLIENT /l2_fibonacci_ros_action_test1/client_inst/Fibonacci_ros_action_client_inst/done
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add wave -noupdate -group CLIENT -radix ROS_RETCODE /l2_fibonacci_ros_action_test1/client_inst/Fibonacci_ros_action_client_inst/return_code
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add wave -noupdate -group CLIENT -radix hexadecimal /l2_fibonacci_ros_action_test1/client_inst/Fibonacci_ros_action_client_inst/goal_id
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add wave -noupdate -group CLIENT -radix hexadecimal /l2_fibonacci_ros_action_test1/client_inst/Fibonacci_ros_action_client_inst/goal_order
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add wave -noupdate -group CLIENT /l2_fibonacci_ros_action_test1/client_inst/Fibonacci_ros_action_client_inst/goal_accepted
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add wave -noupdate -group CLIENT -radix unsigned /l2_fibonacci_ros_action_test1/client_inst/Fibonacci_ros_action_client_inst/goal_stamp
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add wave -noupdate -group CLIENT -radix hexadecimal /l2_fibonacci_ros_action_test1/client_inst/Fibonacci_ros_action_client_inst/result_goal_id
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add wave -noupdate -group CLIENT -radix hexadecimal /l2_fibonacci_ros_action_test1/client_inst/Fibonacci_ros_action_client_inst/cancel_goal_id
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add wave -noupdate -divider SERVER
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add wave -noupdate -group SERVER /l2_fibonacci_ros_action_test1/server_inst/Fibonacci_ros_action_server_inst/start
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add wave -noupdate -group SERVER /l2_fibonacci_ros_action_test1/server_inst/Fibonacci_ros_action_server_inst/opcode
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add wave -noupdate -group SERVER /l2_fibonacci_ros_action_test1/server_inst/Fibonacci_ros_action_server_inst/ack
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add wave -noupdate -group SERVER /l2_fibonacci_ros_action_test1/server_inst/Fibonacci_ros_action_server_inst/done
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add wave -noupdate -group SERVER -radix ROS_RETCODE /l2_fibonacci_ros_action_test1/server_inst/Fibonacci_ros_action_server_inst/return_code
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add wave -noupdate -group SERVER -radix hexadecimal /l2_fibonacci_ros_action_test1/server_inst/Fibonacci_ros_action_server_inst/goal_handle_in
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add wave -noupdate -group SERVER -radix hexadecimal /l2_fibonacci_ros_action_test1/server_inst/Fibonacci_ros_action_server_inst/goal_handle_out
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add wave -noupdate -group SERVER -radix GOAL_STATUS /l2_fibonacci_ros_action_test1/server_inst/Fibonacci_ros_action_server_inst/goal_state_in
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add wave -noupdate -group SERVER -radix GOAL_STATUS /l2_fibonacci_ros_action_test1/server_inst/Fibonacci_ros_action_server_inst/goal_state_out
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add wave -noupdate -group SERVER -radix hexadecimal /l2_fibonacci_ros_action_test1/server_inst/Fibonacci_ros_action_server_inst/goal_id
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add wave -noupdate -group SERVER -radix unsigned /l2_fibonacci_ros_action_test1/server_inst/Fibonacci_ros_action_server_inst/goal_result_index
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add wave -noupdate -group SERVER -radix unsigned /l2_fibonacci_ros_action_test1/server_inst/Fibonacci_ros_action_server_inst/goal_stamp
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add wave -noupdate -group SERVER /l2_fibonacci_ros_action_test1/server_inst/Fibonacci_ros_action_server_inst/new_goal_request
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add wave -noupdate -group SERVER -radix hexadecimal /l2_fibonacci_ros_action_test1/server_inst/Fibonacci_ros_action_server_inst/new_goal_handle
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add wave -noupdate -group SERVER -radix unsigned /l2_fibonacci_ros_action_test1/server_inst/Fibonacci_ros_action_server_inst/new_goal_result_index
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add wave -noupdate -group SERVER -radix hexadecimal /l2_fibonacci_ros_action_test1/server_inst/Fibonacci_ros_action_server_inst/new_goal_order
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add wave -noupdate -group SERVER /l2_fibonacci_ros_action_test1/server_inst/Fibonacci_ros_action_server_inst/new_goal_accepted
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add wave -noupdate -group SERVER /l2_fibonacci_ros_action_test1/server_inst/Fibonacci_ros_action_server_inst/new_goal_response
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add wave -noupdate -group SERVER /l2_fibonacci_ros_action_test1/server_inst/Fibonacci_ros_action_server_inst/cancel_request
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add wave -noupdate -group SERVER -radix hexadecimal /l2_fibonacci_ros_action_test1/server_inst/Fibonacci_ros_action_server_inst/cancel_request_handle
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add wave -noupdate -group SERVER /l2_fibonacci_ros_action_test1/server_inst/Fibonacci_ros_action_server_inst/cancel_accepted
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add wave -noupdate -group SERVER /l2_fibonacci_ros_action_test1/server_inst/Fibonacci_ros_action_server_inst/cancel_response
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add wave -noupdate -group SERVER -radix unsigned /l2_fibonacci_ros_action_test1/server_inst/Fibonacci_ros_action_server_inst/index_result
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add wave -noupdate -group SERVER /l2_fibonacci_ros_action_test1/server_inst/Fibonacci_ros_action_server_inst/index_result_wen
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add wave -noupdate -group SERVER /l2_fibonacci_ros_action_test1/server_inst/Fibonacci_ros_action_server_inst/index_result_ready
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add wave -noupdate -divider MISC
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add wave -noupdate /l2_fibonacci_ros_action_test1/server_inst/Fibonacci_inst/stage
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add wave -noupdate /l2_fibonacci_ros_action_test1/server_inst/Fibonacci_inst/cnt
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add wave -noupdate -radix unsigned /l2_fibonacci_ros_action_test1/server_inst/Fibonacci_inst/order
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add wave -noupdate -radix unsigned /l2_fibonacci_ros_action_test1/server_inst/Fibonacci_inst/i
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add wave -noupdate -radix unsigned /l2_fibonacci_ros_action_test1/server_inst/Fibonacci_inst/a
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add wave -noupdate -radix unsigned /l2_fibonacci_ros_action_test1/server_inst/Fibonacci_inst/b
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add wave -noupdate -radix unsigned /l2_fibonacci_ros_action_test1/server_inst/Fibonacci_inst/ind
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add wave -noupdate -radix unsigned /l2_fibonacci_ros_action_test1/server_inst/Fibonacci_inst/result_seq_len
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add wave -noupdate -radix unsigned /l2_fibonacci_ros_action_test1/server_inst/Fibonacci_inst/result_seq_addr
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add wave -noupdate /l2_fibonacci_ros_action_test1/server_inst/Fibonacci_inst/result_seq_ready
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add wave -noupdate /l2_fibonacci_ros_action_test1/server_inst/Fibonacci_inst/result_seq_ren
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add wave -noupdate /l2_fibonacci_ros_action_test1/server_inst/Fibonacci_inst/result_seq_wen
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add wave -noupdate /l2_fibonacci_ros_action_test1/server_inst/Fibonacci_inst/result_seq_valid
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add wave -noupdate /l2_fibonacci_ros_action_test1/server_inst/Fibonacci_inst/result_seq_ack
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add wave -noupdate -radix unsigned /l2_fibonacci_ros_action_test1/server_inst/Fibonacci_inst/result_seq_r
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add wave -noupdate -radix unsigned /l2_fibonacci_ros_action_test1/server_inst/Fibonacci_inst/result_seq_w
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TreeUpdate [SetDefaultTree]
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WaveRestoreCursors {{Cursor 1} {488675000 ps} 0}
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quietly wave cursor active 1
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configure wave -namecolwidth 182
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configure wave -valuecolwidth 220
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configure wave -justifyvalue left
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configure wave -signalnamewidth 1
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configure wave -snapdistance 10
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configure wave -datasetprefix 0
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configure wave -rowmargin 4
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configure wave -childrowmargin 2
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configure wave -gridoffset 0
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configure wave -gridperiod 1
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configure wave -griddelta 40
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configure wave -timeline 0
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configure wave -timelineunits ns
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update
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WaveRestoreZoom {494011230 ps} {494939270 ps}
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345
src/ros2/Tests/Fibonacci.vhd
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345
src/ros2/Tests/Fibonacci.vhd
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-- altera vhdl_input_version vhdl_2008
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-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.rtps_package.all;
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use work.ros_package.all;
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use work.ros_config;
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use work.GoalStatus_package;
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use work.Fibonacci_package.all;
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entity Fibonacci is
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port (
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-- SYSTEM
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clk : in std_logic;
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reset : in std_logic;
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time : in ROS_TIME_TYPE;
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-- SERVICE SERVER
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start : out std_logic;
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opcode : out ROS_ACTION_OPCODE_TYPE;
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ack : in std_logic;
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done : in std_logic;
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return_code : in std_logic_vector(ROS_RETCODE_WIDTH-1 downto 0);
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goal_handle_in : out std_logic_vector(GOAL_HANDLE_WIDTH-1 downto 0);
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goal_handle_out : in std_logic_vector(GOAL_HANDLE_WIDTH-1 downto 0);
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goal_state_in : out std_logic_vector(CDR_INT8_WIDTH-1 downto 0);
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goal_state_out : in std_logic_vector(CDR_INT8_WIDTH-1 downto 0);
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goal_id : in std_logic_vector(UUID_WIDTH-1 downto 0);
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goal_result_index : in std_logic_vector(WORD_WIDTH-1 downto 0);
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goal_stamp : in ROS_TIME_TYPE;
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-- GOAL
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new_goal_request : in std_logic;
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new_goal_handle : in std_logic_vector(GOAL_HANDLE_WIDTH-1 downto 0);
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new_goal_result_index : in std_logic_vector(WORD_WIDTH-1 downto 0);
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new_goal_order : in std_logic_vector(CDR_LONG_WIDTH-1 downto 0);
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new_goal_accepted : out std_logic;
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new_goal_response : out std_logic;
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-- CANCEL
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cancel_request : in std_logic;
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cancel_request_handle : in std_logic_vector(GOAL_HANDLE_WIDTH-1 downto 0);
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cancel_accepted : out std_logic;
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cancel_response : out std_logic;
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-- RESULT SIGNALS
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index_result : out std_logic_vector(WORD_WIDTH-1 downto 0);
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index_result_wen : out std_logic;
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index_result_ready : in std_logic;
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result_seq_len : out std_logic_vector(R_RR_SEQ_ADDR_WIDTH-1 downto 0);
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result_seq_addr : out std_logic_vector(R_RR_SEQ_ADDR_WIDTH-1 downto 0);
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result_seq_ready : in std_logic;
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result_seq_ren : out std_logic;
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result_seq_wen : out std_logic;
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result_seq_valid : in std_logic;
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result_seq_ack : out std_logic;
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result_seq_r : in std_logic_vector(CDR_LONG_WIDTH-1 downto 0);
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result_seq_w : out std_logic_vector(CDR_LONG_WIDTH-1 downto 0);
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-- FEEDBACK SIGNALS
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feedback_seq_len : out std_logic_vector(F_SEQ_ADDR_WIDTH-1 downto 0);
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feedback_seq_addr : out std_logic_vector(F_SEQ_ADDR_WIDTH-1 downto 0);
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feedback_seq_ready : in std_logic;
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feedback_seq_ren : out std_logic;
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feedback_seq_wen : out std_logic;
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feedback_seq_valid : in std_logic;
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feedback_seq_ack : out std_logic;
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feedback_seq_r : in std_logic_vector(CDR_LONG_WIDTH-1 downto 0);
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feedback_seq_w : out std_logic_vector(CDR_LONG_WIDTH-1 downto 0)
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);
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end entity;
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architecture arch of Fibonacci is
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--*****TYPE DECLARATION*****
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type STAGE_TYPE is (IDLE,START_EXECUTION,INITIALIZE_EXECUTION,EXECUTE,FEEDBACK,TIMER,FINALIZE,CANCEL);
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--*****SIGNAL DECLARATION*****
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signal stage, stage_next : STAGE_TYPE;
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signal i, i_next : unsigned(R_RR_SEQ_ADDR_WIDTH-1 downto 0);
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signal order, order_next, a, a_next, b, b_next : unsigned(CDR_LONG_WIDTH-1 downto 0);
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signal handle, handle_next : std_logic_vector(GOAL_HANDLE_WIDTH-1 downto 0);
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signal ind, ind_next : std_logic_vector(WORD_WIDTH-1 downto 0);
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signal cnt, cnt_next : natural range 0 to 2;
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signal deadline, deadline_next : ROS_TIME_TYPE;
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||||||
|
begin
|
||||||
|
|
||||||
|
index_result <= ind;
|
||||||
|
feedback_seq_len <= std_logic_vector(i);
|
||||||
|
result_seq_len <= std_logic_vector(i);
|
||||||
|
|
||||||
|
main_prc : process(all)
|
||||||
|
begin
|
||||||
|
-- DEFAULT
|
||||||
|
stage_next <= stage;
|
||||||
|
order_next <= order;
|
||||||
|
a_next <= a;
|
||||||
|
b_next <= b;
|
||||||
|
handle_next <= handle;
|
||||||
|
ind_next <= ind;
|
||||||
|
cnt_next <= cnt;
|
||||||
|
i_next <= i;
|
||||||
|
deadline_next <= deadline;
|
||||||
|
-- DEFAULT Unregistered
|
||||||
|
new_goal_accepted <= '0';
|
||||||
|
new_goal_response <= '0';
|
||||||
|
cancel_accepted <= '0';
|
||||||
|
cancel_response <= '0';
|
||||||
|
start <= '0';
|
||||||
|
index_result_wen <= '0';
|
||||||
|
opcode <= NOP;
|
||||||
|
goal_handle_in <= GOAL_HANDLE_UNKNOWN;
|
||||||
|
goal_state_in <= GoalStatus_package.STATUS_UNKNOWN;
|
||||||
|
feedback_seq_ren <= '0';
|
||||||
|
result_seq_ren <= '0';
|
||||||
|
feedback_seq_wen <= '0';
|
||||||
|
result_seq_wen <= '0';
|
||||||
|
feedback_seq_ack <= '0';
|
||||||
|
result_seq_ack <= '0';
|
||||||
|
feedback_seq_addr <= (others => '0');
|
||||||
|
result_seq_addr <= (others => '0');
|
||||||
|
feedback_seq_w <= (others => '0');
|
||||||
|
result_seq_w <= (others => '0');
|
||||||
|
|
||||||
|
case (stage) is
|
||||||
|
when IDLE =>
|
||||||
|
if (new_goal_request = '1') then
|
||||||
|
new_goal_accepted <= '1';
|
||||||
|
new_goal_response <= '1';
|
||||||
|
|
||||||
|
-- Latch DATA
|
||||||
|
order_next <= unsigned(new_goal_order);
|
||||||
|
handle_next <= new_goal_handle;
|
||||||
|
ind_next <= new_goal_result_index;
|
||||||
|
|
||||||
|
stage_next <= START_EXECUTION;
|
||||||
|
cnt_next <= 0;
|
||||||
|
elsif (cancel_request = '1') then
|
||||||
|
cancel_response <= '1';
|
||||||
|
end if;
|
||||||
|
when START_EXECUTION =>
|
||||||
|
case (cnt) is
|
||||||
|
when 0 =>
|
||||||
|
start <= '1';
|
||||||
|
opcode <= UPDATE_GOAL_STATE;
|
||||||
|
goal_handle_in <= handle;
|
||||||
|
goal_state_in <= GoalStatus_package.STATUS_EXECUTING;
|
||||||
|
if (ack = '1') then
|
||||||
|
cnt_next <= cnt + 1;
|
||||||
|
end if;
|
||||||
|
when 1 =>
|
||||||
|
if (done = '1') then
|
||||||
|
assert (return_code = ROS_RET_OK) severity FAILURE;
|
||||||
|
stage_next <= INITIALIZE_EXECUTION;
|
||||||
|
cnt_next <= 0;
|
||||||
|
end if;
|
||||||
|
when others =>
|
||||||
|
null;
|
||||||
|
end case;
|
||||||
|
when INITIALIZE_EXECUTION =>
|
||||||
|
case (cnt) is
|
||||||
|
when 0 =>
|
||||||
|
feedback_seq_addr <= std_logic_vector(i);
|
||||||
|
result_seq_addr <= std_logic_vector(i);
|
||||||
|
feedback_seq_w <= (others => '0');
|
||||||
|
result_seq_w <= (others => '0');
|
||||||
|
a_next <= (others => '0');
|
||||||
|
|
||||||
|
if (feedback_seq_ready = '1' and result_seq_ready = '1') then
|
||||||
|
feedback_seq_wen <= '1';
|
||||||
|
result_seq_wen <= '1';
|
||||||
|
|
||||||
|
i_next <= i + 1;
|
||||||
|
cnt_next <= cnt + 1;
|
||||||
|
end if;
|
||||||
|
when 1 =>
|
||||||
|
feedback_seq_addr <= std_logic_vector(i);
|
||||||
|
result_seq_addr <= std_logic_vector(i);
|
||||||
|
feedback_seq_w <= (0 => '1', others => '0');
|
||||||
|
result_seq_w <= (0 => '1', others => '0');
|
||||||
|
b_next <= (0 => '1', others => '0');
|
||||||
|
|
||||||
|
if (feedback_seq_ready = '1' and result_seq_ready = '1') then
|
||||||
|
feedback_seq_wen <= '1';
|
||||||
|
result_seq_wen <= '1';
|
||||||
|
|
||||||
|
i_next <= i + 1;
|
||||||
|
if (order /= 0) then
|
||||||
|
order_next <= order - 1;
|
||||||
|
end if;
|
||||||
|
stage_next <= TIMER;
|
||||||
|
cnt_next <= 0;
|
||||||
|
end if;
|
||||||
|
when others =>
|
||||||
|
null;
|
||||||
|
end case;
|
||||||
|
when EXECUTE =>
|
||||||
|
case (cnt) is
|
||||||
|
when 0 =>
|
||||||
|
a_next <= b;
|
||||||
|
b_next <= a + b;
|
||||||
|
|
||||||
|
cnt_next <= cnt + 1;
|
||||||
|
when 1 =>
|
||||||
|
feedback_seq_addr <= std_logic_vector(i);
|
||||||
|
result_seq_addr <= std_logic_vector(i);
|
||||||
|
feedback_seq_w <= std_logic_vector(b);
|
||||||
|
result_seq_w <= std_logic_vector(b);
|
||||||
|
|
||||||
|
if (feedback_seq_ready = '1' and result_seq_ready = '1') then
|
||||||
|
feedback_seq_wen <= '1';
|
||||||
|
result_seq_wen <= '1';
|
||||||
|
|
||||||
|
i_next <= i + 1;
|
||||||
|
order_next <= order - 1;
|
||||||
|
stage_next <= FEEDBACK;
|
||||||
|
cnt_next <= 0;
|
||||||
|
end if;
|
||||||
|
when others =>
|
||||||
|
null;
|
||||||
|
end case;
|
||||||
|
when FEEDBACK =>
|
||||||
|
case (cnt) is
|
||||||
|
when 0 =>
|
||||||
|
start <= '1';
|
||||||
|
opcode <= PUBLISH_FEEDBACK;
|
||||||
|
goal_handle_in <= handle;
|
||||||
|
if (ack = '1') then
|
||||||
|
cnt_next <= cnt + 1;
|
||||||
|
end if;
|
||||||
|
when 1 =>
|
||||||
|
if (done = '1') then
|
||||||
|
assert (return_code = ROS_RET_OK) severity FAILURE;
|
||||||
|
stage_next <= TIMER;
|
||||||
|
cnt_next <= 0;
|
||||||
|
end if;
|
||||||
|
when others =>
|
||||||
|
null;
|
||||||
|
end case;
|
||||||
|
when TIMER =>
|
||||||
|
case (cnt) is
|
||||||
|
when 0 =>
|
||||||
|
-- NOTE: During simulation we essentially skip the timer
|
||||||
|
if (ros_config.SIMULATION_TIMING) then
|
||||||
|
deadline_next <= time;
|
||||||
|
else
|
||||||
|
deadline_next.sec <= std_logic_vector(unsigned(time.sec) + 1);
|
||||||
|
deadline_next.nanosec <= time.nanosec;
|
||||||
|
end if;
|
||||||
|
|
||||||
|
cnt_next <= cnt + 1;
|
||||||
|
when 1 =>
|
||||||
|
if (cancel_request = '1') then
|
||||||
|
cancel_response <= '1';
|
||||||
|
|
||||||
|
if (cancel_request_handle = handle) then
|
||||||
|
cancel_accepted <= '1';
|
||||||
|
stage_next <= CANCEL;
|
||||||
|
cnt_next <= 0;
|
||||||
|
end if;
|
||||||
|
elsif (deadline <= time) then
|
||||||
|
if (order = 0) then
|
||||||
|
stage_next <= FINALIZE;
|
||||||
|
cnt_next <= 0;
|
||||||
|
else
|
||||||
|
stage_next <= EXECUTE;
|
||||||
|
cnt_next <= 0;
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
when others =>
|
||||||
|
null;
|
||||||
|
end case;
|
||||||
|
when FINALIZE =>
|
||||||
|
case (cnt) is
|
||||||
|
when 0 =>
|
||||||
|
index_result_wen <= '1';
|
||||||
|
|
||||||
|
if (index_result_ready = '1') then
|
||||||
|
cnt_next <= cnt + 1;
|
||||||
|
end if;
|
||||||
|
when 1 =>
|
||||||
|
start <= '1';
|
||||||
|
opcode <= UPDATE_GOAL_STATE;
|
||||||
|
goal_handle_in <= handle;
|
||||||
|
goal_state_in <= GoalStatus_package.STATUS_SUCCEEDED;
|
||||||
|
if (ack = '1') then
|
||||||
|
cnt_next <= cnt + 1;
|
||||||
|
end if;
|
||||||
|
when 2 =>
|
||||||
|
if (done = '1') then
|
||||||
|
assert (return_code = ROS_RET_OK) severity FAILURE;
|
||||||
|
stage_next <= IDLE;
|
||||||
|
end if;
|
||||||
|
when others =>
|
||||||
|
null;
|
||||||
|
end case;
|
||||||
|
when CANCEL =>
|
||||||
|
case (cnt) is
|
||||||
|
when 0 =>
|
||||||
|
start <= '1';
|
||||||
|
opcode <= UPDATE_GOAL_STATE;
|
||||||
|
goal_handle_in <= handle;
|
||||||
|
goal_state_in <= GoalStatus_package.STATUS_CANCELED;
|
||||||
|
if (ack = '1') then
|
||||||
|
cnt_next <= cnt + 1;
|
||||||
|
end if;
|
||||||
|
when 1 =>
|
||||||
|
if (done = '1') then
|
||||||
|
assert (return_code = ROS_RET_OK) severity FAILURE;
|
||||||
|
stage_next <= IDLE;
|
||||||
|
cnt_next <= 0;
|
||||||
|
end if;
|
||||||
|
when others =>
|
||||||
|
null;
|
||||||
|
end case;
|
||||||
|
end case;
|
||||||
|
end process;
|
||||||
|
|
||||||
|
sync_prc : process(clk)
|
||||||
|
begin
|
||||||
|
if rising_edge(clk) then
|
||||||
|
if (reset = '1') then
|
||||||
|
stage <= IDLE;
|
||||||
|
handle <= GOAL_HANDLE_UNKNOWN;
|
||||||
|
deadline <= ROS_TIME_INFINITE;
|
||||||
|
cnt <= 0;
|
||||||
|
order <= (others => '0');
|
||||||
|
a <= (others => '0');
|
||||||
|
b <= (others => '0');
|
||||||
|
ind <= (others => '0');
|
||||||
|
i <= (others => '0');
|
||||||
|
else
|
||||||
|
stage <= stage_next;
|
||||||
|
handle <= handle_next;
|
||||||
|
deadline <= deadline_next;
|
||||||
|
cnt <= cnt_next;
|
||||||
|
order <= order_next;
|
||||||
|
a <= a_next;
|
||||||
|
b <= b_next;
|
||||||
|
ind <= ind_next;
|
||||||
|
i <= i_next;
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
end process;
|
||||||
|
|
||||||
|
end architecture;
|
||||||
307
src/ros2/Tests/Level_2/L2_Fibonacci_ros_action_test1.vhd
Normal file
307
src/ros2/Tests/Level_2/L2_Fibonacci_ros_action_test1.vhd
Normal file
@ -0,0 +1,307 @@
|
|||||||
|
library ieee;
|
||||||
|
use ieee.std_logic_1164.all;
|
||||||
|
use ieee.numeric_std.all;
|
||||||
|
|
||||||
|
library osvvm; -- Utility Library
|
||||||
|
context osvvm.OsvvmContext;
|
||||||
|
|
||||||
|
library Testbench_ROS_Lib4;
|
||||||
|
library Testbench_ROS_Lib5;
|
||||||
|
|
||||||
|
use work.rtps_package.all;
|
||||||
|
use work.ros_package.all;
|
||||||
|
use work.rtps_test_package.all;
|
||||||
|
|
||||||
|
-- This testbench test the general the general ROS Action operation by interconnecting a system with a action client, with a system with a action server.
|
||||||
|
-- Libraries are used to allow to use systems with different configurations. Testbench_ROS_Lib4 contains the ROS service server, and Testbench_ROS_Lib5
|
||||||
|
-- contains the ROS service client.
|
||||||
|
-- The ROS Service is the Fibonacci service used in the example tutorials, which sends a a goal request of order 10, and gets the fibonacci sequence as
|
||||||
|
-- result.
|
||||||
|
|
||||||
|
|
||||||
|
entity L2_Fibonacci_ros_action_test1 is
|
||||||
|
end entity;
|
||||||
|
|
||||||
|
architecture testbench of L2_Fibonacci_ros_action_test1 is
|
||||||
|
|
||||||
|
signal clk, reset : std_logic := '0';
|
||||||
|
signal time : TIME_TYPE := TIME_ZERO;
|
||||||
|
signal empty_s, empty_c, read_s, read_c, full_s, full_c, write_s, write_c : std_logic := '0';
|
||||||
|
signal data_in_s, data_in_c, data_out_s, data_out_c : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
|
||||||
|
|
||||||
|
signal start_c, ack_c, done_c, data_available_c_c, data_available_g_c, data_available_r_c, data_available_f_c : std_logic := '0';
|
||||||
|
signal opcode_c : ROS_ACTION_OPCODE_TYPE := NOP;
|
||||||
|
signal sequence_id_c : std_logic_vector(ROS_SEQUENCE_ID_WIDTH-1 downto 0) := (others => '0');
|
||||||
|
signal service_info_c : Testbench_ROS_Lib5.ros_package.SERVICE_INFO_TYPE := Testbench_ROS_Lib5.ros_package.EMPTY_SERVICE_INFO;
|
||||||
|
signal return_code_c : std_logic_vector(ROS_RETCODE_WIDTH-1 downto 0) := (others => '0');
|
||||||
|
signal goal_id_c, result_goal_id_c, cancel_goal_id_c, cancel_goals_canceling_goal_id_c, feedback_goal_id_c : std_logic_vector(UUID_WIDTH-1 downto 0) := (others => '0');
|
||||||
|
signal goal_order_c, result_seq_c, feedback_seq_c : std_logic_vector(CDR_LONG_WIDTH-1 downto 0) := (others => '0');
|
||||||
|
signal goal_accepted_c, result_seq_ready_c, result_seq_ren_c, result_seq_valid_c, result_seq_ack_c : std_logic := '0';
|
||||||
|
signal goal_stamp_c, cancel_stamp_c : Testbench_ROS_Lib5.ros_package.ROS_TIME_TYPE := Testbench_ROS_Lib5.ros_package.ROS_TIME_ZERO;
|
||||||
|
signal result_status_c, cancel_return_code_c : std_logic_vector(CDR_INT8_WIDTH-1 downto 0) := (others => '0');
|
||||||
|
signal result_seq_len_c, result_seq_addr_c : std_logic_vector(Testbench_ROS_Lib5.Fibonacci_package.R_RR_SEQ_ADDR_WIDTH-1 downto 0) := (others => '0');
|
||||||
|
signal cancel_goals_canceling_len_c, cancel_goals_canceling_addr_c : std_logic_vector(Testbench_ROS_Lib5.CancelGoal_package.RR_GOALS_CANCELING_ADDR_WIDTH-1 downto 0) := (others => '0');
|
||||||
|
signal cancel_goals_canceling_ready_c, cancel_goals_canceling_ren_c, cancel_goals_canceling_valid_c, cancel_goals_canceling_ack_c : std_logic := '0';
|
||||||
|
signal cancel_goals_canceling_stamp_c : std_logic_vector(ROS_TIME_WIDTH-1 downto 0) := (others => '0');
|
||||||
|
signal feedback_seq_len_c, feedback_seq_addr_c : std_logic_vector(Testbench_ROS_Lib5.Fibonacci_package.F_SEQ_ADDR_WIDTH-1 downto 0) := (others => '0');
|
||||||
|
signal feedback_seq_ready_c, feedback_seq_ren_c, feedback_seq_valid_c, feedback_seq_ack_c : std_logic := '0';
|
||||||
|
|
||||||
|
-- HACK: For some reason (possibly Modelsim/Questasim Bug) I cannot declare the opcode signals from their respective Library sources,
|
||||||
|
-- because I cannot use a qualified expression to define an enumeration literal (and direct type casting cannot be done because
|
||||||
|
-- the types are not closely related). So I have to do define explicit type conversions between the types...
|
||||||
|
|
||||||
|
function to_Lib5(input : ROS_ACTION_OPCODE_TYPE) return Testbench_ROS_Lib5.ros_package.ROS_ACTION_OPCODE_TYPE is
|
||||||
|
begin
|
||||||
|
return Testbench_ROS_Lib5.ros_package.ROS_ACTION_OPCODE_TYPE'VAL(ROS_ACTION_OPCODE_TYPE'POS(input));
|
||||||
|
end function;
|
||||||
|
|
||||||
|
begin
|
||||||
|
|
||||||
|
server_inst : entity Testbench_ROS_Lib4.L2_Testbench_ROS_Lib4(arch)
|
||||||
|
port map (
|
||||||
|
-- SYSTEM
|
||||||
|
clk => clk,
|
||||||
|
reset => reset,
|
||||||
|
time => Testbench_ROS_Lib4.rtps_package.TIME_TYPE(time),
|
||||||
|
-- INPUT
|
||||||
|
empty => empty_s,
|
||||||
|
read => read_s,
|
||||||
|
data_in => data_in_s,
|
||||||
|
-- OUTPUT
|
||||||
|
full => full_s,
|
||||||
|
write => write_s,
|
||||||
|
data_out => data_out_s
|
||||||
|
);
|
||||||
|
|
||||||
|
fifo_s_c_inst : configuration Testbench_ROS_Lib4.FWFT_FIFO_cfg
|
||||||
|
generic map (
|
||||||
|
FIFO_DEPTH => 65536/(WORD_WIDTH/BYTE_WIDTH),
|
||||||
|
DATA_WIDTH => WORD_WIDTH
|
||||||
|
)
|
||||||
|
port map
|
||||||
|
(
|
||||||
|
reset => reset,
|
||||||
|
clk => clk,
|
||||||
|
data_in => data_out_s,
|
||||||
|
write => write_s,
|
||||||
|
read => read_c,
|
||||||
|
data_out => data_in_c,
|
||||||
|
empty => empty_c,
|
||||||
|
full => full_s,
|
||||||
|
free => open
|
||||||
|
);
|
||||||
|
|
||||||
|
fifo_c_s_inst : configuration Testbench_ROS_Lib4.FWFT_FIFO_cfg
|
||||||
|
generic map (
|
||||||
|
FIFO_DEPTH => 65536/(WORD_WIDTH/BYTE_WIDTH),
|
||||||
|
DATA_WIDTH => WORD_WIDTH
|
||||||
|
)
|
||||||
|
port map
|
||||||
|
(
|
||||||
|
reset => reset,
|
||||||
|
clk => clk,
|
||||||
|
data_in => data_out_c,
|
||||||
|
write => write_c,
|
||||||
|
read => read_s,
|
||||||
|
data_out => data_in_s,
|
||||||
|
empty => empty_s,
|
||||||
|
full => full_c,
|
||||||
|
free => open
|
||||||
|
);
|
||||||
|
|
||||||
|
client_inst : entity Testbench_ROS_Lib5.L2_Testbench_ROS_Lib5(arch)
|
||||||
|
port map (
|
||||||
|
-- SYSTEM
|
||||||
|
clk => clk,
|
||||||
|
reset => reset,
|
||||||
|
time => Testbench_ROS_Lib5.rtps_package.TIME_TYPE(time),
|
||||||
|
-- INPUT
|
||||||
|
empty => empty_c,
|
||||||
|
read => read_c,
|
||||||
|
data_in => data_in_c,
|
||||||
|
-- OUTPUT
|
||||||
|
full => full_c,
|
||||||
|
write => write_c,
|
||||||
|
data_out => data_out_c,
|
||||||
|
-- SERVICE CLIENT
|
||||||
|
start_c => start_c,
|
||||||
|
opcode_c => to_Lib5(opcode_c),
|
||||||
|
ack_c => ack_c,
|
||||||
|
sequence_id_c => sequence_id_c,
|
||||||
|
service_info_c => service_info_c,
|
||||||
|
data_available_g_c => data_available_g_c,
|
||||||
|
data_available_r_c => data_available_r_c,
|
||||||
|
data_available_c_c => data_available_c_c,
|
||||||
|
data_available_f_c => data_available_f_c,
|
||||||
|
done_c => done_c,
|
||||||
|
return_code_c => return_code_c,
|
||||||
|
goal_id_c => goal_id_c,
|
||||||
|
goal_order_c => goal_order_c,
|
||||||
|
goal_accepted_c => goal_accepted_c,
|
||||||
|
goal_stamp_c => goal_stamp_c,
|
||||||
|
result_goal_id_c => result_goal_id_c,
|
||||||
|
result_status_c => result_status_c,
|
||||||
|
result_seq_len_c => result_seq_len_c,
|
||||||
|
result_seq_addr_c => result_seq_addr_c,
|
||||||
|
result_seq_ready_c => result_seq_ready_c,
|
||||||
|
result_seq_ren_c => result_seq_ren_c,
|
||||||
|
result_seq_valid_c => result_seq_valid_c,
|
||||||
|
result_seq_ack_c => result_seq_ack_c,
|
||||||
|
result_seq_c => result_seq_c,
|
||||||
|
cancel_goal_id_c => cancel_goal_id_c,
|
||||||
|
cancel_stamp_c => cancel_stamp_c,
|
||||||
|
cancel_return_code_c => cancel_return_code_c,
|
||||||
|
cancel_goals_canceling_len_c => cancel_goals_canceling_len_c,
|
||||||
|
cancel_goals_canceling_addr_c => cancel_goals_canceling_addr_c,
|
||||||
|
cancel_goals_canceling_ready_c => cancel_goals_canceling_ready_c,
|
||||||
|
cancel_goals_canceling_ren_c => cancel_goals_canceling_ren_c,
|
||||||
|
cancel_goals_canceling_valid_c => cancel_goals_canceling_valid_c,
|
||||||
|
cancel_goals_canceling_ack_c => cancel_goals_canceling_ack_c,
|
||||||
|
cancel_goals_canceling_goal_id_c => cancel_goals_canceling_goal_id_c,
|
||||||
|
cancel_goals_canceling_stamp_c => cancel_goals_canceling_stamp_c,
|
||||||
|
feedback_goal_id_c => feedback_goal_id_c,
|
||||||
|
feedback_seq_len_c => feedback_seq_len_c,
|
||||||
|
feedback_seq_addr_c => feedback_seq_addr_c,
|
||||||
|
feedback_seq_ready_c => feedback_seq_ready_c,
|
||||||
|
feedback_seq_ren_c => feedback_seq_ren_c,
|
||||||
|
feedback_seq_valid_c => feedback_seq_valid_c,
|
||||||
|
feedback_seq_ack_c => feedback_seq_ack_c,
|
||||||
|
feedback_seq_c => feedback_seq_c
|
||||||
|
);
|
||||||
|
|
||||||
|
stimulus_prc : process
|
||||||
|
variable RV : RandomPType;
|
||||||
|
variable ref : std_logic_vector(CDR_LONG_LONG_WIDTH-1 downto 0);
|
||||||
|
variable sid : std_logic_vector(ROS_SEQUENCE_ID_WIDTH-1 downto 0);
|
||||||
|
variable a, b, c : natural;
|
||||||
|
|
||||||
|
-- Waits until signal toggles high for at least 1 ps
|
||||||
|
procedure wait_on_sig(signal sig : std_logic) is
|
||||||
|
begin
|
||||||
|
loop
|
||||||
|
if (sig /= '1') then
|
||||||
|
wait on sig until sig = '1';
|
||||||
|
end if;
|
||||||
|
-- Prevent triggering on glitches
|
||||||
|
wait for 1 ps;
|
||||||
|
if (sig = '1') then
|
||||||
|
exit;
|
||||||
|
end if;
|
||||||
|
end loop;
|
||||||
|
end procedure;
|
||||||
|
|
||||||
|
impure function gen_goal_id return std_logic_vector is
|
||||||
|
begin
|
||||||
|
return RV.RandSlv(UUID_WIDTH);
|
||||||
|
end function;
|
||||||
|
|
||||||
|
procedure client_op(op : in ROS_ACTION_OPCODE_TYPE; ret : in std_logic_vector(ROS_RETCODE_WIDTH-1 downto 0)) is
|
||||||
|
begin
|
||||||
|
start_c <= '1';
|
||||||
|
opcode_c <= op;
|
||||||
|
wait_on_sig(ack_c);
|
||||||
|
wait until rising_edge(clk);
|
||||||
|
start_c <= '0';
|
||||||
|
wait_on_sig(done_c);
|
||||||
|
wait for 1 ps; -- Make sure all signals stable
|
||||||
|
AlertIf(return_code_c /= ret, "Unexpected Client Response", FAILURE);
|
||||||
|
end procedure;
|
||||||
|
begin
|
||||||
|
|
||||||
|
SetAlertLogName("L2_Fibonacci_ros_action_test1 - General");
|
||||||
|
SetAlertEnable(FAILURE, TRUE);
|
||||||
|
SetAlertEnable(ERROR, TRUE);
|
||||||
|
SetAlertEnable(WARNING, TRUE);
|
||||||
|
SetLogEnable(DEBUG, FALSE);
|
||||||
|
SetLogEnable(PASSED, FALSE);
|
||||||
|
SetLogEnable(INFO, TRUE);
|
||||||
|
RV.InitSeed(RV'instance_name);
|
||||||
|
|
||||||
|
Log("Initial Reset", INFO);
|
||||||
|
reset <= '1';
|
||||||
|
wait until rising_edge(clk);
|
||||||
|
wait until rising_edge(clk);
|
||||||
|
reset <= '0';
|
||||||
|
|
||||||
|
Log("Sent Goal Request (Goal 1, Order 10)", INFO);
|
||||||
|
goal_id_c <= gen_goal_id;
|
||||||
|
goal_order_c <= int(10,goal_order_c'length);
|
||||||
|
client_op(SEND_GOAL_REQUEST,ROS_RET_OK);
|
||||||
|
sid := sequence_id_c;
|
||||||
|
wait until rising_edge(clk);
|
||||||
|
|
||||||
|
wait_on_sig(data_available_g_c);
|
||||||
|
|
||||||
|
Log("Take Goal Response", INFO);
|
||||||
|
client_op(TAKE_GOAL_RESPONSE,ROS_RET_OK);
|
||||||
|
AffirmIfEqual(to_unsigned(SEQUENCENUMBER_TYPE(service_info_c.request_id.sequence_number)), unsigned(sid));
|
||||||
|
AffirmIfEqual(goal_accepted_c, '1');
|
||||||
|
wait until rising_edge(clk);
|
||||||
|
|
||||||
|
Log("Sent Result Request (Goal 1)", INFO);
|
||||||
|
result_goal_id_c <= goal_id_c;
|
||||||
|
client_op(SEND_RESULT_REQUEST,ROS_RET_OK);
|
||||||
|
sid := sequence_id_c;
|
||||||
|
wait until rising_edge(clk);
|
||||||
|
|
||||||
|
wait_on_sig(data_available_r_c);
|
||||||
|
|
||||||
|
Log("Take Result Response", INFO);
|
||||||
|
client_op(TAKE_RESULT_RESPONSE,ROS_RET_OK);
|
||||||
|
AffirmIfEqual(to_unsigned(SEQUENCENUMBER_TYPE(service_info_c.request_id.sequence_number)), unsigned(sid));
|
||||||
|
AffirmIfEqual(result_status_c, Testbench_ROS_Lib5.GoalStatus_package.STATUS_SUCCEEDED);
|
||||||
|
AffirmIfEqual(result_seq_len_c, int(11,result_seq_len_c'length));
|
||||||
|
a := 0;
|
||||||
|
b := 1;
|
||||||
|
c := a + b;
|
||||||
|
for i in 0 to to_integer(unsigned(result_seq_len_c))-1 loop
|
||||||
|
result_seq_addr_c <= int(i,result_seq_addr_c'length);
|
||||||
|
wait_on_sig(result_seq_ready_c);
|
||||||
|
result_seq_ren_c <= '1';
|
||||||
|
wait until rising_edge(clk);
|
||||||
|
result_seq_ren_c <= '0';
|
||||||
|
wait_on_sig(result_seq_valid_c);
|
||||||
|
AffirmIfEqual(result_seq_c, int(a,result_seq_c'length));
|
||||||
|
a := b;
|
||||||
|
b := c;
|
||||||
|
c := a + b;
|
||||||
|
result_seq_ack_c <= '1';
|
||||||
|
wait until rising_edge(clk);
|
||||||
|
result_seq_ack_c <= '0';
|
||||||
|
end loop;
|
||||||
|
|
||||||
|
TranscriptOpen(RESULTS_FILE, APPEND_MODE);
|
||||||
|
SetTranscriptMirror;
|
||||||
|
ReportAlerts;
|
||||||
|
TranscriptClose;
|
||||||
|
std.env.stop;
|
||||||
|
wait;
|
||||||
|
end process;
|
||||||
|
|
||||||
|
clock_prc : process
|
||||||
|
begin
|
||||||
|
clk <= '0';
|
||||||
|
wait for TEST_CLOCK_PERIOD/2;
|
||||||
|
clk <= '1';
|
||||||
|
wait for TEST_CLOCK_PERIOD/2;
|
||||||
|
end process;
|
||||||
|
|
||||||
|
time_prc : process(clk)
|
||||||
|
begin
|
||||||
|
if rising_edge(clk) then
|
||||||
|
if (reset = '1') then
|
||||||
|
time <= TIME_ZERO;
|
||||||
|
else
|
||||||
|
time <= time + gen_duration(TEST_CLOCK_PERIOD);
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
end process;
|
||||||
|
|
||||||
|
watchdog : process
|
||||||
|
begin
|
||||||
|
wait for 1 ms;
|
||||||
|
Alert("Test timeout", FAILURE);
|
||||||
|
std.env.stop;
|
||||||
|
end process;
|
||||||
|
|
||||||
|
end architecture;
|
||||||
957
src/ros2/Tests/Level_2/L2_Testbench_ROS_Lib4.vhd
Normal file
957
src/ros2/Tests/Level_2/L2_Testbench_ROS_Lib4.vhd
Normal file
@ -0,0 +1,957 @@
|
|||||||
|
-- altera vhdl_input_version vhdl_2008
|
||||||
|
-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
|
||||||
|
|
||||||
|
library ieee;
|
||||||
|
use ieee.std_logic_1164.all;
|
||||||
|
use ieee.numeric_std.all;
|
||||||
|
|
||||||
|
use work.ros_package.all;
|
||||||
|
use work.ros_config.all;
|
||||||
|
use work.rtps_package.all;
|
||||||
|
use work.user_config.all;
|
||||||
|
use work.rtps_config_package.all;
|
||||||
|
use work.Fibonacci_package.all;
|
||||||
|
|
||||||
|
entity L2_Testbench_ROS_Lib4 is
|
||||||
|
port (
|
||||||
|
-- SYSTEM
|
||||||
|
clk : in std_logic;
|
||||||
|
reset : in std_logic;
|
||||||
|
time : in TIME_TYPE;
|
||||||
|
-- INPUT
|
||||||
|
empty : in std_logic;
|
||||||
|
read : out std_logic;
|
||||||
|
data_in : in std_logic_vector(WORD_WIDTH-1 downto 0);
|
||||||
|
-- OUTPUT
|
||||||
|
full : in std_logic;
|
||||||
|
write : out std_logic;
|
||||||
|
data_out : out std_logic_vector(WORD_WIDTH-1 downto 0)
|
||||||
|
);
|
||||||
|
end entity;
|
||||||
|
|
||||||
|
architecture arch of L2_Testbench_ROS_Lib4 is
|
||||||
|
|
||||||
|
type EARRAY_DATA_TYPE is array (0 to NUM_ENDPOINTS-1) of std_logic_vector(WORD_WIDTH downto 0);
|
||||||
|
type HISTORY_CACHE_OPCODE_RARRAY_TYPE is array (0 to NUM_READERS-1) of HISTORY_CACHE_OPCODE_TYPE;
|
||||||
|
type HISTORY_CACHE_OPCODE_WARRAY_TYPE is array (0 to NUM_WRITERS-1) of HISTORY_CACHE_OPCODE_TYPE;
|
||||||
|
type HISTORY_CACHE_RESPONSE_RARRAY_TYPE is array (0 to NUM_READERS-1) of HISTORY_CACHE_RESPONSE_TYPE;
|
||||||
|
type HISTORY_CACHE_RESPONSE_WARRAY_TYPE is array (0 to NUM_WRITERS-1) of HISTORY_CACHE_RESPONSE_TYPE;
|
||||||
|
type RARRAY_DATA_TYPE is array (0 to NUM_READERS-1) of std_logic_vector(WORD_WIDTH downto 0);
|
||||||
|
type WARRAY_DATA_TYPE is array (0 to NUM_WRITERS-1) of std_logic_vector(WORD_WIDTH downto 0);
|
||||||
|
type SEQUENCENUMBER_WARRAY_TYPE is array (0 to NUM_WRITERS-1) of SEQUENCENUMBER_TYPE;
|
||||||
|
type INSTANCE_HANDLE_RARRAY_TYPE is array (0 to NUM_READERS-1) of INSTANCE_HANDLE_TYPE;
|
||||||
|
type INSTANCE_HANDLE_WARRAY_TYPE is array (0 to NUM_WRITERS-1) of INSTANCE_HANDLE_TYPE;
|
||||||
|
type CACHE_CHANGE_KIND_WARRAY_TYPE is array (0 to NUM_WRITERS-1) of CACHE_CHANGE_KIND_TYPE;
|
||||||
|
type TIME_WARRAY_TYPE is array (0 to NUM_WRITERS-1) of TIME_TYPE;
|
||||||
|
type DDS_READER_OPCODE_RARRAY_TYPE is array (0 to NUM_READERS-1) of DDS_READER_OPCODE_TYPE;
|
||||||
|
type DDS_WRITER_OPCODE_WARRAY_TYPE is array (0 to NUM_WRITERS-1) of DDS_WRITER_OPCODE_TYPE;
|
||||||
|
type INSTANCE_STATE_RARRAY_TYPE is array (0 to NUM_READERS-1) of std_logic_vector(INSTANCE_STATE_KIND_WIDTH-1 downto 0);
|
||||||
|
type VIEW_STATE_RARRAY_TYPE is array (0 to NUM_READERS-1) of std_logic_vector(VIEW_STATE_KIND_WIDTH-1 downto 0);
|
||||||
|
type SAMPLE_STATE_RARRAY_TYPE is array (0 to NUM_READERS-1) of std_logic_vector(SAMPLE_STATE_KIND_WIDTH-1 downto 0);
|
||||||
|
type MAX_SAMPLES_RARRAY_TYPE is array (0 to NUM_READERS-1) of std_logic_vector(MAX_SAMPLES_WIDTH-1 downto 0);
|
||||||
|
type RETURN_CODE_RARRAY_TYPE is array (0 to NUM_READERS-1) of std_logic_vector(RETURN_CODE_WIDTH-1 downto 0);
|
||||||
|
type RETURN_CODE_WARRAY_TYPE is array (0 to NUM_WRITERS-1) of std_logic_vector(RETURN_CODE_WIDTH-1 downto 0);
|
||||||
|
type STATUS_KIND_RARRAY_TYPE is array (0 to NUM_READERS-1) of std_logic_vector(STATUS_KIND_WIDTH-1 downto 0);
|
||||||
|
type STATUS_KIND_WARRAY_TYPE is array (0 to NUM_WRITERS-1) of std_logic_vector(STATUS_KIND_WIDTH-1 downto 0);
|
||||||
|
type DURATION_WARRAY_TYPE is array (0 to NUM_WRITERS-1) of DURATION_TYPE;
|
||||||
|
type SAMPLE_INFO_RARRAY_TYPE is array (0 to NUM_READERS-1) of SAMPLE_INFO_TYPE;
|
||||||
|
|
||||||
|
signal ros_time : ROS_TIME_TYPE;
|
||||||
|
signal full_fire_rh, write_rh_fire : std_logic_vector(0 to NUM_ENDPOINTS-1);
|
||||||
|
signal data_rh_fire, data_rh_fidm : std_logic_vector(WORD_WIDTH downto 0);
|
||||||
|
signal full_fidm_rh, write_rh_fidm : std_logic;
|
||||||
|
signal read_dm_fidm, empty_fidm_dm : std_logic;
|
||||||
|
signal data_fidm_dm : std_logic_vector(WORD_WIDTH downto 0);
|
||||||
|
signal read_re_fire, empty_fire_re : std_logic_vector(0 to NUM_ENDPOINTS);
|
||||||
|
signal data_fire_re : EARRAY_DATA_TYPE;
|
||||||
|
signal alive_re_dm, full_fdmre_re, write_dm_fdmre : std_logic_vector(0 to NUM_ENDPOINTS-1);
|
||||||
|
signal data_dm_fdmre , data_dm_firo : std_logic_vector(WORD_WIDTH downto 0);
|
||||||
|
signal full_firo_dm, write_dm_firo : std_logic;
|
||||||
|
signal empty_fdmre_re, read_re_fdmre : std_logic_vector(0 to NUM_ENDPOINTS-1);
|
||||||
|
signal data_fdmre_re : EARRAY_DATA_TYPE;
|
||||||
|
signal full_firo_re, write_re_firo : std_logic_vector(0 to NUM_ENDPOINTS-1);
|
||||||
|
signal data_re_firo : EARRAY_DATA_TYPE;
|
||||||
|
signal start_rr_dr, ack_dr_rr, done_dr_rr, valid_rr_dr, ready_dr_rr : std_logic_vector(0 to NUM_READERS-1);
|
||||||
|
signal opcode_rr_dr : HISTORY_CACHE_OPCODE_RARRAY_TYPE;
|
||||||
|
signal ret_dr_rr : HISTORY_CACHE_RESPONSE_RARRAY_TYPE;
|
||||||
|
signal data_rr_dr : RARRAY_DATA_TYPE;
|
||||||
|
signal liveliness_assertion_dw_rw, data_available_dw_rw, start_rw_dw, ack_dw_rw, done_rw_dw, get_data_rw_dw, valid_dw_rw, ready_rw_dw : std_logic_vector(0 to NUM_WRITERS-1);
|
||||||
|
signal opcode_rw_dw : HISTORY_CACHE_OPCODE_WARRAY_TYPE;
|
||||||
|
signal seq_nr_rw_dw, cc_seq_nr_dw_rw : SEQUENCENUMBER_WARRAY_TYPE;
|
||||||
|
signal ret_dw_rw : HISTORY_CACHE_RESPONSE_WARRAY_TYPE;
|
||||||
|
signal data_dw_rw : WARRAY_DATA_TYPE;
|
||||||
|
signal cc_instance_handle_dw_rw : INSTANCE_HANDLE_WARRAY_TYPE;
|
||||||
|
signal cc_kind_dw_rw : CACHE_CHANGE_KIND_WARRAY_TYPE;
|
||||||
|
signal cc_source_timestamp_dw_rw : TIME_WARRAY_TYPE;
|
||||||
|
signal sample_info_dr_ri : SAMPLE_INFO_RARRAY_TYPE;
|
||||||
|
signal start_ri_dr, ack_dr_ri, get_data_ri_dr, done_dr_ri, ready_ri_dr, valid_dr_ri, sample_info_valid_dr_ri, sample_info_ack_ri_dr, eoc_dr_ri : std_logic_vector(0 to NUM_READERS-1);
|
||||||
|
signal opcode_ri_dr : DDS_READER_OPCODE_RARRAY_TYPE;
|
||||||
|
signal instance_state_ri_dr : INSTANCE_STATE_RARRAY_TYPE;
|
||||||
|
signal view_state_ri_dr : VIEW_STATE_RARRAY_TYPE;
|
||||||
|
signal sample_state_ri_dr : SAMPLE_STATE_RARRAY_TYPE;
|
||||||
|
signal instance_handle_ri_dr : INSTANCE_HANDLE_RARRAY_TYPE;
|
||||||
|
signal max_samples_ri_dr : MAX_SAMPLES_RARRAY_TYPE;
|
||||||
|
signal return_code_dr_ri : RETURN_CODE_RARRAY_TYPE;
|
||||||
|
signal data_dr_ri : RARRAY_DATA_TYPE;
|
||||||
|
signal status_dr_ri : STATUS_KIND_RARRAY_TYPE;
|
||||||
|
signal start_wi_dw, ack_dw_wi, done_dw_wi, valid_wi_dw, valid_dw_wi, ready_wi_dw, ready_dw_wi : std_logic_vector(0 to NUM_WRITERS-1);
|
||||||
|
signal opcode_wi_dw : DDS_WRITER_OPCODE_WARRAY_TYPE;
|
||||||
|
signal instance_handle_wi_dw, instance_handle_dw_wi : INSTANCE_HANDLE_WARRAY_TYPE;
|
||||||
|
signal source_ts_wi_dw : TIME_WARRAY_TYPE;
|
||||||
|
signal max_wait_wi_dw : DURATION_WARRAY_TYPE;
|
||||||
|
signal return_code_dw_wi : RETURN_CODE_WARRAY_TYPE;
|
||||||
|
signal data_dw_wi, data_wi_dw : WARRAY_DATA_TYPE;
|
||||||
|
signal status_dw_wi : STATUS_KIND_WARRAY_TYPE;
|
||||||
|
signal empty_firo_ro, read_ro_firo, last_word_firo_ro : std_logic_vector(0 to NUM_ENDPOINTS);
|
||||||
|
signal data_firo_ro : RTPS_OUT_DATA_TYPE;
|
||||||
|
signal action_if : ACTION_INTERFACE_ARRAY_TYPE(0 to NUM_ACTIONS-1);
|
||||||
|
-- ###GENERATED START###
|
||||||
|
signal start_s, ack_s, done_s : std_logic;
|
||||||
|
signal opcode_s : ROS_ACTION_OPCODE_TYPE;
|
||||||
|
signal return_code_s : std_logic_vector(ROS_RETCODE_WIDTH-1 downto 0);
|
||||||
|
signal goal_handle_in_s, goal_handle_out_s, new_goal_handle_s, cancel_request_handle_s : std_logic_vector(GOAL_HANDLE_WIDTH-1 downto 0);
|
||||||
|
signal goal_state_in_s, goal_state_out_s : std_logic_vector(CDR_INT8_WIDTH-1 downto 0);
|
||||||
|
signal goal_id_s : std_logic_vector(UUID_WIDTH-1 downto 0);
|
||||||
|
signal goal_result_index_s, new_goal_result_index_s, index_result_s : std_logic_vector(WORD_WIDTH-1 downto 0);
|
||||||
|
signal goal_stamp_s : ROS_TIME_TYPE;
|
||||||
|
signal new_goal_request_s, new_goal_accepted_s, new_goal_response_s, cancel_request_s, cancel_accepted_s, cancel_response_s, index_result_wen_s, index_result_ready_s : std_logic;
|
||||||
|
signal new_goal_order_s : std_logic_vector(CDR_LONG_WIDTH-1 downto 0);
|
||||||
|
signal result_seq_len_s, result_seq_addr_s : std_logic_vector(R_RR_SEQ_ADDR_WIDTH-1 downto 0);
|
||||||
|
signal result_seq_ready_s, result_seq_ren_s, result_seq_wen_s, result_seq_valid_s, result_seq_ack_s : std_logic;
|
||||||
|
signal result_seq_r_s, result_seq_w_s : std_logic_vector(CDR_LONG_WIDTH-1 downto 0);
|
||||||
|
signal feedback_seq_len_s, feedback_seq_addr_s : std_logic_vector(F_SEQ_ADDR_WIDTH-1 downto 0);
|
||||||
|
signal feedback_seq_ready_s, feedback_seq_ren_s, feedback_seq_wen_s, feedback_seq_valid_s, feedback_seq_ack_s : std_logic;
|
||||||
|
signal feedback_seq_r_s, feedback_seq_w_s : std_logic_vector(CDR_LONG_WIDTH-1 downto 0);
|
||||||
|
-- ######GENERATED END######
|
||||||
|
begin
|
||||||
|
|
||||||
|
ros_time_converter_inst : entity work.ros_time_converter(arch)
|
||||||
|
port map (
|
||||||
|
clk => clk,
|
||||||
|
reset => reset,
|
||||||
|
time_in => time,
|
||||||
|
time_out => ros_time
|
||||||
|
);
|
||||||
|
|
||||||
|
rtps_handler_inst : entity work.rtps_handler(arch)
|
||||||
|
port map (
|
||||||
|
-- SYSTEM
|
||||||
|
clk => clk,
|
||||||
|
reset => reset,
|
||||||
|
-- INPUT
|
||||||
|
empty => empty,
|
||||||
|
rd => read,
|
||||||
|
data_in => data_in,
|
||||||
|
-- TO DISCOVERY MODULE
|
||||||
|
full_dm => full_fidm_rh,
|
||||||
|
wr_dm => write_rh_fidm,
|
||||||
|
data_out_dm => data_rh_fidm(WORD_WIDTH-1 downto 0),
|
||||||
|
last_word_out_dm => data_rh_fidm(WORD_WIDTH),
|
||||||
|
-- TO USER ENDPOINTS
|
||||||
|
full_rtps => full_fire_rh,
|
||||||
|
wr_rtps => write_rh_fire,
|
||||||
|
data_out_rtps => data_rh_fire(WORD_WIDTH-1 downto 0),
|
||||||
|
last_word_out_rtps => data_rh_fire(WORD_WIDTH)
|
||||||
|
);
|
||||||
|
|
||||||
|
|
||||||
|
fifo_in_dm_inst : configuration work.FWFT_FIFO_cfg
|
||||||
|
generic map (
|
||||||
|
FIFO_DEPTH => 2,
|
||||||
|
DATA_WIDTH => WORD_WIDTH+1
|
||||||
|
)
|
||||||
|
port map (
|
||||||
|
-- SYSTEM
|
||||||
|
reset => reset,
|
||||||
|
clk => clk,
|
||||||
|
-- INPUT
|
||||||
|
full => full_fidm_rh,
|
||||||
|
write => write_rh_fidm,
|
||||||
|
data_in => data_rh_fidm,
|
||||||
|
-- OUTPUT
|
||||||
|
empty => empty_fidm_dm,
|
||||||
|
read => read_dm_fidm,
|
||||||
|
data_out => data_fidm_dm,
|
||||||
|
-- MISC
|
||||||
|
free => open
|
||||||
|
);
|
||||||
|
|
||||||
|
|
||||||
|
fifo_in_re_gen : for i in 0 to NUM_ENDPOINTS-1 generate
|
||||||
|
fifo_in_re_inst : configuration work.FWFT_FIFO_cfg
|
||||||
|
generic map (
|
||||||
|
FIFO_DEPTH => 2,
|
||||||
|
DATA_WIDTH => WORD_WIDTH+1
|
||||||
|
)
|
||||||
|
port map (
|
||||||
|
-- SYSTEM
|
||||||
|
reset => reset,
|
||||||
|
clk => clk,
|
||||||
|
-- INPUT
|
||||||
|
full => full_fire_rh(i),
|
||||||
|
write => write_rh_fire(i),
|
||||||
|
data_in => data_rh_fire, -- Multicast
|
||||||
|
-- OUTPUT
|
||||||
|
empty => empty_fire_re(i),
|
||||||
|
read => read_re_fire(i),
|
||||||
|
data_out => data_fire_re(i),
|
||||||
|
-- MISC
|
||||||
|
free => open
|
||||||
|
);
|
||||||
|
end generate;
|
||||||
|
|
||||||
|
|
||||||
|
rtps_discovery_module_inst : entity work.rtps_discovery_module(arch)
|
||||||
|
generic map (
|
||||||
|
MAX_REMOTE_PARTICIPANTS => MAX_REMOTE_PARTICIPANTS
|
||||||
|
)
|
||||||
|
port map (
|
||||||
|
clk => clk,
|
||||||
|
reset => reset,
|
||||||
|
time => time,
|
||||||
|
-- FROM RTPS HANDLER
|
||||||
|
empty => empty_fidm_dm,
|
||||||
|
rd => read_dm_fidm,
|
||||||
|
data_in => data_fidm_dm(WORD_WIDTH-1 downto 0),
|
||||||
|
last_word_in => data_fidm_dm(WORD_WIDTH),
|
||||||
|
-- FROM RTPS ENDPOINTS
|
||||||
|
alive => alive_re_dm,
|
||||||
|
-- TO RTPS ENDPOINTS
|
||||||
|
full_rtps => full_fdmre_re,
|
||||||
|
wr_rtps => write_dm_fdmre,
|
||||||
|
data_out_rtps => data_dm_fdmre(WORD_WIDTH-1 downto 0),
|
||||||
|
last_word_out_rtps => data_dm_fdmre(WORD_WIDTH),
|
||||||
|
-- TO RTPS OUT
|
||||||
|
full_ro => full_firo_dm,
|
||||||
|
wr_ro => write_dm_firo,
|
||||||
|
data_out_ro => data_dm_firo(WORD_WIDTH-1 downto 0),
|
||||||
|
last_word_out_ro => data_dm_firo(WORD_WIDTH)
|
||||||
|
);
|
||||||
|
|
||||||
|
|
||||||
|
fifo_dm_re_gen : for i in 0 to NUM_ENDPOINTS-1 generate
|
||||||
|
fifo_dm_re_inst : configuration work.FWFT_FIFO_cfg
|
||||||
|
generic map (
|
||||||
|
FIFO_DEPTH => 2,
|
||||||
|
DATA_WIDTH => WORD_WIDTH+1
|
||||||
|
)
|
||||||
|
port map (
|
||||||
|
-- SYSTEM
|
||||||
|
reset => reset,
|
||||||
|
clk => clk,
|
||||||
|
-- INPUT
|
||||||
|
full => full_fdmre_re(i),
|
||||||
|
write => write_dm_fdmre(i),
|
||||||
|
data_in => data_dm_fdmre, -- Multicast
|
||||||
|
-- OUTPUT
|
||||||
|
empty => empty_fdmre_re(i),
|
||||||
|
read => read_re_fdmre(i),
|
||||||
|
data_out => data_fdmre_re(i),
|
||||||
|
-- MISC
|
||||||
|
free => open
|
||||||
|
);
|
||||||
|
end generate;
|
||||||
|
|
||||||
|
|
||||||
|
rtps_endpoint_gen : for i in 0 to NUM_ENDPOINTS-1 generate
|
||||||
|
rtps_endpoint_if : if (i < NUM_READERS) generate
|
||||||
|
rtps_reader_inst : entity work.rtps_reader(arch)
|
||||||
|
generic map (
|
||||||
|
ENTITYID => ENTITYID(i),
|
||||||
|
RELIABILITY_QOS => ENDPOINT_CONFIG(i).RELIABILITY_QOS,
|
||||||
|
LIVELINESS_QOS => ENDPOINT_CONFIG(i).LIVELINESS_QOS,
|
||||||
|
DURABILITY_QOS => ENDPOINT_CONFIG(i).DURABILITY_QOS,
|
||||||
|
HEARTBEAT_RESPONSE_DELAY => ENDPOINT_CONFIG(i).HEARTBEAT_RESPONSE_DELAY,
|
||||||
|
HEARTBEAT_SUPPRESSION_DELAY => ENDPOINT_CONFIG(i).HEARTBEAT_SUPPRESSION_DELAY,
|
||||||
|
LEASE_DURATION => ENDPOINT_CONFIG(i).LEASE_DURATION,
|
||||||
|
WITH_KEY => ENDPOINT_CONFIG(i).WITH_KEY,
|
||||||
|
MAX_REMOTE_ENDPOINTS => MAX_REMOTE_ENDPOINTS
|
||||||
|
)
|
||||||
|
port map (
|
||||||
|
-- SYSTEM
|
||||||
|
clk => clk,
|
||||||
|
reset => reset,
|
||||||
|
time => time,
|
||||||
|
-- FROM RTPS_HANDLER (USER TRAFFIC)
|
||||||
|
empty_user => empty_fire_re(i),
|
||||||
|
rd_user => read_re_fire(i),
|
||||||
|
data_in_user => data_fire_re(i)(WORD_WIDTH-1 downto 0),
|
||||||
|
last_word_in_user => data_fire_re(i)(WORD_WIDTH),
|
||||||
|
-- FROM DISCOVERY MODULE (META TRAFFIC)
|
||||||
|
empty_meta => empty_fdmre_re(i),
|
||||||
|
rd_meta => read_re_fdmre(i),
|
||||||
|
data_in_meta => data_fdmre_re(i)(WORD_WIDTH-1 downto 0),
|
||||||
|
last_word_in_meta => data_fdmre_re(i)(WORD_WIDTH),
|
||||||
|
-- RTPS OUTPUT
|
||||||
|
full_ro => full_firo_re(i),
|
||||||
|
wr_ro => write_re_firo(i),
|
||||||
|
data_out_ro => data_re_firo(i)(WORD_WIDTH-1 downto 0),
|
||||||
|
last_word_out_ro => data_re_firo(i)(WORD_WIDTH),
|
||||||
|
-- TO HISTORY CACHE
|
||||||
|
start_hc => start_rr_dr(i),
|
||||||
|
opcode_hc => opcode_rr_dr(i),
|
||||||
|
ack_hc => ack_dr_rr(i),
|
||||||
|
done_hc => done_dr_rr(i),
|
||||||
|
ret_hc => ret_dr_rr(i),
|
||||||
|
valid_out_hc => valid_rr_dr(i),
|
||||||
|
ready_out_hc => ready_dr_rr(i),
|
||||||
|
data_out_hc => data_rr_dr(i)(WORD_WIDTH-1 downto 0),
|
||||||
|
last_word_out_hc => data_rr_dr(i)(WORD_WIDTH)
|
||||||
|
);
|
||||||
|
|
||||||
|
-- Set Alive Signals of Readers to Zero
|
||||||
|
alive_re_dm(i) <= ('0');
|
||||||
|
else generate
|
||||||
|
rtps_writer_inst : entity work.rtps_writer(arch)
|
||||||
|
generic map (
|
||||||
|
RELIABILITY_QOS => ENDPOINT_CONFIG(i).RELIABILITY_QOS,
|
||||||
|
LIVELINESS_QOS => ENDPOINT_CONFIG(i).LIVELINESS_QOS,
|
||||||
|
DURABILITY_QOS => ENDPOINT_CONFIG(i).DURABILITY_QOS,
|
||||||
|
DESTINATION_ORDER_QOS => ENDPOINT_CONFIG(i).DESTINATION_ORDER_QOS,
|
||||||
|
ACKNACK_RESPONSE_DELAY => ENDPOINT_CONFIG(i).ACKNACK_RESPONSE_DELAY,
|
||||||
|
ACKNACK_SUPPRESSION_DELAY => ENDPOINT_CONFIG(i).ACKNACK_SUPPRESSION_DELAY,
|
||||||
|
LEASE_DURATION => ENDPOINT_CONFIG(i).LEASE_DURATION,
|
||||||
|
HEARTBEAT_PERIOD => ENDPOINT_CONFIG(i).HEARTBEAT_PERIOD,
|
||||||
|
ENTITYID => ENTITYID(i),
|
||||||
|
WITH_KEY => ENDPOINT_CONFIG(i).WITH_KEY,
|
||||||
|
PUSH_MODE => ENDPOINT_CONFIG(i).PUSH_MODE,
|
||||||
|
INLINE_QOS => gen_inline_qos(i),
|
||||||
|
MAX_REMOTE_ENDPOINTS => MAX_REMOTE_ENDPOINTS
|
||||||
|
)
|
||||||
|
port map (
|
||||||
|
-- SYSTEM
|
||||||
|
clk => clk,
|
||||||
|
reset => reset,
|
||||||
|
time => time,
|
||||||
|
-- FROM RTPS_HANDLER (USER TRAFFIC)
|
||||||
|
empty_user => empty_fire_re(i),
|
||||||
|
rd_user => read_re_fire(i),
|
||||||
|
data_in_user => data_fire_re(i)(WORD_WIDTH-1 downto 0),
|
||||||
|
last_word_in_user => data_fire_re(i)(WORD_WIDTH),
|
||||||
|
-- FROM DISCOVERY MODULE (META TRAFFIC)
|
||||||
|
empty_meta => empty_fdmre_re(i),
|
||||||
|
rd_meta => read_re_fdmre(i),
|
||||||
|
data_in_meta => data_fdmre_re(i)(WORD_WIDTH-1 downto 0),
|
||||||
|
last_word_in_meta => data_fdmre_re(i)(WORD_WIDTH),
|
||||||
|
-- TO DISCOVERY MODULE (META TRAFFIC)
|
||||||
|
alive_sig => alive_re_dm(i),
|
||||||
|
-- RTPS OUTPUT
|
||||||
|
full_ro => full_firo_re(i),
|
||||||
|
wr_ro => write_re_firo(i),
|
||||||
|
data_out_ro => data_re_firo(i)(WORD_WIDTH-1 downto 0),
|
||||||
|
last_word_out_ro => data_re_firo(i)(WORD_WIDTH),
|
||||||
|
-- FROM HC
|
||||||
|
liveliness_assertion => liveliness_assertion_dw_rw(i-NUM_READERS),
|
||||||
|
data_available => data_available_dw_rw(i-NUM_READERS),
|
||||||
|
start_hc => start_rw_dw(i-NUM_READERS),
|
||||||
|
opcode_hc => opcode_rw_dw(i-NUM_READERS),
|
||||||
|
ack_hc => ack_dw_rw(i-NUM_READERS),
|
||||||
|
seq_nr_hc => seq_nr_rw_dw(i-NUM_READERS),
|
||||||
|
done_hc => done_rw_dw(i-NUM_READERS),
|
||||||
|
ret_hc => ret_dw_rw(i-NUM_READERS),
|
||||||
|
get_data_hc => get_data_rw_dw(i-NUM_READERS),
|
||||||
|
valid_in_hc => valid_dw_rw(i-NUM_READERS),
|
||||||
|
ready_in_hc => ready_rw_dw(i-NUM_READERS),
|
||||||
|
data_in_hc => data_dw_rw(i-NUM_READERS)(WORD_WIDTH-1 downto 0),
|
||||||
|
last_word_in_hc => data_dw_rw(i-NUM_READERS)(WORD_WIDTH),
|
||||||
|
cc_instance_handle => cc_instance_handle_dw_rw(i-NUM_READERS),
|
||||||
|
cc_kind => cc_kind_dw_rw(i-NUM_READERS),
|
||||||
|
cc_source_timestamp => cc_source_timestamp_dw_rw(i-NUM_READERS),
|
||||||
|
cc_seq_nr => cc_seq_nr_dw_rw(i-NUM_READERS)
|
||||||
|
);
|
||||||
|
end generate;
|
||||||
|
end generate;
|
||||||
|
|
||||||
|
|
||||||
|
dds_endpoint_gen : for i in 0 to NUM_ENDPOINTS-2 generate
|
||||||
|
dds_endpoint_if : if (i < NUM_READERS) generate
|
||||||
|
dds_reader_inst : entity work.dds_reader(arch)
|
||||||
|
generic map (
|
||||||
|
TIME_BASED_FILTER_QOS => ENDPOINT_CONFIG(i).TIME_BASED_FILTER_QOS,
|
||||||
|
DEADLINE_QOS => ENDPOINT_CONFIG(i).DEADLINE_QOS,
|
||||||
|
MAX_INSTANCES => ENDPOINT_CONFIG(i).MAX_INSTANCES,
|
||||||
|
MAX_SAMPLES_PER_INSTANCE => ENDPOINT_CONFIG(i).MAX_SAMPLES_PER_INSTANCE,
|
||||||
|
MAX_SAMPLES => ENDPOINT_CONFIG(i).MAX_SAMPLES,
|
||||||
|
HISTORY_QOS => ENDPOINT_CONFIG(i).HISTORY_QOS,
|
||||||
|
RELIABILITY_QOS => ENDPOINT_CONFIG(i).RELIABILITY_QOS,
|
||||||
|
PRESENTATION_QOS => ENDPOINT_CONFIG(i).PRESENTATION_QOS,
|
||||||
|
DESTINATION_ORDER_QOS => ENDPOINT_CONFIG(i).DESTINATION_ORDER_QOS,
|
||||||
|
COHERENT_ACCESS => ENDPOINT_CONFIG(i).COHERENT_ACCESS,
|
||||||
|
ORDERED_ACCESS => ENDPOINT_CONFIG(i).ORDERED_ACCESS,
|
||||||
|
WITH_KEY => ENDPOINT_CONFIG(i).WITH_KEY,
|
||||||
|
PAYLOAD_FRAME_SIZE => ENDPOINT_CONFIG(i).MAX_PAYLOAD_SIZE,
|
||||||
|
MAX_REMOTE_ENDPOINTS => MAX_REMOTE_ENDPOINTS
|
||||||
|
)
|
||||||
|
port map (
|
||||||
|
-- SYSTEM
|
||||||
|
clk => clk,
|
||||||
|
reset => reset,
|
||||||
|
time => time,
|
||||||
|
-- FROM RTPS ENDPOINT
|
||||||
|
start_rtps => start_rr_dr(i),
|
||||||
|
opcode_rtps => opcode_rr_dr(i),
|
||||||
|
ack_rtps => ack_dr_rr(i),
|
||||||
|
done_rtps => done_dr_rr(i),
|
||||||
|
ret_rtps => ret_dr_rr(i),
|
||||||
|
valid_in_rtps => valid_rr_dr(i),
|
||||||
|
ready_in_rtps => ready_dr_rr(i),
|
||||||
|
data_in_rtps => data_rr_dr(i)(WORD_WIDTH-1 downto 0),
|
||||||
|
last_word_in_rtps => data_rr_dr(i)(WORD_WIDTH),
|
||||||
|
-- TO USER ENTITY
|
||||||
|
start_dds => start_ri_dr(i),
|
||||||
|
ack_dds => ack_dr_ri(i),
|
||||||
|
opcode_dds => opcode_ri_dr(i),
|
||||||
|
instance_state_dds => instance_state_ri_dr(i),
|
||||||
|
view_state_dds => view_state_ri_dr(i),
|
||||||
|
sample_state_dds => sample_state_ri_dr(i),
|
||||||
|
instance_handle_dds => instance_handle_ri_dr(i),
|
||||||
|
max_samples_dds => max_samples_ri_dr(i),
|
||||||
|
get_data_dds => get_data_ri_dr(i),
|
||||||
|
done_dds => done_dr_ri(i),
|
||||||
|
return_code_dds => return_code_dr_ri(i),
|
||||||
|
valid_out_dds => valid_dr_ri(i),
|
||||||
|
ready_out_dds => ready_ri_dr(i),
|
||||||
|
data_out_dds => data_dr_ri(i)(WORD_WIDTH-1 downto 0),
|
||||||
|
last_word_out_dds => data_dr_ri(i)(WORD_WIDTH),
|
||||||
|
sample_info => sample_info_dr_ri(i),
|
||||||
|
sample_info_valid => sample_info_valid_dr_ri(i),
|
||||||
|
sample_info_ack => sample_info_ack_ri_dr(i),
|
||||||
|
eoc => eoc_dr_ri(i),
|
||||||
|
-- Communication Status
|
||||||
|
status => status_dr_ri(i)
|
||||||
|
);
|
||||||
|
else generate
|
||||||
|
dds_writer_inst : entity work.dds_writer(arch)
|
||||||
|
generic map (
|
||||||
|
HISTORY_QOS => ENDPOINT_CONFIG(i).HISTORY_QOS,
|
||||||
|
DEADLINE_QOS => ENDPOINT_CONFIG(i).DEADLINE_QOS,
|
||||||
|
LIFESPAN_QOS => ENDPOINT_CONFIG(i).LIFESPAN_QOS,
|
||||||
|
LEASE_DURATION => ENDPOINT_CONFIG(i).LEASE_DURATION,
|
||||||
|
WITH_KEY => ENDPOINT_CONFIG(i).WITH_KEY,
|
||||||
|
MAX_SAMPLES => ENDPOINT_CONFIG(i).MAX_SAMPLES,
|
||||||
|
MAX_INSTANCES => ENDPOINT_CONFIG(i).MAX_INSTANCES,
|
||||||
|
MAX_SAMPLES_PER_INSTANCE => ENDPOINT_CONFIG(i).MAX_SAMPLES_PER_INSTANCE,
|
||||||
|
PAYLOAD_FRAME_SIZE => ENDPOINT_CONFIG(i).MAX_PAYLOAD_SIZE
|
||||||
|
)
|
||||||
|
port map (
|
||||||
|
-- SYSTEM
|
||||||
|
clk => clk,
|
||||||
|
reset => reset,
|
||||||
|
time => time,
|
||||||
|
-- TO/FROM RTPS ENDPOINT
|
||||||
|
start_rtps => start_rw_dw(i-NUM_READERS),
|
||||||
|
opcode_rtps => opcode_rw_dw(i-NUM_READERS),
|
||||||
|
ack_rtps => ack_dw_rw(i-NUM_READERS),
|
||||||
|
done_rtps => done_rw_dw(i-NUM_READERS),
|
||||||
|
ret_rtps => ret_dw_rw(i-NUM_READERS),
|
||||||
|
seq_nr_rtps => seq_nr_rw_dw(i-NUM_READERS),
|
||||||
|
get_data_rtps => get_data_rw_dw(i-NUM_READERS),
|
||||||
|
valid_out_rtps => valid_dw_rw(i-NUM_READERS),
|
||||||
|
ready_out_rtps => ready_rw_dw(i-NUM_READERS),
|
||||||
|
data_out_rtps => data_dw_rw(i-NUM_READERS)(WORD_WIDTH-1 downto 0),
|
||||||
|
last_word_out_rtps => data_dw_rw(i-NUM_READERS)(WORD_WIDTH),
|
||||||
|
liveliness_assertion => liveliness_assertion_dw_rw(i-NUM_READERS),
|
||||||
|
data_available => data_available_dw_rw(i-NUM_READERS),
|
||||||
|
-- Cache Change
|
||||||
|
cc_instance_handle => cc_instance_handle_dw_rw(i-NUM_READERS),
|
||||||
|
cc_kind => cc_kind_dw_rw(i-NUM_READERS),
|
||||||
|
cc_source_timestamp => cc_source_timestamp_dw_rw(i-NUM_READERS),
|
||||||
|
cc_seq_nr => cc_seq_nr_dw_rw(i-NUM_READERS),
|
||||||
|
-- TO/FROM USER ENTITY
|
||||||
|
start_dds => start_wi_dw(i-NUM_READERS),
|
||||||
|
ack_dds => ack_dw_wi(i-NUM_READERS),
|
||||||
|
opcode_dds => opcode_wi_dw(i-NUM_READERS),
|
||||||
|
instance_handle_in_dds => instance_handle_wi_dw(i-NUM_READERS),
|
||||||
|
source_ts_dds => source_ts_wi_dw(i-NUM_READERS),
|
||||||
|
max_wait_dds => max_wait_wi_dw(i-NUM_READERS),
|
||||||
|
done_dds => done_dw_wi(i-NUM_READERS),
|
||||||
|
return_code_dds => return_code_dw_wi(i-NUM_READERS),
|
||||||
|
instance_handle_out_dds => instance_handle_dw_wi(i-NUM_READERS),
|
||||||
|
valid_in_dds => valid_wi_dw(i-NUM_READERS),
|
||||||
|
ready_in_dds => ready_dw_wi(i-NUM_READERS),
|
||||||
|
data_in_dds => data_wi_dw(i-NUM_READERS)(WORD_WIDTH-1 downto 0),
|
||||||
|
last_word_in_dds => data_wi_dw(i-NUM_READERS)(WORD_WIDTH),
|
||||||
|
valid_out_dds => valid_dw_wi(i-NUM_READERS),
|
||||||
|
ready_out_dds => ready_wi_dw(i-NUM_READERS),
|
||||||
|
data_out_dds => data_dw_wi(i-NUM_READERS)(WORD_WIDTH-1 downto 0),
|
||||||
|
last_word_out_dds => data_dw_wi(i-NUM_READERS)(WORD_WIDTH),
|
||||||
|
-- Communication Status
|
||||||
|
status => status_dw_wi(i-NUM_READERS)
|
||||||
|
);
|
||||||
|
end generate;
|
||||||
|
end generate;
|
||||||
|
|
||||||
|
ros_discovery_writer_inst : entity work.ros_static_discovery_writer(arch)
|
||||||
|
port map (
|
||||||
|
-- SYSTEM
|
||||||
|
clk => clk,
|
||||||
|
reset => reset,
|
||||||
|
-- TO/FROM RTPS ENDPOINT
|
||||||
|
start => start_rw_dw(NUM_WRITERS-1),
|
||||||
|
opcode => opcode_rw_dw(NUM_WRITERS-1),
|
||||||
|
ack => ack_dw_rw(NUM_WRITERS-1),
|
||||||
|
done => done_rw_dw(NUM_WRITERS-1),
|
||||||
|
ret => ret_dw_rw(NUM_WRITERS-1),
|
||||||
|
seq_nr => seq_nr_rw_dw(NUM_WRITERS-1),
|
||||||
|
get_data => get_data_rw_dw(NUM_WRITERS-1),
|
||||||
|
valid_out => valid_dw_rw(NUM_WRITERS-1),
|
||||||
|
ready_out => ready_rw_dw(NUM_WRITERS-1),
|
||||||
|
data_out => data_dw_rw(NUM_WRITERS-1)(WORD_WIDTH-1 downto 0),
|
||||||
|
last_word_out => data_dw_rw(NUM_WRITERS-1)(WORD_WIDTH),
|
||||||
|
liveliness_assertion => liveliness_assertion_dw_rw(NUM_WRITERS-1),
|
||||||
|
data_available => data_available_dw_rw(NUM_WRITERS-1),
|
||||||
|
-- Cache Change
|
||||||
|
cc_instance_handle => cc_instance_handle_dw_rw(NUM_WRITERS-1),
|
||||||
|
cc_kind => cc_kind_dw_rw(NUM_WRITERS-1),
|
||||||
|
cc_source_timestamp => cc_source_timestamp_dw_rw(NUM_WRITERS-1),
|
||||||
|
cc_seq_nr => cc_seq_nr_dw_rw(NUM_WRITERS-1)
|
||||||
|
);
|
||||||
|
|
||||||
|
|
||||||
|
fifo_in_ro_gen : for i in 0 to NUM_ENDPOINTS generate
|
||||||
|
fifo_in_ro_if : if (i = NUM_ENDPOINTS) generate
|
||||||
|
fifo_in_ro_inst : configuration work.FWFT_FIFO_cfg
|
||||||
|
generic map (
|
||||||
|
FIFO_DEPTH => 2,
|
||||||
|
DATA_WIDTH => WORD_WIDTH+1
|
||||||
|
)
|
||||||
|
port map (
|
||||||
|
-- SYSTEM
|
||||||
|
reset => reset,
|
||||||
|
clk => clk,
|
||||||
|
-- INPUT
|
||||||
|
full => full_firo_dm,
|
||||||
|
write => write_dm_firo,
|
||||||
|
data_in => data_dm_firo,
|
||||||
|
-- OUTPUT
|
||||||
|
empty => empty_firo_ro(i),
|
||||||
|
read => read_ro_firo(i),
|
||||||
|
data_out(WORD_WIDTH) => last_word_firo_ro(i),
|
||||||
|
data_out(WORD_WIDTH-1 downto 0) => data_firo_ro(i),
|
||||||
|
-- MISC
|
||||||
|
free => open
|
||||||
|
);
|
||||||
|
else generate
|
||||||
|
fifo_in_ro_inst : configuration work.FWFT_FIFO_cfg
|
||||||
|
generic map (
|
||||||
|
FIFO_DEPTH => 2,
|
||||||
|
DATA_WIDTH => WORD_WIDTH+1
|
||||||
|
)
|
||||||
|
port map (
|
||||||
|
-- SYSTEM
|
||||||
|
reset => reset,
|
||||||
|
clk => clk,
|
||||||
|
-- INPUT
|
||||||
|
full => full_firo_re(i),
|
||||||
|
write => write_re_firo(i),
|
||||||
|
data_in => data_re_firo(i),
|
||||||
|
-- OUTPUT
|
||||||
|
empty => empty_firo_ro(i),
|
||||||
|
read => read_ro_firo(i),
|
||||||
|
data_out(WORD_WIDTH) => last_word_firo_ro(i),
|
||||||
|
data_out(WORD_WIDTH-1 downto 0) => data_firo_ro(i),
|
||||||
|
-- MISC
|
||||||
|
free => open
|
||||||
|
);
|
||||||
|
end generate;
|
||||||
|
end generate;
|
||||||
|
|
||||||
|
|
||||||
|
rtps_out_inst : entity work.rtps_out(arch)
|
||||||
|
port map (
|
||||||
|
-- SYSTEM
|
||||||
|
clk => clk,
|
||||||
|
reset => reset,
|
||||||
|
-- INPUT
|
||||||
|
empty => empty_firo_ro,
|
||||||
|
rd => read_ro_firo,
|
||||||
|
data_in => data_firo_ro,
|
||||||
|
last_word_in => last_word_firo_ro,
|
||||||
|
-- OUTPUT
|
||||||
|
full => full,
|
||||||
|
wr => write,
|
||||||
|
data_out => data_out
|
||||||
|
);
|
||||||
|
|
||||||
|
action_if_gen : for i in 0 to NUM_ACTIONS-1 generate
|
||||||
|
--
|
||||||
|
start_ri_dr(i) <= action_if(i).g_start_r;
|
||||||
|
action_if(i).g_ack_r <= ack_dr_ri(i);
|
||||||
|
opcode_ri_dr(i) <= action_if(i).g_opcode_r;
|
||||||
|
instance_state_ri_dr(i) <= action_if(i).g_instance_state_r;
|
||||||
|
view_state_ri_dr(i) <= action_if(i).g_view_state_r;
|
||||||
|
sample_state_ri_dr(i) <= action_if(i).g_sample_state_r;
|
||||||
|
instance_handle_ri_dr(i) <= action_if(i).g_instance_handle_r;
|
||||||
|
max_samples_ri_dr(i) <= action_if(i).g_max_samples_r;
|
||||||
|
get_data_ri_dr(i) <= action_if(i).g_get_data_r;
|
||||||
|
action_if(i).g_done_r <= done_dr_ri(i);
|
||||||
|
action_if(i).g_return_code_r <= return_code_dr_ri(i);
|
||||||
|
action_if(i).g_valid_in_r <= valid_dr_ri(i);
|
||||||
|
ready_ri_dr(i) <= action_if(i).g_ready_in_r;
|
||||||
|
action_if(i).g_data_in_r <= data_dr_ri(i)(WORD_WIDTH-1 downto 0);
|
||||||
|
action_if(i).g_last_word_in_r <= data_dr_ri(i)(WORD_WIDTH);
|
||||||
|
action_if(i).g_sample_info_r <= sample_info_dr_ri(i);
|
||||||
|
action_if(i).g_sample_info_valid_r <= sample_info_valid_dr_ri(i);
|
||||||
|
sample_info_ack_ri_dr(i) <= action_if(i).g_sample_info_ack_r;
|
||||||
|
action_if(i).g_eoc_r <= eoc_dr_ri(i);
|
||||||
|
action_if(i).g_status_r <= status_dr_ri(i);
|
||||||
|
start_wi_dw(i) <= action_if(i).g_start_w;
|
||||||
|
action_if(i).g_ack_w <= ack_dw_wi(i);
|
||||||
|
opcode_wi_dw(i) <= action_if(i).g_opcode_w;
|
||||||
|
action_if(i).g_instance_handle_out_w <= instance_handle_dw_wi(i);
|
||||||
|
source_ts_wi_dw(i) <= action_if(i).g_source_ts_w;
|
||||||
|
max_wait_wi_dw(i) <= action_if(i).g_max_wait_w;
|
||||||
|
action_if(i).g_done_w <= done_dw_wi(i);
|
||||||
|
action_if(i).g_return_code_w <= return_code_dw_wi(i);
|
||||||
|
instance_handle_wi_dw(i) <= action_if(i).g_instance_handle_in_w;
|
||||||
|
valid_wi_dw(i) <= action_if(i).g_valid_out_w;
|
||||||
|
action_if(i).g_ready_out_w <= ready_dw_wi(i);
|
||||||
|
data_wi_dw(i)(WORD_WIDTH-1 downto 0) <= action_if(i).g_data_out_w;
|
||||||
|
data_wi_dw(i)(WORD_WIDTH) <= action_if(i).g_last_word_out_w;
|
||||||
|
action_if(i).g_valid_in_w <= valid_dw_wi(i);
|
||||||
|
ready_wi_dw(i) <= action_if(i).g_ready_in_w;
|
||||||
|
action_if(i).g_data_in_w <= data_dw_wi(i)(WORD_WIDTH-1 downto 0);
|
||||||
|
action_if(i).g_last_word_in_w <= data_dw_wi(i)(WORD_WIDTH);
|
||||||
|
action_if(i).g_status_w <= status_dw_wi(i);
|
||||||
|
--
|
||||||
|
start_ri_dr(i+1) <= action_if(i).r_start_r;
|
||||||
|
action_if(i).r_ack_r <= ack_dr_ri(i+1);
|
||||||
|
opcode_ri_dr(i+1) <= action_if(i).r_opcode_r;
|
||||||
|
instance_state_ri_dr(i+1) <= action_if(i).r_instance_state_r;
|
||||||
|
view_state_ri_dr(i+1) <= action_if(i).r_view_state_r;
|
||||||
|
sample_state_ri_dr(i+1) <= action_if(i).r_sample_state_r;
|
||||||
|
instance_handle_ri_dr(i+1) <= action_if(i).r_instance_handle_r;
|
||||||
|
max_samples_ri_dr(i+1) <= action_if(i).r_max_samples_r;
|
||||||
|
get_data_ri_dr(i+1) <= action_if(i).r_get_data_r;
|
||||||
|
action_if(i).r_done_r <= done_dr_ri(i+1);
|
||||||
|
action_if(i).r_return_code_r <= return_code_dr_ri(i+1);
|
||||||
|
action_if(i).r_valid_in_r <= valid_dr_ri(i+1);
|
||||||
|
ready_ri_dr(i+1) <= action_if(i).r_ready_in_r;
|
||||||
|
action_if(i).r_data_in_r <= data_dr_ri(i+1)(WORD_WIDTH-1 downto 0);
|
||||||
|
action_if(i).r_last_word_in_r <= data_dr_ri(i+1)(WORD_WIDTH);
|
||||||
|
action_if(i).r_sample_info_r <= sample_info_dr_ri(i+1);
|
||||||
|
action_if(i).r_sample_info_valid_r <= sample_info_valid_dr_ri(i+1);
|
||||||
|
sample_info_ack_ri_dr(i+1) <= action_if(i).r_sample_info_ack_r;
|
||||||
|
action_if(i).r_eoc_r <= eoc_dr_ri(i+1);
|
||||||
|
action_if(i).r_status_r <= status_dr_ri(i+1);
|
||||||
|
start_wi_dw(i+1) <= action_if(i).r_start_w;
|
||||||
|
action_if(i).r_ack_w <= ack_dw_wi(i+1);
|
||||||
|
opcode_wi_dw(i+1) <= action_if(i).r_opcode_w;
|
||||||
|
action_if(i).r_instance_handle_out_w <= instance_handle_dw_wi(i+1);
|
||||||
|
source_ts_wi_dw(i+1) <= action_if(i).r_source_ts_w;
|
||||||
|
max_wait_wi_dw(i+1) <= action_if(i).r_max_wait_w;
|
||||||
|
action_if(i).r_done_w <= done_dw_wi(i+1);
|
||||||
|
action_if(i).r_return_code_w <= return_code_dw_wi(i+1);
|
||||||
|
instance_handle_wi_dw(i+1) <= action_if(i).r_instance_handle_in_w;
|
||||||
|
valid_wi_dw(i+1) <= action_if(i).r_valid_out_w;
|
||||||
|
action_if(i).r_ready_out_w <= ready_dw_wi(i+1);
|
||||||
|
data_wi_dw(i+1)(WORD_WIDTH-1 downto 0) <= action_if(i).r_data_out_w;
|
||||||
|
data_wi_dw(i+1)(WORD_WIDTH) <= action_if(i).r_last_word_out_w;
|
||||||
|
action_if(i).r_valid_in_w <= valid_dw_wi(i+1);
|
||||||
|
ready_wi_dw(i+1) <= action_if(i).r_ready_in_w;
|
||||||
|
action_if(i).r_data_in_w <= data_dw_wi(i+1)(WORD_WIDTH-1 downto 0);
|
||||||
|
action_if(i).r_last_word_in_w <= data_dw_wi(i+1)(WORD_WIDTH);
|
||||||
|
action_if(i).r_status_w <= status_dw_wi(i+1);
|
||||||
|
--
|
||||||
|
start_ri_dr(i+2) <= action_if(i).c_start_r;
|
||||||
|
action_if(i).c_ack_r <= ack_dr_ri(i+2);
|
||||||
|
opcode_ri_dr(i+2) <= action_if(i).c_opcode_r;
|
||||||
|
instance_state_ri_dr(i+2) <= action_if(i).c_instance_state_r;
|
||||||
|
view_state_ri_dr(i+2) <= action_if(i).c_view_state_r;
|
||||||
|
sample_state_ri_dr(i+2) <= action_if(i).c_sample_state_r;
|
||||||
|
instance_handle_ri_dr(i+2) <= action_if(i).c_instance_handle_r;
|
||||||
|
max_samples_ri_dr(i+2) <= action_if(i).c_max_samples_r;
|
||||||
|
get_data_ri_dr(i+2) <= action_if(i).c_get_data_r;
|
||||||
|
action_if(i).c_done_r <= done_dr_ri(i+2);
|
||||||
|
action_if(i).c_return_code_r <= return_code_dr_ri(i+2);
|
||||||
|
action_if(i).c_valid_in_r <= valid_dr_ri(i+2);
|
||||||
|
ready_ri_dr(i+2) <= action_if(i).c_ready_in_r;
|
||||||
|
action_if(i).c_data_in_r <= data_dr_ri(i+2)(WORD_WIDTH-1 downto 0);
|
||||||
|
action_if(i).c_last_word_in_r <= data_dr_ri(i+2)(WORD_WIDTH);
|
||||||
|
action_if(i).c_sample_info_r <= sample_info_dr_ri(i+2);
|
||||||
|
action_if(i).c_sample_info_valid_r <= sample_info_valid_dr_ri(i+2);
|
||||||
|
sample_info_ack_ri_dr(i+2) <= action_if(i).c_sample_info_ack_r;
|
||||||
|
action_if(i).c_eoc_r <= eoc_dr_ri(i+2);
|
||||||
|
action_if(i).c_status_r <= status_dr_ri(i+2);
|
||||||
|
start_wi_dw(i+2) <= action_if(i).c_start_w;
|
||||||
|
action_if(i).c_ack_w <= ack_dw_wi(i+2);
|
||||||
|
opcode_wi_dw(i+2) <= action_if(i).c_opcode_w;
|
||||||
|
action_if(i).c_instance_handle_out_w <= instance_handle_dw_wi(i+2);
|
||||||
|
source_ts_wi_dw(i+2) <= action_if(i).c_source_ts_w;
|
||||||
|
max_wait_wi_dw(i+2) <= action_if(i).c_max_wait_w;
|
||||||
|
action_if(i).c_done_w <= done_dw_wi(i+2);
|
||||||
|
action_if(i).c_return_code_w <= return_code_dw_wi(i+2);
|
||||||
|
instance_handle_wi_dw(i+2) <= action_if(i).c_instance_handle_in_w;
|
||||||
|
valid_wi_dw(i+2) <= action_if(i).c_valid_out_w;
|
||||||
|
action_if(i).c_ready_out_w <= ready_dw_wi(i+2);
|
||||||
|
data_wi_dw(i+2)(WORD_WIDTH-1 downto 0) <= action_if(i).c_data_out_w;
|
||||||
|
data_wi_dw(i+2)(WORD_WIDTH) <= action_if(i).c_last_word_out_w;
|
||||||
|
action_if(i).c_valid_in_w <= valid_dw_wi(i+2);
|
||||||
|
ready_wi_dw(i+2) <= action_if(i).c_ready_in_w;
|
||||||
|
action_if(i).c_data_in_w <= data_dw_wi(i+2)(WORD_WIDTH-1 downto 0);
|
||||||
|
action_if(i).c_last_word_in_w <= data_dw_wi(i+2)(WORD_WIDTH);
|
||||||
|
action_if(i).c_status_w <= status_dw_wi(i+2);
|
||||||
|
--
|
||||||
|
end generate;
|
||||||
|
|
||||||
|
-- ######GENERATED START######
|
||||||
|
|
||||||
|
Fibonacci_ros_action_server_inst : entity work.Fibonacci_ros_action_server(arch)
|
||||||
|
generic map (
|
||||||
|
TIMEOUT_DURATION => ROS_DURATION_INFINITE,
|
||||||
|
MAX_GOALS => 1,
|
||||||
|
MAX_RESULT_REQUESTS => 1,
|
||||||
|
ENABLE_FEEDBACK => '1'
|
||||||
|
)
|
||||||
|
port map (
|
||||||
|
clk => clk,
|
||||||
|
reset => reset,
|
||||||
|
time => ros_time,
|
||||||
|
g_start_r => action_if(0).g_start_r,
|
||||||
|
g_ack_r => action_if(0).g_ack_r,
|
||||||
|
g_opcode_r => action_if(0).g_opcode_r,
|
||||||
|
g_instance_state_r => action_if(0).g_instance_state_r,
|
||||||
|
g_view_state_r => action_if(0).g_view_state_r,
|
||||||
|
g_sample_state_r => action_if(0).g_sample_state_r,
|
||||||
|
g_instance_handle_r => action_if(0).g_instance_handle_r,
|
||||||
|
g_max_samples_r => action_if(0).g_max_samples_r,
|
||||||
|
g_get_data_r => action_if(0).g_get_data_r,
|
||||||
|
g_done_r => action_if(0).g_done_r,
|
||||||
|
g_return_code_r => action_if(0).g_return_code_r,
|
||||||
|
g_valid_in_r => action_if(0).g_valid_in_r,
|
||||||
|
g_ready_in_r => action_if(0).g_ready_in_r,
|
||||||
|
g_data_in_r => action_if(0).g_data_in_r,
|
||||||
|
g_last_word_in_r => action_if(0).g_last_word_in_r,
|
||||||
|
g_sample_info_r => action_if(0).g_sample_info_r,
|
||||||
|
g_sample_info_valid_r => action_if(0).g_sample_info_valid_r,
|
||||||
|
g_sample_info_ack_r => action_if(0).g_sample_info_ack_r,
|
||||||
|
g_eoc_r => action_if(0).g_eoc_r,
|
||||||
|
g_status_r => action_if(0).g_status_r,
|
||||||
|
g_start_w => action_if(0).g_start_w,
|
||||||
|
g_ack_w => action_if(0).g_ack_w,
|
||||||
|
g_opcode_w => action_if(0).g_opcode_w,
|
||||||
|
g_instance_handle_out_w => action_if(0).g_instance_handle_out_w,
|
||||||
|
g_source_ts_w => action_if(0).g_source_ts_w,
|
||||||
|
g_max_wait_w => action_if(0).g_max_wait_w,
|
||||||
|
g_done_w => action_if(0).g_done_w,
|
||||||
|
g_return_code_w => action_if(0).g_return_code_w,
|
||||||
|
g_instance_handle_in_w => action_if(0).g_instance_handle_in_w,
|
||||||
|
g_valid_out_w => action_if(0).g_valid_out_w,
|
||||||
|
g_ready_out_w => action_if(0).g_ready_out_w,
|
||||||
|
g_data_out_w => action_if(0).g_data_out_w,
|
||||||
|
g_last_word_out_w => action_if(0).g_last_word_out_w,
|
||||||
|
g_valid_in_w => action_if(0).g_valid_in_w,
|
||||||
|
g_ready_in_w => action_if(0).g_ready_in_w,
|
||||||
|
g_data_in_w => action_if(0).g_data_in_w,
|
||||||
|
g_last_word_in_w => action_if(0).g_last_word_in_w,
|
||||||
|
g_status_w => action_if(0).g_status_w,
|
||||||
|
r_start_r => action_if(0).r_start_r,
|
||||||
|
r_ack_r => action_if(0).r_ack_r,
|
||||||
|
r_opcode_r => action_if(0).r_opcode_r,
|
||||||
|
r_instance_state_r => action_if(0).r_instance_state_r,
|
||||||
|
r_view_state_r => action_if(0).r_view_state_r,
|
||||||
|
r_sample_state_r => action_if(0).r_sample_state_r,
|
||||||
|
r_instance_handle_r => action_if(0).r_instance_handle_r,
|
||||||
|
r_max_samples_r => action_if(0).r_max_samples_r,
|
||||||
|
r_get_data_r => action_if(0).r_get_data_r,
|
||||||
|
r_done_r => action_if(0).r_done_r,
|
||||||
|
r_return_code_r => action_if(0).r_return_code_r,
|
||||||
|
r_valid_in_r => action_if(0).r_valid_in_r,
|
||||||
|
r_ready_in_r => action_if(0).r_ready_in_r,
|
||||||
|
r_data_in_r => action_if(0).r_data_in_r,
|
||||||
|
r_last_word_in_r => action_if(0).r_last_word_in_r,
|
||||||
|
r_sample_info_r => action_if(0).r_sample_info_r,
|
||||||
|
r_sample_info_valid_r => action_if(0).r_sample_info_valid_r,
|
||||||
|
r_sample_info_ack_r => action_if(0).r_sample_info_ack_r,
|
||||||
|
r_eoc_r => action_if(0).r_eoc_r,
|
||||||
|
r_status_r => action_if(0).r_status_r,
|
||||||
|
r_start_w => action_if(0).r_start_w,
|
||||||
|
r_ack_w => action_if(0).r_ack_w,
|
||||||
|
r_opcode_w => action_if(0).r_opcode_w,
|
||||||
|
r_instance_handle_out_w => action_if(0).r_instance_handle_out_w,
|
||||||
|
r_source_ts_w => action_if(0).r_source_ts_w,
|
||||||
|
r_max_wait_w => action_if(0).r_max_wait_w,
|
||||||
|
r_done_w => action_if(0).r_done_w,
|
||||||
|
r_return_code_w => action_if(0).r_return_code_w,
|
||||||
|
r_instance_handle_in_w => action_if(0).r_instance_handle_in_w,
|
||||||
|
r_valid_out_w => action_if(0).r_valid_out_w,
|
||||||
|
r_ready_out_w => action_if(0).r_ready_out_w,
|
||||||
|
r_data_out_w => action_if(0).r_data_out_w,
|
||||||
|
r_last_word_out_w => action_if(0).r_last_word_out_w,
|
||||||
|
r_valid_in_w => action_if(0).r_valid_in_w,
|
||||||
|
r_ready_in_w => action_if(0).r_ready_in_w,
|
||||||
|
r_data_in_w => action_if(0).r_data_in_w,
|
||||||
|
r_last_word_in_w => action_if(0).r_last_word_in_w,
|
||||||
|
r_status_w => action_if(0).r_status_w,
|
||||||
|
c_start_r => action_if(0).c_start_r,
|
||||||
|
c_ack_r => action_if(0).c_ack_r,
|
||||||
|
c_opcode_r => action_if(0).c_opcode_r,
|
||||||
|
c_instance_state_r => action_if(0).c_instance_state_r,
|
||||||
|
c_view_state_r => action_if(0).c_view_state_r,
|
||||||
|
c_sample_state_r => action_if(0).c_sample_state_r,
|
||||||
|
c_instance_handle_r => action_if(0).c_instance_handle_r,
|
||||||
|
c_max_samples_r => action_if(0).c_max_samples_r,
|
||||||
|
c_get_data_r => action_if(0).c_get_data_r,
|
||||||
|
c_done_r => action_if(0).c_done_r,
|
||||||
|
c_return_code_r => action_if(0).c_return_code_r,
|
||||||
|
c_valid_in_r => action_if(0).c_valid_in_r,
|
||||||
|
c_ready_in_r => action_if(0).c_ready_in_r,
|
||||||
|
c_data_in_r => action_if(0).c_data_in_r,
|
||||||
|
c_last_word_in_r => action_if(0).c_last_word_in_r,
|
||||||
|
c_sample_info_r => action_if(0).c_sample_info_r,
|
||||||
|
c_sample_info_valid_r => action_if(0).c_sample_info_valid_r,
|
||||||
|
c_sample_info_ack_r => action_if(0).c_sample_info_ack_r,
|
||||||
|
c_eoc_r => action_if(0).c_eoc_r,
|
||||||
|
c_status_r => action_if(0).c_status_r,
|
||||||
|
c_start_w => action_if(0).c_start_w,
|
||||||
|
c_ack_w => action_if(0).c_ack_w,
|
||||||
|
c_opcode_w => action_if(0).c_opcode_w,
|
||||||
|
c_instance_handle_out_w => action_if(0).c_instance_handle_out_w,
|
||||||
|
c_source_ts_w => action_if(0).c_source_ts_w,
|
||||||
|
c_max_wait_w => action_if(0).c_max_wait_w,
|
||||||
|
c_done_w => action_if(0).c_done_w,
|
||||||
|
c_return_code_w => action_if(0).c_return_code_w,
|
||||||
|
c_instance_handle_in_w => action_if(0).c_instance_handle_in_w,
|
||||||
|
c_valid_out_w => action_if(0).c_valid_out_w,
|
||||||
|
c_ready_out_w => action_if(0).c_ready_out_w,
|
||||||
|
c_data_out_w => action_if(0).c_data_out_w,
|
||||||
|
c_last_word_out_w => action_if(0).c_last_word_out_w,
|
||||||
|
c_valid_in_w => action_if(0).c_valid_in_w,
|
||||||
|
c_ready_in_w => action_if(0).c_ready_in_w,
|
||||||
|
c_data_in_w => action_if(0).c_data_in_w,
|
||||||
|
c_last_word_in_w => action_if(0).c_last_word_in_w,
|
||||||
|
c_status_w => action_if(0).c_status_w,
|
||||||
|
f_start_dds => start_wi_dw(3),
|
||||||
|
f_ack_dds => ack_dw_wi(3),
|
||||||
|
f_opcode_dds => opcode_wi_dw(3),
|
||||||
|
f_instance_handle_out_dds => instance_handle_dw_wi(3),
|
||||||
|
f_source_ts_dds => source_ts_wi_dw(3),
|
||||||
|
f_max_wait_dds => max_wait_wi_dw(3),
|
||||||
|
f_done_dds => done_dw_wi(3),
|
||||||
|
f_return_code_dds => return_code_dw_wi(3),
|
||||||
|
f_instance_handle_in_dds => instance_handle_wi_dw(3),
|
||||||
|
f_valid_out_dds => valid_wi_dw(3),
|
||||||
|
f_ready_out_dds => ready_dw_wi(3),
|
||||||
|
f_data_out_dds => data_wi_dw(3)(WORD_WIDTH-1 downto 0),
|
||||||
|
f_last_word_out_dds => data_wi_dw(3)(WORD_WIDTH),
|
||||||
|
f_valid_in_dds => valid_dw_wi(3),
|
||||||
|
f_ready_in_dds => ready_wi_dw(3),
|
||||||
|
f_data_in_dds => data_dw_wi(3)(WORD_WIDTH-1 downto 0),
|
||||||
|
f_last_word_in_dds => data_dw_wi(3)(WORD_WIDTH),
|
||||||
|
f_status_dds => status_dw_wi(3),
|
||||||
|
s_start_dds => start_wi_dw(3+1),
|
||||||
|
s_ack_dds => ack_dw_wi(3+1),
|
||||||
|
s_opcode_dds => opcode_wi_dw(3+1),
|
||||||
|
s_instance_handle_out_dds => instance_handle_dw_wi(3+1),
|
||||||
|
s_source_ts_dds => source_ts_wi_dw(3+1),
|
||||||
|
s_max_wait_dds => max_wait_wi_dw(3+1),
|
||||||
|
s_done_dds => done_dw_wi(3+1),
|
||||||
|
s_return_code_dds => return_code_dw_wi(3+1),
|
||||||
|
s_instance_handle_in_dds => instance_handle_wi_dw(3+1),
|
||||||
|
s_valid_out_dds => valid_wi_dw(3+1),
|
||||||
|
s_ready_out_dds => ready_dw_wi(3+1),
|
||||||
|
s_data_out_dds => data_wi_dw(3+1)(WORD_WIDTH-1 downto 0),
|
||||||
|
s_last_word_out_dds => data_wi_dw(3+1)(WORD_WIDTH),
|
||||||
|
s_valid_in_dds => valid_dw_wi(3+1),
|
||||||
|
s_ready_in_dds => ready_wi_dw(3+1),
|
||||||
|
s_data_in_dds => data_dw_wi(3+1)(WORD_WIDTH-1 downto 0),
|
||||||
|
s_last_word_in_dds => data_dw_wi(3+1)(WORD_WIDTH),
|
||||||
|
s_status_dds => status_dw_wi(3+1),
|
||||||
|
start => start_s,
|
||||||
|
opcode => opcode_s,
|
||||||
|
ack => ack_s,
|
||||||
|
done => done_s,
|
||||||
|
return_code => return_code_s,
|
||||||
|
goal_handle_in => goal_handle_in_s,
|
||||||
|
goal_handle_out => goal_handle_out_s,
|
||||||
|
goal_state_in => goal_state_in_s,
|
||||||
|
goal_state_out => goal_state_out_s,
|
||||||
|
goal_id => goal_id_s,
|
||||||
|
goal_result_index => goal_result_index_s,
|
||||||
|
goal_stamp => goal_stamp_s,
|
||||||
|
new_goal_request => new_goal_request_s,
|
||||||
|
new_goal_handle => new_goal_handle_s,
|
||||||
|
new_goal_result_index => new_goal_result_index_s,
|
||||||
|
new_goal_order => new_goal_order_s,
|
||||||
|
new_goal_accepted => new_goal_accepted_s,
|
||||||
|
new_goal_response => new_goal_response_s,
|
||||||
|
cancel_request => cancel_request_s,
|
||||||
|
cancel_request_handle => cancel_request_handle_s,
|
||||||
|
cancel_accepted => cancel_accepted_s,
|
||||||
|
cancel_response => cancel_response_s,
|
||||||
|
index_result => index_result_s,
|
||||||
|
index_result_wen => index_result_wen_s,
|
||||||
|
index_result_ready => index_result_ready_s,
|
||||||
|
result_seq_len => result_seq_len_s,
|
||||||
|
result_seq_addr => result_seq_addr_s,
|
||||||
|
result_seq_ready => result_seq_ready_s,
|
||||||
|
result_seq_ren => result_seq_ren_s,
|
||||||
|
result_seq_wen => result_seq_wen_s,
|
||||||
|
result_seq_valid => result_seq_valid_s,
|
||||||
|
result_seq_ack => result_seq_ack_s,
|
||||||
|
result_seq_r => result_seq_r_s,
|
||||||
|
result_seq_w => result_seq_w_s,
|
||||||
|
feedback_seq_len => feedback_seq_len_s,
|
||||||
|
feedback_seq_addr => feedback_seq_addr_s,
|
||||||
|
feedback_seq_ready => feedback_seq_ready_s,
|
||||||
|
feedback_seq_ren => feedback_seq_ren_s,
|
||||||
|
feedback_seq_wen => feedback_seq_wen_s,
|
||||||
|
feedback_seq_valid => feedback_seq_valid_s,
|
||||||
|
feedback_seq_ack => feedback_seq_ack_s,
|
||||||
|
feedback_seq_r => feedback_seq_r_s,
|
||||||
|
feedback_seq_w => feedback_seq_w_s
|
||||||
|
);
|
||||||
|
|
||||||
|
|
||||||
|
Fibonacci_inst : entity work.Fibonacci(arch)
|
||||||
|
port map (
|
||||||
|
clk => clk,
|
||||||
|
reset => reset,
|
||||||
|
time => ros_time,
|
||||||
|
start => start_s,
|
||||||
|
opcode => opcode_s,
|
||||||
|
ack => ack_s,
|
||||||
|
done => done_s,
|
||||||
|
return_code => return_code_s,
|
||||||
|
goal_handle_in => goal_handle_in_s,
|
||||||
|
goal_handle_out => goal_handle_out_s,
|
||||||
|
goal_state_in => goal_state_in_s,
|
||||||
|
goal_state_out => goal_state_out_s,
|
||||||
|
goal_id => goal_id_s,
|
||||||
|
goal_result_index => goal_result_index_s,
|
||||||
|
goal_stamp => goal_stamp_s,
|
||||||
|
new_goal_request => new_goal_request_s,
|
||||||
|
new_goal_handle => new_goal_handle_s,
|
||||||
|
new_goal_result_index => new_goal_result_index_s,
|
||||||
|
new_goal_order => new_goal_order_s,
|
||||||
|
new_goal_accepted => new_goal_accepted_s,
|
||||||
|
new_goal_response => new_goal_response_s,
|
||||||
|
cancel_request => cancel_request_s,
|
||||||
|
cancel_request_handle => cancel_request_handle_s,
|
||||||
|
cancel_accepted => cancel_accepted_s,
|
||||||
|
cancel_response => cancel_response_s,
|
||||||
|
index_result => index_result_s,
|
||||||
|
index_result_wen => index_result_wen_s,
|
||||||
|
index_result_ready => index_result_ready_s,
|
||||||
|
result_seq_len => result_seq_len_s,
|
||||||
|
result_seq_addr => result_seq_addr_s,
|
||||||
|
result_seq_ready => result_seq_ready_s,
|
||||||
|
result_seq_ren => result_seq_ren_s,
|
||||||
|
result_seq_wen => result_seq_wen_s,
|
||||||
|
result_seq_valid => result_seq_valid_s,
|
||||||
|
result_seq_ack => result_seq_ack_s,
|
||||||
|
result_seq_r => result_seq_r_s,
|
||||||
|
result_seq_w => result_seq_w_s,
|
||||||
|
feedback_seq_len => feedback_seq_len_s,
|
||||||
|
feedback_seq_addr => feedback_seq_addr_s,
|
||||||
|
feedback_seq_ready => feedback_seq_ready_s,
|
||||||
|
feedback_seq_ren => feedback_seq_ren_s,
|
||||||
|
feedback_seq_wen => feedback_seq_wen_s,
|
||||||
|
feedback_seq_valid => feedback_seq_valid_s,
|
||||||
|
feedback_seq_ack => feedback_seq_ack_s,
|
||||||
|
feedback_seq_r => feedback_seq_r_s,
|
||||||
|
feedback_seq_w => feedback_seq_w_s
|
||||||
|
);
|
||||||
|
-- ######GENERATED END######
|
||||||
|
|
||||||
|
end architecture;
|
||||||
98
src/ros2/Tests/Level_2/L2_Testbench_ROS_Lib4_config.vhd
Normal file
98
src/ros2/Tests/Level_2/L2_Testbench_ROS_Lib4_config.vhd
Normal file
@ -0,0 +1,98 @@
|
|||||||
|
-- altera vhdl_input_version vhdl_2008
|
||||||
|
-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
|
||||||
|
|
||||||
|
library ieee;
|
||||||
|
use ieee.std_logic_1164.all;
|
||||||
|
use ieee.numeric_std.all;
|
||||||
|
|
||||||
|
use work.rtps_package.all;
|
||||||
|
use work.ros_package.all;
|
||||||
|
use work.Fibonacci_package.all;
|
||||||
|
|
||||||
|
package ros_config is
|
||||||
|
|
||||||
|
-- Period of ros system clock
|
||||||
|
constant ROS_CLOCK_PERIOD : time := 50 ns;
|
||||||
|
-- IPv4 Address of ROS System [Default 192.168.0.131]
|
||||||
|
constant ROS_ADDRESS : std_logic_vector(IPv4_ADDRESS_WIDTH-1 downto 0) := x"C0A80082";
|
||||||
|
-- Random Key used to generate GUIDs
|
||||||
|
constant ROS_RAND_KEY : std_logic_vector(47 downto 0) := x"632E2BD47EEB";
|
||||||
|
|
||||||
|
constant NUM_NODES : natural := 1;
|
||||||
|
|
||||||
|
constant ROS_NODES : ROS_NODE_ARRAY_TYPE(0 to NUM_NODES-1) := (
|
||||||
|
0 => (
|
||||||
|
name => gen_user_string("fibonacci_action_server"),
|
||||||
|
namespace => gen_user_string(""),
|
||||||
|
domain_id => 0,
|
||||||
|
NUM_PUBS => 0,
|
||||||
|
NUM_SUBS => 0,
|
||||||
|
NUM_SERVICES => 0,
|
||||||
|
NUM_ACTIONS => 1
|
||||||
|
)
|
||||||
|
);
|
||||||
|
|
||||||
|
constant NUM_PUBS : natural := get_num_pubs(ROS_NODES);
|
||||||
|
constant NUM_SUBS : natural := get_num_subs(ROS_NODES);
|
||||||
|
constant NUM_SERVICES : natural := get_num_services(ROS_NODES);
|
||||||
|
constant NUM_ACTIONS : natural := get_num_actions(ROS_NODES);
|
||||||
|
|
||||||
|
constant ROS_PUBLICATIONS : ROS_TOPIC_ARRAY_TYPE(0 to NUM_PUBS-1) := (
|
||||||
|
others => (
|
||||||
|
node_id => 0,
|
||||||
|
TOPICNAME => gen_user_string(""),
|
||||||
|
TYPENAME => gen_user_string(""),
|
||||||
|
QOS => ROS_QOS_PROFILE_DEFAULT,
|
||||||
|
MAX_SIZE => 0
|
||||||
|
)
|
||||||
|
);
|
||||||
|
|
||||||
|
constant ROS_SUBSCRIPTIONS : ROS_TOPIC_ARRAY_TYPE(0 to NUM_SUBS-1) := (
|
||||||
|
others => (
|
||||||
|
node_id => 0,
|
||||||
|
TOPICNAME => gen_user_string(""),
|
||||||
|
TYPENAME => gen_user_string(""),
|
||||||
|
QOS => ROS_QOS_PROFILE_DEFAULT,
|
||||||
|
MAX_SIZE => 0
|
||||||
|
)
|
||||||
|
);
|
||||||
|
|
||||||
|
constant ROS_SERVICES : ROS_SERVICE_ARRAY_TYPE(0 to NUM_SERVICES-1) := (
|
||||||
|
others => (
|
||||||
|
node_id => 0,
|
||||||
|
SERVICENAME => gen_user_string(""),
|
||||||
|
RQ_TYPENAME => gen_user_string(""),
|
||||||
|
RR_TYPENAME => gen_user_string(""),
|
||||||
|
QOS => ROS_QOS_PROFILE_TRANSIENT,
|
||||||
|
MAX_RQ_SIZE => 0,
|
||||||
|
MAX_RR_SIZE => 0,
|
||||||
|
is_client => FALSE
|
||||||
|
)
|
||||||
|
);
|
||||||
|
|
||||||
|
constant ROS_ACTIONS : ROS_ACTION_ARRAY_TYPE(0 to NUM_ACTIONS-1) := (
|
||||||
|
0 => (
|
||||||
|
node_id => 0,
|
||||||
|
ACTIONNAME => gen_user_string("fibonacci"),
|
||||||
|
GOAL_RQ_TYPENAME => gen_user_string("action_tutorials_interfaces::action::dds_::Fibonacci_SendGoal_Request_"),
|
||||||
|
GOAL_RR_TYPENAME => gen_user_string("action_tutorials_interfaces::action::dds_::Fibonacci_SendGoal_Response_"),
|
||||||
|
RESULT_RQ_TYPENAME => gen_user_string("action_tutorials_interfaces::action::dds_::Fibonacci_GetResult_Request_"),
|
||||||
|
RESULT_RR_TYPENAME => gen_user_string("action_tutorials_interfaces::action::dds_::Fibonacci_GetResult_Response_"),
|
||||||
|
FEEDBACK_TYPENAME => gen_user_string("action_tutorials_interfaces::action::dds_::Fibonacci_FeedbackMessage_"),
|
||||||
|
GOAL_QOS => ROS_QOS_PROFILE_TRANSIENT,
|
||||||
|
RESULT_QOS => ROS_QOS_PROFILE_TRANSIENT,
|
||||||
|
FEEDBACK_QOS => ROS_QOS_PROFILE_DEFAULT,
|
||||||
|
CANCEL_QOS => ROS_QOS_PROFILE_TRANSIENT,
|
||||||
|
MAX_GOAL_RQ_SIZE => G_RQ_MAX_FIBONACCI_SIZE,
|
||||||
|
MAX_GOAL_RR_SIZE => G_RR_MAX_FIBONACCI_SIZE,
|
||||||
|
MAX_RESULT_RQ_SIZE => R_RQ_MAX_FIBONACCI_SIZE,
|
||||||
|
MAX_RESULT_RR_SIZE => R_RR_MAX_FIBONACCI_SIZE,
|
||||||
|
MAX_FEEDBACK_SIZE => F_MAX_FIBONACCI_SIZE,
|
||||||
|
is_client => FALSE,
|
||||||
|
enable_feedback => TRUE
|
||||||
|
)
|
||||||
|
);
|
||||||
|
|
||||||
|
-- Defines sensible RTPS timings for simulation
|
||||||
|
constant SIMULATION_TIMING : boolean := TRUE;
|
||||||
|
end package;
|
||||||
916
src/ros2/Tests/Level_2/L2_Testbench_ROS_Lib5.vhd
Normal file
916
src/ros2/Tests/Level_2/L2_Testbench_ROS_Lib5.vhd
Normal file
@ -0,0 +1,916 @@
|
|||||||
|
-- altera vhdl_input_version vhdl_2008
|
||||||
|
-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
|
||||||
|
|
||||||
|
library ieee;
|
||||||
|
use ieee.std_logic_1164.all;
|
||||||
|
use ieee.numeric_std.all;
|
||||||
|
|
||||||
|
use work.ros_package.all;
|
||||||
|
use work.ros_config.all;
|
||||||
|
use work.rtps_package.all;
|
||||||
|
use work.user_config.all;
|
||||||
|
use work.rtps_config_package.all;
|
||||||
|
use work.CancelGoal_package;
|
||||||
|
use work.Fibonacci_package.all;
|
||||||
|
|
||||||
|
entity L2_Testbench_ROS_Lib5 is
|
||||||
|
port (
|
||||||
|
-- SYSTEM
|
||||||
|
clk : in std_logic;
|
||||||
|
reset : in std_logic;
|
||||||
|
time : in TIME_TYPE;
|
||||||
|
-- INPUT
|
||||||
|
empty : in std_logic;
|
||||||
|
read : out std_logic;
|
||||||
|
data_in : in std_logic_vector(WORD_WIDTH-1 downto 0);
|
||||||
|
-- OUTPUT
|
||||||
|
full : in std_logic;
|
||||||
|
write : out std_logic;
|
||||||
|
data_out : out std_logic_vector(WORD_WIDTH-1 downto 0);
|
||||||
|
|
||||||
|
-- ACTION CLIENT
|
||||||
|
start_c : in std_logic;
|
||||||
|
opcode_c : in ROS_ACTION_OPCODE_TYPE;
|
||||||
|
ack_c : out std_logic;
|
||||||
|
sequence_id_c : out std_logic_vector(ROS_SEQUENCE_ID_WIDTH-1 downto 0);
|
||||||
|
service_info_c : out SERVICE_INFO_TYPE;
|
||||||
|
data_available_g_c : out std_logic;
|
||||||
|
data_available_r_c : out std_logic;
|
||||||
|
data_available_c_c : out std_logic;
|
||||||
|
data_available_f_c : out std_logic;
|
||||||
|
done_c : out std_logic;
|
||||||
|
return_code_c : out std_logic_vector(ROS_RETCODE_WIDTH-1 downto 0);
|
||||||
|
goal_id_c : in std_logic_vector(UUID_WIDTH-1 downto 0);
|
||||||
|
goal_order_c : in std_logic_vector(CDR_LONG_WIDTH-1 downto 0);
|
||||||
|
goal_accepted_c : out std_logic;
|
||||||
|
goal_stamp_c : out ROS_TIME_TYPE;
|
||||||
|
result_goal_id_c : in std_logic_vector(UUID_WIDTH-1 downto 0);
|
||||||
|
result_status_c : out std_logic_vector(CDR_INT8_WIDTH-1 downto 0);
|
||||||
|
result_seq_len_c : out std_logic_vector(R_RR_SEQ_ADDR_WIDTH-1 downto 0);
|
||||||
|
result_seq_addr_c : in std_logic_vector(R_RR_SEQ_ADDR_WIDTH-1 downto 0);
|
||||||
|
result_seq_ready_c : out std_logic;
|
||||||
|
result_seq_ren_c : in std_logic;
|
||||||
|
result_seq_valid_c : out std_logic;
|
||||||
|
result_seq_ack_c : in std_logic;
|
||||||
|
result_seq_c : out std_logic_vector(CDR_LONG_WIDTH-1 downto 0);
|
||||||
|
cancel_goal_id_c : in std_logic_vector(UUID_WIDTH-1 downto 0);
|
||||||
|
cancel_stamp_c : in ROS_TIME_TYPE;
|
||||||
|
cancel_return_code_c : out std_logic_vector(CDR_INT8_WIDTH-1 downto 0);
|
||||||
|
cancel_goals_canceling_len_c : out std_logic_vector(CancelGoal_package.RR_GOALS_CANCELING_ADDR_WIDTH-1 downto 0);
|
||||||
|
cancel_goals_canceling_addr_c : in std_logic_vector(CancelGoal_package.RR_GOALS_CANCELING_ADDR_WIDTH-1 downto 0);
|
||||||
|
cancel_goals_canceling_ready_c : out std_logic;
|
||||||
|
cancel_goals_canceling_ren_c : in std_logic;
|
||||||
|
cancel_goals_canceling_valid_c : out std_logic;
|
||||||
|
cancel_goals_canceling_ack_c : in std_logic;
|
||||||
|
cancel_goals_canceling_goal_id_c : out std_logic_vector(UUID_WIDTH-1 downto 0);
|
||||||
|
cancel_goals_canceling_stamp_c : out std_logic_vector(ROS_TIME_WIDTH-1 downto 0);
|
||||||
|
feedback_goal_id_c : out std_logic_vector(UUID_WIDTH-1 downto 0);
|
||||||
|
feedback_seq_len_c : out std_logic_vector(F_SEQ_ADDR_WIDTH-1 downto 0);
|
||||||
|
feedback_seq_addr_c : in std_logic_vector(F_SEQ_ADDR_WIDTH-1 downto 0);
|
||||||
|
feedback_seq_ready_c : out std_logic;
|
||||||
|
feedback_seq_ren_c : in std_logic;
|
||||||
|
feedback_seq_valid_c : out std_logic;
|
||||||
|
feedback_seq_ack_c : in std_logic;
|
||||||
|
feedback_seq_c : out std_logic_vector(CDR_LONG_WIDTH-1 downto 0)
|
||||||
|
);
|
||||||
|
end entity;
|
||||||
|
|
||||||
|
architecture arch of L2_Testbench_ROS_Lib5 is
|
||||||
|
|
||||||
|
type EARRAY_DATA_TYPE is array (0 to NUM_ENDPOINTS-1) of std_logic_vector(WORD_WIDTH downto 0);
|
||||||
|
type HISTORY_CACHE_OPCODE_RARRAY_TYPE is array (0 to NUM_READERS-1) of HISTORY_CACHE_OPCODE_TYPE;
|
||||||
|
type HISTORY_CACHE_OPCODE_WARRAY_TYPE is array (0 to NUM_WRITERS-1) of HISTORY_CACHE_OPCODE_TYPE;
|
||||||
|
type HISTORY_CACHE_RESPONSE_RARRAY_TYPE is array (0 to NUM_READERS-1) of HISTORY_CACHE_RESPONSE_TYPE;
|
||||||
|
type HISTORY_CACHE_RESPONSE_WARRAY_TYPE is array (0 to NUM_WRITERS-1) of HISTORY_CACHE_RESPONSE_TYPE;
|
||||||
|
type RARRAY_DATA_TYPE is array (0 to NUM_READERS-1) of std_logic_vector(WORD_WIDTH downto 0);
|
||||||
|
type WARRAY_DATA_TYPE is array (0 to NUM_WRITERS-1) of std_logic_vector(WORD_WIDTH downto 0);
|
||||||
|
type SEQUENCENUMBER_WARRAY_TYPE is array (0 to NUM_WRITERS-1) of SEQUENCENUMBER_TYPE;
|
||||||
|
type INSTANCE_HANDLE_RARRAY_TYPE is array (0 to NUM_READERS-1) of INSTANCE_HANDLE_TYPE;
|
||||||
|
type INSTANCE_HANDLE_WARRAY_TYPE is array (0 to NUM_WRITERS-1) of INSTANCE_HANDLE_TYPE;
|
||||||
|
type CACHE_CHANGE_KIND_WARRAY_TYPE is array (0 to NUM_WRITERS-1) of CACHE_CHANGE_KIND_TYPE;
|
||||||
|
type TIME_WARRAY_TYPE is array (0 to NUM_WRITERS-1) of TIME_TYPE;
|
||||||
|
type DDS_READER_OPCODE_RARRAY_TYPE is array (0 to NUM_READERS-1) of DDS_READER_OPCODE_TYPE;
|
||||||
|
type DDS_WRITER_OPCODE_WARRAY_TYPE is array (0 to NUM_WRITERS-1) of DDS_WRITER_OPCODE_TYPE;
|
||||||
|
type INSTANCE_STATE_RARRAY_TYPE is array (0 to NUM_READERS-1) of std_logic_vector(INSTANCE_STATE_KIND_WIDTH-1 downto 0);
|
||||||
|
type VIEW_STATE_RARRAY_TYPE is array (0 to NUM_READERS-1) of std_logic_vector(VIEW_STATE_KIND_WIDTH-1 downto 0);
|
||||||
|
type SAMPLE_STATE_RARRAY_TYPE is array (0 to NUM_READERS-1) of std_logic_vector(SAMPLE_STATE_KIND_WIDTH-1 downto 0);
|
||||||
|
type MAX_SAMPLES_RARRAY_TYPE is array (0 to NUM_READERS-1) of std_logic_vector(MAX_SAMPLES_WIDTH-1 downto 0);
|
||||||
|
type RETURN_CODE_RARRAY_TYPE is array (0 to NUM_READERS-1) of std_logic_vector(RETURN_CODE_WIDTH-1 downto 0);
|
||||||
|
type RETURN_CODE_WARRAY_TYPE is array (0 to NUM_WRITERS-1) of std_logic_vector(RETURN_CODE_WIDTH-1 downto 0);
|
||||||
|
type STATUS_KIND_RARRAY_TYPE is array (0 to NUM_READERS-1) of std_logic_vector(STATUS_KIND_WIDTH-1 downto 0);
|
||||||
|
type STATUS_KIND_WARRAY_TYPE is array (0 to NUM_WRITERS-1) of std_logic_vector(STATUS_KIND_WIDTH-1 downto 0);
|
||||||
|
type DURATION_WARRAY_TYPE is array (0 to NUM_WRITERS-1) of DURATION_TYPE;
|
||||||
|
type SAMPLE_INFO_RARRAY_TYPE is array (0 to NUM_READERS-1) of SAMPLE_INFO_TYPE;
|
||||||
|
|
||||||
|
signal ros_time : ROS_TIME_TYPE;
|
||||||
|
signal full_fire_rh, write_rh_fire : std_logic_vector(0 to NUM_ENDPOINTS-1);
|
||||||
|
signal data_rh_fire, data_rh_fidm : std_logic_vector(WORD_WIDTH downto 0);
|
||||||
|
signal full_fidm_rh, write_rh_fidm : std_logic;
|
||||||
|
signal read_dm_fidm, empty_fidm_dm : std_logic;
|
||||||
|
signal data_fidm_dm : std_logic_vector(WORD_WIDTH downto 0);
|
||||||
|
signal read_re_fire, empty_fire_re : std_logic_vector(0 to NUM_ENDPOINTS);
|
||||||
|
signal data_fire_re : EARRAY_DATA_TYPE;
|
||||||
|
signal alive_re_dm, full_fdmre_re, write_dm_fdmre : std_logic_vector(0 to NUM_ENDPOINTS-1);
|
||||||
|
signal data_dm_fdmre , data_dm_firo : std_logic_vector(WORD_WIDTH downto 0);
|
||||||
|
signal full_firo_dm, write_dm_firo : std_logic;
|
||||||
|
signal empty_fdmre_re, read_re_fdmre : std_logic_vector(0 to NUM_ENDPOINTS-1);
|
||||||
|
signal data_fdmre_re : EARRAY_DATA_TYPE;
|
||||||
|
signal full_firo_re, write_re_firo : std_logic_vector(0 to NUM_ENDPOINTS-1);
|
||||||
|
signal data_re_firo : EARRAY_DATA_TYPE;
|
||||||
|
signal start_rr_dr, ack_dr_rr, done_dr_rr, valid_rr_dr, ready_dr_rr : std_logic_vector(0 to NUM_READERS-1);
|
||||||
|
signal opcode_rr_dr : HISTORY_CACHE_OPCODE_RARRAY_TYPE;
|
||||||
|
signal ret_dr_rr : HISTORY_CACHE_RESPONSE_RARRAY_TYPE;
|
||||||
|
signal data_rr_dr : RARRAY_DATA_TYPE;
|
||||||
|
signal liveliness_assertion_dw_rw, data_available_dw_rw, start_rw_dw, ack_dw_rw, done_rw_dw, get_data_rw_dw, valid_dw_rw, ready_rw_dw : std_logic_vector(0 to NUM_WRITERS-1);
|
||||||
|
signal opcode_rw_dw : HISTORY_CACHE_OPCODE_WARRAY_TYPE;
|
||||||
|
signal seq_nr_rw_dw, cc_seq_nr_dw_rw : SEQUENCENUMBER_WARRAY_TYPE;
|
||||||
|
signal ret_dw_rw : HISTORY_CACHE_RESPONSE_WARRAY_TYPE;
|
||||||
|
signal data_dw_rw : WARRAY_DATA_TYPE;
|
||||||
|
signal cc_instance_handle_dw_rw : INSTANCE_HANDLE_WARRAY_TYPE;
|
||||||
|
signal cc_kind_dw_rw : CACHE_CHANGE_KIND_WARRAY_TYPE;
|
||||||
|
signal cc_source_timestamp_dw_rw : TIME_WARRAY_TYPE;
|
||||||
|
signal sample_info_dr_ri : SAMPLE_INFO_RARRAY_TYPE;
|
||||||
|
signal start_ri_dr, ack_dr_ri, get_data_ri_dr, done_dr_ri, ready_ri_dr, valid_dr_ri, sample_info_valid_dr_ri, sample_info_ack_ri_dr, eoc_dr_ri : std_logic_vector(0 to NUM_READERS-1);
|
||||||
|
signal opcode_ri_dr : DDS_READER_OPCODE_RARRAY_TYPE;
|
||||||
|
signal instance_state_ri_dr : INSTANCE_STATE_RARRAY_TYPE;
|
||||||
|
signal view_state_ri_dr : VIEW_STATE_RARRAY_TYPE;
|
||||||
|
signal sample_state_ri_dr : SAMPLE_STATE_RARRAY_TYPE;
|
||||||
|
signal instance_handle_ri_dr : INSTANCE_HANDLE_RARRAY_TYPE;
|
||||||
|
signal max_samples_ri_dr : MAX_SAMPLES_RARRAY_TYPE;
|
||||||
|
signal return_code_dr_ri : RETURN_CODE_RARRAY_TYPE;
|
||||||
|
signal data_dr_ri : RARRAY_DATA_TYPE;
|
||||||
|
signal status_dr_ri : STATUS_KIND_RARRAY_TYPE;
|
||||||
|
signal start_wi_dw, ack_dw_wi, done_dw_wi, valid_wi_dw, valid_dw_wi, ready_wi_dw, ready_dw_wi : std_logic_vector(0 to NUM_WRITERS-1);
|
||||||
|
signal opcode_wi_dw : DDS_WRITER_OPCODE_WARRAY_TYPE;
|
||||||
|
signal instance_handle_wi_dw, instance_handle_dw_wi : INSTANCE_HANDLE_WARRAY_TYPE;
|
||||||
|
signal source_ts_wi_dw : TIME_WARRAY_TYPE;
|
||||||
|
signal max_wait_wi_dw : DURATION_WARRAY_TYPE;
|
||||||
|
signal return_code_dw_wi : RETURN_CODE_WARRAY_TYPE;
|
||||||
|
signal data_dw_wi, data_wi_dw : WARRAY_DATA_TYPE;
|
||||||
|
signal status_dw_wi : STATUS_KIND_WARRAY_TYPE;
|
||||||
|
signal empty_firo_ro, read_ro_firo, last_word_firo_ro : std_logic_vector(0 to NUM_ENDPOINTS);
|
||||||
|
signal data_firo_ro : RTPS_OUT_DATA_TYPE;
|
||||||
|
signal action_if : ACTION_INTERFACE_ARRAY_TYPE(0 to NUM_ACTIONS-1);
|
||||||
|
|
||||||
|
begin
|
||||||
|
|
||||||
|
ros_time_converter_inst : entity work.ros_time_converter(arch)
|
||||||
|
port map (
|
||||||
|
clk => clk,
|
||||||
|
reset => reset,
|
||||||
|
time_in => time,
|
||||||
|
time_out => ros_time
|
||||||
|
);
|
||||||
|
|
||||||
|
rtps_handler_inst : entity work.rtps_handler(arch)
|
||||||
|
port map (
|
||||||
|
-- SYSTEM
|
||||||
|
clk => clk,
|
||||||
|
reset => reset,
|
||||||
|
-- INPUT
|
||||||
|
empty => empty,
|
||||||
|
rd => read,
|
||||||
|
data_in => data_in,
|
||||||
|
-- TO DISCOVERY MODULE
|
||||||
|
full_dm => full_fidm_rh,
|
||||||
|
wr_dm => write_rh_fidm,
|
||||||
|
data_out_dm => data_rh_fidm(WORD_WIDTH-1 downto 0),
|
||||||
|
last_word_out_dm => data_rh_fidm(WORD_WIDTH),
|
||||||
|
-- TO USER ENDPOINTS
|
||||||
|
full_rtps => full_fire_rh,
|
||||||
|
wr_rtps => write_rh_fire,
|
||||||
|
data_out_rtps => data_rh_fire(WORD_WIDTH-1 downto 0),
|
||||||
|
last_word_out_rtps => data_rh_fire(WORD_WIDTH)
|
||||||
|
);
|
||||||
|
|
||||||
|
|
||||||
|
fifo_in_dm_inst : configuration work.FWFT_FIFO_cfg
|
||||||
|
generic map (
|
||||||
|
FIFO_DEPTH => 2,
|
||||||
|
DATA_WIDTH => WORD_WIDTH+1
|
||||||
|
)
|
||||||
|
port map (
|
||||||
|
-- SYSTEM
|
||||||
|
reset => reset,
|
||||||
|
clk => clk,
|
||||||
|
-- INPUT
|
||||||
|
full => full_fidm_rh,
|
||||||
|
write => write_rh_fidm,
|
||||||
|
data_in => data_rh_fidm,
|
||||||
|
-- OUTPUT
|
||||||
|
empty => empty_fidm_dm,
|
||||||
|
read => read_dm_fidm,
|
||||||
|
data_out => data_fidm_dm,
|
||||||
|
-- MISC
|
||||||
|
free => open
|
||||||
|
);
|
||||||
|
|
||||||
|
|
||||||
|
fifo_in_re_gen : for i in 0 to NUM_ENDPOINTS-1 generate
|
||||||
|
fifo_in_re_inst : configuration work.FWFT_FIFO_cfg
|
||||||
|
generic map (
|
||||||
|
FIFO_DEPTH => 2,
|
||||||
|
DATA_WIDTH => WORD_WIDTH+1
|
||||||
|
)
|
||||||
|
port map (
|
||||||
|
-- SYSTEM
|
||||||
|
reset => reset,
|
||||||
|
clk => clk,
|
||||||
|
-- INPUT
|
||||||
|
full => full_fire_rh(i),
|
||||||
|
write => write_rh_fire(i),
|
||||||
|
data_in => data_rh_fire, -- Multicast
|
||||||
|
-- OUTPUT
|
||||||
|
empty => empty_fire_re(i),
|
||||||
|
read => read_re_fire(i),
|
||||||
|
data_out => data_fire_re(i),
|
||||||
|
-- MISC
|
||||||
|
free => open
|
||||||
|
);
|
||||||
|
end generate;
|
||||||
|
|
||||||
|
|
||||||
|
rtps_discovery_module_inst : entity work.rtps_discovery_module(arch)
|
||||||
|
generic map (
|
||||||
|
MAX_REMOTE_PARTICIPANTS => MAX_REMOTE_PARTICIPANTS
|
||||||
|
)
|
||||||
|
port map (
|
||||||
|
clk => clk,
|
||||||
|
reset => reset,
|
||||||
|
time => time,
|
||||||
|
-- FROM RTPS HANDLER
|
||||||
|
empty => empty_fidm_dm,
|
||||||
|
rd => read_dm_fidm,
|
||||||
|
data_in => data_fidm_dm(WORD_WIDTH-1 downto 0),
|
||||||
|
last_word_in => data_fidm_dm(WORD_WIDTH),
|
||||||
|
-- FROM RTPS ENDPOINTS
|
||||||
|
alive => alive_re_dm,
|
||||||
|
-- TO RTPS ENDPOINTS
|
||||||
|
full_rtps => full_fdmre_re,
|
||||||
|
wr_rtps => write_dm_fdmre,
|
||||||
|
data_out_rtps => data_dm_fdmre(WORD_WIDTH-1 downto 0),
|
||||||
|
last_word_out_rtps => data_dm_fdmre(WORD_WIDTH),
|
||||||
|
-- TO RTPS OUT
|
||||||
|
full_ro => full_firo_dm,
|
||||||
|
wr_ro => write_dm_firo,
|
||||||
|
data_out_ro => data_dm_firo(WORD_WIDTH-1 downto 0),
|
||||||
|
last_word_out_ro => data_dm_firo(WORD_WIDTH)
|
||||||
|
);
|
||||||
|
|
||||||
|
|
||||||
|
fifo_dm_re_gen : for i in 0 to NUM_ENDPOINTS-1 generate
|
||||||
|
fifo_dm_re_inst : configuration work.FWFT_FIFO_cfg
|
||||||
|
generic map (
|
||||||
|
FIFO_DEPTH => 2,
|
||||||
|
DATA_WIDTH => WORD_WIDTH+1
|
||||||
|
)
|
||||||
|
port map (
|
||||||
|
-- SYSTEM
|
||||||
|
reset => reset,
|
||||||
|
clk => clk,
|
||||||
|
-- INPUT
|
||||||
|
full => full_fdmre_re(i),
|
||||||
|
write => write_dm_fdmre(i),
|
||||||
|
data_in => data_dm_fdmre, -- Multicast
|
||||||
|
-- OUTPUT
|
||||||
|
empty => empty_fdmre_re(i),
|
||||||
|
read => read_re_fdmre(i),
|
||||||
|
data_out => data_fdmre_re(i),
|
||||||
|
-- MISC
|
||||||
|
free => open
|
||||||
|
);
|
||||||
|
end generate;
|
||||||
|
|
||||||
|
|
||||||
|
rtps_endpoint_gen : for i in 0 to NUM_ENDPOINTS-1 generate
|
||||||
|
rtps_endpoint_if : if (i < NUM_READERS) generate
|
||||||
|
rtps_reader_inst : entity work.rtps_reader(arch)
|
||||||
|
generic map (
|
||||||
|
ENTITYID => ENTITYID(i),
|
||||||
|
RELIABILITY_QOS => ENDPOINT_CONFIG(i).RELIABILITY_QOS,
|
||||||
|
LIVELINESS_QOS => ENDPOINT_CONFIG(i).LIVELINESS_QOS,
|
||||||
|
DURABILITY_QOS => ENDPOINT_CONFIG(i).DURABILITY_QOS,
|
||||||
|
HEARTBEAT_RESPONSE_DELAY => ENDPOINT_CONFIG(i).HEARTBEAT_RESPONSE_DELAY,
|
||||||
|
HEARTBEAT_SUPPRESSION_DELAY => ENDPOINT_CONFIG(i).HEARTBEAT_SUPPRESSION_DELAY,
|
||||||
|
LEASE_DURATION => ENDPOINT_CONFIG(i).LEASE_DURATION,
|
||||||
|
WITH_KEY => ENDPOINT_CONFIG(i).WITH_KEY,
|
||||||
|
MAX_REMOTE_ENDPOINTS => MAX_REMOTE_ENDPOINTS
|
||||||
|
)
|
||||||
|
port map (
|
||||||
|
-- SYSTEM
|
||||||
|
clk => clk,
|
||||||
|
reset => reset,
|
||||||
|
time => time,
|
||||||
|
-- FROM RTPS_HANDLER (USER TRAFFIC)
|
||||||
|
empty_user => empty_fire_re(i),
|
||||||
|
rd_user => read_re_fire(i),
|
||||||
|
data_in_user => data_fire_re(i)(WORD_WIDTH-1 downto 0),
|
||||||
|
last_word_in_user => data_fire_re(i)(WORD_WIDTH),
|
||||||
|
-- FROM DISCOVERY MODULE (META TRAFFIC)
|
||||||
|
empty_meta => empty_fdmre_re(i),
|
||||||
|
rd_meta => read_re_fdmre(i),
|
||||||
|
data_in_meta => data_fdmre_re(i)(WORD_WIDTH-1 downto 0),
|
||||||
|
last_word_in_meta => data_fdmre_re(i)(WORD_WIDTH),
|
||||||
|
-- RTPS OUTPUT
|
||||||
|
full_ro => full_firo_re(i),
|
||||||
|
wr_ro => write_re_firo(i),
|
||||||
|
data_out_ro => data_re_firo(i)(WORD_WIDTH-1 downto 0),
|
||||||
|
last_word_out_ro => data_re_firo(i)(WORD_WIDTH),
|
||||||
|
-- TO HISTORY CACHE
|
||||||
|
start_hc => start_rr_dr(i),
|
||||||
|
opcode_hc => opcode_rr_dr(i),
|
||||||
|
ack_hc => ack_dr_rr(i),
|
||||||
|
done_hc => done_dr_rr(i),
|
||||||
|
ret_hc => ret_dr_rr(i),
|
||||||
|
valid_out_hc => valid_rr_dr(i),
|
||||||
|
ready_out_hc => ready_dr_rr(i),
|
||||||
|
data_out_hc => data_rr_dr(i)(WORD_WIDTH-1 downto 0),
|
||||||
|
last_word_out_hc => data_rr_dr(i)(WORD_WIDTH)
|
||||||
|
);
|
||||||
|
|
||||||
|
-- Set Alive Signals of Readers to Zero
|
||||||
|
alive_re_dm(i) <= ('0');
|
||||||
|
else generate
|
||||||
|
rtps_writer_inst : entity work.rtps_writer(arch)
|
||||||
|
generic map (
|
||||||
|
RELIABILITY_QOS => ENDPOINT_CONFIG(i).RELIABILITY_QOS,
|
||||||
|
LIVELINESS_QOS => ENDPOINT_CONFIG(i).LIVELINESS_QOS,
|
||||||
|
DURABILITY_QOS => ENDPOINT_CONFIG(i).DURABILITY_QOS,
|
||||||
|
DESTINATION_ORDER_QOS => ENDPOINT_CONFIG(i).DESTINATION_ORDER_QOS,
|
||||||
|
ACKNACK_RESPONSE_DELAY => ENDPOINT_CONFIG(i).ACKNACK_RESPONSE_DELAY,
|
||||||
|
ACKNACK_SUPPRESSION_DELAY => ENDPOINT_CONFIG(i).ACKNACK_SUPPRESSION_DELAY,
|
||||||
|
LEASE_DURATION => ENDPOINT_CONFIG(i).LEASE_DURATION,
|
||||||
|
HEARTBEAT_PERIOD => ENDPOINT_CONFIG(i).HEARTBEAT_PERIOD,
|
||||||
|
ENTITYID => ENTITYID(i),
|
||||||
|
WITH_KEY => ENDPOINT_CONFIG(i).WITH_KEY,
|
||||||
|
PUSH_MODE => ENDPOINT_CONFIG(i).PUSH_MODE,
|
||||||
|
INLINE_QOS => gen_inline_qos(i),
|
||||||
|
MAX_REMOTE_ENDPOINTS => MAX_REMOTE_ENDPOINTS
|
||||||
|
)
|
||||||
|
port map (
|
||||||
|
-- SYSTEM
|
||||||
|
clk => clk,
|
||||||
|
reset => reset,
|
||||||
|
time => time,
|
||||||
|
-- FROM RTPS_HANDLER (USER TRAFFIC)
|
||||||
|
empty_user => empty_fire_re(i),
|
||||||
|
rd_user => read_re_fire(i),
|
||||||
|
data_in_user => data_fire_re(i)(WORD_WIDTH-1 downto 0),
|
||||||
|
last_word_in_user => data_fire_re(i)(WORD_WIDTH),
|
||||||
|
-- FROM DISCOVERY MODULE (META TRAFFIC)
|
||||||
|
empty_meta => empty_fdmre_re(i),
|
||||||
|
rd_meta => read_re_fdmre(i),
|
||||||
|
data_in_meta => data_fdmre_re(i)(WORD_WIDTH-1 downto 0),
|
||||||
|
last_word_in_meta => data_fdmre_re(i)(WORD_WIDTH),
|
||||||
|
-- TO DISCOVERY MODULE (META TRAFFIC)
|
||||||
|
alive_sig => alive_re_dm(i),
|
||||||
|
-- RTPS OUTPUT
|
||||||
|
full_ro => full_firo_re(i),
|
||||||
|
wr_ro => write_re_firo(i),
|
||||||
|
data_out_ro => data_re_firo(i)(WORD_WIDTH-1 downto 0),
|
||||||
|
last_word_out_ro => data_re_firo(i)(WORD_WIDTH),
|
||||||
|
-- FROM HC
|
||||||
|
liveliness_assertion => liveliness_assertion_dw_rw(i-NUM_READERS),
|
||||||
|
data_available => data_available_dw_rw(i-NUM_READERS),
|
||||||
|
start_hc => start_rw_dw(i-NUM_READERS),
|
||||||
|
opcode_hc => opcode_rw_dw(i-NUM_READERS),
|
||||||
|
ack_hc => ack_dw_rw(i-NUM_READERS),
|
||||||
|
seq_nr_hc => seq_nr_rw_dw(i-NUM_READERS),
|
||||||
|
done_hc => done_rw_dw(i-NUM_READERS),
|
||||||
|
ret_hc => ret_dw_rw(i-NUM_READERS),
|
||||||
|
get_data_hc => get_data_rw_dw(i-NUM_READERS),
|
||||||
|
valid_in_hc => valid_dw_rw(i-NUM_READERS),
|
||||||
|
ready_in_hc => ready_rw_dw(i-NUM_READERS),
|
||||||
|
data_in_hc => data_dw_rw(i-NUM_READERS)(WORD_WIDTH-1 downto 0),
|
||||||
|
last_word_in_hc => data_dw_rw(i-NUM_READERS)(WORD_WIDTH),
|
||||||
|
cc_instance_handle => cc_instance_handle_dw_rw(i-NUM_READERS),
|
||||||
|
cc_kind => cc_kind_dw_rw(i-NUM_READERS),
|
||||||
|
cc_source_timestamp => cc_source_timestamp_dw_rw(i-NUM_READERS),
|
||||||
|
cc_seq_nr => cc_seq_nr_dw_rw(i-NUM_READERS)
|
||||||
|
);
|
||||||
|
end generate;
|
||||||
|
end generate;
|
||||||
|
|
||||||
|
|
||||||
|
dds_endpoint_gen : for i in 0 to NUM_ENDPOINTS-2 generate
|
||||||
|
dds_endpoint_if : if (i < NUM_READERS) generate
|
||||||
|
dds_reader_inst : entity work.dds_reader(arch)
|
||||||
|
generic map (
|
||||||
|
TIME_BASED_FILTER_QOS => ENDPOINT_CONFIG(i).TIME_BASED_FILTER_QOS,
|
||||||
|
DEADLINE_QOS => ENDPOINT_CONFIG(i).DEADLINE_QOS,
|
||||||
|
MAX_INSTANCES => ENDPOINT_CONFIG(i).MAX_INSTANCES,
|
||||||
|
MAX_SAMPLES_PER_INSTANCE => ENDPOINT_CONFIG(i).MAX_SAMPLES_PER_INSTANCE,
|
||||||
|
MAX_SAMPLES => ENDPOINT_CONFIG(i).MAX_SAMPLES,
|
||||||
|
HISTORY_QOS => ENDPOINT_CONFIG(i).HISTORY_QOS,
|
||||||
|
RELIABILITY_QOS => ENDPOINT_CONFIG(i).RELIABILITY_QOS,
|
||||||
|
PRESENTATION_QOS => ENDPOINT_CONFIG(i).PRESENTATION_QOS,
|
||||||
|
DESTINATION_ORDER_QOS => ENDPOINT_CONFIG(i).DESTINATION_ORDER_QOS,
|
||||||
|
COHERENT_ACCESS => ENDPOINT_CONFIG(i).COHERENT_ACCESS,
|
||||||
|
ORDERED_ACCESS => ENDPOINT_CONFIG(i).ORDERED_ACCESS,
|
||||||
|
WITH_KEY => ENDPOINT_CONFIG(i).WITH_KEY,
|
||||||
|
PAYLOAD_FRAME_SIZE => ENDPOINT_CONFIG(i).MAX_PAYLOAD_SIZE,
|
||||||
|
MAX_REMOTE_ENDPOINTS => MAX_REMOTE_ENDPOINTS
|
||||||
|
)
|
||||||
|
port map (
|
||||||
|
-- SYSTEM
|
||||||
|
clk => clk,
|
||||||
|
reset => reset,
|
||||||
|
time => time,
|
||||||
|
-- FROM RTPS ENDPOINT
|
||||||
|
start_rtps => start_rr_dr(i),
|
||||||
|
opcode_rtps => opcode_rr_dr(i),
|
||||||
|
ack_rtps => ack_dr_rr(i),
|
||||||
|
done_rtps => done_dr_rr(i),
|
||||||
|
ret_rtps => ret_dr_rr(i),
|
||||||
|
valid_in_rtps => valid_rr_dr(i),
|
||||||
|
ready_in_rtps => ready_dr_rr(i),
|
||||||
|
data_in_rtps => data_rr_dr(i)(WORD_WIDTH-1 downto 0),
|
||||||
|
last_word_in_rtps => data_rr_dr(i)(WORD_WIDTH),
|
||||||
|
-- TO USER ENTITY
|
||||||
|
start_dds => start_ri_dr(i),
|
||||||
|
ack_dds => ack_dr_ri(i),
|
||||||
|
opcode_dds => opcode_ri_dr(i),
|
||||||
|
instance_state_dds => instance_state_ri_dr(i),
|
||||||
|
view_state_dds => view_state_ri_dr(i),
|
||||||
|
sample_state_dds => sample_state_ri_dr(i),
|
||||||
|
instance_handle_dds => instance_handle_ri_dr(i),
|
||||||
|
max_samples_dds => max_samples_ri_dr(i),
|
||||||
|
get_data_dds => get_data_ri_dr(i),
|
||||||
|
done_dds => done_dr_ri(i),
|
||||||
|
return_code_dds => return_code_dr_ri(i),
|
||||||
|
valid_out_dds => valid_dr_ri(i),
|
||||||
|
ready_out_dds => ready_ri_dr(i),
|
||||||
|
data_out_dds => data_dr_ri(i)(WORD_WIDTH-1 downto 0),
|
||||||
|
last_word_out_dds => data_dr_ri(i)(WORD_WIDTH),
|
||||||
|
sample_info => sample_info_dr_ri(i),
|
||||||
|
sample_info_valid => sample_info_valid_dr_ri(i),
|
||||||
|
sample_info_ack => sample_info_ack_ri_dr(i),
|
||||||
|
eoc => eoc_dr_ri(i),
|
||||||
|
-- Communication Status
|
||||||
|
status => status_dr_ri(i)
|
||||||
|
);
|
||||||
|
else generate
|
||||||
|
dds_writer_inst : entity work.dds_writer(arch)
|
||||||
|
generic map (
|
||||||
|
HISTORY_QOS => ENDPOINT_CONFIG(i).HISTORY_QOS,
|
||||||
|
DEADLINE_QOS => ENDPOINT_CONFIG(i).DEADLINE_QOS,
|
||||||
|
LIFESPAN_QOS => ENDPOINT_CONFIG(i).LIFESPAN_QOS,
|
||||||
|
LEASE_DURATION => ENDPOINT_CONFIG(i).LEASE_DURATION,
|
||||||
|
WITH_KEY => ENDPOINT_CONFIG(i).WITH_KEY,
|
||||||
|
MAX_SAMPLES => ENDPOINT_CONFIG(i).MAX_SAMPLES,
|
||||||
|
MAX_INSTANCES => ENDPOINT_CONFIG(i).MAX_INSTANCES,
|
||||||
|
MAX_SAMPLES_PER_INSTANCE => ENDPOINT_CONFIG(i).MAX_SAMPLES_PER_INSTANCE,
|
||||||
|
PAYLOAD_FRAME_SIZE => ENDPOINT_CONFIG(i).MAX_PAYLOAD_SIZE
|
||||||
|
)
|
||||||
|
port map (
|
||||||
|
-- SYSTEM
|
||||||
|
clk => clk,
|
||||||
|
reset => reset,
|
||||||
|
time => time,
|
||||||
|
-- TO/FROM RTPS ENDPOINT
|
||||||
|
start_rtps => start_rw_dw(i-NUM_READERS),
|
||||||
|
opcode_rtps => opcode_rw_dw(i-NUM_READERS),
|
||||||
|
ack_rtps => ack_dw_rw(i-NUM_READERS),
|
||||||
|
done_rtps => done_rw_dw(i-NUM_READERS),
|
||||||
|
ret_rtps => ret_dw_rw(i-NUM_READERS),
|
||||||
|
seq_nr_rtps => seq_nr_rw_dw(i-NUM_READERS),
|
||||||
|
get_data_rtps => get_data_rw_dw(i-NUM_READERS),
|
||||||
|
valid_out_rtps => valid_dw_rw(i-NUM_READERS),
|
||||||
|
ready_out_rtps => ready_rw_dw(i-NUM_READERS),
|
||||||
|
data_out_rtps => data_dw_rw(i-NUM_READERS)(WORD_WIDTH-1 downto 0),
|
||||||
|
last_word_out_rtps => data_dw_rw(i-NUM_READERS)(WORD_WIDTH),
|
||||||
|
liveliness_assertion => liveliness_assertion_dw_rw(i-NUM_READERS),
|
||||||
|
data_available => data_available_dw_rw(i-NUM_READERS),
|
||||||
|
-- Cache Change
|
||||||
|
cc_instance_handle => cc_instance_handle_dw_rw(i-NUM_READERS),
|
||||||
|
cc_kind => cc_kind_dw_rw(i-NUM_READERS),
|
||||||
|
cc_source_timestamp => cc_source_timestamp_dw_rw(i-NUM_READERS),
|
||||||
|
cc_seq_nr => cc_seq_nr_dw_rw(i-NUM_READERS),
|
||||||
|
-- TO/FROM USER ENTITY
|
||||||
|
start_dds => start_wi_dw(i-NUM_READERS),
|
||||||
|
ack_dds => ack_dw_wi(i-NUM_READERS),
|
||||||
|
opcode_dds => opcode_wi_dw(i-NUM_READERS),
|
||||||
|
instance_handle_in_dds => instance_handle_wi_dw(i-NUM_READERS),
|
||||||
|
source_ts_dds => source_ts_wi_dw(i-NUM_READERS),
|
||||||
|
max_wait_dds => max_wait_wi_dw(i-NUM_READERS),
|
||||||
|
done_dds => done_dw_wi(i-NUM_READERS),
|
||||||
|
return_code_dds => return_code_dw_wi(i-NUM_READERS),
|
||||||
|
instance_handle_out_dds => instance_handle_dw_wi(i-NUM_READERS),
|
||||||
|
valid_in_dds => valid_wi_dw(i-NUM_READERS),
|
||||||
|
ready_in_dds => ready_dw_wi(i-NUM_READERS),
|
||||||
|
data_in_dds => data_wi_dw(i-NUM_READERS)(WORD_WIDTH-1 downto 0),
|
||||||
|
last_word_in_dds => data_wi_dw(i-NUM_READERS)(WORD_WIDTH),
|
||||||
|
valid_out_dds => valid_dw_wi(i-NUM_READERS),
|
||||||
|
ready_out_dds => ready_wi_dw(i-NUM_READERS),
|
||||||
|
data_out_dds => data_dw_wi(i-NUM_READERS)(WORD_WIDTH-1 downto 0),
|
||||||
|
last_word_out_dds => data_dw_wi(i-NUM_READERS)(WORD_WIDTH),
|
||||||
|
-- Communication Status
|
||||||
|
status => status_dw_wi(i-NUM_READERS)
|
||||||
|
);
|
||||||
|
end generate;
|
||||||
|
end generate;
|
||||||
|
|
||||||
|
ros_discovery_writer_inst : entity work.ros_static_discovery_writer(arch)
|
||||||
|
port map (
|
||||||
|
-- SYSTEM
|
||||||
|
clk => clk,
|
||||||
|
reset => reset,
|
||||||
|
-- TO/FROM RTPS ENDPOINT
|
||||||
|
start => start_rw_dw(NUM_WRITERS-1),
|
||||||
|
opcode => opcode_rw_dw(NUM_WRITERS-1),
|
||||||
|
ack => ack_dw_rw(NUM_WRITERS-1),
|
||||||
|
done => done_rw_dw(NUM_WRITERS-1),
|
||||||
|
ret => ret_dw_rw(NUM_WRITERS-1),
|
||||||
|
seq_nr => seq_nr_rw_dw(NUM_WRITERS-1),
|
||||||
|
get_data => get_data_rw_dw(NUM_WRITERS-1),
|
||||||
|
valid_out => valid_dw_rw(NUM_WRITERS-1),
|
||||||
|
ready_out => ready_rw_dw(NUM_WRITERS-1),
|
||||||
|
data_out => data_dw_rw(NUM_WRITERS-1)(WORD_WIDTH-1 downto 0),
|
||||||
|
last_word_out => data_dw_rw(NUM_WRITERS-1)(WORD_WIDTH),
|
||||||
|
liveliness_assertion => liveliness_assertion_dw_rw(NUM_WRITERS-1),
|
||||||
|
data_available => data_available_dw_rw(NUM_WRITERS-1),
|
||||||
|
-- Cache Change
|
||||||
|
cc_instance_handle => cc_instance_handle_dw_rw(NUM_WRITERS-1),
|
||||||
|
cc_kind => cc_kind_dw_rw(NUM_WRITERS-1),
|
||||||
|
cc_source_timestamp => cc_source_timestamp_dw_rw(NUM_WRITERS-1),
|
||||||
|
cc_seq_nr => cc_seq_nr_dw_rw(NUM_WRITERS-1)
|
||||||
|
);
|
||||||
|
|
||||||
|
|
||||||
|
fifo_in_ro_gen : for i in 0 to NUM_ENDPOINTS generate
|
||||||
|
fifo_in_ro_if : if (i = NUM_ENDPOINTS) generate
|
||||||
|
fifo_in_ro_inst : configuration work.FWFT_FIFO_cfg
|
||||||
|
generic map (
|
||||||
|
FIFO_DEPTH => 2,
|
||||||
|
DATA_WIDTH => WORD_WIDTH+1
|
||||||
|
)
|
||||||
|
port map (
|
||||||
|
-- SYSTEM
|
||||||
|
reset => reset,
|
||||||
|
clk => clk,
|
||||||
|
-- INPUT
|
||||||
|
full => full_firo_dm,
|
||||||
|
write => write_dm_firo,
|
||||||
|
data_in => data_dm_firo,
|
||||||
|
-- OUTPUT
|
||||||
|
empty => empty_firo_ro(i),
|
||||||
|
read => read_ro_firo(i),
|
||||||
|
data_out(WORD_WIDTH) => last_word_firo_ro(i),
|
||||||
|
data_out(WORD_WIDTH-1 downto 0) => data_firo_ro(i),
|
||||||
|
-- MISC
|
||||||
|
free => open
|
||||||
|
);
|
||||||
|
else generate
|
||||||
|
fifo_in_ro_inst : configuration work.FWFT_FIFO_cfg
|
||||||
|
generic map (
|
||||||
|
FIFO_DEPTH => 2,
|
||||||
|
DATA_WIDTH => WORD_WIDTH+1
|
||||||
|
)
|
||||||
|
port map (
|
||||||
|
-- SYSTEM
|
||||||
|
reset => reset,
|
||||||
|
clk => clk,
|
||||||
|
-- INPUT
|
||||||
|
full => full_firo_re(i),
|
||||||
|
write => write_re_firo(i),
|
||||||
|
data_in => data_re_firo(i),
|
||||||
|
-- OUTPUT
|
||||||
|
empty => empty_firo_ro(i),
|
||||||
|
read => read_ro_firo(i),
|
||||||
|
data_out(WORD_WIDTH) => last_word_firo_ro(i),
|
||||||
|
data_out(WORD_WIDTH-1 downto 0) => data_firo_ro(i),
|
||||||
|
-- MISC
|
||||||
|
free => open
|
||||||
|
);
|
||||||
|
end generate;
|
||||||
|
end generate;
|
||||||
|
|
||||||
|
|
||||||
|
rtps_out_inst : entity work.rtps_out(arch)
|
||||||
|
port map (
|
||||||
|
-- SYSTEM
|
||||||
|
clk => clk,
|
||||||
|
reset => reset,
|
||||||
|
-- INPUT
|
||||||
|
empty => empty_firo_ro,
|
||||||
|
rd => read_ro_firo,
|
||||||
|
data_in => data_firo_ro,
|
||||||
|
last_word_in => last_word_firo_ro,
|
||||||
|
-- OUTPUT
|
||||||
|
full => full,
|
||||||
|
wr => write,
|
||||||
|
data_out => data_out
|
||||||
|
);
|
||||||
|
|
||||||
|
action_if_gen : for i in 0 to NUM_ACTIONS-1 generate
|
||||||
|
--
|
||||||
|
start_ri_dr(i) <= action_if(i).g_start_r;
|
||||||
|
action_if(i).g_ack_r <= ack_dr_ri(i);
|
||||||
|
opcode_ri_dr(i) <= action_if(i).g_opcode_r;
|
||||||
|
instance_state_ri_dr(i) <= action_if(i).g_instance_state_r;
|
||||||
|
view_state_ri_dr(i) <= action_if(i).g_view_state_r;
|
||||||
|
sample_state_ri_dr(i) <= action_if(i).g_sample_state_r;
|
||||||
|
instance_handle_ri_dr(i) <= action_if(i).g_instance_handle_r;
|
||||||
|
max_samples_ri_dr(i) <= action_if(i).g_max_samples_r;
|
||||||
|
get_data_ri_dr(i) <= action_if(i).g_get_data_r;
|
||||||
|
action_if(i).g_done_r <= done_dr_ri(i);
|
||||||
|
action_if(i).g_return_code_r <= return_code_dr_ri(i);
|
||||||
|
action_if(i).g_valid_in_r <= valid_dr_ri(i);
|
||||||
|
ready_ri_dr(i) <= action_if(i).g_ready_in_r;
|
||||||
|
action_if(i).g_data_in_r <= data_dr_ri(i)(WORD_WIDTH-1 downto 0);
|
||||||
|
action_if(i).g_last_word_in_r <= data_dr_ri(i)(WORD_WIDTH);
|
||||||
|
action_if(i).g_sample_info_r <= sample_info_dr_ri(i);
|
||||||
|
action_if(i).g_sample_info_valid_r <= sample_info_valid_dr_ri(i);
|
||||||
|
sample_info_ack_ri_dr(i) <= action_if(i).g_sample_info_ack_r;
|
||||||
|
action_if(i).g_eoc_r <= eoc_dr_ri(i);
|
||||||
|
action_if(i).g_status_r <= status_dr_ri(i);
|
||||||
|
start_wi_dw(i) <= action_if(i).g_start_w;
|
||||||
|
action_if(i).g_ack_w <= ack_dw_wi(i);
|
||||||
|
opcode_wi_dw(i) <= action_if(i).g_opcode_w;
|
||||||
|
action_if(i).g_instance_handle_out_w <= instance_handle_dw_wi(i);
|
||||||
|
source_ts_wi_dw(i) <= action_if(i).g_source_ts_w;
|
||||||
|
max_wait_wi_dw(i) <= action_if(i).g_max_wait_w;
|
||||||
|
action_if(i).g_done_w <= done_dw_wi(i);
|
||||||
|
action_if(i).g_return_code_w <= return_code_dw_wi(i);
|
||||||
|
instance_handle_wi_dw(i) <= action_if(i).g_instance_handle_in_w;
|
||||||
|
valid_wi_dw(i) <= action_if(i).g_valid_out_w;
|
||||||
|
action_if(i).g_ready_out_w <= ready_dw_wi(i);
|
||||||
|
data_wi_dw(i)(WORD_WIDTH-1 downto 0) <= action_if(i).g_data_out_w;
|
||||||
|
data_wi_dw(i)(WORD_WIDTH) <= action_if(i).g_last_word_out_w;
|
||||||
|
action_if(i).g_valid_in_w <= valid_dw_wi(i);
|
||||||
|
ready_wi_dw(i) <= action_if(i).g_ready_in_w;
|
||||||
|
action_if(i).g_data_in_w <= data_dw_wi(i)(WORD_WIDTH-1 downto 0);
|
||||||
|
action_if(i).g_last_word_in_w <= data_dw_wi(i)(WORD_WIDTH);
|
||||||
|
action_if(i).g_status_w <= status_dw_wi(i);
|
||||||
|
--
|
||||||
|
start_ri_dr(i+1) <= action_if(i).r_start_r;
|
||||||
|
action_if(i).r_ack_r <= ack_dr_ri(i+1);
|
||||||
|
opcode_ri_dr(i+1) <= action_if(i).r_opcode_r;
|
||||||
|
instance_state_ri_dr(i+1) <= action_if(i).r_instance_state_r;
|
||||||
|
view_state_ri_dr(i+1) <= action_if(i).r_view_state_r;
|
||||||
|
sample_state_ri_dr(i+1) <= action_if(i).r_sample_state_r;
|
||||||
|
instance_handle_ri_dr(i+1) <= action_if(i).r_instance_handle_r;
|
||||||
|
max_samples_ri_dr(i+1) <= action_if(i).r_max_samples_r;
|
||||||
|
get_data_ri_dr(i+1) <= action_if(i).r_get_data_r;
|
||||||
|
action_if(i).r_done_r <= done_dr_ri(i+1);
|
||||||
|
action_if(i).r_return_code_r <= return_code_dr_ri(i+1);
|
||||||
|
action_if(i).r_valid_in_r <= valid_dr_ri(i+1);
|
||||||
|
ready_ri_dr(i+1) <= action_if(i).r_ready_in_r;
|
||||||
|
action_if(i).r_data_in_r <= data_dr_ri(i+1)(WORD_WIDTH-1 downto 0);
|
||||||
|
action_if(i).r_last_word_in_r <= data_dr_ri(i+1)(WORD_WIDTH);
|
||||||
|
action_if(i).r_sample_info_r <= sample_info_dr_ri(i+1);
|
||||||
|
action_if(i).r_sample_info_valid_r <= sample_info_valid_dr_ri(i+1);
|
||||||
|
sample_info_ack_ri_dr(i+1) <= action_if(i).r_sample_info_ack_r;
|
||||||
|
action_if(i).r_eoc_r <= eoc_dr_ri(i+1);
|
||||||
|
action_if(i).r_status_r <= status_dr_ri(i+1);
|
||||||
|
start_wi_dw(i+1) <= action_if(i).r_start_w;
|
||||||
|
action_if(i).r_ack_w <= ack_dw_wi(i+1);
|
||||||
|
opcode_wi_dw(i+1) <= action_if(i).r_opcode_w;
|
||||||
|
action_if(i).r_instance_handle_out_w <= instance_handle_dw_wi(i+1);
|
||||||
|
source_ts_wi_dw(i+1) <= action_if(i).r_source_ts_w;
|
||||||
|
max_wait_wi_dw(i+1) <= action_if(i).r_max_wait_w;
|
||||||
|
action_if(i).r_done_w <= done_dw_wi(i+1);
|
||||||
|
action_if(i).r_return_code_w <= return_code_dw_wi(i+1);
|
||||||
|
instance_handle_wi_dw(i+1) <= action_if(i).r_instance_handle_in_w;
|
||||||
|
valid_wi_dw(i+1) <= action_if(i).r_valid_out_w;
|
||||||
|
action_if(i).r_ready_out_w <= ready_dw_wi(i+1);
|
||||||
|
data_wi_dw(i+1)(WORD_WIDTH-1 downto 0) <= action_if(i).r_data_out_w;
|
||||||
|
data_wi_dw(i+1)(WORD_WIDTH) <= action_if(i).r_last_word_out_w;
|
||||||
|
action_if(i).r_valid_in_w <= valid_dw_wi(i+1);
|
||||||
|
ready_wi_dw(i+1) <= action_if(i).r_ready_in_w;
|
||||||
|
action_if(i).r_data_in_w <= data_dw_wi(i+1)(WORD_WIDTH-1 downto 0);
|
||||||
|
action_if(i).r_last_word_in_w <= data_dw_wi(i+1)(WORD_WIDTH);
|
||||||
|
action_if(i).r_status_w <= status_dw_wi(i+1);
|
||||||
|
--
|
||||||
|
start_ri_dr(i+2) <= action_if(i).c_start_r;
|
||||||
|
action_if(i).c_ack_r <= ack_dr_ri(i+2);
|
||||||
|
opcode_ri_dr(i+2) <= action_if(i).c_opcode_r;
|
||||||
|
instance_state_ri_dr(i+2) <= action_if(i).c_instance_state_r;
|
||||||
|
view_state_ri_dr(i+2) <= action_if(i).c_view_state_r;
|
||||||
|
sample_state_ri_dr(i+2) <= action_if(i).c_sample_state_r;
|
||||||
|
instance_handle_ri_dr(i+2) <= action_if(i).c_instance_handle_r;
|
||||||
|
max_samples_ri_dr(i+2) <= action_if(i).c_max_samples_r;
|
||||||
|
get_data_ri_dr(i+2) <= action_if(i).c_get_data_r;
|
||||||
|
action_if(i).c_done_r <= done_dr_ri(i+2);
|
||||||
|
action_if(i).c_return_code_r <= return_code_dr_ri(i+2);
|
||||||
|
action_if(i).c_valid_in_r <= valid_dr_ri(i+2);
|
||||||
|
ready_ri_dr(i+2) <= action_if(i).c_ready_in_r;
|
||||||
|
action_if(i).c_data_in_r <= data_dr_ri(i+2)(WORD_WIDTH-1 downto 0);
|
||||||
|
action_if(i).c_last_word_in_r <= data_dr_ri(i+2)(WORD_WIDTH);
|
||||||
|
action_if(i).c_sample_info_r <= sample_info_dr_ri(i+2);
|
||||||
|
action_if(i).c_sample_info_valid_r <= sample_info_valid_dr_ri(i+2);
|
||||||
|
sample_info_ack_ri_dr(i+2) <= action_if(i).c_sample_info_ack_r;
|
||||||
|
action_if(i).c_eoc_r <= eoc_dr_ri(i+2);
|
||||||
|
action_if(i).c_status_r <= status_dr_ri(i+2);
|
||||||
|
start_wi_dw(i+2) <= action_if(i).c_start_w;
|
||||||
|
action_if(i).c_ack_w <= ack_dw_wi(i+2);
|
||||||
|
opcode_wi_dw(i+2) <= action_if(i).c_opcode_w;
|
||||||
|
action_if(i).c_instance_handle_out_w <= instance_handle_dw_wi(i+2);
|
||||||
|
source_ts_wi_dw(i+2) <= action_if(i).c_source_ts_w;
|
||||||
|
max_wait_wi_dw(i+2) <= action_if(i).c_max_wait_w;
|
||||||
|
action_if(i).c_done_w <= done_dw_wi(i+2);
|
||||||
|
action_if(i).c_return_code_w <= return_code_dw_wi(i+2);
|
||||||
|
instance_handle_wi_dw(i+2) <= action_if(i).c_instance_handle_in_w;
|
||||||
|
valid_wi_dw(i+2) <= action_if(i).c_valid_out_w;
|
||||||
|
action_if(i).c_ready_out_w <= ready_dw_wi(i+2);
|
||||||
|
data_wi_dw(i+2)(WORD_WIDTH-1 downto 0) <= action_if(i).c_data_out_w;
|
||||||
|
data_wi_dw(i+2)(WORD_WIDTH) <= action_if(i).c_last_word_out_w;
|
||||||
|
action_if(i).c_valid_in_w <= valid_dw_wi(i+2);
|
||||||
|
ready_wi_dw(i+2) <= action_if(i).c_ready_in_w;
|
||||||
|
action_if(i).c_data_in_w <= data_dw_wi(i+2)(WORD_WIDTH-1 downto 0);
|
||||||
|
action_if(i).c_last_word_in_w <= data_dw_wi(i+2)(WORD_WIDTH);
|
||||||
|
action_if(i).c_status_w <= status_dw_wi(i+2);
|
||||||
|
--
|
||||||
|
end generate;
|
||||||
|
|
||||||
|
-- ######GENERATED START######
|
||||||
|
|
||||||
|
Fibonacci_ros_action_client_inst : entity work.Fibonacci_ros_action_client(arch)
|
||||||
|
generic map (
|
||||||
|
ENABLE_FEEDBACK => '1'
|
||||||
|
)
|
||||||
|
port map (
|
||||||
|
clk => clk,
|
||||||
|
reset => reset,
|
||||||
|
time => ros_time,
|
||||||
|
g_start_r => action_if(0).g_start_r,
|
||||||
|
g_ack_r => action_if(0).g_ack_r,
|
||||||
|
g_opcode_r => action_if(0).g_opcode_r,
|
||||||
|
g_instance_state_r => action_if(0).g_instance_state_r,
|
||||||
|
g_view_state_r => action_if(0).g_view_state_r,
|
||||||
|
g_sample_state_r => action_if(0).g_sample_state_r,
|
||||||
|
g_instance_handle_r => action_if(0).g_instance_handle_r,
|
||||||
|
g_max_samples_r => action_if(0).g_max_samples_r,
|
||||||
|
g_get_data_r => action_if(0).g_get_data_r,
|
||||||
|
g_done_r => action_if(0).g_done_r,
|
||||||
|
g_return_code_r => action_if(0).g_return_code_r,
|
||||||
|
g_valid_in_r => action_if(0).g_valid_in_r,
|
||||||
|
g_ready_in_r => action_if(0).g_ready_in_r,
|
||||||
|
g_data_in_r => action_if(0).g_data_in_r,
|
||||||
|
g_last_word_in_r => action_if(0).g_last_word_in_r,
|
||||||
|
g_sample_info_r => action_if(0).g_sample_info_r,
|
||||||
|
g_sample_info_valid_r => action_if(0).g_sample_info_valid_r,
|
||||||
|
g_sample_info_ack_r => action_if(0).g_sample_info_ack_r,
|
||||||
|
g_eoc_r => action_if(0).g_eoc_r,
|
||||||
|
g_status_r => action_if(0).g_status_r,
|
||||||
|
g_start_w => action_if(0).g_start_w,
|
||||||
|
g_ack_w => action_if(0).g_ack_w,
|
||||||
|
g_opcode_w => action_if(0).g_opcode_w,
|
||||||
|
g_instance_handle_out_w => action_if(0).g_instance_handle_out_w,
|
||||||
|
g_source_ts_w => action_if(0).g_source_ts_w,
|
||||||
|
g_max_wait_w => action_if(0).g_max_wait_w,
|
||||||
|
g_done_w => action_if(0).g_done_w,
|
||||||
|
g_return_code_w => action_if(0).g_return_code_w,
|
||||||
|
g_instance_handle_in_w => action_if(0).g_instance_handle_in_w,
|
||||||
|
g_valid_out_w => action_if(0).g_valid_out_w,
|
||||||
|
g_ready_out_w => action_if(0).g_ready_out_w,
|
||||||
|
g_data_out_w => action_if(0).g_data_out_w,
|
||||||
|
g_last_word_out_w => action_if(0).g_last_word_out_w,
|
||||||
|
g_valid_in_w => action_if(0).g_valid_in_w,
|
||||||
|
g_ready_in_w => action_if(0).g_ready_in_w,
|
||||||
|
g_data_in_w => action_if(0).g_data_in_w,
|
||||||
|
g_last_word_in_w => action_if(0).g_last_word_in_w,
|
||||||
|
g_status_w => action_if(0).g_status_w,
|
||||||
|
r_start_r => action_if(0).r_start_r,
|
||||||
|
r_ack_r => action_if(0).r_ack_r,
|
||||||
|
r_opcode_r => action_if(0).r_opcode_r,
|
||||||
|
r_instance_state_r => action_if(0).r_instance_state_r,
|
||||||
|
r_view_state_r => action_if(0).r_view_state_r,
|
||||||
|
r_sample_state_r => action_if(0).r_sample_state_r,
|
||||||
|
r_instance_handle_r => action_if(0).r_instance_handle_r,
|
||||||
|
r_max_samples_r => action_if(0).r_max_samples_r,
|
||||||
|
r_get_data_r => action_if(0).r_get_data_r,
|
||||||
|
r_done_r => action_if(0).r_done_r,
|
||||||
|
r_return_code_r => action_if(0).r_return_code_r,
|
||||||
|
r_valid_in_r => action_if(0).r_valid_in_r,
|
||||||
|
r_ready_in_r => action_if(0).r_ready_in_r,
|
||||||
|
r_data_in_r => action_if(0).r_data_in_r,
|
||||||
|
r_last_word_in_r => action_if(0).r_last_word_in_r,
|
||||||
|
r_sample_info_r => action_if(0).r_sample_info_r,
|
||||||
|
r_sample_info_valid_r => action_if(0).r_sample_info_valid_r,
|
||||||
|
r_sample_info_ack_r => action_if(0).r_sample_info_ack_r,
|
||||||
|
r_eoc_r => action_if(0).r_eoc_r,
|
||||||
|
r_status_r => action_if(0).r_status_r,
|
||||||
|
r_start_w => action_if(0).r_start_w,
|
||||||
|
r_ack_w => action_if(0).r_ack_w,
|
||||||
|
r_opcode_w => action_if(0).r_opcode_w,
|
||||||
|
r_instance_handle_out_w => action_if(0).r_instance_handle_out_w,
|
||||||
|
r_source_ts_w => action_if(0).r_source_ts_w,
|
||||||
|
r_max_wait_w => action_if(0).r_max_wait_w,
|
||||||
|
r_done_w => action_if(0).r_done_w,
|
||||||
|
r_return_code_w => action_if(0).r_return_code_w,
|
||||||
|
r_instance_handle_in_w => action_if(0).r_instance_handle_in_w,
|
||||||
|
r_valid_out_w => action_if(0).r_valid_out_w,
|
||||||
|
r_ready_out_w => action_if(0).r_ready_out_w,
|
||||||
|
r_data_out_w => action_if(0).r_data_out_w,
|
||||||
|
r_last_word_out_w => action_if(0).r_last_word_out_w,
|
||||||
|
r_valid_in_w => action_if(0).r_valid_in_w,
|
||||||
|
r_ready_in_w => action_if(0).r_ready_in_w,
|
||||||
|
r_data_in_w => action_if(0).r_data_in_w,
|
||||||
|
r_last_word_in_w => action_if(0).r_last_word_in_w,
|
||||||
|
r_status_w => action_if(0).r_status_w,
|
||||||
|
c_start_r => action_if(0).c_start_r,
|
||||||
|
c_ack_r => action_if(0).c_ack_r,
|
||||||
|
c_opcode_r => action_if(0).c_opcode_r,
|
||||||
|
c_instance_state_r => action_if(0).c_instance_state_r,
|
||||||
|
c_view_state_r => action_if(0).c_view_state_r,
|
||||||
|
c_sample_state_r => action_if(0).c_sample_state_r,
|
||||||
|
c_instance_handle_r => action_if(0).c_instance_handle_r,
|
||||||
|
c_max_samples_r => action_if(0).c_max_samples_r,
|
||||||
|
c_get_data_r => action_if(0).c_get_data_r,
|
||||||
|
c_done_r => action_if(0).c_done_r,
|
||||||
|
c_return_code_r => action_if(0).c_return_code_r,
|
||||||
|
c_valid_in_r => action_if(0).c_valid_in_r,
|
||||||
|
c_ready_in_r => action_if(0).c_ready_in_r,
|
||||||
|
c_data_in_r => action_if(0).c_data_in_r,
|
||||||
|
c_last_word_in_r => action_if(0).c_last_word_in_r,
|
||||||
|
c_sample_info_r => action_if(0).c_sample_info_r,
|
||||||
|
c_sample_info_valid_r => action_if(0).c_sample_info_valid_r,
|
||||||
|
c_sample_info_ack_r => action_if(0).c_sample_info_ack_r,
|
||||||
|
c_eoc_r => action_if(0).c_eoc_r,
|
||||||
|
c_status_r => action_if(0).c_status_r,
|
||||||
|
c_start_w => action_if(0).c_start_w,
|
||||||
|
c_ack_w => action_if(0).c_ack_w,
|
||||||
|
c_opcode_w => action_if(0).c_opcode_w,
|
||||||
|
c_instance_handle_out_w => action_if(0).c_instance_handle_out_w,
|
||||||
|
c_source_ts_w => action_if(0).c_source_ts_w,
|
||||||
|
c_max_wait_w => action_if(0).c_max_wait_w,
|
||||||
|
c_done_w => action_if(0).c_done_w,
|
||||||
|
c_return_code_w => action_if(0).c_return_code_w,
|
||||||
|
c_instance_handle_in_w => action_if(0).c_instance_handle_in_w,
|
||||||
|
c_valid_out_w => action_if(0).c_valid_out_w,
|
||||||
|
c_ready_out_w => action_if(0).c_ready_out_w,
|
||||||
|
c_data_out_w => action_if(0).c_data_out_w,
|
||||||
|
c_last_word_out_w => action_if(0).c_last_word_out_w,
|
||||||
|
c_valid_in_w => action_if(0).c_valid_in_w,
|
||||||
|
c_ready_in_w => action_if(0).c_ready_in_w,
|
||||||
|
c_data_in_w => action_if(0).c_data_in_w,
|
||||||
|
c_last_word_in_w => action_if(0).c_last_word_in_w,
|
||||||
|
c_status_w => action_if(0).c_status_w,
|
||||||
|
f_start_dds => start_ri_dr(3),
|
||||||
|
f_ack_dds => ack_dr_ri(3),
|
||||||
|
f_opcode_dds => opcode_ri_dr(3),
|
||||||
|
f_instance_state_dds => instance_state_ri_dr(3),
|
||||||
|
f_view_state_dds => view_state_ri_dr(3),
|
||||||
|
f_sample_state_dds => sample_state_ri_dr(3),
|
||||||
|
f_instance_handle_dds => instance_handle_ri_dr(3),
|
||||||
|
f_max_samples_dds => max_samples_ri_dr(3),
|
||||||
|
f_get_data_dds => get_data_ri_dr(3),
|
||||||
|
f_done_dds => done_dr_ri(3),
|
||||||
|
f_return_code_dds => return_code_dr_ri(3),
|
||||||
|
f_valid_in_dds => valid_dr_ri(3),
|
||||||
|
f_ready_in_dds => ready_ri_dr(3),
|
||||||
|
f_data_in_dds => data_dr_ri(3)(WORD_WIDTH-1 downto 0),
|
||||||
|
f_last_word_in_dds => data_dr_ri(3)(WORD_WIDTH),
|
||||||
|
f_sample_info_dds => sample_info_dr_ri(3),
|
||||||
|
f_sample_info_valid_dds => sample_info_valid_dr_ri(3),
|
||||||
|
f_sample_info_ack_dds => sample_info_ack_ri_dr(3),
|
||||||
|
f_eoc_dds => eoc_dr_ri(3),
|
||||||
|
f_status_dds => status_dr_ri(3),
|
||||||
|
start => start_c,
|
||||||
|
opcode => opcode_c,
|
||||||
|
ack => ack_c,
|
||||||
|
sequence_id => sequence_id_c,
|
||||||
|
service_info => service_info_c,
|
||||||
|
data_available_g => data_available_g_c,
|
||||||
|
data_available_r => data_available_r_c,
|
||||||
|
data_available_c => data_available_c_c,
|
||||||
|
data_available_f => data_available_f_c,
|
||||||
|
done => done_c,
|
||||||
|
return_code => return_code_c,
|
||||||
|
goal_id => goal_id_c,
|
||||||
|
goal_order => goal_order_c,
|
||||||
|
goal_accepted => goal_accepted_c,
|
||||||
|
goal_stamp => goal_stamp_c,
|
||||||
|
result_goal_id => result_goal_id_c,
|
||||||
|
result_status => result_status_c,
|
||||||
|
result_seq_len => result_seq_len_c,
|
||||||
|
result_seq_addr => result_seq_addr_c,
|
||||||
|
result_seq_ready => result_seq_ready_c,
|
||||||
|
result_seq_ren => result_seq_ren_c,
|
||||||
|
result_seq_valid => result_seq_valid_c,
|
||||||
|
result_seq_ack => result_seq_ack_c,
|
||||||
|
result_seq => result_seq_c,
|
||||||
|
cancel_goal_id => cancel_goal_id_c,
|
||||||
|
cancel_stamp => cancel_stamp_c,
|
||||||
|
cancel_return_code => cancel_return_code_c,
|
||||||
|
cancel_goals_canceling_len => cancel_goals_canceling_len_c,
|
||||||
|
cancel_goals_canceling_addr => cancel_goals_canceling_addr_c,
|
||||||
|
cancel_goals_canceling_ready => cancel_goals_canceling_ready_c,
|
||||||
|
cancel_goals_canceling_ren => cancel_goals_canceling_ren_c,
|
||||||
|
cancel_goals_canceling_valid => cancel_goals_canceling_valid_c,
|
||||||
|
cancel_goals_canceling_ack => cancel_goals_canceling_ack_c,
|
||||||
|
cancel_goals_canceling_goal_id => cancel_goals_canceling_goal_id_c,
|
||||||
|
cancel_goals_canceling_stamp => cancel_goals_canceling_stamp_c,
|
||||||
|
feedback_goal_id => feedback_goal_id_c,
|
||||||
|
feedback_seq_len => feedback_seq_len_c,
|
||||||
|
feedback_seq_addr => feedback_seq_addr_c,
|
||||||
|
feedback_seq_ready => feedback_seq_ready_c,
|
||||||
|
feedback_seq_ren => feedback_seq_ren_c,
|
||||||
|
feedback_seq_valid => feedback_seq_valid_c,
|
||||||
|
feedback_seq_ack => feedback_seq_ack_c,
|
||||||
|
feedback_seq => feedback_seq_c
|
||||||
|
);
|
||||||
|
-- ######GENERATED END######
|
||||||
|
|
||||||
|
end architecture;
|
||||||
98
src/ros2/Tests/Level_2/L2_Testbench_ROS_Lib5_config.vhd
Normal file
98
src/ros2/Tests/Level_2/L2_Testbench_ROS_Lib5_config.vhd
Normal file
@ -0,0 +1,98 @@
|
|||||||
|
-- altera vhdl_input_version vhdl_2008
|
||||||
|
-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
|
||||||
|
|
||||||
|
library ieee;
|
||||||
|
use ieee.std_logic_1164.all;
|
||||||
|
use ieee.numeric_std.all;
|
||||||
|
|
||||||
|
use work.rtps_package.all;
|
||||||
|
use work.ros_package.all;
|
||||||
|
use work.Fibonacci_package.all;
|
||||||
|
|
||||||
|
package ros_config is
|
||||||
|
|
||||||
|
-- Period of ros system clock
|
||||||
|
constant ROS_CLOCK_PERIOD : time := 50 ns;
|
||||||
|
-- IPv4 Address of ROS System [Default 192.168.0.132]
|
||||||
|
constant ROS_ADDRESS : std_logic_vector(IPv4_ADDRESS_WIDTH-1 downto 0) := x"C0A80083";
|
||||||
|
-- Random Key used to generate GUIDs
|
||||||
|
constant ROS_RAND_KEY : std_logic_vector(47 downto 0) := x"4E8589142E6A";
|
||||||
|
|
||||||
|
constant NUM_NODES : natural := 1;
|
||||||
|
|
||||||
|
constant ROS_NODES : ROS_NODE_ARRAY_TYPE(0 to NUM_NODES-1) := (
|
||||||
|
0 => (
|
||||||
|
name => gen_user_string("fibonacci_action_client"),
|
||||||
|
namespace => gen_user_string(""),
|
||||||
|
domain_id => 0,
|
||||||
|
NUM_PUBS => 0,
|
||||||
|
NUM_SUBS => 0,
|
||||||
|
NUM_SERVICES => 0,
|
||||||
|
NUM_ACTIONS => 1
|
||||||
|
)
|
||||||
|
);
|
||||||
|
|
||||||
|
constant NUM_PUBS : natural := get_num_pubs(ROS_NODES);
|
||||||
|
constant NUM_SUBS : natural := get_num_subs(ROS_NODES);
|
||||||
|
constant NUM_SERVICES : natural := get_num_services(ROS_NODES);
|
||||||
|
constant NUM_ACTIONS : natural := get_num_actions(ROS_NODES);
|
||||||
|
|
||||||
|
constant ROS_PUBLICATIONS : ROS_TOPIC_ARRAY_TYPE(0 to NUM_PUBS-1) := (
|
||||||
|
others => (
|
||||||
|
node_id => 0,
|
||||||
|
TOPICNAME => gen_user_string(""),
|
||||||
|
TYPENAME => gen_user_string(""),
|
||||||
|
QOS => ROS_QOS_PROFILE_DEFAULT,
|
||||||
|
MAX_SIZE => 0
|
||||||
|
)
|
||||||
|
);
|
||||||
|
|
||||||
|
constant ROS_SUBSCRIPTIONS : ROS_TOPIC_ARRAY_TYPE(0 to NUM_SUBS-1) := (
|
||||||
|
others => (
|
||||||
|
node_id => 0,
|
||||||
|
TOPICNAME => gen_user_string(""),
|
||||||
|
TYPENAME => gen_user_string(""),
|
||||||
|
QOS => ROS_QOS_PROFILE_DEFAULT,
|
||||||
|
MAX_SIZE => 0
|
||||||
|
)
|
||||||
|
);
|
||||||
|
|
||||||
|
constant ROS_SERVICES : ROS_SERVICE_ARRAY_TYPE(0 to NUM_SERVICES-1) := (
|
||||||
|
others => (
|
||||||
|
node_id => 0,
|
||||||
|
SERVICENAME => gen_user_string(""),
|
||||||
|
RQ_TYPENAME => gen_user_string(""),
|
||||||
|
RR_TYPENAME => gen_user_string(""),
|
||||||
|
QOS => ROS_QOS_PROFILE_TRANSIENT,
|
||||||
|
MAX_RQ_SIZE => 0,
|
||||||
|
MAX_RR_SIZE => 0,
|
||||||
|
is_client => FALSE
|
||||||
|
)
|
||||||
|
);
|
||||||
|
|
||||||
|
constant ROS_ACTIONS : ROS_ACTION_ARRAY_TYPE(0 to NUM_ACTIONS-1) := (
|
||||||
|
0 => (
|
||||||
|
node_id => 0,
|
||||||
|
ACTIONNAME => gen_user_string("fibonacci"),
|
||||||
|
GOAL_RQ_TYPENAME => gen_user_string("action_tutorials_interfaces::action::dds_::Fibonacci_SendGoal_Request_"),
|
||||||
|
GOAL_RR_TYPENAME => gen_user_string("action_tutorials_interfaces::action::dds_::Fibonacci_SendGoal_Response_"),
|
||||||
|
RESULT_RQ_TYPENAME => gen_user_string("action_tutorials_interfaces::action::dds_::Fibonacci_GetResult_Request_"),
|
||||||
|
RESULT_RR_TYPENAME => gen_user_string("action_tutorials_interfaces::action::dds_::Fibonacci_GetResult_Response_"),
|
||||||
|
FEEDBACK_TYPENAME => gen_user_string("action_tutorials_interfaces::action::dds_::Fibonacci_FeedbackMessage_"),
|
||||||
|
GOAL_QOS => ROS_QOS_PROFILE_TRANSIENT,
|
||||||
|
RESULT_QOS => ROS_QOS_PROFILE_TRANSIENT,
|
||||||
|
FEEDBACK_QOS => ROS_QOS_PROFILE_DEFAULT,
|
||||||
|
CANCEL_QOS => ROS_QOS_PROFILE_TRANSIENT,
|
||||||
|
MAX_GOAL_RQ_SIZE => G_RQ_MAX_FIBONACCI_SIZE,
|
||||||
|
MAX_GOAL_RR_SIZE => G_RR_MAX_FIBONACCI_SIZE,
|
||||||
|
MAX_RESULT_RQ_SIZE => R_RQ_MAX_FIBONACCI_SIZE,
|
||||||
|
MAX_RESULT_RR_SIZE => R_RR_MAX_FIBONACCI_SIZE,
|
||||||
|
MAX_FEEDBACK_SIZE => F_MAX_FIBONACCI_SIZE,
|
||||||
|
is_client => TRUE,
|
||||||
|
enable_feedback => TRUE
|
||||||
|
)
|
||||||
|
);
|
||||||
|
|
||||||
|
-- Defines sensible RTPS timings for simulation
|
||||||
|
constant SIMULATION_TIMING : boolean := TRUE;
|
||||||
|
end package;
|
||||||
@ -84,6 +84,119 @@ analyze ../example_interfaces/AddTwoInts_ros_srv_client.vhd
|
|||||||
analyze ../example_interfaces/AddTwoInts_ros_srv_server.vhd
|
analyze ../example_interfaces/AddTwoInts_ros_srv_server.vhd
|
||||||
analyze Level_2/L2_Testbench_ROS_Lib3.vhd
|
analyze Level_2/L2_Testbench_ROS_Lib3.vhd
|
||||||
|
|
||||||
|
library Testbench_ROS_Lib4
|
||||||
|
analyze ../../math_pkg.vhd
|
||||||
|
analyze ../../rtps_package.vhd
|
||||||
|
analyze ../ros_package.vhd
|
||||||
|
analyze ../rcl_interfaces/action_msgs/GoalInfo_package.vhd
|
||||||
|
analyze ../rcl_interfaces/action_msgs/GoalStatus_package.vhd
|
||||||
|
analyze ../rcl_interfaces/action_msgs/GoalStatusArray_package.vhd
|
||||||
|
analyze ../rcl_interfaces/action_msgs/CancelGoal_package.vhd
|
||||||
|
analyze ../example_interfaces/Fibonacci_package.vhd
|
||||||
|
analyze Level_2/L2_Testbench_ROS_Lib4_config.vhd
|
||||||
|
analyze ../dds_user_config.vhd
|
||||||
|
analyze ../../rtps_config_package.vhd
|
||||||
|
analyze ../../rtps_test_package.vhd
|
||||||
|
analyze ../ros_config_package.vhd
|
||||||
|
analyze ../../single_port_ram.vhd
|
||||||
|
analyze ../../single_port_ram_Altera.vhd
|
||||||
|
analyze ../../single_port_ram_cfg.vhd
|
||||||
|
analyze ../../dual_port_ram.vhd
|
||||||
|
analyze ../../dual_port_ram_Altera.vhd
|
||||||
|
analyze ../../dual_port_ram_cfg.vhd
|
||||||
|
analyze ../../FWFT_FIFO.vhd
|
||||||
|
analyze ../../FWFT_FIFO_Altera.vhd
|
||||||
|
analyze ../../FWFT_FIFO_cfg.vhd
|
||||||
|
analyze ../../mem_ctrl.vhd
|
||||||
|
analyze ../../dp_mem_ctrl.vhd
|
||||||
|
analyze ../../rtps_handler.vhd
|
||||||
|
analyze ../../rtps_discovery_module.vhd
|
||||||
|
analyze ../../rtps_out.vhd
|
||||||
|
analyze ../../rtps_reader.vhd
|
||||||
|
analyze ../../rtps_writer.vhd
|
||||||
|
analyze ../../dds_writer.vhd
|
||||||
|
analyze ../../dds_reader.vhd
|
||||||
|
analyze ../../key_holder.vhd
|
||||||
|
analyze ../../key_hash_generator.vhd
|
||||||
|
analyze ../../Tests/test_key_holder.vhd
|
||||||
|
analyze ../../Tests/test_key_hash_generator.vhd
|
||||||
|
analyze ../../mult.vhd
|
||||||
|
analyze ../../mult_Altera.vhd
|
||||||
|
analyze ../../mult_cfg.vhd
|
||||||
|
analyze ../ros_time_converter.vhd
|
||||||
|
analyze ../rcl_interfaces/action_msgs/GoalStatusArray_ros_pub.vhd
|
||||||
|
analyze ../rcl_interfaces/action_msgs/GoalStatusArray_ros_sub.vhd
|
||||||
|
analyze ../rcl_interfaces/action_msgs/CancelGoal_ros_srv_server.vhd
|
||||||
|
analyze ../rcl_interfaces/action_msgs/CancelGoal_ros_srv_client.vhd
|
||||||
|
analyze ../ros_static_discovery_writer.vhd
|
||||||
|
analyze ../example_interfaces/Fibonacci_ros_action_goal_srv_server.vhd
|
||||||
|
analyze ../example_interfaces/Fibonacci_ros_action_goal_srv_client.vhd
|
||||||
|
analyze ../example_interfaces/Fibonacci_ros_action_result_srv_server.vhd
|
||||||
|
analyze ../example_interfaces/Fibonacci_ros_action_result_srv_client.vhd
|
||||||
|
analyze ../example_interfaces/Fibonacci_ros_action_feedback_pub.vhd
|
||||||
|
analyze ../example_interfaces/Fibonacci_ros_action_feedback_sub.vhd
|
||||||
|
analyze ../ros_action_server.vhd
|
||||||
|
analyze ../example_interfaces/Fibonacci_ros_action_client.vhd
|
||||||
|
analyze ../example_interfaces/Fibonacci_ros_action_server.vhd
|
||||||
|
analyze Fibonacci.vhd
|
||||||
|
analyze Level_2/L2_Testbench_ROS_Lib4.vhd
|
||||||
|
|
||||||
|
library Testbench_ROS_Lib5
|
||||||
|
analyze ../../math_pkg.vhd
|
||||||
|
analyze ../../rtps_package.vhd
|
||||||
|
analyze ../ros_package.vhd
|
||||||
|
analyze ../rcl_interfaces/action_msgs/GoalInfo_package.vhd
|
||||||
|
analyze ../rcl_interfaces/action_msgs/GoalStatus_package.vhd
|
||||||
|
analyze ../rcl_interfaces/action_msgs/GoalStatusArray_package.vhd
|
||||||
|
analyze ../rcl_interfaces/action_msgs/CancelGoal_package.vhd
|
||||||
|
analyze ../example_interfaces/Fibonacci_package.vhd
|
||||||
|
analyze Level_2/L2_Testbench_ROS_Lib5_config.vhd
|
||||||
|
analyze ../dds_user_config.vhd
|
||||||
|
analyze ../../rtps_config_package.vhd
|
||||||
|
analyze ../../rtps_test_package.vhd
|
||||||
|
analyze ../ros_config_package.vhd
|
||||||
|
analyze ../../single_port_ram.vhd
|
||||||
|
analyze ../../single_port_ram_Altera.vhd
|
||||||
|
analyze ../../single_port_ram_cfg.vhd
|
||||||
|
analyze ../../dual_port_ram.vhd
|
||||||
|
analyze ../../dual_port_ram_Altera.vhd
|
||||||
|
analyze ../../dual_port_ram_cfg.vhd
|
||||||
|
analyze ../../FWFT_FIFO.vhd
|
||||||
|
analyze ../../FWFT_FIFO_Altera.vhd
|
||||||
|
analyze ../../FWFT_FIFO_cfg.vhd
|
||||||
|
analyze ../../mem_ctrl.vhd
|
||||||
|
analyze ../../dp_mem_ctrl.vhd
|
||||||
|
analyze ../../rtps_handler.vhd
|
||||||
|
analyze ../../rtps_discovery_module.vhd
|
||||||
|
analyze ../../rtps_out.vhd
|
||||||
|
analyze ../../rtps_reader.vhd
|
||||||
|
analyze ../../rtps_writer.vhd
|
||||||
|
analyze ../../dds_writer.vhd
|
||||||
|
analyze ../../dds_reader.vhd
|
||||||
|
analyze ../../key_holder.vhd
|
||||||
|
analyze ../../key_hash_generator.vhd
|
||||||
|
analyze ../../Tests/test_key_holder.vhd
|
||||||
|
analyze ../../Tests/test_key_hash_generator.vhd
|
||||||
|
analyze ../../mult.vhd
|
||||||
|
analyze ../../mult_Altera.vhd
|
||||||
|
analyze ../../mult_cfg.vhd
|
||||||
|
analyze ../ros_time_converter.vhd
|
||||||
|
analyze ../rcl_interfaces/action_msgs/GoalStatusArray_ros_pub.vhd
|
||||||
|
analyze ../rcl_interfaces/action_msgs/GoalStatusArray_ros_sub.vhd
|
||||||
|
analyze ../rcl_interfaces/action_msgs/CancelGoal_ros_srv_server.vhd
|
||||||
|
analyze ../rcl_interfaces/action_msgs/CancelGoal_ros_srv_client.vhd
|
||||||
|
analyze ../ros_static_discovery_writer.vhd
|
||||||
|
analyze ../example_interfaces/Fibonacci_ros_action_goal_srv_server.vhd
|
||||||
|
analyze ../example_interfaces/Fibonacci_ros_action_goal_srv_client.vhd
|
||||||
|
analyze ../example_interfaces/Fibonacci_ros_action_result_srv_server.vhd
|
||||||
|
analyze ../example_interfaces/Fibonacci_ros_action_result_srv_client.vhd
|
||||||
|
analyze ../example_interfaces/Fibonacci_ros_action_feedback_pub.vhd
|
||||||
|
analyze ../example_interfaces/Fibonacci_ros_action_feedback_sub.vhd
|
||||||
|
analyze ../ros_action_server.vhd
|
||||||
|
analyze ../example_interfaces/Fibonacci_ros_action_client.vhd
|
||||||
|
analyze ../example_interfaces/Fibonacci_ros_action_server.vhd
|
||||||
|
analyze Level_2/L2_Testbench_ROS_Lib5.vhd
|
||||||
|
|
||||||
library Testbench_ROS_Lib1
|
library Testbench_ROS_Lib1
|
||||||
analyze ../../math_pkg.vhd
|
analyze ../../math_pkg.vhd
|
||||||
analyze ../../rtps_package.vhd
|
analyze ../../rtps_package.vhd
|
||||||
@ -133,6 +246,7 @@ analyze Level_0/L0_ros_action_server_test1.vhd
|
|||||||
analyze Level_0/L0_ros_action_server_test2.vhd
|
analyze Level_0/L0_ros_action_server_test2.vhd
|
||||||
analyze Level_1/L1_Fibonacci_ros_action_test1.vhd
|
analyze Level_1/L1_Fibonacci_ros_action_test1.vhd
|
||||||
analyze Level_1/L1_Fibonacci_ros_action_test2.vhd
|
analyze Level_1/L1_Fibonacci_ros_action_test2.vhd
|
||||||
|
analyze Level_2/L2_Fibonacci_ros_action_test1.vhd
|
||||||
|
|
||||||
|
|
||||||
simulate L1_AddTwoInts_ros_srv_test1
|
simulate L1_AddTwoInts_ros_srv_test1
|
||||||
@ -151,4 +265,5 @@ simulate L1_Fibonacci_ros_action_result_srv_test2
|
|||||||
simulate L0_ros_action_server_test1
|
simulate L0_ros_action_server_test1
|
||||||
simulate L0_ros_action_server_test2
|
simulate L0_ros_action_server_test2
|
||||||
simulate L1_Fibonacci_ros_action_test1
|
simulate L1_Fibonacci_ros_action_test1
|
||||||
simulate L1_Fibonacci_ros_action_test2
|
simulate L1_Fibonacci_ros_action_test2
|
||||||
|
simulate L2_Fibonacci_ros_action_test1
|
||||||
Loading…
Reference in New Issue
Block a user