diff --git a/src/Tests/Level_2/L2_Type1_test1.vhd b/src/Tests/Level_2/L2_Type1_test1.vhd index 782af90..5ea842b 100644 --- a/src/Tests/Level_2/L2_Type1_test1.vhd +++ b/src/Tests/Level_2/L2_Type1_test1.vhd @@ -225,12 +225,37 @@ begin procedure wait_on_data(signal sig : std_logic_vector) is begin - assert (sig'length = STATUS_KIND_WIDTH) severity FAILURE; - - if ((sig and DATA_AVAILABLE_STATUS) = (sig'reverse_range => '0')) then - wait on sig until ((sig and DATA_AVAILABLE_STATUS) = DATA_AVAILABLE_STATUS); + if (not check_mask(sig, DATA_AVAILABLE_STATUS)) then + wait on sig until check_mask(sig, DATA_AVAILABLE_STATUS); end if; end procedure; + + procedure try_read is + begin + loop + start_r <= '1'; + opcode_r <= TAKE_NEXT_SAMPLE; + wait_on_sig(ack_r); + wait until rising_edge(clk); + start_r <= '0'; + wait_on_sig(done_r); + wait for 1 ps; -- Make sure all signals stable + case (return_code_r) is + when RETCODE_OK => + -- DONE + exit; + when RETCODE_NO_DATA => + Log("No Samples", INFO); + Log("Wait on Data Arrival", INFO); + wait_on_data(status_r); + Log("Retry Read", INFO); + when others => + Alert("Unexpected DDS Reader Response", FAILURE); + end case; + wait until rising_edge(clk); + end loop; + end procedure; + begin SetAlertLogName("System - Level 2 - (Type1) - General"); @@ -347,15 +372,7 @@ begin wait until rising_edge(clk); Log("Read Sample (Instance 1 Sample 1)", INFO); - start_r <= '1'; - opcode_r <= TAKE_NEXT_SAMPLE; - wait_on_sig(ack_r); - wait until rising_edge(clk); - start_r <= '0'; - wait_on_sig(done_r); - wait for 1 ps; -- Make sure all signals stable - AlertIf(return_code_r /= RETCODE_OK, "DDS Read Operation Failed", ERROR); - wait until rising_edge(clk); + try_read; wait_on_sig(si_valid_r); wait for 1 ps; -- Make sure all signals stable AlertIf(si_valid_data_r /= '1', "Reader returned no Data", ERROR); @@ -373,15 +390,7 @@ begin wait until rising_edge(clk); Log("Read Sample (Instance 2 Sample 1)", INFO); - start_r <= '1'; - opcode_r <= TAKE_NEXT_SAMPLE; - wait_on_sig(ack_r); - wait until rising_edge(clk); - start_r <= '0'; - wait_on_sig(done_r); - wait for 1 ps; -- Make sure all signals stable - AlertIf(return_code_r /= RETCODE_OK, "DDS Read Operation Failed", ERROR); - wait until rising_edge(clk); + try_read; wait_on_sig(si_valid_r); wait for 1 ps; -- Make sure all signals stable AlertIf(si_valid_data_r /= '1', "Reader returned no Data", ERROR); @@ -399,15 +408,7 @@ begin wait until rising_edge(clk); Log("Read Sample (Instance 1 Sample 2)", INFO); - start_r <= '1'; - opcode_r <= TAKE_NEXT_SAMPLE; - wait_on_sig(ack_r); - wait until rising_edge(clk); - start_r <= '0'; - wait_on_sig(done_r); - wait for 1 ps; -- Make sure all signals stable - AlertIf(return_code_r /= RETCODE_OK, "DDS Read Operation Failed", ERROR); - wait until rising_edge(clk); + try_read; wait_on_sig(si_valid_r); wait for 1 ps; -- Make sure all signals stable AlertIf(si_valid_data_r /= '1', "Reader returned no Data", ERROR); @@ -425,15 +426,7 @@ begin wait until rising_edge(clk); Log("Read Sample (Instance 2 Sample 2)", INFO); - start_r <= '1'; - opcode_r <= TAKE_NEXT_SAMPLE; - wait_on_sig(ack_r); - wait until rising_edge(clk); - start_r <= '0'; - wait_on_sig(done_r); - wait for 1 ps; -- Make sure all signals stable - AlertIf(return_code_r /= RETCODE_OK, "DDS Read Operation Failed", ERROR); - wait until rising_edge(clk); + try_read; wait_on_sig(si_valid_r); wait for 1 ps; -- Make sure all signals stable AlertIf(si_valid_data_r /= '1', "Reader returned no Data", ERROR); @@ -482,15 +475,7 @@ begin wait until rising_edge(clk); Log("Read Sample (Instance 3 Sample 1)", INFO); - start_r <= '1'; - opcode_r <= TAKE_NEXT_SAMPLE; - wait_on_sig(ack_r); - wait until rising_edge(clk); - start_r <= '0'; - wait_on_sig(done_r); - wait for 1 ps; -- Make sure all signals stable - AlertIf(return_code_r /= RETCODE_OK, "DDS Read Operation Failed", ERROR); - wait until rising_edge(clk); + try_read; wait_on_sig(si_valid_r); wait for 1 ps; -- Make sure all signals stable AlertIf(si_valid_data_r /= '1', "Reader returned no Data", ERROR); diff --git a/src/Tests/Level_2/L2_Type1_test2.vhd b/src/Tests/Level_2/L2_Type1_test2.vhd index 10aa2eb..2f68a09 100644 --- a/src/Tests/Level_2/L2_Type1_test2.vhd +++ b/src/Tests/Level_2/L2_Type1_test2.vhd @@ -218,9 +218,7 @@ begin procedure wait_on_data(signal sig : std_logic_vector) is begin - assert (sig'length = STATUS_KIND_WIDTH) severity FAILURE; - - if ((sig and DATA_AVAILABLE_STATUS) = (sig'reverse_range => '0')) then + if (not check_mask(sig, DATA_AVAILABLE_STATUS)) then wait on sig until check_mask(sig, DATA_AVAILABLE_STATUS); end if; end procedure; @@ -323,7 +321,6 @@ begin Log("Wait on Data Arrival", INFO); wait_on_data(status_r); wait until rising_edge(clk); - null; when others => Alert("Unexpected DDS Reader Response", FAILURE); end case; diff --git a/src/Tests/testbench.pro b/src/Tests/testbench.pro index f1aafef..0303958 100644 --- a/src/Tests/testbench.pro +++ b/src/Tests/testbench.pro @@ -9,13 +9,13 @@ analyze ../rtps_config_package.vhd analyze ../rtps_test_package.vhd analyze ../single_port_ram.vhd analyze ../single_port_ram_Altera.vhd -analyze single_port_ram_cfg.vhd +analyze ../single_port_ram_cfg.vhd analyze ../dual_port_ram.vhd analyze ../dual_port_ram_Altera.vhd -analyze dual_port_ram_cfg.vhd +analyze ../dual_port_ram_cfg.vhd analyze ../FWFT_FIFO.vhd analyze ../FWFT_FIFO_Altera.vhd -analyze FWFT_FIFO_cfg.vhd +analyze ../FWFT_FIFO_cfg.vhd analyze ../mem_ctrl.vhd analyze ../dp_mem_ctrl.vhd analyze ../rtps_handler.vhd @@ -77,13 +77,13 @@ analyze ../rtps_config_package.vhd analyze ../rtps_test_package.vhd analyze ../single_port_ram.vhd analyze ../single_port_ram_Altera.vhd -analyze single_port_ram_cfg.vhd +analyze ../single_port_ram_cfg.vhd analyze ../dual_port_ram.vhd analyze ../dual_port_ram_Altera.vhd -analyze dual_port_ram_cfg.vhd +analyze ../dual_port_ram_cfg.vhd analyze ../FWFT_FIFO.vhd analyze ../FWFT_FIFO_Altera.vhd -analyze FWFT_FIFO_cfg.vhd +analyze ../FWFT_FIFO_cfg.vhd analyze ../mem_ctrl.vhd analyze ../dp_mem_ctrl.vhd analyze ../rtps_handler.vhd