diff --git a/src/ros2/example_interfaces/Fibonacci_ros_action_server.vhd b/src/ros2/example_interfaces/Fibonacci_ros_action_server.vhd
index e8ce78a..3bbbe0b 100644
--- a/src/ros2/example_interfaces/Fibonacci_ros_action_server.vhd
+++ b/src/ros2/example_interfaces/Fibonacci_ros_action_server.vhd
@@ -865,7 +865,7 @@ begin
                     -- WRITE
                     when 1 =>
                         -- Memory Operation Guard
-                        if (result_seq_ready = '1' and r_seq_mem_valid_out(to_integer(unsigned(r_index))) = '1') then
+                        if (seq_ready_sig = '1' and r_seq_mem_valid_out(to_integer(unsigned(r_index))) = '1') then
                             seq_addr_sig    <= std_logic_vector(to_unsigned(seq_cnt,R_RR_SEQ_ADDR_WIDTH));
                             seq_wen_sig     <= '1';
                             seq_w_sig       <= r_seq_mem_data_out(to_integer(unsigned(r_index)));