greek64/rtps-fpga
2
1
Fork 0
Code Issues Pull Requests Releases Wiki Activity

Minor declaration & documentation fixes

Browse Source
This commit is contained in:
Greek 2021-11-02 11:29:09 +01:00
parent e33d982182
commit ee67fe9493
4 changed files with 483 additions and 440 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
.gitignore vendored
View File

@ -1,7 +1,6 @@
#Ignore List #Ignore List
/syn/** /syn/**
/sim/** /sim/**
/download/**
*.NPPSESS *.NPPSESS
#Unignore Directories (Needed to unignore files in Subdirectories) #Unignore Directories (Needed to unignore files in Subdirectories)
@ -23,4 +22,8 @@
#Settings File #Settings File
!*.qsf !*.qsf
#QSYS File #QSYS File
!*.qsys !*.qsys
#Delete download from existence
/download
/download/**

884
src/REF.txt
View File

File diff suppressed because it is too large Load Diff

10
src/rtps_builtin_endpoint.vhd
View File

@ -395,12 +395,12 @@ architecture arch of rtps_builtin_endpoint is
alias header_flags : std_logic_vector(7 downto 0) is data_in(23 downto 16); alias header_flags : std_logic_vector(7 downto 0) is data_in(23 downto 16);
alias header_udp_port : std_logic_vector(15 downto 0) is data_in(15 downto 0); alias header_udp_port : std_logic_vector(15 downto 0) is data_in(15 downto 0);
-- RTPS PARAMETER LIST HEADER -- RTPS PARAMETER LIST HEADER
alias parameter_id : std_logic_vector(15 downto 0) is data_in(31 downto 16); alias parameter_id : std_logic_vector(PARAMETER_ID_WIDTH-1 downto 0) is data_in(WORD_WIDTH-1 downto WORD_WIDTH-PARAMETER_ID_WIDTH);
alias parameter_length : std_logic_vector(15 downto 0) is data_in(15 downto 0); alias parameter_length : std_logic_vector(PARAMETER_LENGTH_WIDTH-1 downto 0) is data_in(PARAMETER_LENGTH_WIDTH-1 downto 0);
alias must_understand : std_logic is parameter_id(14); alias must_understand : std_logic is parameter_id(PARAMETER_ID_WIDTH-1);
-- RTPS DATA PAYLOAD HEADER -- RTPS DATA PAYLOAD HEADER
alias representation_id : std_logic_vector(15 downto 0) is data_in(31 downto 16); alias representation_id : std_logic_vector(PAYLOAD_REPRESENTATION_ID_WIDTH-1 downto 0) is data_in(WORD_WIDTH-1 downto WORD_WIDTH-PAYLOAD_REPRESENTATION_ID_WIDTH);
alias representation_options : std_logic_vector(15 downto 0) is data_in(15 downto 0); alias representation_options : std_logic_vector(PAYLOAD_REPRESENTATION_ID_WIDTH-1 downto 0) is data_in(PAYLOAD_REPRESENTATION_OPTIONS_WIDTH-1 downto 0);
-- RTPS SUBMESSAGE FLAGS -- RTPS SUBMESSAGE FLAGS
alias endian_flag : std_logic is flags(0); alias endian_flag : std_logic is flags(0);
alias endian_flag_next : std_logic is flags_next(0); alias endian_flag_next : std_logic is flags_next(0);

22
src/rtps_package.vhd
View File

@ -14,10 +14,12 @@ package rtps_package is
constant UDP_PORT_WIDTH : natural := 16; constant UDP_PORT_WIDTH : natural := 16;
constant IPv4_ADDRESS_WIDTH : natural := 32; constant IPv4_ADDRESS_WIDTH : natural := 32;
constant UDP_HEADER_LENGTH_WIDTH : natural := 16; constant UDP_HEADER_LENGTH_WIDTH : natural := 16;
-- CDR ENCODING WIDTHS -- IDL CDR ENCODING WIDTHS
constant CDR_INT8_WIDTH : natural := 8;
constant CDR_CHAR_WIDTH : natural := 8; constant CDR_CHAR_WIDTH : natural := 8;
constant CDR_OCTET_WIDTH : natural := 8; constant CDR_OCTET_WIDTH : natural := 8;
constant CDR_BOOLEAN_WIDTH : natural := 8; constant CDR_BOOLEAN_WIDTH : natural := 8;
constant CDR_WCHAR_WIDTH : natural := 16;
constant CDR_SHORT_WIDTH : natural := 16; constant CDR_SHORT_WIDTH : natural := 16;
constant CDR_ENUMERATION_SHORT_WIDTH : natural := 16; constant CDR_ENUMERATION_SHORT_WIDTH : natural := 16;
constant CDR_LONG_WIDTH : natural := 32; constant CDR_LONG_WIDTH : natural := 32;
@ -25,7 +27,7 @@ package rtps_package is
constant CDR_ENUMERATION_WIDTH : natural := 32; constant CDR_ENUMERATION_WIDTH : natural := 32;
constant CDR_LONG_LONG_WIDTH : natural := 64; constant CDR_LONG_LONG_WIDTH : natural := 64;
constant CDR_DOUBLE_WIDTH : natural := 64; constant CDR_DOUBLE_WIDTH : natural := 64;
constant CDR_LONG_DOUBLE_WIDTH : natural := 64; constant CDR_LONG_DOUBLE_WIDTH : natural := 128;
-- RTPS -- RTPS
-- NOTE: Widths not defined with a CDR Width are defined as byte arrays (Same Endian representation) -- NOTE: Widths not defined with a CDR Width are defined as byte arrays (Same Endian representation)
constant GUIDPREFIX_WIDTH : natural := 96; constant GUIDPREFIX_WIDTH : natural := 96;
@ -159,16 +161,16 @@ package rtps_package is
constant ANY_SAMPLE_STATE : std_logic_vector(SAMPLE_STATE_KIND_WIDTH-1 downto 0) := x"FFFFFFFF"; constant ANY_SAMPLE_STATE : std_logic_vector(SAMPLE_STATE_KIND_WIDTH-1 downto 0) := x"FFFFFFFF";
-- *VIEW STATE KIND* (DDS) -- *VIEW STATE KIND* (DDS)
constant NEW_VIEW_STATE : std_logic_vector(SAMPLE_STATE_KIND_WIDTH-1 downto 0) := x"00000001"; constant NEW_VIEW_STATE : std_logic_vector(VIEW_STATE_KIND_WIDTH-1 downto 0) := x"00000001";
constant NOT_NEW_VIEW_STATE : std_logic_vector(SAMPLE_STATE_KIND_WIDTH-1 downto 0) := x"00000002"; constant NOT_NEW_VIEW_STATE : std_logic_vector(VIEW_STATE_KIND_WIDTH-1 downto 0) := x"00000002";
constant ANY_VIEW_STATE : std_logic_vector(SAMPLE_STATE_KIND_WIDTH-1 downto 0) := x"FFFFFFFF"; constant ANY_VIEW_STATE : std_logic_vector(VIEW_STATE_KIND_WIDTH-1 downto 0) := x"FFFFFFFF";
-- *INSTANCE STATE KIND* (DDS) -- *INSTANCE STATE KIND* (DDS)
constant ALIVE_INSTANCE_STATE : std_logic_vector(SAMPLE_STATE_KIND_WIDTH-1 downto 0) := x"00000001"; constant ALIVE_INSTANCE_STATE : std_logic_vector(INSTANCE_STATE_KIND_WIDTH-1 downto 0) := x"00000001";
constant NOT_ALIVE_DISPOSED_INSTANCE_STATE : std_logic_vector(SAMPLE_STATE_KIND_WIDTH-1 downto 0) := x"00000002"; constant NOT_ALIVE_DISPOSED_INSTANCE_STATE : std_logic_vector(INSTANCE_STATE_KIND_WIDTH-1 downto 0) := x"00000002";
constant NOT_ALIVE_NO_WRITERS_INSTANCE_STATE : std_logic_vector(SAMPLE_STATE_KIND_WIDTH-1 downto 0) := x"00000004"; constant NOT_ALIVE_NO_WRITERS_INSTANCE_STATE : std_logic_vector(INSTANCE_STATE_KIND_WIDTH-1 downto 0) := x"00000004";
constant NOT_ALIVE_INSTANCE_STATE : std_logic_vector(SAMPLE_STATE_KIND_WIDTH-1 downto 0) := x"00000006"; constant NOT_ALIVE_INSTANCE_STATE : std_logic_vector(INSTANCE_STATE_KIND_WIDTH-1 downto 0) := x"00000006";
constant ANY_INSTANCE_STATE : std_logic_vector(SAMPLE_STATE_KIND_WIDTH-1 downto 0) := x"FFFFFFFF"; constant ANY_INSTANCE_STATE : std_logic_vector(INSTANCE_STATE_KIND_WIDTH-1 downto 0) := x"FFFFFFFF";
-- *SAMPLE REJECTED STATUS KIND* (DDS) -- *SAMPLE REJECTED STATUS KIND* (DDS)
constant NOT_REJECTED : std_logic_vector(CDR_ENUMERATION_WIDTH-1 downto 0) := std_logic_vector(to_unsigned(0,CDR_ENUMERATION_WIDTH)); constant NOT_REJECTED : std_logic_vector(CDR_ENUMERATION_WIDTH-1 downto 0) := std_logic_vector(to_unsigned(0,CDR_ENUMERATION_WIDTH));