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Add/Modify synthesis entities to synthesize test_loopback

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Greek 2021-12-08 15:25:49 +01:00 committed by Greek64
parent 4896929e1b
commit f13d28d811
10 changed files with 293 additions and 238 deletions
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3
src/verbatim_key_hash_generator.vhd
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@ -1,3 +1,6 @@
-- altera vhdl_input_version vhdl_2008
-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
library ieee; library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;
use ieee.numeric_std.all; use ieee.numeric_std.all;

15
syn/DE10-Nano/top.qsf
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@ -50,16 +50,22 @@ set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name SDC_FILE ../top.sdc
set_global_assignment -name VHDL_FILE ../test_top.vhd -hdl_version VHDL_2008 set_global_assignment -name VHDL_FILE ../test_top.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../test_fpga.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/Avalon_MM_wrapper.vhd -hdl_version VHDL_2008 set_global_assignment -name VHDL_FILE ../../src/Avalon_MM_wrapper.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/Tests/Level_2/L2_testbench_Lib4.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/Tests/test_loopback.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../test_fpga.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../dds_reader_syn.vhd -hdl_version VHDL_2008 set_global_assignment -name VHDL_FILE ../dds_reader_syn.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/dds_reader.vhd -hdl_version VHDL_2008 set_global_assignment -name VHDL_FILE ../../src/dds_reader.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../dds_writer_syn.vhd -hdl_version VHDL_2008 set_global_assignment -name VHDL_FILE ../dds_writer_syn.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/dds_writer.vhd -hdl_version VHDL_2008 set_global_assignment -name VHDL_FILE ../../src/dds_writer.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/Tests/test_key_hash_generator.vhd -hdl_version VHDL_2008 set_global_assignment -name VHDL_FILE ../../src/Tests/Type1_config.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/Tests/Type1_writer_wrapper.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/Tests/Type1_reader_wrapper.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/Tests/Type1_key_holder.vhd -hdl_version VHDL_2008 set_global_assignment -name VHDL_FILE ../../src/Tests/Type1_key_holder.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/Tests/Type1_package.vhd -hdl_version VHDL_2008 set_global_assignment -name VHDL_FILE ../../src/Tests/Type1_package.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/verbatim_key_hash_generator.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/key_hash_generator.vhd -hdl_version VHDL_2008 set_global_assignment -name VHDL_FILE ../../src/key_hash_generator.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/key_holder.vhd -hdl_version VHDL_2008 set_global_assignment -name VHDL_FILE ../../src/key_holder.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../rtps_reader_syn.vhd -hdl_version VHDL_2008 set_global_assignment -name VHDL_FILE ../rtps_reader_syn.vhd -hdl_version VHDL_2008
@ -68,16 +74,21 @@ set_global_assignment -name VHDL_FILE ../rtps_writer_syn.vhd -hdl_version VHDL_2
set_global_assignment -name VHDL_FILE ../../src/rtps_writer.vhd -hdl_version VHDL_2008 set_global_assignment -name VHDL_FILE ../../src/rtps_writer.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/rtps_builtin_endpoint.vhd -hdl_version VHDL_2008 set_global_assignment -name VHDL_FILE ../../src/rtps_builtin_endpoint.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/rtps_handler.vhd -hdl_version VHDL_2008 set_global_assignment -name VHDL_FILE ../../src/rtps_handler.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/rtps_out.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../test5.vhd -hdl_version VHDL_2008 set_global_assignment -name VHDL_FILE ../test5.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../test4.vhd -hdl_version VHDL_2008 set_global_assignment -name VHDL_FILE ../test4.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../test3.vhd -hdl_version VHDL_2008 set_global_assignment -name VHDL_FILE ../test3.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../test2.vhd -hdl_version VHDL_2008 set_global_assignment -name VHDL_FILE ../test2.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../test.vhd -hdl_version VHDL_2008 set_global_assignment -name VHDL_FILE ../test.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../test_package.vhd -hdl_version VHDL_2008 set_global_assignment -name VHDL_FILE ../test_package.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/dp_mem_ctrl.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/mem_ctrl.vhd -hdl_version VHDL_2008 set_global_assignment -name VHDL_FILE ../../src/mem_ctrl.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/FWFT_FIFO_cfg.vhd -hdl_version VHDL_2008 set_global_assignment -name VHDL_FILE ../../src/FWFT_FIFO_cfg.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/FWFT_FIFO_Altera.vhd -hdl_version VHDL_2008 set_global_assignment -name VHDL_FILE ../../src/FWFT_FIFO_Altera.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/FWFT_FIFO.vhd -hdl_version VHDL_2008 set_global_assignment -name VHDL_FILE ../../src/FWFT_FIFO.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/dual_port_ram_cfg.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/dual_port_ram_Altera.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/dual_port_ram.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/single_port_ram_cfg.vhd -hdl_version VHDL_2008 set_global_assignment -name VHDL_FILE ../../src/single_port_ram_cfg.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/single_port_ram_Altera.vhd -hdl_version VHDL_2008 set_global_assignment -name VHDL_FILE ../../src/single_port_ram_Altera.vhd -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/single_port_ram.vhd -hdl_version VHDL_2008 set_global_assignment -name VHDL_FILE ../../src/single_port_ram.vhd -hdl_version VHDL_2008

2
syn/dds_reader_syn.vhd
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@ -67,6 +67,7 @@ end entity;
architecture arch of dds_reader_syn is architecture arch of dds_reader_syn is
begin begin
if_gen : if (NUM_READERS > 0) generate
syn_inst : entity work.dds_reader(arch) syn_inst : entity work.dds_reader(arch)
generic map ( generic map (
TIME_BASED_FILTER_QOS => ENDPOINT_TIME_BASED_FILTER_QOS(0), TIME_BASED_FILTER_QOS => ENDPOINT_TIME_BASED_FILTER_QOS(0),
@ -128,5 +129,6 @@ begin
eoc => eoc, eoc => eoc,
status => status status => status
); );
end generate;
end architecture; end architecture;

24
syn/dds_writer_syn.vhd
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@ -40,11 +40,12 @@ entity dds_writer_syn is
start_dds : in std_logic; start_dds : in std_logic;
ack_dds : out std_logic; ack_dds : out std_logic;
opcode_dds : in DDS_WRITER_OPCODE_TYPE; opcode_dds : in DDS_WRITER_OPCODE_TYPE;
instance_handle_dds : in INSTANCE_HANDLE_TYPE; instance_handle_in_dds : in INSTANCE_HANDLE_TYPE;
source_ts_dds : in TIME_TYPE; source_ts_dds : in TIME_TYPE;
max_wait_dds : in DURATION_TYPE; max_wait_dds : in DURATION_TYPE;
done_dds : out std_logic; done_dds : out std_logic;
return_code_dds : out std_logic_vector(RETURN_CODE_WIDTH-1 downto 0); return_code_dds : out std_logic_vector(RETURN_CODE_WIDTH-1 downto 0);
instance_handle_out_dds : out INSTANCE_HANDLE_TYPE;
ready_in_dds : out std_logic; ready_in_dds : out std_logic;
valid_in_dds : in std_logic; valid_in_dds : in std_logic;
data_in_dds : in std_logic_vector(WORD_WIDTH-1 downto 0); data_in_dds : in std_logic_vector(WORD_WIDTH-1 downto 0);
@ -61,16 +62,17 @@ end entity;
architecture arch of dds_writer_syn is architecture arch of dds_writer_syn is
begin begin
if_gen : if (NUM_WRITERS > 0) generate
syn_inst : entity work.dds_writer(arch) syn_inst : entity work.dds_writer(arch)
generic map ( generic map (
HISTORY_QOS => ENDPOINT_HISTORY_QOS(1), HISTORY_QOS => ENDPOINT_HISTORY_QOS(NUM_READERS),
DEADLINE_QOS => ENDPOINT_DEADLINE_QOS(1), DEADLINE_QOS => ENDPOINT_DEADLINE_QOS(NUM_READERS),
LIFESPAN_QOS => ENDPOINT_LIFESPAN_QOS(1), LIFESPAN_QOS => ENDPOINT_LIFESPAN_QOS(NUM_READERS),
LEASE_DURATION => ENDPOINT_LEASE_DURATION(1), LEASE_DURATION => ENDPOINT_LEASE_DURATION(NUM_READERS),
WITH_KEY => ENDPOINT_WITH_KEY(1), WITH_KEY => ENDPOINT_WITH_KEY(NUM_READERS),
MAX_SAMPLES => ENDPOINT_MAX_SAMPLES(1), MAX_SAMPLES => ENDPOINT_MAX_SAMPLES(NUM_READERS),
MAX_INSTANCES => ENDPOINT_MAX_INSTANCES(1), MAX_INSTANCES => ENDPOINT_MAX_INSTANCES(NUM_READERS),
MAX_SAMPLES_PER_INSTANCE => ENDPOINT_MAX_SAMPLES_PER_INSTANCE(1), MAX_SAMPLES_PER_INSTANCE => ENDPOINT_MAX_SAMPLES_PER_INSTANCE(NUM_READERS),
PAYLOAD_FRAME_SIZE => MAX_TYPE1_SIZE PAYLOAD_FRAME_SIZE => MAX_TYPE1_SIZE
) )
port map ( port map (
@ -97,11 +99,12 @@ begin
start_dds => start_dds, start_dds => start_dds,
ack_dds => ack_dds, ack_dds => ack_dds,
opcode_dds => opcode_dds, opcode_dds => opcode_dds,
instance_handle_dds => instance_handle_dds, instance_handle_in_dds => instance_handle_in_dds,
source_ts_dds => source_ts_dds, source_ts_dds => source_ts_dds,
max_wait_dds => max_wait_dds, max_wait_dds => max_wait_dds,
done_dds => done_dds, done_dds => done_dds,
return_code_dds => return_code_dds, return_code_dds => return_code_dds,
instance_handle_out_dds => instance_handle_out_dds,
ready_in_dds => ready_in_dds, ready_in_dds => ready_in_dds,
valid_in_dds => valid_in_dds, valid_in_dds => valid_in_dds,
data_in_dds => data_in_dds, data_in_dds => data_in_dds,
@ -112,5 +115,6 @@ begin
last_word_out_dds => last_word_out_dds, last_word_out_dds => last_word_out_dds,
status => status status => status
); );
end generate;
end architecture; end architecture;

2
syn/rtps_reader_syn.vhd
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@ -47,6 +47,7 @@ end entity;
architecture arch of rtps_reader_syn is architecture arch of rtps_reader_syn is
begin begin
if_gen : if (NUM_READERS > 0) generate
syn_inst : entity work.rtps_reader(arch) syn_inst : entity work.rtps_reader(arch)
generic map ( generic map (
ENTITYID => ENTITYID(0), ENTITYID => ENTITYID(0),
@ -84,5 +85,6 @@ begin
ready_out_hc => ready_out_hc, ready_out_hc => ready_out_hc,
last_word_out_hc => last_word_out_hc last_word_out_hc => last_word_out_hc
); );
end generate;
end architecture; end architecture;

26
syn/rtps_writer_syn.vhd
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@ -57,20 +57,21 @@ end entity;
architecture arch of rtps_writer_syn is architecture arch of rtps_writer_syn is
begin begin
if_gen : if (NUM_WRITERS > 0) generate
syn_inst : entity work.rtps_writer(arch) syn_inst : entity work.rtps_writer(arch)
generic map ( generic map (
RELIABILITY_QOS => ENDPOINT_RELIABILITY_QOS(1), RELIABILITY_QOS => ENDPOINT_RELIABILITY_QOS(NUM_READERS),
LIVELINESS_QOS => ENDPOINT_LIVELINESS_QOS(1), LIVELINESS_QOS => ENDPOINT_LIVELINESS_QOS(NUM_READERS),
DURABILITY_QOS => ENDPOINT_DURABILITY_QOS(1), DURABILITY_QOS => ENDPOINT_DURABILITY_QOS(NUM_READERS),
DESTINATION_ORDER_QOS => ENDPOINT_DESTINATION_ORDER_QOS(1), DESTINATION_ORDER_QOS => ENDPOINT_DESTINATION_ORDER_QOS(NUM_READERS),
ACKNACK_RESPONSE_DELAY => ENDPOINT_ACKNACK_RESPONSE_DELAY(1), ACKNACK_RESPONSE_DELAY => ENDPOINT_ACKNACK_RESPONSE_DELAY(NUM_READERS),
ACKNACK_SUPPRESSION_DELAY => ENDPOINT_ACKNACK_SUPPRESSION_DELAY(1), ACKNACK_SUPPRESSION_DELAY => ENDPOINT_ACKNACK_SUPPRESSION_DELAY(NUM_READERS),
LEASE_DURATION => ENDPOINT_LEASE_DURATION(1), LEASE_DURATION => ENDPOINT_LEASE_DURATION(NUM_READERS),
HEARTBEAT_PERIOD => ENDPOINT_HEARTBEAT_PERIOD(1), HEARTBEAT_PERIOD => ENDPOINT_HEARTBEAT_PERIOD(NUM_READERS),
ENTITYID => ENTITYID(1), ENTITYID => ENTITYID(NUM_READERS),
WITH_KEY => ENDPOINT_WITH_KEY(1), WITH_KEY => ENDPOINT_WITH_KEY(NUM_READERS),
PUSH_MODE => ENDPOINT_PUSH_MODE(1), PUSH_MODE => ENDPOINT_PUSH_MODE(NUM_READERS),
INLINE_QOS => gen_inline_qos(1) INLINE_QOS => gen_inline_qos(NUM_READERS)
) )
port map ( port map (
-- SYSTEM -- SYSTEM
@ -108,5 +109,6 @@ begin
cc_source_timestamp => cc_source_timestamp, cc_source_timestamp => cc_source_timestamp,
cc_seq_nr => cc_seq_nr cc_seq_nr => cc_seq_nr
); );
end generate;
end architecture; end architecture;

45
syn/syn_config.vhd
View File

@ -1,6 +1,3 @@
-- altera vhdl_input_version vhdl_2008
-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
library ieee; library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;
use ieee.numeric_std.all; use ieee.numeric_std.all;
@ -10,11 +7,17 @@ use work.rtps_package.all;
package user_config is package user_config is
--*****USER CONFIG***** --*****USER CONFIG*****
-- NOTE: All strings have to be padded to 256 characters -- NOTE: All strings have to be padded to 256 characters
-- Unicast IPv4 Address used by all RTPS Entities [Default 192.168.0.80] -- Period of system clock
constant DEFAULT_IPv4_ADDRESS : std_logic_vector(IPv4_ADDRESS_WIDTH-1 downto 0) := x"C0A80080"; constant CLOCK_PERIOD : time := 20 ns; -- 50 MHz
-- Maximum number of supported remote Participants (Affects generated Memory Size)
constant MAX_REMOTE_PARTICIPANTS : natural := 50;
-- Maximum number of supported remote Endpoints (Affects generated Memory Size)
constant MAX_REMOTE_ENDPOINTS : natural := 50;
-- Unicast IPv4 Address used by all RTPS Entities [Default 192.168.0.90]
constant DEFAULT_IPv4_ADDRESS : std_logic_vector(IPv4_ADDRESS_WIDTH-1 downto 0) := x"C0A8005A";
-- Number of RTPS Writer Endpoints -- Number of RTPS Writer Endpoints
constant NUM_WRITERS : natural := 1; constant NUM_WRITERS : natural := 1;
-- Number of RTPS Reader Endpoints -- Number of RTPS Reader Endpoints
@ -36,7 +39,7 @@ package user_config is
-- D3 Value of Default Port Generation (see DDSI-RTPS 2.3 Section 9.6.1) -- D3 Value of Default Port Generation (see DDSI-RTPS 2.3 Section 9.6.1)
constant PORT_CONFIG_D3 : natural := 11; constant PORT_CONFIG_D3 : natural := 11;
-- MAC Address of underlying network stack (Used to generate GUIDs) -- MAC Address of underlying network stack (Used to generate GUIDs)
constant MAC_ADDRESS : std_logic_vector(47 downto 0) := x"97917E0BA8CF"; constant MAC_ADDRESS : std_logic_vector(47 downto 0) := x"924DD9E79DE6";
-- Domain ID -- Domain ID
constant USER_DOMAIN_ID : natural := 1; constant USER_DOMAIN_ID : natural := 1;
-- Domain TAG -- Domain TAG
@ -48,12 +51,12 @@ package user_config is
-- Array denoting which mode the Endpoints are operating with -- Array denoting which mode the Endpoints are operating with
constant ENDPOINT_PUSH_MODE : USER_BOOLEAN_ARRAY_TYPE(0 to NUM_ENDPOINTS-1) := (others => TRUE); constant ENDPOINT_PUSH_MODE : USER_BOOLEAN_ARRAY_TYPE(0 to NUM_ENDPOINTS-1) := (others => TRUE);
-- Array mapping Topic Names to Endpoints -- Array mapping Topic Names to Endpoints
constant ENDPOINT_TOPIC_STRING : USER_STRING_ARRAY_TYPE(0 to NUM_ENDPOINTS-1) := (others => "Placeholder" & (12 to 256 => NUL)); constant ENDPOINT_TOPIC_STRING : USER_STRING_ARRAY_TYPE(0 to NUM_ENDPOINTS-1) := (others => "Topic1" & (7 to 256 => NUL));
-- Array mapping Type Names to Endpoints -- Array mapping Type Names to Endpoints
constant ENDPOINT_TYPE_STRING : USER_STRING_ARRAY_TYPE(0 to NUM_ENDPOINTS-1) := (others => "Placeholder" & (12 to 256 => NUL)); constant ENDPOINT_TYPE_STRING : USER_STRING_ARRAY_TYPE(0 to NUM_ENDPOINTS-1) := (others => "Type1" & (6 to 256 => NUL));
-- *TIMING CHARACTERISTICS* -- *TIMING CHARACTERISTICS*
-- Timing Characteristics for Participant -- Timing Characteristics for Participant
constant PARTICIPANT_ANNOUNCEMENT_PERIOD : DURATION_TYPE := gen_duration(30,0); -- 30 s constant PARTICIPANT_ANNOUNCEMENT_PERIOD : DURATION_TYPE := gen_duration(10,0); -- 10 s
constant PARTICIPANT_LEASE_DURATION : DURATION_TYPE := DEFAULT_PARTICIPANT_LEASE_DURATION; constant PARTICIPANT_LEASE_DURATION : DURATION_TYPE := DEFAULT_PARTICIPANT_LEASE_DURATION;
-- Denotes how much faster then the deadline/period we schedule in order to account for transport delay. -- Denotes how much faster then the deadline/period we schedule in order to account for transport delay.
constant DURATION_DELTA : DURATION_TYPE := gen_duration(0, 100*(10**6)); -- 100 ms constant DURATION_DELTA : DURATION_TYPE := gen_duration(0, 100*(10**6)); -- 100 ms
@ -70,10 +73,10 @@ package user_config is
constant ENDPOINT_ACKNACK_RESPONSE_DELAY : USER_DURATION_ARRAY_TYPE(0 to NUM_ENDPOINTS-1) := (others => gen_duration(0,200*(10**6))); -- 200 ms constant ENDPOINT_ACKNACK_RESPONSE_DELAY : USER_DURATION_ARRAY_TYPE(0 to NUM_ENDPOINTS-1) := (others => gen_duration(0,200*(10**6))); -- 200 ms
constant ENDPOINT_ACKNACK_SUPPRESSION_DELAY : USER_DURATION_ARRAY_TYPE(0 to NUM_ENDPOINTS-1) := (others => gen_duration(0,0)); constant ENDPOINT_ACKNACK_SUPPRESSION_DELAY : USER_DURATION_ARRAY_TYPE(0 to NUM_ENDPOINTS-1) := (others => gen_duration(0,0));
--***ENDPOINT DDS QOS*** --***ENDPOINT DDS QOS***
-- Array mapping DURABILITY QoS to Endpoints -- Array mapping DURABILITY QoS to Endpoints
constant ENDPOINT_DURABILITY_QOS : USER_ENUMERATION_ARRAY_TYPE(0 to NUM_ENDPOINTS-1) := (others => DEFAULT_DURABILITY_QOS); constant ENDPOINT_DURABILITY_QOS : USER_ENUMERATION_ARRAY_TYPE(0 to NUM_ENDPOINTS-1) := (others => TRANSIENT_LOCAL_DURABILITY_QOS);
-- Array mapping DURABILITY SERVICE QoS to Endpoints
constant ENDPOINT_DURABILITY_SERVICE_CLEANUP_DELAY : USER_DURATION_ARRAY_TYPE(0 to NUM_ENDPOINTS-1) := (others => DEFAULT_DURABILITY_SERVICE_CLEANUP_DELAY); constant ENDPOINT_DURABILITY_SERVICE_CLEANUP_DELAY : USER_DURATION_ARRAY_TYPE(0 to NUM_ENDPOINTS-1) := (others => DEFAULT_DURABILITY_SERVICE_CLEANUP_DELAY);
constant ENDPOINT_DURABILITY_SERVICE_HISTORY : USER_LONG_ARRAY_TYPE(0 to NUM_ENDPOINTS-1) := (others => DEFAULT_DURABILITY_SERVICE_HISTORY); constant ENDPOINT_DURABILITY_SERVICE_HISTORY : USER_LONG_ARRAY_TYPE(0 to NUM_ENDPOINTS-1) := (others => DEFAULT_DURABILITY_SERVICE_HISTORY);
constant ENDPOINT_DURABILITY_SERVICE_HISTORY_DEPTH : USER_LONG_ARRAY_TYPE(0 to NUM_ENDPOINTS-1) := (others => DEFAULT_DURABILITY_SERVICE_HISTORY_DEPTH); constant ENDPOINT_DURABILITY_SERVICE_HISTORY_DEPTH : USER_LONG_ARRAY_TYPE(0 to NUM_ENDPOINTS-1) := (others => DEFAULT_DURABILITY_SERVICE_HISTORY_DEPTH);
@ -85,7 +88,7 @@ package user_config is
constant ENDPOINT_COHERENT_ACCESS : USER_BOOLEAN_ARRAY_TYPE(0 to NUM_ENDPOINTS-1) := (others => DEFAULT_COHERENT_ACCESS); constant ENDPOINT_COHERENT_ACCESS : USER_BOOLEAN_ARRAY_TYPE(0 to NUM_ENDPOINTS-1) := (others => DEFAULT_COHERENT_ACCESS);
constant ENDPOINT_ORDERED_ACCESS : USER_BOOLEAN_ARRAY_TYPE(0 to NUM_ENDPOINTS-1) := (others => DEFAULT_ORDERED_ACCESS); constant ENDPOINT_ORDERED_ACCESS : USER_BOOLEAN_ARRAY_TYPE(0 to NUM_ENDPOINTS-1) := (others => DEFAULT_ORDERED_ACCESS);
-- Array mapping DEADLINE QoS to Endpoints -- Array mapping DEADLINE QoS to Endpoints
constant ENDPOINT_DEADLINE_QOS : USER_DURATION_ARRAY_TYPE(0 to NUM_ENDPOINTS-1) := (others => gen_duration(60,0)); -- 60s constant ENDPOINT_DEADLINE_QOS : USER_DURATION_ARRAY_TYPE(0 to NUM_ENDPOINTS-1) := (others => DEFAULT_DEADLINE_QOS);
-- Array mapping LATENCY_BUDGET QoS to Endpoints -- Array mapping LATENCY_BUDGET QoS to Endpoints
constant ENDPOINT_LATENCY_BUDGET_QOS : USER_DURATION_ARRAY_TYPE(0 to NUM_ENDPOINTS-1) := (others => DEFAULT_LATENCY_BUDGET_QOS); constant ENDPOINT_LATENCY_BUDGET_QOS : USER_DURATION_ARRAY_TYPE(0 to NUM_ENDPOINTS-1) := (others => DEFAULT_LATENCY_BUDGET_QOS);
-- Array mapping OWNERSHIP QoS to Endpoints -- Array mapping OWNERSHIP QoS to Endpoints
@ -94,9 +97,9 @@ package user_config is
constant ENDPOINT_OWNERSHIP_STRENGTH_QOS : USER_LONG_ARRAY_TYPE(0 to NUM_ENDPOINTS-1) := (others => DEFAULT_OWNERSHIP_STRENGTH_QOS); constant ENDPOINT_OWNERSHIP_STRENGTH_QOS : USER_LONG_ARRAY_TYPE(0 to NUM_ENDPOINTS-1) := (others => DEFAULT_OWNERSHIP_STRENGTH_QOS);
-- Array mapping LIVELINESS QoS to Endpoints -- Array mapping LIVELINESS QoS to Endpoints
constant ENDPOINT_LIVELINESS_QOS : USER_ENUMERATION_ARRAY_TYPE(0 to NUM_ENDPOINTS-1) := (others => DEFAULT_LIVELINESS_QOS); constant ENDPOINT_LIVELINESS_QOS : USER_ENUMERATION_ARRAY_TYPE(0 to NUM_ENDPOINTS-1) := (others => DEFAULT_LIVELINESS_QOS);
constant ENDPOINT_LEASE_DURATION : USER_DURATION_ARRAY_TYPE(0 to NUM_ENDPOINTS-1) := (others => gen_duration(100,0)); -- 100s constant ENDPOINT_LEASE_DURATION : USER_DURATION_ARRAY_TYPE(0 to NUM_ENDPOINTS-1) := (others => DEFAULT_LEASE_DURATION);
-- Array mapping TIME_BASED_FILTER QoS to Endpoints (Only relevant to Readers) -- Array mapping TIME_BASED_FILTER QoS to Endpoints (Only relevant to Readers)
constant ENDPOINT_TIME_BASED_FILTER_QOS : USER_DURATION_ARRAY_TYPE(0 to NUM_ENDPOINTS-1) := (others => gen_duration(1,0)); -- 1s constant ENDPOINT_TIME_BASED_FILTER_QOS : USER_DURATION_ARRAY_TYPE(0 to NUM_ENDPOINTS-1) := (others => DEFAULT_TIME_BASED_FILTER_QOS);
-- XXX: PARTITION QoS Ignored -- XXX: PARTITION QoS Ignored
-- Array mapping RELIABILITY QoS to Endpoints -- Array mapping RELIABILITY QoS to Endpoints
constant ENDPOINT_RELIABILITY_QOS : USER_ENUMERATION_ARRAY_TYPE(0 to NUM_ENDPOINTS-1) := (others => DEFAULT_RELIABILITY_QOS); constant ENDPOINT_RELIABILITY_QOS : USER_ENUMERATION_ARRAY_TYPE(0 to NUM_ENDPOINTS-1) := (others => DEFAULT_RELIABILITY_QOS);
@ -105,15 +108,15 @@ package user_config is
-- Array mapping TRANSPORT_PRIORITY QoS to Endpoints (Only relevant to Writers) -- Array mapping TRANSPORT_PRIORITY QoS to Endpoints (Only relevant to Writers)
constant ENDPOINT_TRANSPORT_PRIORITY_QOS : USER_LONG_ARRAY_TYPE(0 to NUM_ENDPOINTS-1) := (others => DEFAULT_TRANSPORT_PRIORITY_QOS); constant ENDPOINT_TRANSPORT_PRIORITY_QOS : USER_LONG_ARRAY_TYPE(0 to NUM_ENDPOINTS-1) := (others => DEFAULT_TRANSPORT_PRIORITY_QOS);
-- Array mapping LIFESPAN QoS to Endpoints (Only relevant to Writers) -- Array mapping LIFESPAN QoS to Endpoints (Only relevant to Writers)
constant ENDPOINT_LIFESPAN_QOS : USER_DURATION_ARRAY_TYPE(0 to NUM_ENDPOINTS-1) := (others => gen_duration(40,0)); -- 40s constant ENDPOINT_LIFESPAN_QOS : USER_DURATION_ARRAY_TYPE(0 to NUM_ENDPOINTS-1) := (others => DEFAULT_LIFESPAN_QOS);
-- Array mapping DESTINATION_ORDER QoS to Endpoints -- Array mapping DESTINATION_ORDER QoS to Endpoints
constant ENDPOINT_DESTINATION_ORDER_QOS : USER_ENUMERATION_ARRAY_TYPE(0 to NUM_ENDPOINTS-1) := (others => DEFAULT_DESTINATION_ORDER_QOS); constant ENDPOINT_DESTINATION_ORDER_QOS : USER_ENUMERATION_ARRAY_TYPE(0 to NUM_ENDPOINTS-1) := (others => DEFAULT_DESTINATION_ORDER_QOS);
-- Array mapping HISTORY QoS to Endpoints -- Array mapping HISTORY QoS to Endpoints
constant ENDPOINT_HISTORY_QOS : USER_ENUMERATION_ARRAY_TYPE(0 to NUM_ENDPOINTS-1) := (others => DEFAULT_HISTORY_QOS); constant ENDPOINT_HISTORY_QOS : USER_ENUMERATION_ARRAY_TYPE(0 to NUM_ENDPOINTS-1) := (others => DEFAULT_HISTORY_QOS);
constant ENDPOINT_HISTORY_DEPTH : USER_LONG_ARRAY_TYPE(0 to NUM_ENDPOINTS-1) := (others => DEFAULT_HISTORY_DEPTH); constant ENDPOINT_HISTORY_DEPTH : USER_LONG_ARRAY_TYPE(0 to NUM_ENDPOINTS-1) := (others => std_logic_vector(to_unsigned(5, CDR_LONG_WIDTH)));
-- Array mapping RESOURCE_LIMITS QoS to Endpoints -- Array mapping RESOURCE_LIMITS QoS to Endpoints
constant ENDPOINT_MAX_SAMPLES : USER_LONG_ARRAY_TYPE(0 to NUM_ENDPOINTS-1) := (others => std_logic_vector(to_unsigned(50, CDR_LONG_WIDTH))); constant ENDPOINT_MAX_SAMPLES : USER_LONG_ARRAY_TYPE(0 to NUM_ENDPOINTS-1) := (others => std_logic_vector(to_unsigned(20, CDR_LONG_WIDTH)));
constant ENDPOINT_MAX_INSTANCES : USER_LONG_ARRAY_TYPE(0 to NUM_ENDPOINTS-1) := (others => std_logic_vector(to_unsigned(50, CDR_LONG_WIDTH))); constant ENDPOINT_MAX_INSTANCES : USER_LONG_ARRAY_TYPE(0 to NUM_ENDPOINTS-1) := (others => std_logic_vector(to_unsigned(5, CDR_LONG_WIDTH)));
constant ENDPOINT_MAX_SAMPLES_PER_INSTANCE : USER_LONG_ARRAY_TYPE(0 to NUM_ENDPOINTS-1) := (others => DEFAULT_MAX_SAMPLES_PER_INSTANCE); constant ENDPOINT_MAX_SAMPLES_PER_INSTANCE : USER_LONG_ARRAY_TYPE(0 to NUM_ENDPOINTS-1) := (others => DEFAULT_MAX_SAMPLES_PER_INSTANCE);
-- XXX: ENTITY_FACTORY QoS Ignored -- XXX: ENTITY_FACTORY QoS Ignored
-- Array mapping WRITER_DATA_LIFECYCLE QoS to Endpoints (Only relevant to Writers) -- Array mapping WRITER_DATA_LIFECYCLE QoS to Endpoints (Only relevant to Writers)
@ -122,10 +125,6 @@ package user_config is
constant ENDPOINT_AUTOPURGE_NOWRITER_SAMPLES_DELAY : USER_DURATION_ARRAY_TYPE(0 to NUM_ENDPOINTS-1) := (others => DEFAULT_AUTOPURGE_NOWRITER_SAMPLES_DELAY); constant ENDPOINT_AUTOPURGE_NOWRITER_SAMPLES_DELAY : USER_DURATION_ARRAY_TYPE(0 to NUM_ENDPOINTS-1) := (others => DEFAULT_AUTOPURGE_NOWRITER_SAMPLES_DELAY);
constant ENDPOINT_AUTOPURGE_DISPOSED_SAMPLES_DELAY : USER_DURATION_ARRAY_TYPE(0 to NUM_ENDPOINTS-1) := (others => DEFAULT_AUTOPURGE_DISPOSED_SAMPLES_DELAY); constant ENDPOINT_AUTOPURGE_DISPOSED_SAMPLES_DELAY : USER_DURATION_ARRAY_TYPE(0 to NUM_ENDPOINTS-1) := (others => DEFAULT_AUTOPURGE_DISPOSED_SAMPLES_DELAY);
-- NOTE: The buffer will not only store participants, but also endpoint data
-- Used to determine the size of the builtin endpoint buffer
constant MAX_REMOTE_PARTICIPANTS : natural := 50;
-- Set to TRUE for Simulation Testing (Extra Code generated) -- Set to TRUE for Simulation Testing (Extra Code generated)
constant SIMULATION_FLAG : boolean := FALSE; constant SIMULATION_FLAG : boolean := FALSE;
end package; end package;

2
syn/test_fpga.vhd
View File

@ -101,7 +101,7 @@ begin
-- Output Guard -- Output Guard
if (full = '0') then if (full = '0') then
write <= '1'; write <= '1';
data_out <= RES_IPv4_ADDRESS; data_out <= src_addr;
stage_next <= UDP_PORTS_OUT; stage_next <= UDP_PORTS_OUT;
end if; end if;

22
syn/test_top.vhd
View File

@ -6,6 +6,7 @@ use ieee.std_logic_1164.all;
use ieee.numeric_std.all; use ieee.numeric_std.all;
use work.rtps_package.all; use work.rtps_package.all;
use work.rtps_config_package.all;
entity test_top is entity test_top is
port ( port (
@ -26,6 +27,7 @@ architecture arch of test_top is
signal full_fi_wr, write_wr_fi, empty_fo_wr, read_wr_fo, empty_fi_test, read_test_fi, full_fo_test, write_test_fo : std_logic; signal full_fi_wr, write_wr_fi, empty_fo_wr, read_wr_fo, empty_fi_test, read_test_fi, full_fo_test, write_test_fo : std_logic;
signal data_wr_fi, data_fo_wr, data_fi_test, data_test_fo : std_logic_vector(WORD_WIDTH-1 downto 0); signal data_wr_fi, data_fo_wr, data_fi_test, data_test_fo : std_logic_vector(WORD_WIDTH-1 downto 0);
signal time : TIME_TYPE;
begin begin
@ -50,7 +52,7 @@ begin
FIFO_IN_inst : configuration work.FWFT_FIFO_cfg FIFO_IN_inst : configuration work.FWFT_FIFO_cfg
generic map ( generic map (
FIFO_DEPTH => 16384, FIFO_DEPTH => 16384,
DATA_WIDTH => 32 DATA_WIDTH => WORD_WIDTH
) )
port map ( port map (
clk => clk, clk => clk,
@ -67,7 +69,7 @@ begin
FIFO_OUT_inst : configuration work.FWFT_FIFO_cfg FIFO_OUT_inst : configuration work.FWFT_FIFO_cfg
generic map ( generic map (
FIFO_DEPTH => 16384, FIFO_DEPTH => 16384,
DATA_WIDTH => 32 DATA_WIDTH => WORD_WIDTH
) )
port map ( port map (
clk => clk, clk => clk,
@ -81,17 +83,31 @@ begin
free => open free => open
); );
test_fpga_inst : entity work.test_fpga(arch) dds_loopback_inst : entity work.L2_Testbench_Lib4(arch)
port map ( port map (
-- SYSTEM
clk => clk, clk => clk,
reset => reset, reset => reset,
time => time,
-- INPUT
empty => empty_fi_test, empty => empty_fi_test,
read => read_test_fi, read => read_test_fi,
data_in => data_fi_test, data_in => data_fi_test,
-- OUTPUT
full => full_fo_test, full => full_fo_test,
write => write_test_fo, write => write_test_fo,
data_out => data_test_fo data_out => data_test_fo
); );
time_prc : process(clk)
begin
if rising_edge(clk) then
if (reset = '1') then
time <= TIME_ZERO;
else
time <= time + CLOCK_DURATION;
end if;
end if;
end process;
end architecture; end architecture;

16
syn/top.sdc Normal file
View File

@ -0,0 +1,16 @@
#**************************************************************
# Time Information
#**************************************************************
set_time_format -unit ns -decimal_places 3
#**************************************************************
# Create Clock
#**************************************************************
#100 MHz
#create_clock -name {clk} -period 10.000 -waveform { 0.000 5.000 } [get_ports { clk }]
# 50 MHz
create_clock -name {clk} -period 20.000 -waveform { 0.000 10.000 } [get_ports { clk }]