Add/Modify synthesis entities to synthesize AddTwoInts_srv_server
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@ -10,9 +10,6 @@ use work.ros_config.all;
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use work.rtps_package.all;
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use work.rtps_package.all;
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use work.user_config.all;
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use work.user_config.all;
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use work.rtps_config_package.all;
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use work.rtps_config_package.all;
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use work.rtps_test_package.all;
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entity L2_Testbench_ROS_Lib2 is
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entity L2_Testbench_ROS_Lib2 is
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port (
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port (
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@ -50,9 +50,13 @@ set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
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set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
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set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
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set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
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set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
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set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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set_global_assignment -name VHDL_FILE ../test6.vhd -hdl_version VHDL_2008
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set_global_assignment -name SDC_FILE ../top.sdc
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set_global_assignment -name SDC_FILE ../top.sdc
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set_global_assignment -name VHDL_FILE ../test_top.vhd -hdl_version VHDL_2008
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set_global_assignment -name VHDL_FILE ../test_top.vhd -hdl_version VHDL_2008
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set_global_assignment -name VHDL_FILE ../../src/ros2/Tests/Level_2/L2_Testbench_ROS_Lib2.vhd -hdl_version VHDL_2008
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set_global_assignment -name VHDL_FILE ../../src/ros2/example_interfaces/AddTwoInts_srv_server.vhd -hdl_version VHDL_2008
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set_global_assignment -name VHDL_FILE ../../src/ros2/example_interfaces/AddTwoInts_srv_client.vhd -hdl_version VHDL_2008
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set_global_assignment -name VHDL_FILE ../../src/ros2/Tests/AddTwoInts.vhd -hdl_version VHDL_2008
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set_global_assignment -name VHDL_FILE ../../src/ros2/ros_static_discovery_writer.vhd -hdl_version VHDL_2008
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set_global_assignment -name VHDL_FILE ../../src/Avalon_MM_wrapper.vhd -hdl_version VHDL_2008
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set_global_assignment -name VHDL_FILE ../../src/Avalon_MM_wrapper.vhd -hdl_version VHDL_2008
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set_global_assignment -name VHDL_FILE ../../src/Tests/Level_2/L2_testbench_Lib4.vhd -hdl_version VHDL_2008
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set_global_assignment -name VHDL_FILE ../../src/Tests/Level_2/L2_testbench_Lib4.vhd -hdl_version VHDL_2008
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set_global_assignment -name VHDL_FILE ../../src/Tests/test_loopback.vhd -hdl_version VHDL_2008
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set_global_assignment -name VHDL_FILE ../../src/Tests/test_loopback.vhd -hdl_version VHDL_2008
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@ -76,6 +80,7 @@ set_global_assignment -name VHDL_FILE ../../src/rtps_writer.vhd -hdl_version VHD
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set_global_assignment -name VHDL_FILE ../../src/rtps_discovery_module.vhd -hdl_version VHDL_2008
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set_global_assignment -name VHDL_FILE ../../src/rtps_discovery_module.vhd -hdl_version VHDL_2008
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set_global_assignment -name VHDL_FILE ../../src/rtps_handler.vhd -hdl_version VHDL_2008
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set_global_assignment -name VHDL_FILE ../../src/rtps_handler.vhd -hdl_version VHDL_2008
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set_global_assignment -name VHDL_FILE ../../src/rtps_out.vhd -hdl_version VHDL_2008
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set_global_assignment -name VHDL_FILE ../../src/rtps_out.vhd -hdl_version VHDL_2008
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set_global_assignment -name VHDL_FILE ../test6.vhd -hdl_version VHDL_2008
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set_global_assignment -name VHDL_FILE ../test5.vhd -hdl_version VHDL_2008
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set_global_assignment -name VHDL_FILE ../test5.vhd -hdl_version VHDL_2008
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set_global_assignment -name VHDL_FILE ../test4.vhd -hdl_version VHDL_2008
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set_global_assignment -name VHDL_FILE ../test4.vhd -hdl_version VHDL_2008
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set_global_assignment -name VHDL_FILE ../test3.vhd -hdl_version VHDL_2008
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set_global_assignment -name VHDL_FILE ../test3.vhd -hdl_version VHDL_2008
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@ -93,8 +98,12 @@ set_global_assignment -name VHDL_FILE ../../src/dual_port_ram.vhd -hdl_version V
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set_global_assignment -name VHDL_FILE ../../src/single_port_ram_cfg.vhd -hdl_version VHDL_2008
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set_global_assignment -name VHDL_FILE ../../src/single_port_ram_cfg.vhd -hdl_version VHDL_2008
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set_global_assignment -name VHDL_FILE ../../src/single_port_ram_Altera.vhd -hdl_version VHDL_2008
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set_global_assignment -name VHDL_FILE ../../src/single_port_ram_Altera.vhd -hdl_version VHDL_2008
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set_global_assignment -name VHDL_FILE ../../src/single_port_ram.vhd -hdl_version VHDL_2008
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set_global_assignment -name VHDL_FILE ../../src/single_port_ram.vhd -hdl_version VHDL_2008
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set_global_assignment -name VHDL_FILE ../../src/ros2/ros_config_package.vhd -hdl_version VHDL_2008
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set_global_assignment -name VHDL_FILE ../../src/rtps_config_package.vhd -hdl_version VHDL_2008
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set_global_assignment -name VHDL_FILE ../../src/rtps_config_package.vhd -hdl_version VHDL_2008
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set_global_assignment -name VHDL_FILE ../syn_config.vhd -hdl_version VHDL_2008
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set_global_assignment -name VHDL_FILE ../../src/ros2/dds_user_config.vhd -hdl_version VHDL_2008
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set_global_assignment -name VHDL_FILE ../syn_ros_service_config.vhd -hdl_version VHDL_2008
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set_global_assignment -name VHDL_FILE ../../src/ros2/example_interfaces/AddTwoInts_package.vhd -hdl_version VHDL_2008
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set_global_assignment -name VHDL_FILE ../../src/ros2/ros_package.vhd -hdl_version VHDL_2008
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set_global_assignment -name VHDL_FILE ../../src/rtps_package.vhd -hdl_version VHDL_2008
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set_global_assignment -name VHDL_FILE ../../src/rtps_package.vhd -hdl_version VHDL_2008
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set_global_assignment -name VHDL_FILE ../../src/math_pkg.vhd -hdl_version VHDL_2008
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set_global_assignment -name VHDL_FILE ../../src/math_pkg.vhd -hdl_version VHDL_2008
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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78
syn/syn_ros_service_config.vhd
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78
syn/syn_ros_service_config.vhd
Normal file
@ -0,0 +1,78 @@
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-- altera vhdl_input_version vhdl_2008
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-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.rtps_package.all;
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use work.ros_package.all;
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use work.AddTwoInts_package.all;
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package ros_config is
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-- IPv4 Address of ROS System [192.168.0.90]
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constant ROS_ADDRESS : std_logic_vector(IPv4_ADDRESS_WIDTH-1 downto 0) := x"C0A8005A";
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-- Random Key used to generate GUIDs
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constant ROS_RAND_KEY : std_logic_vector(47 downto 0) := x"1D4EEC915C7C";
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constant NUM_NODES : natural := 1;
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constant ROS_NODES : ROS_NODE_ARRAY_TYPE(0 to NUM_NODES-1) := (
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0 => (
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name => gen_user_string("add_two_ints_server"),
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namespace => gen_user_string(""),
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domain_id => 0,
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NUM_PUBS => 0,
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NUM_SUBS => 0,
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NUM_SERVICES => 1,
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NUM_ACTIONS => 0
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)
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);
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constant NUM_PUBS : natural := get_num_pubs(ROS_NODES);
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constant NUM_SUBS : natural := get_num_subs(ROS_NODES);
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constant NUM_SERVICES : natural := get_num_services(ROS_NODES);
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constant NUM_ACTIONS : natural := get_num_actions(ROS_NODES);
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constant ROS_PUBLICATIONS : ROS_TOPIC_ARRAY_TYPE(0 to NUM_PUBS-1) := (
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others => (
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node_id => 0,
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TOPICNAME => gen_user_string(""),
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TYPENAME => gen_user_string(""),
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QOS => ROS_QOS_PROFILE_DEFAULT,
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MAX_SIZE => 0
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)
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);
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constant ROS_SUBSCRIPTIONS : ROS_TOPIC_ARRAY_TYPE(0 to NUM_SUBS-1) := (
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others => (
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node_id => 0,
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TOPICNAME => gen_user_string(""),
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TYPENAME => gen_user_string(""),
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QOS => ROS_QOS_PROFILE_DEFAULT,
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MAX_SIZE => 0
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)
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);
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constant ROS_SERVICES : ROS_SERVICE_ARRAY_TYPE(0 to NUM_SERVICES-1) := (
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0 => (
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node_id => 0,
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SERVICENAME => gen_user_string("add_two_ints"),
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TYPENAME => gen_user_string("example_interfaces::srv::dds_::AddTwoInts_Request_"),
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QOS => ROS_QOS_PROFILE_SERVICES_DEFAULT,
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MAX_RQ_SIZE => MAX_ADDTWOINTS_RQ_SIZE,
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MAX_RR_SIZE => MAX_ADDTWOINTS_RR_SIZE,
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is_client => FALSE
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)
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);
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constant ROS_ACTIONS : ROS_ACTION_ARRAY_TYPE(0 to NUM_ACTIONS-1) := (
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others => (
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node_id => 0
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)
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);
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-- Defines sensible RTPS timings for simulation
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constant SIMULATION_TIMING : boolean := FALSE;
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end package;
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@ -83,7 +83,23 @@ begin
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free => open
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free => open
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);
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);
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dds_loopback_inst : entity work.L2_Testbench_Lib4(arch)
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--dds_loopback_inst : entity work.L2_Testbench_Lib4(arch)
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-- port map (
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-- -- SYSTEM
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-- clk => clk,
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-- reset => reset,
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-- time => time,
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-- -- INPUT
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-- empty => empty_fi_test,
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-- read => read_test_fi,
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-- data_in => data_fi_test,
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-- -- OUTPUT
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-- full => full_fo_test,
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-- write => write_test_fo,
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-- data_out => data_test_fo
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-- );
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ros_service_inst : entity work.L2_Testbench_ROS_Lib2(arch)
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port map (
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port map (
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-- SYSTEM
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-- SYSTEM
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clk => clk,
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clk => clk,
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