-- altera vhdl_input_version vhdl_2008
-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.math_pkg.all;
use work.rtps_package.all;

-- Test synthesis of array indexing

entity test4 is
    port (
        clk             : in std_logic;
        reset           : in std_logic;
        input           : in std_logic_vector(31 downto 0);
        input2          : in std_logic_vector(31 downto 0);
        output          : out std_logic_vector(31 downto 0)
    );
end entity;

architecture arch of test4 is
    
    type TEST_ARRAY_TYPE is array (0 to 3) of std_logic_vector(31 downto 0);
    
    signal test_array : TEST_ARRAY_TYPE;
    
begin
    
    process (all)
    begin
        if rising_edge(clk) then
            if (reset = '1') then
                output      <= (others => '0');
                test_array  <= (others => (others => '0'));
            else
                case (to_integer(unsigned(input))) is
                    when 0 =>
                        output          <= test_array(0);
                        test_array(0)   <= input2;
                    when 1 =>
                        output          <= test_array(1);
                        test_array(1)   <= input2;
                    when 2 =>
                        output          <= test_array(2);
                        test_array(2)   <= input2;
                    when 3 =>
                        output          <= test_array(3);
                        test_array(3)   <= input2;
                    when others =>
                end case;
            end if;
        end if;
    end process;
    
--    process (all)
--    begin
--        if rising_edge(clk) then
--            if (reset = '1') then
--                output      <= (others => '0');
--                test_array  <= (others => (others => '0'));
--            else
--                test_array(to_integer(unsigned(input)))  <= input2;
--                output  <= test_array(to_integer(unsigned(input)));
--            end if;
--        end if;
--    end process;

end architecture;