-- altera vhdl_input_version vhdl_2008
-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.test_package.all;

-- Test synthesis of array indexing

entity test7 is
    port (
        clk             : in std_logic;
        reset           : in std_logic;
        in1             : in std_logic;
        in2             : in std_logic;
        output          : out std_logic_vector(84 downto 0)
    );
end entity;

architecture arch of test7 is
    signal a : std_logic_vector(52 downto 0);
    signal b : std_logic_vector(31 downto 0);
    signal res : std_logic_vector(84 downto 0);
begin
    
    output  <= res;
    
    mult_inst : entity work.mult(SYN)
        generic map (
            PIPELINE_STAGES => 1,
            DATAA_WIDTH     => 32,
            DATAB_WIDTH     => 53,
            DATAB_CONST     => FALSE
        )
        port map (
            clk		    => clk,
            reset       => reset,
            dataa		=> a,
            datab		=> b,
            result		=> res
        );
    
    sync_prc : process(clk)
    begin
        if rising_edge(clk) then
            if (reset = '1') then
                a   <= (others => '0');
                b   <= (others => '0');
            else
                a   <= a(51 downto 0) & in1;
                b   <= b(30 downto 0) & in2;
            end if;
        end if;
    end process;
end architecture;