-- altera vhdl_input_version vhdl_2008
-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;

architecture altera of dual_port_ram is
    
begin

    altsyncram_component : altsyncram
	generic map (
        address_aclr_b                      => "NONE",
		address_reg_b                       => "CLOCK0",
		clock_enable_input_a                => "BYPASS",
		clock_enable_input_b                => "BYPASS",
		clock_enable_output_b               => "BYPASS",
		intended_device_family              => "Cyclone V",
		lpm_type                            => "altsyncram",
		numwords_a                          => MEMORY_DEPTH,
		numwords_b                          => MEMORY_DEPTH,
		operation_mode                      => "DUAL_PORT",
		outdata_aclr_b                      => "NONE",
		outdata_reg_b                       => "UNREGISTERED",
		power_up_uninitialized              => "FALSE",
		rdcontrol_reg_b                     => "CLOCK0",
		read_during_write_mode_mixed_ports  => "DONT_CARE",
		widthad_a                           => ADDR_WIDTH,
		widthad_b                           => ADDR_WIDTH,
		width_a                             => DATA_WIDTH,
		width_b                             => DATA_WIDTH,
		width_byteena_a                     => 1
	)
	port map (
		address_a   => waddr,
		address_b   => raddr,
		clock0      => clk,
		data_a      => wr_data,
		rden_b      => ren,
		wren_a      => wen,
		q_b         => rd_data
	);
    
end architecture;