-- altera vhdl_input_version vhdl_2008
-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.test_package.all;

-- Test synthesis of array indexing

entity test6 is
    port (
        clk             : in std_logic;
        reset           : in std_logic;
        input1          : in TEST_ENUM;
        input2          : in TEST_ENUM;
        input3          : in TEST_ENUM;
        input4          : in std_logic;
        input5          : in std_logic;
        output          : out std_logic
    );
end entity;

architecture arch of test6 is
    
    type STAGE_TYPE is (IN1, IN2, IN3);
    
    signal stage : STAGE_TYPE;
    
begin
    
--    process (all)
--        variable tmp_bool : boolean;
--    begin
--        if rising_edge(clk) then
--            if (reset = '1') then
--                output  <= '0';
--            else
--                tmp_bool := TRUE;
--                
--                case (input1) is
--                    when A =>
--                        if (input4 = '1') then
--                            tmp_bool    := FALSE;
--                        end if;
--                    when B =>
--                        if (input5 = '1') then
--                            tmp_bool    := FALSE;
--                        end if;
--                    when C =>
--                        tmp_bool    := FALSE;
--                    when others =>
--                        null;
--                end case;
--                
--                case (input2) is
--                    when C =>
--                        if (input4 = '1') then
--                            tmp_bool    := FALSE;
--                        end if;
--                    when others =>
--                        null;
--                end case;
--                
--                case (input3) is
--                    when A =>
--                        tmp_bool    := FALSE;
--                    when D =>
--                        if (input4 = '0' and input5 = '1') then
--                            tmp_bool    := FALSE;
--                        end if;
--                    when others =>
--                        null;
--                end case;
--                
--                if (tmp_bool) then
--                    output  <= '1';
--                else
--                    output  <= '0';
--                end if;
--            end if;
--        end if;
--    end process;
    
    process (all)
    begin
        if rising_edge(clk) then
            if (reset = '1') then
                output  <= '0';
                stage   <= IN1;
            else
                
                case (stage) is
                    when IN1 =>
                        -- DEFAULT
                        stage   <= IN2;
                        
                        case (input1) is
                            when A =>
                                if (input4 = '1') then
                                    output  <= '0';
                                    stage   <= IN1;
                                end if;
                            when B =>
                                if (input5 = '1') then
                                    output  <= '0';
                                    stage   <= IN1;
                                end if;
                            when C =>
                                output  <= '0';
                                stage   <= IN1;
                            when others =>
                                null;
                        end case;
                    when IN2 =>
                        -- DEFAULT
                        stage   <= IN3;
                        
                        case (input2) is
                            when C =>
                                if (input4 = '1') then
                                    output  <= '0';
                                    stage   <= IN1;
                                end if;
                            when others =>
                                null;
                        end case;
                    when IN3 =>
                        -- DEFAULT
                        stage   <= IN1;
                        output  <= '1';
                        
                        case (input3) is
                            when A =>
                                output  <= '0';
                                stage   <= IN1;
                            when D =>
                                if (input4 = '0' and input5 = '1') then
                                    output  <= '0';
                                    stage   <= IN1;
                                end if;
                            when others =>
                                null;
                        end case;
                end case;
            end if;
        end if;
    end process;
    
end architecture;