-- altera vhdl_input_version vhdl_2008 -- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html) library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.ros_package.all; use work.ros_config.all; use work.rtps_package.all; use work.user_config.all; use work.rtps_config_package.all; use work.Fibonacci_package.all; entity L2_Testbench_ROS_Lib4 is port ( -- SYSTEM clk : in std_logic; reset : in std_logic; time : in TIME_TYPE; -- INPUT empty : in std_logic; read : out std_logic; data_in : in std_logic_vector(WORD_WIDTH-1 downto 0); -- OUTPUT full : in std_logic; write : out std_logic; data_out : out std_logic_vector(WORD_WIDTH-1 downto 0) ); end entity; architecture arch of L2_Testbench_ROS_Lib4 is signal full_fire_rh, write_rh_fire : std_logic_vector(0 to NUM_ENDPOINTS-1); signal last_word_rh_firb, last_word_rh_fire : std_logic; signal data_rh_fire, data_rh_firb : std_logic_vector(WORD_WIDTH-1 downto 0); signal full_firb_rh, write_rh_firb : std_logic; signal read_rb_firb, empty_firb_rb, last_word_firb_rb : std_logic; signal data_firb_rb : std_logic_vector(WORD_WIDTH-1 downto 0); signal read_re_fire, last_word_fire_re : std_logic_vector(0 to 1); signal empty_fire_re : std_logic_vector(0 to NUM_ENDPOINTS-1); signal data_fire_re : WORD_ARRAY_TYPE(0 to 1); signal alive_re_rb, full_frbre_re, write_rb_frbre : std_logic_vector(0 to NUM_ENDPOINTS-1); signal last_word_rb_frbre , last_word_rb_firo : std_logic; signal data_rb_frbre , data_rb_firo : std_logic_vector(WORD_WIDTH-1 downto 0); signal full_firo_rb, write_rb_firo : std_logic; signal read_re_frbre, last_word_frbre_re : std_logic_vector(0 to 1); signal empty_frbre_re : std_logic_vector(0 to NUM_ENDPOINTS-1); signal data_frbre_re : WORD_ARRAY_TYPE(0 to 1); signal full_firo_re, write_re_firo, last_word_re_firo : std_logic_vector(0 to 1); signal data_re_firo : WORD_ARRAY_TYPE(0 to 1); signal start_rr_dr, ack_dr_rr, done_dr_rr, valid_rr_dr, ready_dr_rr, last_word_rr_dr : std_logic_vector(0 to NUM_READERS-1); signal opcode_rr_dr : HISTORY_CACHE_OPCODE_ARRAY_TYPE(0 to NUM_READERS-1); signal ret_dr_rr : HISTORY_CACHE_RESPONSE_ARRAY_TYPE(0 to NUM_READERS-1); signal data_rr_dr : WORD_ARRAY_TYPE(0 to NUM_READERS-1); signal liveliness_assertion_dw_rw, data_available_dw_rw, start_rw_dw, ack_dw_rw, done_rw_dw, get_data_rw_dw, valid_dw_rw, ready_rw_dw, last_word_dw_rw : std_logic_vector(0 to NUM_WRITERS-1); signal opcode_rw_dw : HISTORY_CACHE_OPCODE_ARRAY_TYPE(0 to NUM_WRITERS-1); signal seq_nr_rw_dw, cc_seq_nr_dw_rw : SEQUENCENUMBER_ARRAY_TYPE(0 to NUM_WRITERS-1); signal ret_dw_rw : HISTORY_CACHE_RESPONSE_ARRAY_TYPE(0 to NUM_WRITERS-1); signal data_dw_rw : WORD_ARRAY_TYPE(0 to NUM_WRITERS-1); signal cc_instance_handle_dw_rw : INSTANCE_HANDLE_ARRAY_TYPE(0 to NUM_WRITERS-1); signal cc_kind_dw_rw : CACHE_CHANGE_KIND_ARRAY_TYPE(0 to NUM_WRITERS-1); signal cc_source_timestamp_dw_rw : TIME_ARRAY_TYPE(0 to NUM_WRITERS-1); signal sample_info_dr_ri : SAMPLE_INFO_ARRAY_TYPE(0 to NUM_READERS-1); signal start_ri_dr, ack_dr_ri, get_data_ri_dr, done_dr_ri, ready_ri_dr, valid_dr_ri, sample_info_valid_dr_ri, sample_info_ack_ri_dr, eoc_dr_ri, last_word_dr_ri : std_logic_vector(0 to NUM_READERS-1); signal opcode_ri_dr : DDS_READER_OPCODE_ARRAY_TYPE(0 to NUM_READERS-1); signal instance_state_ri_dr : INSTANCE_STATE_ARRAY_TYPE(0 to NUM_READERS-1); signal view_state_ri_dr : VIEW_STATE_ARRAY_TYPE(0 to NUM_READERS-1); signal sample_state_ri_dr : SAMPLE_STATE_ARRAY_TYPE(0 to NUM_READERS-1); signal instance_handle_ri_dr : INSTANCE_HANDLE_ARRAY_TYPE(0 to NUM_READERS-1); signal max_samples_ri_dr : MAX_SAMPLES_ARRAY_TYPE(0 to NUM_READERS-1); signal return_code_dr_ri : RETURN_CODE_ARRAY_TYPE(0 to NUM_READERS-1); signal data_dr_ri : WORD_ARRAY_TYPE(0 to NUM_READERS-1); signal status_dr_ri : STATUS_KIND_ARRAY_TYPE(0 to NUM_READERS-1); signal start_wi_dw, ack_dw_wi, done_dw_wi, valid_wi_dw, valid_dw_wi, ready_wi_dw, ready_dw_wi, last_word_wi_dw, last_word_dw_wi : std_logic_vector(0 to NUM_WRITERS-1); signal opcode_wi_dw : DDS_WRITER_OPCODE_ARRAY_TYPE(0 to NUM_WRITERS-1); signal instance_handle_wi_dw, instance_handle_dw_wi : INSTANCE_HANDLE_ARRAY_TYPE(0 to NUM_WRITERS-1); signal source_ts_wi_dw : TIME_ARRAY_TYPE(0 to NUM_WRITERS-1); signal max_wait_wi_dw : DURATION_ARRAY_TYPE(0 to NUM_WRITERS-1); signal return_code_dw_wi : RETURN_CODE_ARRAY_TYPE(0 to NUM_WRITERS-1); signal data_dw_wi, data_wi_dw : WORD_ARRAY_TYPE(0 to NUM_WRITERS-1); signal status_dw_wi : STATUS_KIND_ARRAY_TYPE(0 to NUM_WRITERS-1); signal empty_firo_ro, read_ro_firo, last_word_firo_ro : std_logic_vector(0 to 2); signal data_firo_ro : WORD_ARRAY_TYPE(0 to 2); signal action_if : ACTION_INTERFACE_ARRAY_TYPE(0 to NUM_ACTIONS-1); signal ros_time : ROS_TIME_TYPE; -- ###GENERATED START### signal start_s, ack_s, done_s : std_logic; signal opcode_s : ROS_ACTION_OPCODE_TYPE; signal return_code_s : std_logic_vector(ROS_RETCODE_WIDTH-1 downto 0); signal goal_handle_in_s, goal_handle_out_s, new_goal_handle_s, cancel_request_handle_s : std_logic_vector(GOAL_HANDLE_WIDTH-1 downto 0); signal goal_state_in_s, goal_state_out_s : std_logic_vector(CDR_INT8_WIDTH-1 downto 0); signal goal_id_s : std_logic_vector(UUID_WIDTH-1 downto 0); signal goal_result_index_s, new_goal_result_index_s, result_addr_s : std_logic_vector(WORD_WIDTH-1 downto 0); signal goal_stamp_s : ROS_TIME_TYPE; signal new_goal_request_s, new_goal_accepted_s, new_goal_response_s, cancel_request_s, cancel_accepted_s, cancel_response_s, result_ready_s, result_ren_s, result_wen_s, result_valid_s, result_ack_s : std_logic; signal new_goal_order_s : std_logic_vector(CDR_LONG_WIDTH-1 downto 0); signal result_seq_len_s, result_seq_addr_s : std_logic_vector(R_RR_SEQ_ADDR_WIDTH-1 downto 0); signal result_seq_ready_s, result_seq_ren_s, result_seq_wen_s, result_seq_valid_s, result_seq_ack_s : std_logic; signal result_seq_r_s, result_seq_w_s : std_logic_vector(CDR_LONG_WIDTH-1 downto 0); signal feedback_seq_len_s, feedback_seq_addr_s : std_logic_vector(F_SEQ_ADDR_WIDTH-1 downto 0); signal feedback_seq_ready_s, feedback_seq_ren_s, feedback_seq_wen_s, feedback_seq_valid_s, feedback_seq_ack_s : std_logic; signal feedback_seq_r_s, feedback_seq_w_s : std_logic_vector(CDR_LONG_WIDTH-1 downto 0); -- ######GENERATED END###### begin rtps_handler_inst : entity work.rtps_handler(arch) port map ( -- SYSTEM clk => clk, reset => reset, -- INPUT empty => empty, rd => read, data_in => data_in, -- TO DISCOVERY MODULE full_dm => full_firb_rh, wr_dm => write_rh_firb, data_out_dm => data_rh_firb, last_word_out_dm => last_word_rh_firb, -- TO USER ENDPOINTS full_rtps => full_fire_rh, wr_rtps => write_rh_fire, data_out_rtps => data_rh_fire, last_word_out_rtps => last_word_rh_fire ); fifo_in_rb_inst : configuration work.FWFT_FIFO_cfg generic map ( FIFO_DEPTH => 2, DATA_WIDTH => WORD_WIDTH+1 ) port map ( -- SYSTEM reset => reset, clk => clk, -- INPUT full => full_firb_rh, write => write_rh_firb, data_in(WORD_WIDTH-1 downto 0) => data_rh_firb, data_in(WORD_WIDTH) => last_word_rh_firb, -- OUTPUT empty => empty_firb_rb, read => read_rb_firb, data_out(WORD_WIDTH-1 downto 0) => data_firb_rb, data_out(WORD_WIDTH) => last_word_firb_rb, -- MISC free => open ); fifo_in_re_r_if : if (NUM_READERS > 0) generate fifo_in_re_inst : entity work.vector_FIFO generic map ( FIFO_DEPTH => 2, DATA_WIDTH => WORD_WIDTH+1, FIFO_WIDTH => NUM_READERS ) port map ( -- SYSTEM reset => reset, clk => clk, -- INPUT full => full_fire_rh(0 to NUM_READERS-1), write => write_rh_fire(0 to NUM_READERS-1), data_in(WORD_WIDTH-1 downto 0) => data_rh_fire, -- Multicast data_in(WORD_WIDTH) => last_word_rh_fire, -- Multicast -- OUTPUT empty => empty_fire_re(0 to NUM_READERS-1), read => read_re_fire(0), data_out(WORD_WIDTH-1 downto 0) => data_fire_re(0), data_out(WORD_WIDTH) => last_word_fire_re(0) ); end generate; fifo_in_re_w_if : if (NUM_WRITERS > 0) generate fifo_in_re_inst : entity work.vector_FIFO generic map ( FIFO_DEPTH => 2, DATA_WIDTH => WORD_WIDTH+1, FIFO_WIDTH => NUM_WRITERS ) port map ( -- SYSTEM reset => reset, clk => clk, -- INPUT full => full_fire_rh(NUM_READERS to NUM_ENDPOINTS-1), write => write_rh_fire(NUM_READERS to NUM_ENDPOINTS-1), data_in(WORD_WIDTH-1 downto 0) => data_rh_fire, -- Multicast data_in(WORD_WIDTH) => last_word_rh_fire, -- Multicast -- OUTPUT empty => empty_fire_re(NUM_READERS to NUM_ENDPOINTS-1), read => read_re_fire(1), data_out(WORD_WIDTH-1 downto 0) => data_fire_re(1), data_out(WORD_WIDTH) => last_word_fire_re(1) ); end generate; rtps_discovery_module_inst : entity work.rtps_discovery_module(arch) generic map ( MAX_REMOTE_PARTICIPANTS => MAX_REMOTE_PARTICIPANTS, PREFER_MULTICAST => PREFER_MULTICAST_LOCATORS ) port map ( clk => clk, reset => reset, time => time, -- FROM RTPS HANDLER empty => empty_firb_rb, rd => read_rb_firb, data_in => data_firb_rb, last_word_in => last_word_firb_rb, -- FROM USER ENDPOINTS alive => alive_re_rb, -- TO USER ENDPOINTS full_rtps => full_frbre_re, wr_rtps => write_rb_frbre, data_out_rtps => data_rb_frbre, last_word_out_rtps => last_word_rb_frbre, -- TO RTPS OUT full_ro => full_firo_rb, wr_ro => write_rb_firo, data_out_ro => data_rb_firo, last_word_out_ro => last_word_rb_firo ); fifo_rb_re_r_if : if (NUM_READERS > 0) generate fifo_rb_re_inst : entity work.vector_FIFO generic map ( FIFO_DEPTH => 2, DATA_WIDTH => WORD_WIDTH+1, FIFO_WIDTH => NUM_READERS ) port map ( -- SYSTEM reset => reset, clk => clk, -- INPUT full => full_frbre_re(0 to NUM_READERS-1), write => write_rb_frbre(0 to NUM_READERS-1), data_in(WORD_WIDTH-1 downto 0) => data_rb_frbre, data_in(WORD_WIDTH) => last_word_rb_frbre, -- OUTPUT empty => empty_frbre_re(0 to NUM_READERS-1), read => read_re_frbre(0), data_out(WORD_WIDTH-1 downto 0) => data_frbre_re(0), data_out(WORD_WIDTH) => last_word_frbre_re(0) ); end generate; fifo_rb_re_w_if : if (NUM_WRITERS > 0) generate fifo_rb_re_inst : entity work.vector_FIFO generic map ( FIFO_DEPTH => 2, DATA_WIDTH => WORD_WIDTH+1, FIFO_WIDTH => NUM_WRITERS ) port map ( -- SYSTEM reset => reset, clk => clk, -- INPUT full => full_frbre_re(NUM_READERS to NUM_ENDPOINTS-1), write => write_rb_frbre(NUM_READERS to NUM_ENDPOINTS-1), data_in(WORD_WIDTH-1 downto 0) => data_rb_frbre, data_in(WORD_WIDTH) => last_word_rb_frbre, -- OUTPUT empty => empty_frbre_re(NUM_READERS to NUM_ENDPOINTS-1), read => read_re_frbre(1), data_out(WORD_WIDTH-1 downto 0) => data_frbre_re(1), data_out(WORD_WIDTH) => last_word_frbre_re(1) ); end generate; rtps_endpoint_r_if : if (NUM_READERS > 0) generate rtps_reader_inst : entity work.rtps_reader(arch) generic map ( NUM_READERS => NUM_READERS, CONFIG_ARRAY => to_QUARTUS_CONFIG_ARRAY_TYPE(ENDPOINT_CONFIG(0 to NUM_READERS-1)), ENTITYID => ENTITYID(0 to NUM_READERS-1), MAX_REMOTE_ENDPOINTS => MAX_REMOTE_ENDPOINTS ) port map ( -- SYSTEM clk => clk, reset => reset, time => time, -- FROM RTPS_HANDLER (USER TRAFFIC) empty_user => empty_fire_re(0 to NUM_READERS-1), rd_user => read_re_fire(0), data_in_user => data_fire_re(0), last_word_in_user => last_word_fire_re(0), -- FROM DISCOVERY MODULE (META TRAFFIC) empty_meta => empty_frbre_re(0 to NUM_READERS-1), rd_meta => read_re_frbre(0), data_in_meta => data_frbre_re(0), last_word_in_meta => last_word_frbre_re(0), -- RTPS OUTPUT full_ro => full_firo_re(0), wr_ro => write_re_firo(0), data_out_ro => data_re_firo(0), last_word_out_ro => last_word_re_firo(0), -- TO HISTORY CACHE start_hc => start_rr_dr(0 to NUM_READERS-1), opcode_hc => opcode_rr_dr(0 to NUM_READERS-1), ack_hc => ack_dr_rr(0 to NUM_READERS-1), done_hc => done_dr_rr(0 to NUM_READERS-1), ret_hc => ret_dr_rr(0 to NUM_READERS-1), valid_out_hc => valid_rr_dr(0 to NUM_READERS-1), ready_out_hc => ready_dr_rr(0 to NUM_READERS-1), data_out_hc => data_rr_dr(0 to NUM_READERS-1), last_word_out_hc => last_word_rr_dr(0 to NUM_READERS-1) ); -- Set Alive Signals of Readers to Zero alive_re_rb(0 to NUM_READERS-1) <= (others => '0'); end generate; rtps_endpoint_w_if : if (NUM_WRITERS > 0) generate rtps_writer_inst : entity work.rtps_writer(arch) generic map ( NUM_WRITERS => NUM_WRITERS, CONFIG_ARRAY => to_QUARTUS_CONFIG_ARRAY_TYPE(ENDPOINT_CONFIG(NUM_READERS to NUM_ENDPOINTS-1)), ENTITYID => ENTITYID(NUM_READERS to NUM_ENDPOINTS-1), INLINE_QOS => INLINE_QOS_DATA(0 to NUM_WRITERS-1), MAX_REMOTE_ENDPOINTS => MAX_REMOTE_ENDPOINTS ) port map ( -- SYSTEM clk => clk, reset => reset, time => time, -- FROM RTPS_HANDLER (USER TRAFFIC) empty_user => empty_fire_re(NUM_READERS to NUM_ENDPOINTS-1), rd_user => read_re_fire(1), data_in_user => data_fire_re(1), last_word_in_user => last_word_fire_re(1), -- FROM DISCOVERY MODULE (META TRAFFIC) empty_meta => empty_frbre_re(NUM_READERS to NUM_ENDPOINTS-1), rd_meta => read_re_frbre(1), data_in_meta => data_frbre_re(1), last_word_in_meta => last_word_frbre_re(1), -- TO DISCOVERY MODULE (META TRAFFIC) alive_sig => alive_re_rb(NUM_READERS to NUM_ENDPOINTS-1), -- RTPS OUTPUT full_ro => full_firo_re(1), wr_ro => write_re_firo(1), data_out_ro => data_re_firo(1), last_word_out_ro => last_word_re_firo(1), -- FROM HC liveliness_assertion => liveliness_assertion_dw_rw(0 to NUM_WRITERS-1), data_available => data_available_dw_rw(0 to NUM_WRITERS-1), start_hc => start_rw_dw(0 to NUM_WRITERS-1), opcode_hc => opcode_rw_dw(0 to NUM_WRITERS-1), ack_hc => ack_dw_rw(0 to NUM_WRITERS-1), seq_nr_hc => seq_nr_rw_dw(0 to NUM_WRITERS-1), done_hc => done_rw_dw(0 to NUM_WRITERS-1), ret_hc => ret_dw_rw(0 to NUM_WRITERS-1), get_data_hc => get_data_rw_dw(0 to NUM_WRITERS-1), valid_in_hc => valid_dw_rw(0 to NUM_WRITERS-1), ready_in_hc => ready_rw_dw(0 to NUM_WRITERS-1), data_in_hc => data_dw_rw(0 to NUM_WRITERS-1), last_word_in_hc => last_word_dw_rw(0 to NUM_WRITERS-1), cc_instance_handle => cc_instance_handle_dw_rw(0 to NUM_WRITERS-1), cc_kind => cc_kind_dw_rw(0 to NUM_WRITERS-1), cc_source_timestamp => cc_source_timestamp_dw_rw(0 to NUM_WRITERS-1), cc_seq_nr => cc_seq_nr_dw_rw(0 to NUM_WRITERS-1) ); end generate; dds_endpoint_w_if : if (NUM_WRITERS > 1) generate dds_writer_inst : entity work.dds_writer(arch) generic map ( NUM_WRITERS => NUM_WRITERS-1, CONFIG_ARRAY => to_QUARTUS_CONFIG_ARRAY_TYPE(ENDPOINT_CONFIG(NUM_READERS to NUM_ENDPOINTS-2)) ) port map ( -- SYSTEM clk => clk, reset => reset, time => time, -- TO/FROM RTPS ENDPOINT start_rtps => start_rw_dw(0 to NUM_WRITERS-2), opcode_rtps => opcode_rw_dw(0 to NUM_WRITERS-2), ack_rtps => ack_dw_rw(0 to NUM_WRITERS-2), done_rtps => done_rw_dw(0 to NUM_WRITERS-2), ret_rtps => ret_dw_rw(0 to NUM_WRITERS-2), seq_nr_rtps => seq_nr_rw_dw(0 to NUM_WRITERS-2), get_data_rtps => get_data_rw_dw(0 to NUM_WRITERS-2), valid_out_rtps => valid_dw_rw(0 to NUM_WRITERS-2), ready_out_rtps => ready_rw_dw(0 to NUM_WRITERS-2), data_out_rtps => data_dw_rw(0 to NUM_WRITERS-2), last_word_out_rtps => last_word_dw_rw(0 to NUM_WRITERS-2), liveliness_assertion => liveliness_assertion_dw_rw(0 to NUM_WRITERS-2), data_available => data_available_dw_rw(0 to NUM_WRITERS-2), -- Cache Change cc_instance_handle => cc_instance_handle_dw_rw(0 to NUM_WRITERS-2), cc_kind => cc_kind_dw_rw(0 to NUM_WRITERS-2), cc_source_timestamp => cc_source_timestamp_dw_rw(0 to NUM_WRITERS-2), cc_seq_nr => cc_seq_nr_dw_rw(0 to NUM_WRITERS-2), -- TO/FROM USER ENTITY start_dds => start_wi_dw(0 to NUM_WRITERS-2), ack_dds => ack_dw_wi(0 to NUM_WRITERS-2), opcode_dds => opcode_wi_dw(0 to NUM_WRITERS-2), instance_handle_in_dds => instance_handle_wi_dw(0 to NUM_WRITERS-2), source_ts_dds => source_ts_wi_dw(0 to NUM_WRITERS-2), max_wait_dds => max_wait_wi_dw(0 to NUM_WRITERS-2), done_dds => done_dw_wi(0 to NUM_WRITERS-2), return_code_dds => return_code_dw_wi(0 to NUM_WRITERS-2), instance_handle_out_dds => instance_handle_dw_wi(0 to NUM_WRITERS-2), valid_in_dds => valid_wi_dw(0 to NUM_WRITERS-2), ready_in_dds => ready_dw_wi(0 to NUM_WRITERS-2), data_in_dds => data_wi_dw(0 to NUM_WRITERS-2), last_word_in_dds => last_word_wi_dw(0 to NUM_WRITERS-2), valid_out_dds => valid_dw_wi(0 to NUM_WRITERS-2), ready_out_dds => ready_wi_dw(0 to NUM_WRITERS-2), data_out_dds => data_dw_wi(0 to NUM_WRITERS-2), last_word_out_dds => last_word_dw_wi(0 to NUM_WRITERS-2), -- Communication Status status => status_dw_wi(0 to NUM_WRITERS-2) ); end generate; dds_endpoint_r_if : if (NUM_READERS > 0) generate dds_reader_inst : entity work.dds_reader(arch) generic map ( NUM_READERS => NUM_READERS, CONFIG_ARRAY => to_QUARTUS_CONFIG_ARRAY_TYPE(ENDPOINT_CONFIG(0 to NUM_READERS-1)), MAX_REMOTE_ENDPOINTS => MAX_REMOTE_ENDPOINTS ) port map ( -- SYSTEM clk => clk, reset => reset, time => time, -- FROM RTPS ENDPOINT start_rtps => start_rr_dr(0 to NUM_READERS-1), opcode_rtps => opcode_rr_dr(0 to NUM_READERS-1), ack_rtps => ack_dr_rr(0 to NUM_READERS-1), done_rtps => done_dr_rr(0 to NUM_READERS-1), ret_rtps => ret_dr_rr(0 to NUM_READERS-1), valid_in_rtps => valid_rr_dr(0 to NUM_READERS-1), ready_in_rtps => ready_dr_rr(0 to NUM_READERS-1), data_in_rtps => data_rr_dr(0 to NUM_READERS-1), last_word_in_rtps => last_word_rr_dr(0 to NUM_READERS-1), -- TO USER ENTITY start_dds => start_ri_dr(0 to NUM_READERS-1), ack_dds => ack_dr_ri(0 to NUM_READERS-1), opcode_dds => opcode_ri_dr(0 to NUM_READERS-1), instance_state_dds => instance_state_ri_dr(0 to NUM_READERS-1), view_state_dds => view_state_ri_dr(0 to NUM_READERS-1), sample_state_dds => sample_state_ri_dr(0 to NUM_READERS-1), instance_handle_dds => instance_handle_ri_dr(0 to NUM_READERS-1), max_samples_dds => max_samples_ri_dr(0 to NUM_READERS-1), get_data_dds => get_data_ri_dr(0 to NUM_READERS-1), done_dds => done_dr_ri(0 to NUM_READERS-1), return_code_dds => return_code_dr_ri(0 to NUM_READERS-1), valid_out_dds => valid_dr_ri(0 to NUM_READERS-1), ready_out_dds => ready_ri_dr(0 to NUM_READERS-1), data_out_dds => data_dr_ri(0 to NUM_READERS-1), last_word_out_dds => last_word_dr_ri(0 to NUM_READERS-1), sample_info => sample_info_dr_ri(0 to NUM_READERS-1), sample_info_valid => sample_info_valid_dr_ri(0 to NUM_READERS-1), sample_info_ack => sample_info_ack_ri_dr(0 to NUM_READERS-1), eoc => eoc_dr_ri(0 to NUM_READERS-1), -- Communication Status status => status_dr_ri(0 to NUM_READERS-1) ); end generate; ros_discovery_writer_inst : entity work.ros_static_discovery_writer(arch) port map ( -- SYSTEM clk => clk, reset => reset, -- TO/FROM RTPS ENDPOINT start => start_rw_dw(NUM_WRITERS-1), opcode => opcode_rw_dw(NUM_WRITERS-1), ack => ack_dw_rw(NUM_WRITERS-1), done => done_rw_dw(NUM_WRITERS-1), ret => ret_dw_rw(NUM_WRITERS-1), seq_nr => seq_nr_rw_dw(NUM_WRITERS-1), get_data => get_data_rw_dw(NUM_WRITERS-1), valid_out => valid_dw_rw(NUM_WRITERS-1), ready_out => ready_rw_dw(NUM_WRITERS-1), data_out => data_dw_rw(NUM_WRITERS-1), last_word_out => last_word_dw_rw(NUM_WRITERS-1), liveliness_assertion => liveliness_assertion_dw_rw(NUM_WRITERS-1), data_available => data_available_dw_rw(NUM_WRITERS-1), -- Cache Change cc_instance_handle => cc_instance_handle_dw_rw(NUM_WRITERS-1), cc_kind => cc_kind_dw_rw(NUM_WRITERS-1), cc_source_timestamp => cc_source_timestamp_dw_rw(NUM_WRITERS-1), cc_seq_nr => cc_seq_nr_dw_rw(NUM_WRITERS-1) ); fifo_in_ro_gen : for i in 0 to 2 generate fifo_in_ro_if : if (i = 2) generate fifo_in_ro_inst : configuration work.FWFT_FIFO_cfg generic map ( FIFO_DEPTH => 2, DATA_WIDTH => WORD_WIDTH+1 ) port map ( -- SYSTEM reset => reset, clk => clk, -- INPUT full => full_firo_rb, write => write_rb_firo, data_in(WORD_WIDTH-1 downto 0) => data_rb_firo, data_in(WORD_WIDTH) => last_word_rb_firo, -- OUTPUT empty => empty_firo_ro(i), read => read_ro_firo(i), data_out(WORD_WIDTH) => last_word_firo_ro(i), data_out(WORD_WIDTH-1 downto 0) => data_firo_ro(i), -- MISC free => open ); else generate fifo_in_ro_inst : configuration work.FWFT_FIFO_cfg generic map ( FIFO_DEPTH => 2, DATA_WIDTH => WORD_WIDTH+1 ) port map ( -- SYSTEM reset => reset, clk => clk, -- INPUT full => full_firo_re(i), write => write_re_firo(i), data_in(WORD_WIDTH-1 downto 0) => data_re_firo(i), data_in(WORD_WIDTH) => last_word_re_firo(i), -- OUTPUT empty => empty_firo_ro(i), read => read_ro_firo(i), data_out(WORD_WIDTH) => last_word_firo_ro(i), data_out(WORD_WIDTH-1 downto 0) => data_firo_ro(i), -- MISC free => open ); end generate; end generate; rtps_out_inst : entity work.rtps_out(arch) generic map ( RTPS_OUT_WIDTH => 3 ) port map ( -- SYSTEM clk => clk, reset => reset, -- INPUT empty => empty_firo_ro, rd => read_ro_firo, data_in => data_firo_ro, last_word_in => last_word_firo_ro, -- OUTPUT full => full, wr => write, data_out => data_out ); action_if_gen : for i in 0 to NUM_ACTIONS-1 generate -- start_ri_dr(i) <= action_if(i).g_start_r; action_if(i).g_ack_r <= ack_dr_ri(i); opcode_ri_dr(i) <= action_if(i).g_opcode_r; instance_state_ri_dr(i) <= action_if(i).g_instance_state_r; view_state_ri_dr(i) <= action_if(i).g_view_state_r; sample_state_ri_dr(i) <= action_if(i).g_sample_state_r; instance_handle_ri_dr(i) <= action_if(i).g_instance_handle_r; max_samples_ri_dr(i) <= action_if(i).g_max_samples_r; get_data_ri_dr(i) <= action_if(i).g_get_data_r; action_if(i).g_done_r <= done_dr_ri(i); action_if(i).g_return_code_r <= return_code_dr_ri(i); action_if(i).g_valid_in_r <= valid_dr_ri(i); ready_ri_dr(i) <= action_if(i).g_ready_in_r; action_if(i).g_data_in_r <= data_dr_ri(i); action_if(i).g_last_word_in_r <= last_word_dr_ri(i); action_if(i).g_sample_info_r <= sample_info_dr_ri(i); action_if(i).g_sample_info_valid_r <= sample_info_valid_dr_ri(i); sample_info_ack_ri_dr(i) <= action_if(i).g_sample_info_ack_r; action_if(i).g_eoc_r <= eoc_dr_ri(i); action_if(i).g_status_r <= status_dr_ri(i); start_wi_dw(i) <= action_if(i).g_start_w; action_if(i).g_ack_w <= ack_dw_wi(i); opcode_wi_dw(i) <= action_if(i).g_opcode_w; action_if(i).g_instance_handle_out_w <= instance_handle_dw_wi(i); source_ts_wi_dw(i) <= action_if(i).g_source_ts_w; max_wait_wi_dw(i) <= action_if(i).g_max_wait_w; action_if(i).g_done_w <= done_dw_wi(i); action_if(i).g_return_code_w <= return_code_dw_wi(i); instance_handle_wi_dw(i) <= action_if(i).g_instance_handle_in_w; valid_wi_dw(i) <= action_if(i).g_valid_out_w; action_if(i).g_ready_out_w <= ready_dw_wi(i); data_wi_dw(i) <= action_if(i).g_data_out_w; last_word_wi_dw(i) <= action_if(i).g_last_word_out_w; action_if(i).g_valid_in_w <= valid_dw_wi(i); ready_wi_dw(i) <= action_if(i).g_ready_in_w; action_if(i).g_data_in_w <= data_dw_wi(i); action_if(i).g_last_word_in_w <= last_word_dw_wi(i); action_if(i).g_status_w <= status_dw_wi(i); -- start_ri_dr(i+1) <= action_if(i).r_start_r; action_if(i).r_ack_r <= ack_dr_ri(i+1); opcode_ri_dr(i+1) <= action_if(i).r_opcode_r; instance_state_ri_dr(i+1) <= action_if(i).r_instance_state_r; view_state_ri_dr(i+1) <= action_if(i).r_view_state_r; sample_state_ri_dr(i+1) <= action_if(i).r_sample_state_r; instance_handle_ri_dr(i+1) <= action_if(i).r_instance_handle_r; max_samples_ri_dr(i+1) <= action_if(i).r_max_samples_r; get_data_ri_dr(i+1) <= action_if(i).r_get_data_r; action_if(i).r_done_r <= done_dr_ri(i+1); action_if(i).r_return_code_r <= return_code_dr_ri(i+1); action_if(i).r_valid_in_r <= valid_dr_ri(i+1); ready_ri_dr(i+1) <= action_if(i).r_ready_in_r; action_if(i).r_data_in_r <= data_dr_ri(i+1); action_if(i).r_last_word_in_r <= last_word_dr_ri(i+1); action_if(i).r_sample_info_r <= sample_info_dr_ri(i+1); action_if(i).r_sample_info_valid_r <= sample_info_valid_dr_ri(i+1); sample_info_ack_ri_dr(i+1) <= action_if(i).r_sample_info_ack_r; action_if(i).r_eoc_r <= eoc_dr_ri(i+1); action_if(i).r_status_r <= status_dr_ri(i+1); start_wi_dw(i+1) <= action_if(i).r_start_w; action_if(i).r_ack_w <= ack_dw_wi(i+1); opcode_wi_dw(i+1) <= action_if(i).r_opcode_w; action_if(i).r_instance_handle_out_w <= instance_handle_dw_wi(i+1); source_ts_wi_dw(i+1) <= action_if(i).r_source_ts_w; max_wait_wi_dw(i+1) <= action_if(i).r_max_wait_w; action_if(i).r_done_w <= done_dw_wi(i+1); action_if(i).r_return_code_w <= return_code_dw_wi(i+1); instance_handle_wi_dw(i+1) <= action_if(i).r_instance_handle_in_w; valid_wi_dw(i+1) <= action_if(i).r_valid_out_w; action_if(i).r_ready_out_w <= ready_dw_wi(i+1); data_wi_dw(i+1) <= action_if(i).r_data_out_w; last_word_wi_dw(i+1) <= action_if(i).r_last_word_out_w; action_if(i).r_valid_in_w <= valid_dw_wi(i+1); ready_wi_dw(i+1) <= action_if(i).r_ready_in_w; action_if(i).r_data_in_w <= data_dw_wi(i+1); action_if(i).r_last_word_in_w <= last_word_dw_wi(i+1); action_if(i).r_status_w <= status_dw_wi(i+1); -- start_ri_dr(i+2) <= action_if(i).c_start_r; action_if(i).c_ack_r <= ack_dr_ri(i+2); opcode_ri_dr(i+2) <= action_if(i).c_opcode_r; instance_state_ri_dr(i+2) <= action_if(i).c_instance_state_r; view_state_ri_dr(i+2) <= action_if(i).c_view_state_r; sample_state_ri_dr(i+2) <= action_if(i).c_sample_state_r; instance_handle_ri_dr(i+2) <= action_if(i).c_instance_handle_r; max_samples_ri_dr(i+2) <= action_if(i).c_max_samples_r; get_data_ri_dr(i+2) <= action_if(i).c_get_data_r; action_if(i).c_done_r <= done_dr_ri(i+2); action_if(i).c_return_code_r <= return_code_dr_ri(i+2); action_if(i).c_valid_in_r <= valid_dr_ri(i+2); ready_ri_dr(i+2) <= action_if(i).c_ready_in_r; action_if(i).c_data_in_r <= data_dr_ri(i+2); action_if(i).c_last_word_in_r <= last_word_dr_ri(i+2); action_if(i).c_sample_info_r <= sample_info_dr_ri(i+2); action_if(i).c_sample_info_valid_r <= sample_info_valid_dr_ri(i+2); sample_info_ack_ri_dr(i+2) <= action_if(i).c_sample_info_ack_r; action_if(i).c_eoc_r <= eoc_dr_ri(i+2); action_if(i).c_status_r <= status_dr_ri(i+2); start_wi_dw(i+2) <= action_if(i).c_start_w; action_if(i).c_ack_w <= ack_dw_wi(i+2); opcode_wi_dw(i+2) <= action_if(i).c_opcode_w; action_if(i).c_instance_handle_out_w <= instance_handle_dw_wi(i+2); source_ts_wi_dw(i+2) <= action_if(i).c_source_ts_w; max_wait_wi_dw(i+2) <= action_if(i).c_max_wait_w; action_if(i).c_done_w <= done_dw_wi(i+2); action_if(i).c_return_code_w <= return_code_dw_wi(i+2); instance_handle_wi_dw(i+2) <= action_if(i).c_instance_handle_in_w; valid_wi_dw(i+2) <= action_if(i).c_valid_out_w; action_if(i).c_ready_out_w <= ready_dw_wi(i+2); data_wi_dw(i+2) <= action_if(i).c_data_out_w; last_word_wi_dw(i+2) <= action_if(i).c_last_word_out_w; action_if(i).c_valid_in_w <= valid_dw_wi(i+2); ready_wi_dw(i+2) <= action_if(i).c_ready_in_w; action_if(i).c_data_in_w <= data_dw_wi(i+2); action_if(i).c_last_word_in_w <= last_word_dw_wi(i+2); action_if(i).c_status_w <= status_dw_wi(i+2); -- end generate; ros_time_converter_inst : entity work.ros_time_converter(arch) port map ( clk => clk, reset => reset, time_in => time, time_out => ros_time ); -- ######GENERATED START###### Fibonacci_ros_action_server_inst : entity work.Fibonacci_ros_action_server(arch) generic map ( TIMEOUT_DURATION => ROS_DURATION_INFINITE, MAX_GOALS => 2, MAX_RESULT_REQUESTS => 1, ENABLE_FEEDBACK => '1' ) port map ( clk => clk, reset => reset, time => ros_time, g_start_r => action_if(0).g_start_r, g_ack_r => action_if(0).g_ack_r, g_opcode_r => action_if(0).g_opcode_r, g_instance_state_r => action_if(0).g_instance_state_r, g_view_state_r => action_if(0).g_view_state_r, g_sample_state_r => action_if(0).g_sample_state_r, g_instance_handle_r => action_if(0).g_instance_handle_r, g_max_samples_r => action_if(0).g_max_samples_r, g_get_data_r => action_if(0).g_get_data_r, g_done_r => action_if(0).g_done_r, g_return_code_r => action_if(0).g_return_code_r, g_valid_in_r => action_if(0).g_valid_in_r, g_ready_in_r => action_if(0).g_ready_in_r, g_data_in_r => action_if(0).g_data_in_r, g_last_word_in_r => action_if(0).g_last_word_in_r, g_sample_info_r => action_if(0).g_sample_info_r, g_sample_info_valid_r => action_if(0).g_sample_info_valid_r, g_sample_info_ack_r => action_if(0).g_sample_info_ack_r, g_eoc_r => action_if(0).g_eoc_r, g_status_r => action_if(0).g_status_r, g_start_w => action_if(0).g_start_w, g_ack_w => action_if(0).g_ack_w, g_opcode_w => action_if(0).g_opcode_w, g_instance_handle_out_w => action_if(0).g_instance_handle_out_w, g_source_ts_w => action_if(0).g_source_ts_w, g_max_wait_w => action_if(0).g_max_wait_w, g_done_w => action_if(0).g_done_w, g_return_code_w => action_if(0).g_return_code_w, g_instance_handle_in_w => action_if(0).g_instance_handle_in_w, g_valid_out_w => action_if(0).g_valid_out_w, g_ready_out_w => action_if(0).g_ready_out_w, g_data_out_w => action_if(0).g_data_out_w, g_last_word_out_w => action_if(0).g_last_word_out_w, g_valid_in_w => action_if(0).g_valid_in_w, g_ready_in_w => action_if(0).g_ready_in_w, g_data_in_w => action_if(0).g_data_in_w, g_last_word_in_w => action_if(0).g_last_word_in_w, g_status_w => action_if(0).g_status_w, r_start_r => action_if(0).r_start_r, r_ack_r => action_if(0).r_ack_r, r_opcode_r => action_if(0).r_opcode_r, r_instance_state_r => action_if(0).r_instance_state_r, r_view_state_r => action_if(0).r_view_state_r, r_sample_state_r => action_if(0).r_sample_state_r, r_instance_handle_r => action_if(0).r_instance_handle_r, r_max_samples_r => action_if(0).r_max_samples_r, r_get_data_r => action_if(0).r_get_data_r, r_done_r => action_if(0).r_done_r, r_return_code_r => action_if(0).r_return_code_r, r_valid_in_r => action_if(0).r_valid_in_r, r_ready_in_r => action_if(0).r_ready_in_r, r_data_in_r => action_if(0).r_data_in_r, r_last_word_in_r => action_if(0).r_last_word_in_r, r_sample_info_r => action_if(0).r_sample_info_r, r_sample_info_valid_r => action_if(0).r_sample_info_valid_r, r_sample_info_ack_r => action_if(0).r_sample_info_ack_r, r_eoc_r => action_if(0).r_eoc_r, r_status_r => action_if(0).r_status_r, r_start_w => action_if(0).r_start_w, r_ack_w => action_if(0).r_ack_w, r_opcode_w => action_if(0).r_opcode_w, r_instance_handle_out_w => action_if(0).r_instance_handle_out_w, r_source_ts_w => action_if(0).r_source_ts_w, r_max_wait_w => action_if(0).r_max_wait_w, r_done_w => action_if(0).r_done_w, r_return_code_w => action_if(0).r_return_code_w, r_instance_handle_in_w => action_if(0).r_instance_handle_in_w, r_valid_out_w => action_if(0).r_valid_out_w, r_ready_out_w => action_if(0).r_ready_out_w, r_data_out_w => action_if(0).r_data_out_w, r_last_word_out_w => action_if(0).r_last_word_out_w, r_valid_in_w => action_if(0).r_valid_in_w, r_ready_in_w => action_if(0).r_ready_in_w, r_data_in_w => action_if(0).r_data_in_w, r_last_word_in_w => action_if(0).r_last_word_in_w, r_status_w => action_if(0).r_status_w, c_start_r => action_if(0).c_start_r, c_ack_r => action_if(0).c_ack_r, c_opcode_r => action_if(0).c_opcode_r, c_instance_state_r => action_if(0).c_instance_state_r, c_view_state_r => action_if(0).c_view_state_r, c_sample_state_r => action_if(0).c_sample_state_r, c_instance_handle_r => action_if(0).c_instance_handle_r, c_max_samples_r => action_if(0).c_max_samples_r, c_get_data_r => action_if(0).c_get_data_r, c_done_r => action_if(0).c_done_r, c_return_code_r => action_if(0).c_return_code_r, c_valid_in_r => action_if(0).c_valid_in_r, c_ready_in_r => action_if(0).c_ready_in_r, c_data_in_r => action_if(0).c_data_in_r, c_last_word_in_r => action_if(0).c_last_word_in_r, c_sample_info_r => action_if(0).c_sample_info_r, c_sample_info_valid_r => action_if(0).c_sample_info_valid_r, c_sample_info_ack_r => action_if(0).c_sample_info_ack_r, c_eoc_r => action_if(0).c_eoc_r, c_status_r => action_if(0).c_status_r, c_start_w => action_if(0).c_start_w, c_ack_w => action_if(0).c_ack_w, c_opcode_w => action_if(0).c_opcode_w, c_instance_handle_out_w => action_if(0).c_instance_handle_out_w, c_source_ts_w => action_if(0).c_source_ts_w, c_max_wait_w => action_if(0).c_max_wait_w, c_done_w => action_if(0).c_done_w, c_return_code_w => action_if(0).c_return_code_w, c_instance_handle_in_w => action_if(0).c_instance_handle_in_w, c_valid_out_w => action_if(0).c_valid_out_w, c_ready_out_w => action_if(0).c_ready_out_w, c_data_out_w => action_if(0).c_data_out_w, c_last_word_out_w => action_if(0).c_last_word_out_w, c_valid_in_w => action_if(0).c_valid_in_w, c_ready_in_w => action_if(0).c_ready_in_w, c_data_in_w => action_if(0).c_data_in_w, c_last_word_in_w => action_if(0).c_last_word_in_w, c_status_w => action_if(0).c_status_w, f_start_dds => start_wi_dw(3), f_ack_dds => ack_dw_wi(3), f_opcode_dds => opcode_wi_dw(3), f_instance_handle_out_dds => instance_handle_dw_wi(3), f_source_ts_dds => source_ts_wi_dw(3), f_max_wait_dds => max_wait_wi_dw(3), f_done_dds => done_dw_wi(3), f_return_code_dds => return_code_dw_wi(3), f_instance_handle_in_dds => instance_handle_wi_dw(3), f_valid_out_dds => valid_wi_dw(3), f_ready_out_dds => ready_dw_wi(3), f_data_out_dds => data_wi_dw(3), f_last_word_out_dds => last_word_wi_dw(3), f_valid_in_dds => valid_dw_wi(3), f_ready_in_dds => ready_wi_dw(3), f_data_in_dds => data_dw_wi(3), f_last_word_in_dds => last_word_dw_wi(3), f_status_dds => status_dw_wi(3), s_start_dds => start_wi_dw(3+1), s_ack_dds => ack_dw_wi(3+1), s_opcode_dds => opcode_wi_dw(3+1), s_instance_handle_out_dds => instance_handle_dw_wi(3+1), s_source_ts_dds => source_ts_wi_dw(3+1), s_max_wait_dds => max_wait_wi_dw(3+1), s_done_dds => done_dw_wi(3+1), s_return_code_dds => return_code_dw_wi(3+1), s_instance_handle_in_dds => instance_handle_wi_dw(3+1), s_valid_out_dds => valid_wi_dw(3+1), s_ready_out_dds => ready_dw_wi(3+1), s_data_out_dds => data_wi_dw(3+1), s_last_word_out_dds => last_word_wi_dw(3+1), s_valid_in_dds => valid_dw_wi(3+1), s_ready_in_dds => ready_wi_dw(3+1), s_data_in_dds => data_dw_wi(3+1), s_last_word_in_dds => last_word_dw_wi(3+1), s_status_dds => status_dw_wi(3+1), start => start_s, opcode => opcode_s, ack => ack_s, done => done_s, return_code => return_code_s, goal_handle_in => goal_handle_in_s, goal_handle_out => goal_handle_out_s, goal_state_in => goal_state_in_s, goal_state_out => goal_state_out_s, goal_id => goal_id_s, goal_result_index => goal_result_index_s, goal_stamp => goal_stamp_s, new_goal_request => new_goal_request_s, new_goal_handle => new_goal_handle_s, new_goal_result_index => new_goal_result_index_s, new_goal_order => new_goal_order_s, new_goal_accepted => new_goal_accepted_s, new_goal_response => new_goal_response_s, cancel_request => cancel_request_s, cancel_request_handle => cancel_request_handle_s, cancel_accepted => cancel_accepted_s, cancel_response => cancel_response_s, result_addr => result_addr_s, result_ready => result_ready_s, result_ren => result_ren_s, result_wen => result_wen_s, result_valid => result_valid_s, result_ack => result_ack_s, result_seq_len => result_seq_len_s, result_seq_addr => result_seq_addr_s, result_seq_ready => result_seq_ready_s, result_seq_ren => result_seq_ren_s, result_seq_wen => result_seq_wen_s, result_seq_valid => result_seq_valid_s, result_seq_ack => result_seq_ack_s, result_seq_r => result_seq_r_s, result_seq_w => result_seq_w_s, feedback_seq_len => feedback_seq_len_s, feedback_seq_addr => feedback_seq_addr_s, feedback_seq_ready => feedback_seq_ready_s, feedback_seq_ren => feedback_seq_ren_s, feedback_seq_wen => feedback_seq_wen_s, feedback_seq_valid => feedback_seq_valid_s, feedback_seq_ack => feedback_seq_ack_s, feedback_seq_r => feedback_seq_r_s, feedback_seq_w => feedback_seq_w_s ); Fibonacci_inst : entity work.Fibonacci(arch) port map ( clk => clk, reset => reset, time => ros_time, start => start_s, opcode => opcode_s, ack => ack_s, done => done_s, return_code => return_code_s, goal_handle_in => goal_handle_in_s, goal_handle_out => goal_handle_out_s, goal_state_in => goal_state_in_s, goal_state_out => goal_state_out_s, goal_id => goal_id_s, goal_result_index => goal_result_index_s, goal_stamp => goal_stamp_s, new_goal_request => new_goal_request_s, new_goal_handle => new_goal_handle_s, new_goal_result_index => new_goal_result_index_s, new_goal_order => new_goal_order_s, new_goal_accepted => new_goal_accepted_s, new_goal_response => new_goal_response_s, cancel_request => cancel_request_s, cancel_request_handle => cancel_request_handle_s, cancel_accepted => cancel_accepted_s, cancel_response => cancel_response_s, result_addr => result_addr_s, result_ready => result_ready_s, result_ren => result_ren_s, result_wen => result_wen_s, result_valid => result_valid_s, result_ack => result_ack_s, result_seq_len => result_seq_len_s, result_seq_addr => result_seq_addr_s, result_seq_ready => result_seq_ready_s, result_seq_ren => result_seq_ren_s, result_seq_wen => result_seq_wen_s, result_seq_valid => result_seq_valid_s, result_seq_ack => result_seq_ack_s, result_seq_r => result_seq_r_s, result_seq_w => result_seq_w_s, feedback_seq_len => feedback_seq_len_s, feedback_seq_addr => feedback_seq_addr_s, feedback_seq_ready => feedback_seq_ready_s, feedback_seq_ren => feedback_seq_ren_s, feedback_seq_wen => feedback_seq_wen_s, feedback_seq_valid => feedback_seq_valid_s, feedback_seq_ack => feedback_seq_ack_s, feedback_seq_r => feedback_seq_r_s, feedback_seq_w => feedback_seq_w_s ); -- ######GENERATED END###### end architecture;