onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -divider SYSTEM
add wave -noupdate /l0_dds_writer_test1_aik/uut/clk
add wave -noupdate /l0_dds_writer_test1_aik/uut/reset
add wave -noupdate -radix unsigned /l0_dds_writer_test1_aik/uut/time
add wave -noupdate -divider {RTPS IN}
add wave -noupdate -group {RTPS IN} /l0_dds_writer_test1_aik/uut/start_rtps
add wave -noupdate -group {RTPS IN} -radix unsigned /l0_dds_writer_test1_aik/uut/seq_nr_rtps
add wave -noupdate -group {RTPS IN} /l0_dds_writer_test1_aik/uut/opcode_rtps
add wave -noupdate -group {RTPS IN} /l0_dds_writer_test1_aik/uut/ack_rtps
add wave -noupdate -group {RTPS IN} /l0_dds_writer_test1_aik/uut/done_rtps
add wave -noupdate -group {RTPS IN} /l0_dds_writer_test1_aik/uut/ret_rtps
add wave -noupdate -divider {RTPS OUT}
add wave -noupdate -group {RTPS OUT} -radix hexadecimal /l0_dds_writer_test1_aik/uut/cc_instance_handle
add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test1_aik/uut/cc_kind
add wave -noupdate -group {RTPS OUT} -radix unsigned /l0_dds_writer_test1_aik/uut/cc_source_timestamp
add wave -noupdate -group {RTPS OUT} -radix unsigned -childformat {{/l0_dds_writer_test1_aik/uut/cc_seq_nr(0) -radix unsigned -childformat {{/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(31) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(30) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(29) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(28) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(27) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(26) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(25) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(24) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(23) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(22) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(21) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(20) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(19) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(18) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(17) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(16) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(15) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(14) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(13) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(12) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(11) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(10) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(9) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(8) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(7) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(6) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(5) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(4) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(3) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(2) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(1) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(0) -radix unsigned}}} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(1) -radix unsigned}} -subitemconfig {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0) {-height 15 -radix unsigned -childformat {{/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(31) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(30) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(29) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(28) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(27) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(26) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(25) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(24) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(23) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(22) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(21) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(20) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(19) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(18) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(17) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(16) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(15) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(14) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(13) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(12) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(11) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(10) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(9) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(8) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(7) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(6) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(5) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(4) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(3) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(2) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(1) -radix unsigned} {/l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(0) -radix unsigned}}} /l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(31) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(30) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(29) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(28) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(27) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(26) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(25) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(24) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(23) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(22) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(21) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(20) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(19) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(18) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(17) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(16) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(15) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(14) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(13) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(12) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(11) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(10) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(9) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(8) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(7) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(6) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(5) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(4) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(3) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(2) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(1) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/cc_seq_nr(0)(0) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/cc_seq_nr(1) {-height 15 -radix unsigned}} /l0_dds_writer_test1_aik/uut/cc_seq_nr
add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test1_aik/uut/get_data_rtps
add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test1_aik/uut/ready_out_rtps
add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test1_aik/uut/valid_out_rtps
add wave -noupdate -group {RTPS OUT} -radix hexadecimal /l0_dds_writer_test1_aik/uut/data_out_rtps
add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test1_aik/uut/last_word_out_rtps
add wave -noupdate -divider {DDS IN}
add wave -noupdate -expand -group DDS /l0_dds_writer_test1_aik/uut/start_dds
add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_writer_test1_aik/uut/instance_handle_dds
add wave -noupdate -expand -group DDS -radix unsigned /l0_dds_writer_test1_aik/uut/source_ts_dds
add wave -noupdate -expand -group DDS /l0_dds_writer_test1_aik/uut/opcode_dds
add wave -noupdate -expand -group DDS /l0_dds_writer_test1_aik/uut/ack_dds
add wave -noupdate -expand -group DDS /l0_dds_writer_test1_aik/uut/done_dds
add wave -noupdate -expand -group DDS -radix unsigned /l0_dds_writer_test1_aik/uut/return_code_dds
add wave -noupdate -expand -group DDS /l0_dds_writer_test1_aik/uut/ready_in_dds
add wave -noupdate -expand -group DDS /l0_dds_writer_test1_aik/uut/valid_in_dds
add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_writer_test1_aik/uut/data_in_dds
add wave -noupdate -expand -group DDS /l0_dds_writer_test1_aik/uut/last_word_in_dds
add wave -noupdate -expand -group DDS /l0_dds_writer_test1_aik/uut/ready_out_dds
add wave -noupdate -expand -group DDS /l0_dds_writer_test1_aik/uut/valid_out_dds
add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_writer_test1_aik/uut/data_out_dds
add wave -noupdate -expand -group DDS /l0_dds_writer_test1_aik/uut/last_word_out_dds
add wave -noupdate -divider {MAIN FSM}
add wave -noupdate /l0_dds_writer_test1_aik/uut/stage
add wave -noupdate /l0_dds_writer_test1_aik/uut/stage_next
add wave -noupdate /l0_dds_writer_test1_aik/uut/cnt
add wave -noupdate -radix unsigned /l0_dds_writer_test1_aik/uut/global_seq_nr
add wave -noupdate -radix unsigned /l0_dds_writer_test1_aik/uut/global_sample_cnt
add wave -noupdate -radix unsigned /l0_dds_writer_test1_aik/uut/global_ack_cnt
add wave -noupdate -radix unsigned /l0_dds_writer_test1_aik/uut/stale_inst_cnt
add wave -noupdate /l0_dds_writer_test1_aik/uut/remove_oldest_inst_sample
add wave -noupdate /l0_dds_writer_test1_aik/uut/remove_oldest_sample
add wave -noupdate /l0_dds_writer_test1_aik/uut/remove_ack_sample
add wave -noupdate -divider MEMORY
add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test1_aik/uut/sample_abort_read
add wave -noupdate -group {SAMPLE MEM} -radix unsigned -childformat {{/l0_dds_writer_test1_aik/uut/sample_mem_ctrl_inst/addr(5) -radix unsigned} {/l0_dds_writer_test1_aik/uut/sample_mem_ctrl_inst/addr(4) -radix unsigned} {/l0_dds_writer_test1_aik/uut/sample_mem_ctrl_inst/addr(3) -radix unsigned} {/l0_dds_writer_test1_aik/uut/sample_mem_ctrl_inst/addr(2) -radix unsigned} {/l0_dds_writer_test1_aik/uut/sample_mem_ctrl_inst/addr(1) -radix unsigned} {/l0_dds_writer_test1_aik/uut/sample_mem_ctrl_inst/addr(0) -radix unsigned}} -subitemconfig {/l0_dds_writer_test1_aik/uut/sample_mem_ctrl_inst/addr(5) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/sample_mem_ctrl_inst/addr(4) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/sample_mem_ctrl_inst/addr(3) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/sample_mem_ctrl_inst/addr(2) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/sample_mem_ctrl_inst/addr(1) {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/sample_mem_ctrl_inst/addr(0) {-height 15 -radix unsigned}} /l0_dds_writer_test1_aik/uut/sample_mem_ctrl_inst/addr
add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test1_aik/uut/sample_mem_ctrl_inst/read
add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test1_aik/uut/sample_mem_ctrl_inst/ready_in
add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test1_aik/uut/sample_mem_ctrl_inst/valid_in
add wave -noupdate -group {SAMPLE MEM} -radix hexadecimal /l0_dds_writer_test1_aik/uut/sample_mem_ctrl_inst/data_in
add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test1_aik/uut/sample_mem_ctrl_inst/ready_out
add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test1_aik/uut/sample_mem_ctrl_inst/valid_out
add wave -noupdate -group {SAMPLE MEM} -radix hexadecimal /l0_dds_writer_test1_aik/uut/sample_mem_ctrl_inst/data_out
add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test1_aik/uut/payload_abort_read
add wave -noupdate -group {PAYLOAD MEM} -radix unsigned /l0_dds_writer_test1_aik/uut/payload_mem_ctrl_inst/addr
add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test1_aik/uut/payload_mem_ctrl_inst/read
add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test1_aik/uut/payload_mem_ctrl_inst/ready_in
add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test1_aik/uut/payload_mem_ctrl_inst/valid_in
add wave -noupdate -group {PAYLOAD MEM} -radix hexadecimal /l0_dds_writer_test1_aik/uut/payload_mem_ctrl_inst/data_in
add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test1_aik/uut/payload_mem_ctrl_inst/ready_out
add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test1_aik/uut/payload_mem_ctrl_inst/valid_out
add wave -noupdate -group {PAYLOAD MEM} -radix hexadecimal /l0_dds_writer_test1_aik/uut/payload_mem_ctrl_inst/data_out
add wave -noupdate /l0_dds_writer_test1_aik/uut/inst_op_start
add wave -noupdate /l0_dds_writer_test1_aik/uut/inst_opcode
add wave -noupdate /l0_dds_writer_test1_aik/uut/inst_op_done
add wave -noupdate /l0_dds_writer_test1_aik/uut/inst_stage
add wave -noupdate /l0_dds_writer_test1_aik/uut/inst_stage_next
add wave -noupdate /l0_dds_writer_test1_aik/uut/inst_cnt
add wave -noupdate -radix unsigned /l0_dds_writer_test1_aik/uut/inst_addr_base
add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test1_aik/uut/inst_abort_read
add wave -noupdate -group {INSTANCE MEM} -radix unsigned /l0_dds_writer_test1_aik/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/addr
add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test1_aik/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/read
add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test1_aik/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/ready_in
add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test1_aik/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/valid_in
add wave -noupdate -group {INSTANCE MEM} -radix hexadecimal /l0_dds_writer_test1_aik/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/data_in
add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test1_aik/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/ready_out
add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test1_aik/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/valid_out
add wave -noupdate -group {INSTANCE MEM} -radix hexadecimal /l0_dds_writer_test1_aik/uut/gen_instance_mem_ctrl_inst/instance_mem_ctrl_inst/data_out
add wave -noupdate -childformat {{/l0_dds_writer_test1_aik/uut/inst_data.key_hash -radix hexadecimal} {/l0_dds_writer_test1_aik/uut/inst_data.status_info -radix binary} {/l0_dds_writer_test1_aik/uut/inst_data.sample_cnt -radix unsigned} {/l0_dds_writer_test1_aik/uut/inst_data.ack_cnt -radix unsigned}} -expand -subitemconfig {/l0_dds_writer_test1_aik/uut/inst_data.key_hash {-height 15 -radix hexadecimal} /l0_dds_writer_test1_aik/uut/inst_data.status_info {-height 15 -radix binary} /l0_dds_writer_test1_aik/uut/inst_data.sample_cnt {-height 15 -radix unsigned} /l0_dds_writer_test1_aik/uut/inst_data.ack_cnt {-height 15 -radix unsigned}} /l0_dds_writer_test1_aik/uut/inst_data
add wave -noupdate -radix unsigned /l0_dds_writer_test1_aik/uut/inst_next_addr_base
add wave -noupdate -radix unsigned /l0_dds_writer_test1_aik/uut/inst_prev_addr_base
add wave -noupdate -divider {KEY HOLDER}
add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test1_aik/uut/start_kh
add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test1_aik/uut/opcode_kh
add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test1_aik/uut/ack_kh
add wave -noupdate -group {KEY HOLDER} -radix hexadecimal /l0_dds_writer_test1_aik/uut/data_in_kh
add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test1_aik/uut/valid_in_kh
add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test1_aik/uut/ready_in_kh
add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test1_aik/uut/last_word_in_kh
add wave -noupdate -group {KEY HOLDER} -radix hexadecimal /l0_dds_writer_test1_aik/uut/data_out_kh
add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test1_aik/uut/valid_out_kh
add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test1_aik/uut/ready_out_kh
add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test1_aik/uut/last_word_out_kh
add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test1_aik/uut/abort_kh
add wave -noupdate -divider POINTERS
add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test1_aik/uut/empty_sample_list_head
add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test1_aik/uut/empty_sample_list_tail
add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test1_aik/uut/empty_payload_list_head
add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test1_aik/uut/oldest_sample
add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test1_aik/uut/newest_sample
add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test1_aik/uut/inst_empty_head
add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test1_aik/uut/inst_occupied_head
add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test1_aik/uut/cur_sample
add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test1_aik/uut/prev_sample
add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test1_aik/uut/next_sample
add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test1_aik/uut/cur_payload
add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test1_aik/uut/next_payload
add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test1_aik/uut/cur_inst
add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test1_aik/uut/next_inst
add wave -noupdate -divider TESTBENCH
add wave -noupdate -group TESTBENCH /l0_dds_writer_test1_aik/stim_start
add wave -noupdate -group TESTBENCH /l0_dds_writer_test1_aik/stim_stage
add wave -noupdate -group TESTBENCH /l0_dds_writer_test1_aik/stim_cnt
add wave -noupdate -group TESTBENCH /l0_dds_writer_test1_aik/stim_done
add wave -noupdate -group TESTBENCH /l0_dds_writer_test1_aik/ref_start
add wave -noupdate -group TESTBENCH /l0_dds_writer_test1_aik/ref_stage
add wave -noupdate -group TESTBENCH /l0_dds_writer_test1_aik/ref_cnt
add wave -noupdate -group TESTBENCH /l0_dds_writer_test1_aik/ref_done
add wave -noupdate -group TESTBENCH /l0_dds_writer_test1_aik/kh_cnt
add wave -noupdate -group TESTBENCH /l0_dds_writer_test1_aik/kh_stage
add wave -noupdate -divider MISC
add wave -noupdate /l0_dds_writer_test1_aik/uut/cnt2
add wave -noupdate /l0_dds_writer_test1_aik/uut/cnt3
add wave -noupdate -radix unsigned /l0_dds_writer_test1_aik/uut/long_latch
add wave -noupdate /l0_dds_writer_test1_aik/uut/sample_status_info
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {106575000 ps} 0}
quietly wave cursor active 1
configure wave -namecolwidth 187
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {106074680 ps} {107075321 ps}