-- altera vhdl_input_version vhdl_2008
-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library altera_mf;
use altera_mf.altera_mf_components.all;
use work.math_pkg.all;

architecture altera of FWFT_FIFO is
    
    signal used_sig : std_logic_vector(log2c(FIFO_DEPTH)-1 downto 0);
    
begin
    
    -- XXX: Possible Worst Case Path
    free    <= FIFO_DEPTH - to_integer(unsigned(used_sig));
    
    scfifo_component : scfifo
	generic map (
		add_ram_output_register => "OFF",
		intended_device_family  => "Cyclone V",
		lpm_numwords            => FIFO_DEPTH,
		lpm_showahead           => "ON",
		lpm_type                => "scfifo",
		lpm_width               => DATA_WIDTH,
		lpm_widthu              => log2c(FIFO_DEPTH),
		overflow_checking       => "ON",
		underflow_checking      => "ON",
		use_eab                 => "ON"
	)
	port map (
		clock   => clk,
		sclr    => reset,
        data    => data_in,
		rdreq   => read,
		wrreq   => write,
		empty   => empty,
		full    => full,
		q       => data_out,
		usedw   => used_sig
	);
    
end architecture;