library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;

entity single_port_ram is
        generic (
            ADDR_WIDTH      : natural := 8;
            DATA_WIDTH      : natural := 12;
            MEMORY_DEPTH    : natural := 256
        );
        port (
            clk         : in std_logic;
            addr        : in std_logic_vector(ADDR_WIDTH-1 downto 0);
            wen         : in std_logic;
            ren         : in std_logic;
            wr_data     : in std_logic_vector(DATA_WIDTH-1 downto 0);
            rd_data     : out std_logic_vector(DATA_WIDTH-1 downto 0)
        );
end entity;

architecture arch of single_port_ram is
    
begin

    altsyncram_component : altsyncram
        generic map (
            clock_enable_input_a            => "BYPASS",
            clock_enable_output_a           => "BYPASS",
            intended_device_family          => "Cyclone V",
            lpm_hint                        => "ENABLE_RUNTIME_MOD=NO",
            lpm_type                        => "altsyncram",
            numwords_a                      => MEMORY_DEPTH,
            operation_mode                  => "SINGLE_PORT",
            outdata_aclr_a                  => "NONE",
            outdata_reg_a                   => "UNREGISTERED",
            power_up_uninitialized          => "FALSE",
            read_during_write_mode_port_a   => "DONT_CARE",
            widthad_a                       => ADDR_WIDTH,
            width_a                         => DATA_WIDTH,
            width_byteena_a                 => 1
        )
        port map (
            address_a   => addr,
            clock0      => clk,
            data_a      => wr_data,
            rden_a      => ren,
            wren_a      => wen,
            q_a         => rd_data
        );

end architecture;